Drivers for shared buses, especially the LIN bus

Abstract

A driver for a shared bus, such as a LIN bus, having a supply node (Vbat), a bus node (LIN), a transmit data input node (TX), and a receive data output node (RX), the driver comprising: pull-up circuitry between the supply node and the bus node; driver circuitry (100) having a control input connected to the transmit data input node; feedback circuitry (200) configured to provide feedback from the shared bus to the control input of the driver circuitry; copy circuitry (210) configured to derive at least one copy signal representative of a signal on the bus node; filter circuitry (220) configured to low-pass filter the at least one copy signal; and differentiation circuitry (230) configured to derive at least one derivative signal representative of a rate at which the signal on the bus node fluctuates.

Description

[Technical field]

[0001] The field of the invention relates to drivers for interposing between a shared bus, such as a Local Interconnect Network (LIN) bus, and a logical device. [Background technology]

[0002] The increase in communication in automotive applications has led to the introduction of the LIN protocol in addition to the CAN protocol. The LIN (Local Interconnect Network) protocol is an inexpensive low-speed communication. Typically, one master node and up to 16 slave nodes can be set up. The LIN protocol is specified in Parts 1 to 7 of the ISO standard ISO17987. In recent years, LIN is used not only in automotive applications but also in other industrial applications.

[0003] LIN is a single-wire low-speed communication device (transmitter / receiver). A LIN line can be connected to one master and 16 slaves, and therefore the exact load is unknown. As shown in Figure 1, LIN line 1 is connected to a diode D EXT and resistor R EXT In the recessive state, LIN line 1 is pulled to a high voltage value near Vbat. During communication, LIN line 1 will be pulled to ground GND, a state called the dominant state. Figure 2 shows the recessive state S R and dominant state S D Typically the circuitry is designed to avoid or limit interference and generation of unwanted RF signals (EMI and EMC). Fast switching between recessive and dominant states should be avoided. Typically the gradient between recessive and dominant states will be limited to around 5μs for example, as dictated by the LIN standard mentioned above.

[0004] A typical LIN node including a LIN driver 2 is shown in Figure 1. The LIN driver 2 has a receiver connected to a receive data output pin RX and a transmitter M1 connected to a transmit data input pin TX. The receive data output pin RX and the transmit data input pin TX may be connected to a controller (not shown). The LIN driver 2 and the controller may be integrated on the same chip or may be provided as separate components. External to the chip, a diode D EXT , and a resistor R of value, for example, 1k ohm EXT is provided to pull the LIN pin to the battery voltage Vbat when no communication is required (recessive state). In addition, an internal diode D1 and a resistor R1, for example with a value of 30 kOhms, are provided in the LIN driver 2. That way, current flow is avoided if the LIN, GND and VBAT pins are not wired correctly or if there is a loss of GND or BAT. A MOSFET M1 is used as a transmitter. Furthermore, the LIN driver 2 may be provided with a gradient control circuitry to obtain the required gradient during the transition.

[0005] When a high frequency signal (e.g. DPI (Direct power injection) IEC62132-4) test) is applied at the LIN pin, the signal can be coupled to the gate of MOSFET M1 through diode D2. The gate voltage will be pulled higher than the required gate voltage due to the RF signal. This higher gate voltage will affect the slope of the signal. To address this issue, some prior art solutions use feedback circuitry between the LIN pin and the gate of MOSFET M1. However, known feedback circuitry usually suffers from at least one of the following disadvantages: high energy consumption, high load on the LIN pin, and unstable feedback.

[0006] US2009 / 0243655 discloses a transceiver suitable for interfacing a logic device to a shared bus. The transceiver includes a transmit node that receives an input signal from the logic device and an I / O node that is coupled to the shared bus. The transceiver may be designed for use with a shared bus, single master, multiple slave architecture, such as a Local Interconnect Network (LIN). The driver current may result in a sinusoidal transition of the shared bus voltage. The transceiver includes a slew time module that is connected to the shared bus through a low pass filter element. The slew time module asserts a first 70% output when VLIN falls below about 70% of VBAT and asserts a second 40% output when VLIN falls below about 40% of VBAT. The implementation presented in US2009 / 0243655 is somewhat complex and requires a look-up table to obtain the appropriate bias signal.

[0007] WO2007135491 discloses a LIN network with a transmit driver for communicating on a single communication bus. A gradient control module is operatively coupled to a supply voltage and controls the transmit driver to selectively apply one of a first voltage transition mode including a constant DV / DT gradient transition or a second voltage transition mode including a fixed time transition based on the detected supply voltage when the voltage transition occurs. [Prior art documents] [Patent documents]

[0008] [Patent Document 1] US Patent Application Publication No. 2009 / 0243655 [Patent Document 2] WO2007135491 [Non-patent literature]

[0009] [Non-Patent Document 1] ISO17987 Parts 1 to 7 [Non-Patent Document 2] IEC62132-4 Summary of the Invention [Problem to be solved by the invention]

[0010] It is an object of embodiments of the present invention to provide a driver for a shared bus with improved feedback circuitry. [Means for solving the problem]

[0011] According to a first aspect of the present invention, there is provided a driver for insertion between a shared bus, such as a Local Interconnect Network (LIN) bus, and a logic device. The driver has a supply node for connection to a voltage source, a bus node for connection to the shared bus, a transmit data input node, and a receive data output node. The driver comprises pull-up circuitry between the supply node and the bus node, driver circuitry, and feedback circuitry. The driver circuitry is configured to draw current from the shared bus in response to a signal on the transmit data input node. The driver circuitry may also be referred to as transmitter circuitry, as it performs a transmit function of the driver. The driver circuitry has a control input connected to the transmit data input node. The feedback circuitry is configured to provide feedback from the shared bus to the control input of the driver circuitry. The feedback circuitry comprises copy circuitry, filter circuitry, and differentiation circuitry. The copy circuitry is configured to obtain at least one copy signal representative of a signal on the bus node. The filter circuitry is configured to low pass filter the at least one copy signal to obtain at least one filtered signal. The differentiation circuitry is configured to derive at least one differentiated signal representative of the speed, or rate, at which the signal on the bus node varies based on the at least one filtered signal.

[0012] Such feedback circuitry has the advantage that it can be implemented in a simple and robust manner, and that the energy consumption can be substantially independent of the bus load and can be low compared to prior art solutions. Indeed, the copy circuitry can realize a high impedance copy, thereby allowing the energy consumption to be limited. An embodiment of the invention can reduce both the energy consumption on the bus as well as the total energy consumption. By including filter circuitry, any high frequency disturbances can be filtered out from at least one copy signal. Using differentiation circuitry to provide feedback to the control input of the driver circuitry allows the control input to be precisely adjusted with limited energy consumption.

[0013] Preferably, the differentiation circuitry is configured to obtain at least one differentiated signal by performing a differentiation over time on the at least one filtered signal. Preferably, the output of the differentiation circuitry is a current or a voltage whose value depends on the slope of the signal on the bus node. Preferably, the differentiation circuitry is configured to obtain the at least one differentiated signal in a continuous manner during operation.

[0014] According to one exemplary embodiment, the pull-up circuitry comprises a diode and a resistor connected in series between the supply node and the bus node. In this way, the driver can be made compliant with the above-mentioned LIN standard. However, other pull-up circuitry configurations may be envisaged, for example, if the driver has to comply with another standard.

[0015] According to an exemplary embodiment, the driver further comprises mixing circuitry configured to mix the at least one differentiated signal with an input signal representative of the signal on the transmit data input node to provide a corrected signal to a control input of the driver circuitry. The input signal can be a positive or negative current depending on the level of the signal on the transmit data input node. Such mixing circuitry can be easily implemented using circuitry with limited energy consumption.

[0016] According to an exemplary embodiment, the feedback circuitry is connected to the receive data output node, such that at least one filtered signal or a signal representative of said at least one filtered signal is provided at the receive data output node. In other words, a part of the feedback circuitry can have a "double" function, on the one hand providing feedback to the control input of the driver circuitry and on the other hand converting a signal on the bus node into a signal suitable for use at the receive data output node. In that way the driver becomes more compact and the load and leakage on the shared bus is limited. The feedback circuitry can be connected to the receive data output node via the receiver circuitry.

[0017] According to an exemplary embodiment, the driver circuitry comprises a series connection of a low-voltage transistor, a high-voltage transistor, and a diode, the low-voltage transistor having a control input. This allows RF interference signals to be fed to the control input of the high-voltage transistor, thereby limiting the effect of such signals on the control input of the low-voltage transistor. The low-voltage transistor can be a low-voltage MOSFET and the high-voltage transistor can be a high-voltage MOSFET. The gate of the high-voltage MOSFET can be connected to a DC voltage source. This DC supply voltage is different from the supply voltage connected to the supply node of the driver. The DC supply voltage can be, for example, a DC supply voltage of 5V. The DC supply voltage can be generated based on the supply voltage connected to the supply node of the driver (this supply voltage will typically be, for example, a battery voltage between 5V and 20V). Alternatively, the DC supply voltage can originate from a separate power source. More preferably, the gate of the high-voltage MOSFET can be coupled to a push-pull circuit between the supply node and ground. In that way, additional direct power injection (DPI) shielding is obtained. Furthermore, the low-voltage transistor can be faster than the high-voltage transistor. Typically, the high voltage transistor will be able to withstand a higher voltage than the low voltage transistor. For example, the high voltage transistor will be able to support a voltage higher than 5V. The push-pull circuit may be set by a DC voltage source. Even more preferably, the control input of the high voltage transistor, i.e. the gate in case of the HV MOSFET, may be connected to a capacitor configured to bleed any additional RF power to ground. Optionally, a diode may be provided between the gate of the HV MOSFET and an intermediate node between the HV MOSFET and the LV MOSFET, the diode being connected to lead forward from the intermediate node to the gate. This will ensure a safe operating area of ​​the LV MOSFET during its off state.

[0018] According to an exemplary embodiment, the copy circuitry comprises at least one current mirror circuit. The copy circuitry may comprise a first current mirror including a first branch between the bus node and a supply node and a second branch generating a first mirror current, and a second current mirror including a first branch between the bus node and a ground node and a second branch generating a second mirror current, and the filter circuitry may then be configured to filter both the first mirror current and the second mirror current to obtain a first filtered signal and a second filtered signal. In this way, a good copy can be obtained regardless of the state of the bus node, and the impact on the shared bus will be limited, for example in terms of loading and leakage.

[0019] According to one exemplary embodiment, the copy circuitry is configured such that the leakage current flowing from the bus node to the copy circuitry is less than 20 microamps and / or the equivalent capacitance of the copy circuitry seen by the bus node is less than 250 pF, such that signals on the bus node are not significantly disturbed by the copy circuitry.

[0020] According to one exemplary embodiment, the copy circuitry is configured to sense a voltage on the bus node and effect the transition using a resistor between the supply node and the bus node and / or using a resistor between the bus node and ground to at least one copy current that constitutes at least one copy signal.

[0021] According to a second aspect of the invention, there is provided a driver for insertion between a shared bus, such as a Local Interconnect Network (LIN) bus, and a logic device. The driver has a supply node for connection to a voltage source, a bus node for connection to the shared bus, a transmit data input node, and a receive data output node. The driver comprises pull-up circuitry between the supply node and the bus node, driver circuitry, and feedback circuitry. The driver circuitry is configured to draw current from the shared bus in response to a signal on the transmit data input node. The driver circuitry has a control input connected to the transmit data input node. The feedback circuitry is configured to provide feedback from the shared bus to the control input of the driver circuitry. The feedback circuitry comprises filter circuitry configured to low pass filter at least one signal representative of a signal on the bus node to obtain at least one filtered signal. The feedback circuitry is connected to the receive data output node such that at least one filtered signal, or a signal representative of said at least one filtered signal, is provided at the receive data output node.

[0022] This aspect has the advantage that part of the feedback circuitry can have a "dual" function, on the one hand providing feedback to the control input of the driver circuitry, and on the other hand converting the signal on the bus node into a filtered signal suitable for use at the receive data output node. In that way the driver will be more compact and have a limited impact on the shared bus, for example in terms of loading and leakage.

[0023] Also according to the second aspect, preferably the driver further comprises differentiation circuitry configured to obtain at least one differentiated signal representative of the rate at which the signal on the bus node varies based on the filtered at least one signal. The driver may also comprise mixing circuitry configured to mix the at least one differentiated signal with the signal on the transmit data input node to provide a corrected signal to a control input of the driver circuitry. However, other circuitry may be used in the feedback loop as an alternative to the differentiation and / or mixing circuitry.

[0024] Also according to the second aspect, preferably the feedback circuitry further comprises copy circuitry configured to derive at least one copy signal representative of the signal on the bus node and connected to supply said at least one copy signal to an input of the filter circuitry.

[0025] The following preferred features apply to both the first and second aspects.

[0026] According to an exemplary embodiment, the filter circuitry comprises a low-pass filter and at least one of a pre-filter shaping circuit between the copy circuitry and the low-pass filter, and a post-filter shaping circuit between the low-pass filter and the differentiation circuitry. The received data output node may be connected to the output of the low-pass filter or the output of the post-filter shaping circuit. The pre-filter shaping may be current shaping or voltage shaping depending on whether the copy signal is a current signal or a voltage signal. Also, the post-filter shaping may be current shaping or voltage shaping depending on whether the signal to be post-shaped is a current signal or a voltage signal. Preferably, the pre-filter shaping circuit is configured to adapt the current range or voltage range of the at least one copy signal to a current range or voltage range optimized for the low-pass filter. Similarly, the post-filter shaping circuit may be configured to adapt the current range or voltage range of the at least one signal output by the low-pass filter to a current range or voltage range optimized for the differentiation circuitry.

[0027] The feedback circuitry may be connected to the receive data output node via the receiver circuitry. Optionally, further current or voltage shaping circuits may be provided between the receiver circuitry and the filter circuitry. In that way, the range of the signal output by the feedback circuitry may be further optimized for the receiver circuitry. In exemplary embodiments of the present invention, the receiver circuitry may comprise any one or more of the following: an inverter circuit, an operational amplifier circuit, a Schmitt trigger circuit.

[0028] According to an exemplary embodiment, the copy circuitry is configured to obtain at least one copied current signal representative of the signal on the bus node, and the feedback circuitry comprises a current-to-voltage converter configured to convert the at least one copied current signal into at least one voltage signal, the current-to-voltage converter being disposed between the filter circuitry and the differentiation circuitry or between the copy circuitry and the filter circuitry.

[0029] According to an exemplary embodiment, the differentiation circuitry comprises a first differentiation circuitry configured to obtain a first differentiation signal representative of a rising slope of the signal on the bus node based on the at least one filtered signal, and a second differentiation circuitry configured to obtain a second differentiation signal representative of a falling slope of the signal on the bus node based on the at least one filtered signal, such that an accurate feedback mechanism is realized for both the rising and falling slopes.

[0030] According to one exemplary embodiment, the feedback circuitry is implemented in MOS technology.

[0031] According to yet another aspect, a local interconnect network is provided comprising a shared bus and a plurality of drivers, each driver comprising at least one driver according to any one of the above defined embodiments, each driver being connected to the shared bus by its bus node. One driver of the plurality of drivers may be configured to function as a master and the other driver or drivers may be configured to function as one or more slaves. It is noted that one or more drivers according to an embodiment of the present invention may be combined with one or more other drivers, e.g. state-of-the-art drivers. For example, only the master driver may be a driver according to an embodiment of the present invention, or only one or more slave drivers may be according to an embodiment of the present invention.

[0032] The above and other advantages of the features and objects of the present invention will become more apparent and the invention will be better understood from the following detailed description, when read in conjunction with the accompanying drawings, in which the accompanying drawings are used to illustrate presently preferred, non-limiting exemplary embodiments of the device of the present invention. [Brief description of the drawings]

[0033] [Figure 1] FIG. 1 is a circuit diagram of a LIN driver according to the prior art. [Diagram 2] 1 is a schematic time graph showing the voltage on the LIN node (VLIN) and the voltage on the gate of transistor M1 (Vgate, also referred to as Vc in the following description) as a function of time. [Figure 3A] FIG. 2 is a circuit diagram of an exemplary embodiment of a driver according to the present invention. [Figure 3B] FIG. 4 is a circuit diagram of another exemplary embodiment of a driver according to the present invention. [Figure 4] FIG. 2 is a block diagram of an exemplary embodiment of feedback circuitry for a driver. [Diagram 5] FIG. 2 is a block diagram of an exemplary embodiment of feedback circuitry for a driver. [Figure 6] FIG. 2 is a block diagram of an exemplary embodiment of feedback circuitry for a driver. [Figure 7] FIG. 2 is a block diagram of an exemplary embodiment of feedback circuitry for a driver. [Figure 8] FIG. 2 is a block diagram of an exemplary embodiment of feedback circuitry for a driver. [Figure 9] FIG. 2 is a block diagram of an exemplary embodiment of feedback circuitry for a driver. [Figure 10] FIG. 2 is a block diagram of an exemplary embodiment of feedback circuitry for a driver. [Figure 11] FIG. 2 is a block diagram of an exemplary embodiment of feedback circuitry for a driver. [Figure 12] FIG. 2 is a block diagram of an exemplary embodiment of feedback circuitry for a driver. [Figure 13A] FIG. 2 is a circuit diagram of an exemplary embodiment of copy circuitry. [Figure 13B] FIG. 2 is a circuit diagram of an exemplary embodiment of copy circuitry. [Figure 13C] FIG. 2 is a circuit diagram of an exemplary embodiment of copy circuitry. [Figure 14A] FIG. 2 is a circuit diagram of an exemplary embodiment of a filter circuit configuration. [Figure 14B] FIG. 2 is a circuit diagram of an exemplary embodiment of a filter circuit configuration. [Figure 15] FIG. 2 is a circuit diagram of an exemplary embodiment of a differentiation circuit configuration. [Figure 16A] FIG. 2 is a circuit diagram of an exemplary embodiment of mixing circuitry and gate bias circuitry. [Figure 16B] FIG. 2 is a circuit diagram of an exemplary embodiment of mixing circuitry and gate bias circuitry. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0034] FIG. 3A shows a circuit diagram providing a high level overview of one exemplary embodiment of a driver 2, typically a LIN driver, also called a LIN transceiver.

[0035] The driver 2 is inserted between a shared bus 1, such as a Local Interconnect Network (LIN) bus, and a logic device (not shown). The driver 2 has a supply node Vbat for connecting to a voltage source, a bus node LIN for connecting to the shared bus, a transmit data input node TX, and a receive data output node RX. The driver 2 includes a pull-up circuit arrangement including a diode D1 and a resistor R1 connected in series between the supply node Vbat and the bus node LIN. The series resistor R1 may have a value between 10 kOhms and 100 kOhms, for example, approximately 30 kOhms. The diode D1 and resistor R1 may be as specified in the LIN specification / standard.

[0036] The driver 2 further comprises a driver circuitry 100 and a feedback circuitry 200. The driver circuitry 100 is configured to draw current from the shared bus 1 in response to a signal on a transmit data input node TX. The driver circuitry 100 has a control input Vc (in FIG. 2 , V gate The feedback circuitry 200 is configured to provide feedback from the shared bus LIN to a control input Vc of the driver circuitry 100.

[0037] The driver circuitry may include an LV NMOS device M11 including an HV NMOS device M12 and a diode D2 in series, and an HV gate bias circuit 110 connected to the gate of the HV NMOS device M12. The LV NMOS device M11 pulls the bus node LIN towards ground, i.e., drives the driver 2 into a dominant state S D The HV NMOS device M12 is designed to supply a current to make the LV NMOS device M11 high (see also FIG. 2). The HV NMOS device M12 is used to block high voltages on the bus node LIN. The LV NMOS device M12 can be from a power domain of, for example, 1.8V, 2.5V, 3.3V or 5V. However, other power domains are possible. In a typical embodiment, the maximum voltage on the bus node LIN can go up to 40V, which is much higher than the maximum allowed voltage of the LV NMOS device M11, and therefore the HV NMOS device M12 will limit the voltage at the drain 101 of the LV NMOS device M11 to the voltage defined by the HV gate bias circuit 110. Normally, this will be the voltage for which the LV NMOS device M11 is designed. In a typical embodiment, the voltage on the bus node LIN may go below ground to -27V. An additional diode D2 in the driver circuitry 100 will block current flow of negative voltages.

[0038] The control input Vc of the driver circuitry 100, here the gate of the LV NMOS M11, is controlled by the LV gate bias circuit 500. The LV gate bias circuit 500 provides a positive or negative current to the gate Vc of the LV NMOS M11 based on the signal on the transmit data input node TX to charge or discharge the gate node. The current applied to the gate of the LV NMOS M11 is controlled and thus the output signal V on the bus node LIN. LIN will have a predefined slew rate. Preferably, the slew rate is limited to prevent disturbances on the shared bus 1.

[0039] During normal operation, the shared bus 1 may be disturbed by RF signals. These RF signals may be coupled to the gate Vc of the LV NMOS M11 through the drain-gate capacitance of the LV NMOS M11. This coupling may pull the gate Vc to a higher voltage than desired, resulting in the signal V LIN The slew rate of the output signal V on the shared bus 1 becomes shorter. A possible test to simulate and measure this effect is the DPI test (Direct Power Injection). The changes in the battery voltage Vbat, temperature and load on the shared bus 1 LIN This will also affect the shape of

[0040] During such a disturbance event, the output signal V LIN To correct for this, feedback circuitry 200 is provided. The feedback circuitry 200 is configured to LIN and applies a correction to the current provided by the LV gate bias 500. To that end, a mixing circuitry 300 is provided for mixing the input signal output by the LV gate bias 500 with the feedback current output by the feedback circuitry 200. The feedback circuitry 200 mixes the signal V LIN, filter it and perform a differentiation (in time) on the filtered signal. A current proportional to the differentiated signal is provided to the mixing circuitry 300 to adjust the gate voltage Vc. The feedback circuitry 200 may be implemented in MOS technology. More details on possible embodiments of the feedback circuitry 200 are given below with reference to Figures 4 to 12. The mixing circuitry 300 is configured to mix at least one differentiated signal with an input signal output by the LV gate bias 500 and representative of the signal on the transmit data input node TX and provide a corrected signal Vc to the control input of the driver circuitry 100. The input signal output by the LV gate bias 500 may be a positive or negative current depending on the level of the signal on the transmit data input node TX.

[0041] As shown in FIG. 3A, the driver 2 further comprises a receiver circuitry 400. The receiver circuitry 400 may comprise, for example, an inverter circuit, an operational amplifier circuit, a Schmitt trigger circuit, or a combination thereof. The receiver circuitry 400 is connected to a feedback circuitry 200. The feedback circuitry 200 is connected to a receive data output node RX, such that at least one filtered signal or a signal representative of said at least one filtered signal is provided at the receive data output node RX via the receiver circuitry 400. This prevents the signal on the bus node LIN from having to be filtered twice and also limits the load on the bus node LIN. However, in another embodiment shown in FIG. 3B, the receiver circuitry 400 may include a filter and is connected directly to the bus node LIN. The other components of the circuit of FIG. 3B are identical to those of FIG. 3A, and reference is made to the above and below description.

[0042] Optionally, discharge circuitry 600 and / or pre-charge circuitry 700 may be added. The pre-charge circuitry 700 can be useful in two ways. LIN is recessive state S R From dominant state S D When the control input Vc of the driver 2 becomes th The pre-charge circuitry 700 charges the battery from 0 V to a threshold voltage V th Second, the pre-charge circuitry 700 can provide additional current to transition to the dominant state S D , additional current can be sourced so that the LV NMOS transistor M11 is pulled completely open (see t2 in FIG. 2). Similarly, the discharge circuitry 600 also provides a D From recessive state S R When the current reaches t3 and t4 in Figure 2, the resistor R is able to supply extra current.

[0043] As shown in Figures 4-12, in one exemplary embodiment, feedback circuitry 200 includes copy circuitry 210 configured to derive at least one copy signal representative of the signal on the bus node, filter circuitry 220 configured to low pass filter the at least one copy signal, and derivative circuitry 230 configured to derive at least one derivative signal representative of the speed, i.e., rate, at which the signal on the bus node LIN varies based on the at least one filtered signal.

[0044] A first implementation of feedback circuitry 200 is depicted in Figure 4. The feedback circuitry 200 has an input 201 (see also Figures 3A, 3B) that is to be coupled to a shared bus 1, and an output 203 (see also Figures 3A, 3B) that is to be coupled to mixing circuitry 300. Additionally, the feedback circuitry 200 may have an output 204 that is to be coupled to receiver circuitry 400.

[0045] The copy circuitry 210 obtains a copy signal representative of the signal on the bus node LIN and outputs the bus signal V LIN , and is configured to make a robust copy of the signal LIN. Preferably, the copy circuitry 210 is configured to sense the voltage on the bus node LIN and bring the transition therein into the copy current constituting the copy signal. This can be done using a resistor between the supply node Vbat and the bus node LIN and / or using a resistor between the bus node LIN and the ground GND. Preferably, the current through the resistor is further copied using a current mirror. The copy current constituting the copy signal can therefore be the current output by the current mirror or, if no current mirror is present, the current through the resistor. More preferably, the copy circuitry 210 is configured such that the leakage current flowing from the bus node LIN to the copy circuitry 210 is less than 20 microamps and / or the equivalent capacitance of the copy circuitry 210 seen by the bus node LIN is less than 250 pF. The advantage of such a copy circuitry 210 is that the load on the bus 1 becomes limited and that the load of the filter circuitry 220 is known by design. If the copy circuitry were not present, the loading of the filter circuitry 220 would depend on the bus 1 which would be a variable loading depending on the amount and type of different slaves on the bus 1 .

[0046] The filter circuitry 220 is configured to low-pass filter the copy signal output by the copy circuitry 210. The filter circuitry 220 is configured to remove jammers such as RF components. The filtered signal is sent to the time differentiation circuitry 230 and may also be sent to the receiver circuitry 400. It is noted that the frequency range of the bus signals on the shared bus 1 is much smaller than the frequency range of the RF jammers, so that the low-pass filter can effectively filter out the RF jammers. For example, when the driver is connected to a LIN bus, the LIN frequency is typically between 10 kHz and 100 kHz, and the RF jammers tend to be towards 1 MHz or higher. The filter circuitry 220 may comprise a low-pass filter with a cutoff frequency between 100 kHz and 900 kHz, more preferably between 120 kHz and 300 kHz, for example around 150 kHz.

[0047] The differentiation circuitry 230 is configured to obtain a differentiation signal representing the rate at which the signal on the bus node LIN varies based on the filtered signal. The time differentiation circuitry 230 will take the time differentiation of the filtered signal, which will be indicative of the slope of the signal on the bus node LIN. The output 203 of the differentiation circuitry 230 is a current (or voltage) according to the slope of the signal on the bus node LIN. In the mixing circuitry 300 (see Fig. 3A, Fig. 3B), this current will be mixed with the current generated by the LV gate bias current 500. If the signal slope of the signal on the bus node LIN is too fast, the output 203 of the differentiation circuitry 230 will be higher and more current will be subtracted from the bias current generated by the LV gate bias circuitry 500. If the signal slope of the signal on the bus node LIN is too slow, the output 203 of the differentiation circuitry 230 will be lower and less current will be subtracted from the bias current generated by the LV gate bias circuitry 500.

[0048] A second implementation of the feedback circuitry 200 is depicted in Fig. 5. The filter circuitry 220 comprises a low-pass filter 222, a pre-filter current shaping circuit 221 between the copy circuitry 210 and the low-pass filter 222, and a post-filter current shaping circuit 223 between the low-pass filter 222 and the differentiation circuitry 230. The receiver circuitry 400 may be connected to the output of the low-pass filter 222 (as shown) or to the output of the post-filter current shaping circuit 223 (not shown). Optionally, an additional current shaping circuit (not shown) may be provided in the connection line between the output 204 and the receiver circuitry 400, which may be optimized for the receiver circuitry 400. It should be noted that although both the pre-filter current shaping circuit 221 and the post-filter current shaping circuit 223 are shown in Fig. 5, it is also possible to have only one of the two shaping circuits. The current shaping circuits 221, 223 are introduced to change the available current range to another more suitable range. For example, the current delivered after the copy circuitry 210 will have minimum and maximum values. These values ​​may not be the optimal value range for the filter 222, and therefore the current can be scaled to optimal minimum and maximum values ​​for optimal operation of the filter 222. Similarly, the current can be scaled after the filter 222 to obtain an optimal current range for the time differentiation circuitry 230.

[0049] 6-8 further illustrate possible implementations of feedback circuitry 200. FIG. 6 and 7, the copy circuitry 210 is configured to obtain a copied current signal representative of the signal on the bus node, and the feedback circuitry 200 includes a current-to-voltage converter 240 configured to convert the filtered copied current signal into a voltage signal. The current-to-voltage converter 240 is disposed between the filter circuitry 220 and the differentiation circuitry 230. 8, feedback circuitry 200 includes a current-to-voltage converter 240 configured to convert the copied current signal (before filtering) into a voltage signal, which is then low-pass filtered by filter circuitry 220. The current-to-voltage converter 240 is disposed between the copy circuitry 210 and the filter circuitry 220.

[0050] A further embodiment is shown in Fig. 9. Differentiation of the filtered signal can be performed by two differentiating circuits, one for the falling edge and one for the rising edge. In that way clipping of the filtered signal can be prevented. The differentiating circuitry 230 comprises a first differentiating circuitry 230a configured to obtain a first differentiating signal V1 representing the rising slope of the signal on the bus node based on the filtered signal, and a second differentiating circuitry 230b configured to obtain a second differentiating signal V2 representing the falling slope of the signal on the bus node based on the filtered signal.

[0051] In another embodiment shown in FIG. 10, the copy of the signal on the bus node LIN can be done in two copies. If only one copy is taken, clipping of the signal may occur when Vbat or GND is reached. To prevent this, two copied signals C1, C2 can be used, one signal will not have clipping when the voltage on the bus reaches GND and the other signal will not have clipping when Vbat is reached. After the copy circuitry 210, both signals can be merged again. The copy circuitry 210 can comprise a first copy circuit between the bus node LIN and the supply node Vbat, generating a first copy signal C1, and a second copy circuit between the bus node LIN and the ground node GND, generating a second copy signal C2. The filter circuitry 220 is then configured to filter both the first copy signal C1 and the second copy signal C2.

[0052] FIG. 11 shows a further embodiment which combines features of the embodiments of FIGS.

[0053] Figure 12 shows yet another embodiment combining features of the embodiments of Figures 9 and 10, but here again the filter circuitry 220 and the current / voltage converter 240 are split in two branches and two copied signals C1, C2 are fed to respective branches 221a, 222a, 223a and 221b, 222b, 223b to obtain respective filtered signals F1, F2, which are fed to respective current / voltage converters 240a, 240b to obtain respective voltage signals T1, T2, which are fed to respective first and second differentiation circuitry 230a, 230b.

[0054] 13A-13C show different embodiments of copy circuitry 210. FIG. In the embodiment of Fig. 13A, the copy circuit arrangement 210 comprises a first copy circuit 210a between the bus node LIN and the supply node Vbat for generating a first copy signal C1, and a second copy circuit 210b between the bus node LIN and the ground node GND for generating a second copy signal C2. The first copy circuit 210a comprises a first current mirror 215a including a first branch 216a between the bus node LIN and the supply node Vbat and a second branch 217a for generating a first mirror current C1 at the first output Vl,u. The first branch 216a further comprises a resistor 218a and a diode 219a. Similarly, the second copy circuit 210b comprises a second current mirror 215b including a first branch 216b between the bus node LIN and the ground node GND and a second branch 217b for generating a second mirror current C2. The first branch 216b further comprises a resistor 218b and a diode 219b. The first copy circuit 210a between the bus node and the supply node Vbat will be able to copy voltages below Vbat-Vth, where Vth is the sum of the threshold voltage of the transistor of the current mirror 215a and the forward voltage of the diode 219a. The second copy circuit 210b between the supply node Vbat and the ground node GND will be able to copy voltages above Vth, where Vth is the sum of the threshold voltage of the transistor of the current mirror 215b and the forward voltage of the diode 219b. By having both the first copy circuit 210a and the second copy circuit 210b, all voltage levels can be copied. In the embodiment of Fig. 13B, the copy circuitry 210 comprises a current mirror 215 including a first branch 216 between the bus node LIN and the supply node Vbat, and a second branch 217 generating a mirrored current C at the output Vl,u. The first branch 216 further comprises a resistor 218 and a diode 219. An additional branch 213 is provided to conduct a current from the bus node LIN to ground GND when the bus node LIN is high, the additional branch 213 being connected between ground GND and an intermediate node between the resistor 218 and the diode 219. The additional branch 213 comprises a current source 212 and optionally a further resistor 218' and a diode 219'. By providing the additional branch 213, the voltage range that can be copied is not limited by Vbat-Vth. In the embodiment of FIG. 13C, the copy circuitry 210 comprises a first copy circuit 210a between the bus node LIN and the supply node Vbat for generating a first copy signal C1, and a second copy circuit 210b between the bus node LIN and the ground node GND for generating a second copy signal C2. The first copy circuit 210a comprises a first dual current mirror 215a, 215a' including a first branch 216a between the bus node LIN and the supply node Vbat and a second branch 217a for generating a first mirror current C1 at the first output Vl,u. The first branch 216a further comprises a resistor 218a. Similarly, the second copy circuit 210b comprises a second dual current mirror 215b, 215b' including a first branch 216b between the bus node LIN and the ground node GND and a second branch 217b for generating a second mirror current C2. The first branch 216b further comprises a resistor 218b.The accuracy of the copy circuitry 210 may be further improved by providing a "double" current mirror. The embodiment of Figures 13A to 13C makes it possible to obtain a good copy (either one copy signal C or two copy signals C1, C2) regardless of the state of the bus node LIN, with limited impact on the shared bus, e.g. in terms of loading and leakage.

[0055] 14A and 14B show possible embodiments of filter circuitry 220. FIG. In the embodiment of FIG. 14A, the filter circuitry 220 comprises a first current mirror 225a including a first branch 226 between an input pin receiving a copy signal C (optionally this may be a shaped copy signal C) and ground GND, and a second branch which is part of a common branch 227 which also includes a first branch of a second current mirror 225b. The common branch 227 extends between ground GND and a DC supply voltage Vcc. This DC supply voltage Vcc is different from a supply voltage Vbat connected to a supply node of the driver. The DC supply voltage Vcc may be, for example, a DC supply voltage of 5V. The DC supply voltage Vcc may be generated based on a supply voltage Vbat (typically a battery voltage between, for example, 5V and 20V). Alternatively, the DC supply voltage Vcc may originate from a separate power source. The ability to use such a DC supply voltage Vcc is also one of the advantages resulting from the use of the copy circuitry 210; in fact, by using the copy circuitry 210, further circuitry (i.e., the filter circuitry 220, the differentiation circuitry 230, and the mixing circuitry 300) can be made in the LV domain, resulting in less noise and allowing the use of LV transistors. The second current mirror 225b includes a second branch 228 extending between the DC supply voltage Vcc and the output pin "FILTER" and generates a filter output signal F in said second branch 228. The first branch 216 of the first current mirror 225a is connected in parallel with the capacitor 221a. The first branch of the second current mirror 225b is connected in parallel with the capacitor 221b. Mainly, the filtering is determined on the one hand by the parallel connection of the equivalent resistance of the current mirror 225a and the capacitor 221a, and on the other hand by the parallel connection of the equivalent resistance of the current mirror 225b and the capacitor 221b. The values ​​of the capacitors 221a, 221b may be selected to obtain appropriate filtering. The embodiment of FIG. 14B is similar to the embodiment of FIG. 14A, except that the current mirror is implemented as a dual current mirror 225a, 225a' and 225b, 225b'.

[0056] 15 is a circuit diagram of an exemplary embodiment of the current / voltage circuitry 240 and the differentiation circuitry 230. The differentiation circuitry 230 comprises a first differentiation circuit 230a between an output node 247 of the current / voltage circuitry 240 and a first output node der+ that generates a first differentiation signal V1, and a second differentiation circuit 230b between the output node 247 and a second output node der- that generates a second differentiation signal V2. The first differentiation circuit 230a comprises a first current mirror 225a including a first branch 236a and a second branch 237a where the first differentiation signal V1 is generated. The first differentiation circuit 230a comprises a capacitor 231a connected between the output node 247 and the first branch 236a, and a current source 232a connected to a DC supply voltage Vcc to generate a DC current in the first branch 236a. This DC current varies depending on the signal on node 247 passing through capacitor 231a. Similarly, second differentiator 230b comprises a first current mirror 225b including a first branch 236b and a second branch 237b in which a second differentiated signal V2 is generated. Second differentiator 230b comprises a capacitor 231b connected between output node 247 and first branch 236b, and a current source 232b connected to ground GND to generate a DC current in first branch 236b. This DC current varies depending on the signal on node 247 passing through capacitor 231b.

[0057] 16A and 16B are circuit diagrams of various exemplary embodiments of the mixing circuitry 300 and the gate bias circuitry 500. The mixing circuitry 300 comprises a pull-up circuit 300a including a current mirror 320a, and a pull-down circuit 300b including a current mirror 320b. Similarly, the gate bias circuitry 500 comprises a pull-up circuit 500a including a current mirror 520a, and a pull-down circuit 500b including a current mirror 520b. The mixing circuitry 300 receives a signal "not TX" to activate either the pull-up circuit 300a or the pull-down circuit 300b. The gate bias circuitry 500 receives a signal "TX" to activate either the pull-up circuit 500a or the pull-down circuit 500b. The input voltages at TX and "non-TX" can be high or low, enabling the pull-up circuit 300a, 500a or the pull-down circuit 300b, 500b. The pull-up circuit 300a, 500a will enable or disable the current mirror 320a, 520a. The pull-down circuit 300b, 500b will enable or disable the current mirror 320b, 520b. The current mirror 320a receives the first differentiated signal V1 output by the differentiation circuitry 230 (see also FIG. 15). The current mirror 320b receives the second differentiated signal V2 output by the differentiation circuitry 230 (see also FIG. 15). The current mirror 520a receives the first DC current 530a and the current mirror 520b receives the second DC current 530b. When "TX" is high, the bias current Ibias generated by the gate bias circuitry 500 will be positive, which causes the bias current to flow towards the gate. The mixing circuitry 300 will generate a current Icor opposite to the bias current Ibias, resulting in a corrected current going towards the gate with a value |Ibias|-|Icor|. The pull-down circuit 500b will disable the current mirror 520b and the current mirror 520a will be enabled, resulting in a current flow towards the gate. The pull-up circuit 300a will disable the current mirror 320a ("not TX" goes low) and enable the current mirror 520b, resulting in a current flow from the gate towards ground. If the signal slope of the signal on the bus node LIN is too fast, more current |Icor| will be subtracted from the bias current |Ibias|. If the signal slope of the signal on the bus node LIN is too slow, less current |Icor| will be subtracted from the bias current |Ibias|. When "TX" is low, the bias current Ibias generated by the gate bias circuitry 500 becomes negative, which causes the bias current to flow from the gate into the gate bias circuitry 500. The mixing circuitry 300 generates a current Icor opposite to the bias current Ibias, resulting in a corrected current going out of the gate with a value |Ibias|-|Icor|. The pull-up circuit 500a will disable the current mirror 520a and the current mirror 520b will be enabled, resulting in a current flow from the gate to ground. The pull-down circuit 300b will disable the current mirror 320a ("not TX" goes high) and enable the current mirror 520a, resulting in a current flow towards the gate. Again, if the signal slope of the signal on the bus node LIN is too fast, more current |Icor| will be subtracted from the bias current |Ibias|. If the signal slope of the signal on the bus node LIN is too slow, less current |Icor| will be subtracted from the bias current |Ibias|.

[0058] In the embodiment of Fig. 16B, the mixing circuitry 300 further comprises an interrupt transistor 310a in series with the pull-up circuit 300a and an interrupt transistor 310b in series with the pull-down circuit 300b. Similarly, the gate bias circuitry 500 further comprises an interrupt transistor 510a in series with the pull-up circuit 500a and an interrupt transistor 510b in series with the pull-down circuit 500b. The interrupt transistors 310a, 310b, 510a, 510b allow the current paths to be switched off when the respective branches are not in use, thereby further reducing any leakage current.

[0059] Another exemplary embodiment relates to a local interconnect network comprising a shared bus and a plurality of drivers, one or more of which may be implemented as described above with reference to the figures, each driver being connected to the shared bus by its bus node, one driver of the plurality of drivers may be configured to function as a master and the other one or more drivers may be configured to function as one or more slaves.

[0060] The current mirrors shown in this application may be replaced with alternative implementations (e.g., the single current mirror may be replaced with a double / stacked current mirror; see, for example, the current mirrors used in Figures 13A and 13C).

[0061] Furthermore, those skilled in the art will appreciate that the bulk of the MOS transistors used in this application may be coupled to the source of the transistor or alternatively to a power supply (GND, VSS, substrate for NMOS transistors, VDD for PMOS transistors).

[0062] While the principles of the present invention have been presented above with reference to specific embodiments, it is to be understood that this description is made by way of example only and not as a limitation on the scope of protection determined by the appended claims. [Explanation of symbols]

[0063] 1 LIN line, shared bus 2 LIN driver, driver 100 Driver circuit configuration 101 Drain 110 HV Gate Bias Circuit 200 Feedback circuit configuration 201 Input 203, 204 Output 210 Copy circuit configuration 210a First copy circuit 210b Second copy circuit 212 Current source 213 Additional Branches 215 Current Mirror 215a, 215a', 225a First current mirror 215b, 215b', 225b Second current mirror 216, 216a, 216b, 226 First branch 217, 217a, 217b, 228 Second branch 218, 218', 218a, 218b, R1, R EXT resistor 219, 219', 219a, D1, D2, D EXT diode 220 Filter circuit configuration 221 Pre-filter current shaping circuit 221a, 222a, 223a, 221b, 222b, 223b, 236a, 237a Branch 221a, 221b, 231a capacitors 222 Low-pass filter 223 Post-filter current shaping circuit 225a, 225a', 225b, 225b' Dual current mirror 227 Common Branch 230 Differential Circuit Configuration 230a first differentiation circuit configuration, first differentiation circuit 230b second differentiation circuit configuration, second differentiation circuit 232a, 232b current source 240 Current / Voltage Converter 240a, 240b Current / Voltage Converter 247 Output Nodes 300 Mixing circuit configuration 300a, 500a pull-up circuit 300b, 500b pull-down circuit 310a, 310b, 510a, 510b Interrupt transistors 320a, 320b, 520a Current mirror 400 Receiver circuit configuration 500 LV Gate Bias Circuit 530a First DC current 530b Second DC Current 600 Discharge circuit configuration 700 Pre-charge Circuit Configuration der+ first output node der- second output node C Mirror current, copy signal C1, C2 copied signals F1, F2 Filtered signal GND grounding M12 HV NMOS Device M11 LV NMOS Device, LV NMOS Transistor LIN Bus Node RX Received Data Output Pin, Received Data Output Node S R Recessive State S D Dominant state TX Transmit data input pin, transmit data input node T1, T2 voltage signal V1 First differential signal V2 Second derivative signal Vbat Battery, Supply Node, Battery Voltage, Supply Voltage Vc, V gate Control Input, Gate, Gate Voltage Vcc DC supply voltage V LIN Output signals, bus signals Vl,u 1st output

Claims

1. 1. A driver for insertion between a shared bus, such as a Local Interconnect Network (LIN) bus, and a logic device, the driver having a supply node (Vbat) for connection to a voltage source, a bus node (LIN) for connection to the shared bus, a transmit data input node (TX), and a receive data output node (RX), the driver comprising: - pull-up circuitry between said supply node and said bus node; - a driver circuitry (100) configured to draw current from the shared bus in response to a signal on the transmit data input node, the driver circuitry (100) having a control input (Vc) connected to the transmit data input node; - feedback circuitry (200) configured to provide feedback from the shared bus to the control input (Vc) of the driver circuitry; Equipped with The feedback circuit configuration: - copy circuitry (210) configured to obtain at least one copy signal representative of a signal on said bus node; - a filter circuitry (220) configured to low-pass filter the at least one copy signal to obtain at least one filtered signal; - differentiation circuitry (230) configured to obtain at least one differentiated signal representative of the rate at which the signal on the bus node varies based on the at least one filtered signal; A driver comprising:

2. 2. The driver of claim 1, wherein the pull-up circuitry comprises a diode (D1) and a resistor (R1) connected in series.

3. 3. The driver of claim 1 or 2, further comprising a mixing circuitry (300) configured to mix the at least one differentiated signal with an input signal representative of a signal on the transmit data input node (TX) to provide a corrected signal to the control input (Vc) of the driver circuitry.

4. 4. The driver of claim 3, further comprising a gate bias circuitry (500) configured to generate the input signal based on the signal on the transmit data input node (TX), the gate bias circuitry (500) configured to generate the input signal as a positive or negative current depending on the level of the signal on the transmit data input node (TX).

5. 5. The driver of claim 1, wherein the feedback circuitry is connected to the receive data output node (RX) such that the at least one filtered signal, or a signal representative of the at least one filtered signal, is provided at the receive data output node (RX).

6. 6. The driver of claim 1, wherein the driver circuitry (100) comprises a series connection of a low voltage transistor (M11), a high voltage transistor (M12) and a diode (D2), the low voltage transistor having the control input.

7. 7. The driver of claim 1, wherein the copy circuitry comprises at least one current mirror circuit (215a, 215b).

8. 8. The driver of claim 1, wherein the copy circuitry (210) comprises a first current mirror (215a) including a first branch (216a) between the bus node and the supply node and a second branch (217a) for generating a first mirror current, and a second current mirror (215b) including a first branch (216b) between the bus node and a ground node and a second branch (217b) for generating a second mirror current, and the filter circuitry is configured to filter both the first mirror current and the second mirror current.

9. 9. The driver of claim 1, wherein the copy circuitry (210) is configured such that leakage current from the bus node to the copy circuitry is less than 20 microamps and / or the equivalent capacitance of the copy circuitry seen by the bus node is less than 250 pF.

10. 10. A driver according to any one of claims 1 to 9, wherein the differentiation circuitry is configured to obtain the at least one differentiated signal by performing a differentiation with respect to time on the at least one filtered signal, preferably whereby an output of the differentiation circuitry is a current or a voltage whose value depends on a slope of the signal on the bus node.

11. 1. A driver for insertion between a shared bus, such as a Local Interconnect Network (LIN) bus, and a logic device, the driver having a supply node (Vbat) for connection to a voltage source, a bus node (LIN) for connection to the shared bus, a transmit data input node (TX), and a receive data output node (RX), the driver comprising: - pull-up circuitry between said supply node and said bus node; - a driver circuitry (100) configured to draw current from the shared bus in response to a signal on the transmit data input node, the driver circuitry (100) having a control input (Vc) connected to the transmit data input node; - feedback circuitry (200) configured to provide feedback from the shared bus to the control input (Vc) of the driver circuitry; Equipped with the feedback circuitry comprises copy circuitry (210) configured to obtain at least one copy signal representative of a signal on the bus node, and filter circuitry (220) configured to low-pass filter the at least one copy signal to obtain at least one filtered signal; the feedback circuitry is connected to the receive data output node (RX) such that the at least one filtered signal, or a signal representative of the at least one filtered signal, is provided at the receive data output node (RX), and the filter circuitry (220) comprises a low pass filter (222) and a pre-filter shaping circuit (221) between the copy circuitry and the low pass filter; driver.

12. 12. The driver of claim 11, wherein the pull-up circuitry comprises a diode (D1) and a resistor (R1) connected in series.

13. 13. The driver of claim 11 or 12, further comprising a differentiation circuit arrangement (230) configured to derive at least one differentiated signal representative of a rate at which the signal on the bus node varies based on the at least one filtered signal.

14. 14. The driver of claim 13, further comprising mixing circuitry (300) configured to mix the at least one differentiated signal with a signal on the transmit data input node to provide a corrected signal to the control input of the driver circuitry.

15. 11. The driver of claim 1, wherein the filter circuitry (220) comprises a low pass filter (222) and at least one of a pre-filter shaping circuit (221) between the copy circuitry and the low pass filter, and a post-filter shaping circuit (223) between the low pass filter and the differentiation circuitry.

16. 16. The driver of claim 15, wherein the receive data output node is connected to an output of the low pass filter (222) or to an output of the post-filter shaping circuit (223).

17. 16. The driver of claim 1, wherein the copy circuitry is configured to obtain at least one copied current signal representative of a signal on the bus node, and the feedback circuitry comprises a current / voltage converter (240) configured to convert the at least one copied current signal into at least one voltage signal, the current / voltage converter being arranged between the filter circuitry (220) and the differentiation circuitry (230) or between the copy circuitry (210) and the filter circuitry (220).

18. 18. The driver according to claim 1, wherein the differentiation circuit arrangement (230) comprises a first differentiation circuit arrangement (230a) configured to obtain a first differentiation signal (V1) representative of a rising slope of the signal on the bus node based on the at least one filtered signal, and a second differentiation circuit arrangement (230b) configured to obtain a second differentiation signal (V2) representative of a falling slope of the signal on the bus node based on the at least one filtered signal.

19. 19. A driver as claimed in any one of the preceding claims, wherein the feedback circuitry is implemented in MOS technology.

20. 1. A driver for insertion between a shared bus, such as a Local Interconnect Network (LIN) bus, and a logic device, the driver having a supply node (Vbat) for connection to a voltage source, a bus node (LIN) for connection to the shared bus, a transmit data input node (TX), and a receive data output node (RX), the driver comprising: - pull-up circuitry between said supply node and said bus node; - a driver circuitry (100) configured to draw current from the shared bus in response to a signal on the transmit data input node, the driver circuitry (100) having a control input (Vc) connected to the transmit data input node; - feedback circuitry (200) configured to provide feedback from the shared bus to the control input (Vc) of the driver circuitry; Equipped with the driver circuitry comprises a series connection of a low voltage transistor, a high voltage transistor, and a diode, the low voltage transistor having the control input, the control input of the high voltage transistor being coupled to a push-pull circuit between the supply node and ground, the push-pull circuit being established by a DC voltage source; driver.

21. 21. The driver of claim 20, wherein the pull-up circuitry comprises a diode (D1) and a resistor (R1) connected in series.

22. 22. A driver as claimed in claim 20 or 21, wherein the low voltage transistor is a low voltage MOSFET and the high voltage transistor is a high voltage MOSFET.

23. 23. A driver as claimed in any one of claims 20 to 22, wherein a control input of the high voltage transistor is connected to a capacitor configured to bleed off an RF signal.

24. 24. A local interconnect network comprising a shared bus and a plurality of drivers comprising the driver of any one of claims 1 to 23, said drivers being connected to the shared bus by their bus nodes.

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