Semiconductor Device

Abstract

To provide a semiconductor device that reduces a parasitic capacitance.SOLUTION: A transistor 10 includes: a first insulation layer 110; a first oxide semiconductor layer 121 on the first insulation layer; a second oxide semiconductor layer 122 of the first oxide semiconductor layer; a source electrode layer 130 and a drain electrode layer 140 on the second oxide semiconductor layer; a first insulation layer and a second insulation layer 170 on the source electrode layer and the drain electrode layer; a third insulation layer 175 on the second insulation layer; a third oxide semiconductor layer 123 on the second oxide semiconductor layer; a gate insulation layer 150 on the third oxide semiconductor layer; and a gate electrode layer 160 on the gate insulation layer. The second insulation layer is an oxidation barrier layer, and includes a region contacted to each side surface of the first oxide semiconductor layer, the second oxide semiconductor layer, the source electrode layer, and the drain electrode layer. The third oxide semiconductor layer includes a region contacted to each surface of the second oxide semiconductor layer, the source electrode layer, the drain electrode layer, the second insulation layer, and the third insulation layer.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to an article, a method, or a manufacturing method. , manufacture, or composition of matter. The present invention relates to, for example, a semiconductor device, a display device, a light-emitting device, a power storage device, an imaging device, In particular, one embodiment of the present invention relates to a semiconductor device or a driving method thereof. or a method for producing the same.

[0002] In this specification and the like, a semiconductor device is a device that can function by utilizing semiconductor characteristics. A transistor and a semiconductor circuit are one embodiment of a semiconductor device. A display device or an electronic device may include a semiconductor device. [Background technology]

[0003] The technology of constructing transistors using semiconductor films formed on substrates with insulating surfaces is attracting attention. The transistor is expected to be used in devices such as integrated circuits (ICs) and image display devices (display devices). Silicon is widely used as a semiconductor thin film that can be applied to transistors. Silicon-based semiconductor materials are widely known, but oxide semiconductors are also attracting attention as other materials. There are.

[0004] For example, indium (In), gallium (Ga), and A transistor using an amorphous oxide semiconductor containing zinc (Zn) is disclosed in Patent Document 1. There are. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] JP 2006-165528 A Summary of the Invention [Problem to be solved by the invention]

[0006] As semiconductor elements become smaller, parasitic capacitance near transistors becomes a major problem.

[0007] In transistor operation, the area near the channel (for example, between the source electrode and the drain electrode) If parasitic capacitance is present, it takes time for the parasitic capacitance to charge, which slows down the transistor response. This reduces the performance and thus the response of the semiconductor device.

[0008] In addition, the various processes for forming transistors (especially film formation, processing, etc.) It is becoming increasingly difficult to control this, and variations in the manufacturing process can affect transistor characteristics, and even has a significant impact on reliability.

[0009] In addition, as miniaturization progresses, pattern formation becomes difficult due to the resolution limit of exposure equipment, and Problems have also arisen in the manufacturing of transistors, and the costs of capital investment are becoming enormous.

[0010] Therefore, one aspect of the present invention has an object to reduce parasitic capacitance in the vicinity of a transistor. Another object is to provide a semiconductor device having good electrical characteristics. Another object of the present invention is to provide a semiconductor device having high reliability. To provide a method for manufacturing a transistor or semiconductor device that allows for pattern formation below the resolution limit Alternatively, the present invention aims to prevent a problem that occurs during the manufacturing process of a transistor or a semiconductor device. One of the purposes is to reduce the variation in characteristics caused by oxygen deficiency. Another object of the present invention is to provide a semiconductor device having a nitride semiconductor layer. Another object of the present invention is to provide a semiconductor device that can be formed in a short period of time. The present invention aims to provide a semiconductor device having a structure capable of reducing an interface state density in the vicinity of a semiconductor layer. Another object is to provide a semiconductor device with low power consumption. Another object of the present invention is to provide a novel method for manufacturing a semiconductor device with reduced development costs. Another object is to provide a novel semiconductor device or the like. One of the objects of the present invention is to provide a method for manufacturing the device.

[0011] The description of these problems does not preclude the existence of other problems. It is not necessary for the embodiment to solve all of these problems. The above will become apparent from the description in the specification, drawings, claims, etc. It is possible to extract other issues from the descriptions in the patent, claims, etc. [Means for solving the problem]

[0012] One embodiment of the present invention is a semiconductor device including a first insulating layer, a first oxide semiconductor layer over the first insulating layer, and a first a second oxide semiconductor layer on the oxide semiconductor layer; a source electrode layer on the second oxide semiconductor layer; and a drain electrode layer, and a second insulating layer on the first insulating layer, the source electrode layer, and the drain electrode layer. an insulating layer, a third insulating layer on the second insulating layer, and a third oxide semiconductor layer on the second oxide semiconductor layer; a conductor layer, a gate insulating layer on the third oxide semiconductor layer, and a gate electrode layer on the gate insulating layer; The second insulating layer is an oxygen barrier layer, and the first oxide semiconductor layer and the second oxide semiconductor layer are a third oxide layer having a region in contact with a side surface of the semiconductor layer, the source electrode layer, and the drain electrode layer; The oxide semiconductor layer includes a second oxide semiconductor layer, a source electrode layer, a drain electrode layer, a second insulating layer, and a region in contact with a side surface of the third insulating layer.

[0013] Another embodiment of the present invention is a semiconductor device including a first insulating layer, a first oxide semiconductor layer on the first insulating layer, and a second oxide semiconductor layer. a second oxide semiconductor layer on the first oxide semiconductor layer, and a source electrode on the second oxide semiconductor layer. a first conductive layer having a region in contact with a side surface of the second oxide semiconductor layer, a drain electrode layer, and the second oxide semiconductor layer; a first insulating layer, a second conductive layer, and a first insulating layer on the source electrode layer, and the drain electrode layer; a second insulating layer, a third insulating layer on the second insulating layer, and a third oxide semiconductor layer on the second oxide semiconductor layer. a gate insulating layer on the third oxide semiconductor layer; and a gate electrode on the gate insulating layer. and a second insulating layer, the second insulating layer being an oxygen barrier layer, the first electrode layer and the second electrode layer being disposed adjacent to each other. The third oxide semiconductor layer is in contact with the second insulating layer at the side portion, and the third oxide semiconductor layer is in contact with the first insulating layer and the second insulating layer. A first oxide semiconductor layer, a second oxide semiconductor layer, a source electrode layer, a drain electrode layer, a second insulating layer, A semiconductor device having a side portion of a border layer and a region in contact with a third insulating layer. be.

[0014] Another embodiment of the present invention is a semiconductor device including a first insulating layer, a first oxide semiconductor layer on the first insulating layer, and a second oxide semiconductor layer. a second oxide semiconductor layer on the first oxide semiconductor layer, and a source electrode on the second oxide semiconductor layer. a first insulating layer, a source electrode layer, and a drain electrode layer; and a second insulating layer on the first insulating layer, the source electrode layer, and the drain electrode layer. A second insulating layer, a third insulating layer on the second insulating layer, and a source electrode layer and a drain electrode layer and a fourth insulating layer formed in contact with a side surface of the second insulating layer and the third insulating layer. a third oxide semiconductor layer on the second oxide semiconductor layer; and a gate electrode on the third oxide semiconductor layer. a gate insulating layer on the gate insulating layer, and a gate electrode layer on the gate insulating layer, the first insulating layer being an oxygen barrier layer A first oxide semiconductor layer, a second oxide semiconductor layer, a source electrode layer, and a drain electrode layer The third oxide semiconductor layer has a region in contact with a side surface of the first oxide semiconductor layer. a second oxide semiconductor layer, a source electrode layer, a drain electrode layer, and a fourth insulating layer The semiconductor device is characterized in that it has a region that contacts the side surface of the edge layer.

[0015] In addition, it is preferable to use an aluminum oxide layer as the second insulating layer.

[0016] Another aspect of the present invention is a semiconductor device comprising a first conductive layer, a first insulating layer on the first conductive layer, and a first insulating a first oxide semiconductor layer on the first oxide semiconductor layer; a second oxide semiconductor layer on the first oxide semiconductor layer; A source electrode layer and a drain electrode layer on the oxide semiconductor layer of 2, a first insulating layer, a source electrode a second insulating layer on the first insulating layer and the drain electrode layer; a third insulating layer on the second insulating layer; a third oxide semiconductor layer on the second oxide semiconductor layer; and a gate insulating film on the third oxide semiconductor layer. a gate electrode layer on the gate insulating layer; a third insulating layer; a third oxide semiconductor layer; a gate a fourth insulating layer on the gate electrode layer, the second insulating layer having an oxygen barrier A first oxide semiconductor layer, a second oxide semiconductor layer, a source electrode layer, and a drain electrode layer. The third oxide semiconductor layer is in contact with a side portion of the indium electrode layer, and the third oxide semiconductor layer is formed of the first insulating layer, the first oxide semiconductor a second oxide semiconductor layer, a source electrode layer, a drain electrode layer, a second insulating layer, a third insulating layer, The fourth insulating layer has an area contacting the side surface of the edge layer, and the fourth insulating layer is an oxygen barrier layer. The semiconductor device is as follows.

[0017] It is also preferable to use an aluminum oxide film as the second insulating layer and the fourth insulating layer. It is nice.

[0018] Another embodiment of the present invention is a method for forming a first insulating layer, and forming a first oxide semiconductor film over the first insulating layer. a second oxide semiconductor film is formed over the first oxide semiconductor film, and a first heat treatment is performed. a first conductive film is formed over the second oxide semiconductor film, and a first mask and a first conductive film are formed over the second oxide semiconductor film. The first oxide semiconductor film and the second oxide semiconductor film are partly etched using the film. As a result, the first oxide semiconductor layer and the second oxide semiconductor layer are formed in an island shape. A second insulating layer is formed on the insulating layer and the first conductive film, and when the second insulating layer is formed, A mixed layer of an insulating layer and a second insulating film is formed, and at the same time, an acid is introduced into the mixed layer or the first insulating layer. Then, second heat treatment is performed to diffuse oxygen into the second oxide semiconductor layer. A third insulating film is formed on the insulating layer, and the third insulating layer is planarized to form a third insulating layer. Then, the third insulating layer and the second insulating layer are selectively etched using a second mask. The first conductive film is selectively etched using the second mask and the second insulating layer. The source electrode layer and the drain electrode layer are formed by the above-mentioned method, and the third insulating layer and the second oxide semiconductor are formed by the above-mentioned method. A third oxide semiconductor film is formed on the conductor layer, and a fourth insulating film is formed on the third oxide semiconductor film. a second conductive film is formed on the fourth insulating film; and a second conductive film, a third insulating film, and a fourth insulating film are formed on the second conductive film, the third insulating film, and the fourth insulating film. The third oxide semiconductor film is subjected to chemical mechanical polishing treatment to form a third oxide semiconductor layer, A method for manufacturing a semiconductor device, comprising the steps of: forming a gate insulating layer and a gate electrode layer; be.

[0019] Another embodiment of the present invention is a method for forming a first insulating layer, and forming a first oxide semiconductor film over the first insulating layer. a second oxide semiconductor film is formed over the first oxide semiconductor film, and a first heat treatment is performed. a first conductive film is formed over the second oxide semiconductor film, and a first mask and a first conductive film are formed over the second oxide semiconductor film. The first oxide semiconductor film and the second oxide semiconductor film are selectively etched using the film. As a result, the first oxide semiconductor layer and the second oxide semiconductor layer are formed in an island shape. A second insulating film is formed on the insulating layer and the first conductive film, and the first insulating film is formed on the insulating layer and the first conductive film. forming a mixed layer of the edge layer and the second insulating film, and doping oxygen into the mixed layer or the first insulating layer; A second heat treatment is performed to diffuse oxygen into the second oxide semiconductor layer. The oxygen vacancies in the layer are reduced, a third insulating film is formed on the second insulating film, and a flat insulating film is formed on the third insulating film. A planarization process is performed, and the third insulating film and a part of the second insulating film are etched using a second mask. The third insulating layer and the second insulating layer are formed by etching the first conductive layer, the third A fourth insulating film is formed on the insulating layer and anisotropically etched to form the second insulating layer and A fourth insulating layer is formed in contact with a side surface of the third insulating layer, and the fourth insulating layer is used as a mask. The first conductive film is partially etched to form a source electrode and a drain electrode. and forming a third oxide semiconductor film over the third insulating layer and the second oxide semiconductor layer. A fifth insulating film is formed over the third oxide semiconductor film, and a second conductive film is formed over the fifth insulating film. The second conductive film, the third insulating film, and the third oxide semiconductor film are subjected to a chemical mechanical polishing process. By carrying out the steps, a third oxide semiconductor layer, a gate insulating layer, and a gate electrode layer are formed. The present invention relates to a method for manufacturing a semiconductor device.

[0020] The second insulating film is preferably formed by sputtering using oxygen gas. stomach.

[0021] The second insulating film is formed by sputtering using an aluminum oxide target. It is preferable that the oxygen concentration is 50% by volume or more and that the oxygen concentration is 50% by volume or more.

[0022] The second heat treatment is preferably performed at a temperature of 300° C. or higher and 450° C. or lower.

[0023] Moreover, a configuration can be provided in which a semiconductor device, a microphone, a speaker, and a housing are used. Effect of the Invention

[0024] By using one embodiment of the present invention, parasitic capacitance near a transistor can be reduced. Alternatively, a semiconductor device having good electrical characteristics can be provided. Alternatively, a pattern can be formed below the resolution limit of an exposure device. It is possible to provide a method for manufacturing a transistor or a semiconductor device that can achieve the above. It is possible to reduce the variation in characteristics of a transistor or semiconductor device due to the manufacturing process. Alternatively, a semiconductor device including an oxide semiconductor layer with few oxygen vacancies can be provided. Alternatively, a semiconductor device that can be formed through a simple process can be provided. Alternatively, a semiconductor device having a structure capable of reducing an interface state density in the vicinity of an oxide semiconductor layer is provided. Alternatively, a semiconductor device with low power consumption can be provided. It is possible to provide a novel method for manufacturing a semiconductor device with reduced development costs. A semiconductor device or the like can be provided. Or, a manufacturing method of the semiconductor device can be provided. can be done.

[0025] The description of these effects does not preclude the existence of other effects. An embodiment does not necessarily have to have all of these effects. Effects other than these may also be included. The above is self-evident from the description, drawings, claims, etc. Other effects can be extracted from the claims and other descriptions. [Brief description of the drawings]

[0026] [Figure 1] 1A and 1B are a top view and a cross-sectional view illustrating a transistor. [Diagram 2] 1A and 1B are a top view and a cross-sectional view illustrating a transistor. [Diagram 3] 1A and 1B are a top view and a cross-sectional view illustrating a transistor. [Figure 4] 1A and 1B are band diagrams of an oxide semiconductor layer and an enlarged cross-sectional view of a transistor. [Diagram 5] ALD film formation principle. [Figure 6] Schematic diagram of the ALD equipment. [Figure 7] 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a transistor. [Figure 8] 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a transistor. [Figure 9] 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a transistor. [Figure 10] 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a transistor. [Figure 11] 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a transistor. [Figure 12] 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a transistor. [Figure 13] 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a transistor. [Figure 14] 1A and 1B are a top view and a cross-sectional view illustrating a transistor. [Figure 15] 1A and 1B are a top view and a cross-sectional view illustrating a transistor. [Figure 16] 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a transistor. [Figure 17] 1A and 1B are a top view and a cross-sectional view illustrating a transistor. [Figure 18] 1A and 1B are a top view and a cross-sectional view illustrating a transistor. [Figure 19] 1A and 1B are a top view and a cross-sectional view illustrating a transistor. [Figure 20] 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a transistor. [Figure 21] 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a transistor. [Figure 22] 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a transistor. [Diagram 23] 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a transistor. [Figure 24] Cs-corrected high-resolution TEM image of a cross section of CAAC-OS, and a schematic cross-sectional diagram of CAAC-OS. [Diagram 25] Cs-corrected high-resolution TEM image of the CAAC-OS in the plane. [Figure 26] 13A to 13C show structural analyses of a CAAC-OS and a single-crystal oxide semiconductor by XRD. [Figure 27] Electron diffraction pattern of CAAC-OS. [Figure 28] FIG. 1 shows the change in the crystal part of an In-Ga-Zn oxide due to electron irradiation. [Figure 29] 1A and 1B are a cross-sectional view and a circuit diagram of a semiconductor device. [Diagram 30] 1A and 1B are a cross-sectional view and a circuit diagram of a semiconductor device. [Diagram 31] FIG. [Diagram 32] FIG. 2 is a plan view showing pixels of the imaging device. [Diagram 33] FIG. [Diagram 34] FIG. [Diagram 35] FIG. 2 is a diagram for explaining an example of the configuration of an RF tag. [Diagram 36] FIG. 2 is a diagram for explaining an example of the configuration of a CPU. [Figure 37] FIG. [Figure 38] 1A and 1B are diagrams illustrating a configuration example of a display device and a circuit diagram of a pixel. [Figure 39] FIG. 2 is a diagram illustrating a display module. [Diagram 40] FIG. 1 is a perspective view showing a cross-sectional structure of a package using a lead frame type interposer. [Diagram 41] 1A to 1C are diagrams illustrating electronic devices. [Diagram 42] 1A to 1C are diagrams illustrating electronic devices. [Diagram 43] 1A to 1C are diagrams illustrating electronic devices. [Diagram 44] 1A to 1C are diagrams illustrating electronic devices. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0027] The embodiment will be described in detail with reference to the drawings. However, the present invention is not limited to the following description. The present invention may be modified in various ways in form and detail without departing from the spirit and scope of the present invention. It will be readily understood by those skilled in the art that the present invention can be modified in various ways. The present invention is not limited to the above-mentioned embodiments. In the drawings, the same reference numerals are used to designate the same parts or parts having similar functions. In addition, the same elements constituting the figures are used in the same way, and their repeated explanations may be omitted. In some cases, the patterns may be omitted or changed as appropriate between different drawings.

[0028] For example, in the present specification, when it is explicitly stated that X and Y are connected, In this case, X and Y are electrically connected, and X and Y are functionally connected. The case where X and Y are directly connected is also considered to be disclosed in the present specification. Therefore, the present invention is not limited to a specific connection relationship, for example, a connection relationship shown in a drawing or a sentence. Any connections other than those shown in the drawings or text shall be deemed to be included in the drawings or text. do.

[0029] Here, X and Y are objects (e.g., devices, elements, circuits, wiring, electrodes, terminals, conductive films, layers, etc.). , etc.).

[0030] An example of a direct connection between X and Y is a circuit that allows electrical connection between X and Y. The elements to be considered (e.g., switches, transistors, capacitance elements, inductors, resistance elements, When a resistor (such as an electrode, display element, light-emitting element, or load) is not connected between X and Y, The elements that allow electrical connection between X and Y (e.g., switches, transistors, capacitors, etc.) elements, inductors, resistors, diodes, display elements, light-emitting elements, loads, etc.) , X and Y are connected.

[0031] An example of a case where X and Y are electrically connected is The elements to be considered (e.g., switches, transistors, capacitance elements, inductors, resistance elements, One or more elements (such as an electrode, a display element, a light-emitting element, or a load) can be connected between X and Y. It is possible. The switch has a function that allows it to be turned on and off. A switch can be in a conductive state (on state) or a non-conductive state (off state) and can either pass current or not. The switch has the function of controlling whether or not current flows. When X and Y are electrically connected, This includes the case where Y is directly connected.

[0032] An example of a case where X and Y are functionally connected is a case where a functional connection between X and Y is possible. Circuits that perform the above functions (for example, logic circuits (inverters, NAND circuits, NOR circuits, etc.), signal conversion conversion circuits (DA conversion circuits, AD conversion circuits, gamma correction circuits, etc.), potential level conversion circuits ( power supply circuits (voltage boost circuits, voltage drop circuits, etc.), level shifter circuits that change the potential level of signals, etc.) , voltage sources, current sources, switching circuits, amplifier circuits (which can increase the signal amplitude or current amount, etc.) circuits, operational amplifiers, differential amplifier circuits, source follower circuits, buffer circuits, etc.), signal generation One or more devices (such as a memory circuit, a control circuit, etc.) can be connected between X and Y. For example, even if another circuit is inserted between X and Y, the signal output from X If X is transmitted to Y, then X and Y are considered to be functionally connected. When X and Y are functionally connected, there are cases where X and Y are directly connected and cases where X and Y are functionally connected. and the case where they are electrically connected to each other.

[0033] In addition, if it is explicitly stated that X and Y are electrically connected, are electrically connected (i.e., there is another element or circuit between X and Y) When X and Y are functionally connected (i.e., when X and Y are connected), (When there is a functional connection between X and Y via another circuit in between) and when X and Y are directly connected (i.e., when X and Y are connected without any other element or circuit between them) is deemed to be disclosed in the present specification. If it is explicitly stated that it is connected, The same contents are deemed to be disclosed in the present specification and the like.

[0034] For example, the source (or the first terminal, etc.) of the transistor is connected via Z1 (or The drain (or second terminal, etc.) of the transistor is electrically connected to Z 2 (or not), it may be electrically connected to Y, or the source of the transistor (or the first terminal, etc.) is directly connected to a part of Z1, and another part of Z1 is directly connected to X. The drain (or second terminal, etc.) of the transistor is directly connected to a part of Z2. and another part of Z2 is directly connected to Y, It is possible to do so.

[0035] For example, "X and Y and the source (or first terminal, etc.) and drain (or second terminal, etc.) of a transistor The terminals of the transistor (or the first terminal, etc.) are electrically connected to each other, and X, the source of the transistor (or the first terminal, etc.) 1 terminal, etc.), the drain (or second terminal, etc.) of the transistor, and Y. "The source (or the third) of the transistor is connected to the The drain (or second terminal, etc.) of the transistor is electrically connected to X. The transistor source (or first terminal, etc.) is electrically connected to Y, and the transistor source (or first terminal, etc.) is electrically connected to X. The drain (or second terminal, etc.) of the transistor, Y, is electrically connected in this order. " Alternatively, "X is the source (or first terminal, etc.) of a transistor. The transistor is electrically connected to Y via a drain (or a second terminal, etc.) and a transistor is electrically connected to X via a drain (or a second terminal, etc.). The source (or first terminal, etc.) of a resistor, the drain (or second terminal, etc.) of a transistor ), Y is provided in this connection order. By using a simple expression method and specifying the order of connections in the circuit configuration, Distinguish between the source (or first terminal, etc.) and the drain (or second terminal, etc.) of a transistor. The technical scope can be determined based on the above.

[0036] Or, as another way of expressing it, for example, "the source (or first terminal, etc.) of a transistor is electrically connected to X through at least a first connection path, and the first connection path is , the second connection path does not have a second connection path, and the second connection path is a transistor The source (or first terminal, etc.) of the transistor and the drain (or second terminal, etc.) of the transistor The first connection path is a path via Z1, and the second connection path is a path between the transistor The drain (or second terminal, etc.) of the capacitor is electrically connected to Y through at least a third connection path. The third connection path does not include the second connection path, and the third The connection path is the path through Z2. The source (or the first terminal, etc.) of the resistor is connected to the resistor via Z1 by at least the first connection path. and electrically connected to X, and the first connection path does not have a second connection path, The second connection path has a connection path through a transistor, and the drain of the transistor (or the second terminal, etc.) is connected to Y via Z2 by at least a third connection path. The third connection path does not have the second connection path. Alternatively, the source (or the first terminal, etc.) of the transistor may be at least The first electrical path is electrically connected to X through Z1. The primary path does not have a second electrical path, and the second electrical path is a From the source (or first terminal, etc.) to the drain (or second terminal, etc.) of the transistor The drain (or second terminal, etc.) of the transistor is connected to at least a third The third electrical path is electrically connected to Y through Z2. , the fourth electrical path is not included, and the fourth electrical path is a drain of the transistor (or second terminal, etc.) to the source (or first terminal, etc.) of the transistor. Using the same expression as these examples, the circuit configuration By defining the connection path in Distinguish between the first terminal (or the second terminal, etc.) and the drain (or the second terminal, etc.) to determine the technical scope. can be done.

[0037] Note that these expression methods are merely examples, and the present invention is not limited to these expression methods. , Y, Z1, and Z2 are objects (e.g., devices, elements, circuits, wiring, electrodes, terminals, conductive films, layer, etc.).

[0038] In addition, the circuit diagram shows independent components as if they are electrically connected to each other. Even if the components are the same, one component may have the functions of multiple components. For example, when a part of the wiring also functions as an electrode, one conductive film has the function of the wiring and The electrode functions as both components. The term "electrochemically connected" refers to a case where one conductive film has the functions of multiple components. This also falls within the scope of the above.

[0039] The embodiment will be described in detail with reference to the drawings. However, the present invention is not limited to the following description. The present invention is not limited to the above embodiment, and various changes and modifications may be made in the form and details without departing from the spirit and scope of the present invention. It will be easily understood by those skilled in the art that the above-mentioned invention can be obtained by the following embodiments. The present invention should not be construed as being limited to the contents described below. The same reference numerals are used in different drawings to indicate the same parts or parts having similar functions. A repeated explanation will be omitted.

[0040] <Notes on the description explaining the drawings> In this specification, the terms "above" and "below" that indicate the positional relationship between components are used. The above is used for convenience in describing the drawings. The meaning of the term varies depending on the direction in which the configuration is depicted. It is not limited to this and can be rephrased appropriately depending on the situation.

[0041] In addition, the terms "above" and "below" refer to the positional relationship of components directly above or below each other and directly adjacent to each other. For example, if the expression is "electrode B on insulating layer A," It is not necessary for electrode B to be formed directly on insulating layer A. This does not exclude the inclusion of other components.

[0042] In this specification, "parallel" means that two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, it includes the case where the angle is between -5° and 5°. "Line" refers to the state in which two straight lines are arranged at an angle between -30° and 30°. "Perpendicular" means that two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, the angle may be between 85° and 95°. This refers to a state in which two straight lines are arranged at an angle of 60° or more and 120° or less.

[0043] In addition, in this specification, when the crystal is a trigonal or rhombohedral crystal, it is represented as a hexagonal crystal system. .

[0044] In addition, in the drawings, the size, layer thickness, and area are shown arbitrarily for convenience of explanation. Therefore, the drawings are not necessarily limited to the scale. The drawings are merely schematic illustrations for illustrative purposes only, and are not limited to the shapes or values ​​shown in the drawings.

[0045] In addition, in the drawings, in top views (also called plan views or layout views) and perspective views, In order to clarify the drawings, some components may be omitted.

[0046] In addition, "the same" may mean having the same area or the same shape. Due to the manufacturing process, it is expected that the shapes will not be completely identical. In other words, they are the same.

[0047] <Notes on possible alternative descriptions> In the present specification and the like, when describing the connection relationship of a transistor, is expressed as "one of the source and drain" (or the first electrode, or the first terminal), and The other side of the drain is referred to as the "other side of the source or drain" (or the second electrode, or the second terminal). This is because the source and drain of a transistor are This is because it changes depending on the conditions. Regarding the names of the source and drain of a transistor, can be appropriately rephrased as source (drain) terminal, source (drain) electrode, etc., depending on the situation. It is possible to do so.

[0048] In addition, the terms "electrode" and "wiring" used in this specification and the like do not limit the functionality of these components. For example, an "electrode" may be used as part of a "wire." In addition, the term "electrode" or "wiring" may be used to refer to the plural "electrodes" or "wirings". This also includes cases where the "line" is formed as a single unit.

[0049] In this specification, a transistor includes a gate, a drain, and a source. It is an element that has at least three terminals. And the drain (drain terminal, drain A channel is formed between the source (source terminal, source region or drain electrode) and the source (source terminal, source region or source electrode). The transistor has a channel region and allows current to flow through the drain, the channel region, and the source. It is possible.

[0050] Here, the source and drain vary depending on the structure or operating conditions of the transistor. Therefore, it is difficult to determine which is the source and which is the drain. The part that functions as a source and the part that functions as a drain are not called a source or a drain. One of the source and the drain is referred to as a first electrode, and the other of the source and the drain is referred to as a second electrode. It may be indicated.

[0051] In this specification, the ordinal numbers "first," "second," and "third" are used to avoid confusion of the elements. It should be noted that the numbers are added to avoid confusion and are not intended to be limiting.

[0052] In the present specification, the substrate of the display panel is provided with, for example, an FPC (Flexible Printed Circuit). Integrated Circuits) or TCP (Tape Carrier Packa ge) or COG (Chip On Glass) on the board Devices in which ICs (integrated circuits) are directly mounted using this method are sometimes called display devices.

[0053] In addition, the words "membrane" and "layer" may be interchangeable depending on the situation. For example, the term "conductive layer" can be used interchangeably with the term "conductive film." ". Alternatively, for example, the term "insulating film" may be used. It may be possible to change the term to "insulating layer."

[0054] <Notes on definitions of terms> The following provides an explanation of the definitions of each term used in this specification.

[0055] In this specification, the term "trench" or "groove" refers to a thin, band-shaped recess. This refers to only that.

[0056] In this specification, when a film is represented by, for example, silicon oxynitride, it is represented by SiOxNy. In this case, x and y may be natural numbers or numbers with decimal points. Good too.

[0057] <About connection> In this specification, "A and B are connected" does not mean that A and B are directly connected. In addition to the above, it also includes those that are electrically connected. Here, A and B are electrically connected. Being connected means that there is an object between A and B that has some electrical effect. A communication line is a line that enables the transmission of electrical signals between A and B.

[0058] Note that these expression methods are merely examples, and the present invention is not limited to these expression methods. , Y, Z1, and Z2 are objects (e.g., devices, elements, circuits, wiring, electrodes, terminals, conductive films, layer, etc.).

[0059] In addition, the contents (or even a part of the contents) described in one embodiment may be used in the embodiment. Another subject matter (or a part of the subject matter) described in the above and / or one or more other embodiments The contents (or a part of the contents) described in the embodiments may be applied, combined, or replaced. It is possible to do things like drawing.

[0060] The contents described in the embodiments are explained in detail with reference to various figures in each embodiment. This refers to the content that is stated or stated using the text in the specification.

[0061] In addition, a figure (or a part thereof) described in one embodiment may be different from another part of the figure, Another figure (or a part thereof) described in the embodiment, and / or one or more By combining the figures (or a part of them) described in the other embodiments of the present invention, This allows even more diagrams to be constructed.

[0062] (Embodiment 1) In this embodiment, a semiconductor device according to one embodiment of the present invention and a manufacturing method thereof will be described with reference to the drawings. explain.

[0063] 1A, 1B, and 1C are top views and diagrams of a transistor 10 according to one embodiment of the present invention. 1(A) is a top view, and FIG. 1(B) is a cross-sectional view of the structure shown in FIG. 1(A). FIG. 1(A) is a cross-sectional view of the A1-A2 section, and FIG. 1(C) is a cross-sectional view of the A3-A4 section. For clarity, some elements are illustrated enlarged, reduced, or omitted. The A1-A2 direction is called the channel length direction, and the dashed line A3-A4 direction is called the channel width direction. There are cases.

[0064] The transistor 10 includes a substrate 100, an insulating layer 110, an oxide semiconductor layer 121, and an oxide A semiconductor layer 122, an oxide semiconductor layer 123, a source electrode layer 130, and a drain electrode layer 1 40, a gate insulating layer 150, a gate electrode layer 160, an insulating layer 170, and an insulating layer 175. The insulating layer 110 is formed on the substrate 100. The oxide semiconductor layer 121 has The oxide semiconductor layer 122 is formed on the insulating layer 110. The source electrode layer 130 and the drain electrode layer 140 are formed on the oxide semiconductor layer 122. The insulating layer 170 is formed on the insulating layer 110 and is electrically connected to the oxide semiconductor layer 122. , the source electrode layer 130, and the drain electrode layer 140. The insulating layer 175 is formed on the insulating layer 170 and is in contact with the side surface of the oxide semiconductor layer 122. The oxide semiconductor layer 123 is in contact with the oxide semiconductor layer 123 at a portion of the oxide semiconductor layer 123. The oxide semiconductor layer 123 is formed on the side surface of the insulating layer 170 and the insulating layer 175. The gate electrode layer 130 is in contact with a side surface of the gate electrode layer 130, a side surface of the source electrode layer 130, and a side surface of the drain electrode layer 140. The gate insulating layer 150 is formed on the oxide semiconductor layer 123. The gate electrode layer 160 is The insulating layer 150 is formed on the insulating layer 150 .

[0065] In FIG. 1B, the gate electrode layer 160 is shown as a single layer. The transistor 10 may include a stack of an electrode layer 161 and a gate electrode layer 162. The end portions of the oxide semiconductor layer 123 and the gate insulating layer 150 are closer to the gate electrode layer 160 than the end portions of the gate insulating layer 150. The above-described structure includes an oxide semiconductor layer 122 and an oxide semiconductor Since the semiconductor layer 123 is in contact with the source electrode layer 130 and the drain electrode layer 140, During operation of the transistor 10, the oxide semiconductor layer 121, the oxide semiconductor layer 122, and the oxide semiconductor layer 123 are This has the characteristic of being highly effective in dissipating heat generated within the conductor layer 123 .

[0066] In addition, when the second insulating film that becomes the insulating layer 170 is formed, the transistor 10 is The material of the insulating layer 110 and the material of the second insulating film are used at the interface with the insulating film 10. A mixed layer containing the gas, etc., is formed, and oxygen (excess oxygen) is added to the mixed layer or the insulating layer 110. Further, by performing heat treatment, the oxygen is added to the oxide semiconductor layer The oxide semiconductor layer 121 and the oxide semiconductor layer 122 are diffused. The oxygen can compensate for the oxygen vacancies present in the layer 122. The transistor characteristics (eg, threshold voltage, reliability, etc.) can be improved.

[0067] The excess oxygen added during the formation of the second insulating film is, for example, a SiO 2 film formed by sputtering. The oxygen radiance may change due to the voltage, power, plasma, or substrate temperature applied during film formation. The excess oxygen exists in various forms, such as oxygen atoms, oxygen ions, or oxygen atoms. is a state having more energy than the stable state, and penetrates into the insulating layer 110. It is possible.

[0068] The method for adding oxygen is not limited to the above method. It may have excess oxygen or may be formed by other methods (e.g., ion implantation, ion plasma) after deposition. A method such as a dipping method may also be used.

[0069] As shown in the cross-sectional view of FIG. 1C along A3-A4, the transistor 10 has a channel width direction The gate electrode layer 160 is connected to the oxide semiconductor layer 121 and the oxide semiconductor layer 122 via the gate insulating layer 150. The conductor layer 122 faces the side surface of the oxide semiconductor layer 123. When pressure is applied, the oxide semiconductor layer 121, the oxide semiconductor layer 122, and the oxide semiconductor layer 12 3 is surrounded by the electric field of the gate electrode layer 160 in the channel width direction. The structure of a transistor in which the semiconductor layer is surrounded by an electric field of 0 is called the surrounded channel. The transistor 10 has a cell structure using a trench. Since the gate electrode, source electrode, and drain electrode can be formed in a single line, This method has excellent alignment accuracy and makes it possible to easily fabricate fine transistors. Such a structure is called a self-aligned s-channel FET (Self Aligned S -channel FET, SA s-channel FET) structure, or trench Gate s-channel FET(Trench gate s-channel F ET), or TGSA FET (Trench Gate Self Align) structure or GLSA FET (Gate Last Self Align FET) Call.

[0070] Here, the oxide semiconductor layer 121, the oxide semiconductor layer 122, and the oxide semiconductor layer 123 are combined. When the oxide semiconductor layer 120 is formed by combining the above, a transistor having an SA s-channel structure is formed. In the on-state, a channel is formed in the entire oxide semiconductor layer 120 (bulk). On the other hand, in the off state, the on-state current is increased due to the formation of the oxide semiconductor layer 120. Since the entire channel region is depleted, the off-current can be further reduced.

[0071] As a result, the oxide semiconductor layer 123, the gate insulating layer 150, and the gate electrode layer 124 are formed in the groove 174. When forming the transistor 10, the embedding property of each film can be improved. It can be easily produced.

[0072] In addition, since the transistor 10 has a TGSA structure, or reducing the parasitic capacitance occurring between the gate electrode and the drain electrode, thereby improving the cutoff frequency of the transistor 10. This allows the transistor 10 to have high-speed response, for example by improving wave number characteristics.

[0073] The position of the top surface of the source electrode layer 130 or the drain electrode layer 140 is the same as that of the gate electrode layer It may be lower than the position of the bottom surface of 160, may be the same as, or may be higher.

[0074] In addition, the transistor 10 may have the groove 174 in FIG. As shown in FIG. 2B, the upper surface of the gate electrode layer 160 is lower than the upper surface of the insulating layer 175. Alternatively, the transistor 10 may be provided with an insulating film 150a, The third oxide semiconductor film 123a does not necessarily need to be planarized. As shown in FIG. 3(A), the ends of the source electrode layer 130 and the drain electrode layer are made of oxide. The insulating layer 124 may have a shape that is shorter or longer than the nitride semiconductor layer 122 .

[0075] <Channel length> Note that the channel length is, for example, the length of a semiconductor (or transistor) in a top view of a transistor. The area where the gate electrode overlaps with the semiconductor (the part of the semiconductor through which current flows when the transistor is in the on-state). or a source (source region or source electrode) in the region where the channel is formed This refers to the distance between the drain (drain region or drain electrode) and the transistor. In a transistor, the channel length does not necessarily have the same value in all regions. The channel length of a transistor may not be determined to a single value. The channel length is a value, a maximum value, or a minimum value in the region where the channel is formed. Or the average value.

[0076] <About channel width> The channel width is the width of the semiconductor (or transistor) when it is in the on state. This refers to the length of the area where the gate electrode overlaps with the current-carrying part of a transistor. In a transistor, the channel width does not necessarily have the same value in all regions. The channel width of a transistor may not be determined to a single value. The channel width is a value that can be any one of the values, the maximum value, the minimum value, or the like in the region where the channel is formed. or the average value.

[0077] Depending on the structure of the transistor, the channel in the region where the channel is actually formed may vary. The effective channel width (hereinafter referred to as the effective channel width) shown in the top view of the transistor The channel width (hereinafter referred to as the apparent channel width) may be different. For example, In a transistor having a three-dimensional structure, the effective channel width is The effect of the channel width becomes larger than the apparent channel width shown in For example, in a transistor with a fine, three-dimensional structure, The percentage of the channel region that is formed on the side of the semiconductor, compared to the percentage of the channel region that is formed In that case, the apparent channel width shown in the top view may be larger. In this case, the effective channel width where the channel is actually formed is larger than the width of the channel formed by the MOSFET.

[0078] By the way, in a transistor having a three-dimensional structure, the effective channel width is For example, it may be difficult to estimate the effective channel width from the design value. In order to obtain this, it is necessary to assume that the shape of the semiconductor is known. Unless k is precisely known, it is difficult to accurately measure the effective channel width.

[0079] <SCWについて> Therefore, in this specification, in a top view of a transistor, a semiconductor and a gate electrode are overlapped. The apparent channel width in the region is called the Surrounding Channel Width (SCW). In this specification, it is simply called When channel width is mentioned, it refers to enclosed channel width or apparent channel width. In this specification, when the term "channel width" is used, it means an effective channel width. In addition, channel length, channel width, effective channel width, apparent channel width, The width of the upper channel and the width of the enclosed channel are obtained by taking a cross-sectional TEM image. The value can be determined, such as by analysis.

[0080] In addition, the field effect mobility of the transistor and the current value per channel width are calculated. In some cases, the effective channel width may be used. The value may differ from that calculated using the channel width.

[0081] <Improvement of characteristics through miniaturization> In order to increase the integration density of semiconductor devices, it is essential to miniaturize transistors. It is known that the electrical characteristics of transistors deteriorate as the channel width shrinks. When the ON current is reduced, the ON current decreases.

[0082] For example, in the transistor of one embodiment of the present invention shown in FIG. 1, as described above, the channel is formed A third oxide semiconductor layer 123 is formed so as to cover the oxide semiconductor layer 122 formed on the first oxide semiconductor layer 122. Therefore, the channel formation layer and the gate insulating layer are not in contact with each other. This suppresses the scattering of carriers at the interface between the layer and the gate insulating layer, The on-state current can be increased.

[0083] In the transistor of one embodiment of the present invention, the oxide semiconductor layer 122 serving as a channel Since the gate electrode layer 160 is formed so as to electrically surround the panel in the width direction, the oxide In addition to the gate electric field from the vertical direction, the semiconductor layer 1223 is also subjected to the gate electric field from the side direction. That is, the gate electric field is applied to the entire oxide semiconductor layer. As a result, a current flows through the entire oxide semiconductor layer 122, which further increases the on-state current. can be.

[0084] In the transistor of one embodiment of the present invention, the oxide semiconductor layer 123 is By forming the oxide semiconductor layer 122, it is possible to prevent the formation of an interface state. By making the semiconductor layer 122 the intermediate layer, the influence of impurities from above and below can be eliminated. Therefore, in addition to the above-mentioned improvement in the on-state current of the transistor, This makes it possible to stabilize the threshold voltage and reduce the S value (subthreshold value). Therefore, Icut (the current when the gate voltage VG is 0V) can be reduced, and power consumption In addition, the threshold voltage of the transistor is stabilized, The long-term reliability of the semiconductor device can be improved.

[0085] In this embodiment, the oxide semiconductor layer 120 is used in the channel, etc. However, one aspect of the embodiment of the present invention is not limited to this. Depending on the circumstances, the channel or its vicinity, the source region, the drain region, etc. Depending on the material, silicon (including distorted silicon), germanium, silicon germanium, silicon carbide Cu, gallium arsenide, aluminum gallium arsenide, indium phosphide, gallium nitride, organic It may be formed of a material having a semiconductor or the like.

[0086] <Transistor structure> The structure of a transistor in this embodiment will be described below.

[0087] <<Substrate 100>> The substrate 100 may be, for example, a glass substrate, a ceramic substrate, a quartz substrate, a sapphire substrate, etc. In addition, a single crystal semiconductor substrate made of silicon or silicon carbide, a multi-crystal Semiconductor substrates, compound semiconductor substrates made of silicon germanium, SOI (Semiconductor on Insulation) It is also possible to use a substrate such as an inductor-on-insulator (Inductor-On-Insulator) substrate. A semiconductor element may be provided on the substrate. The substrate 100 is not limited to being a simple support material, but may also be a substrate on which other devices such as transistors are formed. In this case, the gate electrode layer 160 and the source electrode layer 13 of the transistor 0, and one of the drain electrode layers 140 is electrically connected to the other devices described above. This is also fine.

[0088] A flexible substrate may be used as the substrate 100. As a method for providing the transistor, a transistor is formed on a non-flexible substrate, and then the transistor is Alternatively, the substrate 100 may be peeled off and transferred to a flexible substrate 100. A peeling layer may be provided between the substrate and the transistor. Alternatively, a sheet, film, or foil having a stretchable structure may be used. In addition, the substrate 100 has the property of returning to its original shape when bending or pulling is stopped. Alternatively, the substrate 100 may have a property of not returning to its original shape. For example, the thickness is 5 μm or more and 700 μm or less, preferably 10 μm or more and 500 μm or less, and more preferably 10 μm or more and 500 μm or less. The thickness of the substrate 100 is preferably 15 μm or more and 300 μm or less. In addition, by making the substrate 100 thinner, it is possible to reduce the weight of the substrate. It has the ability to stretch even when bent or pulled, and to return to its original shape when bending or pulling is stopped. Therefore, the semiconductor device on the substrate 100 may be subjected to a shock due to being dropped or the like. In other words, a robust semiconductor device can be provided.

[0089] The substrate 100, which is a flexible substrate, may be, for example, a metal, an alloy, a resin, or a glass. The substrate 100, which is a flexible substrate, has a linear expansion coefficient of The lower the temperature, the more preferable it is since deformation due to the environment is suppressed. For example, the linear expansion coefficient is 1×10 -3 / K or less, 5×10 -5 / K or less, or 1×10 -5 The resin may be, for example, polyester or polyolefin. Polyimide, polycarbonate, acrylic Aramid, in particular, has a linear expansion coefficient of Since the resistance is low, it is suitable for the substrate 100 which is a flexible substrate.

[0090] Insulating layer 110 The insulating layer 110 serves to prevent the diffusion of impurities from the substrate 100 and also serves to form an oxide semiconductor. The insulating layer 110 can supply oxygen to the conductor layer 120. It is preferable that the insulating film contains oxygen in an amount larger than the stoichiometric composition. For example, it is more preferable that the amount of oxygen released, calculated as oxygen atoms, is 1.0 ×10 19 atoms / cm 3The membrane is the membrane at the time of the above TDS analysis. The surface temperature is in the range of 100°C to 700°C or 100°C to 500°C. As described above, when the substrate 100 is a substrate on which other devices are formed, In this case, the insulating layer 110 is formed so as to have a flat surface. It can be polished by chemical mechanical polishing (CMP) method. It is preferable to carry out a smoothing treatment.

[0091] <Oxide semiconductor layers 121, 122, and 123> The oxide semiconductor layer 122 is an oxide semiconductor film containing In or Zn, typically In-Ga oxide, In-Zn oxide, In-Mg oxide, Zn-Mg oxide, In-M -Zn oxide (M is Al, Ti, Ga, Y, Zr, Sn, La, Ce, Mg, or Nd ) is available.

[0092] The oxide semiconductor layers 121, 122, and 123 are formed of The oxide semiconductor that can be used is one that contains at least indium (In) or zinc (Zn). It is preferable that the oxide contains both In and Zn. In order to reduce the variation in the electrical characteristics of semiconductor transistors, It is preferred to include a riser.

[0093] The stabilizers are gallium (Ga), tin (Sn), hafnium (Hf), and aluminum. Aluminum (Al) or zirconium (Zr). Also, with other stabilizers The lanthanides lanthanum (La), cerium (Ce), and praseodymium (P r), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium ( Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium Er, Thulium, Ytterbium, Lutetium, etc. .

[0094] When the oxide semiconductor layer 123 is an In-M-Zn oxide, the ratio of In atoms to M atoms is is preferably such that In is 25 atomic % or more and M is less than 75 atomic %; Preferably, In is 34 atomic % or more and M is less than 66 atomic %.

[0095] The contents of indium, gallium, and the like in the oxide semiconductor layer 123 are determined by time-of-flight secondary ion Mass spectrometry (TOF-SIMS), X-ray electron spectroscopy (XPS), ICP mass spectrometry (IC P-MS) for comparison.

[0096] The oxide semiconductor layer 122 has an energy gap of 2 eV or more, preferably 2.5 eV or more. More preferably, the voltage is 3 eV or more, so that the off-state current of the transistor 10 can be reduced. can.

[0097] The thickness of the oxide semiconductor layer 122 is 3 nm to 200 nm, preferably 3 nm to 10 0 nm or less, and more preferably 3 nm or more and 50 nm or less.

[0098] The oxide semiconductor layer 121 and the oxide semiconductor layer 123 constitute the oxide semiconductor layer 122. Therefore, the oxide semiconductor layer 12 is an oxide semiconductor film composed of one or more elements. At the interfaces between the oxide semiconductor layer 122 and the oxide semiconductor layer 124, interface scattering occurs. Therefore, the movement of carriers is not hindered at the interface, and the transistor The field effect mobility of the sintered body 10 is increased.

[0099] The oxide semiconductor layer 121 and the oxide semiconductor layer 123 are typically made of In—Ga oxide or In -Zn oxide, In-Mg oxide, Ga-Zn oxide, Zn-Mg oxide, In-MZ n oxide (M is Al, Ti, Ga, Y, Zr, Sn, La, Ce, Mg, or Nd) the energy level of the conduction band minimum is closer to the vacuum level than that of the oxide semiconductor layer 122; Typically, the energies of the conduction band minimums of the oxide semiconductor layers 121 and 123 are , the difference between the energy of the conduction band minimum of the oxide semiconductor layer 122 and the energy of the oxide semiconductor layer 122 is 0.05 eV or more, 7 eV or more, 0.1 eV or more, or 0.2 eV or more and 2 eV or less, 1 eV or less, 0 That is, the oxide semiconductor layer 121 and the oxide semiconductor layer 122 have a refractive index of 0.5 eV or less, or 0.4 eV or less. The difference between the electron affinity of the oxide semiconductor layer 123 and the electron affinity of the oxide semiconductor layer 122 is 0.05 e V or more, 0.07 eV or more, 0.1 eV or more, or 0.2 eV or more and 2 eV or less, The electron affinity is 1 eV or less, 0.5 eV or less, or 0.4 eV or less. This indicates the difference in energy between the level and the bottom of the conduction band.

[0100] The oxide semiconductor layer 121 and the oxide semiconductor layer 123 are made of Al, Ti, Ga, Y, Zr, S By having a higher atomic ratio of In, La, Ce, Mg, or Nd than In, the following effects are obtained. (1) The oxide semiconductor layer 121, the oxide semiconductor layer 122, and the oxide semiconductor layer 123 may have an effect. (2) The energy gap of the oxide semiconductor layer 121 is increased. (3) To block impurities from the outside. 4) Higher insulation properties compared to the oxide semiconductor layer 122. (5) Al, Ti, Ga, Y , Zr, Sn, La, Ce, Mg, or Nd are metal elements that have strong bonding strength with oxygen. Therefore, Al, Ti, Ga, Y, Zr, Sn, La, Ce, Mg, or Nd is used at a higher concentration than In. By having a low atomic ratio, oxygen deficiency is less likely to occur.

[0101] Note that the oxide semiconductor layers 121 and 123 have a structure similar to that of the oxide semiconductor layer 122. Since it has high insulating properties, it has the same function as a gate insulating layer.

[0102] When the oxide semiconductor layer 121 and the oxide semiconductor layer 123 are made of In-M-Zn oxide, Zn The atomic ratio of In and M excluding O is preferably 50 atomic percent In. % or less, M is 50 atomic % or more, and more preferably In is 25 atomic % or more. Below, M must be 75 atomic% or more.

[0103] The oxide semiconductor layer 121 and the oxide semiconductor layer 123 are made of In-M-Zn oxide (M is Al , Ti, Ga, Y, Zr, Sn, La, Ce, Mg, or Nd) oxide semiconductor Compared with the layer 122, the M(Al , Ti, Ga, Y, Zr, Sn, La, Ce, Mg, or Nd) with a high atomic ratio, Generally speaking, the amount of the atoms contained in the oxide semiconductor layer 123 is preferably 1.5 times or more. The atomic ratio is preferably at least two times, more preferably at least three times higher. Since indium is more strongly bonded to oxygen than indium, oxygen vacancies are formed in the oxide semiconductor layer 121 and the oxide semiconductor layer 122. The oxide semiconductor layer 121 and the oxide The oxide semiconductor layer 123 is an oxide semiconductor film in which oxygen vacancies are less likely to occur than in the oxide semiconductor layer 122. be.

[0104] In addition, the oxide semiconductor layer 122 is more intrinsic than the oxide semiconductor layer 121 and the oxide semiconductor layer 123. In oxide semiconductors, the s orbitals of heavy metals are mainly carriers. By increasing the In content, more s orbitals overlap. Therefore, oxides with a composition in which In is greater than M are oxides with a composition in which In is equal to or less than M. Therefore, the oxide semiconductor layer 122 contains indium. By using a large amount of oxide, it is possible to realize a transistor with high field effect mobility. Cut.

[0105] The oxide semiconductor layer 122 is an In-M-Zn oxide (wherein M is Al, Ti, Ga, Y, Z). In the case of the oxide semiconductor layer 122, the oxide semiconductor layer 122 is formed by using the oxide semiconductor layer 122 as a film. The atomic ratio of the metal elements in the target used for this purpose is In:M:Zn=x1:y1:z If x1 / y1 is 1 / 3 or more and 6 or less, and z1 / It is preferable that y1 is 1 / 3 or more and 6 or less, and more preferably 1 or more and 6 or less. When y1 is 1 or more and 6 or less, the oxide semiconductor layer 122 can have a CAAC-OS (CA xis Aligned Crystalline Oxide Semiconductor A typical example of the atomic ratio of the metal elements in the target is as follows: In:M:Zn=1:1:1, In:M:Zn=1:1:1.2, 2:1:1.5, 2: Examples include 1:2.3, 2:1:3, 3:1:2, 4:2:3, 4:2:4.1, etc.

[0106] The oxide semiconductor layer 121 and the oxide semiconductor layer 123 are made of In-M-Zn oxide (M is A In the case of ZnO, Ti, Ga, Y, Zr, Sn, La, Ce, Mg, or Nd, the oxide semiconductor In the target used for depositing the oxide semiconductor layer 121 and the oxide semiconductor layer 123, If the atomic ratio of elements is In:M:Zn=x2:y2:z2, then x2 / y2 <x1 / y1で z2 / y2 is preferably 1 / 3 or more and 6 or less, and more preferably 1 or more and 6 or less. When z2 / y2 is set to 1 or more and 6 or less, the oxide semiconductor layer 121 and the oxide semiconductor The number of atoms of the metal element in the target is preferably 1 / 100, and more preferably 1 / 100, more preferably 1 / 100. Representative examples of the ratio are In:M:Zn=1:3:2, 1:3:4, 1:3:6, 1:3: 8, 1:4:4, 1:4:5, 1:4:6, 1:4:7, 1:4:8, 1:5:5, 1: Examples include 5:6, 1:5:7, 1:5:8, 1:6:8, 1:6:4, 1:9:6, etc.

[0107] The atomic ratios of the oxide semiconductor layer 121 and the oxide semiconductor layer 123 are each determined by adding an error. The atomic ratios listed above may vary by ±40%.

[0108] The oxide semiconductor layer 123 is made of a metal oxide, for example, aluminum oxide (AlOx), Gallium oxide (GaOx), hafnium oxide (HfOx), silicon oxide (SiOx), oxide It can also be replaced with germanium oxide (GeOx) or zirconia (ZrOx). Alternatively, the metal oxide can be provided over the oxide semiconductor layer 123.

[0109] The atomic ratio is not limited to these, and an appropriate atomic ratio may be used depending on the required semiconductor characteristics. Just use the following.

[0110] The oxide semiconductor layer 121 and the oxide semiconductor layer 123 may have the same composition. The oxide semiconductor layer 121 and the oxide semiconductor layer 123 are formed by sputtering. The atomic ratio of the metal elements is In:Ga:Zn=1:3:2, 1:3:4, or 1:4:5. Alternatively, In-Ga-Zn oxide, which is

[0111] Alternatively, the oxide semiconductor layer 121 and the oxide semiconductor layer 123 may have different compositions. For example, The oxide semiconductor layer 121 is formed by sputtering a metal element atom of a target. The oxide semiconductor layer was formed by using In-Ga-Zn oxide with a numerical ratio of In:Ga:Zn=1:3:4. The atomic ratio of the target metal elements is In:Ga:Zn=1:3:2. Ga-Zn oxide may also be used.

[0112] The thicknesses of the oxide semiconductor layer 121, the oxide semiconductor layer 122, and the oxide semiconductor layer 123 are It is preferable that the thickness is 3 nm or more and 100 nm or less, or 3 nm or more and 50 nm or less.

[0113] Here, the thickness of the oxide semiconductor layer 122 is at least as large as that of the oxide semiconductor layer 121. It may be formed thinly, the same thickness, or thickly. For example, an oxide semiconductor When the conductor layer 122 is made thicker, the on-current of the transistor can be increased. The effect of suppressing the generation of interface states in the oxide semiconductor layer 122 is lost. For example, the thickness of the oxide semiconductor layer 122 is 121, more than 1 time, or more than 2 times, or more than 4 times, or 6 times In addition, when it is not necessary to increase the on-state current of a transistor, The thickness of the oxide semiconductor layer 121 may be equal to or greater than the thickness of the oxide semiconductor layer 122. For example, When the insulating layer 110 or the insulating layer 175 contains excess oxygen, the oxygen is removed by heat treatment. As a result, the amount of oxygen vacancies in the oxide semiconductor layer 122 can be reduced. The electrical characteristics of the device can be stabilized.

[0114] In addition, like the oxide semiconductor layer 121, the oxide semiconductor layer 123 is also It is sufficient if the thickness is such that the effect of suppressing the generation of interface states is not lost. For example, The thickness of the oxide semiconductor layer 123 may be equal to or less than that of the conductor layer 121. , the electric field due to the gate electrode layer 160 (or the gate electrode layer 161 or the gate electrode layer 162) Since the oxide semiconductor layer 123 is thin, the oxide semiconductor layer 123 is not easily reached by the heat. For example, the oxide semiconductor layer 123 is preferably formed to have a thickness equal to or larger than the thickness of the oxide semiconductor layer 122. Note that the thickness of the oxide semiconductor layer 123 is not limited to this, and may be any thickness other than the gate insulating layer. Taking into consideration the withstand voltage of the insulating layer 150, the voltage at which the transistor is driven may be appropriately set. stomach.

[0115] The oxide semiconductor layer 121, the oxide semiconductor layer 122, and the oxide semiconductor layer 123, When the compositions of the two materials are different, the interface is observed by scanning transmission electron microscope (STEM). Observation using a transmission electron microscope It may be possible to do this.

[0116] <About hydrogen concentration> The oxide semiconductor layers 121, 122, and 123 include Hydrogen reacts with oxygen that is bonded to metal atoms to form water, and the oxygen is removed from the lattice (or When hydrogen enters the oxygen vacancy, the In some cases, electrons that are rearranged may be produced. Also, some of the hydrogen may bond with oxygen and metal atoms. By bonding, electrons that act as carriers can be generated. Therefore, hydrogen is included A transistor including an oxide semiconductor such as this tends to be normally-on.

[0117] Therefore, the oxide semiconductor layer 121, the oxide semiconductor layer 122, the oxide semiconductor layer 123, and At the interfaces, it is preferable that hydrogen is reduced as much as possible together with oxygen vacancies. For example, the oxide semiconductor layer 121, the oxide semiconductor layer 122, and the oxide semiconductor layer 123 and secondary ion mass spectrometry (SIMS) at each interface. The hydrogen concentration obtained by ion mass spectrometry was 1×10 16 atoms / cm 3 More than 2×10 20 atoms / cm 3 Less than or equal to 1×10 16 atoms / cm 3 5×10 or more 19 atoms / cm 3 Less than or equal to 1× 10 16 atoms / cm 3 More than 1×10 19 atoms / cm 3 The following is more preferable: is 1×10 16 atoms / cm 3 5×10 or more 18 atoms / cm 3The following shall be done: As a result, the transistor 10 has electrical characteristics in which the threshold voltage is positive (no This is also called the "marie-off" characteristic.

[0118] <Carbon and silicon concentrations> In addition, the oxide semiconductor layer 121, the oxide semiconductor layer 122, the oxide semiconductor layer 123, and the When silicon or carbon, which is one of the group 14 elements, is present at the interface between the two materials, oxides form. Oxygen deficiency in the semiconductor layer 121, the oxide semiconductor layer 122, and the oxide semiconductor layer 123 As a result, the oxide semiconductor layer 121 and the oxide semiconductor layer 122 are formed. The oxide semiconductor layer 122, the oxide semiconductor layer 123, and the silicon and carbon at the interfaces between them. For example, the oxide semiconductor layer 121 and the oxide semiconductor layer 1 22, an oxide semiconductor layer 123, an oxide semiconductor layer 124, and S at their interfaces The silicon and carbon concentrations obtained by IMS are 1×10 16 atoms / cm 3 1 more ×10 19 atoms / cm 3 Less than or equal to 1×10 16 atoms / cm 3 Over 5 ×10 18 atoms / cm 3 Less than 1×10, more preferably 16 atoms / cm 3 More than 2×10 18 atoms / cm 3 As a result, the transistor The transistor 10 has electrical characteristics in which the threshold voltage is positive (also called normally-off characteristics). do.

[0119] <About alkali metal concentration> In addition, alkali metals and alkaline earth metals generate carriers when bonded to oxide semiconductors. This may result in an increase in the off-state current of the transistor. The oxide semiconductor layer 121, the oxide semiconductor layer 122, the oxide semiconductor layer 123, and each of the It is preferable to reduce the concentration of alkali metals or alkaline earth metals at the interface. For example, the oxide semiconductor layer 121, the oxide semiconductor layer 122, the oxide semiconductor layer 123, and At each interface, alkali metal or aluminum was detected by secondary ion mass spectrometry. The concentration of potassium earth metals is 1×10 18 atoms / cm 3 Less than or equal to 2 x 10 16 atoms / cm 3 It is preferable that the transistor 10 has a maximum capacitance of 100 Ω or less. The device can have electrical characteristics where the lowest voltage is positive (also called normally-off characteristics). do.

[0120] <Nitrogen concentration> In addition, the oxide semiconductor layer 121, the oxide semiconductor layer 122, the oxide semiconductor layer 123, and the When nitrogen is present at the interface between the two, electrons acting as carriers are generated, increasing the carrier density. As a result, an n-type region is formed. The transistor tends to be normally on. Nitrogen is formed in the organic semiconductor layer 122, the oxide semiconductor layer 123, and the interface between them. For example, the oxide semiconductor layer 121 and the oxide semiconductor layer 1 22, the oxide semiconductor layer 123, and the nitrogen obtained by SIMS at the interface between them. The element concentration is 1×10 15 atoms / cm3 5×10 or more 19 atoms / cm 3 below, Preferably 1 x 10 15 atoms / cm 3 5×10 or more 18 atoms / cm 3 below, More preferably, 1×10 15 atoms / cm 3 More than 1×10 18 atoms / cm 3 Below or less, and more preferably 1×10 15 atoms / cm 3 5×10 or more 17 atoms / c m 3 It is preferable that the threshold voltage of the transistor 10 is set to 0.5 V or less. The device can have electrical characteristics (also called normally-off characteristics) that are suitable for use as a semiconductor device.

[0121] <About carrier density> Impurities in the oxide semiconductor layer 121, the oxide semiconductor layer 122, and the oxide semiconductor layer 123 are removed by By reducing the amount of the oxide semiconductor layer 121, the oxide semiconductor layer 122, and the oxide semiconductor layer Therefore, the carrier density in the oxide semiconductor layer 121 and the oxide semiconductor layer 123 can be reduced. The compound semiconductor layer 122 and the oxide semiconductor layer 123 have a carrier density of 1×10 15 pcs / c m 3 Less than or equal to 1×10 13 pieces / cm 3 Less than 8×10, more preferably 11 pieces / cm 3 less than 1×10 11 pieces / cm 3 less than 1×10 10 pieces / cm 3 Less than 1 x 10 -9 pieces / cm 3 That is all.

[0122] The oxide semiconductor layer 121, the oxide semiconductor layer 122, and the oxide semiconductor layer 123 are each formed of an oxide semiconductor material. By using an oxide semiconductor film with a low impurity concentration and a low density of defect states, it is possible to obtain a more excellent electrical conductivity. In this case, the impurity concentration is low and the defect A low level density (low oxygen vacancy) is called high purity intrinsic or substantially high purity intrinsic. A highly pure intrinsic or substantially highly pure intrinsic oxide semiconductor has a small carrier generation source. Therefore, the carrier density of the oxide semiconductor film can be reduced in some cases. The transistor in which the channel region is formed has electrical characteristics in which the threshold voltage is positive (no Also known as marrow-off characteristics.) Also, high-purity intrinsic or substantially high-purity intrinsic Since the oxide semiconductor film has a low density of defect states, the density of trap states may also be low. In addition, a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film has a low off-state current. The voltage between the source and drain electrodes (drain voltage) is remarkably small, ranging from 1V to 10V. In the range, the off-state current is below the measurement limit of the semiconductor parameter analyzer, that is, 1× 10 -13 Therefore, the oxide semiconductor film has a channel density of 0.1 A or less. The transistors in which the junction region is formed have small fluctuations in electrical characteristics and are highly reliable. This may result in a problem.

[0123] In addition, a transistor using the purified oxide semiconductor film as described above for a channel formation region can be fabricated. The off-state current of the transistor is extremely small. For example, when the voltage between the source and drain is set to 0.1 V, 5 V or approximately 10V, the off-state current normalized by the transistor channel width It is possible to reduce the current density to several yA / μm to several zA / μm.

[0124] The oxide semiconductor layer 121, the oxide semiconductor layer 122, and the oxide semiconductor layer 123 are, for example, The non-single crystal structure may be, for example, CAAC-OS or polycrystalline structure, which will be described later. , microcrystalline, or amorphous structures. In non-single crystal structures, the amorphous structure is the most defect-free. The defect state density is high in CAAC-OS, while the defect state density is the lowest in CAAC-OS.

[0125] The oxide semiconductor layer 121, the oxide semiconductor layer 122, and the oxide semiconductor layer 123 are, for example, The oxide semiconductor layer 121, the oxide semiconductor layer 122, and the The oxide semiconductor layer 123 has microcrystals with a size of, for example, 1 nm or more and less than 10 nm in the film. Alternatively, the oxide film and the oxide semiconductor film having a microcrystalline structure may have an amorphous phase. It has a mixed phase structure with crystal parts of m or more and less than 10 nm.

[0126] The oxide semiconductor layer 121, the oxide semiconductor layer 122, and the oxide semiconductor layer 123 are, for example, The oxide semiconductor layer 121, the oxide semiconductor layer 122, and the oxide semiconductor layer 123 each having an amorphous structure may be used. The oxide semiconductor layer 123 has, for example, a disordered atomic arrangement and does not include a crystalline component. Alternatively, the amorphous oxide film has a completely amorphous structure and does not have any crystalline portion. .

[0127] Note that the oxide semiconductor layer 121, the oxide semiconductor layer 122, and the oxide semiconductor layer 123 are A mixed film having regions of two or more structures, namely CAAC-OS, microcrystalline structure, and amorphous structure. The mixed film may have, for example, an amorphous structure region, a microcrystalline structure region, and a CA A single layer structure having an AC-OS region and an amorphous region. The structure is a layered structure of a region with a crystal structure, a region with a microcrystalline structure, and a region with a CAAC-OS structure.

[0128] Note that the oxide semiconductor layer 121, the oxide semiconductor layer 122, and the oxide semiconductor layer 123 are For example, it may have a single crystal structure.

[0129] The oxide semiconductor film is formed by forming an oxide semiconductor layer 122 in which oxygen vacancies are less likely to occur than in the oxide semiconductor layer 122. By providing the insulating film 122 above and below the oxide semiconductor layer 122, oxygen vacancies in the oxide semiconductor layer 122 can be reduced. In addition, the oxide semiconductor layer 122 can be formed by using a metal element. The oxide semiconductor layer 121 and the oxide semiconductor layer 123 each have one or more elements. The interface between the semiconductor layer 121 and the oxide semiconductor layer 122, The interface state density at the interface with the insulating layer 123 is extremely low. After the heating, heat treatment is performed to transfer the oxygen to the oxide semiconductor layer 121. Oxygen moves to the layer 122, but at this time, oxygen is not easily captured by the interface state, and the efficiency is improved. It is possible to move oxygen contained in the oxide semiconductor layer 121 to the oxide semiconductor layer 122. As a result, oxygen vacancies in the oxide semiconductor layer 122 can be reduced. In addition, oxygen is added to the oxide semiconductor layer 121. In other words, the localized oxygen vacancies in at least the oxide semiconductor layer 122 can be reduced. The position density can be reduced.

[0130] In addition, the oxide semiconductor layer 122 may be formed of an insulating film having a different constituent element (e.g., a silicon oxide film). When the semiconductor layer contacts the gate insulating layer, an interface state is formed, and the interface state forms a channel. In such a case, a second transistor with a different threshold voltage appears, However, the apparent threshold voltage of the oxide semiconductor The oxide semiconductor layer 121 and the oxide semiconductor layer 122 each containing one or more metal elements Since the oxide semiconductor layer 123 is in contact with the oxide semiconductor layer 122, the oxide semiconductor layer 121 and the oxide semiconductor layer 1 The interface between the oxide semiconductor layer 123 and the oxide semiconductor layer 122 is formed with an interface state. It becomes more difficult to achieve.

[0131] The oxide semiconductor layer 121 and the oxide semiconductor layer 123 are formed on the insulating layer 110 and the gate The constituent elements of the insulating layer 150 are mixed into the oxide semiconductor layer 122, and an impurity level is formed. It also functions as a barrier film to prevent the material from being damaged.

[0132] For example, the insulating layer 110 or the gate insulating layer 150 may be an insulating film containing silicon. In this case, the silicon in the gate insulating layer 150 or the insulating layer 110 and the gate insulating layer 150 Carbon that may be mixed into the oxide semiconductor layer 121 or the oxide semiconductor layer 123 is introduced into the interface. Impurities such as silicon and carbon may be mixed into the oxide semiconductor layer 1 to a thickness of several nm. When the electron enters the n-type nucleus, it forms an impurity level, which acts as a donor and generates an electron. It can become stylized.

[0133] However, when the thickness of the oxide semiconductor layer 121 and the oxide semiconductor layer 123 is larger than several nm, If the impurities are not mixed in, such as silicon and carbon, they will not reach the oxide semiconductor layer 122. Therefore, the influence of the impurity level is reduced.

[0134] Therefore, by providing the oxide semiconductor layer 121 and the oxide semiconductor layer 123, This can reduce variations in the electrical characteristics of the transistors, such as their threshold voltages.

[0135] In addition, the gate insulating layer 150 and the oxide semiconductor layer 122 come into contact with each other, and a channel is formed at the interface. If the interface is too thin, interfacial scattering occurs at the interface, lowering the field effect mobility of the transistor. However, the oxide semiconductor layer 122 includes one or more metal elements. 21, since the oxide semiconductor layer 123 is provided in contact with the oxide semiconductor layer 122, At the interfaces between the conductor layer 122 and the oxide semiconductor layer 121 and between the conductor layer 122 and the oxide semiconductor layer 123, carriers are scattered. Disorder is less likely to occur, and the field effect mobility of the transistor can be increased.

[0136] In this embodiment, the amount of oxygen vacancies in the oxide semiconductor layer 122 and the oxide semiconductor layer The amount of oxygen vacancies in the oxide semiconductor layer 121 and the oxide semiconductor layer 123 in contact with the oxide semiconductor layer 122 is reduced. As a result, the density of localized states in the oxide semiconductor layer 122 can be reduced. As a result, the transistor 10 described in this embodiment has little fluctuation in threshold voltage and high reliability. In addition, the transistor 10 described in this embodiment has excellent electrical characteristics. Has characteristics.

[0137] Note that an insulating film containing silicon is often used as a gate insulating layer of a transistor. For the above reasons, the region serving as a channel of the oxide semiconductor layer is It can be said that a structure that does not contact the gate insulating layer like a gate MOSFET is preferable. When a channel is formed at the interface between the insulating layer and the oxide semiconductor layer, carrier scattering occurs at the interface. This can cause a decrease in the field effect mobility of the transistor. It is preferable that the region of the oxide semiconductor layer that serves as a channel is separated from the gate insulating layer. .

[0138] Therefore, the oxide semiconductor layer 120 is made of the oxide semiconductor layer 121, the oxide semiconductor layer 122, and the oxide By using a stacked structure of the oxide semiconductor layer 123, a channel can be formed in the oxide semiconductor layer 123. This allows the formation of a transistor with high field-effect mobility and stable electrical characteristics. It is possible.

[0139] The oxide semiconductor does not necessarily have to be a three-layer structure, but may be a single layer, two layers, four layers, or even five layers. In the case of using a single layer, the oxide semiconductor layer 122 shown in this embodiment may be used. It is sufficient to use a layer corresponding to the above.

[0140] <Band diagram> Here, a band diagram will be described. In the band diagram, the insulating layer 110, An oxide semiconductor layer 121, an oxide semiconductor layer 122, an oxide semiconductor layer 123, and a gate insulator The energy (Ec) of the conduction band edge of the edge layer 150 is shown.

[0141] As shown in FIG. 4(A) and FIG. 4(B), an oxide semiconductor layer 121, an oxide semiconductor layer 122, In the oxide semiconductor layer 123, the energy of the conduction band minimum changes continuously. The elements constituting the oxide semiconductor layer 121, the oxide semiconductor layer 122, and the oxide semiconductor layer 123 are This is also understood from the fact that oxygen easily diffuses between them due to their commonality. The oxide semiconductor layer 121, the oxide semiconductor layer 122, and the oxide semiconductor layer 123 are stacked layers of films having different compositions. Although it is a layered structure, it can also be said to be physically continuous.

[0142] The oxide semiconductor film, which is laminated with a common main component, is not simply laminated but is continuously joined. In this case, the energy of the conduction band edge changes continuously between layers. In other words, the interface between each layer is fabricated so that a U-shaped well structure is formed. There are no impurities that can form defect levels such as trap centers or recombination centers in the If impurities are present between the layers of the laminated multi-layer film, The continuity of the energy band is lost, and carriers disappear at the interface due to trapping or recombination. It ends up like this.

[0143] Note that in FIG. 4B, the oxide semiconductor layer 121 and the oxide semiconductor layer 123 have the same Ec. Although certain cases are shown, they may be different.

[0144] As shown in FIG. 4B and FIG. 4C, the oxide semiconductor layer 122 serves as a well, and In the case of the gate electrode 10, it can be seen that a channel is formed in the oxide semiconductor layer 122. A U-shaped well in which the energy of the conduction band minimum changes continuously from the oxide semiconductor layer 122 at its bottom. The channel of the door structure may also be called a recessed channel.

[0145] The oxide semiconductor layer 121 and the oxide semiconductor layer 123 are formed of an insulating film such as a silicon oxide film. In the vicinity of the interface with the film, trap levels due to impurities or defects can be formed. The oxide semiconductor layer 122 and the oxide semiconductor layer 123 are formed on the oxide semiconductor layer 121 and the oxide semiconductor layer 123. However, the oxide semiconductor layer 121 or the oxide semiconductor When the energy difference between Ec of the oxide semiconductor layer 123 and Ec of the oxide semiconductor layer 122 is small, Electrons in the compound semiconductor layer 122 may exceed the energy difference and reach the trap level. When electrons that become negative charges are captured by the trap level, negative charges form at the interface of the insulating film. A constant charge is generated, and the threshold voltage of the transistor is shifted in the positive direction. During long-term storage tests of transistors, traps are not fixed, causing fluctuations in characteristics. There are concerns.

[0146] Therefore, in order to reduce the fluctuation in the threshold voltage of the transistor, the oxide semiconductor layer 121 and an energy difference between Ec of the oxide semiconductor layer 123 and the oxide semiconductor layer 122. The energy difference between the two is preferably 0.1 eV or more. More preferably, it is 0.2 eV or more.

[0147] Note that the oxide semiconductor layers 121, 122, and 123 each have a crystal structure. In particular, the use of crystals oriented along the c-axis provides a stable transistor. It is possible to impart the desired electrical properties.

[0148] In addition, in the band diagram shown in FIG. 4B, the oxide semiconductor layer 123 is not provided. Between the compound semiconductor layer 123 and the gate insulating layer 150, an In-Ga oxide (for example, Alternatively, gallium oxide may be used. In addition, when the oxide semiconductor layer 123 is provided, the oxide semiconductor layer 123 and the gate Alternatively, gallium oxide may be provided between the insulating layers 150. This is also fine.

[0149] The oxide semiconductor layer 122 has a higher electrical conductivity than the oxide semiconductor layer 121 and the oxide semiconductor layer 123. For example, an oxide semiconductor having a high electron affinity is used as the oxide semiconductor layer 122. The oxide semiconductor layer 121 and the oxide semiconductor layer 123 have an electron affinity of 0.07 eV or more and 1.3 eV or less. Preferably, the voltage is 0.1 eV or more and 0.7 eV or less, and more preferably, the voltage is 0.2 eV or more and 0.4 eV or less. Oxides with a molecular weight of 100 eV or less can be used.

[0150] The transistor described in this embodiment includes one or more metal elements included in the oxide semiconductor layer 122. Since the oxide semiconductor layer 121 and the oxide semiconductor layer 123 are included, The interface between the conductor layer 121 and the oxide semiconductor layer 122 and the interface between the oxide semiconductor layer 123 and the oxide semiconductor layer The interface state is unlikely to be formed at the interface with the conductor layer 122. By providing the nitride semiconductor layer 123, the electrical characteristics of the transistor, such as the threshold voltage, can be controlled. Variability and fluctuation can be reduced.

[0151] Source Electrode Layer 130, Drain Electrode Layer 140 The source electrode layer 130 and the drain electrode layer 140 are made of copper (Cu), tungsten (W), molybdenum (Mo), and the like. Ribide (Mo), Gold (Au), Aluminum (Al), Manganese (Mn), Titanium (T i), Tantalum (Ta), Nickel (Ni), Chromium (Cr), Lead (Pb), Tin (Sn) , Iron (Fe), Cobalt (Co), Ruthenium (Ru), Platinum (Pt), Iridium (I r), strontium (Sr), or alloys, or materials that mainly consist of these. A single layer or a laminate of a conductive layer containing compounds such as oxygen, nitrogen, fluorine, silicon, etc. For example, in the case of stacking, the lower side in contact with the oxide semiconductor layer 122 The conductive layers (for example, the source electrode layer 131 and the drain electrode layer 141 shown in FIG. 15) are The upper conductive layer (e.g., the source electrode layer 132 shown in FIG. 15, the drain electrode layer 133) has a material that is easy to bond to the The rain electrode layer 142) may be made of a material that is highly resistant to oxidation. It is preferable to use a high melting point material such as tungsten or molybdenum, which has both electrical and mechanical properties. It is also preferable to form the insulating layer from a low-resistance conductive material such as aluminum or copper. When a manganese-Mn alloy is used, manganese oxide is formed at the interface with the insulator containing oxygen, and the manganese oxide Since tantalum has a function of suppressing the diffusion of Cu, it is preferable.

[0152] In addition, when a conductive material that easily bonds with oxygen is brought into contact with an oxide semiconductor layer, The oxygen in the oxide semiconductor layer diffuses to the conductive material side, which is more likely to bond with oxygen. Oxygen vacancies occur in the area near the source electrode layer or the drain electrode layer, and a small amount of oxygen is The hydrogen contained in the region enters the oxygen vacancy, causing the region to become significantly n-type. Therefore, the n-type region can function as the source or drain of a transistor. This can be done.

[0153] For example, a laminated structure using W as the lower conductive layer and Pt as the upper conductive layer may be used. By this, the oxide semiconductor in contact becomes an n-type, and the conductive layer in contact with the insulating layer 170 becomes a conductive layer. This can suppress oxidation of the conductive layer.

[0154] Gate insulating layer 150 The gate insulating layer 150 contains oxygen (O), nitrogen (N), fluorine (F), aluminum (Al ), magnesium (Mg), silicon (Si), gallium (Ga), germanium (Ge ), Yttrium (Y), Zirconium (Zr), Lanthanum (La), Neodymium (Nd) , hafnium (Hf), tantalum (Ta), titanium (Ti), and the like. For example, aluminum oxide (AlOx), magnesium oxide (MgOx), silicon oxide (SiOx), silicon oxynitride (SiOxNy), silicon oxide nitride (SiNxOy) , silicon nitride (SiNx), gallium oxide (GaOx), germanium oxide (GeOx ), yttrium oxide (YOx), zirconium oxide (ZrOx), lanthanum oxide (La Ox), neodymium oxide (NdOx), hafnium oxide (HfOx) and tantalum oxide ( The gate insulating layer 150 may be an insulating film containing one or more of TaOx. The gate insulating layer 150 may be a laminate of the above materials. It may contain impurities such as zirconium (Zr).

[0155] Next, an example of a laminated structure of the gate insulating layer 150 will be described. The gate insulating layer 150 is For example, it contains oxygen, nitrogen, silicon, hafnium, etc. Specifically, hafnium oxide and preferably includes silicon oxide or silicon oxynitride.

[0156] Hafnium oxide has a higher dielectric constant than silicon oxide and silicon oxynitride. Since the physical thickness can be made larger than the equivalent oxide thickness, the equivalent oxide thickness can be made 10 nm or less. Even if the thickness is reduced to 5 nm or less, the leakage current due to the tunnel current can be reduced. In other words, a transistor with a small off-state current can be realized. Hafnium oxide having an amorphous structure has a higher dielectric constant than hafnium oxide having an amorphous structure. Therefore, in order to obtain a transistor with a small off-state current, It is preferable to use hafnium oxide, which has a crystal structure such as monoclinic or cubic. However, one embodiment of the present invention is not limited to these.

[0157] By the way, the surface on which hafnium oxide having a crystalline structure is formed has interface states due to defects. The interface states may function as trap centers. When hafnium oxide is placed adjacent to the channel region of a transistor, the interface states This may cause degradation of the electrical characteristics of the transistor. To achieve this, another film is placed between the channel region of the transistor and the hafnium oxide. It may be preferable to separate the membranes from each other by using a The film having the buffer function may be a film included in the gate insulating layer 150, or may be an oxide semiconductor. The film may be a film included in the conductor film. That is, the film having a buffer function may be silicon oxide. Silicon oxynitride, an oxide semiconductor, or the like can be used. The film may include a semiconductor having a larger energy gap than the semiconductor that is to be the channel region. Alternatively, an insulator is used. Alternatively, the film having a buffer function may be, for example, a material that is a channel region. Use a semiconductor or insulator that has a smaller electron affinity than the semiconductor that is being used. The film to be formed may be a semiconductor having a higher ionization energy than the semiconductor in the channel region. Conductors or insulators are used.

[0158] On the other hand, the interface states (trap By trapping charge in the charge center, it may be possible to control the threshold voltage of a transistor. In order to make the charge exist stably, for example, the channel region and hafnium oxide If an insulator with a larger energy gap than hafnium oxide is placed between the hafnium Alternatively, if a semiconductor or insulator with a smaller electron affinity than hafnium oxide is placed, Alternatively, the film with a buffer function may have a higher ionization energy than hafnium oxide. By using such an insulator, the interface state This makes it difficult for the trapped charge to be released, and the charge can be retained for a long period of time. can.

[0159] Examples of such insulators include silicon oxide and silicon oxynitride. In order to trap charges at the interface state in the gate insulating layer 150, the gate potential must be increased from the oxide semiconductor film. Electrons can be moved toward the pole layer 160. As a specific example, a high temperature (e.g. 125°C to 450°C, typically 150°C to 300°C) The potential of the electrode layer 160 is set higher than the potential of the source electrode layer 130 and the drain electrode layer 140. It is sufficient to maintain the state for at least one second, typically at least one minute.

[0160] In this way, a transistor is formed in which a desired amount of electrons are trapped in the interface state of the gate insulating layer 150, etc. The threshold voltage of the gate electrode layer 160 and the voltage applied to the gate electrode layer 160 are shifted to the positive side. By adjusting the time for which the gate is turned on, the amount of electrons captured (the amount of change in the threshold voltage) can be controlled. If the charge can be trapped, it can be trapped in the gate insulating layer 150. A laminated film having a similar structure may be used for the other insulating layers.

[0161] <Gate electrode layer 160> The gate electrode layer 160 may include, for example, aluminum (Al), titanium (Ti), chromium (C r), cobalt (Co), nickel (Ni), copper (Cu), yttrium (Y), zirconium (ZrO2) Zr, Molybdenum (Mo), Ruthenium (Ru), Silver (Ag), Tantalum (T A conductive film such as a tungsten (W) film and the like can be used. The electrode layer 160 can be a laminate. For example, the gate electrode layer 160 can be a multilayer structure as shown in FIG. The gate electrode layer 2 may be made of the above-mentioned material, and the gate electrode layer 161 and the gate electrode layer 163 may be made of the above-mentioned material. Alternatively, a conductive film containing nitrogen, such as a nitride of a material, may be used.

[0162] Insulating layer 170 The insulating layer 170 may contain oxygen (O), nitrogen (N), fluorine (F), aluminum (Al), ma, and the like. Magnesium (Mg), Silicon (Si), Gallium (Ga), Germanium (Ge), In Tritium (Y), Zirconium (Zr), Lanthanum (La), Neodymium (Nd), Hafnium (Hf) For example, the metals may include hafnium (Hf), tantalum (Ta), titanium (Ti), etc. , Aluminum oxide (AlOx), Magnesium oxide (MgOx), Silicon oxide (Si Ox), silicon oxide nitride (SiOxNy), silicon oxide nitride (SiNxOy), nitride Silicon (SiNx), Gallium oxide (GaOx), Germanium oxide (GeOx), Acid Yttrium oxide (YOx), zirconium oxide (ZrOx), lanthanum oxide (LaOx) , neodymium oxide (NdOx), hafnium oxide (HfOx) and tantalum oxide (TaO The insulating layer 170 may be a laminate of the above materials. may be also possible.

[0163] The insulating layer 170 preferably includes an aluminum oxide film. The aluminum oxide film is Has a barrier effect that prevents impurities such as hydrogen and moisture, as well as oxygen, from passing through the membrane Therefore, the aluminum oxide film can be used during and after the manufacturing process of the transistor. After manufacturing, the oxidation of impurities such as hydrogen and moisture, which are factors that cause fluctuations in the electrical characteristics of transistors, Preventing contamination of the oxide semiconductor layer 121 and the oxide semiconductor layer 122; Preventing emission from the semiconductor layer 121 and the oxide semiconductor layer 122, and eliminating the need for oxygen from the insulating layer 110 It is suitable for use as a protective film having an important emission prevention effect.

[0164] In addition, the insulating layer 170 is preferably a film having an oxygen supplying ability. When the second insulating film is formed, a mixed layer is formed, and the mixed layer or the insulating layer 110 is oxidized. The oxygen diffuses into the oxide semiconductor by the subsequent heat treatment, and the oxide semiconductor is formed. It can replenish oxygen to oxygen deficiencies in the body, improving transistor characteristics (e.g., threshold voltage). , reliability, etc.) can be improved.

[0165] In addition, another insulating layer may be provided above or below the insulating layer 170. For example, an oxide Magnesium, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, oxide Gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, An insulating film containing one or more of neodymium oxide, hafnium oxide, and tantalum oxide may be used. Oxygen (O), nitrogen (N), fluorine (F), aluminum (Al), magnesium (Mg), Silicon (Si), Gallium (Ga), Germanium (Ge), Yttrium (Y), zirconium (Zr), lanthanum (La), neodymium (Nd), hafnium (H f), tantalum (Ta), titanium (Ti), etc. For example, aluminum oxide Aluminum oxide (AlOx), magnesium oxide (MgOx), silicon oxide (SiOx), Silicon oxide nitride (SiOxNy), silicon oxide nitride (SiNxOy), silicon nitride ( SiNx), gallium oxide (GaOx), germanium oxide (GeOx), yttrium oxide Umium oxide (YOx), zirconium oxide (ZrOx), lanthanum oxide (LaOx), neodymium oxide NdOx, hafnium oxide (HfOx) and tantalum oxide (TaOx) The insulating layer 170 may be a laminate of the above materials. It is preferable that the insulating layer 170 has more oxygen than the stoichiometric composition. Oxygen released from the edge layer passes through the gate insulating layer 150 and enters the channel of the oxide semiconductor layer 120. Since the oxygen vacancies formed in the channel formation region can be diffused into the hole formation region, Therefore, it is possible to obtain stable electrical characteristics of the transistor. This can be done.

[0166] Insulating layer 175 The insulating layer 175 contains oxygen (O), nitrogen (N), fluorine (F), aluminum (Al), ma, and Magnesium (Mg), Silicon (Si), Gallium (Ga), Germanium (Ge), In Tritium (Y), Zirconium (Zr), Lanthanum (La), Neodymium (Nd), Hafnium (Hf) For example, the metals may include hafnium (Hf), tantalum (Ta), titanium (Ti), etc. , magnesium oxide (MgOx), silicon oxide (SiOx), silicon oxynitride (Si OxNx), silicon oxynitride (SiNxOx), silicon nitride (SiNx), gallium oxide yttrium oxide (YOx), germanium oxide (GaOx), germanium oxide (GeOx), yttrium oxide (YOx), Zirconium (ZrOx), lanthanum oxide (LaOx), neodymium oxide (NdOx), acid Hafnium oxide (HfOx), tantalum oxide (TaOx), aluminum oxide (AlO The insulating layer 175 may be a laminate of the above materials. The insulating layer preferably has more oxygen than the stoichiometric composition. .

[0167] Alternatively, the insulating layer 175 may be made of a material with a low dielectric constant (Low-k material). Silicon oxide (SiOF) containing a few percent of fluorine (F), and silicon oxide (SiOF) containing a few percent of carbon (C) Silicon oxide (SiOC), fluorinated silicate glass (FSG), organic silicate glass (OSG), Hydrogenated Silsesquioxane (HSQ), Methyl Silsesquioxane (M SQ), organic polymers, polyimides, fluororesins (polytetrafluoroethylene, etc.), The insulating layer 175 can be formed using amorphous carbon to which fluorine is added. In addition, the capacitance associated with the transistor 10 can be further reduced by using low-k materials. can be done.

[0168] <Transistor manufacturing method> Next, a method for manufacturing the semiconductor device according to the present embodiment will be described with reference to FIGS. Note that the parts that overlap with those described in the above transistor configuration will be omitted. The A1-A2 direction shown in FIG. 7 to FIG. 13 corresponds to the channel shown in FIG. 1(A) and FIG. 1(B). The A3-A4 direction shown in FIG. 7 to FIG. 13 is also referred to as the A3-A4 direction. ) and the channel width direction shown in FIG. 1(C).

[0169] In this embodiment, each layer constituting a transistor (insulating layer, oxide semiconductor layer, conductive layer The deposition methods include sputtering, chemical vapor deposition (CVD), vacuum deposition, and pulsed laser deposition. It can be formed by using a PLD method. Alternatively, it can be formed by a coating method or a printing method. The deposition method includes sputtering, plasma enhanced chemical vapor deposition (PECVD), A typical example of the thermal CVD method is MOCVD (organic chemical vapor deposition). Metal Chemical Vapor Deposition (ALD) and ALD (Atomic Layer Deposition) methods may also be used.

[0170] <Thermal CVD method> Thermal CVD is a film formation method that does not use plasma, so defects can occur due to plasma damage. This has the advantage that the

[0171] In the thermal CVD method, the source gas and the oxidizing agent are fed into the chamber at the same time, and the inside of the chamber is By reacting near or on the substrate under atmospheric or reduced pressure, the material is deposited on the substrate. Film formation may also be performed.

[0172] In addition, the thermal CVD method such as the MOCVD method or the ALD method may be used in the above-described embodiments. It is possible to form various films such as metal films, semiconductor films, and inorganic insulating films. For example, In When forming a -Ga-Zn-O film, trimethylindium, trimethylgallium, and dimethyl zinc can be used. The chemical formula for trimethylindium is I The chemical formula for trimethylgallium is Ga(CH3)3. 。 Also, the chemical formula of dimethylzinc is Zn(CH3)2. Also, these combinations are not limited to this, and triethylgallium (chemical formula Ga(C2H5 )3) can be used instead of trimethylgallium, and diethylzinc (chemical formula Zn(C2H5 )2) can be used instead of dimethylzinc.

[0173] <ALD method> In a film-forming apparatus using a conventional CVD method, during film formation, one or more kinds of raw material gases (precursors) for the reaction are simultaneously supplied into the chamber. In a film-forming apparatus using the ALD method, the precursors for the reaction are sequentially introduced into the chamber, and film formation is performed by repeating the order of gas introduction. For example, by switching each switching valve (also called a high-speed valve), two or more kinds of precursors are sequentially supplied into the chamber, and an inert gas (such as argon or nitrogen) is introduced after the first precursor so that the plurality of kinds of precursors do not mix, and then the second precursor is introduced. Also, instead of introducing an inert gas, after exhausting the first precursor by vacuum evacuation, the second precursor can be introduced.

[0174] Figures 5(A), (B), (C), and (D) show the film-forming process of the ALD method. The first precursor 6 01 is adsorbed on the surface of the substrate (see Fig. 5(A)), and the first single layer is formed (see Fig. 5(B )). At this time, metal atoms and the like contained in the precursor can combine with hydroxyl groups present on the substrate surface. The metal atoms may have alkyl groups such as methyl groups and ethyl groups bonded thereto. After exhausting the first precursor 601, the second precursor 602 introduced reacts with it (see Fig. 5(C)), and the second single layer is laminated on the first single layer to form a thin film. (See FIG. 5(D)). For example, if an oxidizing agent is included as the second precursor, a metal atom or an alkyl group bonded to a metal atom present in the first precursor; and an oxidizing agent A chemical reaction occurs between the first precursor and the second precursor, forming an oxide film. If a gas containing hydrogen is used, a metal film can be formed by a reduction reaction.

[0175] The ALD method is a film formation method based on surface chemical reactions, in which precursors are adsorbed onto the film surface, A self-limiting mechanism is in place, allowing the formation of more. For example, trimethylaluminum Such precursors react with the hydroxyl groups (OH groups) present on the surface of the film to be formed. Since only surface reactions occur due to the precursor coming into contact with the target surface and transferring thermal energy, Metal atoms in the precursor can be adsorbed on the surface to be film-formed through the precursor. Casa has a high vapor pressure, is thermally stable before deposition, does not self-decompose, and is highly soluble in water. It has the characteristics of rapid chemical adsorption. In addition, the precursor is introduced as a gas, so the exchange rate is low. If the precursors introduced into each other have enough time to diffuse, high aspect ratios can be achieved. Even in an area having irregularities, a film can be formed with good coverage.

[0176] In addition, in the ALD method, the gas introduction order is controlled and repeated multiple times until the desired thickness is achieved. By repeating the process, a thin film with excellent step coverage can be formed. The thickness can be precisely adjusted by changing the number of times the nozzle is turned on. By increasing the pressure, the deposition rate can be increased and the impurity concentration in the film can be reduced. can be done.

[0177] In addition, there are two types of ALD: ALD using heat (thermal ALD) and ALD using plasma ( In the thermal ALD method, thermal energy is used to induce the reaction of the precursor. In the plasma ALD method, the precursor reaction is carried out in the radical state. do.

[0178] The ALD method can deposit extremely thin films with high precision. Surface coating can be achieved even on uneven surfaces. The rate is high and the film density is high.

[0179] <Plasma ALD> In addition, by forming a film using the plasma ALD method, compared to the ALD method using heat (thermal ALD method), The plasma ALD method can form films at temperatures even lower than 100°C. The deposition rate can be maintained without decreasing. Because the plasma can generate radicals, it is possible to form films of not only oxides but also nitrides. can be done.

[0180] In addition, plasma ALD can enhance the oxidizing power of the oxidizing agent. When forming a film, the precursor remaining in the film or the organic compound desorbed from the precursor It is possible to reduce carbon, chlorine, hydrogen, etc. in the film, and impurities It is possible to have a film with a low concentration of

[0181] In addition, when performing plasma ALD, radical species are generated and ICP (Inductively Coupled Plasma) Plasma is generated when the substrate is separated from the plasma, such as Very Coupled Plasma. It is also possible to generate plasma damage to the substrate or the film on which the protective film is formed. This can reduce the page size.

[0182] From the above, by using the plasma ALD method, the process temperature can be lowered compared to other film-forming methods, and the surface coverage rate can be increased, and the film can be formed. This can suppress the intrusion of water and hydrogen from the outside. Therefore, the reliability of transistor characteristics can be improved.

[0183] <Explanation of the ALD apparatus> Fig. 6(A) shows an example of a film-forming apparatus using the ALD method. The film-forming apparatus using the ALD method includes a film-forming chamber (chamber 1701), a raw material supply unit 1711a, a raw material supply unit 1711b, high-speed valves 1712a and 1712b which are flow controllers, a raw material inlet 1713 a, a raw material inlet 1713b, a raw material outlet 1714, and an exhaust device 1715. The raw material inlets 1713a and 1713b installed in the chamber 1701 are connected to the raw material supply units 1711a and 1711b respectively via supply pipes and valves, and the raw material outlet 1714 is connected to the exhaust device 1715 via a discharge pipe, a valve, and a pressure regulator.

[0184] Inside the chamber, there is a substrate holder 1716 equipped with a heater, and the film-forming substrate 1700 is placed on the substrate holder.

[0185] In the raw material supply units 1711a and 1711b, raw material gas is formed from solid raw materials or liquid raw materials by means of vaporizers and heating means. Alternatively, the raw material supply units 1711a and 1711b may be configured to supply gaseous raw material gas.

[0186] Also, an example of providing two raw material supply units 1711a and 1711b is shown, but There is no particular limitation, and three or more valves may be provided. 12b can be precisely controlled by time and supplies either the source gas or the inert gas. The high-speed valves 1712a and 1712b are flow rate controllers for the source gas. It can also be said to be a flow rate controller for inert gas.

[0187] In the film formation apparatus shown in FIG. 6A, a film formation substrate 1700 is carried onto a substrate holder 1716. After the chamber 1701 is sealed, the substrate holder 1716 is heated by a heater to form a film. The substrate 1700 is heated to a desired temperature (for example, 100° C. or higher or 150° C. or higher), and a source gas supply of inert gas, exhaust by exhaust device 1715, and exhaust by exhaust device 1715. By repeating this process, a thin film is formed on the surface of the substrate.

[0188] In the film forming apparatus shown in FIG. 6(A), the raw material supply units 1711a and 1711b are provided with By appropriately selecting the raw materials (volatile organometallic compounds, etc.), One selected from aluminum (Al), tantalum (Ta), zirconium (Zr), etc. Depositing an insulating layer containing an oxide (including a composite oxide) containing the above elements. Specifically, an insulating layer containing hafnium oxide and an insulating layer containing aluminum oxide can be formed. an insulating layer including hafnium silicate; In addition, the insulating layer containing tungsten silicate can be formed. The raw materials (volatile organometallic compounds, etc.) are provided in the raw material supply unit 1711a and raw material supply unit 1711b. By appropriately selecting the layer, a metal layer such as a tungsten layer or a titanium layer, or a titanium nitride layer, etc. It is also possible to deposit thin films such as nitride layers.

[0189] For example, when a hafnium oxide layer is formed using a deposition apparatus that uses the ALD method, a solvent and liquids containing hafnium precursor compounds (hafnium alkoxides, tetrakisdimethyl The raw material gas is made by vaporizing hafnium amide (such as TDMAH) and acid. In this case, two types of gases are used: The first source gas supplied from the source supply unit 1711b is TDMAH, and the second source gas supplied from the source supply unit 1711c is TDMAH. The raw gas becomes ozone. The chemical formula for tetrakisdimethylamidohafnium is Hf [N(CH3)2]4. Other materials include tetrakis(ethylmethylamine). Nitrogen has the function of eliminating the charge trapping level. Therefore, by including nitrogen in the source gas, a hafnium oxide film having a low charge trap level density can be formed. It is possible.

[0190] For example, when forming an aluminum oxide layer using a deposition apparatus that uses the ALD method, A liquid containing a catalyst and an aluminum precursor compound (such as TMA) is vaporized into a raw gas, and the oxidizer is In this case, two types of gases are used, one for the reagent and the other for H2O. The first source gas is TMA, and the second source gas supplied from the source supply unit 1711b is H 2O. The chemical formula for trimethylaluminum is Al(CH3)3. Other liquid materials include tris(dimethylamido)aluminum and triisobutylaluminum. Aluminum, aluminum tris(2,2,6,6-tetramethyl-3,5-heptanedione) Examples include

[0191] For example, when forming a silicon oxide film using a deposition system that uses ALD, The chlorine contained in the adsorbed material is removed, and the oxidizing gas (O2 , nitrous oxide) radicals are supplied to react with the adsorbate.

[0192] For example, when forming a tungsten film using a deposition system that uses ALD, WF6 gas is used. The initial tungsten film is formed by repeatedly introducing B2H6 gas and WF6 Gas and H2 gas are introduced simultaneously to form a tungsten film. Note that instead of B2H6 gas, Alternatively, SiH4 gas may be used.

[0193] For example, an oxide semiconductor film, such as In-Ga-Zn-O, can be formed by a film formation apparatus using ALD. When forming a film, In(CH3)3 gas and O3 gas are introduced in sequence and repeatedly to form an In- Then, Ga(CH3)3 gas and O3 gas are introduced simultaneously to form a GaO layer. Then, Zn(CH3)2 and O3 gas are introduced simultaneously to form a ZnO layer. The order of these layers is not limited to this example. Also, by mixing these gases, In-Ga-O Alternatively, a mixed compound layer such as an In-Zn-O layer or a Ga-Zn-O layer may be formed. Instead of O3 gas, H2O gas obtained by bubbling with an inert gas such as Ar may be used. However, it is preferable to use O3 gas that does not contain H. Also, instead of In(CH3)3 gas, Alternatively, In(C2H5)3 gas may be used instead of Ga(CH3)3 gas. Alternatively, a(C2H5)3 gas may be used. Also, Zn(CH3)2 gas may be used.

[0194] <Multi-chamber deposition equipment> Also, a multi-chamber manufacturing apparatus having at least one film forming apparatus shown in FIG. An example is shown in Figure 6(B).

[0195] The manufacturing equipment shown in FIG. 6(B) can continuously form a laminated film without exposing it to the air. The aim is to prevent impurities from being mixed in and improve throughput.

[0196] The manufacturing apparatus shown in FIG. 6(B) includes a load chamber 1702, a transfer chamber 1720, a pretreatment chamber 1703, The apparatus includes at least a chamber 1701, which is a film-forming chamber, and an unloading chamber 1706. The chambers of the manufacturing equipment (including the load chamber, processing chamber, transfer chamber, deposition chamber, unload chamber, etc.) In order to prevent moisture from adhering, the container is filled with an inert gas (such as nitrogen gas) with a controlled dew point. It is preferable to keep the pressure reduced, and desirably maintain the reduced pressure.

[0197] Additionally, chambers 1704 and 1705 utilize the same ALD method as chamber 1701. It may be a film forming apparatus, a film forming apparatus using a plasma CVD method, or a sp The deposition apparatus may be a deposition apparatus using a deposition method, or a metal organic chemical vapor deposition (MOCVD) method. Organic Chemical Vapor Deposition (TCCVD) method The deposition apparatus may be a deposition apparatus that uses the same.

[0198] For example, the chamber 1704 may be a film forming device that uses a plasma CVD method. The following is an example of a deposition system using the MOCVD method to deposit a multilayer film. show.

[0199] In FIG. 6B, the top view of the transfer chamber 1720 is shown as an example of a hexagon. If necessary, a manufacturing device having a polygonal shape or more and connected to more chambers may be used. In addition, in FIG. 6B, the top surface shape of the substrate is shown as a rectangle, but this is not particularly limited. Although FIG. 6B shows an example of a single-wafer type, a batch type deposition method in which a film is deposited on multiple substrates at once may also be used. It may also be a device.

[0200] <Formation of Insulating Layer 110> First, the insulating layer 110 is formed on the substrate 100. The insulating layer 110 is formed by a plasma CVD method, a thermal For example, aluminum oxide is deposited by CVD (MOCVD, ALD) or sputtering. nium, magnesium oxide, silicon oxide, silicon oxynitride, gallium oxide, gallium oxide Al, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, halide oxide Oxide insulating films such as tantalum oxide and tantalum oxide, silicon nitride, silicon nitride oxide, and nitride aluminium oxide, aluminium nitride, or a mixture of these materials. Alternatively, the above-mentioned materials may be laminated, and at least one of them may be formed by oxidizing the film. The upper layer of the stack that is in contact with the first oxide semiconductor film that becomes the oxide semiconductor layer 121 is the oxide semiconductor layer 1 It is preferable that the electrode 22 be made of a material that contains excess oxygen, which can be a source of oxygen to the electrode 22 .

[0201] For example, the insulating layer 110 is formed of silicon oxynitride having a thickness of 100 nm by plasma CVD. A membrane may be used.

[0202] Next, heat treatment may be performed to remove water, hydrogen, and the like contained in the insulating layer 110. As a result, it is possible to reduce the concentration of water, hydrogen, etc. contained in the insulating layer 110. This reduces the amount of water, hydrogen, and the like that diffuses into the first oxide semiconductor film that is to be formed later. can be done.

[0203] <Formation of First Oxide Semiconductor Film and Second Oxide Semiconductor Film> Next, a first oxide semiconductor film that will later become an oxide semiconductor layer 121 is formed on the insulating layer 110. A second oxide semiconductor film to be the oxide semiconductor layer 122 is formed. The second oxide semiconductor film is formed by a sputtering method, an MOCVD method, a PLD method, or the like. It is more preferable to form the film by sputtering, since the film can be formed by sputtering. The sputtering method, DC sputtering method, AC sputtering method, etc. can be used. In the facing target method (facing electrode method, vapor phase sputtering method, VDSP (Vapo The method is called the "MgO Deposition Spattering" method. This can reduce plasma damage during film formation.

[0204] For example, when the first oxide semiconductor film is formed by a sputtering method, Each chamber is equipped with a clarifier to remove water and other impurities that are harmful to oxide semiconductors. A high vacuum (5×10) was achieved by using an adsorption type vacuum pump such as an ion pump. -7 Pa~1 ×10 -4 The substrate on which the film is to be formed must be heated to 100° C. or higher, preferably 100° C. or higher. It is preferable that the pump can be heated to 400°C or higher. Alternatively, a turbo molecular pump and a cold transistor can be used. By combining this with a gas cap, gas containing carbon components and moisture does not flow back from the exhaust system into the chamber. It is also preferable to use a turbo molecular pump in combination with a cryopump. An exhaust system having a different structure may also be used.

[0205] In order to obtain a high-purity intrinsic oxide semiconductor, not only is it necessary to evacuate the chamber to a high vacuum, but also to It is also necessary to increase the purity of the sputtering gas. , the dew point is -40°C or less, preferably -80°C or less, more preferably -100°C or less By using a highly purified gas, moisture or the like is prevented from being taken into the oxide semiconductor film as much as possible. This can be prevented.

[0206] The sputtering gas is a rare gas (typically argon), oxygen, or a mixture of a rare gas and oxygen. In the case of a mixture of rare gas and oxygen, the ratio of oxygen to rare gas is It is preferable to increase the ratio.

[0207] Note that when the oxide semiconductor film is formed by, for example, a sputtering method, the substrate temperature The temperature is 150° C. or higher and 750° C. or lower, preferably 150° C. or higher and 450° C. or lower, and more preferably The oxide semiconductor film is formed at a temperature of 200° C. or higher and 420° C. or lower. A film can be formed.

[0208] The first oxide semiconductor film is made of a material so as to have a smaller electron affinity than the second oxide semiconductor film. You can choose the fee.

[0209] In addition, the second oxide semiconductor film has a higher insulating property than the first oxide semiconductor film and the third oxide semiconductor film. In the oxide semiconductor, the s orbital of the heavy metal is mainly carrier. By increasing the In content, more s orbitals overlap, which contributes to rear conduction. Therefore, oxides with a composition in which In is more abundant than Ga have compositions in which In is equal to or less than Ga. Therefore, the oxide semiconductor layer 122 has a higher mobility than an oxide made of indium. By using oxides with a high content of , it is possible to realize transistors with high mobility. do.

[0210] In addition, the first oxide semiconductor film and the second oxide semiconductor film are formed by, for example, a sputtering method. In the case of film formation, a multi-chamber sputtering apparatus is used to form the first oxide semiconductor. The first oxide semiconductor film and the second oxide semiconductor film can be successively formed without being exposed to the air. In this case, unnecessary impurities may enter the interface between the first oxide semiconductor film and the second oxide semiconductor film. As a result, the interface state can be reduced. This makes it possible to stabilize the electrical characteristics of the transistor, particularly the characteristics during reliability testing.

[0211] In addition, in the first oxide semiconductor film to which oxygen is added, In the event of damage to the semiconductor layer 122, the oxide semiconductor layer 122 serves as a main conductive path. As a result, the oxide semiconductor layer 123 can be separated from the damaged portion. The electrical characteristics of the semiconductor device, particularly the characteristics during reliability testing, can be stabilized.

[0212] For example, the first oxide semiconductor film is formed by sputtering In:Ga:Zn=1 A 20 nm thick oxide semiconductor film was formed using a target with an atomic ratio of 3:4. The second oxide semiconductor film can be formed by a sputtering method using In: An oxide film with a thickness of 15 nm was formed using a target with a Ga:Zn=1:1:1 (atomic ratio). A semiconductor film can be used.

[0213] In addition, the second oxide semiconductor film is formed by heat treatment after the formation of the first oxide semiconductor film and the second oxide semiconductor film. Therefore, the amount of oxygen vacancies in the nitride semiconductor film can be reduced.

[0214] Next, first heat treatment is performed to move part of oxygen to the second oxide semiconductor film. The oxygen vacancies in the oxide semiconductor film can be reduced. The oxide semiconductor film is referred to as a second oxide semiconductor film. In addition, the first heat treatment can reduce oxygen vacancies. Hydrogen, water, and the like contained in the oxide semiconductor film and the second oxide semiconductor film can be released. As a result, the first oxide semiconductor film and the second oxide semiconductor film to which oxygen is added can be formed. The amount of impurities contained in the steel can be reduced.

[0215] The temperature of the first heat treatment is 250° C. or higher and lower than the substrate distortion point, preferably 300° C. or higher and 650° C. or higher. °C or less, and more preferably 350°C to 550°C.

[0216] The first heat treatment is performed using a rare gas such as helium, neon, argon, xenon, or krypton. or in an inert gas atmosphere containing nitrogen. Alternatively, after heating in an inert gas atmosphere, Atmosphere or dry air (dew point below -80°C, preferably below -100°C, preferably below - Heating may be performed in an air atmosphere at 120°C or less, or under reduced pressure. In addition to the dry air, it is preferable that the inert gas and oxygen gas do not contain hydrogen, water, etc. Typically, the dew point is -80°C or less, preferably -100°C or less. Treatment times range from 3 minutes to 24 hours.

[0217] In the first heat treatment, a heat transfer heater such as a resistance heater is used instead of an electric furnace. A device that heats the workpiece by induction or thermal radiation may be used. For example, the GRTA ( Gas Rapid Thermal Anneal) equipment, LRTA (Lamp Ra RTA (Rapid Thermal Anneal) equipment, etc. The LRTA device uses halogen lamps, metal Halide lamps, xenon arc lamps, carbon arc lamps, high pressure sodium lamps The workpiece is heated by the radiation of light (electromagnetic waves) emitted from a lamp such as a high-pressure mercury lamp. The GRTA device is a device that performs the first heat treatment using high-temperature gas. The hot gas is an inert gas, such as nitrogen or a noble gas, such as argon. .

[0218] Note that the first heat treatment is performed to form an oxide semiconductor layer 121 and an oxide semiconductor layer 122, which will be described later. This may be done after etching.

[0219] For example, after heat treatment at 450°C for 1 hour in a nitrogen atmosphere, Heat treatment can be performed at 450° C. for 1 hour.

[0220] Through the above process, oxygen vacancies in the oxide semiconductor film are reduced, and impurities such as hydrogen and water are reduced. In addition, an oxide semiconductor film in which the density of localized states is reduced can be formed. Cut.

[0221] <Formation of the first conductive film> Next, a first electrode layer 130 and a first drain electrode layer 140 are formed on the oxide semiconductor layer 123. The first conductive film is formed by sputtering, chemical vapor deposition (CVD), etc. Metal organic chemical vapor deposition (MOCVD), metal chemical vapor deposition, atomic layer deposition (ALD), etc. or plasma enhanced chemical vapor deposition (PECVD), evaporation, pulsed laser deposition It can be formed by using a PLD method or the like.

[0222] The material of the first conductive film is copper (Cu), tungsten (W), molybdenum (Mo), gold (A), u), aluminum (Al), manganese (Mn), titanium (Ti), tantalum (Ta), Nickel (Ni), Chromium (Cr), Lead (Pb), Tin (Sn), Iron (Fe), Cobalt ( Co), ruthenium (Ru), platinum (Pt), iridium (Ir), strontium (S r) A conductive material that contains a single substance, an alloy, or a compound that contains these as its main component. It is preferable that the oxide semiconductor layer 1 be a single layer or a stacked layer. The lower conductive layer in contact with 22 has a material that easily bonds with oxygen, and the upper conductive layer has an oxidation-resistant material. In addition, tungsten (W) is a material that is both heat-resistant and conductive. It is preferable to use a high melting point material such as aluminum (Al) or molybdenum (Mo). It is preferable to form the insulating layer from a low-resistance conductive material such as aluminum (Al) or copper (Cu). When a -Mn alloy is used, a film containing manganese oxide is formed at the interface with the insulator containing oxygen, and the oxide Manganese oxide is preferred because it has the function of suppressing the diffusion of Cu.

[0223] For example, a tungsten film having a thickness of 20 to 100 nm is formed on the first conductive layer by sputtering. It can be formed as a film.

[0224] In addition, the conductive layer 130b formed by processing the first conductive film in a later step will be In the present invention, the semiconductor device has a function as a hard mask and a function as a source electrode layer and a drain electrode layer. Since an additional film formation process is not required, the semiconductor manufacturing process can be shortened. .

[0225] <Formation of Oxide Semiconductor Layer 121 and Oxide Semiconductor Layer 122> Next, a resist mask is formed by a lithography process, and the resist mask is used to The first conductive film is selectively etched to form a conductive layer 130b. After removing the resist on 130b, the second oxide semiconductor The oxide semiconductor layer 122 and the oxide semiconductor film are selectively etched. The compound semiconductor layer 121 can be formed in an island shape (see FIG. 7). For this purpose, a dry etching method can be used. By using the resist mask as a mask to etch the oxide semiconductor layer, the etching efficiency is improved compared to that of a resist mask. The edge roughness of the oxide semiconductor layer after the etching can be reduced.

[0226] For example, methane gas and argon gas are used as etching gas, and the resist mask and The first oxide semiconductor film and the second oxide semiconductor film are selectively etched using the hard mask. By this, the oxide semiconductor layer 121 and the oxide semiconductor layer 122 can be formed. do.

[0227] <Deposition of the second insulating film> Next, a second insulating film is formed on the insulating layer 110 and the conductive layer 130b.

[0228] The second insulating film and the third insulating film are formed by plasma CVD, thermal CVD (MOCVD, ALD For example, aluminum oxide (SiOx), magnesium oxide (MgO) are deposited by a method such as sputtering. Magnesium (MgOx), silicon oxide (SiOx), silicon oxynitride (SiOxNy), Gallium oxide (GaOx), germanium oxide (GeOx), yttrium oxide (YOx ), zirconium oxide (ZrOx), lanthanum oxide (LaOx), neodymium oxide (NdO x), hafnium oxide (HfOx) and tantalum oxide (TaOx) , silicon nitride (SiNx), silicon oxide nitride (SiNxOy), aluminum nitride ( Nitride insulating films such as aluminum oxide nitride (AlNx) and aluminum oxide nitride (AlNxOy), or The insulating film 10 may be formed by using a mixed material of the above materials. Also, the insulating film 10 may be formed by using a laminate of the above materials.

[0229] As the second insulating film, an aluminum oxide film is formed by sputtering. It is also preferable to use aluminum oxide as a sputtering target. It is also preferable that the gas used during film formation contains oxygen gas.

[0230] When the aluminum oxide film is formed, a mixed layer 171 is formed at the interface with the insulating layer 110. do.

[0231] For example, the oxygen gas used in forming the second insulating film is the same as that applied in forming the film by sputtering. Due to the influence of the applied voltage, power, plasma, and substrate temperature, oxygen radicals, oxygen ions, Oxygen atoms exist in various states and have higher energy states than the stable state. At this time, oxygen (excess oxygen, exO) 172 enters the insulating layer 110 or the mixture. It is added in layer 171 (see FIG. 8).

[0232] Next, a second heat treatment may be performed. The second heat treatment is typically performed at a temperature of 150° C. or higher. Less than the plate strain point, preferably 250°C to 500°C, more preferably 300°C to 45°C The heat treatment can be performed at a temperature of 0° C. or lower. The oxygen 172 diffuses and moves to the oxide semiconductor layer 122. This allows oxygen to be supplied to compensate for the oxygen deficiency that exists (see FIG. 9).

[0233] For example, by sputtering, using an aluminum oxide (AlOx) target, The second insulating film is formed using a sputtering gas containing 50% by volume of oxygen gas. The thickness can be 20 nm to 40 nm. As a treatment, it can be treated at 400°C for 1 hour in an oxygen atmosphere.

[0234] <Oxygen addition> In addition, the method for manufacturing the transistor 10 is not limited to the above method. The oxygen addition treatment may be performed on the insulating layer 110 or on the first insulating layer 110. This may be performed on the oxide semiconductor film, or on the third oxide semiconductor film 123a described later. The oxygen to be detected may be any of the following: oxygen radical, oxygen atom, oxygen atomic ion, oxygen molecular ion, etc. The method of adding oxygen includes ion doping, ion implantation, etc. plasma immersion ion implantation and the like.

[0235] When ion implantation is used as a method for adding oxygen, oxygen atomic ions can be used. Alternatively, oxygen molecular ions may be used. When oxygen molecular ions are used, the amount of oxygen added to the film increases. The oxygen molecular ions are capable of reducing damage to the film surface to which the oxygen is added. The oxygen molecules are separated into oxygen atoms and then added. Energy is used to add oxygen molecular ions to the membrane to which the oxygen is added. The energy per oxygen atom ion in This is lower than the case where oxygen is added to the film. Therefore, damage to the film to which the oxygen is added is reduced. It can be reduced.

[0236] In addition, when oxygen molecular ions are implanted, the oxygen is more easily absorbed than when oxygen atomic ions are implanted. The energy per atomic ion is low. Therefore, it is possible to implant oxygen molecular ions. This allows the acceleration voltage to be increased, and the throughput to be improved. In addition, by using oxygen molecular ions, compared to the case of using oxygen atomic ions, It is possible to halve the dose to add the same amount of oxygen atomic ions. As a result, the throughput of the manufacturing process can be increased.

[0237] In addition, when oxygen is added to the film to which the oxygen is added, oxygen atoms are added to the film to which the oxygen is added. The oxygen is added under conditions such that the peak of the concentration profile of the molecular ions is located. It is preferable to add oxygen to the film to be etched. As a result, the film is more resistant to oxygen ion implantation than when oxygen atomic ions are implanted. In addition, the acceleration voltage during implantation can be lowered, reducing damage to the film to which the oxygen is added. That is, the amount of defects in the film to which oxygen is added can be reduced. It is possible to suppress the change in the electrical characteristics of the transistor. This reduces damage to the film that is being processed, and suppresses fluctuations in the electrical characteristics of the transistor. It can be controlled.

[0238] Also, a plasma method is used in which a film to which oxygen is added is exposed to plasma generated in an atmosphere containing oxygen. By plasma immersion ion implantation (PIA), oxygen is added to the film to which the oxygen is added. The oxygen-containing atmosphere may be oxygen, ozone, nitrous oxide, nitrogen dioxide, or the like. The atmosphere contains a chemical gas. By exposing the film to which oxygen is to be added to the plasma, oxygen is added to the film to which oxygen is to be added. It is possible and preferable to increase the amount of the plasma. As an example, there is an ashing device.

[0239] For example, the acceleration voltage is 5 kV and the dose is 1×10 16 / cm 2 The oxygen molecule ions of The first oxide semiconductor film can be doped by an on-implantation method.

[0240] The oxide semiconductor layer 122 is formed by a combination of the above steps and the subsequent heat treatment. The amount of oxygen vacancies can be reduced. Note that the film to which oxygen is added has a thickness of 100 nm, which is smaller than that of the film before the oxygen is added. The film density is lower than that of the film of

[0241] <Deposition of the third insulating film> Next, a third insulating film is formed on the second insulating film. The third insulating film is formed by a plasma CVD method. Thermal CVD (MOCVD, ALD), sputtering, spin coating, etc. For example, aluminum oxide (SiOx), magnesium oxide (MgOx), silicon oxide Silicon (SiOx), silicon oxide nitride (SiOxNy), gallium oxide (GaOx), Germanium oxide (GeOx), yttrium oxide (YOx), zirconium oxide (Zr Ox), lanthanum oxide (LaOx), neodymium oxide (NdOx), hafnium oxide (Hf Oxide insulating films such as tantalum oxide (TaOx), silicon nitride (SiNx) , Silicon oxynitride (SiNxOy), Aluminum nitride (AlNx), Aluminum oxynitride It is formed using a nitride insulating film such as GaN (AlNxOy) or a mixture of these materials. Also, the material may be a laminate of the above materials.

[0242] Alternatively, the third insulating film may be made of a material having a low dielectric constant (a low-k material). Silicon oxide (SiOF) containing a few percent of fluorine (F), and silicon oxide (SiOF) containing a few percent of carbon (C) Silicon oxide (SiOC), fluorinated silicate glass (FSG), organic silicate glass (OSG), Hydrogenated Silsesquioxane (HSQ), Methyl Silsesquioxane (M SQ), organic polymers, fluororesins (polytetrafluoroethylene), polyimides, fluorine It can be formed by using amorphous carbon to which nitrogen is added.

[0243] The second heat treatment may be performed after the formation of the third insulating film.

[0244] <Planarization of the third insulating film> Next, a planarization process is performed on the third insulating film to form an insulating layer 175b. MP (Chemical Mechanical Polishing) method, dry etching The etching can be performed by a etching method, a reflow method, or the like. Also, the planarization can be performed by a CMP method. In this case, a film having a different composition from the third insulating film is introduced on the third insulating film to obtain a C The thickness of the insulating layer 175 within the substrate surface after the MP process can be made uniform.

[0245] Note that the second heat treatment may be performed after the third insulating film is planarized.

[0246] <Formation of Groove, Source Electrode Layer 130, and Gate Insulating Layer 150> Next, a resist mask 176 is formed on the insulating layer 175b by a lithography process (FIG. 10). Note that after applying an organic film onto the insulating layer 175b, or after applying a resist The lithography process may be performed after applying an organic film. It contains cholesteryl monomethyl ether, ethyl lactate, etc., and acts as an anti-reflective coating (BA) during exposure. RC (Bottom Anti Reflective Coating) function In addition, it is known to have the effect of improving the adhesion between the resist and the film and improving the resolution. can.

[0247] In addition, when forming a transistor with an extremely short channel length, at least the source electrode layer 130, in the region dividing the conductive layer 130b which becomes the drain electrode layer 140, an electron beam is Resist mask processing using methods suitable for fine line processing such as nanoimprint exposure, immersion exposure, and EUV exposure. Then, the region is etched by the etching process. When forming a resist mask by light, a positive resist is used as the resist mask. If such a device is used, the exposure area can be minimized and throughput can be improved. Using this method, it is possible to reduce the channel length to 100 nm or less, or even to 30 nm or less. A transistor can be formed. Or, light with a very short wavelength (e.g., extreme ultraviolet light) (EUV: Extreme Ultraviolet) and X-ray exposure technology Fine processing may be performed by techniques.

[0248] Using the resist mask, a groove is formed in the insulating layer 175b by dry etching. As the etching process proceeds selectively, a groove 174 is formed in the insulating layer 175. do.

[0249] Next, the exposed conductive layer 130b is selectively etched in a manner to divide the source electrode layer 1 30, a drain electrode layer 140 may be formed (see FIG. 11).

[0250] After the source electrode layer 130 and the drain electrode layer 140 are formed, etching residues are removed. In order to prevent this, a cleaning process may be performed. This can prevent short circuits in the drain electrode layer 140. Alkaline solutions such as tetramethylammonium hydroxide This can be done using an acidic solution such as diluted hydrofluoric acid, oxalic acid, or phosphoric acid. In addition, the cleaning process etches a part of the oxide semiconductor layer 122, and the oxide semiconductor layer 1 A recess is formed in 22.

[0251] The oxide semiconductor layer 121, the oxide semiconductor layer 122, the source electrode layer 130, the drain electrode The order of forming the source electrode layer 130 may be changed. A groove 174 for forming a drain electrode is provided first, and then the oxide semiconductor layer 121, An oxide semiconductor layer 122 may be formed.

[0252] For example, after the silicon oxynitride film formed as the second insulating film is planarized, the silicon oxynitride film is A resist mask is formed on the carbon film, and the resist mask and a gas containing carbon and fluorine are The silicon oxynitride is opened by dry etching using chlorine, The conductive layer 130b is dry-etched using a fluorine-based gas to form a source electrode Layer 130 and drain electrode layer 140 may be formed.

[0253] <Formation of Third Oxide Semiconductor Film 123a> Next, the oxide semiconductor layer 122 is formed on the insulating layer 175. The third oxide semiconductor film 123a is formed. The third oxide semiconductor film 123a can be formed by a method similar to that for forming the first oxide semiconductor film. A material can be selected so as to have a smaller electron affinity than the oxide semiconductor film of 2.

[0254] For example, the third oxide semiconductor film 123a may be formed by sputtering using In:Ga: An oxide semiconductor film formed to a thickness of 5 nm using a target with a Zn=1:3:2 (atomic ratio) can be used.

[0255] <Formation of insulating film 150a> Next, a fourth insulating film 150a which will become the gate insulating layer 150 is formed on the oxide semiconductor film 123a. The fourth insulating film 150a is formed of, for example, aluminum oxide (AlOx), magnesium oxide, etc. Magnesium (MgOx), silicon oxide (SiOx), silicon oxynitride (SiOxNy) , silicon oxide nitride, silicon nitride, gallium oxide, germanium oxide, yttrium oxide Zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide and tantalum oxide The fourth insulating film 150a may be a laminate of the above materials. The fourth insulating film 150a may be formed by sputtering, CVD (plasma CVD, MOCVD, etc.) or the like. The fourth insulating layer can be formed by using a method such as a CVD method, an ALD method, or an MBE method. The insulating film 150a can be formed as an insulating film by appropriately using a method similar to that for the insulating layer 110. .

[0256] For example, the fourth insulating film 150a is formed by depositing silicon oxynitride to a thickness of 10 nm by plasma CVD. m can be formed.

[0257] <Formation of Conductive Film 160a> Next, a second conductive film 160a which will become a gate electrode layer 160 is formed on the fourth insulating film 150a. (See FIG. 12.) The second conductive film 160a is made of, for example, aluminum (Al). , Titanium (Ti), Chromium (Cr), Cobalt (Co), Nickel (Ni), Copper (Cu) , Yttrium (Y), Zirconium (Zr), Molybdenum (Mo), Ruthenium (Ru ), silver (Ag), gold (Au), platinum (Pt), tantalum (Ta), tungsten (W), Alternatively, an alloy material containing these as a main component can be used. Sputtering method, CVD method (plasma CVD method, MOCVD method, ALD method, etc.), MBE method, The second conductive film 160a can be formed by a deposition method, a plating method, or the like. Alternatively, a conductive film containing nitrogen may be used, and a laminate of the conductive film and a conductive film containing nitrogen may be used. The second conductive film 160a may be a single layer or a multilayer.

[0258] For example, the conductive film 160a is formed by forming titanium nitride at 10 nm and tungsten metal at 10 nm by the ALD method. A 150 nm layered structure can be achieved by the TLC CVD method.

[0259] <Flattening process> Next, a planarization process is performed. The planarization process is performed using a method such as CMP or dry etching. The planarization process may be terminated when the third insulating film 150a is exposed. The process may be terminated when the third oxide semiconductor film 123a is exposed, or when the insulating layer 175 is The process may be terminated when the gate electrode layer 160 and the gate insulating layer 150 are exposed. Then, an oxide semiconductor layer 123 can be formed (see FIG. 13).

[0260] Note that the oxide semiconductor film 123a or the insulating film 150a is formed over the planarized insulating layer 175. In the case where the oxide semiconductor film has a resist mask, the oxide semiconductor film may be processed using a resist mask. A resist mask is formed on the insulating film 23a or the insulating film 150a by a lithography process. The mask has an area larger than the upper surface of the gate electrode layer 160. The insulating film 150a and the oxide semiconductor film 123a are selectively etched to form a gate insulating layer. 150, an oxide semiconductor layer 123 can be formed.

[0261] In the transistor 10, the oxide semiconductor layer 123 is provided so that oxygen vacancies are not easily generated. As a result, oxygen is prevented from being desorbed from the side surface of the oxide semiconductor layer 123 in the channel width direction. This suppresses the generation of oxygen vacancies, resulting in improved electrical characteristics and reliability. This makes it possible to realize transistors with high performance.

[0262] Next, a third heat treatment may be performed. The heat treatment is typically performed at a temperature of 150° C. or higher. Less than the strain point, preferably 250°C to 500°C, more preferably 300°C to 450°C The heat treatment can be performed at a temperature of 0.5° C. or less. The heat treatment can add an additive to the insulating layer (e.g., insulating layer 175). The oxygen diffuses and moves to the oxide semiconductor layer 122. This allows oxygen to be supplied to compensate for the oxygen deficiency that occurs.

[0263] For example, a heat treatment can be performed at 400° C. for 1 hour in an oxygen atmosphere.

[0264] Through the above steps, the localized state density of the oxide semiconductor film is reduced, and the oxide semiconductor film has excellent electrical characteristics. It is possible to manufacture transistors. In addition, the electrical characteristics of the transistors can be checked by aging and stress testing. It is possible to manufacture highly reliable transistors with little fluctuation.

[0265] <Modification 1 of Transistor 10: Transistor 11> A transistor 11 having a different shape from the transistor 10 shown in FIG. 1 will be described with reference to FIG. explain.

[0266] 14A, 14B, and 14C are a top view and a cross-sectional view of a transistor 11. FIG. 14(A) is a top view of the transistor 11, and FIG. 14(B) is a top view of the transistor 11. 14(A) is a cross-sectional view taken along dashed line A1-A2, and FIG. 14(C) is a cross-sectional view taken along dashed line A3-A4.

[0267] The transistor 11 has side surfaces (channel regions) of the oxide semiconductor layers 121 and 122. excluding the above region), the side surfaces of the source electrode layer 130 and the drain electrode layer 140, the side surfaces of the insulating layer 110, and The transistor 10 has a conductive layer 135 that contacts the upper surface and the lower surface of the insulating layer 170. The conductive layer 135 has a sidewall shape as shown in FIG.

[0268] Conductive layer 135 The conductive layer 135 may be made of copper (Cu), tungsten (W), molybdenum (Mo), or gold (Au). , Aluminum (Al), Manganese (Mn), Titanium (Ti), Tantalum (Ta), Ni Ni, Cr, Pb, Sn, Fe, Cobalt ), Ruthenium (Ru), Platinum (Pt), Iridium (Ir), Strontium (Sr) A single substance or alloy consisting of these materials, or oxygen, nitrogen, fluorine, It is preferable to use a single layer or a multilayer of conductive layers containing a compound such as silicon. For example, In the case of stacking, the lower conductive layer in contact with the oxide semiconductor layer 122 is easily bonded to oxygen. The upper conductive layer may have a material having high oxidation resistance. It is preferable to use a high melting point material such as tungsten or molybdenum that has both excellent electrical conductivity and excellent thermal conductivity. It is also preferable to form the electrode from a low resistance conductive material such as aluminum or copper. When a Cu-Mn alloy is used, manganese oxide is formed at the interface with the insulator containing oxygen, and the manganese oxide The use of calcium phosphate as a ferroelectric material is preferred because it has the function of suppressing the diffusion of Cu.

[0269] The conductive layer 135 is provided to contact the oxide semiconductor layer 121 and the oxide semiconductor layer 122. Therefore, the area of ​​the conductive layer can be increased, and the on-current can be increased.

[0270] <Modification 2 of Transistor 10: Transistor 12> Regarding the transistor 12 having a different shape from the transistor 10 shown in FIG. 1, This will be explained using 6.

[0271] 15A, 15B, and 15C are a top view and a cross-sectional view of a transistor 12. FIG. 15(A) is a top view of the transistor 12, and FIG. 15(B) is a top view of the transistor 12. 15(A) is a cross-sectional view taken along dashed line A1-A2, and FIG. 15(C) is a cross-sectional view taken along dashed line A3-A4.

[0272] The transistor 12 includes a conductive layer 165 below the insulating layer 110, an insulating layer 175, and an oxide semiconductor layer. The insulating layer 177 is formed on the upper surface of the gate electrode layer 160. The transistor 10 differs from the transistor 10 in this respect.

[0273] Conductive layer 165 The conductive layer 165 can function as a bottom gate. The potential can be the same as that of the gate electrode layer 160, or a different potential can be applied. The conductive layer 165 may be made of, for example, copper (Cu), tungsten (W), molybdenum (Mo), or gold. (Au), Aluminum (Al), Manganese (Mn), Titanium (Ti), Tantalum (Ta ), Nickel (Ni), Chromium (Cr), Lead (Pb), Tin (Sn), Iron (Fe), Cobalt (Co) Co, Ru, Platinum, Iridium, Strontium (Sr) element or alloy, or oxygen, nitrogen, It is preferable to form a single layer or a multilayer of a conductive layer containing a compound such as fluorine or silicon. For example, the conductive layer 166 may be made of a material that is highly resistant to oxidation. 67 uses high melting point materials such as tungsten and molybdenum that are both heat resistant and conductive. It is also preferable to form the insulating layer 11 from a low-resistance conductive material such as aluminum or copper. It is.

[0274] Insulating layer 177 The insulating layer 177 contains oxygen (O), nitrogen (N), fluorine (F), aluminum (Al), ma Magnesium (Mg), Silicon (Si), Gallium (Ga), Germanium (Ge), In Tritium (Y), Zirconium (Zr), Lanthanum (La), Neodymium (Nd), Hafnium (Hf) For example, the metals may include hafnium (Hf), tantalum (Ta), titanium (Ti), etc. , Aluminum oxide (AlOx), Magnesium oxide (MgOx), Silicon oxide (Si Ox), silicon oxide nitride (SiOxNy), silicon oxide nitride (SiNxOy), nitride Silicon (SiNx), Gallium oxide (GaOx), Germanium oxide (GeOx), Acid Yttrium oxide (YOx), zirconium oxide (ZrOx), lanthanum oxide (LaOx) , neodymium oxide (NdOx), hafnium oxide (HfOx) and tantalum oxide (TaO The insulating layer 177 can be a laminate of the above materials. may be also possible.

[0275] The insulating layer 177 preferably includes an aluminum oxide film. The aluminum oxide film is Has a barrier effect that prevents impurities such as hydrogen and moisture, as well as oxygen, from passing through the membrane Therefore, the aluminum oxide film can be used during and after the manufacturing process of the transistor. After manufacturing, the oxidation of impurities such as hydrogen and moisture, which are factors that cause fluctuations in the electrical characteristics of transistors, Preventing contamination of the oxide semiconductor layer 121 and the oxide semiconductor layer 122; Preventing emission from the semiconductor layer 121 and the oxide semiconductor layer 122, and eliminating the need for oxygen from the insulating layer 175 It is suitable for use as a protective film having an important emission prevention effect.

[0276] The insulating layer 177 is preferably a film having an oxygen supplying ability. It is preferable to form the insulating layer 177 by a sputtering method. A mixed layer is formed at the interface with the insulating layer 175, and oxygen 17 is introduced into the mixed layer or the insulating layer 175. 2 can be added.

[0277] The transistor 12 can be subjected to third heat treatment after the insulating layer 177 is formed. The heat treatment in step 3 is typically performed at a temperature of 150° C. or higher and lower than the substrate distortion point, and preferably at a temperature of 250° C. or higher and lower than the substrate distortion point. The third heating temperature can be set to 00° C. or lower, and more preferably to 300° C. or higher and 450° C. or lower. The treatment causes the dopant in the insulating layer 175 to diffuse, and the oxide semiconductor layer 121 and the oxide semiconductor The oxygen ions move to the oxide semiconductor layer 122 and compensate for oxygen vacancies present in the oxide semiconductor layer 122. It is possible.

[0278] The third heat treatment can also serve as the second heat treatment. 10, oxygen 172 added to the insulating layer 175 is formed in the gate insulating layer 150 and the oxide semiconductor layer 1 23, the oxide semiconductor layer 121, etc., and the oxide semiconductor layer 122, Oxygen deficiencies present in the conductor layer 122 can be compensated for with oxygen (see FIG. 16). .

[0279] This improves the transistor characteristics (e.g., threshold value, reliability, etc.) of the transistor 12. It can be done.

[0280] As shown in FIG. 17, the transistor 12 has a structure in which transistors are arranged in parallel. Transistor 13) (see FIG. 17). As shown in FIG. 18, an insulating layer 180 is formed on the insulating layer 170, and a conductive layer 181 is formed on the gate electrode layer 160. 90 (conductive layer 191, conductive layer 192), and the gate electrode layer 160 and the conductive layer 190 are electrically connected to each other. The structure may be electrically connected.

[0281] The insulating layer 180 can be made of the same material as the insulating layer 175. Layer 190 may be formed of materials similar to gate electrode layer 160 .

[0282] The transistor 13 can increase the on-current while exhibiting good transistor characteristics. do.

[0283] This embodiment mode may be appropriately combined with other embodiment modes and examples shown in this specification. It is possible.

[0284] (Embodiment 2) In this embodiment, a transistor having a structure different from that of the transistor 10 described in the first embodiment is used. A method for manufacturing the stator 14 and the transistor 14 will be described.

[0285] <Transistor 14> 19A, 19B, and 19C are diagrams illustrating the upper surface of a transistor 14 according to one embodiment of the present invention. 19(A) is a top view, and FIG. 19(B) is a cross-sectional view of FIG. 19(A). FIG. 19(C) is a cross-sectional view of the dashed line A3-A4 in FIG. 19(A). In addition, in FIG. 19(A), some elements are enlarged, reduced, or omitted for clarity. The dashed line A1-A2 direction is the channel length direction, and the dashed line A3- The A4 direction may be referred to as the channel width direction.

[0286] The transistor 14 has a groove 17 as shown in FIG. 19(A), FIG. 19(B), and FIG. 19(C). 4, an insulating layer 185 is provided on the upper surfaces of the source electrode layer 130 and the drain electrode layer 140. The insulating layer 185 is different from the transistor 10 in that the insulating layer 185 is formed by insulating layers 170 and 175. The oxide semiconductor layer 123 is in contact with the side surface of the insulating layer 185 and is located above the insulating layer 185 .

[0287] Insulating layer 185 The insulating layer 185 contains oxygen (O), nitrogen (N), fluorine (F), aluminum (Al), ma Magnesium (Mg), Silicon (Si), Gallium (Ga), Germanium (Ge), In Tritium (Y), Zirconium (Zr), Lanthanum (La), Neodymium (Nd), Hafnium (Hf) For example, the metals may include hafnium (Hf), tantalum (Ta), titanium (Ti), etc. , magnesium oxide (MgOx), silicon oxide (SiOx), silicon oxynitride (Si OxNx), silicon oxynitride (SiNxOx), silicon nitride (SiNx), gallium oxide yttrium oxide (YOx), germanium oxide (GaOx), germanium oxide (GeOx), yttrium oxide (YOx), Zirconium (ZrOx), lanthanum oxide (LaOx), neodymium oxide (NdOx), acid Hafnium oxide (HfOx), tantalum oxide (TaOx), aluminum oxide (AlO The insulating layer 185 may be a laminate of the above materials. The insulating layer preferably has more oxygen than the stoichiometric composition. .

[0288] Alternatively, the insulating layer 185 may be made of a material with a low dielectric constant (a low-k material). Silicon oxide (SiOF) containing a few percent of fluorine (F), and silicon oxide (SiOF) containing a few percent of carbon (C) Silicon oxide (SiOC), fluorinated silicate glass (FSG), organic silicate glass (OSG), Hydrogenated Silsesquioxane (HSQ), Methyl Silsesquioxane (M SQ), organic polymers, polyimides, fluororesins (polytetrafluoroethylene), The insulating layer 185 can be formed by using amorphous carbon to which silicon is added. By using low-k materials, the capacitance associated with the transistor 14 can be further reduced. can.

[0289] The transistor 14 has an insulating layer 185, which allows processing below the resolution limit of the device. This allows for finer processing, reducing development costs such as introducing new equipment. It is possible.

[0290] <Method of manufacturing transistor 14> A method for manufacturing the transistor 14 will be described below. For steps similar to those for the transistor 10, the same explanation is used.

[0291] As shown in FIG. 20(A) and FIG. 20(B), after forming the insulating layer 170 and the insulating layer 175b, the groove A resist mask 176 for forming a portion of the transistor 1 is formed. Compared to the conventional method, the groove dimensions can be made wider (the design rules can be relaxed).

[0292] Next, the insulating layer 175b is selectively etched using the resist mask 176, and the insulating layer 1 Form 75.

[0293] Next, a fourth insulating film that will become the insulating layer 185 is formed. The fourth insulating film is formed by a plasma CVD method. , thermal CVD method (MOCVD method, ALD method), sputtering method, spin coating method, etc. It can be formed by:

[0294] Next, an etch-back process is performed using a dry etching method to form an insulating layer 185. .

[0295] Next, the insulating layer 185 is used as a hard mask until the oxide semiconductor layer 122 is exposed. The conductive layer 130b is selectively etched to remove the source electrode layer 130 and the drain electrode layer 140. (See FIG. 21).

[0296] Next, a third oxide semiconductor film 123a, a third insulating film 150a, and a conductive film 160a are formed in this order. A film is formed on the insulating film 14 (see FIG. 22) and then planarized to form a transistor 14 (see FIG. 23). (see).

[0297] This embodiment mode may be appropriately combined with other embodiment modes and examples shown in this specification. It is possible.

[0298] (Embodiment 3) <Structure of oxide semiconductor> In this embodiment, a structure of an oxide semiconductor will be described.

[0299] Oxide semiconductors are classified into single-crystal oxide semiconductors and non-single-crystal oxide semiconductors. As a non-single-crystal oxide semiconductor, CAAC-OS (C Axis Aligned Crystalline Oxide Semiconductor, polycrystalline oxide semiconductor Conductor, nc-OS (nanocrystalline Oxide Semiconductor) ctor), pseudo-amorphous oxide semiconductor (a-like OS: amorphous li ke oxide semiconductor), and amorphous oxide semiconductor.

[0300] From another point of view, the oxide semiconductor is classified into an amorphous oxide semiconductor and a crystalline oxide semiconductor other than the amorphous oxide semiconductor. Crystalline oxide semiconductors are classified into single crystal oxide semiconductors, CAAC-O S, polycrystalline oxide semiconductor, and nc-OS.

[0301] The definition of an amorphous structure is generally that it is not fixed in a metastable state and is isotropic. It is known that the bond angles are flexible and the bond length is short. In other words, it is a structure that has order but does not have long-range order.

[0302] On the other hand, in the case of an essentially stable oxide semiconductor, It cannot be called an oxide semiconductor. The oxide semiconductor (for example, having a periodic structure in a microscopic region) is transformed into a completely amorphous oxide. It cannot be called a semiconductor. However, a-like OS is a periodic Although it has a structure, it has voids and is an unstable structure. Its physical properties are similar to those of an amorphous oxide semiconductor.

[0303] <caac-os> First, let me explain about CAAC-OS.

[0304] CAAC-OS is an oxide semiconductor that has multiple crystal parts (also called pellets) aligned along the c-axis. It is a conductor.

[0305] Transmission Electron Microscope (TEM) A composite analysis image (high resolution) of the bright-field image and the diffraction pattern of CAAC-OS was obtained by using a scope. When observing the high-resolution TEM image, multiple pellets can be confirmed. In the high-resolution TEM image, the boundaries between the pellets, i.e., grain boundaries, are not clearly visible. Therefore, it is not possible to clearly confirm the presence of the CAAC-OS. Therefore, it can be said that the decrease in electron mobility caused by the above phenomenon is unlikely to occur.

[0306] The CAAC-OS observed by TEM will be described below. This shows a high-resolution TEM image of a cross section of CAAC-OS observed from a direction approximately parallel to the sample surface. For high-resolution TEM imaging, spherical aberration correction (SAC) is required. The spherical aberration corrector function was used. In particular, it is called a Cs-corrected high-resolution TEM image. This was carried out using an atomic resolution analytical electron microscope, such as the JEM-ARM200F manufactured by Nippon Denki Co., Ltd. This can be done.

[0307] FIG. 24(B) shows an enlarged Cs-corrected high-resolution TEM image of region (1) in FIG. 24(A). From FIG. 24(B), it can be seen that the metal atoms are arranged in layers in the pellet. The arrangement of each metal atom layer is the same as that of the surface on which the CAAC-OS film is formed (also called the surface on which the film is formed). The surface on which the CAAC-OS is formed or the top surface of the CAAC-OS reflects the unevenness of the surface on which the CAAC-OS is formed or the top surface of the CAAC-OS.

[0308] As shown in Figure 24(B), CAAC-OS has a characteristic atomic arrangement. The characteristic atomic arrangement is shown by auxiliary lines in Figure 24(B) and Figure 24(C). Therefore, the size of each pellet can be 1 nm or more, or 3 nm or more. It can be seen that the size of the gap caused by the tilt between the plate and the pellet is about 0.8 nm. Therefore, the pellets can also be called nanocrystals (nc). In addition, CAAC-OS is also used as a C-Axis Aligned Nanocry The semiconductor may also be referred to as an oxide semiconductor having a stals structure.

[0309] Here, based on the Cs-corrected high-resolution TEM image, the pellet of CAAC-OS on the substrate 5120 was The layout of the 5100 is shown diagrammatically as a stack of bricks or blocks. (See FIG. 24(D)). The inclination between the pellets observed in FIG. 24(C) The location where the crack occurs corresponds to an area 5161 shown in FIG.

[0310] FIG. 25(A) shows the Cs Corrected high-resolution TEM images are shown for regions (1), (2), and (3) in FIG. 25(A). The enlarged Cs-corrected high-resolution TEM images are shown in Fig. 25(B), Fig. 25(C), and Fig. 25(D), respectively. 25(D). From Fig. 25(B), Fig. 25(C) and Fig. 25(D), the pellet is It can be seen that the metal atoms are arranged in triangular, tetragonal or hexagonal shapes. However, no regularity is observed in the arrangement of metal atoms among different pellets.

[0311] Next, the CA analyzed by X-ray diffraction (XRD) We will explain AC-OS. For example, CAAC-OS with InGaZnO4 crystals When the structure is analyzed using the out-of-plane method, the result is as shown in Figure 26(A). A peak may appear at a diffraction angle (2θ) of about 31°. Since the crystal orientation of CAAC-OS is attributed to the (009) plane of nO4, the crystal orientation of CAAC-OS is considered to be c-axis oriented. It can be seen that the c-axis is oriented in a direction substantially perpendicular to the surface on which the film is formed or the upper surface.

[0312] In addition, in the out-of-plane structural analysis of CAAC-OS, 2θ is 31° In addition to the peaks around 2θ of 36°, a peak may also appear around 2θ of 36°. The peaks near the c-axis indicate that some of the CAAC-OS contains crystals that do not have the c-axis orientation. The more preferable CAAC-OS is the structure solution by the out-of-plane method. In the analysis, a peak is observed at 2θ of approximately 31°, but no peak is observed at 2θ of approximately 36°.

[0313] On the other hand, in-plan X-ray irradiation is performed on CAAC-OS in a direction perpendicular to the c-axis. When the structure is analyzed by the δ method, a peak appears at 2θ of about 56°. This peak is due to In It is assigned to the (110) plane of the GaZnO4 crystal. In the case of CAAC-OS, 2θ is set to 56 The sample was rotated around the normal vector of the sample surface as the axis (φ axis) while performing the analysis. Even if a φ scan is performed, no clear peak appears as shown in FIG. 26(B). However, in the case of a single crystal oxide semiconductor such as InGaZnO4, 2θ is fixed at around 56° and φ shift is When scanning was performed, the peaks attributable to the crystal plane equivalent to the (110) plane were as shown in FIG. Therefore, from the structural analysis using XRD, CAAC-OS has the following structure: It can be seen that the orientation of the a-axis and b-axis is irregular.

[0314] Next, we will explain the CAAC-OS analyzed by electron diffraction. For CAAC-OS with nO4 crystals, a probe with a diameter of 300 nm was placed parallel to the sample surface. When an electron beam is incident, a diffraction pattern (selected area transmission electron diffraction) like that shown in FIG. This diffraction pattern may show the InGaZnO4 This includes spots due to the (009) plane of the crystal. Therefore, even with electron diffraction, The pellets contained in the CAAC-OS have a c-axis orientation, and the c-axis is approximately aligned on the surface to be formed or the upper surface. On the other hand, the same sample was probed perpendicular to the sample surface. The diffraction pattern when an electron beam with a diameter of 300 nm is incident is shown in FIG. (B) shows a ring-shaped diffraction pattern. Therefore, by electron diffraction, It is seen that the a-axis and b-axis of the pellets contained in the CAAC-OS have no orientation. In addition, the first ring in FIG. 27(B) is the (010) plane of the InGaZnO4 crystal. This is thought to be due to the (100) plane and other factors. The second ring in Figure 27(B) This is thought to be due to the (110) plane.

[0315] As described above, the CAAC-OS is an oxide semiconductor with high crystallinity. Crystallinity can be reduced by the inclusion of impurities or the formation of defects, so the opposite view is taken. CAAC-OS can be said to be an oxide semiconductor with few impurities and defects (such as oxygen vacancies).

[0316] The impurities are elements other than the main components of the oxide semiconductor, such as hydrogen, carbon, silicon, and transition metals. For example, oxygen is more abundant than metal elements such as silicon that constitute oxide semiconductors. Elements with strong bonding strength with the oxide semiconductor remove oxygen from the oxide semiconductor, thereby changing the atomic arrangement of the oxide semiconductor. In addition, heavy metals such as iron and nickel, argon, and nitrogen Carbon oxide and other elements have a large atomic radius (or molecular radius), so they can easily arrange the atoms of oxide semiconductors. This causes the crystallinity to decrease.

[0317] When an oxide semiconductor has impurities or defects, its characteristics may change due to light, heat, etc. For example, impurities contained in an oxide semiconductor can become carrier traps or can displace carriers. In addition, oxygen vacancies in oxide semiconductors can become carrier traps. In some cases, they act as carrier generation sources by capturing hydrogen.

[0318] CAAC-OS, which has few impurities and oxygen vacancies, is an oxide semiconductor with low carrier density. Specifically, 8×10 11 / cm 3 Less than 1 x 10 11 / cm 3 Less than More preferably, 1×10 10 / cm 3 Less than 1 x 10 -9 / cm 3 More than a career Such an oxide semiconductor can be a high-purity intrinsic or It is essentially a high-purity intrinsic oxide semiconductor. CAAC-OS has a low impurity concentration and In other words, it can be said that the oxide semiconductor has stable characteristics.

[0319] <nc-os> Next, we will explain nc-OS.

[0320] In the high-resolution TEM image, the nc-OS is divided into two groups: one where the crystals can be confirmed, and the other where the crystals can be clearly confirmed. The nc-OS has regions where no crystalline parts can be confirmed. The size is often between 1 nm and 10 nm, or between 1 nm and 3 nm. An oxide semiconductor having a crystal size of 10 nm or more and 100 nm or less is called a microcrystalline oxide. For example, in high-resolution TEM images, nc-OS shows grain boundaries. In addition, the nanocrystals are different from the pellets in CAAC-OS. Therefore, in the following, the crystalline part of nc-OS is called pellets. There may be cases where this happens.

[0321] The nc-OS is a nano-sized area (e.g., an area of ​​1 nm to 10 nm, especially 1 nm to 3 nm). The nc-OS has periodic atomic arrangement in the sub-nm region. There is no regularity in the crystal orientation between the dots. Therefore, no orientation is observed throughout the film. Therefore, depending on the analysis method, nc-OS may be considered to be a-like OS or amorphous oxide semiconductor. For example, for nc-OS, the X-shaped pellets with a diameter larger than that of the pellets may not be distinguishable. When using the line, the peaks indicating the crystal planes were not detected by the out-of-plane method. In addition, for nc-OS, a probe diameter larger than the pellet (e.g. 50n When electron diffraction is performed using an electron beam of 1000 nm or more, a halo-like diffraction pattern is observed. On the other hand, for nc-OS, the size of the pellet is close to or smaller than that of the pellet. When performing nanobeam electron diffraction using an electron beam with a diameter of n When nanobeam electron diffraction is performed on c-OS, bright spots appear in a circular (ring-like) pattern. In some cases, a ring-shaped area may be observed. In addition, multiple spots may be observed within the ring-shaped area. There are cases.

[0322] In this way, the crystal orientation between the pellets (nanocrystals) is not regular, so nc- OS with RANC (Random Aligned nanocrystals) oxide semiconductors, or NANCs (Non-Aligned Nanocrystals) ) can also be referred to as an oxide semiconductor.

[0323] The nc-OS is an oxide semiconductor with higher order than an amorphous oxide semiconductor. The nc-OS has a lower density of defect states than the a-like OS and amorphous oxide semiconductors. However, the crystal orientation of nc-OS is not regular among different pellets. , the nc-OS has a higher density of defect states than the CAAC-OS.

[0324] <a-like OS> The a-like OS is an oxide semiconductor that has a structure between the nc-OS and the amorphous oxide semiconductor. It is a conductor.

[0325] In a-like OS, pores may be observed in high-resolution TEM images. In the high-resolution TEM image, there are areas where crystals can be clearly seen and areas where crystals cannot be seen. and areas where it is not possible to

[0326] Because of the porosity, the a-like OS is an unstable structure. To demonstrate that the OS has a less stable structure compared with CAAC-OS and nc-OS. , shows the change in structure due to electron irradiation.

[0327] The samples to be irradiated with electrons were a-like OS (referred to as sample A), nc-OS ( Sample B) and CAAC-OS (sample C) are prepared. The sample in is also an In-Ga-Zn oxide.

[0328] First, high-resolution cross-sectional TEM images of each sample are obtained. It can be seen that each of the samples has a crystalline portion.

[0329] The determination of which part is regarded as one crystal part can be made as follows. For example, The unit cell of the InGaZnO4 crystal has three In-O layers and one Ga-Zn-O layer. It is known that the structure has a total of nine layers, including six layers, stacked in layers in the c-axis direction. The spacing between adjacent layers is approximately the same as the lattice spacing (also called the d value) of the (009) plane. The value is calculated to be 0.29 nm from crystal structure analysis. The area where the spacing is 0.28 nm or more and 0.30 nm or less is considered to be the crystal part of InGaZnO4. The lattice fringes correspond to the ab plane of the InGaZnO4 crystal.

[0330] Figure 28 shows an example of the average size of the crystal parts (22 to 45 places) of each sample. However, the length of the lattice fringes mentioned above is the size of the crystal part. It can be seen that the crystal part of eOS becomes larger according to the cumulative dose of electron irradiation. As shown by (1) in Figure 28, the initial TEM observation showed a size of about 1.2 nm. The crystal part (also called the initial nucleus) was 4.2×10 in size, but the cumulative irradiation dose was 4.2×10 8 e - / nm 2 On the other hand, in the nc-OS, the size of the nanoparticles grows to about 2.6 nm. For CAAC-OS, the cumulative electron dose from the start of electron irradiation was 4.2 × 10 8 e - / nm 2 It can be seen that there is no change in the size of the crystals within the range of As shown in (2) and (3) in 28, the nc-OS and The sizes of the crystal parts of the CAAC-OS and CAAC-OS are about 1.4 nm and 2.1 nm, respectively. I realize something.

[0331] Thus, in a-like OS, the growth of crystals can be observed by electron irradiation. On the other hand, the growth of the crystals in the nc-OS and CAAC-OS was hardly observed by electron irradiation. In other words, a-like OS is not seen in nc-OS and CAAC-OS. It can be seen that compared with S, it has a less stable structure.

[0332] In addition, because of the porosity, a-like OS is more resistant to vascular endothelial cell proliferation than nc-OS and CAAC-OS. Specifically, the density of the a-like OS is lower than that of a single crystal of the same composition. The density of nc-OS is 78.6% or more and less than 92.3% of that of CAAC. The density of the -OS is 92.3% or more and less than 100% of the density of a single crystal of the same composition. It is difficult to form an oxide semiconductor film having a density of less than 78% of that of the oxide semiconductor film.

[0333] For example, in an oxide semiconductor with an atomic ratio of In:Ga:Zn=1:1:1, The density of single crystal InGaZnO4 with a hexagonal crystal structure is 6.357 g / cm 3 It becomes. For example, in an oxide semiconductor having an atomic ratio of In:Ga:Zn=1:1:1, , the density of a-like OS is 5.0g / cm 3 More than 5.9g / cm 3 It is less than. For example, in an oxide semiconductor having an atomic ratio of In:Ga:Zn=1:1:1, The density of nc-OS and that of CAAC-OS are 5.9 g / cm 3 More than 6.3g / cm 3 It will be less than.

[0334] In addition, there are cases where single crystals with the same composition do not exist. In such cases, the composition may differ in any ratio. By combining single crystals, we estimate the density equivalent to a single crystal of the desired composition. The density corresponding to a single crystal of a desired composition can be determined by combining single crystals of different compositions. The weighted average of the proportion of It is preferable to estimate by combining different types of single crystals.

[0335] As described above, oxide semiconductors have various structures, each of which has various characteristics. The oxide semiconductor may be, for example, an amorphous oxide semiconductor, an a-like OS, an nc-OS, The CAAC-OS may be a laminated film having two or more kinds.

[0336] (Embodiment 4) In this embodiment, an example of a circuit using a transistor of one embodiment of the present invention is shown in FIG. Please refer to the following for explanation.

[0337] <Cross-sectional structure> FIG. 29A is a cross-sectional view of a semiconductor device of one embodiment of the present invention. In FIG. The 1-X2 direction indicates the channel length direction, and the Y1-Y2 direction indicates the channel width direction. The semiconductor device shown in FIG. 2 has a transistor 2200 using a first semiconductor material in the lower part and In FIG. 29A, a transistor 2100 using a second semiconductor material is provided in the first region. As the transistor 2100 using the second semiconductor material, the transistor 2100 shown in the above embodiment may be used. The left side of the dashed line is the channel of the transistor. The left side is a cross section in the longitudinal direction, and the right side is a cross section in the channel width direction.

[0338] The first and second semiconductor materials preferably have different band gaps. For example, the first semiconductor material may be a semiconductor material other than an oxide semiconductor (silicon (including strained silicon)). (including germanium, silicon germanium, silicon carbide, gallium arsenide, aluminum arsenide) The second semiconductor is a The body material can be an oxide semiconductor. On the other hand, transistors using oxide semiconductors can operate at high speed. The transistor can be an excellent substrate by applying the transistor exemplified in the above embodiment. It is possible to obtain threshold characteristics and make a fine transistor. The fast switching speed allows for high-speed operation, and the low off-state current reduces leakage current.

[0339] The transistor 2200 may be an n-channel transistor or a p-channel transistor. Either transistor or transistors may be used, and an appropriate transistor may be used depending on the circuit. In addition to using a transistor according to one embodiment of the present invention using a nitride semiconductor, other materials and structures are not required. For example, the specific configuration of the semiconductor device is not necessarily limited to that shown here.

[0340] In the structure shown in FIG. 29A, an insulator 2201 and an insulator The transistor 2100 is connected via the transistor 2207. A plurality of wirings 2202 are provided between the transistor 2100 and the A plurality of plugs 2203 embedded in the substrate are used to connect the wiring provided in the upper and lower layers. The electrodes are electrically connected to an insulator 2204 that covers the transistor 2100. A wiring 2205 is provided on the insulator 2204 .

[0341] In this way, by stacking two types of transistors, the area occupied by the circuit is reduced, Multiple circuits can be arranged at higher density.

[0342] Here, when a silicon-based semiconductor material is used for the transistor 2200 provided in the lower layer, The hydrogen in the insulator provided near the semiconductor film of the transistor 2200 is a silicon dung. This has the effect of terminating the ring bond and improving the reliability of the transistor 2200. When an oxide semiconductor is used for the transistor 2100 provided in the upper layer, the transistor 21 Hydrogen in the insulator provided near the semiconductor film of 00 generates carriers in the oxide semiconductor. This may be one of the factors that reduces the reliability of the transistor 2100. Therefore, the upper layer of the transistor 2200 using a silicon-based semiconductor material is oxidized. When the transistor 2100 using a semiconductor is stacked, hydrogen diffusion between the transistors may occur. It is particularly effective to provide an insulator 2207 having a function of preventing the above-mentioned. 7, the reliability of the transistor 2200 is improved by trapping hydrogen in the lower layer. In addition, the diffusion of hydrogen from the lower layer to the upper layer is suppressed, so that the transistor 2100 At the same time, reliability can be improved.

[0343] The insulator 2207 may be, for example, aluminum oxide, aluminum oxynitride, or gallium oxide. , gallium oxide nitride, yttrium oxide, yttrium oxide nitride, hafnium oxide, Hafnium nitride, yttria stabilized zirconia (YSZ), etc. can be used.

[0344] In addition, a transistor 2100 including an oxide semiconductor film is formed so as to cover the transistor 2100. It is preferable to form a blocking film having a function of preventing hydrogen diffusion on the substrate 2100. The blocking film can be made of the same material as the insulator 2207, and in particular, It is preferable to use aluminum oxide. The aluminum oxide film is resistant to impurities such as hydrogen and moisture. It has a high blocking effect, preventing both pure substances and oxygen from passing through the membrane. Therefore, an aluminum oxide film is used as the blocking film covering the transistor 2100. This prevents oxygen from being released from the oxide semiconductor film included in the transistor 2100. In addition, it is possible to prevent water and hydrogen from being mixed into the oxide semiconductor film. The locking membrane may be used by laminating the insulator 2204 or by applying a layer of the insulator 2204 to the underside of the insulator 2204. It may also be provided in.

[0345] It should be noted that the transistor 2200 is not limited to a planar type transistor, but may be of various types. It can be a transistor. For example, it can be a transistor such as a FIN (fin) type, a TRI-GATE (tri-gate) type, etc. An example of the cross-sectional view in that case is shown in FIG. 29(D). An insulator 2212 is provided on the semiconductor substrate 2211. The semiconductor substrate 2211 has a thin convex portion (also referred to as a fin) at the tip. Note that an insulator may be provided on the convex portion. The insulator functions as a mask for preventing the semiconductor substrate 2 211 from being etched when forming the convex portion. Note that the convex portion does not necessarily have a thin tip. For example, it may be a convex portion having a substantially rectangular parallelepiped shape, or a convex portion having a thick tip. A gate insulator 2214 is provided on the convex portion of the semiconductor substrate 2211, and a gate electrode 2213 is provided thereon. Source regions and drain regions 2215 are formed in the semiconductor substrate 2211. Here, an example in which the semiconductor substrate 2211 has a convex portion is shown, but the semiconductor device according to one aspect of the present invention is not limited to this. For example, an SOI substrate may be processed to form a semiconductor region having a convex portion.

[0346] <Circuit configuration example> In the above configuration, various circuits can be configured by appropriately connecting the electrodes of the transistor 2100 and the transistor 2200. Hereinafter, an example of a circuit configuration that can be realized by using the semiconductor device according to one aspect of the present invention will be described.

[0347] <CMOS inverter circuit> The circuit diagram shown in FIG. 29(B) is a so-called CMO in which a p-channel type transistor 2200 and an n-channel type transistor 2100 are connected in series, and their gates are connected. 4 shows the configuration of an S inverter.

[0348] <CMOSアナログスイッチ> In addition, the circuit diagram shown in FIG. 29C shows the transistors 2100 and 2200. In FIG. 29(A), the source and drain of each of the transistors are connected. The X2 direction indicates the channel length direction, and the Y1-Y2 direction indicates the channel width direction. This allows it to function as a so-called CMOS analog switch.

[0349] <Example of storage device> By using a transistor according to one embodiment of the present invention, it is possible to preserve memory contents even in a state where power is not supplied. FIG. 30 shows an example of a semiconductor device (memory device) that can hold data and has no limit on the number of times it can be written. As shown in.

[0350] The semiconductor device shown in FIG. 30A includes a transistor 3200 using a first semiconductor material and a The semiconductor device includes a transistor 3300 using the semiconductor material of the second embodiment, and a capacitor element 3400 . Note that the transistor described in Embodiments 1 and 2 is used as the transistor 3300. There can be.

[0351] 30B is a cross-sectional view of the semiconductor device shown in FIG. In the example shown, a back gate is provided in the transistor 3300. It is also possible to adopt a configuration in which no.

[0352] FIG. 30(A) shows a configuration in which the intermediate layer 2210 has electrical conductivity. In the case where 2210 is insulating, the transistor is connected to the wiring 3005 as shown in FIG. 2200 and transistor 2100 are connected.

[0353] The transistor 3300 is a transistor in which a channel is formed in a semiconductor layer having an oxide semiconductor. Since the off-state current of the transistor 3300 is small, This means that the memory contents can be retained for a long period of time without requiring a refresh operation. Alternatively, the frequency of refresh operations can be extremely low. This makes it possible to sufficiently reduce power consumption.

[0354] In FIG. 30A, a first wiring 3001 is electrically connected to a source electrode of a transistor 3200. The second wiring 3002 is electrically connected to the drain electrode of the transistor 3200. The third wiring 3003 is connected to the source electrode or drain of the transistor 3300. The fourth wiring 3004 is electrically connected to one of the drain electrodes of the transistor 3300. The gate electrode of the transistor 3200 is electrically connected to the transistor The other of the source electrode and the drain electrode of the transistor 3300 and the capacitor 3400 The fifth wiring 3005 is electrically connected to one of the electrodes of the capacitor 3400. are electrically connected.

[0355] In the semiconductor device shown in FIG. 30A, the potential of the gate electrode of the transistor 3200 can be held. By taking advantage of this feature, it is possible to write, store, and read information as follows: do.

[0356] The writing and holding of information will be described. First, the potential of the fourth wiring 3004 is changed by a transistor. The transistor 3300 is turned on by applying a potential to the transistor 3300. As a result, the potential of the third wiring 3003 is applied to the gate electrode of the transistor 3200 and and the capacitance element 3400. That is, the gate of the transistor 3200 is provided with a predetermined A charge of 10 ... Either a low level charge or a high level charge is given. After that, the potential of the fourth wiring 3004 is set to a potential at which the transistor 3300 is turned off. By turning off the transistor 3300, the gate of the transistor 3200 The charge applied to is retained (retention).

[0357] Since the off-state current of the transistor 3300 is extremely small, the gate The charge is retained for a long period of time.

[0358] Next, reading of information will be described. A predetermined potential (constant potential) is applied to the first wiring 3001. When an appropriate potential (read potential) is applied to the fifth wiring 3005 in this state, the transistor Depending on the amount of charge held in the gate of the transistor 3200, the second wiring 3002 takes on different potentials. In general, if the transistor 3200 is an n-channel type, the gate of the transistor 3200 is The apparent threshold voltage V when a high-level charge is applied to the port electrode th_H teeth, When a low-level charge is applied to the gate electrode of transistor 3200, Threshold V th_L Here, the apparent threshold voltage is the threshold voltage at This refers to the potential of the fifth wiring 3005 required to turn on the transistor 3200. Therefore, the potential of the fifth wiring 3005 is V th_H and V th_L The potential between By setting V0, the charge applied to the gate of the transistor 3200 can be determined. For example, in a write operation, if a high-level charge is applied, the fifth wiring The potential of 3005 is V0 (>V th_H ), then transistor 3200 is in the "on state." When a low-level charge is applied, the potential of the fifth wiring 3005 becomes V0 ( <V th_L ), transistor 3200 remains in the "off state." Therefore, the stored data can be read by determining the potential of the second wiring 3002. can be done.

[0359] When memory cells are arranged in an array, only the information in a desired memory cell can be read. If the information is not read out, the gate state is not affected. The potential at which transistor 3200 is in the "off state" regardless of the th_H twist A small potential may be applied to the fifth wiring 3005. The potential at which the transistor 3200 is in the "on" state, that is, V th_L Larger current The position can be given to the fifth wiring 3005.

[0360] The semiconductor device shown in FIG. 30C is different from the semiconductor device shown in FIG. 30A in that the transistor 3200 is not provided. In this case, the writing and holding of information is performed in the same manner as above. It is possible.

[0361] Next, the reading of information will be described. When the transistor 3300 is turned on, The third wiring 3003 in the free state and the capacitor element 3400 are electrically connected to each other. Charge is redistributed among the capacitor elements 3400. As a result, the potential of the third wiring 3003 changes. The change in the potential of the third wiring 3003 is proportional to the change in the potential of the first terminal of the capacitor 3400 ( Alternatively, it takes a different value depending on the charge stored in the capacitor element 3400.

[0362] For example, the potential of the first terminal of the capacitance element 3400 is V, the capacitance of the capacitance element 3400 is C, The capacitance component of the third wiring 3003 before the charge is redistributed is CB. If the potential is VB0, the potential of the third wiring 3003 after the charge is redistributed is (CB× VB0+C×V) / (CB+C). Therefore, the state of the memory cell is If the potential of the first terminal of the transistor 3400 has two states, V1 and V0 (V1>V0), The potential of the third wiring 3003 when the potential V1 is held (=(CB×VB0+C×V1) / (CB+C)) is the potential of the third wiring 3003 when the potential V0 is held (=(C B×VB0+C×V0) / (CB+C)).

[0363] Then, the potential of the third wiring 3003 is compared with a predetermined potential, thereby reading out information. can be done.

[0364] In this case, the first semiconductor material is applied to a drive circuit for driving the memory cell. A transistor is used, and a transistor in which a second semiconductor material is applied as the transistor 3300 is used. The transistor may be laminated on the driver circuit.

[0365] In the semiconductor device described in this embodiment, an off-state current is low when an oxide semiconductor is used for a channel formation region. By using extremely small transistors, memory contents can be retained for an extremely long period of time. In other words, the refresh operation is unnecessary or the refresh operation is possible. This allows the frequency of operation to be reduced significantly, resulting in a significant reduction in power consumption. In addition, when there is no power supply (however, it is preferable that the potential is fixed), However, it is possible to retain the stored contents for a long period of time.

[0366] In addition, the semiconductor device described in this embodiment does not require a high voltage for writing data. There is no problem with degradation of the capacitance. For example, unlike conventional non-volatile memory, the floating gate Since there is no need to inject electrons into the floating gate or extract electrons from the floating gate, The problem of deterioration of the gate insulating layer does not occur at all. The device does not have the limit on the number of times it can be rewritten, which is a problem with conventional non-volatile memory, and is reliable. Furthermore, the on and off states of transistors allow the Since writing is performed, high speed operation can be easily achieved.

[0367] In this specification, the terms "active elements" and "passive elements" are used interchangeably. For all terminals of devices (capacitive elements, resistive elements, etc.), the connection destination is not specified. However, a person skilled in the art may be able to configure one aspect of the invention. Even if the destination is not specified, one aspect of the invention is clear. When the contents are described in this specification, etc., one aspect of the invention that does not specify a connection destination is the same as the embodiment of the present specification. In particular, if the terminal is connected to multiple If multiple cases are possible, there is no need to limit the connection of the terminal to a specific location. Therefore, active elements (transistors, diodes, etc.) and passive elements (capacitors, resistors, etc.) By specifying the connection destinations of only some of the terminals of a device (such as a semiconductor device), This may constitute an aspect of the invention.

[0368] In this specification and the like, if at least the connection destination of a certain circuit is specified, it is understood by those skilled in the art that If you are a person who has experience in the field of electronics, you may be able to identify the invention. In some cases, a person skilled in the art may be able to identify an invention by at least specifying the function. In other words, if a function is specified, it can be said that one aspect of the invention is clear. It may be possible to determine that one aspect of the invention is described in the present specification. Therefore, even if the function of a circuit is not specified, if the connection destination is specified, it can be considered as an embodiment of the invention. and can constitute one embodiment of the invention. For a certain circuit, even if the connection destination is not specified, if the function is specified, it can be considered as one aspect of the invention. What is disclosed can constitute an embodiment of the invention.

[0369] In this specification, etc., in a drawing or text described in a certain embodiment, It is possible to extract a part of the invention and use it as an embodiment of the invention. If a figure or text describing a certain part is included, the figure or text of that part is taken out. The above-mentioned contents are disclosed as one aspect of the invention and constitute one aspect of the invention. Therefore, for example, active elements (transistors, diodes, etc.) etc.), wiring, passive elements (capacitive elements, resistive elements, etc.), conductive layers, insulating layers, semiconductor layers, organic Drawings showing one or more materials, inorganic materials, components, devices, operating methods, manufacturing methods, etc. In the text or drawings, a part thereof may be extracted to form one aspect of the invention. For example, from a circuit diagram composed of N (N is an integer) circuit elements (transistors, capacitor elements, etc.), it is possible to extract M (M is an integer, M < N) circuit elements (transistors, capacitor elements, etc.) to form one aspect of the invention. As another example, from a cross-sectional view composed of N (N is an integer) layers, it is possible to extract M (M is an integer, M < N) layers to form one aspect of the invention. As yet another example, from a flowchart composed of N (N is an integer) elements, it is possible to extract M (M is an integer, M < N) elements to form one aspect of the invention.

[0370] <Imaging device> Hereinafter, an imaging device according to one aspect of the present invention will be described.

[0371] FIG. 31(A) is a plan view showing an example of an imaging device 200 according to one aspect of the present invention. The imaging device 200 includes a pixel unit 210, a peripheral circuit 260 for driving the pixel unit 210, and peripheral circuits 270, 280, and 290. The pixel unit 210 has a plurality of pixels 211 arranged in a matrix of p rows and q columns (p and q are integers of 2 or more). The peripheral circuits 260, 270, 280, and 290 are each connected to a plurality of pixels 211 and have a function of supplying signals for driving the plurality of pixels 211. In this specification, etc., all of the peripheral circuits 260, 270, 280, and 290 may be referred to as "peripheral circuits" or "driving circuits". ​ For example, peripheral circuit 260 may be considered a part of the peripheral circuit.

[0372] The imaging device 200 preferably also includes a light source 291. The light source 291 emits detection light P It can emit 1.

[0373] The peripheral circuits include at least a logic circuit, a switch, a buffer, an amplifier, or a converter. The peripheral circuits may be disposed on the substrate on which the pixel portion 210 is formed. In addition, the peripheral circuits may be implemented in part or in whole using semiconductor devices such as ICs. The peripheral circuits are peripheral circuit 260, peripheral circuit 270, peripheral circuit 280 and peripheral circuit 29. One or more of the 0's may be omitted.

[0374] As shown in FIG. 31B, in the pixel section 210 of the imaging device 200, By arranging the pixels 211 at an angle, the pixel size in the row direction and the pixel size in the pixel area can be increased. The pixel interval (pitch) in the column direction can be shortened. This can further improve the quality of the captured images.

[0375] <Pixel configuration example 1> The imaging device 200 has a pixel 211 that is composed of a plurality of sub-pixels 212. The pixel 212 is combined with a filter (color filter) that transmits light of a specific wavelength band. By this, it is possible to obtain information for realizing a color image display.

[0376] FIG. 32A is a plan view showing an example of a pixel 211 for acquiring a color image. The pixel 211 shown in FIG. 32(A) is provided with a color filter that transmits the red (R) wavelength band. The subpixel 212 (hereinafter also referred to as "subpixel 212R") transmits light in the green (G) wavelength band. A subpixel 212 (hereinafter also referred to as "subpixel 212G") provided with a color filter A subpixel 212 (hereinafter, referred to as a “subpixel”) is provided with a color filter that transmits light in the blue (B) wavelength band. The sub-pixel 212 can function as a photosensor. This can be done.

[0377] The subpixels 212 (subpixels 212R, 212G, and 212B) are connected to the wiring 23 1, electrically connected to wiring 247, wiring 248, wiring 249, and wiring 250. The pixel 212R, the sub-pixel 212G, and the sub-pixel 212B are each connected to an independent wiring 25 3. In this specification, for example, The wiring 248 and the wiring 249 are respectively represented as wiring 248[n] and wiring 249[n]. For example, the wiring 253 connected to the pixel 211 in the mth column is designated as wiring 253[m]. In FIG. 32A, the sub-pixel 212R of the pixel 211 in the m-th column is written as follows: The wiring 253 connected to the subpixel 212G is disposed as wiring 253[m]R. The wiring 253 connected to the line 253[m]G and the subpixel 212B is referred to as a wiring 253[m]B. The subpixel 212 is electrically connected to the peripheral circuit via the wiring.

[0378] In addition, the imaging device 200 has color filters that transmit the same wavelength band for adjacent pixels 211. The sub-pixels 212 in which the transistors are provided are electrically connected to each other via switches. 32(B), arranged in n rows (n is an integer between 1 and p) and m columns (m is an integer between 1 and q) A sub-pixel 212 of the pixel 211 and a sub-pixel 213 arranged in the n+1th row and the mth column adjacent to the pixel 211 32B shows an example of a connection of the sub-pixels 212 of the pixel 211. The sub-pixel 212R arranged in the n+1th row and the mth column is switched In addition, the sub-pixel 212G arranged in the nth row and the mth column is connected via the n+1 The sub-pixels 212G arranged in rows and columns m are connected via the switches 202. The sub-pixel 212B arranged in row m and column m and the sub-pixel 212B arranged in row (n+1) and column m are switched. The two are connected via a switch 203.

[0379] The color filters used for the subpixels 212 are not limited to red (R), green (G), and blue (B). The color filters transmit cyan (C), yellow (Y) and magenta (M) light respectively. A single pixel 211 may have three sub-pixels for detecting light of different wavelength bands. By providing 212, a full color image can be obtained.

[0380] Alternatively, color filters that transmit red (R), green (G) and blue (B) light are provided. In addition to the sub-pixel 212, a sub-pixel having a color filter that transmits yellow (Y) light is provided. Alternatively, pixel 211 may be used with pixel 212, or with cyan (C), yellow (Y In addition to the subpixel 212 provided with a color filter that transmits light of red (A) and magenta (M), The pixel 21 has a sub-pixel 212 provided with a color filter that transmits blue (B) light. A single pixel 211 may include sub-pixels 211 for detecting light of four different wavelength bands. By providing the second filter 12, the color reproducibility of the captured image can be further improved.

[0381] Also, for example, in FIG. 32A, a sub-pixel 212 detects the red wavelength band, The ratio of the number of sub-pixels 212 that detect the blue wavelength band and the number of sub-pixels 212 that detect the blue wavelength band ( or light receiving area ratio) does not have to be 1:1:1. For example, The Bayer array may be used with red:green:blue=1:2:1. The light area ratio may be red:green:blue=1:6:1.

[0382] The number of sub-pixels 212 provided in the pixel 211 may be one, but it is preferable that the number is two or more. By providing two or more sub-pixels 212 that detect the same wavelength band, redundancy is increased, and the imaging device This can improve the reliability of the device 200.

[0383] In addition, IR (IR: Infrared) filters absorb or reflect visible light and transmit infrared light. By using a filter, it is possible to realize an imaging device 200 that detects infrared light.

[0384] In addition, ND (Neutral Density) filters are used. This prevents output saturation that occurs when a large amount of light is incident on the photoelectric conversion element (light receiving element). By combining ND filters with different light reduction levels, This allows the dynamic range of the device to be increased.

[0385] In addition to the above-mentioned filter, a lens may be provided in the pixel 211. An example of the arrangement of the pixel 211, the filter 254, and the lens 255 will be described with reference to a cross-sectional view. By providing the lens 255, the photoelectric conversion element can efficiently receive incident light. Specifically, as shown in FIG. 33A, a lens 255 and a filter 25 formed in a pixel 211 4 (filter 254R, filter 254G and filter 254B), and pixel circuit 2 30 or the like, light 256 can be made incident on the photoelectric conversion element 220.

[0386] However, as shown in the area surrounded by the dashed line, a part of the light 256 indicated by the arrow is Therefore, as shown in Figure 33(B), A lens 255 and a filter 254 are disposed on the conversion element 220 side. It is preferable that the light 256 is received efficiently from the photoelectric conversion element 220 side. By making the light incident on the photoelectric conversion element 220, the imaging device 200 with high detection sensitivity is provided. can be done.

[0387] As the photoelectric conversion element 220 shown in FIG. 33, a pn-type junction or a pin-type junction is formed. A photoelectric conversion element may also be used.

[0388] In addition, the photoelectric conversion element 220 is made of a material having a function of absorbing radiation and generating electric charges. The material having the function of absorbing radiation and generating electric charges may be a sintered material. Iron, lead iodide, mercury iodide, gallium arsenide, cadmium telluride, cadmium zinc alloy etc.

[0389] For example, if selenium is used for the photoelectric conversion element 220, in addition to visible light, ultraviolet light, and infrared light, Photoelectric conversion element 2 that has a light absorption coefficient over a wide wavelength range, including X-rays and gamma rays 20 can be achieved.

[0390] Here, one pixel 211 included in the imaging device 200 has a sub-pixel 212 shown in FIG. 2, may include a subpixel 212 having a first filter.

[0391] <Pixel configuration example 2> In the following, a transistor using silicon and a transistor using an oxide semiconductor will be described. An example of forming a pixel using the above will be described.

[0392] 34(A) and 34(B) are cross-sectional views of elements constituting the imaging device.

[0393] The imaging device shown in FIG. 34(A) is a silicon-based transistor provided on a silicon substrate 300. A transistor using an oxide semiconductor that is stacked on the transistor 351. A transistor 352 and a transistor 353, and a transistor 354 provided on the silicon substrate 300. Each transistor includes a photodiode 360 ​​having an anode 361 and a cathode 362. The photodiodes 360 are electrically connected to various plugs 370 and wiring 371. The anode 361 of the photodiode 360 ​​has a low resistance region 363. 3 and has an electrical connection with plug 370 via.

[0394] The imaging device includes a transistor 351 and a photodiode 352 disposed on a silicon substrate 300. A layer 310 having an electrode 360 ​​and a layer 371 provided in contact with the layer 310. 20 and in contact with layer 320, and includes transistors 352 and 353. A layer 330 is provided in contact with the layer 330 and has wiring 372 and wiring 373. It has 40.

[0395] In the example of the cross-sectional view of FIG. 34(A), the transistor 3 is formed on the silicon substrate 300. The light receiving surface of the photodiode 360 ​​is disposed on the opposite side to the surface on which the photodiode 51 is formed. This configuration ensures an optical path without being affected by various transistors and wiring. Therefore, it is possible to form pixels with a high aperture ratio. Alternatively, the light receiving surface of the gate 360 ​​may be the same as the surface on which the transistor 351 is formed.

[0396] In addition, when a pixel is formed using a transistor, the layer 310 is Alternatively, the layer 310 may be omitted, and the pixel may be formed only by a transistor. .

[0397] In the cross-sectional view of FIG. 34(A), a photodiode 360 ​​provided in the layer 310 and a The transistor 330 can be formed so as to overlap with the transistor 330. In other words, the resolution of the imaging device can be increased.

[0398] FIG. 34B shows an imaging device in which a photodiode 365 is provided on the layer 340 side as a transistor. In FIG. 34B, for example, the layer 310 may have a structure in which The layer 320 includes a transistor 351 and a transistor 352 using silicon. 71, and the layer 330 includes a transistor 352 using an oxide semiconductor layer, and a transistor 3 53, and layer 340 includes photodiode 365, and photodiode 365 The semiconductor layer 63, the semiconductor layer 64, and the semiconductor layer 65 are formed. It is electrically connected to wiring 374 via 370.

[0399] By using the element configuration shown in FIG. 34B, the aperture ratio can be increased.

[0400] In addition, the photodiode 365 is made of an amorphous silicon film or a microcrystalline silicon film. A pin-type diode element or the like may be used. The photodiode 365 is an n-type semiconductor A layer 368, an i-type semiconductor layer 367, and a p-type semiconductor layer 366 are laminated in this order. It is preferable to use amorphous silicon for the i-type semiconductor layer 367. The p-type semiconductor layer 366 and the n-type semiconductor layer 368 are provided with dopants that impart their respective conductivity types. Amorphous silicon or microcrystalline silicon containing a dopant can be used. The photodiode 365, which uses silicon as a photoelectric conversion layer, has high sensitivity in the visible light wavelength range. It is highly sensitive to weak visible light.

[0401] This embodiment mode may be appropriately combined with other embodiment modes and examples shown in this specification. It is possible.

[0402] (Embodiment 5) <RFタグ> In this embodiment, an RF device including a transistor or a memory device described in the previous embodiment is The tag will be described with reference to FIG.

[0403] The RF tag in this embodiment has a memory circuit therein and stores necessary information in the memory circuit. In addition, information is exchanged with the outside world using non-contact means, such as wireless communication. Due to these characteristics, RF tags are used as individual devices to identify items by reading their individual information. It can be used for biometric authentication systems, etc. High reliability is required.

[0404] The structure of an RF tag will be described with reference to FIG. 35. FIG. 35 is a block diagram showing an example of the structure of an RF tag. FIG.

[0405] As shown in FIG. 35, an RF tag 800 includes a communicator 801 (also called an interrogator, reader / writer, etc.). 8, which receives a radio signal 803 transmitted from an antenna 802 connected to the The RF tag 800 also includes a rectifier circuit 805, a constant voltage circuit 806, and a demodulator circuit 804. 07, a modulation circuit 808, a logic circuit 809, a memory circuit 810, and a ROM 811. In addition, the reverse current of the transistor having the rectification effect included in the demodulation circuit 807 is sufficiently suppressed. A material capable of being used for the insulating layer 11 may be, for example, an oxide semiconductor. This suppresses the deterioration of the rectification effect caused by the reverse current and prevents the output of the demodulation circuit from becoming saturated. In other words, the output of the demodulation circuit relative to the input of the demodulation circuit can be made closer to linear. The data transmission format is a pair of coils arranged facing each other and communication is carried out by mutual induction. The electromagnetic coupling method uses electromagnetic fields to communicate, the electromagnetic induction method uses radio waves to communicate, The RF tag 800 shown in this embodiment can be used with any of these methods. It is also possible to use it for.

[0406] Next, the configuration of each circuit will be described. The antenna 804 is an antenna connected to the communication device 801. The rectifier circuit 802 is used to transmit and receive a radio signal 803 to and from the antenna 802. 05 is a rectifier for an input AC signal generated by receiving a radio signal through an antenna 804. For example, half-wave double voltage rectification is performed, and the rectified signal is smoothed by a capacitive element provided in the latter stage. The rectifier circuit 805 is a circuit for generating an input potential by rectifying the input side of the rectifier circuit 805. A limiter circuit may be provided on the output side. When the internally generated voltage is large, it is necessary to prevent a certain amount of power from being input to the downstream circuit. This is a circuit for controlling the

[0407] The constant voltage circuit 806 generates a stable power supply voltage from the input potential and supplies it to each circuit. The constant voltage circuit 806 may include a reset signal generating circuit. The reset signal generating circuit uses the stable rise of the power supply voltage to reset the logic circuit 80. This is a circuit for generating the reset signal for 9.

[0408] The demodulation circuit 807 demodulates the input AC signal by envelope detection to generate a demodulated signal. The modulation circuit 808 is a circuit for modulating the data output from the antenna 804. This is a circuit for performing modulation based on the

[0409] The logic circuit 809 is a circuit for analyzing and processing the demodulated signal. This is a circuit that holds input information, and includes a row decoder, column decoder, memory area, etc. The ROM 811 also stores a unique number (ID) and outputs it according to the processing. This is a circuit for this purpose.

[0410] It should be noted that the above-mentioned circuits can be appropriately selected or omitted as necessary.

[0411] Here, the memory circuit described in the above embodiment can be used as the memory circuit 810. The memory circuit of one embodiment of the present invention can retain data even when power is cut off. The memory circuit of one embodiment of the present invention can be suitably used for an RF tag. The power (voltage) required to write data is significantly smaller than that of conventional non-volatile memory. It is also possible not to cause a difference in the maximum communication distance during reading and writing. Further, it is possible to suppress malfunction or incorrect writing due to insufficient power during data writing.

[0412] Also, the memory circuit according to one aspect of the present invention can be used as a non-volatile memory, so it can also be applied to the ROM811. In that case, the producer prepares a command for writing data to the ROM811 separately and makes it impossible for the user to rewrite it freely. By shipping the product after the producer writes the unique number before shipping, it is possible to assign unique numbers not to all the manufactured RF tags, but only to the good products to be shipped, so that the unique numbers of the products after shipping do not become discontinuous, and customer management corresponding to the products after shipping becomes easy.

[0413] Note that this embodiment can be appropriately combined with other embodiments and examples shown in this specification.

[0414] (Embodiment 6) In this embodiment, a CPU including the memory device described in the previous embodiment will be described.

[0415] FIG. 36 is a block diagram showing a configuration of an example of a CPU using at least a part of the transistors described in the previous embodiment.

[0416] <Circuit diagram of CPU> The CPU shown in FIG. 36 has an ALU1191 (ALU: Arithmetic logic unit, arithmetic circuit), an ALU controller 1192, and an instruction ​​​​A timing decoder 1193, an interrupt controller 1194, and a timing controller 1195, register 1196, register controller 1197, bus interface 1 198, rewritable ROM 1199, and ROM interface 1189 The substrate 1190 may be a semiconductor substrate, an SOI substrate, a glass substrate, or the like. 199 and the ROM interface 1189 may be provided on a separate chip. The CPU shown in FIG. 36 is merely an example showing a simplified configuration. There are many different configurations depending on the application. For example, the CPU or arithmetic circuit shown in FIG. A configuration including the above is considered as one core, and multiple such cores are included, and each core operates in parallel. The number of bits that the CPU can handle in the internal arithmetic circuit and data bus is as follows: For example, it can be 8-bit, 16-bit, 32-bit, 64-bit, etc.

[0417] The instructions input to the CPU via the bus interface 1198 are The signal is input to the decoder 1193, decoded, and then passed to the ALU controller 1192, the interface Rupture Controller 1194, Register Controller 1197, Timing Controller Entered into 1195.

[0418] ALU controller 1192, interrupt controller 1194, register controller The controller 1197 and the timing controller 1195 control various Specifically, the ALU controller 1192 controls the operation of the ALU 1191. The interrupt controller 1194 also generates a signal for the CPU program. During execution, interrupt requests from external I / O devices and peripheral circuits are handled according to their priority and mask status. The register controller 1197 determines the address of the register 1196 and processes it. It generates a process and reads and writes to register 1196 according to the CPU state.

[0419] The timing controller 1195 also includes the ALU 1191 and the ALU controller 119 2, an instruction decoder 1193, an interrupt controller 1194, and It generates a signal to control the operation timing of the register controller 1197. The timing controller 1195 generates an internal clock signal based on the reference clock signal. The internal clock generating unit supplies an internal clock signal to the various circuits described above.

[0420] In the CPU shown in FIG. 36, a register 1196 is provided with a memory cell. The transistors described in any of the embodiments 1 to 3 can be used as the memory cells of the 1196. can.

[0421] In the CPU shown in FIG. 36, the register controller 1197 receives the According to the instruction, the holding operation is selected in the register 1196. In the memory cell of 96, data is held by a flip-flop or a capacitance Select whether to hold data by the element. When selected, a power supply voltage is applied to the memory cells in the register 1196. If data retention is selected in the capacitive element, rewriting data to the capacitive element This allows the supply of the power supply voltage to the memory cells in the register 1196 to be stopped. .

[0422] <Recording circuit> FIG. 37 is an example of a circuit diagram of a storage element that can be used as the register 1196. The memory element 1200 includes a circuit 1201 in which stored data is volatilized when the power is cut off, and a circuit 1202 in which stored data is volatilized when the power is cut off. A non-volatile circuit 1202, a switch 1203, a switch 1204, and a logic element The circuit includes a transistor 1206, a capacitor 1207, and a circuit 1220 having a selection function. 1202 includes a capacitor element 1208, a transistor 1209, and a transistor 1210. The memory element 1200 may include a diode, a resistor, an inductor, etc., as necessary. The semiconductor device may further include other elements such as a capacitor.

[0423] Here, the memory device described in the above embodiment can be used for the circuit 1202. When the supply of the power supply voltage to the memory element 1200 is stopped, the transistor 120 The gate of the transistor 9 is supplied with a ground potential (0V) or a potential that turns off the transistor 1209. For example, the first gate of the transistor 1209 is connected to the first gate of the transistor 1209 via a load such as a resistor. The configuration is such that the terminal block is grounded.

[0424] The switch 1203 uses a transistor 1213 of one conductivity type (for example, an n-channel type). The switch 1204 is configured as a transistor of the opposite conductivity type (for example, a p-channel type). An example using a transistor 1214 is shown. Here, the first terminal of the switch 1203 The input corresponds to one of the source and drain of the transistor 1213, and the second input of the switch 1203. The terminal of corresponds to the other of the source and drain of the transistor 1213, and the switch 1203 A control signal RD input to the gate of the transistor 1213 switches the first terminal and the second terminal Conduction or non-conduction between the terminals (i.e., the on or off state of the transistor 1213) The first terminal of the switch 1204 is connected to the source and drain of the transistor 1214. The second terminal of the switch 1204 corresponds to one of the inputs, and the second terminal of the switch 1204 corresponds to the source of the transistor 1214. The other drain of the switch 1204 is connected to the gate of the transistor 1214. The control signal RD determines whether conduction or non-conduction (i.e., truncation) occurs between the first and second terminals. The on or off state of transistor 1214 is selected.

[0425] One of the source and drain of the transistor 1209 is connected to a pair of electrodes of the capacitor 1208. The connection part is electrically connected to one of the gate electrodes of the transistor 1210 and the gate of the transistor 1210. The node M2 ​​is connected to the source or drain of the transistor 1210. The other is electrically connected to a wiring (for example, a GND line) that can supply 1203 (one of the source and drain of the transistor 1213). The second terminal of the switch 1203 (the source and drain of the transistor 1213) is connected to the The other terminal of the switch 1204 (one of the source and drain terminals of the transistor 1214) The second terminal of the switch 1204 (the source terminal of the transistor 1214) is electrically connected to the The other of the source and drain terminals is electrically connected to a wiring that can supply the power supply potential VDD. The second terminal of the switch 1203 (the other of the source and drain of the transistor 1213) ) and a first terminal of the switch 1204 (one of the source and drain of the transistor 1214 ), an input terminal of a logic element 1206, and one of a pair of electrodes of a capacitor 1207; are electrically connected. Here, the connection point is referred to as node M1. The other of the electrodes may be configured to have a constant potential input thereto. It can be configured so that a power supply potential (GND, etc.) or a high power supply potential (VDD, etc.) is input. The other of the pair of electrodes of the capacitor 1207 is connected to a line that can supply a low power supply potential. The other of the pair of electrodes of the capacitor 1208 is electrically connected to a line (for example, a GND line). For example, a low power supply potential (GND, etc.) can be input. ) or a high power supply potential (such as VDD) can be input to the capacitance element 120. The other of the pair of electrodes 8 is connected to a wiring capable of supplying a low power supply potential (for example, GND The power supply is electrically connected to the power supply line.

[0426] The capacitors 1207 and 1208 are used to reduce parasitic capacitance of transistors and wirings. It is possible to omit it by making active use of it.

[0427] A control signal WE is input to a first gate (first gate electrode) of the transistor 1209. The switch 1203 and the switch 1204 are connected to a control signal RD, which is different from the control signal WE. A conductive state or a non-conductive state between the first terminal and the second terminal is selected by When the first terminal and the second terminal of one switch are in a conductive state, the first terminal and the There is no continuity between the two terminals.

[0428] In the transistor 1209 in FIG. 37, the second gate (second gate electrode: back The first gate is connected to a control signal WE, and the second gate is connected to a control signal WE. A control signal WE2 can be input to the output. The control signal WE2 is a signal with a constant potential. The constant potential may be, for example, a ground potential GND or the solenoid potential of the transistor 1209. At this time, the control signal WE2 is set to a potential smaller than the base potential of the transistor. This is the potential signal for controlling the threshold voltage of 1209. In addition, the control signal WE2 is the same potential signal as the control signal WE. The transistor 1209 may be a transistor without a second gate. A resistor can also be used.

[0429] The other of the source and drain of the transistor 1209 is connected to a data register 1204. In FIG. 36, the signal output from the circuit 1201 corresponds to the The example shown is input to the other of the source and drain of the switch 1203. The signal output from the second terminal (the other of the source and drain of the transistor 1213) is The logic value is inverted by the logic element 1206 to become an inverted signal, and the inverted signal is output via the circuit 1220. The signal is then input to the circuit 1201.

[0430] In FIG. 37, the second terminal of the switch 1203 (the source and drain of the transistor 1213) The signal output from the other of the two trains is routed through logic element 1206 and circuit 1220. The second terminal of the switch 1203 is connected to the first terminal of the switch 1203. The signal output from the other of the source and drain of the transistor 1213 is inverted. For example, the following may be included in the circuit 1201: When there is a node that holds a signal with the inverted logical value of the signal input from the input terminal The second terminal of the switch 1203 (the other of the source and drain of the transistor 1213) A signal output from the input terminal can be input to the node.

[0431] In addition, in FIG. 37, among the transistors used in the memory element 1200, The transistors other than the transistor 1209 are formed of a layer or a substrate 119 made of a semiconductor other than an oxide semiconductor. 0. For example, a silicon layer or The transistor may have a channel formed in a silicon substrate. All the transistors used in 1200 are transistors whose channels are formed in an oxide semiconductor layer. Alternatively, the memory element 1200 may include any other element other than the transistor 1209. The other transistors may include a transistor in which a channel is formed using an oxide semiconductor layer. The transistor has a channel formed in a layer or substrate 1190 made of a semiconductor other than an oxide semiconductor. Alternatively, the transistor may be a transistor that is connected to the gate of the transistor.

[0432] For example, a flip-flop circuit can be used for the circuit 1201 in FIG. The logic element 1206 may be, for example, an inverter or a clocked inverter. It is possible.

[0433] In the semiconductor device according to one embodiment of the present invention, while a power supply voltage is not supplied to the memory element 1200, The data stored in the circuit 1201 is transferred to the capacitor 120 provided in the circuit 1202. It can be held by 8.

[0434] Further, a transistor in which a channel is formed in an oxide semiconductor layer has an extremely small off-state current. For example, the off-state current of a transistor in which a channel is formed in an oxide semiconductor layer is The off-state current is significantly lower than that of a transistor whose channel is formed in silicon. Therefore, by using this transistor as the transistor 1209, the memory element 1 Even when the power supply voltage is not supplied to 200, the signal held in the capacitance element 1208 remains constant for a long period of time. In this way, the memory element 1200 can maintain the stored contents (data) even when the supply of the power supply voltage is stopped. It is possible to hold the data.

[0435] In addition, by providing the switches 1203 and 1204, the precharge operation Since the circuit 1201 is a memory element that performs the above-mentioned operation after the power supply voltage is restarted, This shortens the time it takes to restore the original data.

[0436] In the circuit 1202, the signal held by the capacitor 1208 is The power supply voltage to the memory element 1200 is then restarted. After that, the signal held by the capacitance element 1208 is converted into the state of the transistor 1210 ( The state can be converted to an ON state or an OFF state and read out from the circuit 1202. Therefore, even if the potential corresponding to the signal held in the capacitance element 1208 fluctuates slightly, the original signal can be read out accurately.

[0437] Such a memory element 1200 may be a register or a cache memory of a processor. By using it in a storage device, it is possible to prevent data loss in the storage device due to a power supply interruption. In addition, after the supply of power voltage is resumed, the state before the power supply was stopped can be restored in a short time. Therefore, the entire processor, or one or more components of the processor, Since the power supply can be stopped for a short period of time in multiple logic circuits, power consumption can be reduced. It can be suppressed.

[0438] In this embodiment, the memory element 1200 is used as a CPU. The 200 is equipped with a DSP (Digital Signal Processor), custom L SI, PLD (Programmable Logic Device) and other LSIs, R It can also be applied to F (Radio Frequency) tags.

[0439] This embodiment mode may be appropriately combined with other embodiment modes and examples shown in this specification. It is possible.

[0440] (Embodiment 7) In this embodiment, a structural example of a display device using a transistor according to one embodiment of the present invention will be described. explain.

[0441] <Display device circuit configuration example> FIG. 38A is a top view of a display device according to one embodiment of the present invention, and FIG. A pixel circuit that can be used when a liquid crystal element is applied to a pixel of a display device of one embodiment will be described. FIG 38C is a circuit diagram showing a configuration of a pixel of a display device according to one embodiment of the present invention. FIG. 1 is a circuit diagram illustrating a pixel circuit that can be used when an organic EL element is applied. .

[0442] The transistor disposed in the pixel portion can be formed according to any one of the first to third embodiments. In addition, since the transistor can be easily made into an n-channel type, the driver circuit can be made of n-channel A part of the driver circuit that can be configured with a channel transistor is connected to the transistor of the pixel portion. In this manner, the transistor shown in the above embodiment is formed in the pixel portion and the driver circuit. By using the photodiode, a highly reliable display device can be provided.

[0443] An example of a top view of an active matrix display device is shown in FIG. On the display 700, a pixel section 701, a first scanning line driving circuit 702, a second scanning line driving circuit 70 3, a signal line driver circuit 704. A plurality of signal lines are connected to the pixel portion 701. 704, and a plurality of scanning lines are connected to the first scanning line driving circuit 702 and the second scanning line driving circuit 703. The scanning line driving circuit 703 is extended from the scanning line driving circuit 703. In each of the display devices, pixels each having a display element are arranged in a matrix. The substrate 700 is a connection part for FPC (Flexible Printed Circuit) etc. It is connected to a timing control circuit (also called a controller or control IC) via

[0444] In FIG. 38A, a first scanning line driver circuit 702, a second scanning line driver circuit 703, a signal line The driver circuit 704 is formed on the same substrate 700 as the pixel portion 701. The number of components, such as the drive circuits, that are required can be reduced, leading to cost reduction. If a driver circuit is provided outside the 00, the wiring must be extended, and the number of connections between the wiring increases. When a driver circuit is provided on the same substrate 700, the number of connections between the wirings can be reduced. This can improve the reliability or the yield. Any one of the circuit 702, the second scanning line driver circuit 703, and the signal line driver circuit 704 is connected to the substrate 70. 0 or provided outside the substrate 700.

[0445] <Liquid crystal display device> An example of the circuit configuration of a pixel is shown in FIG. 38(B). Here, a VA type liquid crystal display is used as an example. 4 shows a pixel circuit that can be applied to a pixel of a display device.

[0446] This pixel circuit can be applied to a configuration in which one pixel has multiple pixel electrode layers. The pixel electrode layer is connected to different transistors, and each transistor is driven by a different gate signal. This allows individual pixels of a multi-domain pixel to be The signals applied to the electrode layers can be controlled independently.

[0447] The scan line 712 of the transistor 716 and the scan line 713 of the transistor 717 have different On the other hand, the signal line 714 is separated so that a gate signal can be applied. The transistor 716 and the transistor 717 share the same The transistor 717 can be any of the transistors described in any of the embodiments 1 to 3. This makes it possible to provide a highly reliable liquid crystal display device.

[0448] The transistor 716 is electrically connected to a first pixel electrode. The second pixel electrode is electrically connected to the first pixel electrode 7. The first pixel electrode and the second pixel electrode are The first pixel electrode and the second pixel electrode are separated from each other. For example, the first pixel electrode may be V-shaped.

[0449] The gate electrode of the transistor 716 is connected to the scanning line 712, and the gate The gate electrode is connected to a scanning line 713. Different gate signals are applied to the scanning lines 712 and 713. By applying a signal to the transistor 716 and the transistor 717, the operation timing is made different. The orientation of the molecule can be controlled.

[0450] In addition, the capacitance wiring 710, the gate insulating layer functioning as a dielectric, and the first pixel electrode layer or A storage capacitor may be formed by a capacitor electrode electrically connected to the second pixel electrode layer.

[0451] In the multi-domain design, one pixel has a first liquid crystal element 718 and a second liquid crystal element 719. The first liquid crystal element 718 is composed of a first pixel electrode layer, a counter electrode layer, and a liquid crystal layer therebetween. The second liquid crystal element 719 is composed of a second pixel electrode layer, a counter electrode layer, and a liquid crystal layer therebetween. can be.

[0452] Note that the pixel circuit shown in FIG. 38(B) is not limited to this. The pixel circuit is newly equipped with switches, resistors, capacitors, transistors, sensors, or logic Circuits etc. may be added.

[0453] <Organic EL display device> Another example of the circuit configuration of a pixel is shown in FIG. 38(C). 3 shows the pixel structure of the device.

[0454] In an organic EL element, when a voltage is applied to the light-emitting element, electrons are emitted from one of a pair of electrodes. Holes are injected from the other side into the layer containing the light-emitting organic compound, causing a current to flow. The electrons and holes recombine to form an excited state in the light-emitting organic compound, which When the excited state of the electron returns to the ground state, light is emitted. The element is called a current-excited light-emitting element.

[0455] FIG. 38C is a diagram showing an example of an applicable pixel circuit. This example shows how two transistors are used in one pixel. The pixel circuit is a digital time scale. A tonal drive can be applied.

[0456] Regarding the configuration of an applicable pixel circuit and the operation of pixels when digital time gray scale driving is applied, I will explain this in more detail.

[0457] The pixel 720 includes a switching transistor 721, a driving transistor 722, and a light-emitting element The switching transistor 721 has a gate electrode 724 and a capacitor element 723. The gate electrode layer is connected to the scanning line 726, and the first electrode (the source electrode layer and the drain electrode layer) One of the electrodes (the source electrode layer and the drain electrode layer) is connected to a signal line 725, and the second electrode (the other of the source electrode layer and the drain electrode layer) is connected to a signal line 725. ) is connected to the gate electrode layer of the driving transistor 722. In the semiconductor device 22, the gate electrode layer is connected to a power supply line 727 through a capacitor element 723, and the first electrode is The second electrode is connected to the first electrode (pixel electrode) of the light-emitting element 724. The second electrode of the light emitting element 724 corresponds to a common electrode 728. It is electrically connected to a common potential line formed on the substrate.

[0458] The switching transistor 721 and the driving transistor 722 are the same as those in the first embodiment. The transistors described in the sections 1 to 3 can be appropriately used. An EL display device can be provided.

[0459] The potential of the second electrode (common electrode 728) of the light-emitting element 724 is set to a low power supply potential. The power supply potential is a potential lower than the high power supply potential supplied to the power supply line 727, for example, GND , 0V, etc. can be set as the low power supply potential. The high power supply potential and the low power supply potential are set so that the potential difference is equal to or greater than the threshold voltage. By applying a voltage to the light emitting element 724, a current flows through the light emitting element 724, causing it to emit light. The forward voltage in 4 refers to the voltage required to achieve the desired brightness, and must be at least the forward threshold. Includes low-value voltages.

[0460] The capacitance element 723 can be omitted by substituting the gate capacitance of the driving transistor 722. It can be omitted.

[0461] Next, a signal input to the driving transistor 722 will be described. In this case, the driving transistor 722 is in two states: fully on or fully off. A video signal such as the above is input to the driving transistor 722. In order to operate the driving transistor 722 in a linear region, a voltage higher than the voltage of the power supply line 727 is applied to the driving transistor 722. A signal line 725 is connected to the gate electrode layer of the transistor 722. A voltage equal to or greater than the threshold voltage Vth of the transistor 722 is applied.

[0462] When analog gradation driving is performed, the gate electrode layer of the driving transistor 722 is connected to the light emitting element 72 A voltage equal to or greater than the forward voltage of the driving transistor 722 plus the threshold voltage Vth of the driving transistor 722. Note that a video signal is input so that the driving transistor 722 operates in the saturation region. A current flows through the light emitting element 724. In addition, the driving transistor 722 is operated in a saturation region. In order to achieve this, the potential of the power supply line 727 is set higher than the gate potential of the driving transistor 722. By converting the video signal into an analog signal, a current corresponding to the video signal is applied to the light emitting element 724. It is possible to perform analog gray scale driving.

[0463] The configuration of the pixel circuit is not limited to the pixel configuration shown in FIG. A switch, a resistor, a capacitor, a sensor, a transistor or a logic A logic circuit or the like may be added.

[0464] When the transistor illustrated in the above embodiment is applied to the circuit illustrated in FIG. The source electrode (first electrode) is on the low potential side, and the drain electrode (second electrode) is on the high potential side. Furthermore, the potential of the first gate electrode is controlled by a control circuit or the like. A potential lower than that applied to the source electrode is applied to the second gate electrode through a wiring (not shown). It is sufficient to have a configuration in which the potentials exemplified above can be input, for example by applying a potential.

[0465] For example, in this specification and the like, the term "display element," "display device having a display element," "light-emitting element," A light-emitting device, which is a device having a light-emitting element and a light-emitting element, can be used in various forms or in various The display element, the display device, the light-emitting element, or the light-emitting device may include, for example, For example, EL (electroluminescence) elements (EL elements including organic and inorganic materials, organic EL elements, inorganic EL elements), LEDs (white LEDs, red LEDs, green LEDs, blue LEDs) etc.), transistors (transistors that emit light according to electric current), electron-emitting devices, liquid crystal devices , electronic ink, electrophoretic element, grating light valve (GLV), plasma display Display (PDP), MEMS (Micro Electro Mechanical Systems), Digital Micromirror Device (DMD), DMS (Digital Micro Shutter), M IRASOL(R), IMOD (Interference Modulation) element , electrowetting element, piezoelectric ceramic display, carbon nanotube In addition to these, the device has at least one electric or magnetic display element. The display medium has contrast, brightness, reflectance, transmittance, etc. that change due to electrochemical effects. An example of a display device using an EL element is an EL display. An example of a display device using electron-emitting elements is a field emission display ( FED) or SED type flat panel display (SED: Surface-conductive Liquid crystal elements An example of a display device using the liquid crystal display (transmissive liquid crystal display, semi-transmissive liquid crystal display, LCD display, reflective LCD display, direct-view LCD display, projection LCD display Examples of display devices using electronic ink or electrophoretic elements include Examples include electronic paper.

[0466] This embodiment mode may be appropriately combined with other embodiment modes and examples shown in this specification. It is possible.

[0467] (Embodiment 8) In this embodiment, a display module to which a semiconductor device of one embodiment of the present invention is applied will be described with reference to FIG. 29 will be used for explanation.

[0468] <Display module> The display module 6000 shown in FIG. 39 is made up of an upper cover 6001 and a lower cover 6002. In between, touch panel 6004 connected to FPC 6003 and touch panel 6005 connected to FPC 6005 Display panel 6006, backlight unit 6007, frame 6009, printed circuit board 6010 and a battery 6011. In some cases, the read / write head 6011, the touch panel 6004, etc. may not be provided.

[0469] The semiconductor device of one embodiment of the present invention is, for example, a display panel 6006 or a printed circuit board. The present invention can be used in integrated circuits implemented in a semiconductor device.

[0470] The upper cover 6001 and the lower cover 6002 are connected to the touch panel 6004 and the display panel. The shape and dimensions can be changed appropriately to match the size of the cable 6006.

[0471] The touch panel 6004 is a resistive or capacitive touch panel. 6006. In addition, the opposing substrate (sealing substrate) of the display panel 6006 It is also possible to provide the display panel 6 with a touch panel function. It is also possible to add an optical sensor to each pixel of the 006 to add an optical touch panel function. Alternatively, a touch sensor electrode is provided in each pixel of the display panel 6006, and a capacitance method is used. It is also possible to add a touch panel function.

[0472] The backlight unit 6007 includes a light source 6008. It may be provided at the end of the unit 6007 and may be configured to use a light diffusion plate.

[0473] The frame 6009 has a function of protecting the display panel 6006 and also a function of preventing heat generation from the printed circuit board 6010. The frame 600 also functions as an electromagnetic shield to block electromagnetic waves generated by the 9 may also function as a heat sink.

[0474] The printed circuit board 6010 includes a power supply circuit, a signal circuit for outputting a video signal, and a clock signal. The power supply circuit is provided with a signal processing circuit. Alternatively, a battery 6011 may be provided separately. In this case, the battery 6011 can be omitted.

[0475] In addition, the display module 6000 includes components such as a polarizing plate, a retardation plate, and a prism sheet. It may be added.

[0476] This embodiment mode may be appropriately combined with other embodiment modes and examples shown in this specification. It is possible.

[0477] (Embodiment 9) In this embodiment, an example of use of a semiconductor device according to one embodiment of the present invention will be described.

[0478] <Package using lead frame type interposer> Figure 40(A) shows the cross-sectional structure of a package using a lead frame type interposer. The package shown in FIG. 40A is a perspective view of a semiconductor device according to one embodiment of the present invention. A corresponding chip 1751 is attached to the interposer 1750 by wire bonding. The terminal 1752 is connected to the chip 17 of the interposer 1750. 51 is mounted on the surface. The chip 1751 is then molded in resin. 1753, but the sealing is performed with a part of each terminal 1752 exposed. So that it can be done.

[0479] The module configuration of an electronic device (mobile phone) in which a package is mounted on a circuit board is shown in Fig. The mobile phone module shown in FIG. 40(B) includes a printed wiring board 18 The display device 1801 includes a package 1802 and a battery 1804. A printed wiring board 1801 is connected to a panel 1800 having a child by an FPC 1803. It has been implemented.

[0480] This embodiment mode may be appropriately combined with other embodiment modes and examples shown in this specification. It is possible.

[0481] (Embodiment 10) In this embodiment, electronic devices and lighting devices according to one embodiment of the present invention will be described with reference to drawings. do.

[0482] <Electronic equipment> Using the semiconductor device of one embodiment of the present invention, an electronic device or a lighting device can be manufactured. By using the semiconductor device of one embodiment of the present invention, highly reliable electronic devices and lighting devices can be manufactured. The semiconductor device according to one embodiment of the present invention is used in an electronic device or a lighting device in which the detection sensitivity of a touch sensor is improved. You can create devices.

[0483] The electronic device may be, for example, a television device (also called a television or television receiver). (c), computer monitors, digital cameras, digital video cameras, digital Photo frames, mobile phones (also called mobile phones or mobile phone devices), portable game machines, Examples include portable information terminals, audio playback devices, and large game machines such as pachinko machines.

[0484] In addition, when the electronic device or lighting device of one embodiment of the present invention is flexible, it can be attached to the inner wall of a house or a building. Or it can be installed along the curved surface of an exterior wall or the interior or exterior of a car. do.

[0485] Further, the electronic device of one embodiment of the present invention may include a secondary battery and may be configured to use non-contact power transmission. It is preferable to be able to charge the secondary battery.

[0486] As the secondary battery, for example, a lithium polymer battery (lithium ion battery) using a gel electrolyte is used. Lithium-ion secondary batteries such as lithium-ion polymer batteries, lithium-ion batteries, nickel-metal hydride batteries , nickel-cadmium battery, organic radical battery, lead acid battery, secondary air battery, nickel-zinc battery, silver-zinc battery Batteries and the like.

[0487] The electronic device according to one embodiment of the present invention may include an antenna. By doing so, it is possible to display images and information on the display unit. If present, the antenna may be used for contactless power transfer.

[0488] FIG. 41A shows a portable game machine. The portable game machine includes a housing 7101, a housing 7102, a display portion 7103, Display unit 7104, microphone 7105, speaker 7106, operation keys 7107, stylus The semiconductor device according to one embodiment of the present invention is built in the housing 7101. The display portion 7103 or the display portion 7104 can be used for an integrated circuit, a CPU, etc. By using the light-emitting device according to one embodiment of the present invention, the user experience is excellent and deterioration of quality is prevented. It is possible to provide a portable game machine in which the above-mentioned problem is unlikely to occur. The portable game machine has two display units 7103 and 7104. The number of display units that the device has is not limited to this.

[0489] FIG. 41B shows a smart watch. The smart watch includes a housing 7302, a display unit 7304, and operation buttons. 7311, 7312, a connection terminal 7313, a band 7321, a clasp 7322, etc. The semiconductor device according to one embodiment of the present invention includes a memory, a CPU, and the like built in the housing 7302. can be used.

[0490] FIG. 41C shows a portable information terminal. In addition to a display portion 7502 incorporated in a housing 7501, , operation button 7503, external connection port 7504, speaker 7505, microphone 7506 The semiconductor device according to one embodiment of the present invention includes a housing 7501, a display portion 7502, and the like. It can be used for mobile memory and CPU built in the display unit 7. The 502 can achieve extremely high definition, so it can provide full HD despite its small to medium size. It can display a variety of resolutions, such as 4k, 5k, or 8k, and you can get very clear images. can.

[0491] FIG. 41D shows a video camera, which includes a first housing 7701, a second housing 7702, and a display unit 77 03, operation keys 7704, a lens 7705, a connection part 7706, etc. 4 and a lens 7705 are provided in a first housing 7701, and a display unit 7703 is provided in a second housing. The first housing 7701 and the second housing 7702 are connected to each other. The first housing 7701 and the second housing 7702 are connected by a connector 7706. The angle between the first housing 7701 and the second housing 7702 is The connection portion 7706 can change the image on the display portion 7703. 6, the switch is configured according to the angle between the first housing 7701 and the second housing 7702. The imaging device of one embodiment of the present invention may be provided at the focal position of the lens 7705. In the semiconductor device according to one embodiment of the present invention, the semiconductor device is integrated in the first housing 7701. It can be used in integrated circuits, CPUs, etc.

[0492] FIG. 41E shows a digital signage. A display unit 7902 is installed on a utility pole 7901. The display device according to one embodiment of the present invention can be used as a control circuit for the display portion 7902. This can be done.

[0493] FIG. 42A shows a notebook personal computer, which includes a housing 8121 and a display unit 8122. , a keyboard 8123, a pointing device 8124, etc. Such a semiconductor device can be applied to a CPU or a memory built in the housing 8121. Since the display portion 8122 can have a very high resolution, it can be used in small and medium-sized devices. It is possible to display 8K images while using a smartphone, resulting in extremely clear images.

[0494] FIG. 42(B) shows the exterior of the automobile 9700. FIG. 42(C) shows the driver's seat of the automobile 9700. The automobile 9700 includes a body 9701, wheels 9702, a dashboard 9703, and a lighter. The semiconductor device of one embodiment of the present invention includes a display portion of the automobile 9700 and For example, the display portion 9710 shown in FIG. The semiconductor of one embodiment of the present invention can be provided in the display portion 9715.

[0495] The display portion 9710 and the display portion 9711 are a display device provided on a windshield of an automobile, The display device or the input / output device according to one embodiment of the present invention is a display device or By forming the electrodes of the input / output device from a light-transmitting conductive material, The device is a so-called see-through display device or input / output device that allows the opposite side to be seen through. If it is a see-through display device or an input / output device, the operation of the car 9700 can be Therefore, the display device or input / output device according to one embodiment of the present invention can be used without obstructing the view even when the display device is turned on. The display device can be installed on the windshield of the automobile 9700. A display device or an input / output device is provided with transistors for driving the display device or the input / output device. In this case, organic transistors using organic semiconductor materials and transistors using oxide semiconductors are used. For example, a light-transmitting transistor such as a transistor having a light-transmitting property may be used.

[0496] The display unit 9712 is a display device provided on a pillar part. By displaying an image from the imaging means on the display unit 9712, the view blocked by the pillars can be compensated for. The display unit 9713 is a display device provided in the dashboard. For example, an image captured by an imaging means provided on the vehicle body is displayed on the display unit 9713. This can complement the view obstructed by the dashboard. By projecting images from the installed imaging means, blind spots can be filled and safety can be improved. In addition, by projecting an image that complements the invisible parts, it is possible to make the sense of discomfort more natural. Safety checks can be performed without any hassle.

[0497] FIG. 42(D) shows the interior of a car with bench seats for the driver and passenger. The display unit 9721 is a display device or an input / output device provided in the door section. For example, the driver can view the vehicle by displaying an image captured by an imaging means provided on the vehicle body on the display unit 9721. The display unit 9722 can complement the view blocked by the steering wheel. The display unit 9723 is a display device provided in the center of the seat surface of the bench seat. The display device is installed on the seat or backrest, and the display device is The heat generated by the display device can also be used as a seat heater.

[0498] The display unit 9714, the display unit 9715, or the display unit 9722 displays navigation information, odometer, tachometer, mileage, fuel level, gear status, air conditioning settings, etc. It is possible to provide various information. In addition, the display items and layout displayed on the display unit can be The above information can be displayed on the display unit 9. 710 to 9713, the display unit 9721, and the display unit 9723. In addition, the display units 9710 to 9715 and the display units 9721 to 9723 are illuminated. The display units 9710 to 9715 and the display unit The display portion 9721 to the display portion 9723 can also be used as a heating device.

[0499] 43A shows the external appearance of the camera 8000. The camera 8000 has a housing 8001. , a display unit 8002, an operation button 8003, a shutter button 8004, a connection unit 8005, etc. In addition, a lens 8006 can be attached to the camera 8000.

[0500] The coupling section 8005 has electrodes and is connected to the finder 8100 (to be described later) as well as a strobe device, etc. can be connected.

[0501] In this example, a camera 8000 is used, and a lens 8006 is removed from a housing 8001 and replaced. However, the lens 8006 and the housing may be integrated together.

[0502] An image can be captured by pressing the shutter button 8004. The display unit 8002 has a function as a touch panel, and an image is captured by touching the display unit 8002. It is also possible.

[0503] The display device or the input / output device according to one embodiment of the present invention can be applied to the display portion 8002. do.

[0504] FIG. 43B shows an example in which a finder 8100 is attached to a camera 8000. is.

[0505] The finder 8100 includes a housing 8101, a display portion 8102, a button 8103, and the like.

[0506] The housing 8101 has a joint portion that engages with the joint portion 8005 of the camera 8000. The finder 8100 can be attached to the camera 8000. The display unit 8102 displays images received from the camera 8000 via the electrodes. It can be done.

[0507] The button 8103 functions as a power button. The display of 102 can be switched on and off.

[0508] The semiconductor device of one embodiment of the present invention is applied to an integrated circuit and an image sensor in a housing 8101. It can be used.

[0509] In addition, in FIG. 43(A) and (B), the camera 8000 and the finder 8100 are separate electronic devices. The camera 8000 is provided with a housing 8001 that is detachable. A finder having a display device or an input / output device according to an embodiment may be built in.

[0510] FIG. 43C shows the external appearance of the head mounted display 8200.

[0511] The head mounted display 8200 includes a mounting part 8201, a lens 8202, and a main body 820. 3, a display unit 8204, a cable 8205, etc. It has a built-in Teri 8206.

[0512] A cable 8205 supplies power from a battery 8206 to the main body 8203. The reference numeral 3 is provided with a wireless receiver and displays image information such as received image data on a display unit 8204. In addition, the movement of the user's eyeballs and eyelids can be recorded by a camera installed on the main body 8203. The system captures the user's viewpoint and calculates the coordinates of the user's viewpoint based on that information. It can be used as a force means.

[0513] Furthermore, the mounting unit 8201 may be provided with a plurality of electrodes at positions that come into contact with the user. The main body 8203 detects the current flowing through the electrodes in response to the movement of the user's eyeball, The device may have a function of recognizing the user's gaze. Also, the device may have a function of detecting the current flowing through the electrode. In this way, the mounting unit 8201 may have a function of monitoring the pulse of the user. It may have various sensors such as a temperature sensor, a pressure sensor, and an acceleration sensor, and may have a function of displaying the biological information of the user on the display unit 8204. Further, it may detect the movement of the user's head, etc., and change the video displayed on the display unit 8204 according to the movement. 者の生体情報を表示部8204に表示する機能を有していてもよい。また、使用者の頭部 の動きなどを検出し、表示部8204に表示する映像をその動きに合わせて変化させても よい。

[0514] The semiconductor device according to one aspect of the present invention can be applied to the integrated circuit inside the main body 8203. 。

[0515] This embodiment can be implemented in appropriate combination with at least a part of other embodiments described in this specification. 合わせて実施することができる。

[0516] (Embodiment 11) In this embodiment, a usage example of an RF tag using the semiconductor device according to one aspect of the present invention will be described with reference to FIG. 44. 図44を用いながら説明する。

[0517] <Usage Example of RF Tag> The applications of RF tags are extensive. For example, banknotes, coins, securities, bearer bonds, documents (such as driver's licenses and resident cards, see FIG. 44(A)), vehicles (such as bicycles, see FIG. 44(B) 参照)、包装用容器類(包装紙やボトル等、図44(C)参照)、記録媒体(DVDやビ 参照)、身の回り品(鞄や眼鏡等、図44(D)参照)、食品類、植物類、動物類、 デオテープ等身の回り品(鞄や眼鏡等、図44(D)参照)、食品類、植物類、動物類、 人体、衣類、生活用品類、薬品や薬剤を含む医療品、または電子機器(液晶表示装置、E L表示装置、テレビジョン装置、または携帯電話)等の物品、若しくは各物品に取り付け る荷札(図44(E)、図44(F)参照)等に設けて使用することができる。

[0518] The RF tag 4000 according to one aspect of the present invention can be attached to the surface or embedded in an object. For example, in a book, the sensor is embedded in the paper, and in a package made of organic resin, the sensor is embedded in the paper. For example, the RF tag is embedded in the organic resin and fixed to each article. The 4000 is small, thin, and lightweight, and even after it is attached to an object, it does not change the design of the object. In addition, the security of banknotes, coins, securities, bearer bonds, or certificates is not lost. By providing an RF tag 4000 according to one aspect of the present invention to a product or the like, an authentication function can be provided. This authentication function can be used to prevent counterfeiting. The present invention can be applied to various items, such as items of clothing, recording media, personal belongings, food, clothing, household goods, and electronic devices. By attaching RF tags related to the above, the efficiency of systems such as inspection systems can be improved. In addition, even in the case of vehicles, the RF tag according to one embodiment of the present invention can be attached. This can improve security against theft and the like.

[0519] As described above, an RF tag using a semiconductor device according to one embodiment of the present invention is By using these for each of the above applications, it is possible to reduce the power consumption during operation, including writing and reading information. Therefore, it is possible to extend the maximum communication distance. Since the data can be stored for an extremely long period of time, it is also suitable for applications where writing and reading are performed infrequently. It can be suitably used.

[0520] This embodiment mode may be appropriately combined with other embodiment modes and examples shown in this specification. It is possible. [Explanation of symbols]

[0521] 10. Transistor 11 Transistor 12 Transistor 13. Transistor 14 Transistor 63 Semiconductor Layer 64 Semiconductor Layer 65 Semiconductor Layer 100 Substrates 110 Insulating layer 120 Oxide semiconductor layer 121 Oxide semiconductor layer 122 Oxide semiconductor layer 123 Oxide semiconductor layer 123a Oxide semiconductor film 124 Oxide semiconductor layer 130 Source electrode layer 130b Conductive layer 131 Source electrode layer 132 Source electrode layer 135 Conductive Layer 140 Drain electrode layer 141 Drain electrode layer 142 Drain electrode layer 150 Gate insulation layer 150a Insulating film 160 Gate electrode layer 160a Conductive film 161 Gate electrode layer 162 Gate electrode layer 163 Gate electrode layer 165 Conductive Layer 166 Conductive Layer 167 Conductive Layer 170 Insulating layer 171 Mixed layer 172 Oxygen 174 Groove 175 Insulating Layer 175b Insulating layer 176 Resist Mask 177 Insulating Layer 180 Insulating layer 185 Insulating Layer 190 Conductive Layer 191 Conductive Layer 192 Conductive Layer 200 Imaging device 201 Switch 202 Switch 203 Switch 210 Pixel section 211 pixels 212 subpixels 212B subpixel 212G subpixel 212R subpixel 220 Photoelectric conversion element 230 Pixel Circuit 231 Wiring 247 Wiring 248 Wiring 249 Wiring 250 Wiring 253 Wiring 254 Filter 254B Filter 254G Filter 254R Filter 255 Lens 256 light 257 Wiring 260 Peripheral Circuits 270 Peripheral Circuits 280 Peripheral Circuits 290 Peripheral Circuits 291 Light source 300 Silicon substrate 310 layers 320 layers 330 layers 340 layers 351 Transistor 352 Transistor 353 Transistor 360 Photodiode 361 Anode 362 Cathode 363 Low resistance region 365 Photodiode 366 Semiconductor Layer 367 Semiconductor Layer 368 Semiconductor Layer 370 Plug 371 Wiring 372 Wiring 373 Wiring 374 Wiring 601 Precursor 602 Precursor 700 Substrates 701 Pixel section 702 Scanning line driver circuit 703 Scanning line driver circuit 704 Signal Line Driver Circuit 710 Capacitance wiring 712 scan lines 713 scan lines 714 Signal Line 716 Transistor 717 Transistor 718 Liquid crystal element 719 Liquid crystal element 720 pixels 721 Switching Transistors 722 Driving Transistor 723 Capacitive element 724 Light emitting element 725 Signal Line 726 scan lines 727 Power line 728 Common electrode 800 RF Tags 801 Communication Device 802 Antenna 803 radio signal 804 Antenna 805 Rectifier circuit 806 Constant voltage circuit 807 Demodulation Circuit 808 Modulation Circuit 809 Logic Circuit 810 Memory circuit 811 ROM 1189 ROM Interface 1190 Board 1191 ALU 1192 ALU Controller 1193 Instruction Decoder 1194 Interrupt Controller 1195 Timing Controller 1196 Registers 1197 Register Controller 1198 Bus Interface 1199 ROM 1200 memory elements 1201 Circuit 1202 Circuit 1203 Switch 1204 Switch 1206 Logic elements 1207 Capacitive element 1208 Capacitive element 1209 Transistor 1210 Transistor 1213 Transistor 1214 Transistor 1220 Circuit 1223 Oxide semiconductor layer 1700 Substrate to be coated 1701 Chamber 1702 Road Room 1703 Pre-treatment room 1704 Chamber 1705 Chamber 1706 Unloading Room 1711a Raw material supply section 1711b Raw material supply section 1712a High Speed ​​Valve 1712b High Speed ​​Valve 1713a Raw material inlet 1713b Raw material inlet 1714 Raw material discharge port 1715 Exhaust system 1716 PCB Holder 1720 Delivery Room 1750 Interposer 1751 Chips 1752 Terminal 1753 Molding resin 1800 Panel 1801 Printed wiring board 1802 Package 1803 FPC 1804 Battery 2100 Transistor 2200 Transistor 2201 Insulators 2202 Wiring 2203 Plug 2204 Insulators 2205 Wiring 2207 Insulators 2210 Middle Class 2211 Semiconductor substrate 2212 Insulators 2213 Gate electrode 2214 Gate insulator 2215 Drain Region 3001 Wiring 3002 Wiring 3003 Wiring 3004 Wiring 3005 Wiring 3200 Transistors 3300 Transistors 3400 Capacitive element 4000 RF tags 5100 pellets 5120 Circuit Board 5161 area 6000 Display Module 6001 Top cover 6002 Lower cover 6003 FPC 6004 Touch Panel 6005 FPC 6006 Display Panel 6007 Backlight unit 6008 Light source 6009 Frame 6010 Printed Circuit Board 6011 Battery 7101 Case 7102 Case 7103 Display section 7104 Display section 7105 Microphone 7106 Speaker 7107 Operation key 7108 Stylus 7302 Case 7304 Display section 7311 Operation button 7312 Operation button 7313 Connection terminal 7321 Band 7322 Gold 7501 Case 7502 Display section 7503 Operation button 7504 External connection port 7505 Speaker 7506 Microphone 7701 Case 7702 Case 7703 Display section 7704 Operation key 7705 Lens 7706 Connection 7901 Electric pole 7902 Display section 8000 Camera 8001 Case 8002 Display section 8003 Operation button 8004 Shutter button 8005 Joint 8006 Lens 8100 Finder 8101 Case 8102 Display section 8103 Button 8121 Case 8122 Display section 8123 Keyboard 8124 Pointing Device 8200 Head Mounted Display 8201 Mounting part 8202 Lens 8203 Main unit 8204 Display section 8205 Cable 8206 Battery 9700 Automobiles 9701 Body 9702 wheels 9703 Dashboard 9704 Light 9710 Display section 9711 Display section 9712 Display section 9713 Display section 9714 Display section 9715 Display section 9721 Display section 9722 Display section 9723 Display section

Claims

1. A semiconductor device including a first transistor having a first channel formation region including silicon, a second transistor having a second channel formation region including an oxide semiconductor, and a capacitor, a first insulating layer on the first channel formation region; a first conductive layer having a region in contact with an upper surface of the first insulating layer and functioning as a gate electrode of the first transistor; a second insulating layer on the first conductive layer; and a second conductive layer having a region in contact with an upper surface of the second insulating layer and functioning as a first gate electrode of the second transistor; a third insulating layer on the second conductive layer; and an oxide semiconductor layer located over the third insulating layer and having the second channel formation region; a fourth insulating layer located on the oxide semiconductor layer; a third conductive layer located on the fourth insulating layer and having a region that functions as a second gate electrode of the second transistor; a fifth insulating layer having a region in contact with an upper surface of the third conductive layer; a fourth conductive layer having a region in contact with an upper surface of the fifth insulating layer and electrically connected to one of a source region and a drain region of the second transistor; a fifth conductive layer located on the fifth insulating layer and having a region that functions as one electrode of the capacitance element; a sixth insulating layer on the fifth conductive layer; and a sixth conductive layer located on the sixth insulating layer and having a region that functions as the other electrode of the capacitance element; the fifth conductive layer is electrically connected to the other of the source region and the drain region of the second transistor and to a gate electrode of the first transistor; the sixth conductive layer has a region overlapping with the first channel formation region, a region overlapping with the second channel formation region, and a region overlapping with the fourth conductive layer; a width of the second conductive layer is greater than a width of the third conductive layer in a cross-sectional view taken in a channel length direction of the second transistor.

2. A semiconductor device including a first transistor having a first channel formation region including silicon, a second transistor having a second channel formation region including an oxide semiconductor, and a capacitor, a first insulating layer on the first channel formation region; a first conductive layer having a region in contact with an upper surface of the first insulating layer and functioning as a gate electrode of the first transistor; a second insulating layer on the first conductive layer; and a second conductive layer having a region in contact with an upper surface of the second insulating layer and functioning as a first gate electrode of the second transistor; a third insulating layer on the second conductive layer; and an oxide semiconductor layer located over the third insulating layer and having the second channel formation region; a fourth insulating layer located on the oxide semiconductor layer; a third conductive layer located on the fourth insulating layer and having a region that functions as a second gate electrode of the second transistor; a fifth insulating layer having a region in contact with an upper surface of the third conductive layer; a fourth conductive layer having a region in contact with an upper surface of the fifth insulating layer and electrically connected to one of a source region and a drain region of the second transistor; a fifth conductive layer located on the fifth insulating layer and having a region that functions as one electrode of the capacitance element; a sixth insulating layer on the fifth conductive layer; and a sixth conductive layer located on the sixth insulating layer and having a region that functions as the other electrode of the capacitance element; the fifth conductive layer is electrically connected to the other of the source region and the drain region of the second transistor and to a gate electrode of the first transistor; the sixth conductive layer has a region overlapping with the first channel formation region, a region overlapping with the second channel formation region, and a region overlapping with the fourth conductive layer; In a cross-sectional view of the second transistor in a channel length direction, a width of the second conductive layer is larger than a width of the third conductive layer; a part of a lower surface of the third conductive layer is located lower than a lower surface of the oxide semiconductor layer in a cross-sectional view in a channel width direction of the second transistor.

3. A semiconductor device including a first transistor having a first channel formation region including silicon, a second transistor having a second channel formation region including an oxide semiconductor, and a capacitor, a first insulating layer on the first channel formation region; a first conductive layer having a region in contact with an upper surface of the first insulating layer and functioning as a gate electrode of the first transistor; a second insulating layer on the first conductive layer; and a second conductive layer having a region in contact with an upper surface of the second insulating layer and functioning as a first gate electrode of the second transistor; a third insulating layer on the second conductive layer; and an oxide semiconductor layer located over the third insulating layer and having the second channel formation region; a fourth insulating layer located on the oxide semiconductor layer; a third conductive layer located on the fourth insulating layer and having a region that functions as a second gate electrode of the second transistor; a fifth insulating layer having a region in contact with an upper surface of the third conductive layer; a fourth conductive layer having a region in contact with an upper surface of the fifth insulating layer and electrically connected to one of a source region and a drain region of the second transistor; a fifth conductive layer located on the fifth insulating layer and having a region that functions as one electrode of the capacitance element; a sixth insulating layer on the fifth conductive layer; and a sixth conductive layer located on the sixth insulating layer and having a region that functions as the other electrode of the capacitance element; the fifth conductive layer is electrically connected to the other of the source region and the drain region of the second transistor and to a gate electrode of the first transistor; the sixth conductive layer has a region overlapping with the first channel formation region, a region overlapping with the second channel formation region, a region overlapping with the first conductive layer, a region overlapping with the second conductive layer, a region overlapping with the third conductive layer, and a region overlapping with the fourth conductive layer; a width of the second conductive layer is greater than a width of the third conductive layer in a cross-sectional view taken in a channel length direction of the second transistor.

4. A semiconductor device including a first transistor having a first channel formation region including silicon, a second transistor having a second channel formation region including an oxide semiconductor, and a capacitor, a first insulating layer on the first channel formation region; a first conductive layer having a region in contact with an upper surface of the first insulating layer and functioning as a gate electrode of the first transistor; a second insulating layer on the first conductive layer; and a second conductive layer having a region in contact with an upper surface of the second insulating layer and functioning as a first gate electrode of the second transistor; a third insulating layer on the second conductive layer; and an oxide semiconductor layer located over the third insulating layer and having the second channel formation region; a fourth insulating layer located on the oxide semiconductor layer; a third conductive layer located on the fourth insulating layer and having a region that functions as a second gate electrode of the second transistor; a fifth insulating layer having a region in contact with an upper surface of the third conductive layer; a fourth conductive layer having a region in contact with an upper surface of the fifth insulating layer and electrically connected to one of a source region and a drain region of the second transistor; a fifth conductive layer located on the fifth insulating layer and having a region that functions as one electrode of the capacitance element; a sixth insulating layer on the fifth conductive layer; and a sixth conductive layer located on the sixth insulating layer and having a region that functions as the other electrode of the capacitance element; the fifth conductive layer is electrically connected to the other of the source region and the drain region of the second transistor and to a gate electrode of the first transistor; the sixth conductive layer has a region overlapping with the first channel formation region, a region overlapping with the second channel formation region, a region overlapping with the first conductive layer, a region overlapping with the second conductive layer, a region overlapping with the third conductive layer, and a region overlapping with the fourth conductive layer; In a cross-sectional view of the second transistor in a channel length direction, a width of the second conductive layer is larger than a width of the third conductive layer; a part of a lower surface of the third conductive layer is located lower than a lower surface of the oxide semiconductor layer in a cross-sectional view in a channel width direction of the second transistor.

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