Semiconductor Device

Abstract

To provide, for example, a semiconductor device with a new structure.SOLUTION: A semiconductor device includes: a first wiring; a second wiring; a third wiring; a fourth wiring; a first transistor having a first gate electrode, a first source electrode, and a first drain electrode; and a second transistor having a second gate electrode, a second source electrode, and a second drain electrode. The first transistor is provided over a substrate containing a semiconductor material. The second transistor includes an oxide semiconductor layer.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The disclosed invention relates to a semiconductor device using a semiconductor element and a manufacturing method thereof. do. [Background technology]

[0002] Memory devices that use semiconductor elements are volatile memory devices, meaning that the stored contents are lost when the power supply is cut off. They are broadly divided into two types: volatile memory devices, which retain their contents even when the power supply is cut off, and non-volatile memory devices, which retain their contents even when the power supply is cut off. can be.

[0003] A typical example of a volatile memory device is a DRAM (Dynamic Random Access Memory). DRAM is a memory element that can be selected from the transistors. By storing charge in the capacitor, information is stored.

[0004] From the above principle, in DRAM, when information is read, the charge in the capacitor is lost. Therefore, after reading data, another write operation is required to store the information again. In addition, a leakage current exists in the transistors that constitute the memory element, and when the transistors are not selected, Since electric charges flow in and out even under certain conditions, the data retention period is short. A write operation (refresh operation) is required every 100 seconds, which reduces power consumption sufficiently. In addition, if the power supply is cut off, the memory contents are lost, so it is difficult to store the data for a long period of time. To retain this information, a separate storage device using magnetic or optical materials is required.

[0005] Another example of a volatile memory device is SRAM (Static Random Access Memory). SRAM uses circuits such as flip-flops to store data. No refresh operation is required to retain data, which is an advantage over DRAM. However, because it uses circuits such as flip-flops, the cost per unit of memory capacity is high. In addition, if the power supply is cut off, the memory contents are lost. In this regard, there is no difference with DRAM.

[0006] A typical example of a non-volatile memory device is a flash memory. A floating gate is provided between the gate electrode of the transistor and the channel forming region, Since memory is stored by holding an electric charge in the floating gate, the data is retained for an extremely long period of time. The advantage is that it lasts a very long time (semi-permanent) and does not require the refresh operations required for volatile storage devices. For example, see Patent Document 1.

[0007] However, the gate insulating layer that constitutes the memory element is damaged by the tunnel current that occurs during writing. This causes a problem that the memory element may become non-functional after a certain number of writes. In order to alleviate the effect of this problem, for example, the number of write operations to each memory element is made uniform. However, to achieve this, complex peripheral circuits are required. However, even if such a method is adopted, the fundamental problem of life span is not solved. Therefore, flash memory is not suitable for applications where information needs to be rewritten frequently.

[0008] Also, to hold charge on the floating gate or to remove that charge. High voltages are required to maintain or remove the charge. There is also the problem that it takes time to write and erase data, and it is not easy to speed up the writing and erasing operations. [Prior art documents] [Patent documents]

[0009] [Patent Document 1] Japanese Patent Application Publication No. 57-105889 Summary of the Invention [Problem to be solved by the invention]

[0010] In view of the above problems, one embodiment of the disclosed invention provides a method for storing stored contents even when power is not supplied. To provide a semiconductor device having a new structure capable of retaining data and having no limit on the number of times it can be written. Another object of the present invention is to provide a semiconductor device having a configuration that allows easy multi-level operation. It shall be one of the following. [Means for solving the problem]

[0011] One embodiment of the present invention is a transistor formed using an oxide semiconductor and a transistor formed using another material. The present invention relates to a semiconductor device having a stacked structure with a transistor formed using the above-mentioned method. For example, Such a configuration can be adopted.

[0012] One aspect of the present invention is a semiconductor memory device including a source line, a bit line, a first signal line, a plurality of second signal lines, and a plurality of a plurality of memory cells connected in parallel between the word lines, the source lines, and the bit lines; An address signal is input, and one of a plurality of memory cells is designated by the address signal. a second signal for driving a plurality of second signal lines and a plurality of word lines to select the recell; A driving circuit for the line and the word line and a driving circuit for the first signal line and a driving circuit for ... A drive circuit for a first signal line, which outputs the bit line potential and a plurality of reference potentials, A read circuit compares the potential of the bit line with a plurality of reference potentials to read data; A write potential and a plurality of reference potentials are generated to drive a first signal line and a read circuit. a potential generating circuit for supplying a potential to the potential generating circuit; and a boosting circuit for supplying a potential to the potential generating circuit; Each of the memory cells includes a first gate electrode, a first source electrode, and a first drain electrode. a first transistor having a second gate electrode, a second source electrode, and a second drain electrode; a second transistor having a drain electrode, a third gate electrode, a third source electrode, and and a third transistor having a third drain electrode, the first transistor comprising: The second transistor is provided over a substrate including a semiconductor material, and the second transistor includes an oxide semiconductor layer. The first gate electrode and one of the second source electrode and the second drain electrode are electrically connected to each other. the source line and the first source electrode are electrically connected to each other; The electrode and the third source electrode are electrically connected, and the bit line and the third drain electrode are are electrically connected to the first signal line and the second source electrode or the second drain electrode. The first gate electrode is electrically connected to the second signal line, and the second gate electrode is electrically connected to one of the second signal lines. a semiconductor device in which one of the plurality of word lines is electrically connected to a third gate electrode It is.

[0013] In the above structure, the first gate electrode and the second source electrode or the second drain electrode The semiconductor device has a capacitor electrically connected to one of the electrodes.

[0014] In addition, one aspect of the present invention is a semiconductor memory device including a source line, a bit line, a first signal line, and a plurality of second signal lines. A plurality of memory cells are connected in parallel between a plurality of word lines, a source line, and a bit line. An address signal is input, and one of a plurality of memory cells designated by the address signal is selected. a second signal line and a second word line are driven to select the selected memory cell; A drive circuit for the second signal line and the word line, and a drive circuit for the first signal line and a drive circuit for the word line and a drive circuit for the second signal line and a drive circuit for the word line and a drive circuit for the first signal ... word line and a drive circuit for the first signal line and a A drive circuit for a first signal line, which outputs a potential of a bit line and a plurality of reference potentials, , a reference memory cell, and the conductance of the designated memory cell and the conductance of the reference memory cell A read circuit compares the conductance to read data, and and generating a plurality of reference potentials and supplying them to a drive circuit and a readout circuit of the first signal line. A potential generating circuit and a boosting circuit for supplying a potential to the potential generating circuit. A first transistor having a first gate electrode, a first source electrode, and a first drain electrode. a second gate electrode, a second source electrode, and a second drain electrode; a second transistor having a third gate electrode, a third source electrode, and a third drain electrode; and a third transistor having an electrode, the first transistor including a semiconductor material. The second transistor is provided on a substrate and includes an oxide semiconductor layer. The electrode and one of the second source electrode and the second drain electrode are electrically connected to each other. The first source electrode is electrically connected to the first drain electrode. The source electrode is electrically connected to the bit line, and the third drain electrode is electrically connected to the bit line. The first signal line and the other of the second source electrode and the second drain electrode are electrically connected to each other. One of the second signal lines is electrically connected to the second gate electrode. One of the word lines and the third gate electrode are electrically connected to each other in the semiconductor device.

[0015] In addition, one aspect of the present invention is a semiconductor memory device including a source line, a bit line, a first signal line, and a plurality of second signal lines. A plurality of memory cells are connected in parallel between a plurality of word lines, a source line, and a bit line. An address signal and a plurality of reference potentials are input, and among the plurality of memory cells, the address signal is A plurality of second signal lines and a plurality of word lines are connected to select a memory cell designated by the signal. and driving the selected word line to select one of a plurality of reference potentials and output the selected word line. A drive circuit for the second signal line and the word line is connected to the drive circuit for the second signal line and the word line, and one of a plurality of write potentials is selected to be a first write potential. A driver circuit for a first signal line, which outputs to one signal line, and a specified memory connected to the bit line A read circuit for reading data by reading the conductance of the recell; A write potential and a plurality of reference potentials are generated to drive a first signal line and a read circuit. a potential generating circuit for supplying a potential to the potential generating circuit; and a boosting circuit for supplying a potential to the potential generating circuit; Each of the memory cells includes a first gate electrode, a first source electrode, and a first drain electrode. a first transistor having a second gate electrode, a second source electrode, and a second drain electrode; a second transistor having a drain electrode and a capacitance element, and the first transistor The first transistor is provided over a substrate including a semiconductor material, and the second transistor includes an oxide semiconductor layer. a first gate electrode, one of a second source electrode and a second drain electrode, and a capacitance One electrode of the element is electrically connected, and the source line and the first source electrode are electrically The bit line and the first drain electrode are electrically connected to each other, and the first signal line and the The other of the second source electrode and the second drain electrode is electrically connected to a plurality of second signals. The first gate electrode is electrically connected to one of the word lines. The other electrode of the terminal is electrically connected to the semiconductor device.

[0016] In the above, the first transistor is a channel forming transistor provided in a substrate including a semiconductor material. a region, impurity regions provided so as to sandwich the channel forming region, and a region A first gate insulating layer, a first gate electrode on the first gate insulating layer, and an impurity region and an electric and a first source electrode and a first drain electrode electrically connected to the first source electrode.

[0017] In the above, the second transistor has a second gate electrode on a substrate including a semiconductor material. a second gate insulating layer on the second gate electrode; and an oxide semiconductor layer on the second gate insulating layer. a second source electrode and a second drain electrode electrically connected to the oxide semiconductor layer; And, it has.

[0018] In the above, the third transistor is a channel transistor provided in a substrate including a semiconductor material. A dopant region is provided between the dopant regions and the channel region. a third gate insulating layer on the impurity region; a third gate electrode on the third gate insulating layer; and and a third source electrode and a third drain electrode electrically connected to the first source electrode and the second drain electrode.

[0019] In the above, a single crystal semiconductor substrate is preferably used as the substrate containing a semiconductor material. It is particularly preferable that the semiconductor material is silicon. The substrate may be an SOI substrate.

[0020] In the above, the oxide semiconductor layer is made of an In-Ga-Zn-O-based oxide semiconductor material. In particular, the oxide semiconductor layer preferably contains In2Ga2ZnO7 crystals. In addition, the hydrogen concentration in the oxide semiconductor layer is preferably 5×10 19 atoms / cm 3 In addition, the off-state current of the second transistor is preferably 1×10 -13 A It is preferable to have the following:

[0021] In the above, the second transistor is provided in a region overlapping with the first transistor. The configuration can be as follows.

[0022] In this specification, the terms "above" and "below" refer to the positional relationship of the components "directly above" and "below." For example, the term "a first insulating layer on a gate insulating layer" does not necessarily mean "directly under" the gate insulating layer. If the term "gate electrode" is used, other components are provided between the gate insulating layer and the first gate electrode. In addition, the terms "upper" and "lower" are used for convenience of explanation. Unless otherwise specified, the above terms are merely examples and may be reversed.

[0023] In addition, the terms "electrode" and "wiring" used in this specification and the like refer to these components functionally. For example, an "electrode" may be used as a part of a "wiring". Furthermore, the terms "electrode" and "wiring" are used interchangeably to refer to the plural "electrodes". This also includes cases where "conductor" and "wiring" are formed as one unit.

[0024] In addition, the functions of the "source" and "drain" may differ depending on whether transistors of different polarities are used or not. However, they may be swapped when the direction of the current changes during circuit operation. In this specification, the terms "source" and "drain" are used interchangeably. It is assumed that this is possible.

[0025] In this specification, "electrically connected" means "something that has some kind of electrical effect" " includes cases where the device is connected via "anything that has some electrical effect." " is not subject to any particular restriction as long as it enables the transmission and reception of electrical signals between the connection objects.

[0026] For example, "something that has some kind of electrical effect" includes not only electrodes and wiring, but also transistors. Switching elements such as transistors, resistors, inductors, capacitors, and other various devices This includes elements having functions such as:

[0027] In general, an "SOI substrate" is a substrate that has a silicon semiconductor layer on an insulating surface. However, in this specification and the like, a semiconductor layer made of a material other than silicon is provided on an insulating surface. In other words, the semiconductor that "SOI substrate" has is The layer is not limited to a silicon semiconductor layer. Also, the substrate in the "SOI substrate" is a silicon Not only semiconductor substrates such as silicon wafers, but also glass substrates, quartz substrates, sapphire substrates, metal substrates This also includes non-semiconductor substrates such as semiconductor layers on conductive or insulating substrates. In addition, in this specification, etc., the term "SOI substrate" includes those having a "Solid substrate" does not only refer to a substrate made of semiconductor material, but also to any substrate that contains semiconductor material. In other words, in this specification, the term "SOI substrate" is also broadly used to refer to a "semiconductor substrate." is included.

[0028] In this specification and the like, a semiconductor material other than an oxide semiconductor is a semiconductor material other than an oxide semiconductor. Any semiconductor material may be used as long as it is a conductive material. For example, silicon, germanium, Silicon germanium, silicon carbide, gallium arsenide, etc. Others include organic semiconductors. Materials such as those constituting semiconductor devices can also be used. If not, either an oxide semiconductor material or a semiconductor material other than an oxide semiconductor is used. Good too. Effect of the Invention

[0029] In one embodiment of the present invention, a transistor using a material other than an oxide semiconductor for a channel formation region is provided in the lower portion. and a transistor having an oxide semiconductor in a channel formation region therein. A semiconductor device is provided.

[0030] Since a transistor using an oxide semiconductor has an extremely low off-state current, It is possible to retain the memory contents for a much longer period of time. This eliminates the need for refresh operations or makes it possible to reduce the frequency of refresh operations to an extremely low level. Therefore, power consumption can be sufficiently reduced. It is possible to retain the stored contents for a long period of time.

[0031] In addition, high voltage is not required to write information, and there is no problem with element degradation. Unlike non-volatile memory, there is no need to inject and extract electrons from the floating gate. In other words, the semiconductor device according to the present embodiment does not suffer from any deterioration, such as deterioration of the gate insulating layer. Semiconductor devices do not have the limitations on the number of times they can be rewritten, which is a problem with conventional non-volatile memories. This will dramatically improve reliability. Furthermore, the on and off states of transistors will determine the information Since the information is written in the memory, high-speed operation can be easily achieved. Another advantage is that no action is required to erase previous information.

[0032] In addition, transistors using materials other than oxide semiconductors can operate at sufficiently high speed. By using this, it is possible to read out the stored contents at high speed.

[0033] Furthermore, since the boost circuit makes it easy to realize multi-level data, the memory capacity can be improved. It is possible.

[0034] In this way, transistors using materials other than oxide semiconductors and transistors using oxide semiconductors By integrating a transistor, a semiconductor device with unprecedented features can be realized. It is possible. [Brief description of the drawings]

[0035] [Figure 1] FIG. 1 is a circuit diagram illustrating a semiconductor device. [Diagram 2] 1A and 1B are a cross-sectional view and a plan view illustrating a semiconductor device. [Diagram 3] 1A to 1C are cross-sectional views illustrating a manufacturing process of a semiconductor device. [Figure 4] 1A to 1C are cross-sectional views illustrating a manufacturing process of a semiconductor device. [Diagram 5] 1A to 1C are cross-sectional views illustrating a manufacturing process of a semiconductor device. [Figure 6] FIG. 1 is a cross-sectional view of a transistor including an oxide semiconductor. [Figure 7] Energy band diagram (schematic diagram) at the A-A' cross section in Figure 6. [Figure 8](A) shows the state when a positive potential (+VG) is applied to the gate (GE1), and (B) shows the state when a negative potential (VG<0) is applied to the gate (GE1). [Figure 9] A diagram showing the relationship between the vacuum level, the work function of a metal (φM), and the electron affinity of an oxide semiconductor (χ). [Figure 10] FIG. [Figure 11] A graph showing the relationship between Vg and (1 / C)2. [Figure 12] 1 is a cross-sectional view illustrating a semiconductor device. [Figure 13] 1 is a cross-sectional view illustrating a semiconductor device. [Figure 14] 1 is a cross-sectional view illustrating a semiconductor device. [Figure 15] 1 is a cross-sectional view illustrating a semiconductor device. [Figure 16] FIG. 1 is a circuit diagram illustrating a memory element. [Figure 17] FIG. 1 is a circuit diagram illustrating a semiconductor device. [Figure 18] FIG. 4 is a circuit diagram illustrating a drive circuit. [Figure 19] FIG. 4 is a circuit diagram illustrating a drive circuit. [Figure 20] FIG. 4 is a circuit diagram illustrating a read circuit. [Figure 21] FIG. 4 is a circuit diagram for explaining a potential generating circuit. [Figure 22] FIG. 4 is a circuit diagram for explaining a boost circuit. [Diagram 23] FIG. 1 is a circuit diagram for explaining a differential sense amplifier. [Figure 24] FIG. 1 is a circuit diagram for explaining a latch-type sense amplifier. [Diagram 25] FIG. 4 is a timing chart for explaining the operation. [Figure 26] FIG. 1 is a circuit diagram illustrating a semiconductor device. [Figure 27] FIG. 4 is a circuit diagram illustrating a read circuit. [Figure 28] FIG. 4 is a timing chart for explaining the operation. [Figure 29]FIG. 2 is a diagram for explaining a read circuit. [Diagram 30] FIG. 4 is a timing chart for explaining the operation. [Diagram 31] FIG. 1 is a circuit diagram illustrating a memory element. [Diagram 32] FIG. 1 is a circuit diagram illustrating a semiconductor device. [Diagram 33] FIG. 4 is a circuit diagram illustrating a read circuit. [Diagram 34] FIG. 4 is a circuit diagram illustrating a drive circuit. [Diagram 35] FIG. 4 is a timing chart for explaining the operation. [Diagram 36] FIG. 13 is a diagram showing the relationship between node A and the word line potential. [Figure 37] 1A to 1C are diagrams for explaining electronic devices. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0036] An embodiment of the present invention will be described below with reference to the drawings. The present invention is not limited to the above description, and may be modified in various forms and without departing from the spirit and scope of the present invention. It will be readily understood by those skilled in the art that various modifications may be made to the details. The present invention should not be construed as being limited to the description of the embodiment shown in the accompanying drawings.

[0037] In addition, the position, size, range, etc. of each component shown in the drawings are not necessarily the same as in the actual embodiment, for ease of understanding. Therefore, the actual position, size, range, etc. of the product may not necessarily be the same as those shown in the drawings, etc. There is no limitation to the position, size, range, etc. shown.

[0038] In this specification, ordinal numbers such as "first," "second," and "third" are used to avoid confusion of components. It should be noted that the numbers are added to avoid confusion and are not intended to be limiting.

[0039] (Embodiment 1) In this embodiment, a structure and a manufacturing method of a semiconductor device according to one embodiment of the disclosed invention will be described. This will be described with reference to FIGS.

[0040] <Circuit configuration of semiconductor device> FIG. 1 shows an example of a circuit configuration of a semiconductor device. The transistor 160 is made of a material and the transistor 162 is made of an oxide semiconductor. Note that in FIG. 1, the transistor 162 is formed using an oxide semiconductor. For ease of illustration, the OS code is also included.

[0041] Here, the gate electrode of transistor 160 and the source electrode or drain of transistor 162 are The first line (1st Line) is electrically connected to one of the drain electrodes. The second line (also called a source line) and the source electrode of the transistor 160 are electrically connected to each other. The wiring (2nd Line: also called bit line) and the drain electrode of the transistor 160 are electrically connected. A third wiring (3rd Line: also called the first signal line) The other of the source electrode and the drain electrode of the transistor 162 is electrically connected to A fourth wiring (also called a second signal line) and the transistor 162 It is electrically connected to the gate electrode.

[0042] The transistor 160 using a material other than an oxide semiconductor can operate at sufficiently high speed. By using this, it is possible to read out the stored contents at high speed. The transistor 162 including an oxide semiconductor has an extremely low off-state current. Therefore, when the transistor 162 is turned off, the transistor 160 It is possible to hold the potential of the gate electrode for an extremely long period of time.

[0043] By taking advantage of the feature that the potential of the gate electrode can be maintained for a long period of time, As such, information can be written, retained, and read.

[0044] First, the writing and holding of information will be explained. The transistor 162 is turned on by applying a potential that turns on the transistor 162 . As a result, the potential of the third wiring is applied to the gate electrode of the transistor 160 (write After that, the potential of the fourth wiring is set to a potential at which the transistor 162 is turned off. By turning off the transistor 162, the gate electrode of the transistor 160 The potential is maintained (retained).

[0045] Since the off-state current of the transistor 162 is extremely small, the gate electrode of the transistor 160 The potential is maintained for a long period of time. For example, if the potential of the gate electrode of transistor 160 is If the potential is such that the transistor 160 is turned on, the transistor 160 will remain on for a long time. The potential of the gate electrode of the transistor 160 is maintained for a certain period of time. If the potential is such that the transistor 160 is turned off, the transistor 160 will remain in the off state for a long time. is retained over time.

[0046] Next, the reading of information will be described. As described above, when the transistor 160 is in the on state, Alternatively, when the off state is maintained, a predetermined potential (low potential) is applied to the first wiring. When the transistor 160 is turned on, the potential of the second wiring changes depending on whether the transistor 160 is turned on or off. For example, when the transistor 160 is on, the potential of the first wiring As a result, the potential of the second wiring is lowered. In the off state, the potential of the second wiring does not change.

[0047] In this manner, in a state in which information is held, the potential of the first wiring and the potential of the second wiring are By comparing, information can be read out.

[0048] Next, the rewriting of information will be described. The rewriting of information includes the above-mentioned writing of information and That is, the potential of the fourth wiring is held in the same manner as when the transistor 162 is turned on. This causes the transistor 162 to be turned on. (a potential related to new information) is applied to the gate electrode of transistor 160. Then, The potential of the fourth wiring is set to a potential at which the transistor 162 is turned off. By turning off 62, the new information is held.

[0049] In this way, the semiconductor device according to the disclosed invention can directly read data by rewriting the data. It is possible to rewrite information. This is why it is necessary for flash memory etc. This eliminates the need for an erase operation, and makes it possible to suppress a decrease in operation speed caused by the erase operation. That is, high speed operation of the semiconductor device is achieved.

[0050] The above explanation is for n-type transistors (n-channel transistors) that use electrons as carriers. ) is used, but instead of an n-type transistor, a It goes without saying that a p-type transistor can be used.

[0051] In order to facilitate the retention of the potential of the gate electrode of the transistor 160, It goes without saying that a capacitance element or the like may be added to the gate electrode 160 .

[0052] <Plane and cross-sectional configurations of semiconductor device> FIG. 2 shows an example of the configuration of the semiconductor device. FIG. 2(A) shows a cross section of the semiconductor device. 2(B) shows a plan view of the semiconductor device. These correspond to the cross sections taken along lines A1-A2 and B1-B2 in FIG. 2(A) and FIG. 2(B). The semiconductor device shown in FIG. 1 has a transistor 160 using a material other than an oxide semiconductor in the lower portion. The transistor 162 includes an oxide semiconductor in the upper portion. Transistor 160 and transistor 162 are both described as n-type transistors. However, a p-type transistor may be used. In particular, the transistor 160 is preferably a p-type transistor. It is possible.

[0053] The transistor 160 includes a channel forming region 11 provided in a substrate 100 including a semiconductor material. 6, and the impurity region 114 and the high concentration impurity region 115 are provided so as to sandwich the channel forming region 116. A pure region 120 (collectively referred to as an impurity region) and a channel forming region 11 6, and a gate insulating layer 108a provided on the gate insulating layer 108a. The electrode 110a and the impurity region 114 provided on one side of the channel forming region 116 are connected to each other. The source electrode or drain electrode 130a and the channel forming region 116 are electrically connected to each other. A source electrode or a drain electrode electrically connected to the impurity region 114 provided on one side 130b.

[0054] Here, a sidewall insulating layer 118 is provided on the side surface of the gate electrode 110a. In addition, the substrate 100 is provided with a sidewall insulating layer 118 sandwiched therebetween in a plan view. , a high-concentration impurity region 120, and a metal compound region 124 on the high-concentration impurity region 120. In addition, on the substrate 100, an element isolation insulating film is formed so as to surround the p-type transistor 160. A layer 106 is provided, and an interlayer insulating layer 126 and a layer 107 are provided to cover the p-type transistor 160. and an interlayer insulating layer 128 are provided. Through the opening, the source electrode or drain electrode 130a is connected to the channel forming region 1 16 is electrically connected to a metal compound region 124 provided on one side of the The drain electrode 130b is a metal compound semiconductor layer provided on the other side of the channel forming region 116. Electrically connected to region 124. That is, source electrode or drain electrode 130a The channel is formed through a metal compound region 124 provided on one side of the channel forming region 116. A high concentration impurity region 120 and a channel forming region 122 are provided on one side of the channel forming region 116. The region 116 is electrically connected to the impurity region 114 provided on one side thereof, and is connected to a source electrode. The drain electrode 130b is a metal compound electrode provided on the other side of the channel forming region 116. A high-concentration impurity region is provided on the other side of the channel forming region via a material region. 120 and the impurity region 114 provided on the other side of the channel forming region 116. The gate electrode 110a is connected to a source electrode or drain electrode 13. The electrode 130c, which is provided similarly to the source electrode 130a and the source or drain electrode 130b, is electrically is connected to

[0055] The transistor 162 includes a gate electrode 136d provided on the interlayer insulating layer 128 and a gate A gate insulating layer 138 is provided on the electrode 136d. An oxide semiconductor layer 140 and a second insulating film provided on the oxide semiconductor layer 140. A source electrode or drain electrode 142a, which is electrically connected to the source electrode or drain electrode 142b, and an in-electrode 142b.

[0056] Here, the gate electrode 136d is embedded in the insulating layer 132 formed on the interlayer insulating layer 128. Similarly to the gate electrode 136d, the source electrode An electrode 136a is in contact with the drain electrode 130a, and a source or drain electrode 130b is in contact with the drain electrode 130b. An electrode 136b is formed in contact with the electrode 130c, and an electrode 136c is formed in contact with the electrode 130c. do.

[0057] In addition, a protective layer is provided on the transistor 162 so as to be in contact with part of the oxide semiconductor layer 140. An insulating layer 144 is provided, and an interlayer insulating layer 146 is provided on the protective insulating layer 144. Here, the protective insulating layer 144 and the interlayer insulating layer 146 are provided with a source electrode or a drain electrode. The openings reach the source electrode 142a and the source or drain electrode 142b. Through the opening, the electrode 150d and the electrode 150e are connected to the source electrode or the drain electrode. The electrode 142a is formed in contact with the source electrode or the drain electrode 142b. As well as the electrode 150d and the electrode 150e, the gate insulating layer 138, the protective insulating layer 144, the interlayer insulating The layer 146 is provided with openings through which the electrodes 136a, 136b, and 136c are in contact. Electrodes 150a, 150b, and 150c are formed.

[0058] Here, impurities such as hydrogen are sufficiently removed from the oxide semiconductor layer 140, and the oxide semiconductor layer 140 is highly purified. Specifically, the hydrogen concentration in the oxide semiconductor layer 140 is preferably 5×10 19 atoms / cm 3 Less than 5×10 18 atoms / cm 3 More hopes below Preferably 5 x 10 17 atoms / cm 3 In addition, it must contain sufficient oxygen. It is desirable that the defects caused by oxygen deficiency are reduced by the above-mentioned method. The oxide semiconductor layer 14 is highly purified by reducing the amount of oxygen in the oxide semiconductor layer 14 and has fewer defects caused by oxygen deficiency. At 0, the carrier concentration is 1×10 12 / cm 3 Below 1×10 11 / cm 3 In this way, the i-type (intrinsic) or substantially i-type oxide semiconductor is By using this, a transistor 162 with excellent off-state current characteristics can be obtained. For example, when the drain voltage Vd is +1V or +10V, and the gate voltage Vg is -5 Between V and -20 V, the off-state current is 1×10 -13 A or less. Thus, hydrogen The concentration is sufficiently reduced to achieve high purification, and defects due to oxygen deficiency are reduced. By applying the dielectric layer 140 and reducing the off-current of the transistor 162, a new configuration In addition, when the hydrogen concentration in the oxide semiconductor layer 140 is is secondary ion mass spectrometry (SIMS). The measurements were taken using a CT scan.

[0059] An insulating layer 152 is provided on the interlayer insulating layer 146, and a buried insulating film is formed in the insulating layer 152. Electrodes 154a, 154b, 154c, and 154d are provided so that the electrodes 154a, 154b, 154c, and 154d are inserted into the Here, electrode 154a is in contact with electrode 150a, and electrode 154b is in contact with electrode 150. b, electrode 154c is in contact with electrode 150c and electrode 150d, and electrode 1 54d is in contact with electrode 150e.

[0060] That is, in the semiconductor device shown in FIG. 2, the gate electrode 110a of the transistor 160 and The source or drain electrode 142a of the transistor 162 is connected to the electrode 130c. 136c, the electrode 150c, the electrode 154c and the electrode 150d are electrically connected to each other. There are.

[0061] <Method for manufacturing semiconductor device> Next, an example of a method for manufacturing the above semiconductor device will be described. A method for fabricating the transistor 160 will be described with reference to FIG. A method for producing the heater 162 will be described with reference to FIGS.

[0062] <How to make the lower transistor> First, a substrate 100 containing a semiconductor material is prepared (see FIG. 3(A)). The plate 100 may be a single crystal semiconductor substrate such as silicon or silicon carbide, or a polycrystalline semiconductor substrate. Compound semiconductor substrates such as silicon germanium, SOI substrates, etc. can be used. Here, a single crystal silicon substrate is used as the substrate 100 containing a semiconductor material. In general, an "SOI substrate" is a substrate that has a silicon semiconductor on an insulating surface. A substrate having a conductor layer formed thereon is referred to as a substrate having a silicon layer formed on an insulating surface. The term "substrate" is used as a concept including a substrate having a semiconductor layer made of a material other than silicon. The semiconductor layer of the "SOI substrate" is not limited to a silicon semiconductor layer. The substrate is a structure in which a semiconductor layer is provided on an insulating substrate such as a glass substrate via an insulating layer. This includes the following:

[0063] A protective layer 102 is formed on the substrate 100 to serve as a mask for forming an element isolation insulating layer. (See FIG. 3(A)). The protective layer 102 is made of, for example, silicon oxide, silicon nitride, An insulating layer made of silicon oxynitride or the like can be used. In order to control the threshold voltage of a transistor, impurities that give n-type conductivity are used. The substrate 100 may be doped with an impurity element that imparts p-type conductivity or an impurity element that imparts p-type conductivity. In the case of silicon, impurities that give n-type conductivity are, for example, phosphorus or arsenic. In addition, examples of impurities that impart p-type conductivity include boron and aluminum. For example, nium, gallium, etc. can be used.

[0064] Next, etching is performed using the protective layer 102 as a mask, and the The part of the substrate 100 in the area where the semiconductor device is not attached (the exposed area) is removed. The conductor region 104 is formed (see FIG. 3(B)). It is preferable to use an etching gas or an etchant, but wet etching may also be used. The etching liquid can be appropriately selected depending on the material to be etched.

[0065] Next, an insulating layer is formed so as to cover the semiconductor region 104, and a region overlapping the semiconductor region 104 is The insulating layer is selectively removed to form an element isolation insulating layer 106 (see FIG. 3(B)). The insulating layer is formed using silicon oxide, silicon nitride, silicon nitride oxide, etc. Methods for removing the insulating layer include polishing such as CMP and etching. After the semiconductor region 104 is formed or after the element isolation insulating layer 1 After the formation of the insulating film 06, the protective layer 102 is removed.

[0066] Next, an insulating layer is formed on the semiconductor region 104, and a layer containing a conductive material is formed on the insulating layer. do.

[0067] The insulating layer will later become the gate insulating layer and is obtained using a method such as CVD or sputtering. Silicon oxide, silicon nitride oxide, silicon nitride, hafnium oxide, aluminum oxide, etc. It is preferable to use a single layer or multilayer structure of a film containing aluminum, tantalum oxide, etc. The surface of the semiconductor region 104 is oxidized or nitrided by plasma treatment or thermal oxidation treatment. The insulating layer may be formed by the high density plasma treatment. A mixture of rare gases such as e and oxygen, nitrogen oxide, ammonia, nitrogen, hydrogen, etc. The thickness of the insulating layer is not particularly limited, but may be, for example, 1n The thickness can be m or more and 100 nm or less.

[0068] The layer containing a conductive material is a metal material such as aluminum, copper, titanium, tantalum, or tungsten. Also, the insulating layer can be formed using a semiconductor material such as polycrystalline silicon containing a conductive material. The method of formation is not particularly limited, and examples of the method include deposition, C Various film formation methods such as the VD method, the sputtering method, and the spin coating method can be used. In this embodiment, the layer containing a conductive material is formed using a metal material. The following information will be provided.

[0069] Thereafter, the insulating layer and the layer containing the conductive material are selectively etched to form the gate insulating layer 108. A gate electrode 110a is formed (see FIG. 3(C)).

[0070] Next, an insulating layer 112 is formed to cover the gate electrode 110a (see FIG. 3(C)). By doping the semiconductor region 104 with phosphorus (P) or arsenic (As), an impurity region with a shallow junction depth is formed. In this case, in order to form an n-type transistor, a region 114 is formed (see FIG. 3(C)). For this purpose, phosphorus or arsenic is added, but for p-type transistors, boron (B) or An impurity element such as aluminum (Al) may be added. As a result of this formation, a channel forming region 116 is formed below the gate insulating layer 108a of the semiconductor region 104. (See FIG. 3(C)). The concentration of the added impurity can be appropriately set. However, when semiconductor elements are highly miniaturized, it is desirable to increase the concentration. In this embodiment, the step of forming the impurity region 114 is performed after forming the insulating layer 112. However, it may be possible to form the insulating layer 112 after forming the impurity region 114. stomach.

[0071] Next, a sidewall insulating layer 118 is formed (see FIG. 3(D)). The layer 118 is formed by forming an insulating layer to cover the insulating layer 112 and then applying a highly anisotropic By applying a slow etching process, the film can be formed in a self-aligned manner. The insulating layer 112 is partially etched to expose the upper surface of the gate electrode 110a and the impurity region 11 It is a good idea to expose the top surface of 4.

[0072] Next, a layer is formed so as to cover the gate electrode 110a, the impurity region 114, the sidewall insulating layer 118, etc. Then, phosphorus (P) or arsenic is doped in the region in contact with the impurity region 114. By doping arsenic (As) or the like, a high concentration impurity region 120 is formed (see FIG. 3(E)). Thereafter, the insulating layer is removed, and the gate electrode 110a, the sidewall insulating layer 118, and the high concentration impurity A metal layer 122 is formed so as to cover the pure region 120 and the like (see FIG. 3(E)). 122 is formed by various deposition methods such as vacuum deposition, sputtering, and spin coating. The metal layer 122 can be formed by reacting with the semiconductor material that constitutes the semiconductor region 104. It is preferable to form the metal layer using a metal material that forms a metal compound having low resistance. Metal materials include, for example, titanium, tantalum, tungsten, nickel, cobalt, and platinum. etc.

[0073] Next, a heat treatment is performed to react the metal layer 122 with the semiconductor material. A metal compound region 124 is formed in contact with the high concentration impurity region 120 (see FIG. 3(F)). When polycrystalline silicon or the like is used as the gate electrode 110a, the gate electrode 11 A metal compound region is also formed in the portion of 0a that contacts the metal layer 122.

[0074] The heat treatment may be, for example, a heat treatment by irradiation with a flash lamp. Of course, other heat treatment methods may be used, but the chemical reaction involved in the formation of metal compounds is In order to improve the controllability of the heat treatment, it is desirable to use a method that can realize a very short heat treatment. The metal compound region 124 is preferably formed by a reaction between a metal material and a semiconductor material. The metal compound region 124 is formed of a metal compound having a sufficiently high conductivity. By forming the insulating layer, the electrical resistance can be sufficiently reduced and the device characteristics can be improved. After forming the metal compound regions 124, the metal layer 122 is removed.

[0075] Next, an interlayer insulating layer 126 and an interlayer insulating layer 127 are formed to cover the respective components formed by the above-mentioned steps. The interlayer insulating layer 126 and the interlayer insulating layer 128 are formed by using silicon oxide. Silicon, silicon oxide nitride, silicon nitride, hafnium oxide, aluminum oxide, tantalum oxide The insulating layer can be formed using a material containing an inorganic insulating material such as niobium. It is also possible to form the insulating layer using an organic insulating material such as acrylic. Although the substrate has a two-layer structure of an edge layer 126 and an interlayer insulating layer 128, the structure of the interlayer insulating layer is not limited to this. After the interlayer insulating layer 128 is formed, the surface is polished by CMP, etching, or the like. It is desirable to flatten the surface by using a special tool.

[0076] Thereafter, an opening is formed in the interlayer insulating layer so as to reach the metal compound region 124. A source electrode or drain electrode 130a and a source electrode or drain electrode 130b are provided on the The source electrode or drain electrode 130a and the source electrode or The drain electrode 130b is formed by, for example, depositing a layer on a region including an opening using a PVD method, a CVD method, or the like. After the conductive layer is formed, a part of the conductive layer is removed by a method such as etching or CMP. It can be formed by removing

[0077] In addition, a part of the conductive layer is removed to form the source electrode or drain electrode 130a and the source electrode Alternatively, when forming the drain electrode 130b, the surface of the electrode is processed to be flat. For example, after forming a thin titanium film or titanium nitride film in the region including the opening, When a tungsten film is formed to fill the opening, the inclusions are removed by the subsequent CMP. The necessary tungsten film, titanium film, titanium nitride film, etc. are removed, and the flatness of the surface is improved. In this way, the source electrode or drain electrode 130a, By planarizing the surface including the source or drain electrode 130b, This makes it possible to form good electrodes, wiring, insulating layers, semiconductor layers, and the like.

[0078] In this case, the source electrode or drain electrode 130 in contact with the metal compound region 124 Although only the source electrode 130a or the drain electrode 130b is shown, in this process, Electrodes in contact with the base electrode 110a (for example, electrode 130c in FIG. 2(A)) and the like. The source electrode or drain electrode 130a, the source electrode or There is no particular limitation on the material that can be used for the drain electrode 130b. For example, molybdenum, titanium, chromium, tantalum, tungsten, etc. Conductive materials such as stainless steel, aluminum, copper, neodymium, and scandium can be used. Cut.

[0079] In this manner, a transistor 160 is formed using the substrate 100 containing a semiconductor material. After the above steps, electrodes, wiring, an insulating layer, etc. may be further formed. In addition, by adopting a multilayer wiring structure consisting of a laminated structure of interlayer insulating layers and conductive layers, Therefore, it is possible to provide a highly integrated semiconductor device.

[0080] <How to make the upper transistor> Next, a process for forming a transistor 162 on the interlayer insulating layer 128 will be described with reference to FIGS. 4 and 5 show various electrodes and transistors on the interlayer insulating layer 128. Since the figure shows the manufacturing process of the transistor 162, the The transistor 160 and other components that correspond to it are omitted.

[0081] First, an interlayer insulating layer 128, a source electrode or drain electrode 130a, An insulating layer 132 is formed on the drain electrode 130b and the electrode 130c (see FIG. 4(A)). The edge layer 132 can be formed by using a PVD method, a CVD method, or the like. Silicon oxide nitride, silicon nitride, hafnium oxide, aluminum oxide, tantalum oxide The insulating film 10 can be formed using a material containing an inorganic insulating material such as silica.

[0082] Next, the source or drain electrode 130a, the source or Openings are formed so as to reach the drain electrode 130b and the electrode 130c. An opening is also formed in the region where the gate electrode 136d is to be formed. A conductive layer 134 is formed so as to fill the opening (see FIG. 4B). The mask can be formed by a method such as etching using a photomask. It can be formed by a method such as exposure to light. As for etching, wet etching is used. Either etching or dry etching may be used, but from the viewpoint of fine processing, dry etching is preferred. The conductive layer 134 is preferably formed by a deposition method such as PVD or CVD. The conductive layer 134 can be formed by a film method. , molybdenum, titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium Conductive materials such as ZnO, ZnSe, and scandium, as well as their alloys and compounds (e.g., nitrides) are examples of such materials. can be done.

[0083] More specifically, for example, a thin titanium film is formed by PVD in the area including the opening, and then CV After forming a thin titanium nitride film by the D method, a tungsten film is formed to fill the opening. Here, the titanium film formed by the PVD method has a boundary. The oxide film on the surface is reduced, and the lower electrode (here, the source electrode or drain electrode 130a, A function of reducing the contact resistance with the source electrode or drain electrode 130b, electrode 130c, etc. In addition, the titanium nitride film formed thereafter has a burr-free property that suppresses the diffusion of the conductive material. In addition, after forming a barrier film using titanium or titanium nitride, etc., plating is performed. The copper film may be formed by a method.

[0084] After the conductive layer 134 is formed, the conductive layer 134 is etched or CMPed. 13, a part of the insulating layer 132 is removed to expose the insulating layer 132, and the electrodes 136a, 136b, and 136 c, a gate electrode 136d is formed (see FIG. 4(C)). are removed to form electrodes 136a, 136b, 136c, and a gate electrode 136d. In this case, it is desirable to process the insulating layer 132 so that the surface is flat. The surfaces of the electrodes 136a, 136b, 136c, and the gate electrode 136d are planarized. As a result, good electrodes, wiring, insulating layers, semiconductor layers, etc. can be formed in the subsequent steps. This becomes possible.

[0085] Next, the insulating layer 132, the electrode 136a, the electrode 136b, the electrode 136c, and the gate electrode 136d are The gate insulating layer 138 is formed so as to cover the gate insulating layer 138 (see FIG. 4(D)). The gate insulating layer can be formed by using a CVD method, a sputtering method, or the like. 138 is silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, aluminum oxide, oxide It is preferable to form the gate insulating film so as to contain hafnium, tantalum oxide, or the like. The layer 138 may have a single layer structure or a multilayer structure. Silicon oxynitride was produced by plasma CVD using silane (SiH4), oxygen, and nitrogen. The thickness of the gate insulating layer 138 is not particularly limited. However, for example, it can be set to 10 nm or more and 500 nm or less. For example, a first gate insulating layer having a thickness of 50 nm to 200 nm and a first gate insulating It is preferable to laminate a second gate insulating layer having a thickness of 5 nm to 300 nm on the layer.

[0086] Note that an oxide semiconductor (high-temperature oxide semiconductor) that has been made i-type or substantially i-type by removing impurities can be used. Since the purified oxide semiconductor is extremely sensitive to the interface states and the interface charges, When using such an oxide semiconductor for the oxide semiconductor layer, the interface with the gate insulating layer is important. That is, the gate insulating layer 138 in contact with the highly purified oxide semiconductor layer has a high quality There will be a demand for quality improvement.

[0087] For example, the high-density plasma CVD method using microwaves (2.45 GHz) produces dense, high-insulation-voltage This is advantageous in that a high quality gate insulating layer 138 can be formed. The intimate contact between the conductor layer and the high-quality gate insulating layer reduces the interface state and improves the interface characteristics. Because it can be made to be a good thing.

[0088] Of course, if it can form a good insulating layer as a gate insulating layer, highly purified Even when an oxide semiconductor layer is used, other methods such as sputtering and plasma CVD are used. In addition, the film quality and interface characteristics can be improved by heat treatment after formation. In any case, the film quality of the gate insulating layer 138 is good. At the same time, the interface state density with the oxide semiconductor layer can be reduced to form a good interface. It is sufficient to form the following.

[0089] Furthermore, at a temperature of 85°C and an electric field strength of 2×10 6 V / cm, 12 hours gate bias and thermal stress In the BET test, when impurities are added to an oxide semiconductor, The bond with the main component of the oxide semiconductor is broken by a strong electric field (B: bias) and high temperature (T: temperature). The dangling bonds that are generated induce a drift in the threshold voltage (Vth). .

[0090] In response to this, impurities in oxide semiconductors, particularly hydrogen and water, should be eliminated as much as possible, and the above-mentioned By improving the interface characteristics with the base insulating layer, a stable transistor is produced even in the BT test. It is possible to obtain the data.

[0091] Next, an oxide semiconductor layer is formed over the gate insulating layer 138 and etched using a mask. The oxide semiconductor layer is processed by a method such as the above to form an island-shaped oxide semiconductor layer 140. (See FIG. 4(E)).

[0092] The oxide semiconductor layer is made of a quaternary metal oxide, In-Sn-Ga-Zn-O, or a ternary metal oxide, In-Sn-Ga-Zn-O. In-Ga-Zn-O, In-Sn-Zn-O, In-Al-Zn- O, Sn-Ga-Zn-O, Al-Ga-Zn-O, Sn-Al-Zn-O, and binary metals Metal oxides such as In-Zn-O, Sn-Zn-O, Al-Zn-O, Zn-Mg-O, and S n-Mg-O, In-Mg-O, and single-element metal oxides such as In-O, Sn-O, and Zn- An oxide semiconductor layer using O or the like can be used. SiO2 may also be included.

[0093] The oxide semiconductor layer is InMO3(ZnO) m Use a thin film represented by (m>0) Here, M is one or more selected from Ga, Al, Mn and Co. Metal element. For example, M is Ga, Ga and Al, Ga and Mn, or Ga and Co, etc. InMO3(ZnO) m An oxide semiconductor film having a structure represented by (m>0) Among these, oxide semiconductors with a structure containing Ga as M are called In-Ga-Zn-O oxide semiconductors. The thin film is called an In-Ga-Zn-O oxide semiconductor film (In-Ga-Zn-O In this paper, we will refer to these films as amorphous films.

[0094] In this embodiment, an oxide semiconductor layer is formed using an In-Ga-Zn-O oxide semiconductor film forming method. An amorphous oxide semiconductor layer is formed by a sputtering method using a target. Note that by adding silicon to an amorphous oxide semiconductor layer, crystallization of the amorphous oxide semiconductor layer can be suppressed. Therefore, for example, a target containing SiO2 in an amount of 2% by weight or more and 10% by weight or less is used. The oxide semiconductor layer may be formed by using a method similar to that described above.

[0095] Examples of targets for forming an oxide semiconductor layer by a sputtering method include oxide A target made of a metal oxide mainly composed of zinc can be used. In, Ga, and Zn-containing oxide semiconductor film deposition target (composition ratio: In2O3:Ga2O 3:ZnO=1:1:1 [molar ratio]) can also be used. In, Ga As a target for forming oxide semiconductor films containing Zn, In2O3:Ga2O3:Z nO=1:1:2 [molar ratio], or In2O3:Ga2O3:ZnO=1:1:4 A target having a composition ratio of [molar ratio] may be used. The target filling rate is 90% or more and 100% or less, preferably 95% or more (e.g., 99.9%). By using a target for oxide semiconductor deposition with a high filling rate, dense oxide A compound semiconductor layer is formed.

[0096] The oxide semiconductor layer is formed in a rare gas (typically, argon) atmosphere, an oxygen atmosphere, or a fluorine-containing gas atmosphere. Alternatively, it is preferable to use a mixed atmosphere of a rare gas (typically argon) and oxygen. In general, impurities such as hydrogen, water, hydroxyl groups, and hydrides are present at concentrations of about several ppm (desirable). It is preferable to use a high-purity gas in which the concentration has been reduced to about several ppb.

[0097] When forming the oxide semiconductor layer, the substrate is held in a treatment chamber kept in a reduced pressure state. The temperature is set to 100°C or higher and 600°C or lower, preferably 200°C or higher and 400°C or lower. By forming the oxide semiconductor layer while performing the above-mentioned step, the impurity concentration in the oxide semiconductor layer can be reduced. The damage caused by sputtering can be reduced. The residual moisture in the metal oxide film is removed, and a sputtering gas from which hydrogen and water have been removed is introduced. In order to remove residual moisture in the treatment chamber, It is preferable to use an adsorption type vacuum pump. For example, a cryopump or an ion pump A titanium sublimation pump can be used. A cryopump with a cold trap may be used. The deposition chamber is filled with, for example, hydrogen atoms, compounds containing hydrogen atoms such as water (H2O) (preferably Since the oxide semiconductor formed in the film formation chamber is exhausted, The concentration of impurities contained in the layer can be reduced.

[0098] The formation conditions are, for example, a distance between the substrate and the target of 100 mm and a pressure of 0.6 Pa, DC power 0.5kW, oxygen atmosphere (oxygen flow rate 100%) The following conditions can be applied. When a pulsed direct current (DC) power supply is used, the deposition This reduces the amount of powdery material (also called particles or dust) that is generated during coating, and also makes the film thickness distribution uniform. The thickness of the oxide semiconductor layer is preferably 2 nm to 200 nm. The thickness is 5 nm to 30 nm. Note that the appropriate thickness varies depending on the oxide semiconductor material used. Therefore, the thickness may be appropriately selected depending on the material used.

[0099] Before forming the oxide semiconductor layer by sputtering, argon gas was introduced to the plasma A reverse sputtering process is performed to generate a smear, and dust adhering to the surface of the gate insulating layer 138 is removed. Here, the reverse sputtering is a method of removing the sputtering. Instead of bombarding the target with ions, the treatment surface is bombarded with ions. The method of modifying the surface by bombarding the surface with ions is as follows: A high-frequency voltage is applied to the processing surface side in an argon atmosphere to generate plasma near the substrate. In addition, the argon atmosphere can be replaced by a nitrogen atmosphere, a helium atmosphere, or An oxygen atmosphere may also be used.

[0100] The etching of the oxide semiconductor layer can be performed by either dry etching or wet etching. Of course, both can be used in combination. In order to match the etching conditions (etching gas, etching solution, etc.) to the material, The etching time, temperature, etc. should be set appropriately.

[0101] The etching gas used in dry etching is, for example, a gas containing chlorine (chlorine-based gas, For example, chlorine (Cl2), boron chloride (BCl3), silicon chloride (SiCl4), carbon tetrachloride ( CCl4) and others. In addition, gases containing fluorine (fluorine-based gases, such as carbon tetrafluoride) Carbon fluoride (CF4), sulfur hexafluoride (SF6), nitrogen trifluoride (NF3), trifluoromethane (C HF3), hydrogen bromide (HBr), oxygen (O2), and helium (He) or a gas containing a rare gas such as argon (Ar), etc. may be used.

[0102] As a dry etching method, parallel plate type RIE (Reactive Ion Etch) ing method and ICP (Inductively Coupled Plasma) A method of etching a silicon wafer using a plasma-coupled plasma (PPS) can be used. As shown in the figure, the etching conditions (the amount of power applied to the coil-shaped electrode, the amount of power applied to the electrode on the substrate side) The power consumption, electrode temperature on the substrate side, etc. are set appropriately.

[0103] The etching solution used for wet etching is a mixture of phosphoric acid, acetic acid, and nitric acid. Ammonia peroxide water (31% by weight hydrogen peroxide water: 28% by weight ammonia water: water = 5:2:2) In addition, an etching solution such as ITO07N (manufactured by Kanto Chemical Co., Ltd.) can be used. It's fine.

[0104] Next, the oxide semiconductor layer is preferably subjected to a first heat treatment. The temperature of the first heat treatment can be set to The temperature is set to 300° C. or higher and 750° C. or lower, preferably 400° C. or higher and lower than the distortion point of the substrate. For example, The substrate is placed in an electric furnace using a resistance heating element or the like, and the oxide semiconductor layer 140 is heated in a nitrogen atmosphere. During this heat treatment, the oxide semiconductor layer 140 is exposed to the air. Avoid touching and recontamination with water or hydrogen.

[0105] The heat treatment device is not limited to an electric furnace, and may be any device that uses heat conduction from a medium such as a heated gas, or It may be a device that heats the workpiece by thermal radiation. For example, LRTA (Lamp Rapid Thermal Annealing Equipment, GRTA (Gas Rapid RTA (Rapid Thermal Anneal) equipment etc. The LRTA device can be equipped with halogen lamps, metal halide lamps, etc. Lamps, xenon arc lamps, carbon arc lamps, high pressure sodium lamps, high pressure water A device that heats the workpiece by radiating light (electromagnetic waves) emitted from a lamp such as a silver lamp. The GRTA device is a device that performs heat treatment using high-temperature gas. An inert gas that does not react with the workpiece during heat treatment, such as a rare gas such as argon or nitrogen. A gas is used.

[0106] For example, in the first heat treatment, the substrate is immersed in an inert gas heated to a high temperature of 650° C. to 700° C. After heating for a few minutes, the substrate is taken out of the inert gas (GRTA process). GRTA treatment allows high-temperature heat treatment in a short time. Because it is a heat treatment, it can be applied even under temperature conditions exceeding the distortion point of the substrate.

[0107] The first heat treatment is performed in a vacuum chamber mainly containing nitrogen or a rare gas (helium, neon, argon, etc.). It is preferable to carry out the process in an atmosphere that does not contain water, hydrogen, etc. The purity of nitrogen or rare gas such as helium, neon, or argon introduced into the heat treatment device is 6N (99.9999%) or more, preferably 7N (99.99999%) or more (i.e. , the impurity concentration is 1 ppm or less, preferably 0.1 ppm or less.

[0108] Depending on the conditions of the first heat treatment or the material of the oxide semiconductor layer, the oxide semiconductor layer may be crystallized. In some cases, the crystallinity is 90% or more, or 80% or less. % or more of microcrystalline oxide semiconductor layer. Depending on the material of the oxide semiconductor layer, the oxide semiconductor layer may be an amorphous oxide semiconductor layer that does not contain crystalline components. There are also cases where this is the case.

[0109] In addition, the amorphous oxide semiconductor (for example, the surface of the oxide semiconductor layer) may have crystals (grain size of 1 nm or more). In some cases, the oxide semiconductor layer may be a mixture of layers with thicknesses of 20 nm or less (typically 2 nm to 4 nm). be.

[0110] In addition, by providing a crystal layer on an amorphous surface, the electrical characteristics of the oxide semiconductor layer are changed. For example, a target for forming an oxide semiconductor film of In-Ga-Zn-O system is When forming an oxide semiconductor layer using In2Ga2ZnO7 By forming a crystal part in which the crystal grains are oriented, the electrical characteristics of the oxide semiconductor layer are changed. It is possible.

[0111] More specifically, for example, the c-axis of In2Ga2ZnO7 is perpendicular to the surface of the oxide semiconductor layer. By orienting the oxide semiconductor layer in a direction parallel to the surface of the oxide semiconductor layer, the electrical conductivity in the direction parallel to the surface of the oxide semiconductor layer is improved. This can improve the insulating property in the direction perpendicular to the surface of the oxide semiconductor layer. Such a crystal portion has the function of suppressing the intrusion of impurities such as water and hydrogen into the oxide semiconductor layer. Yes.

[0112] Note that the oxide semiconductor layer having the above-mentioned crystal portion is formed by GRTA treatment. It can be formed by surface heating. In addition, the Zn content is higher than the In or Ga content. By using a smaller sputtering target, it is possible to form the film more suitably.

[0113] The first heat treatment for the oxide semiconductor layer 140 is performed to process the oxide semiconductor layer 140 into an island-shaped oxide semiconductor layer 140. In that case, the first heat treatment is performed on the oxide semiconductor layer. The substrate is then removed and subjected to a photolithography process.

[0114] The heat treatment has a dehydration or dehydrogenation effect on the oxide semiconductor layer 140. Therefore, it can also be called dehydration treatment, dehydrogenation treatment, etc. The oxidation treatment is carried out after forming the oxide semiconductor layer, by forming a source electrode or a drain electrode on the oxide semiconductor layer 140. After laminating the source electrode and the drain electrode, a protective insulating layer is formed on the source electrode or the drain electrode. In addition, such dehydration treatment and dehydrogenation can be performed at the following timing. The chemical treatment may be carried out not only once but also multiple times.

[0115] Next, a source electrode or drain electrode 142a, The source or drain electrode 142b is formed (see FIG. 4(F)). The drain electrode 142a and the source or drain electrode 142b are formed on the oxide semiconductor layer 1 After forming a conductive layer so as to cover 40, the conductive layer is selectively etched. It can be formed.

[0116] The conductive layer is formed by using PVD methods such as sputtering and CVD methods such as plasma CVD. The conductive layer can be formed of a material such as aluminum, chromium, copper, Tantalum, titanium, molybdenum, tungsten, or any of the above elements. Manganese, magnesium, zirconium, beryllium, etc. can be used. A material containing one or more elements selected from the group consisting of tungsten, uranium, and thorium may be used. In addition, titanium, tantalum, tungsten, molybdenum, chromium, nickel, Materials containing a single or multiple combinations of elements selected from ZnO, ZnO, and Scandium can also be used. good.

[0117] The conductive layer may be made of a conductive metal oxide. Indium oxide (In2O3), tin oxide (SnO2), zinc oxide (ZnO), indium oxide In2O3-SnO2, sometimes abbreviated as ITO, indium oxide In2O3-ZnO or the above metal oxide materials with silicon or A material containing silicon oxide can be used.

[0118] The conductive layer may have a single layer structure or a laminated structure of two or more layers. A single-layer structure of aluminum film containing conductors, and a two-layer structure of titanium film laminated on aluminum film. and a three-layer structure in which a titanium film, an aluminum film and a titanium film are laminated.

[0119] Here, the exposure to light when forming the mask used for etching is ultraviolet light, KrF laser light, or ArF It is preferable to use laser light.

[0120] As shown in FIG. 4F, the channel length (L) of the transistor is The lower end of the source electrode or drain electrode 142a of the oxide semiconductor layer 140 and the source It is determined by the distance between the bottom end of the channel electrode or drain electrode 142b. When exposing a pattern with a length (L) of less than 25 nm, the length is extremely small, ranging from a few nm to a few tens of nm. Mask formation using extreme ultraviolet light with a short wavelength Exposure to extreme ultraviolet light provides high resolution and a large depth of focus. The channel length (L) of the transistor to be used can be set to 10 nm or more and 1000 nm or less. This enables the circuit to operate at a higher speed. Furthermore, the off-state current is extremely small, so power consumption is reduced. This eliminates the need for large amounts of power.

[0121] In addition, when etching the conductive layer, the oxide semiconductor layer 140 is not removed. The materials and etching conditions are adjusted appropriately. In this step, a part of the oxide semiconductor layer 140 is etched to form a groove (a recess ) may be formed as an oxide semiconductor layer.

[0122] In addition, between the oxide semiconductor layer 140 and the source electrode or drain electrode 142a, An oxide conductive layer is formed between the conductor layer 140 and the source electrode or drain electrode 142b. The oxide conductive layer and the source or drain electrode 142a or The conductive layer for forming the drain electrode 142b is formed continuously (continuous film formation). It is possible. The oxide conductive layer can function as a source region or a drain region. By providing such an oxide conductive layer, the resistance of the source region or the drain region can be reduced. This allows high speed operation of the transistor.

[0123] In order to reduce the number of masks used and the number of processes, an exposure method in which the transmitted light has multiple intensities is used. A resist mask is formed using a multi-tone mask, which is a mask, and the etching process is performed using this. The resist mask formed using the multi-tone mask has a plurality of thicknesses. The shape becomes stepped, and the shape can be further deformed by ashing. It can be used for multiple etching processes to process different patterns. A multi-tone mask is used to create resist masks that correspond to at least two different patterns. Therefore, the number of exposure masks can be reduced, and the corresponding photomasks can be formed. The lithography process can also be eliminated, simplifying the process.

[0124] After the above process, plasma treatment using gas such as N2O, N2, or Ar may be performed. It is preferable that the plasma treatment is performed on the exposed surface of the oxide semiconductor layer. Adherent water and other substances are removed. In addition, gases containing oxygen, such as a mixture of oxygen and argon, In this case, oxygen is supplied to the oxide semiconductor layer, and then a plasma treatment using a gas is performed. It is possible to reduce defects caused by oxygen deficiency.

[0125] Next, the protective insulating layer 14 in contact with a part of the oxide semiconductor layer 140 is removed without exposing it to the air. Form 4 (see Figure 4(G)).

[0126] The protective insulating layer 144 is formed by mixing impurities such as water and hydrogen into the protective insulating layer 144 using a method such as sputtering. The thickness of the insulating film is 1 nm or more. Examples of materials that can be used for the protective insulating layer 144 include silicon oxide, silicon nitride, and silicon oxynitride. The structure may be a single layer structure or a multilayer structure. The substrate temperature when the protective insulating layer 144 is formed is set to be equal to or higher than room temperature and equal to or lower than 300° C. The atmosphere is preferably a rare gas (typically argon) atmosphere, an oxygen atmosphere, or a rare A mixture of gas (typically argon) and oxygen is preferred.

[0127] If hydrogen is contained in the protective insulating layer 144, the hydrogen may penetrate into the oxide semiconductor layer or may be oxidized by the hydrogen. As a result, oxygen is extracted from the oxide semiconductor layer, and the oxide semiconductor layer is The resistance of the protective insulating layer 1 may become low, and a parasitic channel may be formed. It is important that 44 does not contain hydrogen as much as possible, and that hydrogen is not used in the formation method. It is.

[0128] It is also preferable to form the protective insulating layer 144 while removing the residual moisture in the processing chamber. The compound semiconductor layer 140 and the protective insulating layer 144 are preferably made of a material that does not contain hydrogen, hydroxyl groups, or moisture. This is to make it possible.

[0129] To remove residual moisture from within the processing chamber, it is preferable to use an adsorption type vacuum pump. For example, it is preferable to use a cryopump, an ion pump, or a titanium sublimation pump. The exhaust means is a turbo pump with a cold trap added. The deposition chamber evacuated using a cryopump may be filled with hydrogen atoms, water (H2 O) and other compounds containing hydrogen atoms have been removed, The concentration of impurities contained in the layer 144 can be reduced.

[0130] The sputtering gas used in forming the protective insulating layer 144 is hydrogen, water, a hydroxyl group, or Impurities such as hydrides are reduced to a concentration of about several ppm (preferably, a concentration of about several ppb). It is preferred to use high purity gases that have been stripped.

[0131] Then, a second heat treatment (preferably for 20 It is preferable to carry out the heating at a temperature between 0°C and 400°C, for example between 250°C and 350°C. The second heat treatment is performed at 250° C. for 1 hour in a nitrogen atmosphere. The second heat treatment can reduce the variation in the electrical characteristics of the transistors. In this case, oxygen can be supplied to the oxide semiconductor layer.

[0132] In addition, even if heat treatment is performed in air at 100°C to 200°C for 1 hour to 30 hours, This heat treatment may be performed by maintaining a constant heating temperature or by heating from room temperature to 100°C or higher. Repeat heating to a temperature of 200°C or less and then cooling from the heating temperature to room temperature several times. Moreover, this heat treatment may be carried out under reduced pressure before the formation of the protective insulating layer. When the heat treatment is performed under reduced pressure, the heating time can be shortened. This may be carried out instead of the second heat treatment, or may be carried out before or after the second heat treatment.

[0133] Next, an interlayer insulating layer 146 is formed on the protective insulating layer 144 (see FIG. 5(A)). The edge layer 146 can be formed by using a PVD method, a CVD method, or the like. Silicon oxide nitride, silicon nitride, hafnium oxide, aluminum oxide, tantalum oxide The interlayer insulating layer 146 can be formed using a material containing an inorganic insulating material such as fluorine. After that, it is desirable to flatten the surface by a method such as CMP or etching. It is nice.

[0134] Next, an electrode 1 is formed on the interlayer insulating layer 146, the protective insulating layer 144, and the gate insulating layer 138. 36a, electrode 136b, electrode 136c, source or drain electrode 142a, source An opening is formed so as to reach the electrode or drain electrode 142b, and a conductive material is embedded in the opening. A conductive layer 148 is formed (see FIG. 5B). The opening is formed by etching using a mask or the like. The mask can be formed by a method such as exposure using a photomask. The etching method can be wet etching or dry etching. However, from the viewpoint of fine processing, it is preferable to use dry etching. The conductive layer 148 is preferably formed by a film forming method such as a PVD method or a CVD method. Materials that can be used to form the conductive layer 148 include molybdenum, titanium, and the like. Tantalum, chromium, tantalum, tungsten, aluminum, copper, neodymium, scandium, etc. Examples of the conductive materials include any of the conductive materials, their alloys, and compounds (e.g., nitrides).

[0135] Specifically, for example, a thin titanium film is formed in the area including the opening by the PVD method, and then the titanium film is removed by the CVD method. After forming a thin titanium nitride film by , a tungsten film is formed so as to fill the opening. Here, the titanium film formed by the PVD method has a high degree of adhesion at the interface. The oxide film is reduced, and the lower electrodes (here, electrodes 136a, 136b, 136c, a source or drain electrode 142a, a source or drain electrode 142b, etc.) The titanium nitride formed after that has the function of reducing the contact resistance of the conductive layer. It has a barrier function that suppresses the diffusion of materials. It also has a barrier function using titanium and titanium nitride. After the film is formed, a copper film may be formed by plating.

[0136] After the conductive layer 148 is formed, the conductive layer 148 is etched or CMPed. Electrodes 150a, 150b, and 150c are then removed to expose the interlayer insulating layer 146. 50c, an electrode 150d, and an electrode 150e are formed (see FIG. 5(C)). A part of 148 is removed to form electrodes 150a, 150b, 150c, 150d, and When forming the pole 150e, it is desirable to process it so that the surface is flat. As shown in FIG. 1, the interlayer insulating layer 146, the electrode 150a, the electrode 150b, the electrode 150c, the electrode 150d, By planarizing the surface of the electrode 150e, it is possible to obtain good electrodes, wiring, and insulation in the subsequent steps. It is possible to form an insulating layer, a semiconductor layer, etc.

[0137] Further, an insulating layer 152 is formed, and the electrodes 150a, 150b, and 150c are attached to the insulating layer 152. 50c, the electrode 150d, and the electrode 150e are formed, and the After forming the conductive layer as described above, a part of the conductive layer is removed by a method such as etching or CMP. , the insulating layer 152 is exposed, and the electrodes 154a, 154b, 154c, and 154 This step is the same as that for forming the electrodes 150a, etc. Therefore, I will omit the details.

[0138] In the case where the transistor 162 is manufactured by the above-described method, the hydrogen concentration in the oxide semiconductor layer 140 is Degree is 5 x 10 19 / cm3 and the off-current of the transistor 162 is 1×10 -13 A or less. In this way, the hydrogen concentration is sufficiently reduced and the product is highly purified, and there is no oxygen deficiency. By using the oxide semiconductor layer 140 in which defects caused by the above-mentioned are reduced, it is possible to obtain a transistor having excellent characteristics. In addition, a transistor using a material other than an oxide semiconductor can be obtained in the lower portion. The semiconductor device has an excellent semiconductor device having a transistor 160 and a transistor 162 using an oxide semiconductor thereon. It is possible to manufacture a semiconductor device having the above characteristics.

[0139] In addition, in oxide semiconductors, physical properties such as DOS (density of state) Many studies have been done on the localized levels in the energy gap. In one embodiment of the disclosed invention, the cause of the localized level is Water and hydrogen are removed from the oxide semiconductor, whereby a highly purified oxide semiconductor is manufactured. This is based on the idea of ​​sufficiently reducing the localized levels themselves. This makes it possible to manufacture extremely superior industrial products.

[0140] When removing hydrogen and water, oxygen may be removed at the same time. Therefore, oxygen is supplied to the dangling bonds of the metal that are generated due to oxygen deficiency, and localization due to oxygen vacancies occurs. It is preferable to further purify the oxide semiconductor (to make it i-type) by reducing the in-situ level. For example, an oxide film containing excess oxygen is formed in close contact with the channel formation region, and the temperature is increased to 200°C. By performing heat treatment at a temperature of 400℃, typically 250℃, the oxide film is It is possible to supply oxygen to an oxide semiconductor and reduce localized levels due to oxygen defects. During the second heat treatment, the inert gas may be replaced with a gas containing oxygen. Following the heat treatment, the temperature is lowered in an oxygen atmosphere or in an atmosphere from which hydrogen and water have been sufficiently removed. By going through this process, oxygen can be supplied to the oxide semiconductor.

[0141] The deterioration of the properties of oxide semiconductors is due to the shallow level of 0.1 to 0.2 eV below the conduction band caused by excess hydrogen. These defects are thought to be due to deep levels caused by oxygen vacancies. Therefore, the technical idea of ​​thoroughly removing hydrogen and providing a sufficient amount of oxygen is correct. Wax.

[0142] In the disclosed invention, the oxide semiconductor is highly purified, so that the carrier density in the oxide semiconductor is small enough.

[0143] Furthermore, when the Fermi-Dirac distribution law is used at room temperature, the energy gap is 3.0 The intrinsic carrier density of oxide semiconductors is 1×10 -7 / cm 3 Next , the intrinsic carrier density is 1.45×10 10 / cm 3 This is much smaller than silicon, stomach.

[0144] Therefore, the number of holes, which are minority carriers, is extremely small, and Gate Field Effect Transistor) in the off state The leakage current is 100 aA / μm or less at room temperature, preferably 10 aA / μm or less, and Preferably, 1 aA / μm or less can be achieved. This notation is 1aA (1×10 -18 A) current is Indicates flow.

[0145] However, SiC (3. 26 eV) and GaN (3.42 eV) are known, and similar transistor characteristics can be obtained. However, these semiconductor materials require processing temperatures of 1500°C or higher. Thinning is virtually impossible because the process goes through a thin film. However, it is impossible to stack oxide semiconductors because the process temperature is too high. The conductor can be formed into a thin film by thermal sputtering at room temperature to 400℃. (removal of hydrogen and water from the oxide semiconductor layer) and oxidation (supply of oxygen to the oxide semiconductor layer) Since this can be achieved at 450 to 700°C, it is possible to A three-dimensional laminated structure can be formed.

[0146] Note that an oxide semiconductor is generally an n-type semiconductor. By removing impurities such as i and supplying oxygen, which is a constituent element of oxide semiconductors, In this respect, unlike silicon, which is made i-type by adding impurities, It can be said to contain technological ideas never seen before.

[0147] Note that in this embodiment, the transistor 162 including an oxide semiconductor is a bottom-gate transistor. Although a specific configuration has been described, the present invention is not limited thereto. The structure of 62 may be a top gate type or a dual gate type. A gate-type transistor is a transistor that has two gate insulating layers arranged above and below the channel region. A gate electrode layer is a type of transistor.

[0148] <Conduction mechanism of transistors using oxide semiconductors> Here, the conduction mechanism of a transistor using an oxide semiconductor will be described with reference to FIGS. Please note that the following explanation is merely a consideration, and the validity of the invention cannot be denied based on this explanation. It should be noted that this is not a

[0149] FIG. 6 shows a dual-gate transistor (thin film transistor) using an oxide semiconductor. A cross-sectional view. An oxide semiconductor layer ( A source electrode (S) and a drain electrode (D) are provided thereon, and An insulating layer is provided to cover the source electrode (S) and the drain electrode (D).

[0150] FIG. 7 shows an energy band diagram (schematic diagram) in the A-A' cross section of FIG. In 7, the black circles (●) represent electrons, and the white circles (○) represent holes, each of which has a charge (-q, +q )

[0151] A positive voltage (V D >0) is applied to the gate electrode. If not (V G =0), the solid line indicates a positive voltage (V G >0) is applied. When no voltage is applied to the gate electrode, the oxide semiconductor is not directly connected to the electrode due to the high potential barrier. This indicates the off state in which no carriers (electrons) are injected into the conductor and no current flows. When a positive voltage is applied to the MOSFET, the potential barrier decreases, indicating an on-state in which current flows.

[0152] FIG. 8 shows an energy band diagram (schematic diagram) in the cross section taken along line BB' in FIG. FIG. 8(A) shows a case where a positive voltage (V G >0) is a given state, This shows the on-state where carriers (electrons) flow between the source and drain electrodes. FIG. 8B shows a case where a negative voltage (V G <0) is applied. 4 shows the case where the transistor is in the off state (a state in which minority carriers do not flow).

[0153] Figure 9 shows the relationship between the vacuum level and the work function (φ M ) and the electron affinity (χ) of the oxide semiconductor. show.

[0154] At room temperature, electrons in metals are degenerate, and the Fermi level is located within the conduction band. Conventional oxide semiconductors are n-type, and their Fermi level (E F ) is in the center of the band gap The intrinsic Fermi level (E i ) and is located closer to the conduction band. It is known that some hydrogen atoms act as donors in semiconductors, which is one of the factors that causes them to become n-type. There are.

[0155] In contrast, an oxide semiconductor according to one embodiment of the disclosed invention can convert hydrogen, which is a factor in making the oxide semiconductor n-type, into an oxide. The oxide semiconductor is made of a material that is free from elements (impurity elements) other than the main components of the oxide semiconductor. By purifying it to such a high level that it becomes true (type I) or as close to true as possible In other words, instead of adding impurity elements to make it i-type, impurities such as hydrogen and water are extremely By removing the force, it is possible to obtain a highly purified i-type (intrinsic semiconductor) or something close to it. This is the characteristic of the Fermi level (E f ) is the intrinsic Fermi level (E i ) It can be a degree.

[0156] The band gap of oxide semiconductors (E g ) is 3.15 eV, the electron affinity (χ) is It is said that the work of titanium (Ti) that constitutes the source electrode and drain electrode is 4.3 eV. The function is approximately equal to the electron affinity (χ) of the oxide semiconductor. In this case, the metal-oxide semiconductor At the interface, no Schottky-type barrier is formed for electrons.

[0157] At this time, the electrons pass through the gate insulating layer and the highly purified oxide semiconductor as shown in FIG. The electrons move near the interface with the oxide semiconductor (the energetically most stable part of the oxide semiconductor).

[0158] Also, as shown in FIG. 8B, when a negative potential is applied to the gate electrode (GE1), Since the number of holes, which are carriers, is substantially zero, the current is very close to zero.

[0159] In this way, high purity oxide semiconductors are used to minimize the inclusion of elements (impurity elements) other than the main components of the oxide semiconductor. By this, the gate insulating layer becomes intrinsic (i-type) or substantially intrinsic. Therefore, the gate insulating layer is required to have a good interface with the oxide semiconductor. Specifically, for example, the power supply frequency of the VHF band to the microwave band is required. Insulating layers are produced by the CVD method using high-density plasma generated by a large number of processes, and by sputtering. It is preferable to use an insulating layer produced by a method such as the above.

[0160] The oxide semiconductor is highly purified while the interface between the oxide semiconductor and the gate insulating layer is improved. For example, the channel width (W) of a transistor is 1×10 4 μm, channel length When (L) is 3 μm, 10 -13A off-state current, sub-0.1V / dec. A threshold swing value (S value) (gate insulating layer thickness: 100 nm) can be achieved.

[0161] In this way, the oxide semiconductor is highly oxidized so that elements other than the main components (impurity elements) are not included as much as possible. Purification can improve the operation of the transistor.

[0162] <Carrier concentration> The technical idea of ​​the disclosed invention is to sufficiently reduce the carrier concentration in the oxide semiconductor layer. The aim is to get as close to the intrinsic (i-type) as possible. , and the actually measured carrier concentration will be described with reference to FIG. 10 and FIG. 11. .

[0163] First, we will briefly explain how to calculate the carrier concentration. The CV characteristics of the MOS capacitor are evaluated by fabricating a MOS capacitor. It is possible.

[0164] More specifically, the relationship between the gate voltage Vg and the capacitance C of a MOS capacitor is plotted as C -V characteristics are obtained, and the gate voltage Vg and (1 / C) are calculated from the CV characteristics. 2 A graph showing the relationship between Obtain a rough graph and calculate (1 / C) in the weak inversion region. 2 Calculate the differential value of By substituting the value of the carrier concentration N d The magnitude of is calculated. In (1), e is the elementary charge, ε0 is the dielectric constant of a vacuum, and ε is the relative dielectric constant of an oxide semiconductor. do.

[0165]

number

[0166] Next, the carrier concentration actually measured using the above method is explained. A titanium film was formed on the glass substrate to a thickness of 300 nm, and a titanium nitride film was then formed on the titanium film to a thickness of 100 nm. The titanium nitride film is formed to a thickness of 100 nm, and an In-Ga-Zn-O oxide semiconductor is used on the titanium nitride film. A 2 μm thick oxide semiconductor layer was formed, and a 300 nm thick silver film was formed on the oxide semiconductor layer. The oxide semiconductor layer was formed using In, Ga, and Zn-containing oxide semiconductor film deposition target (In2O3:Ga2O3:ZnO=1 The oxide semiconductor was formed by sputtering using a SiO2 / SiO2 / SiO2 (molar ratio: 1:1). The atmosphere in which the layer was formed was a mixture of argon and oxygen (flow ratio: Ar:O2 = 30 (sc The temperature was set to 15 (sccm).

[0167] Figure 10 shows the CV characteristics, and Figure 11 shows the relationship between Vg and (1 / C). 2 The relationship between and is shown in Fig. (1 / C) in the weak inversion region of 11 2 The carrier obtained from the differential value of The concentration is 6.0 x 10 10 / cm 3 It was.

[0168] In this way, an oxide semiconductor that has been made i-type or substantially i-type (for example, an oxide semiconductor having a carrier concentration of 1×10 12 / cm 3 Below 1×10 11 / cm 3 By using the following It is possible to obtain a transistor with extremely excellent off-state current characteristics.

[0169] <Modification> 12 to 15 show modified examples of the configuration of the semiconductor device. In this case, the configuration of the transistor 162 is different from that described above. The configuration of register 160 is the same as above.

[0170] In FIG. 12, a gate electrode 136d is provided under an oxide semiconductor layer 140, and a source electrode or The drain electrode 142a and the source or drain electrode 142b are formed on the oxide semiconductor layer 1. The lower surface of the transistor 162 is in contact with the oxide semiconductor layer 140. The following shows an example of a semiconductor device. The planar structure can be changed appropriately according to the cross section. Here, only the cross section is shown.

[0171] The major difference between the configuration shown in FIG. 12 and the configuration shown in FIG. 2 is that the source electrode or drain electrode The electrode 142a and the source or drain electrode 142b are connected to the oxide semiconductor layer 140. In other words, in the configuration shown in FIG. 2, the upper surface of the oxide semiconductor layer 140 is The source electrode or drain electrode 142a and the source electrode or drain electrode 142b are in contact with each other. 12, the lower surface of the oxide semiconductor layer 140 is in contact with the source electrode. Alternatively, the gate electrode 142a is in contact with the drain electrode 142a, or the source or drain electrode 142b. Due to this difference in contact, the arrangement of other electrodes, insulating layers, etc. is different. The details of each component are the same as those in Figure 2.

[0172] Specifically, the semiconductor device includes a gate electrode 136d provided on an interlayer insulating layer 128; A gate insulating layer 138 is provided on the gate electrode 136d. The source or drain electrode 142a and the source or drain electrode 142b are and the source or drain electrode 142a, the source or drain electrode 142b and an oxide semiconductor layer 140 in contact with the upper surface.

[0173] Here, the gate electrode 136d is embedded in the insulating layer 132 formed on the interlayer insulating layer 128. Similarly to the gate electrode 136d, the source electrode An electrode 136a is in contact with the drain electrode 130a, and a source or drain electrode 130b is in contact with the drain electrode 130b. An electrode 136b is formed in contact with the electrode 130c, and an electrode 136c is formed in contact with the electrode 130c. do.

[0174] In addition, a protective layer is provided on the transistor 162 so as to be in contact with part of the oxide semiconductor layer 140. An insulating layer 144 is provided, and an interlayer insulating layer 146 is provided on the protective insulating layer 144. Here, the protective insulating layer 144 and the interlayer insulating layer 146 are provided with a source electrode or a drain electrode. The openings reach the source electrode 142a and the source or drain electrode 142b. Through the opening, the electrode 150d and the electrode 150e are connected to the source electrode or the drain electrode. The electrode 142a is formed in contact with the source electrode or the drain electrode 142b. As well as the electrode 150d and the electrode 150e, the gate insulating layer 138, the protective insulating layer 144, the interlayer insulating The layer 146 is provided with openings through which the electrodes 136a, 136b, and 136c are in contact. Electrodes 150a, 150b, and 150c are formed.

[0175] An insulating layer 152 is provided on the interlayer insulating layer 146, and a buried insulating film is formed in the insulating layer 152. Electrodes 154a, 154b, 154c, and 154d are provided so that the electrodes 154a, 154b, 154c, and 154d are inserted into the Here, electrode 154a is in contact with electrode 150a, and electrode 154b is in contact with electrode 150. b, electrode 154c is in contact with electrode 150c and electrode 150d, and electrode 1 54d is in contact with electrode 150e.

[0176] FIG. 13 shows an example of a configuration in which a gate electrode 136d is provided on an oxide semiconductor layer 140. FIG. 13A shows a source or drain electrode 142a and The drain electrode 142b is disposed on the lower surface of the oxide semiconductor layer 140. FIG. 13B shows a structure in which the source electrode or drain electrode 142a and The source electrode or drain electrode 142b is formed on the upper surface of the oxide semiconductor layer 140. 10 is a configuration example in which the second insulating layer 110 contacts the nitride semiconductor layer 140.

[0177] 13. The major difference between the configurations shown in FIG. 2 and FIG. 12 and the configuration shown in FIG. 13 is that the oxide semiconductor layer 140 13(A) and 13(B). The major difference between the configurations shown in FIG. 1 and FIG. 2 is the source electrode or drain electrode 142a and the source electrode Alternatively, the drain electrode 142b is disposed on either the lower surface or the upper surface of the oxide semiconductor layer 140. And due to these differences, other electric The arrangement of the electrodes, insulating layers, etc. is different. The details of each component are the same as in Figure 2. It is.

[0178] Specifically, in FIG. 13A, the semiconductor device has a source A source or drain electrode 142a, a source or drain electrode 142b, and a source electrode The upper surfaces of the source or drain electrodes 142a and 142b are connected to the and a gate insulating layer 138 provided on the oxide semiconductor layer 140. and a gate electrode 136d in a region overlapping the oxide semiconductor layer 140 on the gate insulating layer 138. And, it has.

[0179] In addition, in FIG. 13B, the oxide semiconductor layer 140 and the oxide semiconductor layer 140 are provided over the interlayer insulating layer 128. A source electrode or a drain electrode provided in contact with the upper surface of the nitride semiconductor layer 140. 142a, a source electrode or drain electrode 142b, an oxide semiconductor layer 140, a source electrode A source electrode or drain electrode 142a and a source electrode or drain electrode 142b are provided on the The gate insulating layer 138 overlaps with the oxide semiconductor layer 140 on the gate insulating layer 138. and a gate electrode 136d in a region that is adjacent to the gate electrode 136a.

[0180] In addition, in the configuration shown in FIG. 13, compared with the configuration shown in FIG. 2, some components can be omitted. In this case, the manufacturing process can be simplified. Of course, this is not essential in the configuration shown in FIG. It goes without saying that some components may be omitted.

[0181] FIG. 14 shows a case where the size of the element is relatively large, in which a gate electrode is provided under the oxide semiconductor layer 140. In this case, the flatness of the surface and the coverage are not important. Since the requirements are relatively low, wiring and electrodes need to be embedded in the insulating layer. For example, by performing patterning after forming a conductive layer, the gate electrode 136d, etc. Although not shown here, the transistor 160 can be formed as follows. However, it is possible to fabricate the same.

[0182] The major difference between the configuration shown in FIG. 14(A) and the configuration shown in FIG. 14(B) is that the source electrode The drain electrode 142a and the source or drain electrode 142b are formed on the oxide semiconductor layer 1. 40 on the lower or upper surface of the Due to these differences, the arrangement of other electrodes, insulating layers, etc. also differs. The details of each component are the same as those in FIG. 2 and the like.

[0183] Specifically, in FIG. 14A, the semiconductor device includes a gate insulating film 128 and a gate An electrode 136d, a gate insulating layer 138 provided on the gate electrode 136d, and a gate insulating A source or drain electrode 142a, a source or drain electrode, A drain electrode 142b, a source electrode or drain electrode 142a, and an oxide semiconductor layer 140 in contact with the upper surface of the inner electrode 142b.

[0184] In FIG. 14B, a gate electrode 136d provided on the interlayer insulating layer 128 and a gate A gate insulating layer 138 is provided on the gate electrode 136d. The oxide semiconductor layer 140 is provided in a region overlapping the electrode 136d. A source electrode or drain electrode 142a is provided in contact with the upper surface of the and a source or drain electrode 142b.

[0185] In addition, in the configuration shown in FIG. 14, compared to the configuration shown in FIG. 2, some components are omitted. In this case as well, the effect of simplifying the manufacturing process can be obtained.

[0186] FIG. 15 shows a case where the size of the element is relatively large, in which a gate electrode is formed on the oxide semiconductor layer 140. In this case, the flatness of the surface and the coverage are not important. Since the requirements for this are relatively not strict, wiring and electrodes are formed by embedding them in the insulating layer. For example, the gate electrode 136d can be formed by patterning the conductive layer after it is formed. Although not shown here, the transistor 160 may be formed with a It is possible to fabricate the same.

[0187] The major difference between the configuration shown in FIG. 15(A) and the configuration shown in FIG. 15(B) is that the source electrode The drain electrode 142a and the source or drain electrode 142b are formed on the oxide semiconductor layer 1. 40 on the lower or upper surface of the Due to these differences, the arrangement of other electrodes, insulating layers, etc. also differs. The details of each component are the same as those in FIG. 2 and the like.

[0188] Specifically, in FIG. 15A, the semiconductor device has a source A source or drain electrode 142a, a source or drain electrode 142b, and a source electrode The upper surfaces of the source or drain electrodes 142a and 142b are connected to the The oxide semiconductor layer 140 and the source or drain electrode 142a and a drain electrode 142b, a gate insulating layer 138 provided on the oxide semiconductor layer 140, A gate electrode 1 is provided in a region on the gate insulating layer 138 that overlaps with the oxide semiconductor layer 140. 36d and.

[0189] In addition, in the semiconductor device shown in FIG. 15B, an oxide semiconductor A source electrode or a gate electrode provided in contact with the upper surface of the oxide semiconductor layer 140. The drain electrode 142a, the source electrode or drain electrode 142b, and the source electrode or A drain electrode 142a, a source or drain electrode 142b, and an oxide semiconductor layer 140 A gate insulating layer 138 is provided on the gate insulating layer 138, and an oxide semiconductor layer 140 is provided on the gate insulating layer 138. and a gate electrode 136d provided in the overlapping region.

[0190] In addition, in the configuration shown in FIG. 15, compared to the configuration shown in FIG. 2, some components can be omitted. In this case as well, the effect of simplifying the manufacturing process can be obtained.

[0191] As described above, a semiconductor device having a novel structure can be realized according to one embodiment of the disclosed invention. In this embodiment, the transistor 160 and the transistor 162 are stacked. Although the above example has been described, the configuration of the semiconductor device is not limited to this example. In this embodiment, the channel lengths of the transistors 160 and 162 are perpendicular to each other. The positional relationship between the transistor 160 and the transistor 162 may be changed as described above. Furthermore, the transistor 160 and the transistor 162 may be overlapped. It may be provided.

[0192] For ease of understanding, the present embodiment will be described with reference to a semiconductor device having a minimum storage unit (1 bit). However, the configuration of the semiconductor device is not limited to this. By appropriately connecting the components, it is possible to configure a more advanced semiconductor device. By using multiple devices, it is possible to configure a NAND type or NOR type semiconductor device. The configuration is not limited to that shown in FIG. 1 and can be modified as appropriate.

[0193] The semiconductor device according to this embodiment has a very low off-state current characteristic of the transistor 162. It is possible to retain information for a long period of time. In other words, it is possible to achieve the same performance as DRAM. No refresh operation is required, and power consumption can be reduced. It is possible to use the semiconductor device as a photo-emissive semiconductor device.

[0194] In addition, in order to write information by switching the transistor 162, It does not require high voltage and does not have the problem of element degradation. Furthermore, the transistor can be turned on or off. Since information is written and erased by the flash memory, high speed operation can be easily realized. In addition, there is no need to erase the information required in a flash memory or the like. There is also another advantage.

[0195] In addition, transistors using materials other than oxide semiconductors can operate at sufficiently high speed. By using this, it is possible to read out the stored contents at high speed.

[0196] The structures, methods, and the like described in this embodiment mode may be appropriately combined with the structures, methods, and the like described in other embodiments. They can be used in combination.

[0197] (Embodiment 2) In this embodiment, a circuit configuration and operation of a semiconductor device according to one embodiment of the present invention will be described. do.

[0198] FIG. 16 shows an example of a circuit diagram of a memory element (hereinafter also referred to as a memory cell) included in a semiconductor device. The memory cell 200 shown in FIG. 16 is a multi-value type, and includes a source line SL, a bit line BL, and , a first signal line S1, a second signal line S2, a word line WL, a transistor 201, The transistor 202, the transistor 203, and the capacitance element 205. The transistor 201 and the transistor 203 are formed using a material other than an oxide semiconductor. The transistor 202 is formed using an oxide semiconductor.

[0199] Here, the gate electrode of the transistor 201 and the source electrode or drain of the transistor 202 are The source line SL is electrically connected to one of the drain electrodes of the transistor. The source electrode of the transistor 201 is electrically connected to the drain electrode of the transistor 201. The source electrode of the transistor 203 is electrically connected to the bit line BL. The drain electrode of the transistor 203 is electrically connected to the first signal line S1. The other of the source electrode and the drain electrode of the transistor 202 is electrically connected to the second signal. The signal line S2 and the gate electrode of the transistor 202 are electrically connected to the word line WL. The gate electrode of the transistor 203 is electrically connected to the capacitor 205. one electrode of the transistor 201 and the other electrode of the transistor 202 The other electrode of the capacitor 205 is electrically connected to A predetermined potential is applied to the terminal, such as GND.

[0200] Next, the operation of the memory cell 200 shown in FIG. 16 will be described. The four states of the memory cell 200 are data "00b", "01b", "10b", and "11b". " and the potentials of node A at that time are V00, V01, V10, and V11 (V00 <V01<V10<V11)とする。

[0201] When writing to the memory cell 200, the source line SL is set to 0 [V] and the word line WL is set to 0 [V]. V], the bit line BL is 0 [V], and the second signal line S2 is 2 [V]. When writing, the first signal line S1 is set to V00 [V]. Write the data "01b". In this case, the first signal line S1 is set to V01 [V]. When writing data "11b", the first signal line S1 is set to V10 [V]. The line S1 is set to V11 [V]. At this time, the transistor 203 is in the off state, When the write operation is completed, the potential of the first signal line S1 becomes Before the change, the second signal line S2 is set to 0 [V] to turn off the transistor 202. .

[0202] As a result, after writing data "00b", "01b", "10b" and "11b", The potential of a node (hereinafter, node A) connected to the gate electrode of the transistor 201 is , approximately V00 [V], approximately V01 [V], approximately V10 [V], approximately V11 [V]. Node A A charge corresponding to the potential of the first signal line S1 is stored in the transistor 202. Since the current is very small or essentially zero, the gate electrode of the transistor 201 The potential is maintained for an extended period of time.

[0203] When reading the memory cell 200, first, the bit line BL is precharged to Vp c [V]. Then, the source line SL is set to Vs_read [V], and the word line WL is set to 2 [V], the second signal line S2 is set to 0 [V], and the first signal line S1 is set to 0 [V]. The transistor 203 is turned on, and the transistor 202 is turned off. c is set lower than V00-Vth. Vs_read is set higher than V11-Vth.

[0204] As a result, a current flows from the source line SL to the bit line BL, and the bit line BL (the voltage at node A) The potential is charged to a potential represented by Vth minus (the threshold voltage Vth of the transistor 201). As a result, the bit line BL potential is data "00b", "01b", "10b", and "11b". V00-Vth, V01-Vth, V10-Vth, V11-Vth, respectively. The read circuit connected to the bit line BL reads the data “0 The following can be read: 0b", 01b", 10b", and 11b.

[0205] FIG. 17 shows a block diagram of a semiconductor device according to one embodiment of the present invention having a storage capacity of m×n bits. The circuit diagram is shown.

[0206] A semiconductor device according to one aspect of the present invention includes m word lines WL and second signal lines S2, and n A bit line BL, a first signal line S1, a source line SL, and a plurality of memory cells 200(1,1) ~200(m, n) in a matrix of m vertical (rows) x n horizontal (columns) (m, n are natural numbers) The memory cell array 210, the read circuit 211, and the first signal line driving circuit 21 2, a driving circuit 213 for the second signal line and the word line, and a peripheral circuit such as a potential generating circuit 214. As other peripheral circuits, a refresh circuit, etc. may be provided. stomach.

[0207] Consider each memory cell, e.g., memory cell 200(i,j), where i is between 1 and m, inclusive. where j is an integer between 1 and n). The memory cell 200(i,j) is connected to the bit line BL(j ), a first signal line S1(j), a source line SL(j), a word line WL(i) and a second signal line S 2(i). Also, the bit lines BL(1) to BL(n) and the source The lines SL(1) to SL(n) are connected to the read circuit 211 through the first signal lines S1(1) to S1(n ) is connected to the first signal line driving circuit 212, the word lines WL(1) to WL(m) and the second signal line S2 (1) to S2(m) are connected to the second signal line and word line driving circuit 213, respectively. do.

[0208] FIG. 18 shows an example of the driver circuit 213 for the second signal lines and the word lines. The driver circuit 213 of the second signal line includes a decoder 215. The decoder 215 is 2 and the word line WL via a switch. The word line WL is connected to GND (ground potential) via a switch. The switch is enabled by the read enable signal (RE signal) or the write enable signal (WE signal). The decoder 215 receives an address signal ADR from the outside.

[0209] When an address signal ADR is input to the driver circuit 213 for the second signal line and the word line, The row specified by the request (hereafter referred to as the selected row) is asserted (enabled), and the other rows (hereafter referred to as the The word lines WL and RE When the signal is asserted, it is connected to the output of the decoder 215 and the RE signal is deasserted. When the WE signal is asserted, the second signal line S2 is connected to the decoder 215. When the WE signal is deasserted, it is connected to the output of the

[0210] FIG. 19 shows an example of the first signal line driver circuit 212. The first signal line driver circuit 212 is a multi-channel type. The multiplexer (MUX1) has input data DI and and write potentials V00, V01, V10, and V11 are input to the multiplexer (MUX The output terminal of 1) is connected to the first signal line S1 via a switch. The line S1 is connected to GND via a switch. The switch is a light enable switch. It is controlled by the WE signal.

[0211] When DI is input to the first signal line driving circuit 212, the multiplexer (MUX1) outputs DI Depending on the value of V, the write potential Vw is selected from V00, V01, V10, and V11. The behavior of the multiplexer (MUX1) is shown in Table 1. When the WE signal is asserted, The selected write potential Vw is applied to the first signal line S1, and the WE signal is deasserted. Then, 0 [V] is applied to the first signal line S1 (the first signal line S1 is connected to GND). ).

[0212] [Table 1]

[0213] FIG. 20 shows an example of the read circuit 211. The read circuit 211 includes a plurality of sense amplifiers. One input terminal of each sense amplifier circuit is a switch circuit. A bit line BL is connected through the switch, or Vpc is applied. One of the reference potentials Vref0, Vref1, or Vref2 is input to the input terminal of the other party. The output terminals of the sense amplifier circuits are connected to the input terminals of the logic circuit 229. Note that the switch is controlled by a read enable signal (RE signal).

[0214] By setting the values of the reference potentials Vref0, Vref1, and Vref2 to satisfy V00 - Vth < Vref0 < V01 - Vth < Vref1 < V10 - Vth < Vref2 < V11 - Vth, the state of the memory cell can be read out as a 3-bit digital signal. For example, in the case of the data "00b", the potential of the bit line BL is V00 - Vth. Since this value is smaller than any of the reference potentials Vref0, Vref1, and Vref2, the outputs SA_OUT0, SA_OUT1, and SA_OUT2 of the sense amplifier circuit are all "0", "0", "0". Similarly, in the case of the data "01b", the potential of the bit line BL is V01 - Vth, and the outputs SA_OUT0, SA_OUT1, and SA_OUT2 of the sense amplifier circuit are "1", "0", "0" respectively. In the case of the data "10b", the potential of the bit line BL is V10 - Vth, and the outputs SA_OUT0, SA_OUT1, and SA_OUT2 of the sense amplifier circuit are "1", "1", "0" respectively. In the case of the data "11b", the potential of the bit line BL is V11 - Vth, and the outputs SA_OUT0, SA_OUT1, and SA_OUT2 of the sense amplifier circuit are "1", "1", "1" respectively. After that, 2-bit data DO is generated using the logic circuit 229 represented by the logic value table shown in Table 2 and output from the read circuit 211.

[0215] ​​​​​​​​ [Table 2]

[0216] In the illustrated read circuit 211, when the RE signal is deasserted, the source line SL is connected to GND, 0 [V] is applied to the source line SL, and the bit lines BL and A potential Vpc [V] is applied to the terminal of the sense amplifier circuit connected to the bit line BL. When the E signal is asserted, Vs_read [V] is applied to the source line SL. As a result, the bit line BL is charged with a potential that reflects the data. The potential Vpc is set lower than V00-Vth. Vs_read is set to V11- Make it higher than Vth.

[0217] In addition, the potential of the bit line BL to be compared during reading is set via a switch. This includes the potential of the node of the input terminal of the sense amplifier connected to the line BL. The potential compared in the read circuit 211 is strictly the same as the potential of the bit line BL. There doesn't have to be one.

[0218] FIG. 21 shows an example of the potential generating circuit 214. In the potential generating circuit 214, a desired potential is generated as follows: It can be generated by dividing the resistors between Vdd and GND. The generated potential is then The write potentials V00 and V0 1, V10, V11, and reference potentials Vref0, Vref1, Vref2 are generated. In the figure, V00 <Vref0<V01<Vref1<V10<Vref2<V11 However, the relationship between the potentials is not limited to this. By adjusting the voltage, the required potential can be generated appropriately. V10, V11 and Vref0, Vref1, Vref2 are generated using separate voltage generation circuits. It's okay to do so.

[0219] A potential boosted by a booster circuit is supplied to the potential generating circuit 214 instead of the power supply potential Vdd. By supplying the output of the boost circuit to the potential generating circuit, the absolute value of the potential difference can be made large. This is because it becomes possible to supply a higher potential.

[0220] Even when the power supply potential Vdd is directly supplied to the potential generating circuit, it is necessary to divide it into a number of potentials. However, in this case, it becomes difficult to distinguish between adjacent potentials, This will increase the number of write and read errors. By supplying the potential to the potential generating circuit, the absolute value of the potential difference can be made large. Therefore, even if the number of divisions is increased, a sufficient difference between adjacent potentials can be ensured.

[0221] This allows the memory cell to be read without increasing the number of write or read errors. It is possible to increase the capacity.

[0222] FIG. 22A shows a booster circuit 219 as an example of a booster circuit that performs four-stage boosting. In (A), the input terminal of the first diode 402 is supplied with the power supply potential Vdd. The output terminal of the first diode 402 is connected to the input terminal of the second diode 404 and the first capacitor. One terminal of the capacitance element 412 is connected to the output terminal of the second diode 404. The input terminal of the third diode 406 and one terminal of the second capacitor element 414 are connected to the terminal. The following description is the same, so detailed explanation will be omitted. It can also be said that one terminal of the nth capacitance element is connected to the nth capacitance element (n: natural number). The output of the fifth diode 410 becomes the output Vout of the boost circuit 219.

[0223] Furthermore, the other terminal of the first capacitance element 412 and the other terminal of the third capacitance element 416 are A clock signal CLK is input to the other terminal of the second capacitance element 414 and the fourth capacitance element 415. The other terminal of the capacitive element 418 receives the inverted clock signal CLKB. A clock signal CLK is input to the other terminal of the 2k-1-th capacitive element, and the 2k-th capacitive element It can be said that the inverted clock signal CLKB is input to the other terminal of the element (k: natural number). However, the ground potential GND is input to the other terminal of the final-stage capacitive element.

[0224] When the clock signal CLK is High, that is, when the inverted clock signal CLKB is Low, In one case, the first capacitive element 412 and the third capacitive element 416 are charged and the clock The potentials of the nodes N1 and N3 that are capacitively coupled to the signal CLK are reduced by a predetermined voltage. On the other hand, the nodes N2 and N3, which are capacitively coupled with the inverted clock signal CLKB, The potential of N4 is pulled down by a predetermined voltage.

[0225] As a result, the first diode 402, the third diode 406, and the fifth diode 41 0, charges move through the node N2 and the node N4, and the potentials of the nodes N2 and N4 are raised to a predetermined value. can be done.

[0226] Next, when the clock signal CLK goes low and the inverted clock signal CLKB goes high, Therefore, the potentials of the nodes N2 and N4 are further increased. The potentials of node N3 and node N5 are lowered by a predetermined voltage.

[0227] This causes charge to move through the second diode 404 and the fourth diode 408, As a result, the potentials of the nodes N3 and N5 are raised to a predetermined potential. In this way, the potential at each node is V N5 >V N4(CLKB=High) >V N3(CLK=High) >V N2(CLKB=High) >V N1(CLK=Hi gh) The boost circuit 219 is configured as follows: The present invention is not limited to a multi-stage boosting method, and the number of boosting stages can be changed as appropriate.

[0228] The output Vout of the boost circuit 219 is greatly affected by the variation in diode characteristics. For example, a diode is created by connecting the source electrode and gate electrode of a transistor. However, in this case, it will be affected by the variation in the threshold voltage of the transistor. .

[0229] In order to control the output Vout with high accuracy, a configuration that feeds back the output Vout is adopted. FIG. 22(B) shows a circuit configuration in which the output Vout is fed back. An example is shown in FIG. 22B. The boost circuit 219 in FIG. 22A is the same as the boost circuit 219 in FIG. It is equivalent.

[0230] The output terminal of the boost circuit 219 is connected to one input terminal of the sense amplifier circuit via a resistor R1. One of the input terminals of the sense amplifier circuit is connected to ground via resistor R2. It is. That is, the potential V1 corresponding to the output Vout is input to one input terminal of the sense amplifier circuit. Here, V1 = Vout·R2 / (R1 + R2). It is.

[0231] Also, the reference potential Vref is input to the other input terminal of the sense amplifier circuit. That is, in the sense amplifier circuit, V1 and Vref are compared. The output terminal of the sense amplifier circuit is connected to the control circuit. Also, the clock signal CLK0 is input to the control circuit. The control circuit outputs the clock signal CLK and the inverted clock signal CLKB to the boost circuit 219 according to the output from the sense amplifier circuit.

[0232] When V1 > Vref, the output sig_1 of the sense amplifier circuit is asserted, and the control circuit stops supplying the clock signal CLK and the inverted clock signal CLKB to the boost circuit 219. As a result, the boost operation stops, so the rise of the potential Vout stops. And the circuit connected to the output of the boost circuit 219 consumes power, so the potential Vout gradually decreases.

[0233] When V1 < Vref, the output sig_1 of the sense amplifier circuit is de-asserted, and the control circuit starts supplying the clock signal CLK and the inverted clock signal CLKB to the boost circuit 219. As a result, the boost operation is performed, so the potential Vout gradually rises.

[0234] In this way, by feeding back the output potential Vout of the boost circuit 219, it is possible to keep the output potential Vout of the boost circuit 219 at a constant value. This configuration is a diode ​​​​​​​​​​It is particularly effective when there are variations. Also, it is effective when generating a predetermined potential based on the reference potential Vref. In the boost circuit 219, it is also possible to generate a plurality of potentials by using a plurality of different reference potentials. By supplying the output of the boost circuit to the potential generation circuit, the absolute value of the potential difference can be increased. Therefore, it is possible to generate a higher potential without changing the minimum unit of the potential difference. That is, it is possible to increase the storage capacity of one memory cell.

[0235]

[0236] Fig. 23 shows a differential sense amplifier as an example of a sense amplifier circuit. The differential sense amplifier has input terminals Vin(+) and Vin(-) and an output terminal Vout, and amplifies the difference between Vin(+) and Vin(-). If Vin(+) > Vin(-), Vout is generally High output, and if Vin(+) < Vin(-), Vout is generally Low output.

[0237] Fig. 24 shows a latch-type sense amplifier as an example of a sense amplifier circuit. The latch-type sense amplifier has input / output terminals V1 and V2 and input terminals for control signals Sp and Sn. First, the signal Sp is set to High, the signal Sn is set to Low, and the power supply is cut off. Then, the potentials for comparison are applied to V1 and V2. After that, when the signal Sp is set to Low, the signal Sn is set to High, and the power supply is supplied, if the potential before power supply is V1 > V2, V1 is High output, V2 is Low output, and if V1 < V2, V1 is Low output, V2 is High output. In this way, the difference between V1 and V2 is amplified.

[0238] An example of a timing chart for a write operation is shown in FIG. This is a timing chart for writing data "10b" to a cell. The voltage of the first signal line S1 during the writing period is 0 [V]. The voltage level is V10. The word line WL, bit line BL, and source line SL are at 0 [V]. An example of a timing chart for a read operation is shown in FIG. 13 is a timing chart for reading data "10b" from a selected memory cell. When the word line WL is asserted and the source line SL becomes Vs_read [V], The BL line is charged to V10-Vth [V], corresponding to the memory cell data "10b". As a result, SA_OUT0, SA_OUT1, and SA_OUT2 are all set to "1". The first signal line S1 and the second signal line S2 are set to 0 [V].

[0239] Here, a specific example of the operating potential (voltage) is shown. For example, the threshold voltage of the transistor 201 is The value voltage is about 0.3V, the power supply potential is VDD=2V, V11=1.6V, V10=1.2 V, V01=0.8V, V00=0V, and Vref0=0.6V, Vref1=1.0 V, Vref2=1.4V. The potential Vpc can be set to 0V, for example. stomach.

[0240] In this embodiment, the first signal line S1 is arranged in the bit line BL direction (column direction), and the second Although the signal line S2 is arranged in the word line WL direction (row direction), this is not necessarily limited to this. For example, the first signal line S1 is arranged in the word line WL direction (row direction), and the second The second signal line S2 may be arranged in the bit line BL direction (column direction). The drive circuit to which the first signal line S1 is connected and the drive circuit to which the second signal line S2 is connected are appropriately Just place it.

[0241] In this embodiment, the operation of a four-level memory cell, that is, four different values ​​are stored in one memory cell. Although the above describes the case where one of the states is written or read, the circuit configuration can be changed appropriately. By changing the value of the bit, the operation of the n-ary memory cell can be changed to any one of n different states (n is an integer greater than or equal to 2) can be written to and read from.

[0242] For example, an 8-level memory cell has three times the memory capacity compared to a 2-level memory cell. In the write operation, eight write potentials are prepared to determine the potential of node A, generating eight states. For readout, seven reference potentials are prepared that can distinguish eight states. For readout, one sense amplifier is provided and seven comparisons can be performed to read out the data. It is also possible to reduce the number of comparisons to three by feeding back the comparison results. In the read method that drives the source line SL, seven sense amplifiers are provided, It is also possible to read out the data by comparing it once. Also, multiple sense amplifiers can be provided to perform multiple comparisons. It is also possible to configure the device to do this.

[0243] In general, 2 k (k is an integer greater than or equal to 1)-valued memory cells have a higher memory capacity than binary memory cells. The capacity is k times larger. In the write operation, the write potential that determines the potential of node A is doubled. k Type preparation Then, 2 k Generates states. For readout, 2 k Two states that can be distinguished k -It is recommended to prepare one reference potential. k -1 comparison In addition, the comparison result can be fed back to the It is also possible to reduce the number of times to k. 2 amplifiers k -You can set one and read it out with one comparison. Also, multiple sense It is also possible to provide an amplifier and perform multiple comparisons.

[0244] The semiconductor device according to this embodiment has a very low off-state current characteristic of the transistor 202. It is possible to retain information for a long period of time. In other words, it is possible to achieve the same performance as DRAM. No refresh operation is required, and power consumption can be reduced. It can be used as a non-volatile memory device.

[0245] In addition, in order to write information by switching the transistor 202, It does not require high voltage and does not have the problem of element degradation. Furthermore, it is possible to turn the transistor on and off with a This allows information to be written and erased, and therefore high-speed operations can be easily achieved. By controlling the potential input to the transistor, data can be directly rewritten. This eliminates the need for the erase operation required in flash memories and the like. This makes it possible to suppress a decrease in operation speed caused by the above-mentioned operation.

[0246] In addition, transistors using materials other than oxide semiconductors can operate at sufficiently high speed. By using this, it is possible to read out the stored contents at high speed.

[0247] In addition, since the semiconductor device according to the present embodiment is a multi-value type, it is possible to increase the memory capacity per area. This allows the semiconductor device to be miniaturized and highly integrated. In the write operation, the potential of the floating node can be directly controlled. This makes it possible to easily control the threshold voltage of a semiconductor device with high accuracy, which is required for a multi-value memory. This also eliminates the need to check the state after writing, which is required for multi-value memory. This can reduce the time required for writing.

[0248] (Embodiment 3) In this embodiment, a circuit configuration and operation of a semiconductor device according to one embodiment of the present invention will be described. do.

[0249] In this embodiment, the circuit configuration of the memory element shown in FIG. 16 is used to implement a different method from that of the second embodiment. 16 shows a case where a read operation is performed by using the capacitor element 205. The memory element is a multi-value type, and a four-value type will be described. The state of node A is data "00b", "01b", "10b", and "11b". The potential is V00, V01, V10, V11 (V00 <V01<V10<V11)とする。

[0250] When writing to the memory cell 200, the source line SL is set to 0 [V] and the word line WL is set to 0 [V]. V], the bit line BL is 0 [V], and the second signal line S2 is 2 [V]. When writing, the first signal line S1 is set to V00 [V]. Write the data "01b". In this case, the first signal line S1 is set to V01 [V]. When writing data "11b", the first signal line S1 is set to V10 [V]. The line S1 is set to V11 [V]. At this time, the transistor 203 is in the off state, When the write operation is completed, the potential of the first signal line S1 becomes Before the change, the second signal line S2 is set to 0 [V] to turn off the transistor 202. .

[0251] As a result, after writing data "00b", "01b", "10b", and "11b", the traffic The potential of a node (hereinafter, node A) connected to the gate electrode of the transistor 201 is Approximately V00 [V], approximately V01 [V], approximately V10 [V], approximately V11 [V]. At node A A charge corresponding to the potential of the first signal line S1 is stored in the transistor 202. Since the potential of the gate electrode of the transistor 201 is extremely small or substantially zero, The position is held for a long time.

[0252] Next, when reading the memory cell 200, the source line SL is set to 0 [V] and the word line W L is VDD, the second signal line S2 is 0 [V], the first signal line S1 is 0 [V], and the bit line BL The read circuit 211 connected to the transistor 203 is put into an operating state. is turned on and transistor 202 is turned off.

[0253] As a result, depending on the state of the memory cell 200, the source line SL of the memory cell 200 and the corresponding The effective resistance between the bit lines BL is determined by the potential of the node A. The read circuit reads the data from the difference in potential caused by this difference in resistance. The following values ​​can be read: 00b", 01b", 10b", and 11b. It is preferable that the transistor 201 is in an on state except for the state "00b" where the potential of A is the lowest. It is appropriate.

[0254] FIG. 26 shows a block diagram of a semiconductor device according to one embodiment of the present invention having a storage capacity of m×n bits. 13 shows another example of a circuit diagram.

[0255] The semiconductor device shown in FIG. 26 includes m word lines WL and second signal lines S2, and n bit lines BL and a first signal line S1, and a plurality of memory cells 200(1,1) to 200(m,n) are arranged vertically. Memory cells arranged in a matrix of m rows x n columns (m and n are natural numbers). The array 210, the readout circuit 211, the first signal line driver circuit 212, the second signal line and The signal line driver 213 and the voltage generator 214 are also included in the peripheral circuitry. As other peripheral circuits, a refresh circuit and the like may be provided.

[0256] Consider each memory cell, for example memory cell 200(i,j), where i is between 1 and m. The memory cell 200(i, j) is connected to the bit line BL (j), a first signal line S1(j), a word line WL(i) and a second signal line S2(i), The source line potential Vs (for example, 0 [V]) is applied to the source line. Also, the bit lines BL(1) to BL(n) are connected to the read circuit 211 via a first signal The signal lines S1(1) to S1(n) are connected to the first signal line driving circuit 212, and the word lines WL(1) to WL (m) and the second signal lines S2(1) to S2(m) are connected to the second signal line and word line drive circuit 21. are connected to 3 respectively.

[0257] In addition, the potential generating circuit 214, the driver circuit 213 for the second signal line and the word line, the first signal line driver The configuration of the circuit 212 is the same as the configuration of FIG. 21, the configuration of FIG. 18, and the configuration of FIG. It can be said that it is completed.

[0258] FIG. 27 shows an example of the read circuit 221. The read circuit 221 is a sense amplifier circuit. , a reference cell 225, a logic circuit 229, a multiplexer (MUX2), a flip-flop circuit The reference cell 225 includes a transistor FF0, a transistor FF1, a transistor FF2, a bias circuit 223, etc. The reference cell 225 has a transistor 216, a transistor 217, and a transistor 218. The transistors 216, 217, and 218 are the transistors 201 and 202 of the memory cell. 02, 203, and have the same circuit configuration as the memory cell. The transistor 6 and the transistor 218 are formed using a material other than an oxide semiconductor. The resistor 217 is preferably formed using an oxide semiconductor. has a capacitive element 205, the reference cell 225 also preferably has a capacitive element. The two output terminals of the bias circuit 223 are connected to the bit lines BL and The reference cell 225 is connected to the drain electrode of the transistor 218. The output terminal of the sense circuit 223 is connected to the input terminal of the sense amplifier circuit. The output terminals of the path are connected to the flip-flop circuits FF0, FF1, and FF2. The output terminals of the flop circuits FF0, FF1, and FF2 are connected to the input terminals of the logic circuit 229. The multiplexer (MUX2) receives the signals RE0, RE1, RE2, and the reference potential Vr ef0, Vref1, Vref2, and GND are input. The output terminal is connected to the source electrode or drain electrode of the transistor 217 of the reference cell 225. Also, the bit line BL and the transistor of the reference cell 225 are connected to one of the poles. The drain electrode of the transistor 218 is connected to the wiring Vpc via a switch. The switch is controlled by a signal ΦA.

[0259] The read circuit 221 detects the potential output from the memory cell and the potential output from the reference cell 225. This is a configuration in which the conductance of the memory cell and the reference cell 225 are compared by comparing the potentials. This configuration has one sense amplifier circuit and performs three comparisons to read out four states. That is, for three kinds of reference potentials, the memory cell and the reference cell 225 are The conductances are compared. The three comparisons are performed by the signals RE0, RE1, RE2, and ΦA. The multiplexer (MUX2) is controlled according to the values ​​of the signals RE0, RE1, and RE2. Depending on the input voltage, one of three reference potentials Vref0, Vref1, Vref2 or GND can be selected. The behavior of the multiplexer (MUX2) is shown in Table 3. The flip-flop circuits FF0, FF1, and FF2 are driven by the signals RE0, RE1, and RE2, respectively. It is controlled to store the value of the output signal SA_OUT of the sense amplifier.

[0260] [Table 3]

[0261] The reference potential is V00 <Vref0<V01<Vref1<V10<Vref2<V11と By doing this, four states can be read out as a result of three comparisons. In the case of data "00b", the values ​​of FF0, FF1, and FF2 are "0", In the case of "0", "0", and data "01b", the values ​​of FF0, FF1, and FF2 are "1", When the data is 0, 0, or 10b, the values ​​of FF0, FF1, and FF2 are 1, 1 When data is "0", data is "11b", the values ​​of FF0, FF1, and FF2 are "1", "1". In this way, the state of the memory cell is read out as a 3-bit digital signal. Then, the logic circuit 229 represented by the logic value table shown in Table 2 is used to convert the two bits. The data DO of the bit is generated and output from the read circuit.

[0262] In the read circuit shown in FIG. 27, when the signal RE is deasserted, the bit lines BL and The reference cell 225 is connected to the wiring Vpc to perform precharging. The signal RE is asserted. The bit line BL and the bias circuit 223, and the reference cell 225 and the bias circuit 223 are respectively and conducts electricity.

[0263] Note that precharging is not necessary. In this circuit, the two inputs to the sense amplifier circuit are It is preferable to make the configurations of the circuits that generate the signals of the reference cell as similar as possible. It is preferable that the transistors corresponding to the memory cells 225 have the same configuration. It is preferable that the bias circuit 223 and the switch have the same configuration.

[0264] The timing chart for the write operation is the same as that shown in FIG. An example of a transfer chart is shown in FIG. 28. The diagram shows the transfer of data “10b” from a memory cell. This is a timing chart for reading. When the signals RE0, RE1, and RE2 are asserted, During this period, Vref0 is applied to the output MUX2_OUT of the multiplexer (MUX2). , Vref1, and Vref2 are input. In the first half of each period, the signal ΦA is asserted, and the reference A predetermined potential is applied to node B of the transistor of cell 225. In the second half of each period, a signal Φ A is deasserted, and a predetermined potential is held at node B of the transistor of the reference cell 225. At the same time, the drain electrode of the transistor 218 of the reference cell 225 is connected to a bias circuit The comparison result in the sense amplifier circuit is connected to a flip-flop circuit These are stored in FF0, FF1, and FF2, respectively. When the data in the memory cell is "10b" In this case, the values ​​of the flip-flop circuits FF0, FF1, and FF2 are "1", "1", and "0". The first signal line S1 and the second signal line S2 are at 0 [V].

[0265] Next, a read circuit and a read method different from the one shown in FIG. 20 will be described. .

[0266] FIG. 29 shows an example of the read circuit 231. The read circuit 231 is a sense amplifier circuit. , a plurality of reference cells (reference cell 225a, reference cell 225b, reference cell 225c), a logic circuit The circuit 229 includes flip-flop circuits FF0, FF1, and FF2, and a bias circuit 223. do.

[0267] The reference cells are transistors 216, 217, and 218. The transistors 216, 217, and 218 are transistors included in the memory cell 200. The memory cells 201, 202, and 203 have the same circuit configuration as the memory cell 200. The transistor 216 and the transistor 218 are formed using a material other than an oxide semiconductor. The transistor 217 is preferably formed using an oxide semiconductor. In addition, when the memory cell has a capacitance element 205, the reference cell also has a capacitance element. The two output terminals of the bias circuit 223 are preferably connected to the A bit line BL and a drain electrode of a transistor 218 of a plurality of reference cells are connected to the bit line BL. The output terminal of the bias circuit 223 is connected to the input terminal of the sense amplifier circuit. The output terminals of the sense amplifier circuit are connected to the flip-flop circuits FF0, FF1, and FF2. The output terminals of the flip-flop circuits FF0, FF1, and FF2 are connected to the logic circuit 229. The input terminal is connected to the bit line BL and the transistors of the plurality of reference cells. The drain electrode of 218 is connected to the wiring Vpc via a switch. is controlled by a read enable signal (RE signal).

[0268] The read circuit 231 detects the potential output from the memory cell and the potential output from the reference cell 225. This configuration involves comparing the potentials and comparing the conductance of a memory cell with a number of reference cells. This configuration has one sense amplifier circuit and performs three comparisons to read out four states. That is, the conductance of the memory cell is compared with that of the three reference cells. The three comparisons are controlled by signals RE0, RE1, and RE2. The three reference cells are The gate electrode of the transistor 216 is connected to Vref0 and Vref1 through the transistor 217. , Vref2 are input to the input terminals. Before reading, the signal ΦA is asserted. All the transistors 217 are turned on and writing is performed on the reference cell. Writing to a cell only needs to be done once before the read operation. Of course, it can be done several times after reading. It may be done once or every time. Also, the flip-flop circuits FF0, FF1, and F F2 is controlled by the signals RE0, RE1, and RE2, respectively, and the output of the sense amplifier The value of the signal SA_OUT is stored.

[0269] The reference potential is V00 <Vref0<V01<Vref1<V10<Vref2<V11と By doing this, four states can be read out as a result of three comparisons. In the case of data "00b", the values ​​of FF0, FF1, and FF2 are "0", In the case of "0", "0", and data "01b", the values ​​of FF0, FF1, and FF2 are "1", When the data is 0, 0, or 10b, the values ​​of FF0, FF1, and FF2 are 1, 1 When data is "0", data is "11b", the values ​​of FF0, FF1, and FF2 are "1", "1". In this way, the state of the memory cell is read out as a 3-bit digital signal. Then, the logic circuit 229 represented by the logic value table shown in Table 2 is used to convert the two bits. The data DO of the bit is generated and output from the read circuit.

[0270] In the read circuit shown in FIG. 29, when the RE signal is deasserted, the bit line BL The RE signal is asserted and the bit The bit line BL and the bias circuit 223, and the reference cell and the bias circuit 223 are electrically connected to each other.

[0271] Note that precharging is not necessary. In this circuit, the two inputs to the sense amplifier circuit are It is preferable to make the configurations of the circuits that generate the signals of the reference cell as similar as possible. It is preferable that the corresponding transistors in the memory cell and the corresponding vias have the same configuration. It is preferable that the switch and the switch circuit 223 have the same configuration.

[0272] The timing chart for the write operation is the same as that shown in FIG. An example of a transfer chart is shown in FIG. 30. The diagram shows the transfer of data “10b” from a memory cell. This is a timing chart for reading. RE0, RE1, and RE2 are asserted. Between them, the reference cell 225a, the reference cell 225b, and the reference cell 225c are selected, respectively. The bias circuit 223 is connected to the sense amplifier circuit 224. The comparison result in the sense amplifier circuit 224 is The data in the memory cell is stored in the flop circuits FF0, FF1, and FF2. In the case of "0b", the values ​​of the flip-flop circuits FF0, FF1, and FF2 are "1", "1" , "0." Note that the first signal line S1 and the second signal line S2 are at 0 [V].

[0273] A specific example of the operating potential (voltage) is shown below. For example, the threshold voltage of the transistor 201 is Approximately 0.3V, power supply voltage is VDD=2V, V11=1.6V, V10=1.2V, V0 1=0.8V, V00=0V, and Vref0=0.6V, Vref1=1.0V, Vr It is possible to set ef2=1.4 V. The potential Vpc may be set to 0 V, for example.

[0274] In this embodiment, the first signal line S1 is arranged in the bit line BL direction (column direction), and the second Although the signal line S2 is arranged in the word line WL direction (row direction), this is not necessarily limited to this. For example, the first signal line S1 is arranged in the word line WL direction (row direction), and the second The second signal line S2 may be arranged in the bit line BL direction (column direction). The drive circuit to which the first signal line S1 is connected and the drive circuit to which the second signal line S2 is connected are appropriately Just place it.

[0275] In this embodiment, the operation of a four-level memory cell, that is, four different values ​​are stored in one memory cell. Although the above describes the case where one of the states is written or read, the circuit configuration can be changed appropriately. By changing the value of the bit, the operation of the n-ary memory cell can be changed to any one of n different states (n is an integer greater than or equal to 2) can be written to and read from.

[0276] For example, an 8-level memory cell has three times the memory capacity compared to a 2-level memory cell. In the write operation, eight write potentials are prepared to determine the potential of node A, generating eight states. For readout, seven reference potentials are prepared that can distinguish eight states. For readout, one sense amplifier is provided and seven comparisons can be performed to read out the data. It is also possible to reduce the number of comparisons to three by feeding back the comparison results. In the read method that drives the source line SL, seven sense amplifiers are provided, It is also possible to read out the data by comparing it once. Also, multiple sense amplifiers can be provided to perform multiple comparisons. It is also possible to configure the device to do this.

[0277] In general, 2 k (k is an integer greater than or equal to 1)-valued memory cells have a higher memory capacity than binary memory cells. The capacity is k times larger. In the write operation, the write potential that determines the potential of node A is doubled. k Type preparation Then, 2 k Generates states. For readout, 2 k Two states that can be distinguished k-It is recommended to prepare one reference potential. k -1 comparison In addition, the comparison result can be fed back to the It is also possible to reduce the number of times to k. 2 amplifiers k -You can set one and read it out with one comparison. Also, multiple sense It is also possible to provide an amplifier and perform multiple comparisons.

[0278] The semiconductor device according to this embodiment has a very low off-state current characteristic of the transistor 202. It is possible to retain information for a long period of time. In other words, it is possible to achieve the same performance as DRAM. No refresh operation is required, and power consumption can be reduced. It can be used as a non-volatile memory device.

[0279] In addition, in order to write information by switching the transistor 202, It does not require high voltage and does not have the problem of element degradation. Furthermore, it is possible to turn the transistor on and off with a This allows information to be written and erased, and therefore high-speed operations can be easily achieved. By controlling the potential input to the transistor, data can be directly rewritten. This eliminates the need for the erase operation required in flash memories and the like. This makes it possible to suppress a decrease in operation speed caused by the above-mentioned operation.

[0280] In addition, transistors using materials other than oxide semiconductors can operate at sufficiently high speed. By using this, it is possible to read out the stored contents at high speed.

[0281] In addition, since the semiconductor device according to the present embodiment is a multi-value type, it is possible to increase the memory capacity per area. This allows the semiconductor device to be miniaturized and highly integrated. In the write operation, the potential of the floating node can be directly controlled. This makes it possible to easily control the threshold voltage of a semiconductor device with high accuracy, which is required for a multi-value memory. This also eliminates the need to check the state after writing, which is required for multi-value memory. This can reduce the time required for writing.

[0282] (Embodiment 4) This embodiment describes an example of a circuit configuration and an operation of a semiconductor device different from those of the second and third embodiments. This article explains:

[0283] An example of a circuit diagram of a memory cell included in a semiconductor device is shown in FIG. 240 includes a source line SL, a bit line BL, a first signal line S1, a second signal line S2, and a The gate line WL, a transistor 201, a transistor 202, and a capacitance element 204. The transistor 201 is formed using a material other than an oxide semiconductor. The transistor 202 is formed using an oxide semiconductor.

[0284] Here, the gate electrode of the transistor 201 and the source electrode or drain of the transistor 202 are One of the drain electrodes and one of the electrodes of the capacitor 204 are electrically connected to each other. The source line SL and the source electrode of the transistor 201 are electrically connected to each other, and the bit line BL and the drain electrode of the transistor 201 are electrically connected to the first signal line S1. The other of the source electrode and the drain electrode of the transistor 202 is electrically connected to The second signal line S2 and the gate electrode of the transistor 202 are electrically connected to each other. WL and the other electrode of the capacitor 204 are electrically connected to each other.

[0285] Next, the operation of the memory cell 240 shown in FIG. 31 will be described. Here, in the case of a four-value type The four states of the memory cell 240 are data "00b", "01b", "10b", Let "11b" and the potential of node A at that time be V00, V01, V10, V11 ( V00 <V01<V10<V11)とする。

[0286] When writing to the memory cell 240, the source line SL is set to 0 [V] and the word line WL is set to 0 [V]. V], the bit line BL is set to 0 [V], and the second signal line S2 is set to VDD. When writing data "01b", the first signal line S1 is set to V00 [V]. In this case, the first signal line S1 is set to V01 [V]. When writing data "10b", The first signal line S1 is set to V10 [V]. When writing data "11b", the first signal The line S1 is V11 [V]. At this time, the transistor 201 is in an off state, and the transistor When writing is completed, the potential of the first signal line S1 is changed. Before the initialization, the second signal line S2 is set to 0 [V] to turn off the transistor 202.

[0287] As a result, after writing data "00b", "01b", "10b", and "11b" (word The potential of the line WL is set to 0 [V]. (hereinafter, node A) are approximately V00 [V], approximately V01 [V], and approximately V10 [V ], which is about V11 [V]. A charge corresponding to the potential of the first signal line S1 is accumulated in the node A. However, since the off-state current of the transistor 202 is extremely small or substantially zero, Therefore, the potential of the gate electrode of the transistor 201 is held for a long period of time.

[0288] When reading the memory cell 240, the source line SL is set to 0 [V] and the second signal line S2 is set to 0 [V], the first signal line S1 is set to 0 [V], and the read circuit connected to the bit line BL At this time, the transistor 202 is turned off.

[0289] The word line WL is set to V_WL [V]. The potential of the node A of the memory cell 240 is The potential of the word line WL is dependent on the potential of the word line WL. The higher the potential of the word line WL, the greater the nodal potential of the memory cell 240. For example, for a memory cell in four different states, the voltage of the word line WL is When the potential is changed from low to high, the transistor of the memory cell of data “11b” 201 is turned on first, followed by data "10b", "01b", and "00b". The memory cells are sequentially turned on. This is achieved by appropriately selecting the word line WL potential. This means that the state of the memory cell (i.e., the data in the memory cell) can be identified. By appropriately selecting the potential of the data line WL, the memory cell in which the transistor 201 is on is in a low state. The memory cell in which the transistor 201 is off is in a high resistance state. By distinguishing these resistance states using a read circuit, data "00b", "01b", "10b" and "11b" can be read out.

[0290] FIG. 32 shows a block diagram of a semiconductor device according to one embodiment of the present invention having a storage capacity of m×n bits. 13 shows another example of a circuit diagram.

[0291] The semiconductor device shown in FIG. 32 includes m word lines WL and second signal lines S2, and n bit lines BL and a first signal line S1, and a plurality of memory cells 240(1,1) to 240(m,n) are arranged vertically. Memory cells arranged in a matrix of m rows x n columns (m and n are natural numbers). The array 210, the readout circuit 231, the first signal line driving circuit 212, the second signal line and The signal line driver 223 and the voltage generator 214 are peripheral circuits. As other peripheral circuits, a refresh circuit and the like may be provided.

[0292] Consider each memory cell, e.g., memory cell 240(i,j), where i is between 1 and m, inclusive. where j is an integer between 1 and n). The memory cell 240(i,j) is connected to the bit line BL(j ), a first signal line S1(j), a word line WL(i) and a second signal line S2(i), SL. The source line SL is connected to a source line potential Vs (for example, 0 [V ]) is applied to the bit lines BL(1) to BL(n). The first signal lines S1(1) to S1(n) are connected to the first signal line driving circuit 212, and the word lines WL(1) to WL(m) and the second signal lines S2(1) to S2(m) are the second signal line S2 and the word line WL. Each is connected to a driving circuit 223 .

[0293] The first signal line driver circuit 212 and the potential generating circuit 214 are configured as shown in FIG. The configuration shown in FIG. 21 may be applied.

[0294] An example of a read circuit is shown in FIG. 33. The read circuit includes a sense amplifier circuit, a flip-flop circuit, and a The bias circuit 224 is connected via a switch. The bias circuit 224 is connected to the input terminal of the sense amplifier circuit. The other input terminal of the sense amplifier circuit is connected to a reference potential Vr. In addition, the output terminal of the sense amplifier circuit is connected to the input terminal of the flip-flop circuits FF0 and FF1. The above switches are controlled by the read enable signal (RE signal). The read circuit detects whether a specified memory cell connected to the bit line BL is a bit line. Data can be read by reading the potential output to the bit line B. The potential of L changes according to the conductance. To read out means to read the on or off state of the transistor 201 constituting the memory cell. It means to give out.

[0295] The read circuit shown in FIG. 33 has one sense amplifier circuit and can distinguish between four different states. Two comparisons are performed to obtain the difference between the two. The two comparisons are controlled by the signals RE0 and RE1. The flip-flop circuits FF0 and FF1 are controlled by the signals RE0 and RE1, respectively. The output of the flip-flop circuit FF0 is controlled by the CLK1 pin and stores the value of the output signal of the sense amplifier circuit. The output of the flip-flop circuit FF1 is read as DO[1], and the output of the flip-flop circuit FF2 is read as DO[0]. and output from the circuit.

[0296] In the illustrated read circuit, when the RE signal is deasserted, the bit line BL is wired. When the RE signal is asserted, the bit line BL and the bias The ass circuit 224 becomes conductive. Note that precharging does not have to be performed.

[0297] FIG. 34 shows another example of the drive circuit 223 for the second signal line S2 and the word line WL.

[0298] The second signal line and word line driver circuit 223 shown in FIG. 34 receives the address signal ADR. When the address is asserted, the line specified by the address (selected line) is asserted, and the other lines (unselected lines) are deasserted. The second signal line S2 is connected to the decoder output when the WE signal is asserted. When the WE signal is deasserted, it is connected to GND. The output of the multiplexer (MUX3) is connected to V_WL, and the word lines of the unselected rows are connected to GND. The multiplexer (MUX3) is connected according to the values ​​of the signals RE0, RE1, and DO0. , one of three reference potentials Vref0, Vref1, Vref2, or GND. The behavior of the multiplexer (MUX3) is shown in Table 4.

[0299] [Table 4]

[0300] Three types of reference potentials Vref0, Vref1, Vref2 (Vref0 <Verf1<Vr ef2) will be explained. Vref0 is the potential of the word line WL. In this case, the transistor 201 of the memory cell storing data "00b" is turned off, and 01b" memory cell transistor 201 is turned on. When ref1 is selected as the potential of the word line WL, it is the memory cell of data “01b”. The transistor 201 of the memory cell is turned off, and the transistor of the memory cell of data "10b" is turned on. The potential Vref2 is selected to turn on the word line W When the transistor 201 of the memory cell of data “10b” is selected as the potential of L, is turned off, and the transistor 201 of the memory cell storing data "11b" is turned on. Select the potential.

[0301] This readout circuit performs two comparisons to read out the signal. The first comparison uses Vref1. The second time, if the comparison result using Vref1 is FF0, Vref 2 is used for comparison, and if it is "1", Vref0 is used for comparison. This makes it possible to read out the four states with two comparisons.

[0302] The timing chart for the write operation is the same as that shown in FIG. An example of a timing chart is shown in FIG. 35. The diagram shows data “1 This is a timing chart for reading out "0b". RE0 and RE1 are asserted. Between them, Vref1 and Vref2 are input to the selected word lines WL, and The comparison results in the amplifier circuit are stored in flip-flop circuits FF0 and FF1, respectively. When the data in the memory cell is "10b", the flip-flop circuits FF0 and FF1 The values ​​are "1" and "0." Note that the first signal line S1 and the second signal line S2 are 0 [V].

[0303] A specific example of the operating potential (voltage) is shown below. For example, the threshold voltage V The potential of node A is determined by the capacitance C1 between the word line WL and node A and the transistor It depends on the gate capacitance C2 of the transistor 202. Assume that C1 / C2>>1 when 02 is off, and C1 / C2=1 when it is on. indicates the relationship between the potential of the node A and the potential of the word line WL when the source line SL is 0 [V]. For example, in the case of writing data “00b”, the potential of node A is set to 0V, and the potential of data “ The node A potential for data “01b” is 0.8V, the node A potential for data “10b” is 1.2V, If the node A potential of the data input “11b” is 1.6V, the reference potential is Vref0=0.6V. It turns out that it is good to set Vref1=1.0V and Vref2=1.4V.

[0304] After writing (when the word line WL potential is 0 [V]), the voltage at the node A of the transistor 201 is The potential is preferably set to be equal to or lower than the threshold voltage of the transistor 201.

[0305] In this embodiment, the first signal line S1 is arranged in the bit line BL direction (column direction), and the second Although the signal line S2 is arranged in the word line WL direction (row direction), this is not necessarily limited to this. For example, the first signal line S1 is arranged in the word line WL direction (row direction), and the second The second signal line S2 may be arranged in the bit line BL direction (column direction). The drive circuit to which the first signal line S1 is connected and the drive circuit to which the second signal line S2 is connected are appropriately Just place it.

[0306] In this embodiment, the operation of a four-level memory cell, that is, four different values ​​are stored in one memory cell. Although the above describes the case where one of the states is written or read, the circuit configuration can be changed appropriately. By changing the value of the bit, the operation of the n-ary memory cell can be changed to any one of n different states (n is an integer greater than or equal to 2) can be written to and read from.

[0307] For example, an 8-level memory cell has three times the memory capacity compared to a 2-level memory cell. In the write operation, eight write potentials are prepared to determine the potential of node A, generating eight states. For readout, seven reference potentials are prepared that can distinguish eight states. For readout, one sense amplifier is provided and seven comparisons can be performed to read out the data. It is also possible to reduce the number of comparisons to three by feeding back the comparison results. .

[0308] In general, 2 k (k is an integer greater than or equal to 1)-valued memory cells have a higher memory capacity than binary memory cells. The capacity is k times larger. In the write operation, the write potential that determines the potential of node A is doubled. k Type preparation Then, 2 k Generates states. For readout, 2 k Two states that can be distinguished k -It is recommended to prepare one reference potential. k -1 comparison In addition, the comparison result can be fed back to the It is also possible to reduce the number of times to k. 2 amplifiers k -You can set one and read it out with one comparison. Also, multiple sense It is also possible to provide an amplifier and perform multiple comparisons.

[0309] The semiconductor device according to this embodiment has a very low off-state current characteristic of the transistor 202. It is possible to retain information for a long period of time. In other words, it is possible to achieve the same performance as DRAM. No refresh operation is required, and power consumption can be reduced. It can be used as a non-volatile memory device.

[0310] In addition, in order to write information by switching the transistor 202, It does not require high voltage and does not have the problem of element degradation. Furthermore, it is possible to turn the transistor on and off with a This allows information to be written and erased, and therefore high-speed operations can be easily achieved. By controlling the potential input to the transistor, data can be directly rewritten. This eliminates the need for the erase operation required in flash memories and the like. This makes it possible to suppress a decrease in operation speed caused by the above-mentioned operation.

[0311] In addition, transistors using materials other than oxide semiconductors can operate at sufficiently high speed. By using this, it is possible to read out the stored contents at high speed.

[0312] In addition, since the semiconductor device according to the present embodiment is a multi-value type, it is possible to increase the memory capacity per area. This allows the semiconductor device to be miniaturized and highly integrated. In the write operation, the potential of the floating node can be directly controlled. This makes it possible to easily control the threshold voltage of a semiconductor device with high accuracy, which is required for a multi-value memory. This also eliminates the need to check the state after writing, which is required for multi-value memory. This can reduce the time required for writing.

[0313] (Embodiment 5) In this embodiment, an example of an electronic device equipped with the semiconductor device obtained in the above embodiment will be described. The semiconductor device obtained in the above embodiment operates without the supply of power. In addition, the data can be retained even if the data is written or erased. Furthermore, the operation is also fast. Therefore, the semiconductor device can be used to realize a new configuration of a power supply. It is possible to provide a child device. The semiconductor device is then mounted on a circuit board or the like and installed inside each electronic device.

[0314] FIG. 37A shows a notebook personal computer including the semiconductor device according to the above embodiment. The computer is composed of a main body 301, a housing 302, a display unit 303, a keyboard 304, etc. The semiconductor device according to one embodiment of the present invention is provided in a notebook personal computer. By applying this technology, it is possible to retain information even when there is no power supply. No degradation occurs due to writing and erasing. Furthermore, the operation is fast. The semiconductor device according to the present invention is preferably applied to a notebook personal computer. It is.

[0315] FIG. 37B shows a personal digital assistant (PDA) including the semiconductor device according to the above embodiment. The main body 311 includes a display unit 313, an external interface 315, and operation buttons 314. The present invention also includes a stylus 312 as an accessory for operation. By applying the semiconductor device according to the present invention to a PDA, information can be retained even when there is no power supply. In addition, there is no degradation caused by writing and erasing. For this reason, it is preferable to apply the semiconductor device according to one aspect of the present invention to a PDA. It is.

[0316] FIG. 37C shows an example of electronic paper including the semiconductor device according to the above embodiment. The electronic book 320 is shown. The electronic book 320 is made up of two housings, a housing 321 and a housing 323. The housing 321 and the housing 323 are integrated with each other by a shaft portion 337. The opening and closing operation can be performed around the axis 337. The semiconductor device according to one embodiment of the present invention can be used like a paper book. By applying this technology to electronic paper, it is possible to retain information even when there is no power supply. In addition, there is no degradation caused by writing and erasing. Furthermore, the operation is fast. For this reason, it is preferable to apply the semiconductor device according to one embodiment of the present invention to electronic paper. do.

[0317] A display unit 325 is incorporated in the housing 321, and a display unit 327 is incorporated in the housing 323. The display unit 325 and the display unit 327 may be configured to display a continuous screen, or may be configured to display different images. By configuring to display different screens, for example, A text is displayed on the right display unit (display unit 325 in FIG. 37(C)) and a text is displayed on the left display unit ( In (C), an image can be displayed on the display unit 327).

[0318] FIG. 37C shows an example in which the housing 321 is provided with an operation unit. The body 321 includes a power source 331, operation keys 333, a speaker 335, etc. The page can be turned by pressing the arrow 333. In addition, a keyboard and a pointer are installed on the same surface as the display unit of the housing. The housing may be provided with an external display device or the like. Connection terminals (earphone terminal, USB terminal, AC adapter and USB cable, etc.) A configuration including a terminal that can be connected to various cables, a recording medium insertion portion, etc. Furthermore, the electronic book 320 may be configured to have the functionality of an electronic dictionary.

[0319] The electronic book 320 may be configured to transmit and receive information wirelessly. It is also possible to purchase and download desired book data from the child book server. It is possible.

[0320] Electronic paper can be applied to any field that displays information. For example, in addition to e-books, posters, in-car advertisements on trains and other vehicles, credit cards, etc. The present invention can be applied to displays on various cards such as gift cards.

[0321] FIG. 37D illustrates a mobile phone including the semiconductor device according to the above embodiment. The phone is made up of two housings, housing 340 and housing 341. Housing 341 has a front display panel 342, speaker 343, microphone 344, pointing device 3 46, a camera lens 347, and an external connection terminal 348. The mobile phone includes a solar cell 349 for charging the mobile phone, an external memory slot 350, etc. The antenna is built into the housing 341. By applying the semiconductor device to a mobile phone, data can be retained even when there is no power supply. In addition, there is no degradation caused by writing and erasing. For this reason, it is preferable to apply the semiconductor device according to one embodiment of the present invention to a mobile phone. It is appropriate.

[0322] The display panel 342 has a touch panel function, and in FIG. The mobile phone has a solar cell 34 A boost circuit is implemented to boost the voltage output by 9 to the voltage required by each circuit. In addition to the above configuration, the device may be configured to incorporate a non-contact IC chip, a small recording device, etc. It is also possible.

[0323] The display direction of the display panel 342 changes appropriately depending on the usage mode. A camera lens 347 is provided on the same surface as the camera 42, making video calling possible. The speaker 343 and microphone 344 are not limited to voice calls, but also video calls, recording, playback, etc. Furthermore, the housing 340 and the housing 341 can be slid, and as shown in FIG. It can be folded from the unfolded state to the overlapping state, making it compact and suitable for carrying. It is Noh.

[0324] The external connection terminal 348 can be connected to various cables such as an AC adapter or a USB cable. The external memory slot 350 can store a recording medium. It can store and move larger amounts of data. In addition to the above features, It may also be equipped with an infrared communication function, a television receiving function, etc.

[0325] FIG. 37E shows a digital camera including the semiconductor device according to the above embodiment. The digital camera is comprised of a main body 361, a display unit (A) 367, an eyepiece 363, and an operation switch 364. , a display unit (B) 365, a battery 366, etc. By applying the semiconductor device according to the present invention to a digital camera, information can be stored even when there is no power supply. In addition, there is no deterioration caused by writing and erasing. For this reason, the semiconductor device according to one embodiment of the present invention is suitable for use in a digital camera. It is preferable to use

[0326] FIG. 37F illustrates a television set including the semiconductor device according to the above embodiment. In the vision device 370, a display unit 373 is built into a housing 371. In this case, the stand 375 is used to hold the case in place. This shows the configuration that supported 371.

[0327] The television device 370 can be operated using an operation switch provided on the housing 371 or a separate remote control. This can be done by the operation device 380. The remote control operation device 380 has an operation key 379. This allows you to control the channel and volume, and to operate the image displayed on the display unit 373. In addition, the remote control operation device 380 can receive the output from the remote control operation device 380. A display unit 377 for displaying information to be displayed may be provided. By applying the body device to a television device, information can be retained even when there is no power supply. In addition, there is no degradation caused by writing and erasing. For this reason, the semiconductor device according to one embodiment of the present invention is applied to a television set. This is preferable.

[0328] It is preferable that the television device 370 is configured to include a receiver, a modem, etc. The receiver can receive general television broadcasts. By connecting to a wired or wireless communication network, The communication of information between a single person (e.g., a sender and a receiver, or between receivers themselves) or between two people (e.g., a sender and a receiver, or a receiver and another receiver) It is possible.

[0329] The structures, methods, and the like described in this embodiment mode may be appropriately combined with the structures, methods, and the like described in other embodiments. They can be used in combination. [Explanation of symbols]

[0330] 100 Substrates 102 Protective layer 104 Semiconductor area 106 Element isolation insulating layer 108a Gate insulating layer 110a Gate electrode 112 Insulating layer 114 Impurity region 116 Channel formation region 118 Sidewall insulating layer 120 High concentration impurity region 122 Metal layer 124 Metal compound area 126 Interlayer Insulation Layer 128 Interlayer Insulation Layer 130a source electrode or drain electrode 130b Source electrode or drain electrode 130c electrode 132 Insulating Layer 134 Conductive Layer 136a electrode 136b Electrode 136c electrode 136d Gate electrode 138 Gate Insulation Layer 140 Oxide semiconductor layer 142a Source electrode or drain electrode 142b Source or drain electrode 144 Protective Insulation Layer 146 Interlayer Insulation Layer 148 Conductive Layer 150a electrode 150b electrode 150c electrode 150d electrode 150e electrode 152 Insulating layer 154a electrode 154b electrode 154c electrode 154d electrode 160 Transistors 162 Transistor 200 memory cells 201 Transistor 202 Transistor 203 Transistor 204 Capacitive element 205 Capacitive element 210 Memory Cell Array 211 Readout circuit 212 Signal line driver circuit 213 Drive circuit 214 Potential generation circuit 215 Decoder 216 Transistor 217 Transistor 218 Transistor 219 Boost circuit 220 Analog Buffer 221 Readout circuit 223 Drive circuit 224 Bias Circuit 225 Reference Cell 225a Reference Cell 225b Reference Cell 225c Reference Cell 229 Logic Circuits 231 Readout circuit 240 memory cells 301 Main unit 302 Case 303 Display section 304 Keyboard 311 Main unit 312 Stylus 313 Display section 314 Operation button 315 External Interface 320 e-books 321 Case 323 Case 325 Display section 327 Display section 331 Power supply 333 Operation Key 335 Speaker 337 Shaft 340 Case 341 Case 342 Display Panel 343 Speakers 344 Microphone 345 Operation Key 346 Pointing Device 347 Camera Lenses 348 External connection terminal 349 Solar Cells 350 external memory slot 361 Main unit 363 Eyepiece 364 Operation Switch 365 Display section (B) 366 Battery 367 Display section (A) 370 Television Equipment 371 Case 373 Display section 375 Stand 377 Display section 379 Operation Key 380 Remote Controlled Device 402 Diode 404 Diode 406 Diode 408 Diode 410 Diode 412 Capacitive element 414 Capacitive element 416 Capacitive element 418 Capacitive element 420 Capacitive element

Claims

1. A plurality of circuits arranged in a matrix form are included, Each of the plurality of circuits comprises: a first transistor having a channel formation region including silicon; a second transistor having a channel formation region including an oxide semiconductor; a third transistor having a channel formation region containing silicon; A capacitance element, a gate of the first transistor, one of a source and a drain of the second transistor, and one electrode of the capacitance element are electrically connected to each other; one of a source and a drain of the first transistor and one of a source and a drain of the third transistor are electrically connected to each other; each of the plurality of circuits is a multi-value type; the second transistor is a semiconductor device having a function of holding a potential of n value (n is an integer of 2 or more) applied to a gate electrode of the first transistor, a semiconductor layer having a channel formation region of the first transistor; a first conductive layer having a region located above the semiconductor layer and functioning as a gate electrode of the first transistor; a first insulating layer having a region overlying the first conductive layer, the first insulating layer comprising silicon nitride; a second conductive layer having a region located above the first insulating layer and functioning as a gate electrode of the second transistor; a second insulating layer having a region located above the second conductive layer and functioning as a gate insulating layer of the second transistor; an oxide semiconductor layer having a region located above the second insulating layer and including a channel formation region of the second transistor; a third insulating layer having a region located above the oxide semiconductor layer and including silicon oxide; a fourth insulating layer having a region overlying the third insulating layer and comprising silicon nitride; a third conductive layer having a region located above the fourth insulating layer; the semiconductor layer comprises silicon; the oxide semiconductor layer contains In, Ga, and Zn; the second insulating layer has a stacked structure including a layer containing silicon oxide and a layer containing silicon nitride, the third insulating layer has a region in contact with an upper surface of the oxide semiconductor layer, the third conductive layer has a region in contact with an upper surface of the fourth insulating layer; the first conductive layer is electrically connected to the oxide semiconductor layer via the third conductive layer.

2. A plurality of circuits arranged in a matrix form are included, Each of the plurality of circuits comprises: a first transistor having a channel formation region including silicon; a second transistor having a channel formation region including an oxide semiconductor; a third transistor having a channel formation region containing silicon; A capacitance element, a gate of the first transistor, one of a source and a drain of the second transistor, and one electrode of the capacitance element are electrically connected to each other; one of a source and a drain of the first transistor and one of a source and a drain of the third transistor are electrically connected to each other; each of the plurality of circuits is a multi-value type; the second transistor is a semiconductor device having a function of holding a potential of n value (n is an integer of 2 or more) applied to a gate electrode of the first transistor, a semiconductor layer having a channel formation region of the first transistor; a first conductive layer having a region located above the semiconductor layer and functioning as a gate electrode of the first transistor; a first insulating layer having a region overlying the first conductive layer, the first insulating layer comprising silicon nitride; a second conductive layer having a region located above the first insulating layer and functioning as a gate electrode of the second transistor; a second insulating layer having a region located above the second conductive layer and functioning as a gate insulating layer of the second transistor; an oxide semiconductor layer having a region located above the second insulating layer and including a channel formation region of the second transistor; a third insulating layer having a region located above the oxide semiconductor layer and including silicon oxide; a fourth insulating layer having a region overlying the third insulating layer and comprising silicon nitride; a third conductive layer having a region located above the fourth insulating layer; the semiconductor layer comprises silicon; the oxide semiconductor layer contains In, Ga, and Zn; the second insulating layer has a stacked structure including a layer containing silicon oxide and a layer containing silicon nitride, the third insulating layer has a region in contact with an upper surface of the oxide semiconductor layer, the third conductive layer has a region in contact with an upper surface of the fourth insulating layer; the first conductive layer is electrically connected to the oxide semiconductor layer via the third conductive layer; a channel formation region of the second transistor not overlapping a channel formation region of the first transistor in a plan view.

3. A plurality of circuits arranged in a matrix form are included, Each of the plurality of circuits comprises: a first transistor having a channel formation region including silicon; a second transistor having a channel formation region including an oxide semiconductor; a third transistor having a channel formation region containing silicon; A capacitance element, a gate of the first transistor, one of a source and a drain of the second transistor, and one electrode of the capacitance element are electrically connected to each other; one of a source and a drain of the first transistor and one of a source and a drain of the third transistor are electrically connected to each other; each of the plurality of circuits is a multi-value type; the second transistor is a semiconductor device having a function of holding a potential of n value (n is an integer of 2 or more) applied to a gate electrode of the first transistor, a semiconductor layer having a channel formation region of the first transistor; a first conductive layer having a region located above the semiconductor layer and functioning as a gate electrode of the first transistor; a first insulating layer having a region located above the first conductive layer and a region located above the semiconductor layer, the first insulating layer comprising silicon nitride; a second conductive layer having a region located above the first insulating layer and functioning as a gate electrode of the second transistor; a second insulating layer having a region located above the second conductive layer and functioning as a gate insulating layer of the second transistor; an oxide semiconductor layer having a region located above the second insulating layer and including a channel formation region of the second transistor; a third insulating layer having a region located above the oxide semiconductor layer and including silicon oxide; a fourth insulating layer having a region overlying the third insulating layer and comprising silicon nitride; a third conductive layer having a region located above the fourth insulating layer; the semiconductor layer comprises silicon; the oxide semiconductor layer contains In, Ga, and Zn; the second insulating layer has a stacked structure including a layer containing silicon oxide and a layer containing silicon nitride, the third insulating layer has a region in contact with an upper surface of the oxide semiconductor layer, the third conductive layer has a region in contact with an upper surface of the fourth insulating layer; a channel length direction of the second transistor intersects with a channel length direction of the first transistor in a plan view; the third conductive layer has a region extending in a direction intersecting a channel length direction of the first transistor, the first conductive layer is electrically connected to the oxide semiconductor layer via the third conductive layer.

4. A plurality of circuits arranged in a matrix form are included, Each of the plurality of circuits comprises: a first transistor having a channel formation region including silicon; a second transistor having a channel formation region including an oxide semiconductor; a third transistor having a channel formation region containing silicon; A capacitance element, a gate of the first transistor, one of a source and a drain of the second transistor, and one electrode of the capacitance element are electrically connected to each other; one of a source and a drain of the first transistor and one of a source and a drain of the third transistor are electrically connected to each other; each of the plurality of circuits is a multi-value type; the second transistor is a semiconductor device having a function of holding a potential of n value (n is an integer of 2 or more) applied to a gate electrode of the first transistor, a semiconductor layer having a channel formation region of the first transistor; a first conductive layer having a region located above the semiconductor layer and functioning as a gate electrode of the first transistor; a first insulating layer having a region located above the first conductive layer and a region located above the semiconductor layer, the first insulating layer comprising silicon nitride; a second conductive layer having a region located above the first insulating layer and functioning as a gate electrode of the second transistor; a second insulating layer having a region located above the second conductive layer and functioning as a gate insulating layer of the second transistor; an oxide semiconductor layer having a region located above the second insulating layer and including a channel formation region of the second transistor; a third insulating layer having a region located above the oxide semiconductor layer and including silicon oxide; a fourth insulating layer having a region overlying the third insulating layer and comprising silicon nitride; a third conductive layer having a region located above the fourth insulating layer; the semiconductor layer comprises silicon; the oxide semiconductor layer contains In, Ga, and Zn; the second insulating layer has a stacked structure including a layer containing silicon oxide and a layer containing silicon nitride, the third insulating layer has a region in contact with an upper surface of the oxide semiconductor layer, the third conductive layer has a region in contact with an upper surface of the fourth insulating layer; a channel formation region of the second transistor does not overlap a channel formation region of the first transistor in a plan view; a channel length direction of the second transistor intersects with a channel length direction of the first transistor in a plan view; the third conductive layer has a region extending in a direction intersecting a channel length direction of the first transistor, the first conductive layer is electrically connected to the oxide semiconductor layer via the third conductive layer.

5. In any one of claims 1 to 4, the oxide semiconductor layer has a region in contact with an upper surface of the layer containing silicon oxide.

6. In any one of claims 1 to 5, The oxide semiconductor layer contains In, Ga, and Zn.

Images