Select Gate Isolation for 3D NAND

Abstract

A memory string is described that includes at least one select gate for drain (SGD) transistor and at least one memory transistor in a vertical hole that extends through a memory stack on a substrate. The memory stack includes alternating word lines and dielectric materials. The at least one select gate for drain (SGD) transistor, including a first gate material, is in a first vertical hole that extends through the memory stack. The at least one memory transistor, including a second gate material different from the first gate material, is in a second vertical hole that extends through the memory stack.

Description

[Technical field]

[0001] FIELD OF THE DISCLOSURE Embodiments of the present disclosure relate to the field of electronic devices and methods and apparatus for manufacturing electronic devices. More particularly, embodiments of the present disclosure provide a 3D-NAND select-gate-for-drain (SGD) transistor and a method for forming the same. [Background technology]

[0002] Semiconductor technology is advancing rapidly, with device dimensions shrinking with technology advances, resulting in faster processing and storage per unit space. In NAND devices, the string current needs to be large enough to get enough current to distinguish between on and off cells. This string current depends on carrier mobility, which is enhanced by enlarging the grain size of the silicon channel.

[0003] Current 3D-NAND devices with memory stacks containing alternating layers of oxide and nitride materials have multiple memory holes between two slits. For access to each cell by word lines and bit lines, the memory holes between the slits need to be divided by a select gate at drain (SGD) cut. For example, Toshiba 96L stacked 3D NAND with 8 memory holes and one dummy hole has one SGD cut that separates the holes into two groups. To reduce the array size of 3D-NAND, the number of holes (nHole) between the slits needs to be increased. If nHole is increased beyond 8 holes, multiple SGD cuts are required for the same technology. Holes under the same bit line level need to be individually accessible by a combination of bit line (BL) and word line (WL). In other words, holes under the same bit line are independently selected by the select gate for drain (SGD) and bit line. For this purpose, the SGD between the slits needs to be separated by an SGD cut. When the number of holes (nHole) between the slits is small (e.g., 8 or less), one SGD cut is used to separate the drain select gates (SGDs). However, when the number of holes (nHole) between the slits is large (e.g., 12 or more), an additional SGD cut is required for every 4 holes.

[0004] Therefore, there is a need in the art for a 3D-NAND device having a select gate for drain (SGD) cut and a method for manufacturing the 3D-NAND device. Summary of the Invention

[0005] One or more embodiments of the present disclosure are directed to a semiconductor memory device. In one or more embodiments, the semiconductor memory device includes at least one drain select gate (SGD) on a memory stack on a substrate, the memory stack including alternating word lines and a dielectric material; at least one drain select gate (SGD) transistor in a first vertical hole extending through the memory stack, the drain select gate (SGD) transistor including a first gate material; and at least one memory transistor in a second vertical hole extending through the memory stack, the memory stack including a second gate material different from the first gate material.

[0006] Another embodiment of the present disclosure is directed to a semiconductor memory device. In one or more embodiments, the semiconductor memory device includes at least one drain select gate (SGD) on a memory stack on a substrate, the memory stack including alternating word lines and dielectric material; a vertical string extending through the memory stack, the vertical string including at least one SGD transistor and at least one memory transistor; a bit line pad on an upper surface of the vertical string, the bit line pad having a first size; and a self-aligned mask layer on an upper surface of the bit line pad, the self-aligned mask layer having a second size 1 nm to 50 nm larger than the first size.

[0007] Additional embodiments of the present disclosure are directed to methods of forming a semiconductor device. In one or more embodiments, a method of forming a semiconductor device having a three-dimensional vertical memory string including a drain select gate (SGD) transistor and a memory transistor includes forming a drain select gate (SGD) gate on a top surface of a memory stack, the memory stack including alternating first and second layers on a substrate; forming a memory string, the memory string extending through the drain select gate (SGD) gate and the memory stack; forming a bit line pad on a top surface of the memory string; forming a self-aligned mask on a top surface of the bit line pad; forming a first opening in the drain select gate (SGD) gate; filling the first opening with a dielectric material; forming a slit extending from a top surface of the drain select gate (SGD) gate through the memory stack to the substrate; removing the first layer to form a second opening; and forming a word line in the second opening.

[0008] In order that the above-mentioned features of the present disclosure may be understood in detail, a more detailed description of the present disclosure, briefly summarized above, may be obtained by referring to the embodiments, some of which are illustrated in the attached drawings. However, it should be noted that the attached drawings illustrate only typical embodiments of the present disclosure, since the present disclosure may admit of other equally effective embodiments, and therefore, the attached drawings should not be considered as limiting the scope of the present disclosure. The embodiments described herein are presented by way of example and are not limited to the figures of the attached drawings, in which like references indicate like elements. [Brief description of the drawings]

[0009] [Figure 1] 1 is a process flow diagram of a method for forming a memory device according to embodiments described herein; [Diagram 2]1 is a cross-sectional view of an electronic device with a memory stack according to one or more embodiments. [Diagram 3] 1 illustrates a cross-sectional view of an electronic device after forming a staircase pattern of a memory stack according to one or more embodiments. [Figure 4] 1 is a cross-sectional view of an electronic device according to one or more embodiments. [Figure 5A] 1 is a cross-sectional view of an electronic device according to one or more embodiments. [Figure 5B] 1 is a close-up view of area 120 in accordance with one or more embodiments. [Figure 6A] 1 is a cross-sectional view of an electronic device according to one or more embodiments. [Figure 6B] 1 is a close-up view of area 120 in accordance with one or more embodiments. [Figure 7A] 1 is a cross-sectional view of an electronic device according to one or more embodiments. [Figure 7B] 1 is a close-up view of area 120 in accordance with one or more embodiments. [Figure 8] 1 is a cross-sectional view of an electronic device according to one or more embodiments. [Figure 9A] 1 is a cross-sectional view of an electronic device according to one or more embodiments. [Figure 9B] 1 is a close-up view of area 120 in accordance with one or more embodiments. [Figure 10A] 1 is a cross-sectional view of an electronic device according to one or more embodiments. [Figure 10B] 1 is a close-up view of area 120 in accordance with one or more embodiments. [Figure 10C] 1 is an expanded view of region 120 in accordance with one or more alternative embodiments. [Figure 11] 1 is a cross-sectional view of an electronic device according to one or more embodiments. [Figure 12] 1 is a cross-sectional view of an electronic device according to one or more embodiments. [Figure 13A] 1 is a cross-sectional view of an electronic device according to one or more embodiments. [Figure 13B] FIG. 1 is a view along line AB in accordance with one or more embodiments. [Figure 14A] 1 is a cross-sectional view of an electronic device according to one or more embodiments. [Figure 14B] FIG. 1 is a view along line AB in accordance with one or more embodiments. [Figure 15A] 1 is a cross-sectional view of an electronic device according to one or more embodiments. [Figure 15B] 1 is a cross-sectional view of an electronic device according to one or more embodiments. [Figure 16] 1 is a cross-sectional view of an electronic device according to one or more embodiments. [Figure 17A] 1 is a cross-sectional view of an electronic device according to one or more embodiments. [Figure 17B] 1 is a cross-sectional view of an electronic device according to one or more embodiments. [Figure 18] 1 is a cross-sectional view of an electronic device according to one or more embodiments. [Figure 19A] 1 is a cross-sectional view of an electronic device according to one or more embodiments. [Figure 19B] 1 is a close-up view of area 148 in accordance with one or more embodiments. [Figure 20] 1 is a cross-sectional view of an electronic device according to one or more embodiments. [Figure 21] 1 is a cross-sectional view of an electronic device according to one or more embodiments. [Figure 22] 1 is a cross-sectional view of an electronic device according to one or more embodiments. [Figure 23] FIG. 1 is a perspective view of an electronic device according to one or more embodiments. [Figure 24] FIG. 1 illustrates a cluster tool in accordance with one or more embodiments. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] Before describing certain example embodiments of the present disclosure, it is to be understood that the present disclosure is not limited to the details of construction or process steps set forth in the following description as the present disclosure is capable of other embodiments and of being practiced or carried out in various ways.

[0011] As used herein and in the appended claims, the terms "precursor," "reactant," "reactive gas," and the like are used interchangeably to refer to any gas species capable of reacting with the substrate surface.

[0012] In the following description, numerous specific details are described, such as specific materials, chemical properties, dimensions, etc. of elements, to provide a thorough understanding of one or more embodiments of the present disclosure. However, it will be apparent to one of ordinary skill in the art that one or more embodiments of the present disclosure may be practiced without these specific details. In other examples, semiconductor manufacturing processes, techniques, materials, devices, etc. have not been described in detail to avoid unnecessarily obscuring this description. One of ordinary skill in the art will be able to implement the appropriate functionality by reading the included description without undue experimentation.

[0013] While certain exemplary embodiments of the present disclosure are described and illustrated in the accompanying drawings, it is to be understood that such embodiments are merely exemplary and do not limit the disclosure, and that the disclosure is not limited to the specific constructions and configurations illustrated and described, as modifications may occur to those skilled in the art.

[0014] In existing 3D NAND devices based on memory stacks of alternating layers of oxide and nitride materials, the current integration scheme cannot be used to form the drain select gate (SGD) cut when there are multiple SGD cuts (e.g., drain select gate before word line replacement). In the current integration scheme, the SGD formed before the replacement blocks the replacement of the word line between the SGD cuts. To reduce the array size of 3D-NAND, the number of memory strings (e.g., holes) between slits (nHole) needs to be increased. The holes under the same bit line level need to be individually accessible by the combination of the bit line (BL) and the word line (WL). In other words, the holes under the same bit line are independently selected by the drain select gate (SGD) and the bit line. For this purpose, the SGD between the slits needs to be separated by an SGD cut. When the number of holes (nHole) between the slits is small (e.g., 8 or less), the drain select gate (SGD) is separated by one SGD cut. However, when the number of holes (nHole) between the slits is large (e.g., 12 or more), an additional SGD cut is required for every 4 holes. Therefore, one or more embodiments provide a 3D NAND structure and a method for fabricating a select gate cut for the drain using a non-replacement gate integration scheme.

[0015] Existing 3D NAND devices using the WL replacement scheme cannot meet the SGD cut requirement for nHole (12 or more). The SGD cut areas formed before the WL replacement block the removal of the silicon nitride (SiN) sacrificial layer. Therefore, the SGD transistors located between the SGD cuts cannot function as transistors due to lack of WL.

[0016] One or more embodiments provide a structure and method for fabricating a select gate for drain (SGD) transistor while transistors other than the SGD transistor are formed by non-replacement. In addition, an SGD cut without dummy holes is formed, thus strengthening the cell.

[0017] The device and fabrication method of one or more embodiments advantageously allows for cutting of the select gate for the drain without dummy holes, thus increasing cell density.

[0018] In one or more embodiments, metal deposition and other processes can be performed in an isolated environment (e.g., a cluster processing tool). Accordingly, some embodiments of the present disclosure provide an integrated tool system with associated process modules for implementing the methods.

[0019] FIG. 1 illustrates a flow chart of an exemplary method 10 for forming a memory device. Those skilled in the art will recognize that the method 10 can include any or all of the illustrated processes. In addition, the order of the individual processes can be partially changed. The method 10 can start with any of the listed processes without departing from the present disclosure. With reference to FIG. 1, in operation 15, a memory stack is formed. In operation 20, a gate for a drain select gate is formed on the memory stack. In operation 25, a stepped word line is formed in the memory stack. In operation 30, a memory hole is patterned. In operation 35, a transistor layer is deposited in the memory hole. In operation 40, a bit line pad is formed. In operation 45, the critical dimension of the bit line pad is increased. In operation 50, a self-aligned mask is formed on the bit line pad. In operation 55, a drain select gate is cut. In operation 60, a dielectric layer is deposited in the opening formed by the drain select gate cut. In operation 65, the device is slit patterned. In operation 70, the common source line sacrificial layer is removed and replaced. In operation 75, word lines are formed. In operation 80, the slits are filled with dielectric material. In operation 85, bit line pad studs are formed. In operation 90, back end of line (BEOL) contacts are formed.

[0020] 2-21 show a portion of a memory device 100 following the process flow shown in method 10 of FIG.

[0021] Figure 2 illustrates an initial or starting memory stack for an electronic device 100 in accordance with one or more embodiments of the present disclosure. In some embodiments, the electronic device 100 illustrated in Figure 2 is formed in layers on a bare substrate 102, as shown. The electronic device of Figure 2 is comprised of a substrate 102, a common source line 103, and a memory stack 130.

[0022] The substrate 102 may be any suitable material known to those of skill in the art. As used herein and in the appended claims, the term "substrate" refers to a surface or a portion of a surface on which processing occurs. Those of skill in the art will also understand that references to a substrate may refer to only a portion of the substrate, unless the context clearly indicates otherwise. Furthermore, references to deposition on a substrate may refer to both a bare substrate and a substrate having one or more films or features deposited or formed thereon.

[0023] As used herein, "substrate" refers to any substrate or material surface formed on a substrate on which a film treatment is performed during a manufacturing process. For example, substrate surfaces on which treatment may be performed include materials such as silicon, silicon oxide, strained silicon, silicon-on-insulator (SOI), carbon-doped silicon oxide, amorphous silicon, doped silicon, germanium, gallium arsenide, glass, sapphire, and any other materials such as metals, metal nitrides, metal alloys, and other conductive materials, depending on the application. Substrates include, but are not limited to, semiconductor wafers. Substrates may be exposed to pretreatment processes to polish, etch, reduce, oxidize, hydroxylate, anneal, and / or bake the substrate surface. In addition to direct film treatment on the surface of the substrate itself, in this disclosure, any of the disclosed film treatment steps may also be performed on underlying layers formed on the substrate, as disclosed in more detail below, and the term "substrate surface" is intended to include such underlying layers as the context indicates. Thus, for example, if a film / layer or partial film / layer is being deposited on a substrate surface, the exposed surface of the newly deposited film / layer becomes the substrate surface.

[0024] In one or more embodiments, the common source line 103 is on the substrate 102. The common source line 103 may also be referred to as a semiconductor layer. The common source line 103 may be formed by any suitable technique known to one of ordinary skill in the art and may be fabricated from any suitable material, including, but not limited to, polysilicon (poly-Si). In some embodiments, the common source line 103 includes several different conductive or semiconductor materials. For example, in one or more embodiments, as shown in FIG. 2, the common source line 103 includes a polysilicon layer 104 on the substrate 102, a sacrificial layer 106 on the polysilicon layer, and a second polysilicon layer 104 on the sacrificial layer 106.

[0025] In one or more embodiments, the sacrificial layer 106 may be formed on the polysilicon layer 104 and may be fabricated from any suitable material. The sacrificial layer 106 in some embodiments is removed and replaced in a later process. In some embodiments, the sacrificial layer 106 is not removed and remains in the memory device 100. In this case, the term "sacrificial" has an expanded meaning to include a permanent layer, and may also be referred to as a conductive layer. In the illustrated embodiment, the sacrificial layer 106 is removed in operation 70, as described further below. In one or more embodiments, the sacrificial layer 106 comprises a material that can be selectively removed relative to the adjacent polysilicon layer 104. In one or more embodiments, the sacrificial layer may be a nitride material, such as, for example, silicon nitride (SiN), or a silicon oxide (SiO x ) and other oxide materials.

[0026] In one or more embodiments, a memory stack 130 is formed on the common source line 103. The memory stack 130 in the illustrated embodiment includes a plurality of alternating first layers 108 and second layers 110. Although the memory stack 130 shown in FIG. 2 has five pairs of alternating first layers 108 and second layers 110, one of ordinary skill in the art will recognize that this is for illustrative purposes only. The memory stack 130 can have any number of alternating first layers 108 and second layers 110. For example, in some embodiments, the memory stack 130 includes 192 pairs of alternating first layers 108 and second layers 110. In other embodiments, the memory stack 130 includes more than 50 pairs of alternating first layers 108 and second layers 110, or more than 100 pairs of alternating first layers 108 and second layers 110, or more than 300 pairs of alternating first layers 108 and second layers 110.

[0027] In one or more embodiments, the first layer 108 and the second layer 110 independently comprise a dielectric material. In one or more embodiments, the dielectric material may comprise any suitable dielectric material known to one of skill in the art. As used herein, the term "dielectric material" refers to an electrical insulator that can be polarized in an electric field. In some embodiments, the dielectric material comprises one or more of an oxide, a carbon-doped oxide, silicon dioxide (SiO2), porous silicon dioxide (SiO2), silicon nitride (SiN), silicon dioxide / silicon nitride, a carbide, an oxycarbide, a nitride, an oxynitride, an oxycarbonitride, a polymer, a phosphosilicate glass, a fluorosilicate (SiOF) glass, or an organosilicate glass (SiOCH).

[0028] In one or more embodiments, the first layer 108 comprises an oxide layer and the second layer 110 comprises a nitride layer. In one or more embodiments, the second layer 110 comprises a material that is etch selective to the first layer 108 such that the second layer 110 can be removed without substantially affecting the first layer 108. In one or more embodiments, the first layer 108 comprises a silicon oxide (SiO x). In one or more embodiments, the second layer 110 comprises silicon nitride (SiN). In one or more embodiments, the first layer 108 and the second layer 110 are deposited by chemical vapor deposition (CVD) or physical vapor deposition (PVD).

[0029] The individual alternating layers can be formed to any suitable thickness. In some embodiments, the thickness of each second layer 110 is approximately equal. In one or more embodiments, each second layer 110 has a second layer thickness. In some embodiments, the thickness of each first layer 108 is approximately equal. As used in this regard, approximately equal thickness is within ±5% of each other. In some embodiments, a silicon layer (not shown) is formed between the second layer 110 and the first layer 108. The thickness of the silicon layer can be relatively thin compared to the layer thickness of the second layer 110 or the first layer 108. In one or more embodiments, the first layer 108 has a thickness in the range of about 0.5 nm to about 30 nm, including about 1 nm, about 3 nm, about 5 nm, about 7 nm, about 10 nm, about 12 nm, about 15 nm, about 17 nm, about 20 nm, about 22 nm, about 25 nm, about 27 nm, and about 30 nm. In one or more embodiments, the first layer 108 has a thickness in the range of about 0.5 to about 40 nm. In one or more embodiments, the second layer 110 has a thickness in the range of about 0.5 to about 30 nm, including about 1 nm, about 3 nm, about 5 nm, about 7 nm, about 10 nm, about 12 nm, about 15 nm, about 17 nm, about 20 nm, about 22 nm, about 25 nm, about 27 nm, and about 30 nm. In one or more embodiments, the second layer 110 has a thickness in the range of about 0.5 to about 40 nm.

[0030] In one or more embodiments, the first layer 108 and the second layer 110 are deposited by chemical vapor deposition (CVD) or physical vapor deposition (PVD). The individual alternating layers can be formed to any suitable thickness. In some embodiments, the thickness of each second layer 112 is approximately equal. In one or more embodiments, each second layer 112 has a thickness of the first second layer. In some embodiments, the thickness of each first layer 110 is approximately equal. As used in this regard, approximately equal thicknesses are within ±5% of each other. In one or more embodiments, the first layer 108 has a thickness in the range of about 0.5 nm to about 30 nm, including about 1 nm, about 3 nm, about 5 nm, about 7 nm, about 10 nm, about 12 nm, about 15 nm, about 17 nm, about 20 nm, about 22 nm, about 25 nm, about 27 nm, and about 30 nm. In one or more embodiments, the second layer 110 has a thickness in the range of about 0.5 nm to about 30 nm, including about 1 nm, about 3 nm, about 5 nm, about 7 nm, about 10 nm, about 12 nm, about 15 nm, about 17 nm, about 20 nm, about 22 nm, about 25 nm, about 27 nm, and about 30 nm.

[0031] 2, in operation 20 of method 10, a drain select gate material 112 is formed on the top surface of memory stack 130. In one or more embodiments, the drain select gate material 112 is formed on the top surface of first layer 108. In one or more embodiments, the drain select gate material 112 includes one or more of polysilicon or a metal. The metal may include any suitable metal known to one of skill in the art. In some embodiments, the metal is a refractory metal, and in one or more embodiments, the metal may be selected from one or more of tungsten (W), molybdenum (Mo), ruthenium (Ru), iridium (Ir), tantalum (Ta), titanium (Ti), and osmium (Os).

[0032] 3, in act 25 of method 10, a staircase structure 131 is created. A mask layer 114 is deposited on top of the gate material 112 of the drain select gate. The mask layer 114 may comprise any suitable material known to one of ordinary skill in the art. In one or more embodiments, the mask layer 114 comprises a nitride.

[0033] In one or more embodiments, the staircase structure 131 exposes a top surface 134 of the first layer 108. The top surface 134 can be used to provide space for forming word line contacts, as described below. A suitable fill material 135 can be deposited to occupy the space outside the staircase structure 131. As will be appreciated by those skilled in the art, a suitable fill material 135 can be any material that prevents electrical shorting between adjacent word lines. The staircase structure 131 has a width (shown from left to right in the figure) such that each word line is narrower than the word line below. The use of relative terms such as "top" and "bottom" should not be construed as limiting the scope of the present disclosure to physical directions in space.

[0034] It should be noted that for ease of explanation, the staircase structure 131 is not shown in FIGS. 4-22, however, as will be appreciated by those skilled in the art, the staircase structure 131 is present.

[0035] 4-5B illustrate the formation of a memory string through the memory stack 130. Referring to FIG. 4, in operation 30, a memory hole channel 116 is opened and patterned through the memory stack 130. In some embodiments, opening the memory hole channel 116 includes etching through the mask layer 114, the memory stack 130, the common source line 103, and into the substrate 102. The memory hole channel 116 extends through the memory stack 130 and has sidewalls that expose the surface 111 of the second layer 110 and the surface 109 of the first layer 108.

[0036] The gate material 112 of the drain select gate has a surface 113 exposed as a sidewall of a memory hole channel 116. The memory hole channel 116 extends a distance into the substrate 102 such that sidewall surfaces 109, 111, 113 and a bottom 115 of the memory hole channel 116 are formed in the substrate 102. The bottom 114 of the memory hole channel 116 can be formed anywhere within the thickness of the substrate 102. In some embodiments, the memory hole channel 116 extends into the substrate 102 at a thickness in the range of about 10% to about 90%, or about 20% to about 80%, or about 30% to about 70%, or about 40% to about 60% of the thickness of the substrate 102. In some embodiments, the memory hole channel 116 extends into the substrate 102 at a distance of 10 nm or more. In some embodiments, the memory hole channel 116 extends from the top surface of the gate of the select gate for drain (SGD) through the memory stack to the bottom surface of the substrate.

[0037] 5A illustrates operation 35 in which a transistor layer 118 is formed in the memory hole channel 116. The transistor layer 118 may be formed by any suitable technique known to those of skill in the art. In some embodiments, the transistor layer is formed by a conformal deposition process. In some embodiments, the transistor layer is formed by one or more of atomic layer deposition or chemical vapor deposition.

[0038] In one or more embodiments, the deposition of the transistor layer 118 is substantially conformal. As used herein, a "substantially conformal" layer refers to a layer whose thickness is approximately the same throughout (e.g., the top, middle, and bottom of the sidewalls, and the bottom of the memory hole channel 116). The thickness of a substantially conformal layer varies by no more than about 5%, 2%, 1%, or 0.5%. The transistor layer 118 in the memory hole may include one or more of an aluminum oxide (AlO) layer, a blocking oxide layer, a trapping layer, a tunnel oxide layer, and a channel layer.

[0039] 5B, which is an expanded view of region 120 of FIG. 5A, in one or more embodiments, the transistor layer 118 includes an aluminum oxide layer 118a, a blocking oxide layer 118b, a nitride trapping layer 118c, a tunnel oxide layer 118d, and a channel material 118e in the memory hole channel 116. In one or more embodiments, the channel material 118e includes polysilicon. In one or more embodiments, the aluminum oxide layer 118a is deposited on the sidewalls of the memory hole channel 116 in the memory hole channel 116.

[0040] The transistor layer 118 can have any suitable thickness depending, for example, on the dimensions of the memory hole channel 116. In some embodiments, the transistor layer 118 has a thickness in the range of about 0.5 nm to about 50 nm, or in the range of about 0.75 nm to about 35 nm, or in the range of about 1 nm to about 20 nm.

[0041] In one or more embodiments, the transistor layer 118 includes one or more of a select gate for drain (SGD) transistor or a memory transistor, and the transistor layer 118 includes one or more transistor layers independently selected from aluminum oxide (AlO), a blocking oxide, a trapping material, a tunnel oxide, and a channel layer / channel material.

[0042] In one or more embodiments, the at least one select gate for drain (SGD) transistor further comprises a first gate dielectric and the at least one memory transistor comprises a second gate dielectric, the first gate dielectric and the second gate dielectric comprising the same material.

[0043] 6A-7B illustrate operation 40 of method 10 in which bitline pad 122 is formed on the top surface of transistor layer 118 and mask layer 114. In one or more embodiments, bitline pad 122 is formed on the drain side of a select gate for drain (SGD) transistor. Bitline pad 122 may be any suitable material known to those of skill in the art, including but not limited to polysilicon. With reference to FIGS. 6A and 6B, transistor layer 118 is etched back to form recess 121. As shown in FIGS. 7A and 7B, the recess is then filled with bitline pad 122.

[0044] In operation 45 of method 10, bitline pad 122 is recessed to form recess opening 123. A critical dimension of recess opening 123 is then enlarged to form enlarged recess opening 125, as shown in Figures 9A and 9B. Enlarged recess opening 125 has a depth D and an overhang O. Overhang O is the distance from an edge of bitline pad 122 to an edge of enlarged recess opening 125. In one or more embodiments, enlarged recess opening 125 has a depth D in the range of 1 nm to 100 nm, or 1 nm to 50 nm, or 1 nm to 20 nm. In one or more embodiments, the amount of overhang O is in the range of 1 nm to 50 nm, or 1 nm to 20 nm.

[0045] 10A and 10B, in operation 50 of method 10, a self-aligned mask layer 124 is formed in the enlarged recess opening 125. In one or more embodiments, the self-aligned mask layer 124 has a thickness equal to a depth D of the enlarged recess opening 125 in a range of 1 nm to 100 nm, or 1 nm to 50 nm, or 1 nm to 20 nm. In one or more embodiments, the self-aligned mask layer 124 has an amount of overhang O equal to an amount of overhang O of the enlarged recess opening 125 in a range of 1 nm to 50 nm, or 1 nm to 20 nm. The self-aligned mask layer 124 may include any suitable material known to one of ordinary skill in the art. In one or more embodiments, the self-aligned mask layer 124 may be selected from one or more of silicon nitride (SiN), aluminum oxide (AlO), hafnium oxide (HfO), refractory metals, refractory metal silicides, and refractory metal oxides.

[0046] 10C, in an alternative embodiment, the enlarged recess opening 125 is filled with a liner 126 and a metal 128. In one or more embodiments, the liner 126 and the metal 128 together have a thickness equal to the depth D of the enlarged recess opening 125, ranging from 1 nm to 100 nm, or from 1 nm to 50 nm, or from 1 nm to 20 nm. In one or more embodiments, the liner 126 and the metal 128 together have an amount of overhang O equal to an amount of overhang O of the enlarged recess opening 125, ranging from 1 nm to 50 nm, or from 1 nm to 20 nm. The liner 126 may include any suitable material known to one of ordinary skill in the art. In one or more embodiments, the liner may be selected from one or more of titanium nitride (TiN) or tantalum nitride (TaN). The metal 128 may include any suitable material known to one of ordinary skill in the art. In one or more embodiments, the metal 128 can be selected from one or more of tungsten (W), molybdenum (Mo), tantalum (Ta), ruthenium (Ru), platinum (Pt), and osmium (Os).

[0047] 11, a hardmask layer 230 is formed on top of the mask layer 114 and the self-aligned mask 124. The hardmask layer 230 may comprise any suitable material known to one of ordinary skill in the art. In one or more embodiments, the hardmask layer 230 may be an amorphous carbon-based film.

[0048] 12, hardmask layer 230 is patterned to form opening 132. Opening 132 extends from the top surface of hardmask layer 230 to the top surface of mask layer 114 and self-aligned mask 124. Etching / patterning can be performed by any suitable means known to those skilled in the art.

[0049] 13A and 13B, in operation 55 of method 10, a drain select gate cut 134 is etched / cut into the device. In some embodiments, this may be referred to as patterning the drain select gate cut (SGD). The drain select gate cut 134 extends from the top surface of the hard mask layer 230 through the drain select gate 112 to the first layer 108. The etching / patterning may be performed by any suitable means known to those skilled in the art. In one or more embodiments, forming the drain select gate cut 134 includes sequentially etching the oxide layer and the drain select gate 112 material, for example, by anisotropic dry etching. FIG. 13B shows a view of the device along line AB.

[0050] 14A and 14B, the hardmask layer 230 is removed. The hardmask layer 230 may be removed by any suitable means known to one of ordinary skill in the art. In some embodiments, the hardmask layer is removed by one or more of ashing and stripping.

[0051] 15A and 15B, a dielectric layer 136 is deposited on the top surface of the mask layer 114 and the self-aligned mask 124 to fill in the drain select gate cut 134. The dielectric layer 136 can be deposited by any suitable technique known to one of skill in the art. The dielectric layer 136 can include any suitable material known to one of skill in the art. In one or more embodiments, the dielectric layer 136 is a low-k dielectric, including materials such as, but not limited to, silicon dioxide, silicon oxide, carbon-doped oxides ("CDO"), such as carbon-doped silicon dioxide, porous silicon dioxide (SiO2), silicon nitride (SiN), or any combination thereof. The term "silicon oxide" may be used to describe the dielectric layer 136, but one of skill in the art will recognize that the present disclosure is not limited to a particular stoichiometry. For example, the terms "silicon oxide" and "silicon dioxide" can both be used to describe materials having silicon atoms and oxygen atoms in any suitable stoichiometric ratio. The same is true for other materials listed in this disclosure, such as silicon nitride, silicon oxynitride, aluminum oxide, zirconium oxide, etc. Referring to Figure 15B, after deposition of dielectric layer 136, the device is planarized to form a smooth and / or flat surface 137.

[0052] 16, in act 65 of method 10 , memory stack 130 is slit patterned to form slit pattern openings 138 extending from the top surface of mask layer 114 to sacrificial layer 106 of common source line 103 .

[0053] 17A and 17B, an operation 70 of method 10 is shown in which sacrificial layer 106 in common source line 103 is removed to form opening 140 and replaced with polysilicon layer 142. Sacrificial layer 106 may be removed by any suitable technique known to those skilled in the art, including, but not limited to, selective etching, hot phosphoric acid, etc. Polysilicon layer 186 may be doped or undoped.

[0054] 18 shows that the second layer 110 is removed to form the wordlines. The second layer 110 may be removed by any suitable means known to one of ordinary skill in the art. In one or more embodiments, the second layer 110 is removed by a selective etch, such as a selective wet etch or a selective dry etch. The removal of the second layer 110 forms an opening 144.

[0055] 19A and 19B illustrate operation 75 of method 10, in which wordlines 146 are formed. FIG. 19B is an expanded view of region 148 of FIG. 19A. Wordlines 146 include one or more of an oxide layer 146a, a barrier layer 146b, and a wordline metal 146c. Oxide layer 146a may include any suitable material known to those of skill in the art. In one or more embodiments, oxide layer 146a is an aluminum oxide layer. Barrier layer 146b may include any suitable material known to those of skill in the art. In one or more embodiments, barrier layer 146b includes one or more of titanium nitride (TiN), tantalum nitride (TaN), or the like. In one or more embodiments, the wordline metal 146c comprises a bulk metal including one or more of copper (Cu), cobalt (Co), tungsten (W), aluminum (Al), ruthenium (Ru), iridium (Ir), molybdenum (Mo), platinum (Pt), tantalum (Ta), titanium (Ti), or rhodium (Rh). In one or more embodiments, the wordline metal 146c comprises tungsten (W). In other embodiments, the wordline metal 146c comprises ruthenium (Ru). In one or more embodiments, the wordline 146 comprises one or more of a metal, a metal nitride, a conductive metal compound, and a semiconductor material. The metal can be selected from one or more of tungsten (W), molybdenum (Mo), tantalum (Ta), niobium (Nb), osmium (Os), zirconium (Zr), iridium (Ir), rhenium (Re), or titanium (Ti). The metal nitride may be selected from one or more of titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), molybdenum nitride (MoN), and zirconium nitride (ZrN). The conductive metal compound may be selected from one or more of tungsten oxide (WOx), ruthenium oxide (RuOx), and iridium oxide (IrOx). The semiconductor material may be selected from one or more of silicon (Si), silicon germanium (SiGe), and germanium (Ge).

[0056] 20 illustrates operation 80 of method 10, in which slits 138 are filled with an insulator material 150. The insulator material 150 may be any suitable material known to one of ordinary skill in the art. In one or more embodiments, the filled slits 138 include an insulator material 150 selected from one or more of silicon oxide, silicon nitride, and silicon oxynitride. In one or more embodiments, the insulator material 150 is silicon oxide.

[0057] 21 illustrates act 85 of method 10, in which bitline pad stud 152 is formed. Bitline stud 152 may be formed by any suitable means known to those of skill in the art.

[0058] 22 illustrates operation 90 of method 10 in which a wordline (W / L) contact is formed. The wordline contact 225 extends through the memory stack 130 a sufficient distance to terminate at one of the wordlines. In one or more embodiments, the wordline contact 225 may comprise any suitable material known to one of ordinary skill in the art. In one or more embodiments, the wordline contact 225 comprises one or more of a metal, a metal silicide, polysilicon, amorphous silicon, or EPI silicon. In one or more embodiments, the wordline contact 225 is doped with either an N-type dopant or a P-type dopant to reduce contact resistance. In one or more embodiments, the metal of the wordline contacts 225 is selected from one or more of copper (Cu), cobalt (Co), tungsten (W), titanium (Ti), molybdenum (Mo), nickel (Ni), ruthenium (Ru), silver (Ag), gold (Au), iridium (Ir), tantalum (Ta), or platinum (Pt).

[0059] 23 illustrates a perspective view of an electronic device 100 according to one or more embodiments. In one or more embodiments, the semiconductor memory device 100 includes at least one drain select gate (SGD) 112 on a memory stack 130 on a substrate 102, the memory stack 130 including alternating word lines 146 and a dielectric material (first layer 108); at least one drain select gate (SGD) transistor 202 in a first vertical hole extending through the memory stack, the drain select gate (SGD) transistor 202 including a first gate material 112; and at least one memory transistor 204 in a second vertical hole extending through the memory stack, the memory transistor 204 including a second gate material 136 different from the first gate material 112. In some embodiments, the first gate material 112 includes a gate-all-around (GAA) gate.

[0060] In another embodiment, a method of forming a semiconductor device is provided. The semiconductor device can have a three-dimensional vertical memory string including a drain select gate (SGD) transistor and a memory transistor. In one or more embodiments, the method of forming the semiconductor device includes forming a drain select gate (SGD) gate on a top surface of a memory stack, the memory stack including alternating first and second layers on a substrate; forming a memory string, the memory string extending through the drain select gate (SGD) gate and the memory stack; forming a bit line pad on a top surface of the memory string; forming a self-aligned mask on a top surface of the bit line pad; forming a first opening in the drain select gate (SGD) gate; filling the first opening with a dielectric material; forming a slit extending from a top surface of the drain select gate (SGD) gate through the memory stack to the substrate; removing the first layer to form a second opening; and forming a word line in the second opening.

[0061] An additional embodiment of the present disclosure is directed to a processing tool 900 for forming the memory devices and methods described, as shown in FIG.

[0062] The cluster tool 900 includes at least one central transfer station 921, 931 with multiple sides. Robots 925, 935 are positioned within the central transfer stations 921, 931 and configured to move a robot blade and a wafer to each of the multiple sides.

[0063] The cluster tool 900 includes multiple processing chambers 902, 904, 906, 908, 910, 912, 914, 916, and 918, also referred to as processing stations, connected to a central transfer station. The various processing chambers provide separate processing regions isolated from adjacent processing stations. The processing chambers may be any suitable chamber, including, but not limited to, a pre-clean chamber, a buffer chamber, a transfer space(s), a wafer orienter / degassing chamber, a cryo cooling chamber, a deposition chamber, an annealing chamber, an etching chamber, a selective oxidation chamber, an oxide layer thinning chamber, or a word line deposition chamber. The particular arrangement of processing chambers and components may vary depending on the cluster tool and should not be construed as limiting the scope of the present disclosure.

[0064] In some embodiments, the cluster tool 900 includes a select gate for drain (SGD) patterning chamber, which in some embodiments includes one or more selective etch chambers.

[0065] 24, a factory interface 950 is connected to the front of the cluster tool 900. The factory interface 950 includes a loading chamber 954 and an unloading chamber 956 on the front side 951 of the factory interface 950. Although the loading chamber 954 is shown on the left and the unloading chamber 956 is shown on the right, one of ordinary skill in the art will understand that this is merely representative of one possible configuration.

[0066] The size and shape of the loading chamber 954 and the unloading chamber 956 can vary depending on, for example, the substrate being processed in the cluster tool 900. In the embodiment shown, the loading chamber 954 and the unloading chamber 956 are sized to hold a wafer cassette with multiple wafers positioned within the cassette.

[0067] The robot 952 is in the factory interface 950 and can move between a loading chamber 954 and an unloading chamber 956. The robot 952 can transfer wafers from a cassette in the loading chamber 954 to a load lock chamber 960 through the factory interface 950. The robot 952 can also transfer wafers from a load lock chamber 962 to a cassette in the unloading chamber 956 through the factory interface 950. As will be appreciated by those skilled in the art, the factory interface 950 can have multiple robots 952. For example, the factory interface 950 can have a first robot that transfers wafers between the loading chamber 954 and the load lock chamber 960, as well as a second robot that transfers wafers between the load lock 962 and the unloading chamber 956.

[0068] The illustrated cluster tool 900 has a first section 920 and a second section 930. The first section 920 is connected to a factory interface 950 via load lock chambers 960, 962. The first section 920 includes a first transfer chamber 921 with at least one robot 925 positioned therein. The robot 925 is also referred to as a robotic wafer transport mechanism. The first transfer chamber 921 is centrally located with respect to the load lock chambers 960, 962, the processing chambers 902, 904, 916, 918, and the buffer chambers 922, 924. The robot 925 in some embodiments is a multi-arm robot capable of independently moving multiple wafers at a time. In some embodiments, the first transfer chamber 921 includes multiple robotic wafer transfer mechanisms. The robot 925 in the first transfer chamber 921 is configured to move wafers between chambers around the first transfer chamber 921. Individual wafers are carried on a wafer transport blade located at the distal end of the first robotic mechanism.

[0069] After processing the wafer in the first section 920, the wafer can be passed to the second section 930 via a pass-through chamber. For example, the chambers 922, 924 can be one-way or two-way pass-through chambers. The pass-through chambers 922, 924 can be used, for example, to cryo-cool the wafer before processing in the second section 930 or to allow for cooling or post-processing of the wafer before returning to the first section 920.

[0070] The system controller 990 communicates with the first robot 925, the second robot 935, the first plurality of processing chambers 902, 904, 916, 918, and the second plurality of processing chambers 906, 908, 910, 912, 914. The system controller 990 may be any suitable component capable of controlling the processing chambers and robots. For example, the system controller 990 may be a computer including a central processing unit, memory, suitable circuits and storage.

[0071] The processes can generally be stored in the memory of the system controller 990 as software routines that, when executed by a processor, cause the processing chamber to perform the processes of the present disclosure. The software routines can also be stored and / or executed by a second processor (not shown) that is remotely located from the hardware being controlled by the processor. Some or all of the methods of the present disclosure can also be performed in hardware. Thus, the processes can be implemented in software and can also be performed using, for example, a computer system in hardware, as an application specific integrated circuit or other type of hardware implementation, or a combination of software and hardware. The software routines, when executed by a processor, transform a general-purpose computer into an application specific computer (controller) that controls the operation of the chamber to perform the processes.

[0072] In one or more embodiments, the processing tool includes a central transfer station including a robot configured to move the wafer; a plurality of processing stations, each processing station connected to the central transfer station and providing a processing region isolated from the processing regions of adjacent processing stations, including a chamber for patterning a select gate for drain (SGD); and a controller connected to the central transfer station and the plurality of processing stations, configured to activate the robot to move the wafer between the processing stations and to control the processing performed at each of the processing stations.

[0073] One or more embodiments provide a non-transitory computer-readable medium that includes instructions, when executed by a controller of a processing chamber, that cause the processing chamber to perform operations of forming a first opening in a memory stack including alternating first and second layers on a substrate; recessing the second layer through the first opening to form a first recessed region; forming a select gate for drain (SGD) isolation in the first opening and in the first recessed region; forming a memory string through the memory stack; forming a slit extending from a top surface of the memory stack to the substrate; removing the second layer to form a second opening; and filling the second opening and the slit with an insulating material.

[0074] The use of the terms "a" and "an" and "the" and similar referents in the context of describing the materials and methods discussed herein (especially in the context of the claims below) should be construed to cover both the singular and the plural, unless otherwise stated herein or clearly contradicted by context. The recitation of ranges of values ​​herein is merely intended to serve as a shorthand method of individually referring to each individual value falling within the range, unless otherwise stated herein, and each individual value is incorporated herein as if set forth individually herein. All methods described herein can be performed in any suitable order, unless otherwise indicated herein or clearly contradicted by context. The use of any and all examples, or exemplary language (e.g., "etc.") provided herein is intended merely to better illuminate the materials and methods, and does not impose limitations on the scope of the claims unless otherwise specified. No language in the specification should be construed as indicating any non-claimed element as essential to the practice of the disclosed materials and methods.

[0075] References throughout this specification to "one embodiment," "a particular embodiment," "one or more embodiments," or "an embodiment" mean that a particular feature, structure, material, or characteristic described in connection with an embodiment is included in at least one embodiment of the disclosure. Thus, the appearances of the phrases "in one or more embodiments," "in an embodiment," "in one embodiment," or "in an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment of the disclosure. Furthermore, the particular features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments.

[0076] Although the disclosure of this specification has been described with reference to specific embodiments, it should be understood that these embodiments are merely illustrative of the principles and applications of the disclosure. It will be apparent to those skilled in the art that various modifications and variations can be made to the disclosed method and apparatus without departing from the spirit and scope of the disclosure. Therefore, the disclosure is intended to cover modifications and variations that come within the scope of the appended claims and their equivalents.

Claims

1. In a semiconductor memory device, At least one select gate for drain (SGD) on a memory stack on a substrate, the memory stack including alternating word lines and dielectric material; at least one select gate for drain (SGD) transistor in a first vertical hole extending through the memory stack, the at least one select gate for drain (SGD) transistor comprising a first gate material; at least one memory transistor in a second vertical hole extending through the memory stack, the at least one memory transistor comprising a second gate material different from the first gate material; a bit line pad on the drain side of the select gate for drain (SGD) transistor; and Self-aligned mask on the bitline pads 1. A semiconductor memory device comprising:

2. 2. The semiconductor memory device of claim 1, wherein the at least one select gate for drain (SGD) transistor further comprises a first gate dielectric, and the at least one memory transistor comprises a second gate dielectric, the first gate dielectric and the second gate dielectric comprising the same material.

3. 2. The semiconductor memory device of claim 1, wherein the select gate for drain (SGD) transistor and the memory transistor independently comprise one or more transistor layers selected from aluminum oxide (AlO), a blocking oxide, a trapping material, a tunnel oxide, and a channel material.

4. 3. The semiconductor memory device of claim 2, wherein the first gate material is a gate-all-around (GAA) gate.

5. 2. The semiconductor memory device of claim 1, wherein the self-aligned mask comprises one or more of silicon nitride (SiN), aluminum oxide (AlO), hafnium oxide (HfO), a refractory metal, a refractory metal silicide, a refractory metal oxide, titanium nitride (TiN), tungsten (W), molybdenum (Mo), tantalum (Ta), tantalum nitride (TaN), ruthenium (Ru), platinum (Pt), and osmium (Os).

6. 10. The semiconductor memory device of claim 1, wherein the wordlines comprise one or more of a metal, a metal nitride, a conductive metal compound, and a semiconductor material.

7. 7. The semiconductor memory device of claim 6, wherein the metal is selected from one or more of tungsten (W), molybdenum (Mo), tantalum (Ta), niobium (Nb), osmium (Os), zirconium (Zr), iridium (Ir), rhenium (Re), or titanium (Ti), and the metal nitride is selected from one or more of titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), molybdenum nitride (MoN), and zirconium nitride (ZrN).

8. 7. The semiconductor memory device of claim 6, wherein the conductive metal compound is selected from one or more of tungsten oxide (WOx), ruthenium oxide (RuOx), and iridium oxide (IrOx).

9. 7. The semiconductor memory device of claim 6, wherein the semiconductor material is selected from one or more of silicon (Si), silicon germanium (SiGe), and germanium (Ge).

10. 2. The semiconductor memory device of claim 1, further comprising at least one filled slit extending through said memory stack adjacent to said at least one select gate for drain (SGD) transistor.

11. 11. The semiconductor memory device of claim 10, wherein the filled slits comprise an insulator material selected from one or more of silicon oxide, silicon nitride, and silicon oxynitride.

12. The semiconductor memory device of claim 1, wherein the common source line comprises a polysilicon layer on the substrate.

13. In a semiconductor memory device, At least one select gate for drain (SGD) on a memory stack on a substrate, the memory stack including alternating word lines and dielectric material; a vertical string extending through the memory stack, the vertical string including at least one SGD transistor and at least one memory transistor; a bit line pad on a top surface of the vertical string, the bit line pad having a first size; and a self-aligned mask layer on top of the bit line pad, the self-aligned mask layer having a second size between 1 nm and 50 nm larger than the first size.

1. A semiconductor memory device comprising:

14. 14. The semiconductor memory device of claim 13, wherein the self-aligned mask comprises one or more of silicon nitride (SiN), aluminum oxide (AlO), hafnium oxide (HfO), a refractory metal, a refractory metal silicide, a refractory metal oxide, titanium nitride (TiN), tungsten (W), molybdenum (Mo), tantalum (Ta), tantalum nitride (TaN), ruthenium (Ru), platinum (Pt), and osmium (Os).

15. 1. A method for forming a semiconductor memory device having a three-dimensional vertical memory string including a select gate for drain (SGD) transistor and a memory transistor, comprising: forming a select gate for drain (SGD) gate on a top surface of a memory stack, the memory stack including alternating first and second layers on a substrate; forming a memory string extending through the gate of the select gate for drain (SGD) and the memory stack; forming bit line pads on a top surface of the memory strings; forming a self-aligned mask on top of the bit line pads; forming a first opening in the gate of the drain select gate (SGD); filling the first opening with a dielectric material; forming a slit extending from an upper surface of the gate of the drain select gate (SGD) through the memory stack to the substrate; removing the first layer to form a second opening; and forming a word line in the second opening; A method comprising:

16. forming the memory string, patterning a memory hole extending from a top surface of the gate of the select gate for drain (SGD) through the memory stack to a bottom surface of the substrate; and depositing a transistor layer in the memory hole, the transistor layer including one or more of an aluminum oxide (AlO) layer, a blocking oxide layer, a trapping layer, a tunnel oxide layer, and a channel layer; 16. The method of claim 15, comprising:

17. 16. The method of claim 15, wherein the self-aligned mask has a thickness in the range of 1 nm to 100 nm, and wherein the self-aligned mask overhangs the bitline pad by an amount in the range of 1 nm to 50 nm.

18. 16. The method of claim 15, wherein the substrate is a common source line including a sacrificial layer, an oxide layer, and a polysilicon layer, the method further comprising removing the sacrificial layer from the common source line to form a common source opening.

19. The method of claim 15 further comprising forming a wordline contact.

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