Semiconductor Device

Abstract

To provide, for example, a semiconductor device with a new structure.SOLUTION: A semiconductor device includes: a first wiring; a second wiring; a third wiring; a fourth wiring; a first transistor having a first gate electrode, a first source electrode, and a first drain electrode; and a second transistor having a second gate electrode, a second source electrode, and a second drain electrode. The first transistor is provided over a substrate containing a semiconductor material. The second transistor includes an oxide semiconductor layer.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The disclosed invention relates to a semiconductor device using a semiconductor element and a manufacturing method thereof. do. [Background technology]

[0002] Memory devices that use semiconductor elements are volatile, meaning that the stored contents are lost when the power supply is cut off. They are broadly divided into volatile types, which retain their memory contents even if the power supply is cut off, and non-volatile types, which retain their memory contents even if the power supply is cut off. .

[0003] A typical example of a volatile memory device is a DRAM (Dynamic Random Access Memory). DRAM is a memory element that can be selected from the transistors. By storing charge in the capacitor, information is stored.

[0004] From the above principle, in DRAM, when information is read, the charge in the capacitor is lost. Therefore, every time data is read, a write operation is required again. The transistors that make up the transistors have leakage currents, and even when they are not selected, charge flows out. Therefore, the data retention period is short. This requires a refresh operation, making it difficult to sufficiently reduce power consumption. In addition, since memory contents are lost when the power supply is cut off, magnetic materials are necessary for long-term memory retention. Therefore, alternative storage devices using optical and optical materials are required.

[0005] Another example of a volatile memory device is SRAM (Static Random Access Memory). SRAM uses circuits such as flip-flops to store data. No refresh operation is required to retain data, which is an advantage over DRAM. However, because it uses circuits such as flip-flops, the cost per unit of memory capacity is high. In addition, if the power supply is cut off, the memory contents are lost. In this regard, there is no difference with DRAM.

[0006] A typical example of a non-volatile memory device is a flash memory. A floating gate is provided between the gate electrode of the transistor and the channel forming region, Since memory is stored by holding an electric charge in the floating gate, the data is retained for an extremely long period of time. The advantage is that it lasts a very long time (semi-permanent) and does not require the refresh operations required for volatile storage devices. For example, see Patent Document 1.

[0007] However, the gate insulating layer that constitutes the memory element is damaged by the tunnel current that occurs during writing. This causes a problem that the memory element may become non-functional after a certain number of writes. In order to alleviate the effect of this problem, for example, the number of write operations to each memory element is made uniform. However, to achieve this, complex peripheral circuits are required. However, even if such a method is adopted, the fundamental problem of life span is not solved. Therefore, flash memory is not suitable for applications where information needs to be rewritten frequently.

[0008] Also, to hold charge on the floating gate or to remove that charge. High voltages are required to maintain or remove the charge. There is also the problem that it takes time to write and erase data, and it is not easy to speed up the writing and erasing operations. [Prior art documents] [Patent documents]

[0009] [Patent Document 1] Japanese Patent Publication No. 57-105889 Summary of the Invention [Problem to be solved by the invention]

[0010] In view of the above problems, one embodiment of the disclosed invention provides a method for storing stored contents even when power is not supplied. To provide a semiconductor device having a new structure capable of retaining data and having no limit on the number of times it can be written. One of the objectives of the organization is to [Means for solving the problem]

[0011] One embodiment of the present invention is a transistor formed using an oxide semiconductor and a transistor formed using another material. The present invention relates to a semiconductor device having a stacked structure with a transistor formed using the above-mentioned method. For example, Such a configuration can be adopted.

[0012] One aspect of the present invention is a semiconductor device including a first wiring, a second wiring, a third wiring, a fourth wiring, and a fifth wiring. A plurality of memory elements are connected in parallel between the first wiring and the second wiring. Each of the plurality of memory elements includes a first gate electrode, a first source electrode, and a first drain electrode. a first transistor having a gate electrode, a second gate electrode, a second source electrode, and a second a second transistor having a second drain electrode, a third gate electrode, and a third source electrode; and a third transistor having a third drain electrode, The first transistor is provided over a substrate including a semiconductor material, and the second transistor includes an oxide semiconductor layer. The first gate electrode and one of the second source electrode and the second drain electrode are The first wiring and the first source electrode are electrically connected to each other. The drain electrode and the third source electrode are electrically connected, and the second wiring and the third drain The third wiring is electrically connected to the second source electrode or the second drain electrode. The fourth wiring and the second gate electrode are electrically connected to each other. The semiconductor device is electrically connected to the fifth wiring and the third gate electrode.

[0013] In addition, one aspect of the present invention is a semiconductor device including a first wiring, a second wiring, a third wiring, and a fourth wiring, and a fifth wiring, and a plurality of memory elements are connected in parallel between the first wiring and the second wiring. Each of the plurality of memory elements includes a first gate electrode, a first source electrode, and a first A first transistor having a drain electrode, a second gate electrode, a second source electrode, and a second transistor having a first drain electrode and a second drain electrode; and a capacitance element. The first transistor is provided over a substrate including a semiconductor material, and the second transistor is provided over an oxide semiconductor layer. The first gate electrode and the second source electrode or the second drain electrode are configured to include One of the electrodes of the capacitor is electrically connected to the first wiring and the first source electrode are electrically connected to each other, and the second wiring and the first drain electrode are electrically connected to each other, The third wiring and the other of the second source electrode and the second drain electrode are electrically connected. The fourth wiring and the second gate electrode are electrically connected to each other, and the fifth wiring and the capacitance element The other electrode of the semiconductor device is electrically connected to the other electrode of the semiconductor device.

[0014] In the above, the first transistor is a channel forming transistor provided in a substrate including a semiconductor material. a region, impurity regions provided so as to sandwich the channel forming region, and a region A first gate insulating layer, a first gate electrode on the first gate insulating layer, and an impurity region and an electric and a first source electrode and a first drain electrode electrically connected to the first source electrode.

[0015] In the above, the second transistor has a second gate electrode on a substrate including a semiconductor material. a second gate insulating layer on the second gate electrode; and an oxide semiconductor layer on the second gate insulating layer. a second source electrode and a second drain electrode electrically connected to the oxide semiconductor layer; And, it has.

[0016] In the above, the third transistor is a channel transistor provided in a substrate including a semiconductor material. A dopant region is provided between the dopant regions and the channel region. a third gate insulating layer on the impurity region; a third gate electrode on the third gate insulating layer; and and a third source electrode and a third drain electrode electrically connected to the first source electrode and the second drain electrode.

[0017] In the above, the substrate containing a semiconductor material is a single crystal semiconductor substrate or an SOI substrate. It is preferable to use a plate, and it is particularly preferable that the semiconductor material is silicon.

[0018] In the above, the oxide semiconductor layer is made of an In-Ga-Zn-O-based oxide semiconductor material. In particular, the oxide semiconductor layer preferably contains a crystal of In2Ga2ZnO7. In addition, the hydrogen concentration in the oxide semiconductor layer is preferably 5×10 19 / cm 3 In addition, the off-state current of the second transistor is preferably 1×10 -13 It is preferable to set it to A or less.

[0019] In the above, the second transistor is provided in a region overlapping with the first transistor. The configuration can be as follows.

[0020] In this specification, the terms "above" and "below" refer to the positional relationship of components "directly above" or "below." For example, "the first gate on the gate insulating layer" is not limited to "directly under" the gate insulating layer. If the expression "gate electrode" is used, it means that other components are included between the gate insulating layer and the gate electrode. In addition, the terms "upper" and "lower" are merely used for the convenience of explanation, Unless otherwise stated, this also includes reversed versions.

[0021] In addition, the terms "electrode" and "wiring" used in this specification and the like do not limit the functionality of these components. For example, an "electrode" may be used as part of a "wire." In addition, the term "electrode" or "wiring" may be used to refer to the plural "electrodes" or "wirings". This also includes cases where the "line" is formed as an integral part.

[0022] In addition, the functions of the "source" and "drain" may differ depending on whether transistors of different polarities are used or not. However, they may be swapped when the direction of the current changes during circuit operation. In this specification and the like, the terms "source" and "drain" may be used interchangeably. It is possible.

[0023] In this specification, "electrically connected" means "something that has some kind of electrical effect" " includes cases where the device is connected via "anything that has some electrical effect." " is not subject to any particular restriction as long as it enables the transmission and reception of electrical signals between the connection objects.

[0024] For example, "something that has some kind of electrical effect" includes not only electrodes and wiring, but also transistors. Switching elements such as transistors, resistors, inductors, capacitors, and other various devices This includes elements having functions such as:

[0025] In general, an "SOI substrate" is a substrate that has a silicon semiconductor layer on an insulating surface. However, in this specification and the like, a semiconductor layer made of a material other than silicon is provided on an insulating surface. In other words, the semiconductor that "SOI substrate" has is The layer is not limited to a silicon semiconductor layer. Also, the substrate in the "SOI substrate" is a silicon Not only semiconductor substrates such as silicon wafers, but also glass substrates, quartz substrates, sapphire substrates, metal substrates This also includes non-semiconductor substrates such as semiconductor layers on conductive or insulating substrates. In addition, in this specification, etc., the term "SOI substrate" includes those having a "Solid substrate" does not only refer to a substrate made of semiconductor material, but also to any substrate that contains semiconductor material. In other words, in this specification, the term "SOI substrate" is also broadly used to refer to a "semiconductor substrate." Included in. Effect of the Invention

[0026] In one embodiment of the present invention, a transistor using a material other than an oxide semiconductor is provided in a lower portion, A semiconductor device including a transistor including an oxide semiconductor is provided.

[0027] Since a transistor using an oxide semiconductor has an extremely low off-state current, It is possible to retain the memory contents for a much longer period of time. This eliminates the need for refresh operations or makes it possible to reduce the frequency of refresh operations to an extremely low level. Therefore, power consumption can be sufficiently reduced. It is possible to retain the stored contents for a long period of time.

[0028] In addition, high voltage is not required to write information, and there is no problem of element deterioration. Information is written depending on the on / off state of the transistor, allowing for high-speed operation. This can be easily achieved. Another advantage is that no action is required to erase the information. .

[0029] In addition, transistors using materials other than oxide semiconductors can operate at sufficiently high speed. By using this, it is possible to read out the stored contents at high speed.

[0030] In this way, transistors using materials other than oxide semiconductors and transistors using oxide semiconductors By integrating a transistor, a semiconductor device with unprecedented features can be realized. It is possible. [Brief description of the drawings]

[0031] [Figure 1] FIG. 1 is a circuit diagram illustrating a semiconductor device. [Diagram 2] 1A and 1B are a cross-sectional view and a plan view illustrating a semiconductor device. [Diagram 3] 1A to 1C are cross-sectional views illustrating a manufacturing process of a semiconductor device. [Figure 4] 1A to 1C are cross-sectional views illustrating a manufacturing process of a semiconductor device. [Diagram 5] 1A to 1C are cross-sectional views illustrating a manufacturing process of a semiconductor device. [Figure 6]1 is a cross-sectional view illustrating a semiconductor device. [Figure 7] 1 is a cross-sectional view illustrating a semiconductor device. [Figure 8] 1 is a cross-sectional view illustrating a semiconductor device. [Figure 9] 1 is a cross-sectional view illustrating a semiconductor device. [Figure 10] FIG. 1 is a circuit diagram illustrating a memory element. [Figure 11] 4 is a timing chart illustrating the operation of a memory element. [Figure 12] FIG. 1 is a circuit diagram illustrating a semiconductor device. [Figure 13] FIG. 1 is a circuit diagram illustrating a memory element. [Figure 14] FIG. 1 is a circuit diagram illustrating a semiconductor device. [Figure 15] FIG. 1 is a circuit diagram illustrating a memory element. [Figure 16] FIG. 13 is a diagram showing the relationship between a node A and a fifth wiring potential. [Figure 17] FIG. 1 is a circuit diagram illustrating a semiconductor device. [Figure 18] FIG. 1 is a circuit diagram illustrating a memory element. [Figure 19] FIG. 1 is a circuit diagram illustrating a semiconductor device. [Figure 20] FIG. 1 is a circuit diagram illustrating a memory element. [Figure 21] FIG. 1 is a circuit diagram illustrating a memory element. [Figure 22] FIG. 4 is a circuit diagram illustrating a readout circuit. [Figure 23] 1A to 1C are diagrams for explaining electronic devices. [Figure 24] FIG. 13 is a cross-sectional view of an inverted staggered transistor including an oxide semiconductor. [Diagram 25] FIG. 25 is an energy band diagram (schematic diagram) taken along the line A-A' of FIG. 24. [Figure 26] (A) shows the state when a positive potential (+VG) is applied to the gate (G1), and (B) shows the state when a negative potential (-VG) is applied to the gate (G1). [Figure 27]A diagram showing the relationship between the vacuum level, the work function of a metal (φM), and the electron affinity of an oxide semiconductor (χ). DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0032] An embodiment of the present invention will be described below with reference to the drawings. The present invention is not limited to the above description, and may be modified in various forms and without departing from the spirit and scope of the present invention. It will be readily understood by those skilled in the art that various modifications may be made to the details. The present invention should not be construed as being limited to the description of the embodiment shown in the accompanying drawings.

[0033] In addition, the position, size, range, etc. of each component shown in the drawings are not necessarily the same as in the actual embodiment, for ease of understanding. Therefore, the actual position, size, range, etc. of the product may not necessarily be the same as those shown in the drawings, etc. There is no limitation to the position, size, range, etc. shown.

[0034] In this specification, ordinal numbers such as "first," "second," and "third" are used to avoid confusion of components. It should be noted that the numbers are added to avoid confusion and are not intended to be limiting.

[0035] (Embodiment 1) In this embodiment, a structure and a manufacturing method of a semiconductor device according to one embodiment of the disclosed invention will be described. This will be described with reference to FIGS.

[0036] <Circuit configuration of semiconductor device> FIG. 1 shows an example of a circuit configuration of a semiconductor device. The transistor 160 is made of a material and the transistor 162 is made of an oxide semiconductor. It is done.

[0037] Here, the gate electrode of transistor 160 and the source electrode or drain of transistor 162 are The first line (1st Line) is electrically connected to one of the drain electrodes. The second line (also called a source line) and the source electrode of the transistor 160 are electrically connected to each other. The wiring (2nd Line: also called bit line) and the drain electrode of the transistor 160 are electrically connected. A third wiring (3rd Line: also called the first signal line) The other of the source electrode and the drain electrode of the transistor 162 is electrically connected to A fourth wiring (also called a second signal line) and the transistor 162 It is electrically connected to the gate electrode.

[0038] The transistor 160 using a material other than an oxide semiconductor can operate at sufficiently high speed. By using this, it is possible to read out the stored contents at high speed. The transistor 162 including an oxide semiconductor has an extremely low off-state current. Therefore, when the transistor 162 is turned off, the transistor 160 It is possible to hold the potential of the gate electrode for an extremely long period of time.

[0039] By utilizing the feature that the potential of the gate electrode can be maintained, information can be written, It is possible to store and read the information.

[0040] First, the writing and holding of information will be explained. The transistor 162 is turned on by applying a potential that turns on the transistor 162 . As a result, the potential of the third wiring is applied to the gate electrode of the transistor 160 (write After that, the potential of the fourth wiring is set to a potential at which the transistor 162 is turned off. By turning off the transistor 162, the gate electrode of the transistor 160 The potential is maintained (retained).

[0041] Since the off-state current of the transistor 162 is extremely small, the gate electrode of the transistor 160 The potential is maintained for a long period of time. For example, if the potential of the gate electrode of transistor 160 is If the potential is such that the transistor 160 is turned on, the transistor 160 will remain on for a long time. The potential of the gate electrode of the transistor 160 is maintained for a certain period of time. If the potential is such that the transistor 160 is turned off, the transistor 160 will remain in the off state for a long time. is retained over time.

[0042] Next, the reading of information will be described. As described above, when the transistor 160 is in the on state, Alternatively, when the off state is maintained, a predetermined potential (low potential) is applied to the first wiring. When the transistor 160 is turned on, the potential of the second wiring changes depending on whether the transistor 160 is turned on or off. For example, when the transistor 160 is on, the potential of the first wiring is On the other hand, the potential of the second wiring is decreased. In this case, the potential of the second wiring does not change.

[0043] In this manner, in a state in which the information is held, the potential of the second wiring is compared with a predetermined potential. This allows the information to be read out.

[0044] Next, the rewriting of information will be described. The rewriting of information includes the above-mentioned writing of information and That is, the potential of the fourth wiring is held in the same manner as when the transistor 162 is turned on. This causes the transistor 162 to be turned on. (a potential related to new information) is applied to the gate electrode of transistor 160. Then, The potential of the fourth wiring is set to a potential at which the transistor 162 is turned off. By turning off 62, the new information is held.

[0045] In this way, the semiconductor device according to the disclosed invention can directly read data by rewriting the data. It is possible to rewrite information. This is why it is necessary for flash memory etc. This eliminates the need for an erase operation, and makes it possible to suppress a decrease in operation speed caused by the erase operation. That is, high speed operation of the semiconductor device is achieved.

[0046] The above explanation is for n-type transistors (n-channel transistors) in which electrons are the majority carriers. This is about using a large number of positive hole-causing transistors instead of n-type transistors. It goes without saying that a p-type transistor can be used as the carrier.

[0047] <Plane and cross-sectional configurations of semiconductor device> FIG. 2 shows an example of the configuration of the semiconductor device. FIG. 2(A) shows a cross section of the semiconductor device. 2(B) shows a plan view of the semiconductor device. These correspond to the cross sections taken along lines A1-A2 and B1-B2 in FIG. 2(A) and FIG. 2(B). The semiconductor device shown in FIG. 1 has a transistor 160 using a material other than an oxide semiconductor in the lower portion. The transistor 162 includes an oxide semiconductor in the upper portion. Transistor 160 and transistor 162 are both described as n-type transistors. However, a p-type transistor may be used. In particular, the transistor 160 is preferably a p-type transistor. It is easy to do so.

[0048] The transistor 160 includes a channel forming region 11 provided in a substrate 100 including a semiconductor material. 6, and the impurity region 114 and the high concentration impurity region 115 are provided so as to sandwich the channel forming region 116. A pure region 120 (collectively referred to as an impurity region) and a channel forming region 11 6, and a gate insulating layer 108a provided on the gate insulating layer 108a. The electrode 110a and the source or drain electrode 111 electrically connected to the impurity region 114 30a, and has a source or drain electrode 130b.

[0049] Here, a sidewall insulating layer 118 is provided on the side surface of the gate electrode 110a. In addition, in the region of the substrate 100 that does not overlap with the sidewall insulating layer 118 in a cross-sectional view, A high-concentration impurity region 120 is provided, and a metal compound region 124 is provided on the high-concentration impurity region 120. In addition, an element isolation insulating layer 10 is formed on the substrate 100 so as to surround the transistor 160. 6 is provided, and an interlayer insulating layer 126 and an interlayer insulating film 128 are provided to cover the transistor 160. An edge layer 128 is provided. A source or drain electrode 130a, a source or drain electrode The drain electrode 130b is formed through an opening formed in the interlayer insulating layer 126 and the interlayer insulating layer 128. That is, the source electrode or the metal compound region 124 is electrically connected to the source electrode or the metal compound region 124 through the The drain electrode 130a and the source or drain electrode 130b are formed on the metal compound region 12. 4, it is electrically connected to the high concentration impurity region 120 and the impurity region 114. The gate electrode 110a is provided with a source or drain electrode 130a and a source or drain electrode 130b. Alternatively, an electrode 130c provided similarly to the drain electrode 130b is electrically connected.

[0050] The transistor 162 includes a gate electrode 136d provided on the interlayer insulating layer 128 and a gate A gate insulating layer 138 is provided on the electrode 136d. An oxide semiconductor layer 140 and a second insulating film provided on the oxide semiconductor layer 140. A source electrode or drain electrode 142a, which is electrically connected to the source electrode or drain electrode 142b, and an in-electrode 142b.

[0051] Here, the gate electrode 136d is embedded in the insulating layer 132 formed on the interlayer insulating layer 128. In addition, like the gate electrode 136d, An electrode 136a is connected to the source or drain electrode 130b. An electrode 136b is formed in contact with the electrode 130c, and an electrode 136c is formed in contact with the electrode 130c.

[0052] In addition, a protective layer is provided on the transistor 162 so as to be in contact with part of the oxide semiconductor layer 140. An insulating layer 144 is provided, and an interlayer insulating layer 146 is provided on the protective insulating layer 144. Here, the protective insulating layer 144 and the interlayer insulating layer 146 are provided with a source electrode or a drain electrode. The openings reach the source electrode 142a and the source or drain electrode 142b. Through the opening, the electrode 150d and the electrode 150e are connected to the source electrode or the drain electrode. The electrode 142a is formed in contact with the source electrode or the drain electrode 142b. As well as the electrode 150d and the electrode 150e, the gate insulating layer 138, the protective insulating layer 144, the interlayer insulating The layer 146 is provided with openings through which the electrodes 136a, 136b, and 136c are in contact. Electrodes 150a, 150b, and 150c are formed.

[0053] Here, impurities such as hydrogen are sufficiently removed from the oxide semiconductor layer 140, and the oxide semiconductor layer 140 is highly purified. Specifically, the hydrogen concentration in the oxide semiconductor layer 140 is preferably 5×10 19 / cm 3 Less than 5×10 18 / cm 3 Less than or equal to 5×10 17 / cm 3 In addition, the hydrogen concentration in the oxide semiconductor layer is sufficiently reduced and the oxide semiconductor layer is highly purified. At 140, the carrier concentration is 5×10 14 / cm 3 Less than 5×10 12 / cm 3 In this way, the hydrogen concentration is sufficiently reduced and the hydrogen is highly purified, and the hydrogen is converted into i-type or By using a qualitatively i-type oxide semiconductor, a transistor with extremely excellent off-state current characteristics can be obtained. For example, when the drain voltage Vd is +1 V or +10 V, In this case, when the gate voltage Vg is in the range of -5V to -20V, the off-state current is 1×10 -1 3 In this way, the hydrogen concentration is sufficiently reduced and the oxide semiconductor is highly purified. By applying the layer 140 and reducing the off-state current of the transistor 162, The semiconductor device can be realized. Note that the hydrogen concentration in the oxide semiconductor layer 140 is , Secondary Ion Mass Spectrometry (SIMS) The measurements were made using a quartz-transducer spectroscopy (QTOS).

[0054] An insulating layer 152 is provided on the interlayer insulating layer 146, and a buried insulating film is formed in the insulating layer 152. Electrodes 154a, 154b, 154c, and 154d are provided so that the electrodes 154a, 154b, 154c, and 154d are inserted into the Here, electrode 154a is in contact with electrode 150a, and electrode 154b is in contact with electrode 150. b, electrode 154c is in contact with electrode 150c and electrode 150d, and electrode 1 54d is in contact with electrode 150e.

[0055] That is, in the semiconductor device shown in FIG. 2, the gate electrode 110a of the transistor 160 and The source or drain electrode 142a of the transistor 162 is connected to the electrode 130c. 136c, the electrode 150c, the electrode 154c and the electrode 150d are electrically connected to each other. There are.

[0056] <Method for manufacturing semiconductor device> Next, an example of a method for manufacturing the above semiconductor device will be described. A method for fabricating the transistor 160 will be described with reference to FIG. A method for producing the heater 162 will be described with reference to FIGS.

[0057] <How to make the lower transistor> First, a substrate 100 containing a semiconductor material is prepared (see FIG. 3(A)). The plate 100 may be a single crystal semiconductor substrate such as silicon or silicon carbide, or a polycrystalline semiconductor substrate. Compound semiconductor substrates such as silicon germanium, SOI substrates, etc. can be used. Here, a single crystal silicon substrate is used as the substrate 100 containing a semiconductor material. In general, an "SOI substrate" is a substrate that has a silicon semiconductor on an insulating surface. A substrate having a conductor layer formed thereon is referred to as a substrate having a silicon layer formed on an insulating surface. The term "substrate" is used as a concept including a substrate having a semiconductor layer made of a material other than silicon. The semiconductor layer of the "SOI substrate" is not limited to a silicon semiconductor layer. The substrate is a structure in which a semiconductor layer is provided on an insulating substrate such as a glass substrate via an insulating layer. This includes the following:

[0058] A protective layer 102 is formed on the substrate 100 to serve as a mask for forming an element isolation insulating layer. (See FIG. 3(A)). The protective layer 102 is made of, for example, silicon oxide, silicon nitride, An insulating layer made of silicon oxynitride or the like can be used. In order to control the threshold voltage of a transistor, impurities that give n-type conductivity are used. The substrate 100 may be doped with an impurity element that imparts p-type conductivity or an impurity element that imparts p-type conductivity. In the case of silicon, impurities that give n-type conductivity are, for example, phosphorus or arsenic. In addition, examples of impurities that impart p-type conductivity include boron and aluminum. For example, nium, gallium, etc. can be used.

[0059] Next, etching is performed using the protective layer 102 as a mask to form a layer covered with the protective layer 102. The part of the substrate 100 in the unbonded area (exposed area) is removed. The semiconductor region 104 is formed by etching (see FIG. 3(B)). It is preferable to use etching, but wet etching may also be used. The etching gas and the etching solution can be appropriately selected depending on the material to be etched.

[0060] Next, an insulating layer is formed so as to cover the semiconductor region 104, and a region overlapping the semiconductor region 104 is The insulating layer is selectively removed to form an element isolation insulating layer 106 (see FIG. 3(B)). The insulating layer is formed using silicon oxide, silicon nitride, silicon nitride oxide, etc. Methods for removing the insulating layer include polishing such as CMP and etching. Either of them may be used. After the semiconductor region 104 is formed or after the element isolation insulation After the layer 106 is formed, the protective layer 102 is removed.

[0061] Next, an insulating layer is formed on the semiconductor region 104, and a layer containing a conductive material is formed on the insulating layer. do.

[0062] The insulating layer will later become the gate insulating layer and is obtained using a method such as CVD or sputtering. Silicon oxide, silicon nitride oxide, silicon nitride, hafnium oxide, aluminum oxide, etc. It is preferable to use a single layer or multilayer structure of a film containing aluminum, tantalum oxide, etc. The surface of the semiconductor region 104 is oxidized or nitrided by plasma treatment or thermal oxidation treatment. The insulating layer may be formed by the high density plasma treatment. It is performed using a mixture of rare gases such as e, oxygen, nitrogen oxide, ammonia, nitrogen, hydrogen, etc. The thickness of the insulating layer is not particularly limited, but may be, for example, 1 nm or more and 100 nm or less. m or less.

[0063] The layer containing a conductive material is a metal material such as aluminum, copper, titanium, tantalum, or tungsten. Also, the insulating layer can be formed using a semiconductor material such as polycrystalline silicon containing a conductive material. The method of formation is not particularly limited, and examples of the method include deposition, C Various film formation methods such as the VD method, the sputtering method, and the spin coating method can be used. In this embodiment, the layer containing a conductive material is formed using a metal material. The following information will be provided.

[0064] Thereafter, the insulating layer and the layer containing the conductive material are selectively etched to form the gate insulating layer 108. A gate electrode 110a is formed (see FIG. 3(C)).

[0065] Next, an insulating layer 112 is formed to cover the gate electrode 110a (see FIG. 3(C)). By doping the semiconductor region 104 with phosphorus (P) or arsenic (As), an impurity region with a shallow junction depth is formed. In this case, in order to form an n-type transistor, a region 114 is formed (see FIG. 3(C)). For this purpose, phosphorus or arsenic is added, but for p-type transistors, boron (B) or An impurity element such as aluminum (Al) may be added. As a result of this formation, a channel forming region 116 is formed below the gate insulating layer 108a of the semiconductor region 104. (See FIG. 3(C)). The concentration of the added impurity can be appropriately set. However, when semiconductor elements are highly miniaturized, it is desirable to increase the concentration. In this embodiment, the step of forming the impurity region 114 is performed after forming the insulating layer 112. However, it may be possible to form the insulating layer 112 after forming the impurity region 114. stomach.

[0066] Next, a sidewall insulating layer 118 is formed (see FIG. 3(D)). The layer 118 is formed by forming an insulating layer to cover the insulating layer 112 and then applying a highly anisotropic By applying a simple etching process, the film can be formed in a self-aligned manner. Then, the insulating layer 112 is partially etched to expose the upper surface of the gate electrode 110a and the impurity region It is advisable to expose the top surface of 114.

[0067] Next, a layer is formed so as to cover the gate electrode 110a, the impurity region 114, the sidewall insulating layer 118, etc. Then, phosphorus (P) or arsenic is doped in the region in contact with the impurity region 114. By doping arsenic (As) or the like, a high concentration impurity region 120 is formed (see FIG. 3(E)). Thereafter, the insulating layer is removed, and the gate electrode 110a, the sidewall insulating layer 118, and the high concentration impurity A metal layer 122 is formed so as to cover the pure region 120 and the like (see FIG. 3(E)). 122 is formed by various deposition methods such as vacuum deposition, sputtering, and spin coating. The metal layer 122 can be formed by reacting with the semiconductor material that constitutes the semiconductor region 104. It is preferable to form the metal layer using a metal material that forms a metal compound having low resistance. Metal materials include, for example, titanium, tantalum, tungsten, nickel, cobalt, and platinum. etc.

[0068] Next, a heat treatment is performed to react the metal layer 122 with the semiconductor material. A metal compound region 124 is formed in contact with the high concentration impurity region 120 (see FIG. 3(F)). When polycrystalline silicon or the like is used as the gate electrode 110a, the gate electrode 11 A metal compound region is also formed in the portion of 0a that contacts the metal layer 122.

[0069] The heat treatment may be, for example, a heat treatment by irradiation with a flash lamp. Of course, other heat treatment methods may be used, but the chemical reaction involved in the formation of metal compounds is In order to improve the controllability of the heat treatment, it is desirable to use a method that can realize a very short heat treatment. The metal compound region is preferably formed by a reaction between a metal material and a semiconductor material. The metal compound region is formed in the region, and the conductivity is sufficiently increased. This sufficiently reduces the electrical resistance and improves the device characteristics. After forming region 124, metal layer 122 is removed.

[0070] Next, an interlayer insulating layer 126 and an interlayer insulating layer 127 are formed to cover the respective components formed by the above-mentioned steps. The interlayer insulating layer 126 and the interlayer insulating layer 128 are formed by using silicon oxide. Silicon, silicon oxide nitride, silicon nitride, hafnium oxide, aluminum oxide, tantalum oxide The insulating layer 11 can be formed of an inorganic insulating material such as palladium. In addition, the insulating layer 11 can be formed of an inorganic insulating material such as polyimide or acrylic. It is also possible to form the interlayer insulating layer 126 using an organic insulating material. and interlayer insulating layer 128, the configuration of the interlayer insulating layer is not limited to this. After the interlayer insulating layer 128 is formed, the surface is flattened by CMP, etching, or the like. It is advisable to make the information available to the public.

[0071] Thereafter, an opening is formed in the interlayer insulating layer so as to reach the metal compound region 124. A source electrode or drain electrode 130a and a source electrode or drain electrode 130b are provided on the The source electrode or drain electrode 130a and the source electrode or The drain electrode 130b is formed by, for example, depositing a layer on a region including an opening using a PVD method, a CVD method, or the like. After the conductive layer is formed, a part of the conductive layer is removed by a method such as etching or CMP. It can be formed by removing

[0072] In addition, a part of the conductive layer is removed to form the source electrode or drain electrode 130a and the source electrode Alternatively, when forming the drain electrode 130b, the surface of the electrode is processed to be flat. For example, after forming a thin titanium film or titanium nitride film in the region including the opening, When a tungsten film is formed to fill the opening, the inclusions are removed by the subsequent CMP. Removes unnecessary tungsten, titanium, titanium nitride, etc. and improves the flatness of the surface. In this manner, the source electrode or drain electrode 130a, the source electrode Alternatively, the surface including the drain electrode 130b may be planarized to improve the quality of the resulting product in a later process. It becomes possible to form favorable electrodes, wiring, insulating layers, semiconductor layers, and the like.

[0073] In this case, the source electrode or drain electrode 130 in contact with the metal compound region 124 Although only the source electrode 130a or the drain electrode 130b is shown, in this process, Electrodes in contact with the base electrode 110a (for example, electrode 130c in FIG. 2) and the like are also included. A source electrode or drain electrode 130a, a source electrode or drain electrode There is no particular limitation on the material that can be used for the inner electrode 130b, and various conductive materials can be used. For example, molybdenum, titanium, chromium, tantalum, and tungsten can be used. Conductive materials such as aluminum, copper, neodymium, and scandium can be used.

[0074] In this manner, a transistor 160 is formed using the substrate 100 containing a semiconductor material. After the above steps, electrodes, wiring, an insulating layer, etc. may be further formed. In addition, by adopting a multilayer wiring structure consisting of a laminated structure of interlayer insulating layers and conductive layers, Therefore, it is possible to provide a highly integrated semiconductor device.

[0075] <How to make the upper transistor> Next, referring to FIG. 4 and FIG. 5, a process for forming a transistor 162 on the interlayer insulating layer 128 will be described. 4 and 5 show various electrodes and transistors on the interlayer insulating layer 128. Since the figure shows the manufacturing process of the transistor 162, the The transistor 160 and other components that correspond to it are omitted.

[0076] First, an interlayer insulating layer 128, a source electrode or drain electrode 130a, An insulating layer 132 is formed on the drain electrode 130b and the electrode 130c (see FIG. 4(A)). The edge layer 132 can be formed by using a PVD method, a CVD method, or the like. Silicon oxide nitride, silicon nitride, hafnium oxide, aluminum oxide, tantalum oxide The insulating film can be formed using an inorganic insulating material such as silica.

[0077] Next, the source or drain electrode 130a, the source or Openings are formed so as to reach the drain electrode 130b and the electrode 130c. An opening is also formed in the region where the gate electrode 136d is to be formed. A conductive layer 134 is formed so as to fill the opening (see FIG. 4B). The mask can be formed by a method such as etching using a photomask. It can be formed by a method such as exposure to light. As for etching, wet etching is used. Either etching or dry etching may be used, but from the viewpoint of fine processing, dry etching is preferred. The conductive layer 134 is preferably formed by a deposition method such as PVD or CVD. The conductive layer 134 can be formed by a film method. , molybdenum, titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium Conductive materials such as ZnO, ZnSe, and scandium, as well as their alloys and compounds (e.g., nitrides) are examples of such materials. can be done.

[0078] More specifically, for example, a thin titanium film is formed by PVD in the area including the opening, and then CV After forming a thin titanium nitride film by the D method, a tungsten film is formed to fill the opening. Here, the titanium film formed by the PVD method has a boundary. The oxide film on the surface is reduced, and the lower electrode (here, the source electrode or drain electrode 130a, A function of reducing the contact resistance with the source electrode or drain electrode 130b, electrode 130c, etc. In addition, the titanium nitride film formed thereafter has a burr-free property that suppresses the diffusion of the conductive material. In addition, after forming a barrier film using titanium or titanium nitride, etc., plating is performed. The copper film may be formed by a method.

[0079] After the conductive layer 134 is formed, the conductive layer 13 is etched or CMP is performed. A part of the insulating layer 132 is removed to expose the electrodes 136a, 136b, and 134. 6c, a gate electrode 136d is formed (see FIG. 4(C)). The electrode 136a, the electrode 136b, the electrode 136c, and the gate electrode 136d are formed by removing the portions. When the insulating layer 132 is formed, it is preferable to process the insulating layer 132 so that the surface is flat. , the surfaces of the electrodes 136a, 136b, 136c, and the gate electrode 136d are planarized. This allows for the formation of good electrodes, wiring, insulating layers, semiconductor layers, etc. in subsequent processes. This makes it possible.

[0080] Next, the insulating layer 132, the electrode 136a, the electrode 136b, the electrode 136c, and the gate electrode 136d are The gate insulating layer 138 is formed so as to cover the gate insulating layer 138 (see FIG. 4(D)). The gate insulating layer can be formed by using a CVD method, a sputtering method, or the like. 138 is silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, aluminum oxide, oxide It is preferable to form the gate insulating film so as to contain hafnium, tantalum oxide, or the like. The layer 138 may have a single layer structure or a multilayer structure. Silicon oxynitride was produced by plasma CVD using silane (SiH4), oxygen, and nitrogen. The thickness of the gate insulating layer 138 is not particularly limited. However, for example, it can be set to 10 nm or more and 500 nm or less. For example, a first gate insulating layer having a thickness of 50 nm to 200 nm and a first gate insulating It is preferable to laminate a second gate insulating layer having a thickness of 5 nm to 300 nm on the layer.

[0081] Note that an oxide semiconductor (high-temperature oxide semiconductor) that has been made i-type or substantially i-type by removing impurities can be used. Since the purified oxide semiconductor is extremely sensitive to the interface states and the interface charges, When using such an oxide semiconductor for the oxide semiconductor layer, the interface with the gate insulating layer is important. That is, the gate insulating layer 138 in contact with the highly purified oxide semiconductor layer has a high quality There will be a demand for quality improvement.

[0082] For example, the high-density plasma CVD method using microwaves (2.45 GHz) produces dense, high-insulation-voltage This is advantageous in that a high quality gate insulating layer 138 can be formed. The intimate contact between the conductor layer and the high-quality gate insulating layer reduces the interface state and improves the interface characteristics. Because it can be made to be a good thing.

[0083] Of course, if it can form a good insulating layer as a gate insulating layer, highly purified Even when an oxide semiconductor layer is used, other methods such as sputtering and plasma CVD are used. In addition, the film quality and interface characteristics can be improved by heat treatment after formation. In any case, the film quality of the gate insulating layer 138 is good. At the same time, the interface state density with the oxide semiconductor layer can be reduced to form a good interface. It is sufficient to form the following.

[0084] Furthermore, at 85°C, 2 × 10 6 V / cm, 12-hour gate bias and thermal stress test (B In the T test, when impurities are added to an oxide semiconductor, The bond with the main component of is broken by a strong electric field (B: bias) and high temperature (T: temperature), and the generated The dangling bonds induce a drift in the threshold voltage (Vth).

[0085] In response to this, impurities in oxide semiconductors, particularly hydrogen and water, should be eliminated as much as possible, and the above-mentioned By improving the interface characteristics with the base insulating layer, a stable transistor is produced even in the BT test. It is possible to obtain the data.

[0086] Next, an oxide semiconductor layer is formed over the gate insulating layer 138 and etched using a mask. The oxide semiconductor layer is processed by a method such as the above to form an island-shaped oxide semiconductor layer 140. (See FIG. 4(E)).

[0087] The oxide semiconductor layer includes In-Ga-Zn-O, In-Sn-Zn-O, and In-A l-Zn-O series, Sn-Ga-Zn-O series, Al-Ga-Zn-O series, Sn-Al-Zn -O series, In-Zn-O series, Sn-Zn-O series, Al-Zn-O series, In-O series, Sn- It is preferable to use an O-based or Zn-O-based oxide semiconductor layer, and in particular an amorphous oxide semiconductor layer. In this embodiment, an In-Ga-Zn-O oxide semiconductor film is formed as the oxide semiconductor layer. The amorphous oxide semiconductor layer is formed by a sputtering method using a target for sputtering. Note that the addition of silicon to an amorphous oxide semiconductor layer suppresses the crystallization of the layer. Therefore, for example, a target containing SiO2 in an amount of 2% by weight or more and 10% by weight or less can be used. An oxide semiconductor layer may be formed using the above-mentioned method.

[0088] Examples of targets for forming an oxide semiconductor layer by a sputtering method include oxide A target made of a metal oxide mainly composed of zinc can be used. In, Ga, and Zn-containing oxide semiconductor film deposition target (composition ratio: In2O3:Ga2O 3:ZnO=1:1:1[mol%], In:Ga:Zn=1:1:0.5[atom% In addition, an oxide semiconductor film containing In, Ga, and Zn can be formed. The target for In:Ga:Zn=1:1:1[atom%] or In:Ga A target having a composition ratio of Zn=1:1:2 [atom %] may be used. The filling rate of the compound semiconductor film deposition target is 90% or more and 100% or less, preferably 95% or more. (For example, 99.9%). Use a target for oxide semiconductor film formation with a high filling rate. As a result, a dense oxide semiconductor layer is formed.

[0089] The oxide semiconductor layer is formed in a rare gas (typically, argon) atmosphere, an oxygen atmosphere, or a fluorine-containing gas atmosphere. Alternatively, it is preferable to use a mixed atmosphere of a rare gas (typically argon) and oxygen. In general, impurities such as hydrogen, water, hydroxyl groups, and hydrides are present at concentrations of about ppm (preferably It is preferable to use a high-purity gas in which the concentration is reduced to about ppb.

[0090] When forming the oxide semiconductor layer, the substrate is held in a treatment chamber kept in a reduced pressure state. The temperature is set to 100°C or higher and 600°C or lower, preferably 200°C or higher and 400°C or lower. By forming the oxide semiconductor layer while performing the above-mentioned step, the impurity concentration in the oxide semiconductor layer can be reduced. Also, damage caused by sputtering can be reduced. The residual moisture in the metal oxide film is removed, and a sputtering gas from which hydrogen and water have been removed is introduced. In order to remove residual moisture in the treatment chamber, It is preferable to use an adsorption type vacuum pump. For example, a cryopump or an ion pump. A titanium sublimation pump can be used. A cryopump with a cold trap may be used. The deposition chamber is filled with, for example, hydrogen atoms, compounds containing hydrogen atoms such as water (H2O) (preferably Since the oxide semiconductor formed in the film formation chamber is exhausted, The concentration of impurities contained in the layer can be reduced.

[0091] The formation conditions are, for example, a distance between the substrate and the target of 100 mm and a pressure of 0.6 Pa, DC power 0.5kW, oxygen atmosphere (oxygen flow rate 100%) The following conditions can be applied. When a pulsed direct current (DC) power supply is used, the deposition This reduces the amount of powdery material (also called particles or dust) that is generated during coating, and also makes the film thickness distribution uniform. The thickness of the oxide semiconductor layer is preferably 2 nm to 200 nm, more preferably 5 The appropriate thickness varies depending on the oxide semiconductor material used. Therefore, the thickness may be appropriately selected depending on the material used.

[0092] Before forming the oxide semiconductor layer by sputtering, argon gas was introduced to the plasma A reverse sputtering process is performed to generate a smear, and dust adhering to the surface of the gate insulating layer 138 is removed. Here, the reverse sputtering is a method of removing the sputtering. Instead of bombarding the target with ions, the treatment surface is bombarded with ions. The method of modifying the surface by bombarding the surface with ions is as follows: A high-frequency voltage is applied to the processing surface side in an argon atmosphere to generate plasma near the substrate. In addition, the argon atmosphere may be replaced by a nitrogen, helium, or oxygen atmosphere. You may use it.

[0093] The etching of the oxide semiconductor layer can be performed by either dry etching or wet etching. Of course, both can be used in combination. In order to match the etching conditions (etching gas, etching solution, etc.) to the material, Etching time, temperature, etc. are set appropriately.

[0094] The etching gas used in dry etching is, for example, a gas containing chlorine (chlorine-based gas, For example, chlorine (Cl2), boron chloride (BCl3), silicon chloride (SiCl4), carbon tetrachloride ( CCl4) and others. In addition, gases containing fluorine (fluorine-based gases, such as carbon tetrafluoride) Fluorine (CF4), sulfur fluoride (SF6), nitrogen fluoride (NF3), trifluoromethane (CHF 3), hydrogen bromide (HBr), oxygen (O2), and the addition of helium (He) or ammonia to these gases. A gas containing an added rare gas such as argon (Ar) may also be used.

[0095] As a dry etching method, parallel plate type RIE (Reactive Ion Etch) ing method and ICP (Inductively Coupled Plasma) A method of etching a silicon wafer using a plasma-coupled plasma (PPS) can be used. As shown in the figure, the etching conditions (the amount of power applied to the coil-shaped electrode, the amount of power applied to the electrode on the substrate side) The power consumption, electrode temperature on the substrate side, etc. are set appropriately.

[0096] The etching solution used for wet etching is a mixture of phosphoric acid, acetic acid, and nitric acid. Ammonia peroxide water (31% by weight hydrogen peroxide water: 28% by weight ammonia water: water = 5:2:2) In addition, an etching solution such as ITO07N (manufactured by Kanto Chemical Co., Ltd.) can be used. It's fine.

[0097] Next, the oxide semiconductor layer is preferably subjected to a first heat treatment. The temperature of the first heat treatment can be set to The temperature is set to 300° C. or higher and 750° C. or lower, preferably 400° C. or higher and lower than the distortion point of the substrate. For example, The substrate is placed in an electric furnace using a resistance heating element or the like, and the oxide semiconductor layer 140 is heated in a nitrogen atmosphere. Heat treatment is performed at 450° C. in air for 1 hour. During this time, the oxide semiconductor layer 140 is not exposed to the air. No touching is required to prevent recontamination of water or hydrogen.

[0098] The heat treatment device is not limited to an electric furnace, and may be any device that uses heat conduction from a medium such as a heated gas, or The apparatus may be a device that heats the object to be treated by thermal radiation. For example, a GRTA (Gas Rapid Thermal Anneal) equipment, LRTA (Lamp Rapid RTA (Rapid Thermal Anneal) equipment etc. The LRTA device can be equipped with halogen lamps, metal halide lamps, etc. Lamps, xenon arc lamps, carbon arc lamps, high pressure sodium lamps, high pressure water A device that heats the workpiece by radiating light (electromagnetic waves) emitted from a lamp such as a silver lamp. The GRTA device is a device that performs heat treatment using high-temperature gas. An inert gas that does not react with the workpiece during heat treatment, such as a rare gas such as argon or nitrogen. A gas is used.

[0099] For example, in the first heat treatment, the substrate is immersed in an inert gas heated to a high temperature of 650° C. to 700° C. After heating for a few minutes, the substrate is taken out of the inert gas (GRTA process). GRTA treatment allows high-temperature heat treatment in a short time. Because it is a heat treatment, it can be applied even under temperature conditions exceeding the distortion point of the substrate.

[0100] The first heat treatment is performed in a vacuum chamber mainly containing nitrogen or a rare gas (helium, neon, argon, etc.). It is preferable to carry out the process in an atmosphere that does not contain water, hydrogen, etc. The purity of nitrogen or rare gas such as helium, neon, or argon introduced into the heat treatment device is 6N (99.9999%) or more, preferably 7N (99.99999%) or more (i.e. , the impurity concentration is 1 ppm or less, preferably 0.1 ppm or less.

[0101] Depending on the conditions of the first heat treatment or the material of the oxide semiconductor layer, the oxide semiconductor layer may be crystallized. In some cases, the crystallinity is 90% or more, or 80% or less. % or more of the crystallinity of the oxide semiconductor layer. Depending on the material of the oxide semiconductor layer, the oxide semiconductor layer may be amorphous and not contain crystalline components. There are also cases where this is the case.

[0102] In addition, microcrystals (grain size of 1 nm or less) are formed in an amorphous oxide semiconductor (for example, on the surface of an oxide semiconductor layer). The oxide semiconductor layer is a mixture of 20 nm or less (typically 2 nm or more and 4 nm or less). There are cases like this.

[0103] In addition, the electrical characteristics of the oxide semiconductor layer can be changed by arranging microcrystals in an amorphous material. For example, a target for forming an oxide semiconductor film of In-Ga-Zn-O system is When forming an oxide semiconductor layer using In2Ga2ZnO7 By forming a microcrystalline portion in which the crystal grains of the oxide semiconductor layer are oriented, the electrical characteristics of the oxide semiconductor layer are changed. It is possible.

[0104] More specifically, for example, the c-axis of In2Ga2ZnO7 is perpendicular to the surface of the oxide semiconductor layer. By orienting the oxide semiconductor layer in a direction parallel to the surface of the oxide semiconductor layer, the electrical conductivity in the direction parallel to the surface of the oxide semiconductor layer is improved. This can improve the insulating property in the direction perpendicular to the surface of the oxide semiconductor layer. The microcrystal parts have a function of suppressing the intrusion of impurities such as water and hydrogen into the oxide semiconductor layer. has.

[0105] Note that the oxide semiconductor layer having the above-described microcrystal portion is a GRTA-treated oxide semiconductor layer. It can be formed by surface heating. Also, the Zn content is higher than the In or Ga content. A more suitable formation can be achieved by using a smaller sputtering target.

[0106] The first heat treatment for the oxide semiconductor layer 140 is performed to process the oxide semiconductor layer 140 into an island-shaped oxide semiconductor layer 140. In that case, the first heat treatment is performed on the oxide semiconductor layer. The substrate is then removed and subjected to a photolithography process.

[0107] The heat treatment has the effect of dehydrating and dehydrogenating the oxide semiconductor layer 140. Such dehydration and dehydrogenation treatments can also be called dehydration treatments, dehydrogenation treatments, etc. The process is performed by forming a source electrode or a drain electrode on the oxide semiconductor layer 140 after forming the oxide semiconductor layer. After laminating electrodes, forming a protective insulating layer on the source electrode or drain electrode, etc. In addition, such dehydration and dehydrogenation treatments can be carried out at the timing of The treatment may be carried out not only once but also multiple times.

[0108] Next, a source electrode or drain electrode 142a, The source or drain electrode 142b is formed (see FIG. 4(F)). The drain electrode 142a and the source or drain electrode 142b are formed on the oxide semiconductor layer 1 After forming a conductive layer so as to cover 40, the conductive layer is selectively etched. It can be formed.

[0109] The conductive layer is formed by using PVD methods such as sputtering and CVD methods such as plasma CVD. The conductive layer can be formed of a material such as aluminum, chromium, copper, Tantalum, titanium, molybdenum, tungsten, or any of the above elements. Manganese, magnesium, zirconium, beryllium, etc. can be used. Alternatively, a material selected from one or more of aluminum, thorium, and aluminum alloy may be used. Titanium, tantalum, tungsten, molybdenum, chromium, neodymium, scandium Alternatively, a material containing a single element selected from the group consisting of aluminum and a combination of multiple elements may be used. It may be a single layer structure or a laminated structure of two or more layers. For example, Single-layer aluminum film structure, two-layer aluminum film with titanium film laminated on top, titanium and a three-layer structure in which a film, an aluminum film, and a titanium film are laminated.

[0110] Here, the exposure to light when forming the mask used for etching is ultraviolet light, KrF laser light, or ArF It is preferable to use laser light.

[0111] The channel length (L) of the transistor is defined as the distance between the bottom end of the source or drain electrode 142a and the is determined by the distance between the lower end of the source electrode or drain electrode 142b. When performing exposure with a channel length (L) of less than 25 nm, the wavelength is extremely low, ranging from a few nm to a few tens of nm. Mask formation exposure using short-length extreme ultraviolet light Extreme ultraviolet light exposure provides high resolution and a large depth of focus. It is also possible to set the channel length (L) of the transistor to be 10 nm or more and 1000 nm or less. This allows the circuit to operate at a high speed. Furthermore, the off-state current is extremely small, so power consumption is The force does not need to be large.

[0112] In addition, when etching the conductive layer, the oxide semiconductor layer 140 is not removed. The materials and etching conditions are adjusted appropriately. In this step, a part of the oxide semiconductor layer 140 is etched to form a groove (a recess ) may be formed as an oxide semiconductor layer.

[0113] In addition, between the oxide semiconductor layer 140 and the source electrode or drain electrode 142a, An oxide conductive layer is formed between the conductor layer 140 and the source electrode or drain electrode 142b. The oxide conductive layer and the source or drain electrode 142a or The metal layer for forming the drain electrode 142b is formed continuously (continuous film formation). It is possible. The oxide conductive layer can function as a source region or a drain region. By providing such an oxide conductive layer, the resistance of the source region or the drain region can be reduced. This allows high speed operation of the transistor.

[0114] In order to reduce the number of masks used and the number of processes, an exposure method in which the transmitted light has multiple intensities is used. A resist mask is formed using a multi-tone mask, which is a mask, and the etching process is performed using this. The resist mask formed using the multi-tone mask has a plurality of thicknesses. The shape becomes stepped, and the shape can be further deformed by ashing. It can be used for multiple etching processes to process different patterns. A multi-tone mask is used to create resist masks that correspond to at least two different patterns. Therefore, the number of exposure masks can be reduced, and the corresponding photomasks can be formed. The lithography process can also be eliminated, simplifying the process.

[0115] After the above process, plasma treatment using gas such as N2O, N2, or Ar may be performed. It is preferable that the plasma treatment is performed on the exposed surface of the oxide semiconductor layer. Water and other adhering substances are removed. In addition, plasma treatment is performed using a mixture of oxygen and argon gas. You may go.

[0116] Next, the protective insulating layer 14 in contact with a part of the oxide semiconductor layer 140 is removed without exposing it to the air. Form 4 (see Figure 4(G)).

[0117] The protective insulating layer 144 is formed by mixing impurities such as water and hydrogen into the protective insulating layer 144 using a method such as sputtering. The thickness of the layer is at least 1 nm. The protective insulating layer 144 can be formed of a material such as silicon oxide, silicon nitride, or the like. Silicon oxynitride, silicon nitride oxide, etc. Also, the structure may be a single layer structure, The substrate temperature when the protective insulating layer 144 is formed is equal to or higher than room temperature and equal to or higher than 300° C. The atmosphere is preferably a rare gas (typically argon) atmosphere or an oxygen atmosphere. Alternatively, a mixed atmosphere of a rare gas (typically argon) and oxygen is preferably used.

[0118] If hydrogen is contained in the protective insulating layer 144, the hydrogen may penetrate into the oxide semiconductor layer or may be oxidized by the hydrogen. As a result, oxygen is extracted from the oxide semiconductor layer, and the oxide semiconductor layer is Therefore, the resistance of the protective insulating layer 1 may become low, and a parasitic channel may be formed. It is important that 44 does not contain hydrogen as much as possible, and that hydrogen is not used in the formation method. It is.

[0119] In addition, it is preferable to form the protective insulating layer 144 while removing residual moisture in the processing chamber. The compound semiconductor layer 140 and the protective insulating layer 144 are preferably made of a material that does not contain hydrogen, hydroxyl groups, or moisture. This is to make it possible.

[0120] In order to remove residual moisture from within the processing chamber, it is preferable to use an adsorption type vacuum pump. For example, cryopumps, ion pumps, and titanium sublimation pumps can be used. It is preferable that the exhaust means is a turbo pump with a cold trap added. The deposition chamber evacuated using a cryopump may be filled with hydrogen atoms, water (H2 O) and other compounds containing hydrogen atoms have been removed, The concentration of impurities contained in the layer 144 can be reduced.

[0121] The sputtering gas used in forming the protective insulating layer 144 is hydrogen, water, a hydroxyl group, or Impurities such as hydrides are removed to a concentration of about ppm (preferably, about ppb). It is preferable to use a high purity gas that has been

[0122] Then, a second heat treatment (preferably for 20 It is preferable to carry out the heating at a temperature between 0°C and 400°C, for example between 250°C and 350°C. The second heat treatment is performed at 250° C. for 1 hour in a nitrogen atmosphere. This can reduce the variation in the electrical characteristics of the transistors.

[0123] In addition, even if heat treatment is performed in air at 100°C to 200°C for 1 hour to 30 hours, This heat treatment may be performed by maintaining a constant heating temperature or by heating from room temperature to 100°C or higher. Repeat heating to a temperature of 200°C or less and then cooling from the heating temperature to room temperature several times. Moreover, this heat treatment may be carried out under reduced pressure before the formation of the protective insulating layer. When the heat treatment is performed under reduced pressure, the heating time can be shortened. This may be carried out instead of the second heat treatment, or may be carried out before or after the second heat treatment.

[0124] Next, an interlayer insulating layer 146 is formed on the protective insulating layer 144 (see FIG. 5(A)). The edge layer 146 can be formed by using a PVD method, a CVD method, or the like. Silicon oxide nitride, silicon nitride, hafnium oxide, aluminum oxide, tantalum oxide After the interlayer insulating layer 146 is formed, the It is preferable to planarize the surface of the substrate by a method such as CMP or etching.

[0125] Next, an electrode 1 is formed on the interlayer insulating layer 146, the protective insulating layer 144, and the gate insulating layer 138. 36a, electrode 136b, electrode 136c, source or drain electrode 142a, source An opening is formed so as to reach the electrode or drain electrode 142b, and a conductive material is embedded in the opening. A conductive layer 148 is formed (see FIG. 5B). The opening is formed by etching using a mask or the like. The mask can be formed by a method such as exposure using a photomask. The etching method can be wet etching or dry etching. However, from the viewpoint of fine processing, it is preferable to use dry etching. The conductive layer 148 is preferably formed by a film forming method such as a PVD method or a CVD method. Materials that can be used to form the conductive layer 148 include molybdenum, titanium, and the like. Tantalum, chromium, tantalum, tungsten, aluminum, copper, neodymium, scandium, etc. Examples of the conductive materials include any of the conductive materials, their alloys, and compounds (e.g., nitrides).

[0126] Specifically, for example, a thin titanium film is formed in the area including the opening by the PVD method, and then the titanium film is removed by the CVD method. After forming a thin titanium nitride film by , a tungsten film is formed so as to fill the opening. Here, the titanium film formed by the PVD method has a high degree of adhesion at the interface. The oxide film is reduced, and the lower electrodes (here, electrodes 136a, 136b, 136c, The connection between the source or drain electrode 142a and the source or drain electrode 142b The titanium nitride film formed after that has the function of reducing the contact resistance. It has a barrier function that suppresses the diffusion of materials. In addition, a barrier film made of titanium or titanium nitride is also used. After forming the insulating film, a copper film may be formed by plating.

[0127] After the conductive layer 148 is formed, the conductive layer 148 is removed by a method such as etching or CMP. A part of the interlayer insulating layer 146 is removed to expose the electrodes 150a, 150b, and 15 Electrode 150c, electrode 150d, and electrode 150e are formed (see FIG. 5(C)). 48 is removed to form electrodes 150a, 150b, 150c, 150d, and When forming 150e, it is desirable to process it so that the surface is flat. The interlayer insulating layer 146, the electrodes 150a, 150b, 150c, 150d, By flattening the surface of the electrode 150e, it is possible to obtain good electrodes, wiring, and insulation in the subsequent processes. It is possible to form a layer, a semiconductor layer, etc.

[0128] Further, an insulating layer 152 is formed, and the electrodes 150a, 150b, and 150c are attached to the insulating layer 152. 50c, the electrode 150d, and the electrode 150e are formed, and the After forming the conductive layer as described above, a part of the conductive layer is removed by a method such as etching or CMP. , the insulating layer 152 is exposed, and the electrodes 154a, 154b, 154c, and 154 This step is the same as that for forming the electrodes 150a, etc. Therefore, I will omit the details.

[0129] In the case where the transistor 162 is manufactured by the above-described method, the hydrogen concentration in the oxide semiconductor layer 140 is Degree is 5 x 10 19 / cm 3 and the off-current of the transistor 162 is 1×10 -13 A or less. In this way, the hydrogen concentration is sufficiently reduced and the oxide semiconductor is highly purified. By using the conductor layer 140, a transistor 162 with excellent characteristics can be obtained. In addition, a transistor 160 using a material other than an oxide semiconductor is provided in the lower portion, and an oxide It is possible to manufacture a semiconductor device having excellent characteristics including a transistor 162 using a semiconductor. Cut.

[0130] In addition, examples of semiconductor materials that can be compared to oxide semiconductors include silicon carbide (e.g., 4H Oxide semiconductors and 4H-SiC have several things in common. The rear density is one example. Using the Fermi-Dirac distribution at room temperature, The number of minority carriers in the body is 10 -7 / cm 3 This is estimated to be about 4H-SiC. 6.7×10 -11 / cm 3 This is an extremely low value, similar to that of the intrinsic carriers in silicon. Density (1.4×10 10 / cm 3 Compared to the degree of I can understand that very well.

[0131] In addition, the energy band gap of oxide semiconductors is 3.0 to 3.5 eV, and The energy band gap of iC is 3.26 eV, so it is called a wide-gap semiconductor. In this respect, oxide semiconductors and silicon carbide have in common.

[0132] On the other hand, there is a very big difference between oxide semiconductors and silicon carbide. In semiconductor processes using silicon carbide, the process temperature is generally 1500℃ to 20 Since activation heat treatment at 00℃ is required, it is difficult to stack semiconductor elements using other semiconductor materials. At such high temperatures, the semiconductor substrate and semiconductor elements are destroyed. On the other hand, oxide semiconductors are heated at temperatures between 300 and 500°C (below the glass transition temperature, It can be fabricated by heat treatment (even at temperatures of around 700°C) and can be integrated with other semiconductor materials. After forming the circuits, a semiconductor element can be formed using an oxide semiconductor.

[0133] In addition, unlike silicon carbide, it is possible to use substrates with low heat resistance, such as glass substrates. Furthermore, it has the advantage that it does not require high-temperature heat treatment, which is advantageous compared to silicon carbide. This has the advantage that the energy cost can be sufficiently reduced.

[0134] In addition, in oxide semiconductors, physical properties such as DOS (density of state) Although many studies have been conducted, these studies have not achieved the idea of ​​sufficiently reducing DOS itself. In one embodiment of the disclosed invention, water or hydrogen, which may cause DOS, is not contained in an oxide semiconductor. By removing the DOS, a highly purified oxide semiconductor is produced. This is based on the idea of ​​reducing emissions sufficiently. It allows the manufacture of products.

[0135] In addition, oxygen is supplied to the dangling bonds of metals that are generated due to oxygen deficiency, and oxygen vacancies are formed. By reducing the DOS, a more highly purified (i-type) oxide semiconductor can be obtained. For example, an oxide film containing excess oxygen is formed in close contact with the channel forming region, By supplying oxygen from the oxide film, it is possible to reduce DOS caused by oxygen defects.

[0136] Defects in oxide semiconductors are caused by excess hydrogen at shallow levels 0.1 to 0.2 eV below the conduction band, or by oxidation. These defects are believed to be caused by deep levels due to a lack of elements. The technical idea of ​​thoroughly removing hydrogen and providing a sufficient amount of oxygen is correct. cormorant.

[0137] In addition, although oxide semiconductors are generally n-type, in one embodiment of the disclosed invention, In particular, the i-type is achieved by removing water and hydrogen. It can be said that this is not an i-type product that is made by adding impurities, but rather contains a technological concept that has never been seen before.

[0138] In this embodiment, the transistor 162 has a bottom gate structure. However, one embodiment of the present invention is not limited thereto. The transistor 162 may have a top-gate structure. A dual-gate type semiconductor device having two gate electrode layers arranged above and below a formation region with a gate insulating layer interposed therebetween. A rugate type structure may also be used.

[0139] <Conduction mechanism of transistors using oxide semiconductors> Here, the conduction mechanism of a transistor using an oxide semiconductor will be described with reference to FIGS. The following explanation is merely a consideration, and the validity of the invention is not denied based on this explanation. It should be noted that this is not a

[0140] FIG. 24 shows a dual-gate transistor (thin film transistor) using an oxide semiconductor. A cross-sectional view of the gate electrode layer (GE1) and an oxide semiconductor layer (GI1) are formed on the gate electrode layer (GE1). A conductor layer (OS) is provided, and a source electrode (S) and a drain electrode (D) are provided thereon. In addition, the oxide semiconductor layer (OS), the source electrode (S) and the drain electrode (D A gate insulating layer (GI2) is provided to cover the oxide semiconductor layer (OS). A gate electrode (GE2) is provided via an insulating layer (GI2).

[0141] FIG. 25 shows an energy band diagram (schematic diagram) in the A-A' cross section of FIG. 5(A) reduces the potential difference between the source and drain to zero (equipotential, V D = 0V) FIG. 25(B) shows the case where the drain potential is increased relative to the source potential (V D >0) is doing.

[0142] FIG. 26 shows an energy band diagram (schematic diagram) in the cross section taken along line B-B' in FIG. Figure 26(A) shows a case where a positive potential (+V G ) is given, and The figure shows the on-state where carriers (electrons) flow between the source and drain. (B) A negative potential (-V G ) is a given state, and the off state ( 4 shows the case where several carriers do not flow.

[0143] Figure 27 shows the relationship between the vacuum level and the work function (φ M ) and the electron affinity (χ) of the oxide semiconductor Shows.

[0144] Conventional oxide semiconductors are n-type, and their Fermi level (E f ) is in the center of the band gap The intrinsic Fermi level (E i ) and is located closer to the conduction band. It is known that some hydrogen atoms act as donors in semiconductors, which is one of the factors that makes them n-type. is.

[0145] In contrast, an oxide semiconductor according to one embodiment of the disclosed invention can convert hydrogen, which is a factor in making the oxide semiconductor n-type, into an oxide. The oxide semiconductor is made of a material that is free from elements (impurity elements) other than the main components of the oxide semiconductor. By purifying it to such a high level that it is indistinguishable from the intrinsic form (type i), or as close to intrinsic as possible, In other words, instead of adding impurity elements to make it i-type, impurities such as hydrogen and water are removed as much as possible. By removing the impurities, it is possible to obtain a highly purified i-type (intrinsic semiconductor) or a semiconductor close to it. This results in the Fermi level (E f ) is the intrinsic Fermi level (E i ) and It is possible.

[0146] The band gap of oxide semiconductors (E g ) is 3.15 eV, the electron affinity (χ) is It is said that the work of titanium (Ti) that constitutes the source electrode and drain electrode is 4.3 eV. The function is approximately equal to the electron affinity (χ) of the oxide semiconductor. In this case, the metal-oxide semiconductor At the interface, no Schottky-type barrier is formed for electrons.

[0147] That is, the work function of the metal (φ M ) and the electron affinity (χ) of the oxide semiconductor are equal, When a person comes into contact with the material, an energy band diagram (schematic diagram) like that shown in FIG. 25(A) is displayed.

[0148] In FIG. 25(B), black circles (●) represent electrons. When a positive potential is applied to the drain, The electrons cross the barrier (h) and are injected into the oxide semiconductor, then flow toward the drain. The height of (h) depends on the gate voltage and the drain voltage. When a voltage is applied, the barrier height in FIG. 25(A) without voltage application, i.e., the band gap Top (E g ) or lower.

[0149] At this time, the electrons pass through the gate insulating layer and the highly purified oxide semiconductor, as shown in FIG. The electrons move near the interface with the body (the most energetically stable part of the oxide semiconductor).

[0150] Also, as shown in FIG. 26(B), when a negative potential is applied to the gate electrode (G1), Since the number of holes, which are carriers, is substantially zero, the current is very close to zero.

[0151] In this way, high purity oxide semiconductors are used to minimize the amount of elements (impurity elements) other than the main components of the oxide semiconductor. By tempering, the gate insulating layer becomes intrinsic (i-type) or substantially intrinsic. Therefore, the gate insulating layer is required to have a good interface with the oxide semiconductor. Specifically, for example, the power supply frequency of the VHF band to the microwave band is required. Insulating layers are produced by the CVD method using high-density plasma generated by a large number of processes, and by sputtering. It is preferable to use an insulating layer produced by a method such as the above.

[0152] The oxide semiconductor is highly purified while the interface between the oxide semiconductor and the gate insulating layer is improved. For example, the channel width W of a transistor is 1×10 4 μm, channel length L In the case of 3 μm, it is 1×10 -13 Off-state current less than A, 0.1V / dec. A subthreshold swing value (S value) of 100 nm (gate insulating layer thickness) was achieved. It is possible.

[0153] In this way, the oxide semiconductor is highly processed so that elements other than the main components (impurity elements) are not included as much as possible. By purifying the material, the operation of the thin film transistor can be improved.

[0154] <Modification> 6 to 9 show modified examples of the configuration of the semiconductor device. In the following, the following modified examples are A description will be given of a transistor 162 having a different configuration from that described above. The configuration of the controller 160 is the same as that described above.

[0155] In FIG. 6, a gate electrode 136d is provided under an oxide semiconductor layer 140, and a source electrode or drain electrode The drain electrode 142a and the source electrode or drain electrode 142b are formed on the oxide semiconductor layer 14. The lower surface of the transistor 162 is in contact with the oxide semiconductor layer 140. An example of a semiconductor device is shown below. The planar structure can be changed appropriately according to the cross section. Here, only the cross section is shown.

[0156] The major difference between the configuration shown in FIG. 6 and the configuration shown in FIG. 2 is that the source electrode or the drain electrode The connection between the oxide semiconductor layer 140 and the source or drain electrode 142a or 142b That is, in the configuration shown in FIG. 2, , the source electrode or drain electrode 142a, the source electrode or drain electrode 142b, 6, the oxide semiconductor layer 140 is in contact with the lower surface of the oxide semiconductor layer 140. The source electrode or drain electrode 142a and the source electrode or drain electrode 142b are in contact with each other. Due to this difference in contact, the arrangement of other electrodes, insulating layers, etc. may differ. The details of each component are the same as those in Figure 2.

[0157] Specifically, the semiconductor device shown in FIG. 6 includes a gate electrode 13 provided on an interlayer insulating layer 128. 6d, a gate insulating layer 138 provided on the gate electrode 136d, and the gate insulating layer 138 A source electrode or drain electrode 142a, a source electrode or drain electrode electrode 142b, a source electrode or drain electrode 142a, a source electrode or drain electrode and an oxide semiconductor layer 140 in contact with the upper surface of 142b.

[0158] Here, the gate electrode 136d is embedded in the insulating layer 132 formed on the interlayer insulating layer 128. In addition, like the gate electrode 136d, An electrode 136a is connected to the source or drain electrode 130b. An electrode 136b is formed in contact with the electrode 130c, and an electrode 136c is formed in contact with the electrode 130c.

[0159] In addition, a protective layer is provided on the transistor 162 so as to be in contact with part of the oxide semiconductor layer 140. An insulating layer 144 is provided, and an interlayer insulating layer 146 is provided on the protective insulating layer 144. Here, the protective insulating layer 144 and the interlayer insulating layer 146 are provided with a source electrode or a drain electrode. The openings reach the source electrode 142a and the source or drain electrode 142b. Through the opening, the electrode 150d and the electrode 150e are connected to the source electrode or the drain electrode. The electrode 142a is formed in contact with the source electrode or the drain electrode 142b. As well as the electrode 150d and the electrode 150e, the gate insulating layer 138, the protective insulating layer 144, the interlayer insulating The layer 146 is provided with openings through which the electrodes 136a, 136b, and 136c are in contact. Electrodes 150a, 150b, and 150c are formed.

[0160] An insulating layer 152 is provided on the interlayer insulating layer 146, and a buried insulating film is formed in the insulating layer 152. Electrodes 154a, 154b, 154c, and 154d are provided so that the electrodes 154a, 154b, 154c, and 154d are inserted into the Here, electrode 154a is in contact with electrode 150a, and electrode 154b is in contact with electrode 150. b, electrode 154c is in contact with electrode 150c and electrode 150d, and electrode 1 54d is in contact with electrode 150e.

[0161] FIG. 7 shows an example of the configuration of a semiconductor device having a gate electrode 136d on an oxide semiconductor layer 140. Here, FIG. 7A shows a source electrode or drain electrode 142a and a source electrode Alternatively, the drain electrode 142b may be formed of an oxide semiconductor on the lower surface of the oxide semiconductor layer 140. 7B is an example of a configuration in which the source electrode or drain electrode 142 is in contact with the layer 140. a and the source electrode or drain electrode 142b are provided on the upper surface of the oxide semiconductor layer 140. 13 is an example of a structure in which the oxide semiconductor layer 140 is in contact with the oxide semiconductor layer 140.

[0162] The major difference between the configuration shown in FIG. 2 and FIG. 6 and the configuration shown in FIG. The difference is that the gate electrode 136d is provided. The major difference in the configuration is the source electrode or drain electrode 142a and The drain electrode 142b is disposed on either the lower surface or the upper surface of the oxide semiconductor layer 140. These differences lead to differences in other electrodes, insulation, and The arrangement of layers is different. The details of each component are the same as in Figure 2.

[0163] Specifically, the semiconductor device shown in FIG. 7A has a source electrode provided on an interlayer insulating layer 128. a source or drain electrode 142a, a source or drain electrode 142b, and a source electrode or in contact with the upper surface of the drain electrode 142a, the source electrode or the drain electrode 142b. and a gate insulating layer 138 provided on the oxide semiconductor layer 140. , a gate electrode 136d in a region overlapping with the oxide semiconductor layer 140 on the gate insulating layer 138; , has.

[0164] In FIG. 7B, the oxide semiconductor layer 140 and the oxide A source electrode or drain electrode 1 is provided in contact with the upper surface of the semiconductor layer 140. 42a, a source electrode or drain electrode 142b, an oxide semiconductor layer 140, a source electrode or drain electrode 142a and a source or drain electrode 142b. The gate insulating layer 138 overlaps with the oxide semiconductor layer 140 on the gate insulating layer 138. and a gate electrode 136d in the region.

[0165] In addition, in the configuration shown in FIG. 7, compared with the configuration shown in FIG. 2, some components may be omitted. In this case, the manufacturing process can be simplified. Of course, this is not essential in the configuration shown in FIG. It goes without saying that components can be omitted.

[0166] FIG. 8 shows a case where the size of the element is relatively large, in which a gate electrode is provided under the oxide semiconductor layer 140. This is an example of a configuration having an electrode 136d. In this case, the requirements for surface flatness and coverage are satisfied. Since the requirements are relatively gentle, wiring, electrodes, etc. are formed by embedding them in the insulating layer. For example, the gate electrode 136 can be formed by patterning the conductive layer after it is formed. Although not shown here, it is possible to form the transistor 160 It is also possible to prepare the same.

[0167] The major difference between the configuration shown in FIG. 8(A) and the configuration shown in FIG. 8(B) is the source electrode or drain electrode. The source electrode 142a and the source or drain electrode 142b are formed on the oxide semiconductor layer 140. The question is whether the contact is made on the lower or upper surface of the Due to these differences, the arrangement of other electrodes, insulating layers, etc. is also different. The details of the components are the same as those in FIG.

[0168] Specifically, in FIG. 8A, a gate electrode 136d is provided on the interlayer insulating layer 128, A gate insulating layer 138 is provided on the gate electrode 136d. The source or drain electrode 142a, the source or drain electrode 142 b, and the source or drain electrode 142a, the source or drain electrode 142b and an oxide semiconductor layer 140 in contact with the upper surface of the substrate.

[0169] In FIG. 8B, a gate electrode 136d is provided on the interlayer insulating layer 128, and a gate A gate insulating layer 138 provided on the electrode 136d, and a gate electrode on the gate insulating layer 138 The oxide semiconductor layer 140 provided in a region overlapping with the oxide semiconductor layer 136d and the oxide semiconductor layer 140 A source electrode or drain electrode 142a provided in contact with the upper surface, a source electrode or a drain electrode 142b.

[0170] In addition, in the configuration shown in FIG. 8, compared to the configuration shown in FIG. 2, some components are omitted. In this case as well, the effect of simplifying the manufacturing process can be obtained.

[0171] FIG. 9 shows a case where the size of the element is relatively large, in which a gate is formed on the oxide semiconductor layer 140. This is an example of a configuration having an electrode 136d. In this case, too, the flatness of the surface and the coverage are important. Since the requirements for the insulation are relatively low, wiring and electrodes are embedded in the insulating layer. For example, the gate electrode 1 can be formed by patterning after the conductive layer is formed. Although not shown here, it is possible to form transistor 1 60 can be produced in the same manner.

[0172] The major difference between the configuration shown in FIG. 9(A) and the configuration shown in FIG. 9(B) is that the source electrode or the drain electrode The source electrode 142a and the source or drain electrode 142b are formed on the oxide semiconductor layer 140. The question is whether the contact is made on the lower or upper surface of the Due to these differences, the arrangement of other electrodes, insulating layers, etc. is also different. The details of the components are the same as those in FIG.

[0173] Specifically, in FIG. 9A, a source electrode or a drain electrode provided on an interlayer insulating layer 128 A source electrode 142a, a source or drain electrode 142b, and a source or drain electrode An oxide semiconductor in contact with the upper surface of the electrode 142a and the source or drain electrode 142b Layer 140, source or drain electrode 142a, source or drain electrode 1 42b, a gate insulating layer 138 provided on the oxide semiconductor layer 140, and a gate insulating layer 13 and a gate electrode 136d provided in a region overlapping with the oxide semiconductor layer 140 on the gate electrode 136. do.

[0174] In FIG. 9B, the oxide semiconductor layer 140 and the oxide A source electrode or drain electrode 1 is provided in contact with the upper surface of the semiconductor layer 140. 42a, source or drain electrode 142b, and source or drain electrode 14 2a, a source electrode or drain electrode 142b, and a gate electrode provided on the oxide semiconductor layer 140. The gate insulating layer 138 is provided in a region overlapping with the oxide semiconductor layer 140 on the gate insulating layer 138. and a gate electrode 136d.

[0175] In addition, in the configuration shown in FIG. 9, compared to the configuration shown in FIG. 2, some components are omitted. In this case as well, the effect of simplifying the manufacturing process can be obtained.

[0176] As described above, a semiconductor device having a novel structure can be realized according to one embodiment of the disclosed invention. In this embodiment, the transistor 160 and the transistor 162 are stacked. Although the above example has been described, the configuration of the semiconductor device is not limited to this example. In this embodiment, the channel lengths of the transistors 160 and 162 are perpendicular to each other. The positional relationship between the transistor 160 and the transistor 162 is the same as that in the above example. Furthermore, the transistor 160 and the transistor 162 may be overlapped. It may be provided.

[0177] For ease of understanding, the present embodiment will be described with reference to a semiconductor device having a minimum storage unit (1 bit). However, the configuration of the semiconductor device is not limited to this. By appropriately connecting the above semiconductor devices, more advanced semiconductor devices can be constructed. By using multiple devices, it is possible to configure a NAND type or NOR type semiconductor device. The configuration is not limited to that shown in FIG. 1 and can be modified as appropriate.

[0178] The semiconductor device according to this embodiment has a very low off-state current characteristic of the transistor 162. It is possible to retain information for a long period of time. In other words, it is the type of memory required for DRAM. No refresh operation is required, and power consumption can be reduced. It is possible to use the semiconductor device as a photo-emissive semiconductor device.

[0179] In addition, in order to write information by switching the transistor 162, It does not require high voltage and does not have the problem of element degradation. Furthermore, it is possible to turn the transistor on and off with a This allows information to be written and erased, and therefore high-speed operations can be easily achieved. This means that there is no need to erase the information required in a flash memory or the like. There are also benefits to this.

[0180] In addition, transistors using materials other than oxide semiconductors can operate at sufficiently high speed. By using this, it is possible to read out the stored contents at high speed.

[0181] The structures, methods, and the like described in this embodiment may be combined as appropriate with the structures, methods, and the like described in other embodiments. They can be used in combination.

[0182] (Embodiment 2) In this embodiment, a semiconductor device according to one embodiment of the present invention will be described. The operation will be described.

[0183] FIG. 10 shows an example of a circuit diagram of a memory element (hereinafter, also referred to as a memory cell) included in a semiconductor device. The memory cell 200 shown in FIG. 10 includes a first wiring SL (source line) and a second wiring BL (bit line), a third wiring S1 (first signal line), and a fourth wiring S2 (second signal line), A fifth wiring WL (word line), a transistor 201 (first transistor), and a transistor A transistor 202 (a second transistor) and a transistor 203 (a third transistor) The transistor 201 and the transistor 203 are made of an oxide semiconductor or The transistor 201 is formed using an oxide semiconductor. is.

[0184] Here, the gate electrode of the transistor 201 and the source electrode or drain of the transistor 202 are The first wiring is electrically connected to one of the drain electrodes of the transistor 2. The source electrode of the transistor 201 is electrically connected to the drain electrode of the transistor 202. The source electrode of the transistor 203 is electrically connected to the second wiring. The drain electrode of the transistor 203 is electrically connected to the third wiring. The other of the source electrode or the drain electrode of 202 is electrically connected to a fourth wiring, The gate electrode of the transistor 202 is electrically connected to the fifth wiring. It is electrically connected to the gate electrode 203 .

[0185] Next, the operation of the circuit will be specifically described.

[0186] When writing to the memory cell 200, the first wire is set to 0 V, the fifth wire is set to 0 V, and the second wire is set to 0 V. The first wire is set to 0V, and the fourth wire is set to 2V. When writing data "1", the third wire is set to When writing data "0", the third wire is set to 0V. The transistor 203 is turned off and the transistor 202 is turned on. Therefore, before the potential of the third wiring changes, the fourth wiring is set to 0 V, and the transistor 20 2 to the off state.

[0187] As a result, after writing data "1", the node connected to the gate electrode of the transistor 201 After writing data "0", the potential of node A becomes approximately 0 V. A charge corresponding to the potential of the third wiring is accumulated in node A, but the transistor Since the off-current of the transistor 202 is extremely small or substantially zero, The potential of the gate electrode is maintained for a long time. An example is shown in Figure 11.

[0188] Next, when reading the memory cell, the first wire is set to 0V, the fifth wire to 2V, and the fourth wire to The first wiring is set to 0 V, the third wiring is set to 0 V, and the readout circuit connected to the second wiring is set to an operating state. At this time, the transistor 203 is in an on state, and the transistor 202 is in an off state. become.

[0189] When data is “0”, that is, when node A is at approximately 0V, transistor 201 is in the off state. Therefore, the resistance between the second wiring and the first wiring is high. That is, when node A is at about 2 V, transistor 201 is in an on state. The resistance between the wiring and the first wiring is low. The read circuit detects the difference in the resistance state of the memory cell. Therefore, data "0" and "1" can be read out. Although it is set to 0V, it may be in a floating state or may be charged to a potential of 0V or higher. The third wire was set to 0V at the time of insertion, but it may be in a floating state or charged to a potential above 0V. It's okay.

[0190] Note that data "1" and data "0" are defined for convenience, and may be reversed. The above-mentioned operating voltage is an example. When data is “1”, transistor 201 is turned on. Also, the transistor 202 is in an on state during writing and is in an off state except during writing. Also, the transistor 203 may be selected so as to be in an on state during reading. Instead of 2V, the power supply potential VDD of the peripheral logic circuits may be used.

[0191] FIG. 12 shows a block diagram of a semiconductor device according to one embodiment of the present invention having a storage capacity of m×n bits. The circuit diagram is shown.

[0192] A semiconductor device according to one aspect of the present invention includes m fifth wirings and fourth wirings, and n second wirings. A wiring, a third wiring, and a plurality of memory cells 200(1, 1) to 200(m, n) are arranged vertically in m pieces. A memory cell array arranged in a matrix of (rows) x (n) (columns) (m and n are natural numbers) 210, the second wiring and the third wiring driving circuit 211, the fourth wiring and the fifth wiring driving circuit The other peripheral circuits are the read circuit 212 and the read circuit 213. A refresh circuit or the like may be provided as a path.

[0193] Consider memory cell 200(i, j) as a representative of the memory cells. 200(i, j) (i is an integer between 1 and m, and j is an integer between 1 and n) is the second wiring BL(j), a third wiring S1(j), a fifth wiring WL(i) and a fourth wiring S2(i), and the first wiring. A first wiring potential Vs is applied to the first wiring. In addition, the second wirings BL(1) to BL(n) and the third wirings S1(1) to S1 (n) is a fifth wiring to the second wiring and third wiring driving circuit 211 and the readout circuit 212. The lines WL(1) to WL(m) and the fourth wirings S2(1) to S2(m) are the fourth wiring and the fifth wiring These are connected to the wiring drive circuit 213, respectively.

[0194] The operation of the semiconductor device shown in FIG. 12 will be described. In this configuration, writing and Read out.

[0195] When writing data to the memory cells 200(i, 1) to 200(i, n) in the i-th row, The wiring potential Vs is set to 0 V, the fifth wiring WL(i) is set to 0 V, and the second wirings BL(1) to BL(n) are set to The fourth wiring S2(i) is set to 0 V, and the fourth wiring S2(i) is set to 2 V. At this time, the transistor 202 is in an on state. The third wiring S1(1) to S1(n) is 2V for the column to which data “1” is written, The column in which the data "0" is written is set to 0V. (1) Before the potential of S1(n) changes, the fourth wiring S2(i) is set to 0V, and the transistor The resistor 202 is turned off. The unselected fifth wiring is set to 0V, and the unselected fourth wiring is set to is set to 0V.

[0196] As a result, the gate electrode of the transistor 201 of the memory cell in which data "1" has been written The potential of the node connected to the MOSFET (hereinafter referred to as node A) is about 2V, and data "0" is written. The potential of node A of the memory cell is about 0 V. The potential of node A of the unselected memory cell is about remains unchanged.

[0197] When reading data from the memory cells 200(i, 1) to 200(i, n) in the i-th row, The wiring potential Vs is set to 0 V, the fifth wiring WL(i) to 2 V, the fourth wiring S2(i) to 0 V, The third wiring S1(1) to S1(n) are set to 0 V and connected to the second wiring BL(1) to BL(n). The read circuit is set in an operating state. In the read circuit, for example, the resistance state of the memory cell is Depending on the difference in the state, data "0" and "1" can be read out. The line is set to 0V, and the unselected fourth line is set to 0V. Note that the second line is set to 0V during writing. However, it may be in a floating state or charged to a potential of 0V or higher. The wiring is set to 0V, but it may be floating or charged to a potential above 0V. stomach.

[0198] Note that data "1" and data "0" are defined for convenience, and may be reversed. The above-mentioned operating voltage is an example. When data is “1”, transistor 201 is turned on. Also, the transistor 202 is in an on state during writing and is in an off state except during writing. Also, the transistor 203 may be selected so as to be in an on state during reading. Instead of 2V, the power supply potential VDD of the peripheral logic circuits may be used.

[0199] Next, another example of the circuit configuration and operation of the memory element of one embodiment of the present invention will be described.

[0200] An example of a memory cell circuit included in a semiconductor device is shown in FIG. 0 is the first wiring SL, the second wiring BL, the third wiring S1, the fourth wiring S2, and the fifth wiring S3. A wiring WL, a transistor 201 (a first transistor), and a transistor 202 (a second transistor) and transistor 203 (third transistor). The transistor 201 and the transistor 203 are formed using a material other than an oxide semiconductor. The transistor 202 is formed using an oxide semiconductor.

[0201] The circuit of the memory cell 220 shown in FIG. 13 is compared with the circuit of the memory cell 200 shown in FIG. In addition, the directions of the third wiring and the fourth wiring are different. The circuit has the third wiring arranged in the fifth wiring direction (row direction) and the fourth wiring arranged in the second wiring direction The pixels are arranged in a column direction.

[0202] Here, the gate electrode of the transistor 201 and the source electrode or drain of the transistor 202 are The first wiring is electrically connected to one of the drain electrodes of the transistor 2. The source electrode of the transistor 201 is electrically connected to the drain electrode of the transistor 202. The source electrode of the transistor 203 is electrically connected to the second wiring. The drain electrode of the transistor 203 is electrically connected to the third wiring. The other of the source electrode or the drain electrode of 202 is electrically connected to a fourth wiring, The gate electrode of the transistor 202 is electrically connected to the fifth wiring. It is electrically connected to the gate electrode 203 .

[0203] The operation of the circuit of the memory cell 220 shown in FIG. 13 is similar to that of the circuit of the memory cell 200 shown in FIG. Since the operation is similar to that of the first embodiment, a detailed description thereof will be omitted.

[0204] FIG. 14 shows a block diagram of a semiconductor device according to one embodiment of the present invention having a storage capacity of m×n bits. The circuit diagram is shown.

[0205] A semiconductor device according to one aspect of the present invention includes m third wirings and fifth wirings, and n second wirings. A wiring, a fourth wiring, and a plurality of memory cells 220(1, 1) to 220(m, n) are arranged vertically in m pieces. A memory cell array arranged in a matrix of (rows) x (n) (columns) (m and n are natural numbers) 230, the second wiring and fourth wiring driving circuit 231, the third wiring and fifth wiring driving circuit The other peripheral circuits are the read circuit 232 and the read circuit 233. A refresh circuit or the like may be provided as a path.

[0206] The semiconductor device shown in FIG. 14 has a third wiring and a fourth wiring, which are different from the semiconductor device shown in FIG. In other words, the semiconductor device of FIG. 14 has the third wiring in the fifth wiring direction ( The first wiring is arranged in the row direction, and the fourth wiring is arranged in the second wiring direction (column direction).

[0207] Consider memory cell 220(i, j) as a representative of the memory cells. 220(i, j) (i is an integer between 1 and m, and j is an integer between 1 and n) is a second wiring BL(j), a fourth wiring S2(j), a fifth wiring WL(i) and a third wiring S1(i), and the first wiring. A first wiring potential Vs is applied to the first wiring. In addition, the second wirings BL(1) to BL(n) and the fourth wirings S2(1) to S2 (n) is a second wiring, a fourth wiring driving circuit 231 and a read circuit 232, The lines WL(1) to WL(m) and the third wirings S1(1) to S1(m) are the third wiring and the fifth wiring These are connected to the wiring drive circuit 233, respectively.

[0208] The operation of the semiconductor device shown in FIG. 14 will be described. In this configuration, writing is performed for each column, and reading is performed for each column. The overflow is done line by line.

[0209] When writing data to the memory cells 220(1,j) to 220(m,j) in the jth column, The wiring potential Vs is set to 0 V, the fifth wiring WL(1) to WL(m) is set to 0 V, and the second wiring BL(j) The third wiring S1(1) to S1(m) are set to 0V, and the fourth wiring S2(j) is set to 2V. The row where data "1" is written is set to 2V, and the row where data "0" is written is set to 0V. When the test is completed, the fourth wiring S1(1) to S1(m) is turned on before the potential of the third wiring S1(1) to S1(m) changes. The wiring S2(j) is set to 0 V to turn off the transistor 202. Wire 2 is set to 0V, and the unselected fourth wire is set to 0V.

[0210] As a result, the gate electrode of the transistor 201 of the memory cell in which data "1" has been written The potential of the node connected to the MOSFET (hereinafter referred to as node A) is about 2V, and data "0" is written. The potential of node A of the memory cell is about 0 V. The potential of node A of the unselected memory cell is about remains unchanged.

[0211] When reading data from the memory cells 220(i,1) to 220(i,n) in the i-th row, The first wiring WL(i) is set to 0 V, the fifth wiring WL(i) is set to 2 V, and the fourth wiring S2(1) to S2(n) are set to 0 V. The third wiring S1(i) is set to 0 V, and the second wirings BL(1) to BL(n) are connected to the third wiring S1(i). The read circuit is in an operating state. For example, the difference in the resistance state of the memory cell is read by the read circuit. Data "0" and "1" can be read out from the selected fifth line. The unselected third line is set to 0V. Note that the second line is set to 0V during writing, but It does not matter if the third wire is in a grounded state or is charged to a potential of 0V or higher. Although 0V is used, it may be in a floating state or may be charged to a potential of 0V or higher.

[0212] Note that data "1" and data "0" are defined for convenience, and may be reversed. The above-mentioned operating voltage is an example. When data is “1”, transistor 201 is turned on. Also, the transistor 202 is in an on state during writing and is in an off state except during writing. Also, the transistor 203 may be selected so as to be in an on state during reading. Instead of 2V, the power supply potential VDD of the peripheral logic circuits may be used.

[0213] Since a transistor using an oxide semiconductor has an extremely low off-state current, It is possible to retain the memory contents for a much longer period of time. This eliminates the need for refresh operations or makes it possible to reduce the frequency of refresh operations to an extremely low level. Therefore, power consumption can be sufficiently reduced. It is possible to retain the stored contents for a long period of time.

[0214] In addition, high voltage is not required to write information, and there is no problem of element deterioration. Information is written depending on the on / off state of the transistor, allowing for high-speed operation. This can be easily realized. In addition, in order to erase the necessary information in a flash memory, etc. Another advantage is that no additional action is required.

[0215] In addition, transistors using materials other than oxide semiconductors can operate at sufficiently high speed. By using this, it is possible to read out the stored contents at high speed.

[0216] (Embodiment 3) In this embodiment, an example of a circuit configuration and an operation of a memory element different from that in Embodiment 2 will be described. explain.

[0217] An example of a circuit diagram of a memory cell included in a semiconductor device is shown in FIG. 240 includes a first wiring SL, a second wiring BL, a third wiring S1, a fourth wiring S2, and a fifth wiring S3. The wiring WL, the transistor 201 (first transistor), and the transistor 202 (second transistor) The transistor 201 is a transistor having a capacitance element 204. The transistor 201 is formed using a material other than an oxide semiconductor. It is formed using.

[0218] Here, the gate electrode of the transistor 201 and the source electrode or drain of the transistor 202 are One of the drain electrodes and one of the electrodes of the capacitor 204 are electrically connected to each other. The first wiring and the source electrode of the transistor 201 are electrically connected, and the second wiring The drain electrode of the transistor 201 is electrically connected to the third wiring. The other of the source electrode and the drain electrode of the transistor 202 is electrically connected to the fourth transistor. The line and the gate electrode of the transistor 202 are electrically connected, and the fifth wiring and the capacitance element The other electrode of terminal 204 is electrically connected to the other electrode of terminal 204 .

[0219] Next, the operation of the circuit will be specifically described.

[0220] When writing to the memory cell 240, the first wiring is set to 0 V, the fifth wiring is set to 0 V, and the second wiring is set to 0 V. The first wire is set to 0V, and the fourth wire is set to 2V. When writing data "1", the third wire is set to When writing data "0", the third wire is set to 0V. When the write operation is completed, the potential of the third wiring is changed to Before this, the fourth wire is set to 0 V to turn off the transistor 202.

[0221] As a result, after writing data "1", the node connected to the gate electrode of the transistor 201 After writing data "0", the potential of node A is about 2V. It becomes about 0V.

[0222] When reading the memory cell 240, the first wire is set to 0V, the fifth wire to 2V, and the fourth wire to The first wiring is set to 0 V, the third wiring is set to 0 V, and the readout circuit connected to the second wiring is set to an operating state. At this time, the transistor 202 is turned off.

[0223] The state of the transistor 201 when the fifth wire is set to 2 V will be described. The potential of node A, which determines the state of the transistor 201, is determined by the capacitance C1 between the fifth wiring and node A and the It depends on the capacitance C2 between the gate source and drain of the transistor 201.

[0224] FIG. 16 shows the relationship between the potential of the fifth wiring and the potential of the node A. Assume that when the transistor 201 is in the off state, C1 / C2≫1, and when it is in the on state, C1 / C2=1. The threshold voltage of the transistor 201 is set to 2.5 V. When the wiring potential is 2V, node A is approximately 2V in the data "0" state. On the other hand, in the data "1" state, node A is about 3.25V The transistor 201 is turned on. When the memory cell is in the on state, it has a low resistance state, and when it is in the off state, it has a high resistance state. The difference in resistance state allows data "0" or "1" to be read out. If this is not the case, that is, when the potential of the fifth wire is 0V, node A is approximately 0V for data "0". When V and data are "1", node A is approximately 2V, and the transistor 201 is in the off state. It becomes a state of mind.

[0225] Although the third wiring was set to 0V during reading, it may be set in a floating state or charged to a potential of 0V or higher. Data "1" and data "0" are defined for convenience and should not be reversed. That's okay.

[0226] The above-mentioned operating voltage is an example. The potential of the third wiring during writing is When the potential of the fifth wiring is 0V, the transistor 201 is turned off. In the range where the bit is in the off state, the potentials of data "0" and "1" can be selected. When the data is "0", the transistor 201 is turned off. The transistor 201 should be selected so that it is turned on when the input is "1". The threshold voltage of the transistor 201 is also an example. Any threshold value may be used as long as it is within the range.

[0227] The semiconductor device according to one embodiment of the present invention shown in FIG. 17 includes m fifth wirings and a fourth wiring, n second wirings and third wirings and a plurality of memory cells 240 (1, 1) to (m, n) Memory cells arranged in a matrix of m rows x n columns (m and n are natural numbers). The array 250, the second wiring and the third wiring driving circuit 211, the fourth wiring and the fifth wiring It is composed of peripheral circuits such as a line driving circuit 213 and a readout circuit 212. A refresh circuit and the like may be provided as peripheral circuits.

[0228] Consider memory cell 240(i, j) as a representative of the memory cells. 240(i, j) (i is an integer between 1 and m, and j is an integer between 1 and n) is the second wiring BL(j), a third wiring S1(j), a fifth wiring WL(i) and a fourth wiring S2(i), and the first wiring. A first wiring potential Vs is applied to the first wiring. In addition, the second wirings BL(1) to BL(n) and the third wirings S1(1) to S1 (n) is a fifth wiring to the second wiring and third wiring driving circuit 211 and the readout circuit 212. The lines WL(1) to WL(m) and the fourth wirings S2(1) to S2(m) are the fourth wiring and the fifth wiring These are connected to the wiring drive circuit 213, respectively.

[0229] The operation of the semiconductor device shown in FIG. 17 will be described. In this configuration, writing and Read out.

[0230] When writing data to the memory cells 240(i, 1) to 240(i, n) in the i-th row, The wiring potential Vs is set to 0 V, the fifth wiring WL(i) is set to 0 V, and the second wirings BL(1) to BL(n ) is set to 0 V, and the fourth wiring S2(i) is set to 2 V. At this time, the transistor 202 is in an on state. The third wirings S1(1) to S1(n) are in a state where the columns to write data “1” are at 2V and the The column to which the data "0" is written is set to 0V. Before the potential of S1(1) to S1(n) changes, the fourth wiring S2(i) is set to 0V, and the transistor The transistor 202 is turned off. The unselected fifth wiring is set to 0 V, and the unselected fourth wiring is set to The line is at 0V.

[0231] As a result, the gate voltage of the transistor 201 of the memory cell in which data "1" is written The potential of the node connected to the pole (hereinafter, node A) is about 2V. After writing data “0”, In the case of a non-selected memory cell, the potential of node A is approximately 0 V. In addition, the potential of node A of the non-selected memory cell does not change. stomach.

[0232] When reading from the memory cells 240(i, 1) to 240(i, n) in the i-th row, The wiring potential Vs is set to 0 V, the fifth wiring WL(i) to 2 V, the fourth wiring S2(i) to 0 V, The third wiring S1(1) to S1(n) are set to 0 V and connected to the second wiring BL(1) to BL(n). The read circuit is put into an operating state. At this time, the transistor 202 is turned off. In addition, the unselected fifth wiring is set to 0V, and the unselected fourth wiring is set to 0V.

[0233] The state of the transistor 201 during reading will now be described. As already explained, If the resistor 201 is off and C1 / C2>>1, and on, C1 / C2=1, then The relationship between the potential of the fifth wiring and the potential of the node A is shown in FIG. The threshold voltage of 201 is 2.5 V. The potential of the fifth line of the unselected memory cells is 0 V. Therefore, the node A of the memory cell having data "0" is about 0V, and the node B of the memory cell having data "1" is about 0V. The node A of the memory cell becomes about 2 V, and the transistor 201 is turned off. In the memory cell in the i-th row, the potential of the fifth line is 2V, so that the memory cell has data "0". The node A of the memory cell is at about 2 V, and the transistor 201 is in an off state. The node A of the memory cell having a "1" is at about 3.25V, and the transistor 201 is turned on. The memory cell is in a low resistance state when the transistor 201 is on and in a high resistance state when it is off. As a result, only the memory cells in the i-th row that have data “0” are The read circuit reads the data from the difference in the load resistance connected to the second wiring. The data "0" or "1" can be read out.

[0234] Although the third wiring was set to 0V during reading, it may be set in a floating state or charged to a potential of 0V or higher. Data "1" and data "0" are defined for convenience and should not be reversed. That's okay.

[0235] The above-mentioned operating voltage is an example. The potential of the third wiring during writing is When the potential of the fifth wiring is 0V, the transistor 201 is turned off. In the range where the bit is in the off state, the potentials of data "0" and "1" can be selected. When the data is "0", the transistor 201 is turned off. The transistor 201 should be selected so that it is turned on when the input is "1". The threshold voltage of the transistor 201 is also an example. Any threshold value may be used as long as it is within the range.

[0236] Since a transistor using an oxide semiconductor has an extremely low off-state current, It is possible to retain the memory contents for a much longer period of time. This eliminates the need for refresh operations or makes it possible to reduce the frequency of refresh operations to an extremely low level. Therefore, power consumption can be sufficiently reduced. It is possible to retain the stored contents for a long period of time.

[0237] In addition, high voltage is not required to write information, and there is no problem of element deterioration. Information is written depending on the on / off state of the transistor, allowing for high-speed operation. This can be easily realized. In addition, in order to erase the necessary information in a flash memory, etc. Another advantage is that no additional action is required.

[0238] In addition, transistors using materials other than oxide semiconductors can operate at sufficiently high speed. By using this, it is possible to read out the stored contents at high speed.

[0239] Next, another example of the circuit configuration and operation of the memory element of one embodiment of the present invention will be described.

[0240] An example of a memory cell circuit included in a semiconductor device is shown in FIG. 0 includes the first wiring SL, the second wiring BL, the third wiring S1, the fourth wiring S2, and the The wiring WL of No. 5, the transistor 201, the transistor 202, the capacitor element 204, The transistor 201 is formed using a material other than an oxide semiconductor. The transistor 202 is formed using an oxide semiconductor.

[0241] The circuit of the memory cell 260 shown in FIG. 18 is different from the circuit of the memory cell 240 shown in FIG. The third wiring and the fourth wiring have different directions. That is, in the memory cell 260 of FIG. The wiring is arranged in the fifth wiring direction (row direction), and the fourth wiring is arranged in the second wiring direction (column direction). The configuration is such that

[0242] Here, the gate electrode of the transistor 201 and the source electrode or drain of the transistor 202 are One of the drain electrodes and one of the electrodes of the capacitor 204 are electrically connected to each other. The first wiring and the source electrode of the transistor 201 are electrically connected, and the second wiring The drain electrode of the transistor 201 is electrically connected to the third wiring. The other of the source electrode and the drain electrode of the transistor 202 is electrically connected to the fourth transistor. The line and the gate electrode of the transistor 202 are electrically connected, and the fifth wiring and the capacitance element The other electrode of terminal 204 is electrically connected to the other electrode of terminal 204 .

[0243] The operation of the circuit of the memory cell 260 shown in FIG. 18 is the same as that of the circuit of the memory cell 240 shown in FIG. Since the operation is similar to that of the first embodiment, a detailed description thereof will be omitted.

[0244] FIG. 19 shows a block diagram of a semiconductor device according to one embodiment of the present invention having a storage capacity of m×n bits. The circuit diagram is shown.

[0245] A semiconductor device according to one aspect of the present invention includes m third wirings and fifth wirings, and n second wirings. A wiring, a fourth wiring, and a plurality of memory cells 260(1, 1) to 260(m, n) are arranged vertically in m pieces. A memory cell array arranged in a matrix of (rows) x (n) (columns) (m and n are natural numbers) 270, the second wiring and fourth wiring driving circuit 231, the third wiring and fifth wiring driving circuit The other peripheral circuits are the read circuit 232 and the read circuit 233. A refresh circuit or the like may be provided as a path.

[0246] The semiconductor device shown in FIG. 19 has a third wiring and a fourth wiring, which are different from the semiconductor device shown in FIG. In other words, the semiconductor device of FIG. 19 has the third wiring in the fifth wiring direction ( The first wiring is arranged in the row direction, and the fourth wiring is arranged in the second wiring direction (column direction).

[0247] Consider memory cell 260(i, j) as a representative of each memory cell. 260(i, j) (i is an integer between 1 and m, and j is an integer between 1 and n) is the second wiring BL(j), a fourth wiring S2(j), a fifth wiring WL(i) and a third wiring S1(i), and the first wiring. A first wiring potential Vs is applied to the first wiring. In addition, the second wirings BL(1) to BL(n) and the fourth wirings S2(1) to S2 (n) is a second wiring, a fourth wiring driving circuit 231 and a read circuit 232, The lines WL(1) to WL(m) and the third wirings S1(1) to S1(m) are the third wiring and the fifth wiring These are connected to the wiring drive circuit 233, respectively.

[0248] The operation of the semiconductor device shown in FIG. 19 is similar to that of the semiconductor device shown in FIG. Detailed explanation will be omitted.

[0249] Since a transistor using an oxide semiconductor has an extremely low off-state current, It is possible to retain the memory contents for a much longer period of time. This eliminates the need for refresh operations or makes it possible to reduce the frequency of refresh operations to an extremely low level. Therefore, power consumption can be sufficiently reduced. It is possible to retain the stored contents for a long period of time.

[0250] In addition, high voltage is not required to write information, and there is no problem of element deterioration. Information is written depending on the on / off state of the transistor, allowing for high-speed operation. This can be easily realized. In addition, in order to erase the necessary information in a flash memory, etc. Another advantage is that no additional action is required.

[0251] In addition, transistors using materials other than oxide semiconductors can operate at sufficiently high speed. By using this, it is possible to read out the stored contents at high speed.

[0252] (Embodiment 4) In this embodiment, an example of a circuit configuration and an operation of a memory element different from those in the second and third embodiments will be described. We will explain about this.

[0253] FIG. 20 shows an example of a circuit diagram of a memory cell included in a semiconductor device. The memory cell 280a shown in FIG. 20B and the memory cell 280b shown in FIG. 13. Compared to the memory cell 200 and the memory cell 220 shown in FIG. This is a configuration in which the series connection relationship of the transistors is reversed.

[0254] Here, the memory cell 280a shown in FIG. 20A has a gate electrode of a transistor 201 and The source electrode or the drain electrode of the transistor 202 is electrically connected to the The first wiring and the source electrode of the transistor 203 are electrically connected to each other. The drain electrode of the transistor 203 and the source electrode of the transistor 201 are electrically connected The second wiring and the drain electrode of the transistor 201 are electrically connected to each other. The third wiring is electrically connected to the source electrode or the drain electrode of the transistor 202. The fourth wiring and the gate electrode of the transistor 202 are electrically connected to each other. The fifth wiring and the gate electrode of the transistor 203 are electrically connected to each other. is.

[0255] The memory cell 280b shown in FIG. 20B is the same as the memory cell circuit shown in FIG. In comparison with FIG. 20(B), the directions of the third and fourth wirings are different. The memory cell circuit has the fourth wiring arranged in the second wiring direction (column direction) and the third wiring arranged in the fifth The elements are arranged in the wiring direction (row direction).

[0256] The circuit of the memory cell 280a shown in FIG. 20(A) and the circuit of the memory cell 280b shown in FIG. 20(B) The operation of the circuit is similar to that of the memory cell 200 shown in FIG. 10 and the memory cell 220 shown in FIG. Since the operation of the circuit is similar to that of the circuit described above, a detailed description thereof will be omitted.

[0257] (Embodiment 5) In this embodiment, an example of a circuit configuration and an operation of a memory element different from those in Embodiments 2 to 4 will be described. We will explain about this.

[0258] An example of a circuit diagram of a memory cell included in a semiconductor device is shown in FIG. The circuit of 290 is different from the circuit of the memory cell 200 of FIG. A capacitive element is provided between the first and second electrodes.

[0259] The memory cell 290 shown in FIG. 21 includes a first wiring SL, a second wiring BL, a third wiring S1, and , the fourth wiring S2, the fifth wiring WL, the transistor 201, and the transistor 202. The transistor 201 is composed of a transistor 203 and a capacitor 205. The transistor 203 is formed using a material other than an oxide semiconductor. The stator 202 is formed using an oxide semiconductor.

[0260] Here, the gate electrode of the transistor 201 and the source electrode or drain of the transistor 202 are One of the drain electrodes and one of the electrodes of the capacitor 205 are electrically connected to each other. The first wiring, the source electrode of the transistor 201, and the other electrode of the capacitor 205 are , electrically connected to the drain electrode of the transistor 201 and the source electrode of the transistor 203. The drain electrode of the transistor 203 is electrically connected to the second wiring. The third wiring is electrically connected to the source electrode of the transistor 202. The other of the drain electrodes is electrically connected to the fourth wiring and the gate of the transistor 202. The fifth wiring and the gate electrode of the transistor 203 are electrically connected to each other. , are electrically connected.

[0261] The operation of the memory cell circuit shown in FIG. 21 is similar to that of the memory cell circuit shown in FIG. By including such a capacitor element 205, the retention characteristic is improved. Improve.

[0262] (Embodiment 6) An example of a readout circuit included in a semiconductor device according to one embodiment of the present invention will be described with reference to FIG. do.

[0263] The read circuit shown in FIG. 22 includes a transistor 206 and a differential amplifier.

[0264] During reading, terminal A is connected to the second wiring to which the memory cell to be read is connected. A bias voltage Vbias is applied to the gate electrode of the transistor 206. Pass an electric current.

[0265] The resistance of the memory cell varies depending on the data stored in it, either "1" or "0". When the transistor 201 of the selected memory cell is in an on state, the resistance is low. When the transistor 201 of the memory cell is in an off state, the resistance is high.

[0266] When the memory cell is in a high resistance state, the potential of terminal A becomes higher than the reference potential Vref, and the differential amplifier On the other hand, when the memory cell is in a low resistance state, the terminal The potential of terminal A becomes lower than the reference potential Vref, and the differential amplifier outputs data "0". Be encouraged.

[0267] In this manner, the read circuit can read data from the memory cells. The read circuit of this embodiment is an example. Other known circuits may be used. For example, A charge circuit may be provided. A second wiring for reference is connected instead of the reference potential Vref. Instead of the differential amplifier, a latch type sense amplifier may be used.

[0268] (Embodiment 7) In this embodiment, an example of an electronic device equipped with the semiconductor device obtained in the above embodiment will be described. The semiconductor device obtained in the above embodiment operates without the supply of power. In addition, the data can be retained even if the data is written or erased. Furthermore, the operation is also fast. Therefore, the semiconductor device can be used to realize a new configuration of a power supply. It is possible to provide a child device. The semiconductor device is then mounted on a circuit board or the like and installed inside each electronic device.

[0269] FIG. 23A shows a notebook type personal computer including the semiconductor device according to the above embodiment. The computer is composed of a main body 301, a housing 302, a display unit 303, a keyboard 304, etc. The semiconductor device according to one embodiment of the present invention is provided in a notebook personal computer. By applying this technology, it is possible to retain information even when there is no power supply. No degradation occurs due to writing and erasing. Furthermore, the operation is fast. The semiconductor device according to the present invention is preferably applied to a notebook personal computer. It is.

[0270] FIG. 23B shows a personal digital assistant (PDA) including the semiconductor device according to the above embodiment. The main body 311 includes a display unit 313, an external interface 315, and operation buttons 314. The present invention also includes a stylus 312 as an accessory for operation. By applying the semiconductor device according to the present invention to a PDA, information can be retained even when there is no power supply. In addition, there is no degradation caused by writing and erasing. For this reason, it is preferable to apply the semiconductor device according to one aspect of the present invention to a PDA. It is.

[0271] FIG. 23C shows an example of electronic paper including the semiconductor device according to the above embodiment. The electronic book 320 is shown. The electronic book 320 is made up of two housings, a housing 321 and a housing 323. The housing 321 and the housing 323 are integrated with each other by a shaft portion 337. The opening and closing operation can be performed around the axis 337. The semiconductor device according to one embodiment of the present invention can be used like a paper book. By applying this technology to electronic paper, it is possible to retain information even when there is no power supply. In addition, there is no degradation caused by writing and erasing. Furthermore, the operation is fast. For this reason, it is preferable to apply the semiconductor device according to one embodiment of the present invention to electronic paper. do.

[0272] A display unit 325 is incorporated in the housing 321, and a display unit 327 is incorporated in the housing 323. The display unit 325 and the display unit 327 may be configured to display a continuous screen, or may be configured to display different images. By configuring to display different screens, for example, A text is displayed on the right display unit (display unit 325 in FIG. 23(C)) and In (C), an image can be displayed on the display unit 327).

[0273] FIG. 23C shows an example in which an operation unit and the like are provided on the housing 321. The body 321 includes a power source 331, operation keys 333, a speaker 335, etc. The page can be turned by pressing the arrow 333. In addition, a keyboard and a pointer are installed on the same surface as the display unit of the housing. The housing may be provided with an external display device or the like. Connection terminals (earphone terminal, USB terminal, AC adapter and USB cable, etc.) A configuration including a terminal that can be connected to various cables, a recording medium insertion portion, etc. Furthermore, the electronic book 320 may be configured to have the functionality of an electronic dictionary.

[0274] The electronic book 320 may be configured to transmit and receive information wirelessly. It is also possible to purchase and download desired book data from the child book server. It is possible.

[0275] Electronic paper can be applied to any field that displays information. For example, in addition to e-books, posters, in-car advertisements on trains and other vehicles, credit cards, etc. The present invention can be applied to displays on various cards such as gift cards.

[0276] FIG. 23D illustrates a mobile phone including the semiconductor device according to the above embodiment. The phone is made up of two housings, housing 340 and housing 341. Housing 341 has a front display panel 342, speaker 343, microphone 344, pointing device 3 46, a camera lens 347, and an external connection terminal 348. The mobile phone includes a solar cell 349 for charging the mobile phone, an external memory slot 350, etc. The antenna is built into the housing 341. By applying the body device to a mobile phone, information can be retained even when there is no power supply. In addition, there is no degradation caused by writing and erasing. Furthermore, the operation is fast. For this reason, it is preferable to apply the semiconductor device according to one embodiment of the present invention to a mobile phone. be.

[0277] The display panel 342 has a touch panel function, and in FIG. The mobile phone has a solar cell 34 A boost circuit is implemented to boost the voltage output by 9 to the voltage required by each circuit. In addition to the above configuration, the device may be configured to incorporate a non-contact IC chip, a small recording device, etc. It is also possible.

[0278] The display direction of the display panel 342 changes appropriately depending on the usage mode. A camera lens 347 is provided on the same surface as the camera 42, making video calling possible. The speaker 343 and microphone 344 are not limited to voice calls, but also video calls, recording, playback, etc. Furthermore, the housing 340 and the housing 341 can be slid, and as shown in FIG. It can be folded from the unfolded state to the overlapping state, making it compact and suitable for carrying. It is Noh.

[0279] The external connection terminal 348 can be connected to various cables such as an AC adapter or a USB cable. The external memory slot 350 can store a recording medium. It can store and move larger amounts of data. In addition to the above features, It may also be equipped with an infrared communication function, a television receiving function, etc.

[0280] FIG. 23E shows a digital camera including the semiconductor device according to the above embodiment. The digital camera is comprised of a main body 361, a display unit (A) 367, an eyepiece 363, and an operation switch 364. , a display unit (B) 365, a battery 366, etc. By applying the semiconductor device according to the present invention to a digital camera, information can be stored even when there is no power supply. In addition, there is no deterioration caused by writing and erasing. For this reason, the semiconductor device according to one embodiment of the present invention is suitable for use in a digital camera. It is preferable to use

[0281] FIG. 23F illustrates a television set including the semiconductor device according to the above embodiment. In the vision device 370, a display unit 373 is built into a housing 371. In this case, the stand 375 is used to hold the case in place. This shows the configuration that supported 371.

[0282] The television device 370 can be operated using an operation switch provided on the housing 371 or a separate remote control. This can be done by the operation device 380. The remote control operation device 380 has an operation key 379. This allows you to control the channel and volume, and to operate the image displayed on the display unit 373. In addition, the remote control operation device 380 can receive the output from the remote control operation device 380. A display unit 377 for displaying information to be displayed may be provided. By applying the body device to a television device, information can be retained even when there is no power supply. In addition, there is no degradation caused by writing and erasing. For this reason, the semiconductor device according to one embodiment of the present invention is applied to a television set. This is preferable.

[0283] It is preferable that the television device 370 is configured to include a receiver, a modem, etc. The receiver can receive general television broadcasts. By connecting to a wired or wireless communication network, The communication of information between a single person (e.g., a sender and a receiver, or between receivers themselves) or between two people (e.g., a sender and a receiver, or a receiver and another receiver) It is possible.

[0284] The structures, methods, and the like described in this embodiment may be combined as appropriate with the structures, methods, and the like described in other embodiments. Can be used in combination [Explanation of symbols]

[0285] 100 Substrates 102 Protective layer 104 Semiconductor area 106 Element isolation insulating layer 108a Gate insulating layer 110a Gate electrode 112 Insulating layer 114 Impurity region 116 Channel formation region 118 Sidewall insulating layer 120 High concentration impurity region 122 Metal layer 124 Metal compound area 126 Interlayer Insulation Layer 128 Interlayer Insulation Layer 130a source electrode or drain electrode 130b Source electrode or drain electrode 130c electrode 130d electrode 132 Insulating Layer 134 Conductive Layer 136a electrode 136b Electrode 136c electrode 136d Gate electrode 138 Gate Insulation Layer 140 Oxide semiconductor layer 142a Source electrode or drain electrode 142b Source or drain electrode 144 Protective Insulation Layer 146 Interlayer Insulation Layer 148 Conductive Layer 150a electrode 150b electrode 150c electrode 150d electrode 150e electrode 152 Insulating layer 154a electrode 154b electrode 154c electrode 154d electrode 154e electrode 160 Transistors 162 Transistor 200 memory cells 201 Transistor 202 Transistor 203 Transistor 204 Capacitive element 205 Capacitive element 206 Transistor 210 Memory Cell Array 211 Second wiring and third wiring drive circuit 212 Readout circuit 213 Fourth wiring and fifth wiring drive circuit 220 memory cells 230 Memory Cell Array 231 Second wiring and fourth wiring drive circuit 232 Readout circuit 233 Third wiring and fifth wiring drive circuit 240 memory cells 250 Memory Cell Array 260 memory cells 270 Memory Cell Array 280a Memory Cell 280b memory cell 290 memory cells 301 Main unit 302 Case 303 Display section 304 Keyboard 311 Main unit 312 Stylus 313 Display section 314 Operation button 315 External Interface 320 e-books 321 Case 323 Case 325 Display section 327 Display section 331 Power supply 333 Operation Key 335 Speaker 337 Shaft 340 Case 341 Case 342 Display Panel 343 Speakers 344 Microphone 345 Operation Key 346 Pointing Device 347 Camera Lenses 348 External connection terminal 349 Solar Cells 350 external memory slot 361 Main unit 363 Eyepiece 364 Operation Switch 365 Display section (B) 366 Battery 367 Display section (A) 370 Television Equipment 371 Case 373 Display section 375 Stand 377 Display section 379 Operation Key 380 Remote Controlled Device

Claims

1. A plurality of circuits arranged in a matrix form are included, The circuit comprises: a first transistor having a channel formation region including silicon; a second transistor having a channel formation region including an oxide semiconductor; a gate of the first transistor is electrically connected to one of a source and a drain of the second transistor, a first conductive layer having a region functioning as a gate electrode of the first transistor above a channel formation region of the first transistor; a first insulating layer having a region disposed above the first conductive layer; a second conductive layer having a region in contact with an upper surface of the first insulating layer and functioning as a gate electrode of the second transistor; a second insulating layer having a region in contact with a top surface of the first insulating layer and a region in contact with a side surface of the second conductive layer; a third insulating layer having a region in contact with an upper surface of the second insulating layer and including silicon oxide; an oxide semiconductor layer having a region in contact with an upper surface of the third insulating layer and overlapping with the second conductive layer with the third insulating layer interposed therebetween; a fourth insulating layer having a region in contact with a top surface of the oxide semiconductor layer and including silicon oxide; a fifth insulating layer having a region in contact with an upper surface of the fourth insulating layer; a third conductive layer having a region provided above the fifth insulating layer and electrically connected to one of a source region and a drain region of the first transistor; a fourth conductive layer provided above the fifth insulating layer and electrically connected to the first conductive layer and one of a source region and a drain region of the second transistor; the fourth insulating layer and the fifth insulating layer are provided with a first opening for electrically connecting the fourth conductive layer to the first conductive layer, and a second opening for electrically connecting the fourth conductive layer to one of a source region and a drain region of the second transistor; the oxide semiconductor layer includes In—O, the oxide semiconductor layer does not have a region overlapping with the first conductive layer in a plan view of the circuit, In a plan view of the circuit, the second conductive layer has a region extending in a first direction, In a plan view of the circuit, the first opening and the second opening are arranged side by side in a second direction intersecting the first direction.

2. A plurality of circuits arranged in a matrix form are included, The circuit comprises: a first transistor having a channel formation region including silicon; a second transistor having a channel formation region including an oxide semiconductor; a gate of the first transistor is electrically connected to one of a source and a drain of the second transistor, a first conductive layer having a region functioning as a gate electrode of the first transistor above a channel formation region of the first transistor; a first insulating layer having a region disposed above the first conductive layer; a second conductive layer having a region in contact with an upper surface of the first insulating layer and functioning as a gate electrode of the second transistor; a second insulating layer having a region in contact with a top surface of the first insulating layer and a region in contact with a side surface of the second conductive layer; a third insulating layer having a region in contact with an upper surface of the second insulating layer and including silicon oxide; an oxide semiconductor layer having a region in contact with an upper surface of the third insulating layer and overlapping with the second conductive layer with the third insulating layer interposed therebetween; a fourth insulating layer having a region in contact with a top surface of the oxide semiconductor layer and including silicon oxide; a fifth insulating layer having a region in contact with an upper surface of the fourth insulating layer; a third conductive layer having a region provided above the fifth insulating layer and electrically connected to one of a source region and a drain region of the first transistor; a fourth conductive layer provided above the fifth insulating layer and electrically connected to the first conductive layer and one of a source region and a drain region of the second transistor; the fourth insulating layer and the fifth insulating layer are provided with a first opening for electrically connecting the fourth conductive layer to the first conductive layer, and a second opening for electrically connecting the fourth conductive layer to one of a source region and a drain region of the second transistor; the oxide semiconductor layer includes In—O, the oxide semiconductor layer does not have a region overlapping with the first conductive layer in a plan view of the circuit, In a plan view of the circuit, the second conductive layer has a region extending in a first direction, In a plan view of the circuit, the first opening and the second opening are arranged side by side in a second direction intersecting the first direction, a channel formation region of the first transistor having a region where a channel length direction intersects with a channel length direction of the second transistor.

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