3D semiconductor device

Abstract

To provide a three-dimensional semiconductor device.SOLUTION: The three-dimensional semiconductor device includes main separation structures MS disposed on a substrate and extending in a first direction parallel to a surface of the substrate; gate electrodes disposed between the main separation structures; a first secondary separation structure SS1 penetrating through the gate electrodes between the main separation structures and including a first linear portion SS1a and a second linear portion SS1b having end portions opposing each other; and second secondary separation structures SS2 disposed between the first secondary separation structure and the main separation structures and penetrating through the gate electrodes. The second secondary separation structures SS2 have end portions opposing each other between the second linear portion SS1b and the main separation structures MS.SELECTED DRAWING: Figure 8

Description

[Technical field]

[0001] The present invention relates to semiconductor devices, and more particularly to three-dimensional semiconductor devices that include gate electrodes. [Background technology]

[0002] Semiconductor elements including gate electrodes stacked in a direction perpendicular to the surface of a semiconductor substrate have been developed. In order to increase the integration density of semiconductor elements, the number of stacked gate electrodes is being increased. As the number of gate electrodes stacked in a direction perpendicular to the surface of a semiconductor substrate increases, the difficulty of the gate formation process increases, and there is a concern that unexpected defects may occur. Summary of the Invention [Problem to be solved by the invention]

[0003] The problem to be solved by the technical idea of ​​the present invention is to provide a three-dimensional semiconductor device.

[0004] The problem to be solved by the technical concept of the present invention is to provide a three-dimensional semiconductor device capable of high integration and a method for forming the same. [Means for solving the problem]

[0005] According to an embodiment of the technical concept of the present invention, there is provided a three-dimensional semiconductor device, the three-dimensional semiconductor device including: a main isolation structure disposed on a substrate and extending in a first direction parallel to a surface of the substrate; a gate electrode disposed between the main isolation structures; a first auxiliary isolation structure penetrating the gate electrode between the main isolation structures and including a first line portion and a second line portion having end portions facing each other; and a second auxiliary isolation structure disposed between the first auxiliary isolation structure and the main isolation structure and penetrating the gate electrode, the second auxiliary isolation structure having end portions facing each other between the second line portion and the main isolation structure.

[0006] According to an embodiment of the technical concept of the present invention, there is provided a three-dimensional semiconductor device, comprising: a main isolation structure across a memory cell array region and a connecting region of a substrate; a gate electrode stacked in sequence on the memory cell array region between the main isolation structures and extending into the connecting region, the gate electrode having a pad region arranged in a stepped manner in the connecting region; a first auxiliary isolation structure penetrating the gate electrode between the main isolation structures; and a second auxiliary isolation structure disposed between the first auxiliary isolation structure and the main isolation structure and penetrating the gate electrode. The first auxiliary isolation structure includes a first line portion extending across the memory cell array region to the connecting region, and a second line portion disposed on the connecting region and having an end portion facing the first line portion in the connecting region. The second auxiliary isolation structure has end portions facing each other in the connecting region.

[0007] According to an embodiment of the technical concept of the present invention, there is provided a three-dimensional semiconductor device, comprising: a substrate having a memory cell array region and a connecting region adjacent to the memory cell array region; a gate electrode stacked in a direction perpendicular to a surface of the substrate in the memory cell array region and extending into the connecting region; a main isolation structure penetrating the gate electrode across the memory cell array region and the connecting region; a first auxiliary isolation structure penetrating the gate electrode between the main isolation structure and including a first line portion and a second line portion having end portions facing each other in the connecting region; and a second auxiliary isolation structure located on both sides of the first auxiliary isolation structure and penetrating the gate electrode between the first auxiliary isolation structure and the main isolation structure. The second auxiliary isolation structure has end portions facing each other and spaced apart from each other in the connecting region. Each of the second auxiliary isolation structures has a length shorter than the first and second line portions of the first auxiliary isolation structure. Effect of the Invention

[0008] According to an embodiment of the technical concept of the present invention, a three-dimensional semiconductor device capable of increasing the number of gate electrode layers can be provided, thereby improving the integration density of the semiconductor device. [Brief description of the drawings]

[0009] [Figure 1] 1 is a schematic block diagram of a three-dimensional semiconductor device according to an embodiment of the present invention. [Diagram 2] 1 is a circuit diagram conceptually illustrating an illustrative example of a memory cell array region of a three-dimensional semiconductor device in accordance with an embodiment of the present invention. [Diagram 3] 1 is a plan view conceptually illustrating an illustrative example of a three-dimensional semiconductor device in accordance with an embodiment of the present invention. [Figure 4] 4 is an enlarged plan view of a portion of FIG. 3 illustrating an illustrative example of a three-dimensional semiconductor device according to an embodiment of the present invention. [Diagram 5] 4 is an enlarged plan view of a portion of FIG. 3 illustrating an illustrative example of a three-dimensional semiconductor device according to an embodiment of the present invention. [Figure 6] 6 is a cross-sectional view showing an area taken along line II' in FIG. 5. [Figure 7] 6 is a cross-sectional view showing an area taken along line II-II' in FIG. 5. [Figure 8] 4 and 5. This is an enlarged plan view of the portions indicated by "B1" and "B2" in FIG. 4 and FIG. 5 to illustrate an illustrative example of a three-dimensional semiconductor device according to one embodiment of the present invention. [Figure 9a] 9 is a cross-sectional view showing an area taken along lines III-III' and IV-IV' in FIG. 8. [Figure 9b] 9 is a cross-sectional view showing an area taken along lines VV' and VI-VI' in FIG. 8. [Figure 9c] 9 is a cross-sectional view showing an area taken along line VII-VII' in FIG. 8. [Figure 10] 1 is a perspective view illustrating an illustrative example of a gate electrode of a three-dimensional semiconductor device according to an embodiment of the present invention. [Figure 11] 11 is a perspective view showing a modified example of a gate electrode of a three-dimensional semiconductor device according to an embodiment of the present invention. FIG. [Figure 12] 4 and 5 to explain a modified example of a three-dimensional semiconductor device according to an embodiment of the present invention. FIG. [Figure 13a] 13 is a cross-sectional view showing an area taken along lines III-III' and IV-IV' in FIG. 12. [Figure 13b] 13 is a cross-sectional view showing an area taken along lines VV' and VI-VI' in FIG. 12. [Figure 13c] 13 is a cross-sectional view showing an area taken along line VII-VII' in FIG. 12. [Figure 14] 4 and 5. This is an enlarged plan view of the portions indicated by "B1" and "B2" in FIG. 4 and FIG. 5 to explain another modified example of a three-dimensional semiconductor device according to an embodiment of the present invention. [Figure 15] 4 and 5. This is an enlarged plan view of the portions indicated by "B1" and "B2" in FIG. 4 and FIG. 5 to explain another modified example of a three-dimensional semiconductor device according to an embodiment of the present invention. [Figure 16] 11 is a perspective view showing yet another modified example of a gate electrode of a three-dimensional semiconductor device according to an embodiment of the present invention. FIG. [Figure 17] 13 is a plan view illustrating yet another modified example of a three-dimensional semiconductor device according to an embodiment of the present invention. FIG. [Figure 18a] 1A to 1C are cross-sectional views illustrating an illustrative example of a method for forming a three-dimensional semiconductor device according to an embodiment of the present invention. [Figure 18b] 1A to 1C are cross-sectional views illustrating an illustrative example of a method for forming a three-dimensional semiconductor device according to an embodiment of the present invention. [Figure 19a] 1A to 1C are cross-sectional views illustrating an illustrative example of a method for forming a three-dimensional semiconductor device according to an embodiment of the present invention. [Figure 19b] 1A to 1C are cross-sectional views illustrating an illustrative example of a method for forming a three-dimensional semiconductor device according to an embodiment of the present invention. [Figure 20a] 1A to 1C are cross-sectional views illustrating an illustrative example of a method for forming a three-dimensional semiconductor device according to an embodiment of the present invention. [Figure 20b] 1A to 1C are cross-sectional views illustrating an illustrative example of a method for forming a three-dimensional semiconductor device according to an embodiment of the present invention. [Figure 21a] 1A to 1C are cross-sectional views illustrating an illustrative example of a method for forming a three-dimensional semiconductor device according to an embodiment of the present invention. [Figure 21b] 1A to 1C are cross-sectional views illustrating an illustrative example of a method for forming a three-dimensional semiconductor device according to an embodiment of the present invention. [Figure 22a] 1A to 1C are cross-sectional views illustrating an illustrative example of a method for forming a three-dimensional semiconductor device according to an embodiment of the present invention. [Figure 22b] 1A to 1C are cross-sectional views illustrating an illustrative example of a method for forming a three-dimensional semiconductor device according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] An illustrative example of a three-dimensional semiconductor device according to the inventive concepts will be described with reference to Figure 1. Figure 1 is a schematic block diagram of a semiconductor device according to one embodiment of the inventive concepts.

[0011] 1, a three-dimensional semiconductor device 1 may include a memory cell array area MA, a row decoder 3, a page buffer 4, a column decoder 5, and a control circuit 6. The memory cell array area MA may include a memory block BLK.

[0012] The memory cell array region MA may include memory cells arranged along a plurality of rows and columns. The memory cells included in the memory cell array region MA may be electrically connected to a row decoder 3 via word lines WL, at least one common source line CSL, string selection lines SSL, at least one ground selection line GSL, etc., and may be electrically connected to a page buffer 4 and a column decoder 5 via bit lines BL.

[0013] In one embodiment, among the memory cells, memory cells arranged along the same row may be connected to the same word line WL, and memory cells arranged along the same column may be connected to the same bit line BL.

[0014] The row decoder 3 may be commonly connected to the memory blocks BLK and may provide driving signals to the word lines WL of the memory blocks BLK selected in response to a block selection signal. For example, the row decoder 3 may receive address information ADDR from an external device and decode the received address information ADDR to determine voltages to be supplied to at least some of the word lines WL, the common source line CSL, the string selection line SSL, and the ground selection line GSL electrically connected to the memory blocks BLK.

[0015] The page buffer 4 may be electrically connected to the memory cell array area MA through the bit lines BL. The page buffer 4 may be connected to a bit line BL selected according to an address decoded by the column decoder 5. The page buffer 4 may temporarily store data to be stored in a memory cell or sense data stored in a memory cell according to an operation mode. For example, the page buffer 4 may operate as a write driver circuit in a program operation mode and as a sense amplifier circuit in a read operation mode. The page buffer 4 may receive power (e.g., voltage or current) from a control logic and provide it to a selected bit line BL.

[0016] The column decoder 5 may provide a data transmission path between the page buffer 4 and an external device (e.g., a memory controller) and may decode an address input from the outside to select one of the bit lines BL.

[0017] The column decoder 5 may be commonly connected to the memory blocks BLK and may provide data information to the bit lines BL of the memory blocks BLK selected in response to a block selection signal.

[0018] The control circuit 6 can control the overall operation of the three-dimensional semiconductor device 1. The control circuit 6 can receive a control signal and an external voltage and operate according to the received control signal. The control circuit 6 can include a voltage generator that uses an external voltage to generate voltages (e.g., program voltage, read voltage, erase voltage, etc.) required for internal operations. The control circuit 6 can control read, write, and / or erase operations in response to a control signal.

[0019] With reference to Fig. 2, an illustrative example of a circuit in the memory cell array area (MA in Fig. 1) of the three-dimensional semiconductor device (1 in Fig. 1) described in Fig. 1 will be described. Fig. 2 is a circuit diagram conceptually showing an example of the memory cell array area (MA in Fig. 1).

[0020] 2, the memory cell array region (MA in FIG. 1) may include memory strings S including memory cells MC connected in series with each other, and ground selection transistors GST and string selection transistors SST connected in series to both ends of the memory cells MC. The memory cells MC connected in series with each other may be connected to word lines WL for selecting the memory cells MC.

[0021] The ground selection transistor GST has a gate terminal connected to a ground selection line GSL, a source terminal connected to a common source line CSL, and a gate terminal of the string selection transistor SST is connected to a string selection line SSL, and a source terminal connected to a drain terminal of the memory cell MC.

[0022] FIG. 2 shows a structure in which the ground selection transistor GST and the string selection transistor SST are connected one by one to the memory cells MC connected in series with each other. However, instead, a plurality of ground selection transistors GST or a plurality of string selection transistors SST may be connected.

[0023] In one embodiment, a first dummy line DL1 may be arranged between a lowest word line WL of the word lines WL and the ground selection line GSL, and a second dummy line DL2 may be arranged between a highest word line WL of the word lines WL and the string selection line SSL. The first dummy line DL1 may be arranged in one or more lines, and the second dummy line DL2 may be arranged in one or more lines.

[0024] A drain terminal of the string selection transistor SST may be connected to a bit line BL. When a signal is applied to a gate terminal of the string selection transistor SST via the string selection line SSL, the signal applied via the bit line BL is transferred to the memory cells MC connected in series to perform data read and write operations. In addition, an erase operation for erasing data recorded in the memory cells MC may be performed by applying a predetermined erase voltage via a substrate.

[0025] The three-dimensional semiconductor device according to an embodiment of the present invention may include at least one dummy string DS. The dummy string DS may be a string including a dummy channel electrically isolated from the bit line BL.

[0026] Next, an exemplary embodiment of a three-dimensional semiconductor device according to an exemplary embodiment of the present invention will be described with reference to Figures 3 and 4. Figure 3 is a plan view conceptually illustrating an exemplary embodiment of a memory cell array region of a three-dimensional semiconductor device according to an exemplary embodiment of the present invention, and Figure 4 is a plan view enlarging a portion marked "A" in Figure 3 to illustrate an exemplary embodiment of the three-dimensional semiconductor device according to an exemplary embodiment of the present invention.

[0027] 3 and 4, a memory block BLK may be disposed on a memory cell array region MA. A connection region IA may be disposed on at least one side of the memory cell array region MA. For example, the connection region IA may be disposed on both opposing sides of the memory cell array region MA.

[0028] In one embodiment, the memory cell array region MA may be a region in which the memory cells (MC in FIG. 2) are arranged, and the connection region IA may be a region in which a pad region of a gate electrode contacting a contact plug for applying an electrical signal or voltage to the string selection line (SSL in FIG. 2), the word line (WL in FIG. 2), and / or the ground selection line (GSL in FIG. 2) is arranged. The memory blocks BLK may be arranged between main isolation structures MS crossing the memory cell array region MA and the connection region IA. Each of the memory blocks BLK may be located between a pair of adjacent main isolation structures MS. Thus, one memory block BLK may be located between a pair of adjacent main isolation structures MS.

[0029] The following description will focus on the components located between a pair of adjacent primary isolation structures MS.

[0030] A plurality of auxiliary separating structures may be disposed between the main separating structures MS. The main separating structures MS may have a line shape extending in a first direction (X). Each of the auxiliary separating structures may have a line shape or a bar shape extending in the first direction (X). Each of the auxiliary separating structures may have a line shape or a bar shape having a shorter length than the main separating structures MS.

[0031] The plurality of auxiliary isolating structures may include a first auxiliary isolating structure SS1 and a second auxiliary isolating structure SS2.

[0032] The first auxiliary isolation structure SS1 may include a first line portion SS1a and a second line portion SS1b having end portions spaced apart from each other and facing each other.

[0033] The first line portion SS1a of the first auxiliary isolation structure SS1 may extend across the memory cell array region MA to a portion of the connection region IA, and the second line portion SS1b of the first auxiliary isolation structure SS1 may be disposed in the connection region IA and have an end portion facing an end portion of the first line portion SS1a.

[0034] The second auxiliary separating structure SS2 may be disposed between the first auxiliary separating structure SS1 and the main separating structure MS. The second auxiliary separating structures SS2 may be disposed in a plurality of lines or bars arranged along the first direction (X) and spaced apart from each other. Each of the second auxiliary separating structures SS2 may have a shorter length in the first direction (X) than the first and second line portions SS1a and SS1b of the first auxiliary separating structure SS1.

[0035] In one example, the second auxiliary separating structure SS2 may be disposed between the second line portion SS1b of the first auxiliary separating structure SS1 and the main separating structure MS. The second auxiliary separating structure SS2 may have end portions facing each other between the second line portion SS1b of the first auxiliary separating structure SS1 and the main separating structure MS. The end portions facing each other of the second auxiliary separating structure SS2 may be arranged along the first direction (X).

[0036] Various components may be disposed between the main isolation structures MS, together with the first and second auxiliary isolation structures SS1 and SS2. An illustrative example of a three-dimensional semiconductor device including the main isolation structures MS and the first and second auxiliary isolation structures SS1 and SS2 will be described with reference to Figures 5, 6, 7, 8, 9a, 9b, and 9c. FIG. 5 is a plan view showing an illustrative example of a three-dimensional semiconductor device according to one embodiment of the present invention by enlarging the portion marked "A" in FIG. 3, FIG. 6 is a cross-sectional view showing an area taken along line I-I' in FIG. 5, FIG. 7 is a cross-sectional view showing an area taken along line II-II' in FIG. 5, FIG. 8 is an enlarged plan view showing the portions marked "B1" and "B2" in FIGS. 4 and 5, FIG. 9a is a cross-sectional view showing the areas taken along lines III-III' and IV-IV' in FIG. 8, FIG. 9b is a cross-sectional view showing the areas taken along lines V-V' and VI-VI' in FIG. 8, and FIG. 9c is a cross-sectional view showing the areas taken along line VII-VII' in FIG. 8.

[0037] Referring to Figures 5 to 8, 9a, 9b and 9c, the main isolation structure MS and the first and second auxiliary isolation structures SS1, SS2 as described with reference to Figures 3 and 4 may be arranged on a substrate 103.

[0038] The substrate 103 may be a semiconductor substrate that may be made of a semiconductor material such as silicon, etc. The substrate 103 may be a bulk silicon substrate or an SOI substrate.

[0039] The main isolation structure MS and the first and second auxiliary isolation structures SS1 and SS2 may have a line shape extending in a first direction (X) parallel to the surface 103s of the substrate 103.

[0040] A gate electrode GE may be disposed on the substrate 103 between the primary isolation structures MS. The gate electrode GE may be formed of a conductive material including at least one of doped polysilicon, a metal nitride (e.g., TiN), a metal silicide (e.g., WSi, TiSi, TaSi, etc.), or a metal (e.g., W). The doped polysilicon may be polysilicon including N-type impurities (e.g., P, As, etc.) or P-type impurities (e.g., B, etc.).

[0041] The gate electrodes GE may be stacked in sequence on the memory cell array region MA in a direction (Z) perpendicular to a surface 103s of the substrate 103, may be spaced apart from each other, and may extend onto the connection region IA. The gate electrodes GE may be arranged in a direction (Z) perpendicular to a surface 103s of the substrate 103, and may be separated by interlayer insulating layers 106. The lowest interlayer insulating layer of the interlayer insulating layers 106 may be interposed between the lowest gate electrode of the gate electrodes GE and the substrate 103.

[0042] The gate electrode GE may include one or more lower gate electrodes GE_g, GE_d1, a plurality of intermediate gate electrodes GE_w arranged on the one or more lower gate electrodes GE_g, GE_d1, and a plurality of upper gate electrodes GE_s, GE_d2 arranged on the plurality of intermediate gate electrodes GE_w.

[0043] In one example, the one or more lower gate electrodes GE_g, GE_d1 may be arranged in a plurality of pieces. The plurality of lower gate electrodes GE_g, GE_d1 may include a lower selection gate electrode GE_g and one or more lower dummy gate electrodes GE_d1 arranged on the lower selection gate electrode GE_g. The lower selection gate electrode GE_g may be the ground selection line (GSL in FIG. 1 and FIG. 2) described in FIG. 1 and FIG. 2.

[0044] The intermediate gate electrodes GE_w may be the word lines (WL in FIGS. 1 and 2) described with reference to FIGS.

[0045] In an embodiment, the one or more upper gate electrodes GE_s, GE_d2 may be arranged in a plurality of pieces. Among the plurality of upper gate electrodes GE_s, GE_d2, the top upper gate electrode and / or the next upper gate electrode may be an upper selection gate electrode GE_s, and one or more upper gate electrodes located between the upper selection gate electrode GE_s and the plurality of middle gate electrodes GE_w may be an upper dummy gate electrode GE_d2. The upper selection gate electrode GE_s may be the string selection line (SSL in FIG. 1 and FIG. 2) described in FIG. 1 and FIG. 2.

[0046] In the first auxiliary isolation structure SS1, the first line portion SS1a crosses the upper selection gate electrode GE_s, and the second line portion SS1b may be spaced apart from the upper selection gate electrode GE_s. In one example, the second auxiliary isolation structure SS2 may be spaced apart from the upper selection gate electrode GE_s.

[0047] A floating dummy gate electrode GE_f may be disposed on the connection region IA on the intermediate gate electrodes GE_w and facing a portion of the upper gate electrodes GE_s, GE_d2. The floating dummy gate electrode GE_f may be formed of the same material as the gate electrode GE. The floating dummy gate electrode GE_f may include floating pad regions Pf arranged in a stepped shape that is gradually lowered in a direction toward the upper gate electrodes GE_s, GE_d2. The floating dummy gate electrode GE_f may be spaced apart from the memory cell array region MA.

[0048] The gate electrode GE may be disposed between the main isolation structures MS. It may also be said that the main isolation structures MS cross and penetrate the gate electrode GE. The gate electrode GE may be penetrated by the first and second auxiliary isolation structures SS1 and SS2 between the main isolation structures MS.

[0049] Each of the main isolation structure MS and the first and second auxiliary isolation structures SS1 and SS2 may include a conductive pattern 180 and a spacer 176 covering a side of the conductive pattern 180. The spacer 176 may be formed of an insulating material such as silicon oxide or silicon nitride. The spacer 176 may separate the conductive pattern 180 from the gate electrode GE. The conductive pattern 180 may be formed of a conductive material including at least one of doped polysilicon, a metal nitride such as titanium nitride, or a metal such as tungsten. In one example, the conductive pattern 180 may be named a source contact plug.

[0050] An impurity region 178 may be disposed in the substrate 103 below the main isolation structure MS and the first and second auxiliary isolation structures SS1 and SS2. The impurity region 178 may form the common source line (CSL in FIGS. 1 and 2) described in FIGS. 1 and 2. The impurity region 178 may have an N-type conductivity, and a portion of the substrate 103 adjacent to the impurity region 178 may have a P-type conductivity.

[0051] An insulating line pattern ISP may be disposed across the upper selection gate electrode GE_s to separate the upper selection gate electrode GE_s in a length direction of the main and auxiliary isolation structures MS, SS1, SS2, i.e., the first direction (X). The insulating line pattern ISP may be disposed at a higher level than the intermediate gate electrodes GE_w. An end portion of the insulating line pattern ISP may face an end portion of the second auxiliary isolation structure SS2. The insulating line pattern ISP may be formed of silicon oxide. In one example, the insulating line pattern ISP has a line shape extending in the first direction (X) and may be interposed between the first line portion SS1a of the first auxiliary isolation structure SS1 and the main isolation structure MS. In one example, the second auxiliary isolation structure SS2 may be spaced apart from the upper selection gate electrode GE_s.

[0052] The gate electrode GE can have pad regions arranged three-dimensionally on the coupling region IA. By arranging the pad regions three-dimensionally in this manner, it is possible to achieve high integration of semiconductor elements.

[0053] The upper selection gate electrode GE_s may include an upper selection pad region Ps, and the upper dummy gate electrode GE_d2 may include an upper dummy pad region Pd2. The upper selection pad region Ps and the upper dummy pad region Pd2 may constitute the upper pad regions Ps, Pd2 of the upper gate electrodes GE_s, GE_d2.

[0054] The upper pad regions Ps, Pd2 may be arranged to be lower in a first direction (X) away from the memory cell array region MA as shown in Fig. 6, and to be at the same level in a second direction (Y) perpendicular to the first direction (X) as shown in Fig. 9a. The first and second directions (X, Y) may be parallel to a surface 103s of the substrate 103.

[0055] Of the lower gate electrodes GE_g and GE_d1, the lower selection gate electrode GE_g may include a lower selection pad region Pg, and the lower dummy gate electrode GE_d1 may include a lower dummy pad region Pd1.

[0056] The floating dummy gate electrode GE_f may include a floating dummy pad region Pf. The floating dummy pad region Pf may be arranged in a stepped shape that decreases in a direction toward the memory cell array region MA. The intermediate gate electrodes GE_w may include intermediate pad regions Pw. The intermediate pad regions Pw may be arranged in a stepped shape that decreases in a stepwise manner to have a first step in the first direction (X) from the memory cell array region MA toward the connection region IA, and in a stepped shape that decreases in a stepwise manner to have a second step smaller than the first step in the second direction (Y) perpendicular to the first direction (X).

[0057] In a planar view such as that of Figure 8, a first boundary PB1 between the intermediate pad regions Pw can be arranged along the first direction (X) and substantially parallel to the second direction (Y), and a second boundary PB2 between the intermediate pad regions Pw can be arranged along the second direction (Y) and substantially parallel to the first direction (X).

[0058] A vertical structure VS may be disposed on the substrate 103. The vertical structure VS may include a memory cell vertical structure VSc and a dummy vertical structure VSd. The vertical structure VS may penetrate the gate electrode GE.

[0059] In one example, a first insulating layer 132, a second insulating layer 163, and a third insulating layer 181 may be disposed on the substrate 103, which are sequentially stacked to cover the gate electrode GE. The vertical structure VS may penetrate the first insulating layer 132 and the gate electrode GE. The main isolation structure MS and the first and second auxiliary isolation structures SS1, SS2 may penetrate the first and second insulating layers 132 and 163 and the gate electrode GE. Top surfaces of the main isolation structure MS and the first and second auxiliary isolation structures SS1, SS2 may be located at a higher level than top surfaces of the vertical structures VS.

[0060] The memory cell vertical structures VSc can be disposed on the memory cell array region MA. A part of the dummy vertical structures VSd can pass through the insulating line pattern ISP on the memory cell array region MA, and the rest can be disposed between the main isolation structures MS on the connecting region IA. The arrangement density of the vertical structures VS on the memory cell array region MA can be higher than the arrangement density of the vertical structures VS on the connecting region IA. The arrangement density of the memory cell vertical structures VSc can be higher than the arrangement density of the dummy vertical structures VSd.

[0061] In one example, the dummy vertical structure VSd on the connection area IA may pass through the pad area.

[0062] Each of the vertical structures VS may include a semiconductor pattern 145, a core pattern 157, a pad pattern 160, a channel semiconductor layer 154, and a first gate dielectric 151. A second gate dielectric 169 may be disposed on upper / lower surfaces of the gate electrode GE and extending between the memory cell vertical structure VSc and the gate electrode GE.

[0063] The semiconductor pattern 145 may be in contact with the substrate 103. In one example, the semiconductor pattern 145 may be an epitaxial material layer that may be formed by a SEG process.

[0064] The core pattern 157 may be disposed on the semiconductor pattern 145 and may be formed of an insulating material (e.g., silicon oxide). The pad pattern 160 may be disposed on the core pattern 157. The pad pattern 160 may be formed of polysilicon having an N-type conductivity and may be a drain region. The pad pattern 160 may be disposed at a higher level than the gate electrode GE.

[0065] The channel semiconductor layer 154 may contact the semiconductor pattern 145 and extend in a direction (Z) perpendicular to the surface 103s of the substrate 103. The channel semiconductor layer 154 may cover a side of the core pattern 157 and may contact the pad pattern 160. The channel semiconductor layer 154 may penetrate the middle gate electrode GE_w, which may include the word line (WL in FIGS. 1 and 2) of the gate electrode GE, and the upper gate electrodes GE_s and GEd, which may include the string selection line (SSL in FIGS. 1 and 2). The channel semiconductor layer 154 may be formed of a polysilicon layer.

[0066] The first gate dielectric 151 may cover the outside of the channel semiconductor layer 154 and be disposed between the channel semiconductor layer 154 and the gate electrode GE.

[0067] Any one of the first and second gate dielectrics 151 and 169 may include a layer capable of storing information. For example, the first gate dielectric 151 may include a layer capable of storing information, but the technical idea of ​​the present invention is not limited thereto. For example, the second gate dielectric 169 may include a layer capable of storing information. Hereinafter, an example in which the first gate dielectric 151 includes a layer capable of storing information will be described.

[0068] The first gate dielectric 151 may include a tunnel dielectric layer 148, an information storage layer 147, and a blocking dielectric layer 146. The information storage layer 147 may be disposed between the tunnel dielectric layer 148 and the blocking dielectric layer 146. The tunnel dielectric layer 148 may be close to the channel semiconductor layer 154, and the blocking dielectric layer 146 may be close to the gate electrode GE.

[0069] The tunnel dielectric layer 148 may include silicon oxide and / or impurity-doped silicon oxide, and the blocking dielectric layer 146 may include silicon oxide and / or high-k dielectric.

[0070] The information storage layer 147 may be interposed between the channel semiconductor layer 154 and the intermediate gate electrode GE_w of the gate electrode GE, and may be a layer for storing information in a nonvolatile memory device such as a flash memory device. For example, the information storage layer 147 may be formed of a material, for example, silicon nitride, capable of trapping and retaining electrons injected from the channel semiconductor layer 154 through the tunnel dielectric layer 148 or erasing the trapped electrons in the information storage layer 147 according to an operating condition of a nonvolatile memory device such as a flash memory device. The second gate dielectric 169 may include a high dielectric constant material (for example, AlO, etc.).

[0071] The information storage layer 147 may store information in a region of the gate electrode GE facing the intermediate gate electrode GE_w corresponding to the word line (WL in FIGS. 1 and 2). In the information storage layer 147 in any one of the cell vertical structures of the memory cell vertical structures VSc, a region capable of storing information may be arranged in a direction perpendicular to the surface of the substrate 103 and may be defined by the memory cell (MC in FIG. 2). Therefore, the memory cell vertical structure VSc may constitute the memory string (S in FIG. 2) described in FIG. 2, and the dummy vertical structure VSd may constitute the dummy string (DS in FIG. 2) described in FIG. 2.

[0072] A bit line contact plug 182 may be disposed on the memory cell vertical structure VSc.

[0073] A contact plug 184 may be disposed on the pad region of the gate electrode GE. The contact plug 184 may include a lower selection contact plug 184g electrically connected to the lower selection pad region Pg of the lower selection gate electrode GE_g, an intermediate contact plug 184w electrically connected to the intermediate pad region Pw of the intermediate gate electrodes GE_w, an upper selection contact plug 184s electrically connected to the upper selection pad region Ps of the upper selection gate electrode GE_s, and a dummy contact plug 184d on the lower and upper dummy pad regions Pd1, Pd2 and the floating pad region Pf.

[0074] An illustrative example of the gate electrode GE will be described with reference to Fig. 10. Fig. 10 is a perspective view showing an illustrative example of the plurality of intermediate gate electrodes GE_w among the gate electrodes GE.

[0075] 10, as described above, the intermediate gate electrodes GE_w may include pad regions Pw that are successively lowered in the second direction (Y) as described in FIG 8. The pad regions Pw may include contact regions in contact with the contact plugs.

[0076] The intermediate gate electrodes GE_w may include a first gate connecting portion GEa located between opposing end portions of the first and second line portions (SS1a, SS1b in FIGS. 5 and 8) of the first auxiliary isolation structure (SS1 in FIGS. 5 and 8) and a second gate connecting portion GEb located between opposing end portions of the second auxiliary isolation structure (SS2 in FIGS. 5 and 8). The second gate connecting portion GEb may be closer to the main isolation structure MS than the first gate connecting portion GEa.

[0077] The gate electrode having the first and second gate connection parts GEa and GEb may be the plurality of intermediate gate electrodes GE_w and the lower selection gate electrode GE_g. In one example, the upper selection gate electrode GE_s may not have the first and second gate connection parts GEa and GEb.

[0078] In one embodiment, the pad region of the gate electrode GE may have the same thickness as the gate electrode GE, but the technical idea of ​​the present invention is not limited thereto. For example, the gate electrode GE may be modified to have a pad region having a thickness increased in the connection region IA compared to the gate electrode GE. As shown in FIG. 11, which shows a perspective view of such a modified example of the gate electrode GE, the intermediate gate electrode GE_w of the gate electrode GE may have a first thickness t1, and the intermediate pad region Pw of the intermediate gate electrode GE_w may have a second thickness t2 greater than the first thickness t1.

[0079] In one embodiment, the dummy vertical structure VSd may be disposed apart from the boundaries between the pad regions Ps, Pd, Pw, and may not be disposed between the opposing end portions of the first and second line portions SS1a, SS1b of the first auxiliary isolation structure SS1 and / or between the opposing end portions of the second auxiliary isolation structure SS2, but the technical idea of ​​the present invention is not limited thereto. Modified examples of the dummy vertical structure VSd will be described with reference to Figures 12, 13a, 13b, and 13c. FIG. 12 is an enlarged plan view of the portions indicated by "B1" and "B2" in FIG. 4 and FIG. 5 to explain a modified example of a three-dimensional semiconductor device according to one embodiment of the present invention, FIG. 13a is a cross-sectional view showing the areas taken along lines III-III' and IV-IV' in FIG. 12, FIG. 13b is a cross-sectional view showing the areas taken along lines V-V' and VI-VI' in FIG. 12, and FIG. 13c is a cross-sectional view showing the areas taken along line VII-VII' in FIG. 12.

[0080] 12, 13a, 13b, and 13c, in the connection region IA, a portion of the dummy vertical structure VSd may be disposed between opposing end portions of the first and second line portions SS1a, SS1b of the first auxiliary separating structure SS1 and / or between opposing end portions of the second auxiliary separating structure SS2. Here, the opposing end portions of the first and second line portions SS1a, SS1b of the first auxiliary separating structure SS1 and the opposing end portions of the second auxiliary separating structure SS2 may be end portions arranged along the first direction (X).

[0081] In one example, a portion of the dummy vertical structure VSd may be arranged along the second direction (Y) and positioned at the second boundary PB2 between the intermediate pad regions Pw parallel to the first direction (X).

[0082] In one example, the dummy vertical structures VSd may be arranged along the first direction (X) and spaced apart from the first boundary PB1 between the intermediate pad regions Pw parallel to the second direction (Y), but the technical idea of ​​the present invention is not limited thereto. As shown in Fig. 14, a portion of the dummy vertical structure VSd may be arranged along the first direction (X) and pass through the first boundary PB1 between the intermediate pad regions Pw parallel to the second direction (Y). Thus, referring to Fig. 14, it can be seen that a portion of the dummy vertical structure VSd passes through the first and second gate connection portions (GEa, GEb in Fig. 10) of the intermediate gate electrode (GE_w in Fig. 10).

[0083] In one embodiment, the second boundary PB2 between the intermediate pad regions Pw arranged along the second direction (Y) and parallel to the first direction (X) may be disposed between the opposing end portions of the auxiliary isolation structures SS1 and SS2, but the technical idea of ​​the present invention is not limited thereto. The intermediate pad region Pw arranged along the second direction (Y) will be described with reference to Figs. 15 and 16. Fig. 15 is an enlarged plan view of the portions indicated by "B1" and "B2" in Figs. 4 and 5 to explain another modified example of a three-dimensional semiconductor device according to an embodiment of the present invention, and Fig. 16 is a perspective view showing another modified example of a gate electrode GE of a three-dimensional semiconductor device according to an embodiment of the present invention.

[0084] Referring to Figures 15 and 16, in a planar view such as Figure 15, the second boundary PB2 between the intermediate pad regions Pw arranged along the second direction (Y) can be made not to overlap with the first and second auxiliary isolation structures SS1, SS2.

[0085] According to an embodiment, the insulating line pattern ISP may be disposed on the intermediate gate electrodes GE_w and may pass through the upper selection gate electrodes GE_s. The insulating line pattern ISP may extend to the connection region IA across the upper selection gate electrodes GE_s in the memory cell array region MA and pass between the upper selection pad regions Ps, but the technical idea of ​​the present invention is not limited thereto. For example, as shown in the plan view of FIG. 17 for explaining yet another modified example of a three-dimensional semiconductor device according to an embodiment of the present invention, the insulating line pattern ISP may cross the upper selection gate electrodes GE_s in the memory cell array region MA, and the second auxiliary isolation structure SS2 may be disposed between the upper selection pad regions Ps.

[0086] Next, an illustrative example of a method for forming a three-dimensional semiconductor device according to the technical concept of the present invention will be described with reference to Figures 18a to 22b. In Figures 18a to 22b, Figures 18a, 19a, 20a, 21a, and 22a are cross-sectional views showing an area taken along line I-I' in Figure 5, and Figures 18b, 19b, 20b, 21b, and 22b are cross-sectional views showing an area taken along line VIII-VIII' in Figure 5.

[0087] 5, 18a and 18b, a mold structure 112 including an interlayer insulating layer 106 and a sacrificial layer 109 may be formed on a surface 103s of a substrate 103 having a memory cell array region MA and a connection region IA. The interlayer insulating layer 106 may be formed of silicon oxide, and the sacrificial layer 109 may be formed of silicon nitride.

[0088] The interlayer insulating layer 106 and the sacrificial layer 109 are alternately formed, and the lowest layer and the uppermost layer may be an interlayer insulating layer. The lowest and uppermost sacrificial layers of the sacrificial layers 109 may be patterned sacrificial layers.

[0089] A first mask pattern 118a and a second mask pattern 121a spaced apart from each other may be formed on the substrate 103 having the interlayer insulating layer 106 and the sacrificial layer 109.

[0090] In one example, the first mask pattern 118a may cover the entire memory cell array region MA and extend onto a portion of the connection region IA. The first mask pattern 118a may cover a top patterned sacrificial layer of the sacrificial layer 109. The second mask pattern 121a may be formed on a portion of the connection region IA.

[0091] In one example, a second mask pattern 121a may be formed in a rectangular shape on a pair of adjacent memory blocks BLK among the memory blocks BLK. The first and second mask patterns 118a and 121a may be formed of photoresist patterns.

[0092] Using the first and second mask patterns 118a and 121a as etching masks, one interlayer insulating layer and one sacrificial layer among the interlayer insulating layer 106 and the sacrificial layer 109 that do not overlap with the first and second mask patterns 118a and 121a can be sequentially etched.

[0093] 5, 19a, and 19b, a first trimming process may be performed to reduce the sizes of the first and second mask patterns (118a and 121a in FIGS. 18a and 18b). The first trimming process may be a partial etching or isotropic etching process to reduce the sizes of the first and second mask patterns (118a and 121a in FIGS. 18a and 18b) in a direction parallel to the surface of the substrate 103. Thus, one interlayer insulating layer and one sacrificial layer that do not overlap the first and second mask patterns 118b and 121b among the interlayer insulating layer 106 and the sacrificial layer 109 may be sequentially etched using the first and second mask patterns 118b and 121b whose sizes have been reduced by the first trimming process.

[0094] 5, 20a, and 20b, a second trimming process may be performed to further reduce the sizes of the first and second mask patterns (118b and 121b in FIGS. 19a and 19b). The second trimming process may be a partial etching or isotropic etching process to reduce the sizes of the first and second mask patterns (118b and 121b in FIGS. 19a and 19b) in a direction horizontal to the surface of the substrate 103.

[0095] Therefore, using the first and second mask patterns 118c, 121c whose sizes have been reduced by the second trimming process, one interlayer insulating layer and one sacrificial layer among the interlayer insulating layer 106 and the sacrificial layer 109 that do not overlap with the first and second mask patterns 118c, 121c can be sequentially etched.

[0096] 5, 21a, and 21b, after removing the first and second mask patterns (118c and 121c in FIGS. 20a and 20b), a step process may be performed to form steps that are lowered to a certain height in an area where the second mask pattern 121c has been removed. Thus, a step (STx2) that is lowered to have a first step in a first direction (X), steps (STx1, STx3) that are lowered to have a second step smaller than the first step in the first direction (X), and steps (STy, STy) that are lowered to have the second step in a second direction (Y) perpendicular to the first direction (X) may be formed.

[0097] 5, 22a, and 22b, a first insulating layer 132 may be formed on the mold structure 112. An insulating line pattern (ISP in FIG. 7) may be formed penetrating the first insulating layer 132 and penetrating the top sacrificial layer and the next top sacrificial layer of the sacrificial layers 109 of the mold structure 112.

[0098] In a modified example, before forming the first insulating layer 132, the uppermost interlayer insulating layer of the interlayer insulating layers 106 may be removed to expose the sacrificial layer 109. Then, the same material as the sacrificial layer may be formed on the sacrificial layer corresponding to the pad region of the sacrificial layer 109 to increase the thickness of the sacrificial layer. The portion of the sacrificial layer whose thickness is increased in this manner may be a portion for forming the pad region (Pw in FIG. 11) whose thickness is increased as described in FIG. 11.

[0099] A vertical structure VS may be formed penetrating the first insulating layer 132 and the mold structure 112. The vertical structure VS may be formed to have the same structure as that described with reference to Fig. 7. A second insulating layer 163 may be formed to cover the first insulating layer 132 and the vertical structure VS.

[0100] A trench 166 may be formed through the first and second insulating layers 132 and 163 and the mold structure 112. Sidewalls of the trench 166 may expose the sacrificial layer 109 of the mold structure 112.

[0101] The trench 166 may be formed in a planar shape corresponding to the main isolation structure (MS in FIGS. 3 and 4) and the first and second auxiliary isolation structures (SS1, SS2 in FIGS. 3 and 4) described in FIGS. 3 and 4.

[0102] 4 to 8, 9a, 9b, and 9c, a gate replacement process can be performed to replace the sacrificial layer (109 in FIGS. 22a and 22b) exposed by the trench (166 in FIGS. 22a and 22b) with a gate. For example, the sacrificial layer (109 in FIGS. 22a and 22b) exposed by the trench (166 in FIGS. 22a and 22b) can be removed to form an empty space, a second gate dielectric 169 can be formed to cover the inner wall of the empty space, and a gate electrode GE can be formed to fill the empty space whose inner wall is covered by the second gate dielectric 169.

[0103] Next, insulating spacers 176 may be formed on the side of the trench (166 in FIGS. 22a and 22b), impurity regions 178 may be formed in the substrate 103 exposed by the trench (166 in FIGS. 22a and 22b), and a conductive pattern 180 may be formed to fill the trench (166 in FIGS. 22a and 22b). The insulating spacers 176 and the conductive pattern 180 may constitute a main isolation structure MS and first and second auxiliary isolation structures SS1 and SS2. Next, an insulating material may be formed to cover the isolation structures MS, SS1, SS2 and the second insulating layer 163, and then a contact and wiring formation process may be performed.

[0104] As described above, the gate electrode GE may include pad regions arranged three-dimensionally. Such pad regions arranged three-dimensionally may improve the integration density of a semiconductor device. In addition, by disposing the first and second auxiliary isolation structures SS1 and SS2, the gate electrodes GE may be stacked more without defects. Therefore, the integration density of a semiconductor device may be improved.

[0105] Although the embodiment of the present invention has been described above with reference to the accompanying drawings, it will be understood by those skilled in the art that the present invention can be embodied in other specific forms without changing the technical idea or essential features of the present invention. Therefore, it should be understood that the above-described embodiment is illustrative in all respects and is not limiting. [Explanation of symbols]

[0106] MA Memory cell array area IA consolidation area BLK Memory block MC memory cell WL Word Line BL Bit Line CSL Common Source Line SSL String Selection Line S Memory String DS Dummy String MS main separation structure SS1 1st auxiliary separation structure SS1a 1st line section SS1b 2nd line part SS2 2nd auxiliary separation structure VS vertical structure VSc memory cell vertical structure VSd dummy vertical structure Ps, Pd, Pf, Pw, Pg Pad Area GE gate electrode 182, 184 Contact plug 103 Substrate 106, 132, 163, 180 Insulating layer 176 Insulating spacer 178 Impurity region 180 Conductive Pattern 151 First gate dielectric 146 Blocking Dielectric Layer 147 Information Storage Layer 148 Tunnel Dielectric Layer 154 Channel Semiconductor Layer 157 Core Pattern 169 Second gate dielectric

Claims

1. a primary isolation structure disposed on the substrate and extending across the memory cell array region and the coupling region of the substrate in a first direction parallel to a surface of the substrate; a gate electrode disposed between a pair of adjacent primary isolation structures; a first auxiliary isolation structure including: a first line portion penetrating the gate electrode between the main isolation structures and extending across the memory cell array region to the connecting region; and a second line portion disposed in the connecting region and having an end portion facing the first line portion in the connecting region; a second auxiliary isolation structure disposed in the connecting region, between the first auxiliary isolation structure and the main isolation structure, and penetrating the gate electrode; Each of the second auxiliary isolation structures extends in the first direction; the second auxiliary isolation structure has opposing end portions between the second line portion and the main isolation structure; the gate electrode extends from a memory cell array region of the substrate to the connecting region and has a plurality of electrode layers stacked in a third direction perpendicular to a surface of the substrate; each of the plurality of electrode layers has a pad region coupled to a contact plug in the connection region; A three-dimensional semiconductor element, wherein the pad regions of the multiple electrode layers are arranged in a stepped manner in the connecting region along the first direction so that a first step is formed in the third direction, and are arranged in a stepped manner in the connecting region along a second direction that, together with the first direction, defines the surface of the substrate so that a second step is formed in the third direction.

2. The three-dimensional semiconductor device of claim 1 , wherein each of the second auxiliary isolation structures has a length in the first direction that is shorter than that of the second line portions.

3. 3. The three-dimensional semiconductor device of claim 1, wherein each of the main isolation structure, the first auxiliary isolation structure, and the second auxiliary isolation structure includes a conductive pattern and an insulating spacer on a side surface of the conductive pattern.

4. The three-dimensional semiconductor device of claim 3 , further comprising an impurity region disposed in the substrate below the main isolation structure, the first auxiliary isolation structure, and the second auxiliary isolation structure.

5. further comprising a vertical structure disposed on the substrate; 5. The three-dimensional semiconductor device of claim 1, wherein the vertical structures include a memory cell vertical structure disposed on the memory cell array region and penetrating the gate electrode, and a dummy vertical structure disposed on the connection region and penetrating the pad region.

6. The three-dimensional semiconductor device of claim 5 , wherein a density of the memory cell vertical structures disposed on the memory cell array region is higher than a density of the dummy vertical structures disposed on the connecting region.

7. 7. The three-dimensional semiconductor device of claim 6, wherein each of the vertical structures includes a channel semiconductor layer extending in a direction perpendicular to a surface of the substrate, and an information storage layer interposed between the channel semiconductor layer and the gate electrode.

8. The three-dimensional semiconductor device of claim 6 , wherein in a plan view, the dummy vertical structures are spaced apart from boundaries between the pad regions.

9. The three-dimensional semiconductor device of claim 6 , wherein in a plan view, a portion of the dummy vertical structure penetrates a boundary between the pad regions.

10. The three-dimensional semiconductor device of claim 6 , wherein a portion of the dummy vertical structure is disposed between end portions of the second auxiliary isolation structures facing each other.

11. a primary isolation structure across the memory cell array region and the coupling region of the substrate; a gate electrode including a plurality of electrode layers stacked in sequence on the memory cell array region along a third direction perpendicular to a surface of the substrate between a pair of the main isolation structures adjacent to each other, the gate electrode extending to the connecting region, and having a pad region coupled to a contact plug in the connecting region; a first auxiliary isolation structure including: a first line portion penetrating the gate electrode between the main isolation structures and extending across the memory cell array region to the connecting region; and a second line portion disposed on the connecting region and having an end portion facing the first line portion at the connecting region; a second auxiliary isolation structure disposed in the connecting region, between the first auxiliary isolation structure and the main isolation structure, and penetrating the gate electrode; Each of the second auxiliary isolation structures extends in a first direction along a surface of the substrate; the second auxiliary isolation structure has end portions facing each other at the connecting region; the opposing end portions of the second auxiliary isolating structure are disposed between the second line portion of the first auxiliary isolating structure and the main isolating structure; A three-dimensional semiconductor element, wherein the pad regions of the multiple electrode layers are arranged in a stepped manner in the connecting region along the first direction so that a first step is formed in the third direction, and are arranged in a stepped manner in the connecting region along a second direction that, together with the first direction, defines the surface of the substrate so that a second step is formed in the third direction.

12. the gate electrode includes a lower gate electrode, a plurality of intermediate gate electrodes disposed on the lower gate electrode, and a plurality of upper gate electrodes disposed on the plurality of intermediate gate electrodes; the plurality of upper gate electrodes includes an upper select gate electrode; The three-dimensional semiconductor device of claim 11 , wherein the first line portion crosses the upper select gate electrode and the second line portion is spaced apart from the upper select gate electrode.

13. The three-dimensional semiconductor device of claim 12 , wherein the second auxiliary isolation structure is spaced apart from the upper select gate electrode.

14. further comprising a vertical structure disposed on the substrate; the vertical structures include a memory cell vertical structure disposed on the memory cell array region and penetrating the gate electrode, and a dummy vertical structure disposed on the coupling region and penetrating the pad region; 13. The three-dimensional semiconductor device of claim 12, wherein a portion of the dummy vertical structure is disposed between opposing end portions of the first and second line portions and between opposing end portions of the second auxiliary isolation structure.

15. a substrate having a memory cell array region and a connection region adjacent to the memory cell array region; a gate electrode including a plurality of electrode layers stacked in a direction perpendicular to the surface of the substrate in the memory cell array region along a third direction perpendicular to the surface of the substrate, the gate electrode extending into the connection region and having a pad region coupled to a contact plug in the connection region; a primary isolation structure extending through the gate electrode across the memory cell array region and the connecting region; a first auxiliary isolation structure penetrating the gate electrode between a pair of adjacent main isolation structures, the first auxiliary isolation structure including a first line portion extending across the memory cell array region to the connecting region, and a second line portion disposed in the connecting region and having an end portion facing the first line portion in the connecting region; second auxiliary isolation structures disposed in the connecting region, located on both sides of the first auxiliary isolation structure, and penetrating the gate electrode between the first auxiliary isolation structure and the main isolation structure; Each of the second auxiliary isolation structures extends in a first direction along a surface of the substrate; the second auxiliary isolation structure has end portions spaced apart opposite each other at the connecting region; each of the second auxiliary isolation structures has a length shorter than the first and second line portions of the first auxiliary isolation structure; the pad regions of the plurality of electrode layers are arranged in a stepped manner in the connecting region along the first direction so as to form a first step in the third direction, and are arranged in a stepped manner in the connecting region along a second direction that, together with the first direction, defines a surface of the substrate so as to form a second step in the third direction; Three-dimensional semiconductor element.

16. any one of the gate electrodes includes a first gate connection portion located between the first and second line portions and a second gate connection portion located between the second auxiliary isolation structure, The three-dimensional semiconductor device of claim 15 , wherein the second gate connection portion is closer to the primary isolation structure than the first gate connection portion.

17. the gate electrode includes a lower gate electrode, a plurality of intermediate gate electrodes disposed on the lower gate electrode, and a plurality of upper gate electrodes disposed on the plurality of intermediate gate electrodes; the second line portion of the first auxiliary isolation structure is spaced apart from the upper gate electrodes; The three-dimensional semiconductor device of claim 16 , wherein the gate electrode having the first and second gate connection portions is one of the plurality of intermediate gate electrodes and the bottom gate electrode.

18. further comprising a vertical structure disposed on the substrate; the vertical structure includes a memory cell vertical structure disposed on the memory cell array region and penetrating the gate electrode, and a dummy vertical structure disposed on the coupling region and penetrating a pad region of the gate electrode; The three-dimensional semiconductor device of claim 16 , wherein a portion of the dummy vertical structure passes through the first and second gate connection portions.

19. The three-dimensional semiconductor device of claim 15 , wherein the gate electrode has a pad region having an increased thickness in the connection region compared to the gate electrode.

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