Transistor

Abstract

To provide a novel metal oxide, a novel transistor, a semiconductor device with large on current, a semiconductor device with a high frequency characteristic, a semiconductor device with excellent reliability, a semiconductor device capable of higher integration, and a semiconductor device with excellent electric characteristics.SOLUTION: In a transistor 10, a metal oxide 230 with crystallinity includes a first layer, which is a (M, Zn)O layer, and a second layer, which is an InO layer. The first layer has a larger band gap than the second layer. By the first layer and the second layer, a crystal lattice is formed. If a carrier is excited in the metal oxide, a carrier is transmitted through the second layer. The element M is one or a plurality of elements selected from Al, Ga, Y, and Sn.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] One embodiment of the present invention relates to a metal oxide and a transistor including the metal oxide. One embodiment of the present invention relates to a semiconductor device, a semiconductor wafer, a module, and an electronic device. do.

[0002] In this specification and the like, a semiconductor device refers to a device that can function by utilizing semiconductor characteristics. This refers to semiconductor devices in general, including semiconductor elements such as transistors, semiconductor circuits, arithmetic units, and memory devices. The device is one aspect of a semiconductor device. device, lighting device, electro-optical device, power storage device, storage device, semiconductor circuit, imaging device, electronic device etc. may be said to have a semiconductor device.

[0003] Note that one embodiment of the present invention is not limited to the above technical fields. An aspect of the present invention relates to an article, a method, or a manufacturing method. is a process, machine, manufacture, or composition of matter. This concerns the issue of the [Background technology]

[0004] In oxide semiconductors, there are c-axis axial crystals (CAACs), which are neither single crystals nor amorphous. gned crystalline structure and nc (nanocrystalline) ) structure has been found (see Non-Patent Documents 1 and 2).

[0005] In Non-Patent Documents 1 and 2, a transistor was developed using an oxide semiconductor having a CAAC structure. A technique for fabricating a transistor is disclosed.

[0006] In the latter half of the 1980s, the energy A layer with a large energy band width and a layer with a small energy band width of a semiconductor interact quantum mechanically. A multi-layered structure technology using such a method has been disclosed (see Patent Document 1).

[0007] In Patent Document 1, a semiconductor layer-insulator layer-semiconductor layer is formed in the channel formation region of a transistor. A superlattice structure consisting of repeated multilayer structures is provided, and each layer is The layers are stacked so that the surfaces of the layers are aligned along the direction of carrier movement. [Prior art documents] [Patent documents]

[0008] [Patent Document 1] Japanese Patent Application Publication No. 63-94680 [Non-patent literature]

[0009] [Non-Patent Document 1] S. Yamazaki et al., “SID Symposium Digest of Technical Papers”, 2012, volume 43, issue 1, pp.183-186 [Non-Patent Document 2] S. Yamazaki et al., “Japanese Journal of Applied Physics”, 2014, volume 53, Number 4S, pp.04ED18-1-04ED18-10 Summary of the Invention [Problem to be solved by the invention]

[0010] An object of one embodiment of the present invention is to provide a novel metal oxide. An object of one embodiment of the present invention is to provide a novel transistor. An object of one embodiment is to provide a semiconductor device with large on-state current. An object of one embodiment of the present invention is to provide a semiconductor device having high frequency characteristics. Another object of one embodiment of the present invention is to provide a semiconductor device with high reliability. Another embodiment of the present invention is to provide a semiconductor device that can be miniaturized or highly integrated. Another object of the present invention is to provide a semiconductor device having favorable electrical characteristics. One of the goals is to

[0011] Another embodiment of the present invention provides a semiconductor device capable of retaining data for a long period of time. Another object of one embodiment of the present invention is to provide a semiconductor device having a high data writing speed. Another object of the present invention is to provide a device that can reduce power consumption. It is an object of the present invention to provide a semiconductor device capable of achieving this.

[0012] The description of these problems does not preclude the existence of other problems. It is not necessary for one embodiment to solve all of these problems. The subject matter will be self-evident from the description, drawings, claims, etc. Other issues can be extracted from the drawings, claims, etc. [Means for solving the problem]

[0013] One aspect of the present invention is a crystalline metal oxide, the crystalline metal oxide being a first layer and , and a second layer, the first layer having a wider band gap than the second layer, The second layer forms a crystal lattice, exciting carriers into the crystalline metal oxide. In this case, the carrier is transmitted through the second layer.

[0014] Another embodiment of the present invention is a crystalline metal oxide, the crystalline metal oxide comprising: a first layer and a second layer, the first layer having a wider band gap than the second layer; Each of the first layer and the second layer is approximately parallel to the surface of the crystalline metal oxide on which it is formed. The first layer and the second layer form a crystal lattice, forming a crystalline metal oxide. When carriers are excited in the object, the carriers are transmitted through the second layer.

[0015] Another embodiment of the present invention is a crystalline metal oxide, the crystalline metal oxide comprising: a first layer and a second layer, the first layer having a wider band gap than the second layer; The first layer is made of an element M (M is one or more selected from Al, Ga, Y, and Sn). The first layer comprises Zn, and the second layer comprises In. The first layer and the second layer are arranged approximately parallel to the surface on which the crystalline metal oxide is formed. Thus, when a crystal lattice is formed and carriers are excited in a crystalline metal oxide, Carriers are transmitted through the second layer.

[0016] Another embodiment of the present invention is a crystalline metal oxide, the crystalline metal oxide comprising: a first layer and a second layer, the first layer having a wider band gap than the second layer; Each of the first layer and the second layer is approximately perpendicular to the surface of the crystalline metal oxide on which it is formed. The first layer and the second layer form a crystal lattice, forming a crystalline metal oxide. When carriers are excited in the object, the carriers are transmitted through the second layer.

[0017] Another embodiment of the present invention is a crystalline metal oxide, the crystalline metal oxide comprising: a first layer and a second layer, the first layer having a wider band gap than the second layer; The first layer is made of an element M (M is one or more selected from Al, Ga, Y, and Sn). The first layer comprises Zn, and the second layer comprises In. The first layer and the second layer are arranged approximately perpendicular to the surface on which the crystalline metal oxide is formed. Thus, when a crystal lattice is formed and carriers are excited in a crystalline metal oxide, Carriers are transmitted through the second layer.

[0018] In the above crystalline metal oxide, the distance between the first layer and the second layer is 1 nm or less. In the above-mentioned crystalline metal oxide, the crystalline metal oxide is preferably When observed from the axial direction using a TEM, crystalline metal oxides have hexagonal lattice points. preferable.

[0019] Another embodiment of the present invention is a semiconductor device including a crystalline metal oxide and a gate, a source, and a drain. and a transistor having the first layer and the second layer, , the first layer has a wider band gap than the second layer, and the first layer and the second layer , each of which is arranged approximately parallel to the channel length direction of the transistor, and a first layer, The second layer forms a crystal lattice, and when a voltage is applied to the gate, the crystalline metal oxide is formed. When carriers are excited in the material, they are transported from the source to the drain through the second layer. The rear is transmitted.

[0020] Another embodiment of the present invention is a semiconductor device including a crystalline metal oxide and a gate, a source, and a drain. and a transistor having the first layer and the second layer, , the first layer has a wider band gap than the second layer, and the first layer and the second layer Each of the first and second layers is disposed approximately parallel to the surface of the crystalline metal oxide on which it is formed. The first and second layers form a crystal lattice, and when a voltage is applied to the gate, the crystalline metal oxide When carriers are excited in the second layer, the carriers are transferred from the source to the drain through the second layer. A is transmitted.

[0021] Another embodiment of the present invention is a semiconductor device including a crystalline metal oxide and a gate, a source, and a drain. and a crystalline metal oxide layer comprising a first layer and a second layer. , the first layer has a wider band gap than the second layer, and the first layer and the second layer Each of the first and second layers is disposed approximately perpendicular to the surface of the crystalline metal oxide on which it is formed. The first and second layers form a crystal lattice, and when a voltage is applied to the gate, the crystalline metal oxide When carriers are excited in the second layer, the carriers are transferred from the source to the drain through the second layer. A is transmitted.

[0022] Another embodiment of the present invention is a semiconductor device including a crystalline metal oxide and a gate, a source, and a drain. and a transistor having the crystalline metal oxide, a second metal oxide on the first metal oxide, and a third metal oxide on the second metal oxide. The first metal oxide, the second metal oxide, and the third metal oxide are each a first layer. and a second layer, the first layer having a wider band gap than the second layer, , and the second layer are arranged approximately parallel to the channel length direction of the transistor. A crystal lattice is formed by the first layer and the second layer, and a voltage is applied to the gate; When carriers are excited in a crystalline metal oxide, they are transported from the source through the second layer. Carriers are transferred from the gate to the drain.

[0023] Another embodiment of the present invention is a semiconductor device including a crystalline metal oxide and a gate, a source, and a drain. and a transistor having the crystalline metal oxide, a second metal oxide on the first metal oxide, and a third metal oxide on the second metal oxide. The first metal oxide, the second metal oxide, and the third metal oxide are each a first layer. and a second layer, the first layer having a wider band gap than the second layer, and the second gold The first layer of the second metal oxide and the second layer of the second metal oxide are each The metal oxide is disposed approximately parallel to the surface on which the metal oxide is formed, and the first layer and the second layer are A crystal lattice is formed, and when a voltage is applied to the gate, carriers are excited into the crystalline metal oxide. When the second layer is applied to the source, carriers are transferred from the source to the drain through the second layer.

[0024] In the above transistor, a third metal oxide The article covers a top surface and a side surface of the second metal oxide, and the gate covers the top surface of the second metal oxide and and covering the side surface of the second metal oxide, the side surface of the second metal oxide being in the c-axis direction of the third metal oxide and the It is preferable that the c-axis direction of the metal oxide of the first metal oxide is different from that of the second metal oxide.

[0025] Another embodiment of the present invention is a semiconductor device including a crystalline metal oxide and a gate, a source, and a drain. and a transistor having the crystalline metal oxide, a second metal oxide on the first metal oxide, and a third metal oxide on the second metal oxide. The first metal oxide, the second metal oxide, and the third metal oxide are each a first layer. and a second layer, the first layer having a wider band gap than the second layer, and the second gold The first layer of the second metal oxide and the second layer of the second metal oxide are each The metal oxide is disposed approximately perpendicular to the surface on which the metal oxide is formed, and the first layer and the second layer are A crystal lattice is formed, and when a voltage is applied to the gate, carriers are excited into the crystalline metal oxide. When the second layer is applied to the source, carriers are transferred from the source to the drain through the second layer.

[0026] In the transistor, a first region that does not overlap with the second metal oxide in the gate The bottom surface of the first region is lower than the bottom surface of the second metal oxide, and the first region and the second region are connected to each other at the gate. The bottom surface of the second region located opposite to the second metal oxide is the bottom surface of the second metal oxide. A lower position is preferable.

[0027] In the above transistor, a second metal oxide and a gate electrode are provided under the first metal oxide. It is preferable that the second gate overlaps at least a portion of the overlapping region of the first gate.

[0028] In the above transistor, either the channel length or the channel width of the transistor is Preferably, one or both have an area of ​​100 nm or less.

[0029] In the above transistor, the first layer is made of an element M (M is Al, Ga, Y, or S). n) and Zn, and the first layer contains In. is preferred. Effect of the Invention

[0030] According to one embodiment of the present invention, a novel metal oxide can be provided. According to one embodiment of the present invention, a novel transistor can be provided. In addition, a semiconductor device having a large on-state current can be provided. A semiconductor device having high frequency characteristics can be provided. In addition, according to one embodiment of the present invention, a semiconductor device with high reliability can be provided. It is possible to provide a semiconductor device that can be miniaturized or highly integrated. In this manner, a semiconductor device having good electrical characteristics can be provided.

[0031] According to another embodiment of the present invention, a semiconductor device capable of retaining data for a long period of time is provided. According to one embodiment of the present invention, a semiconductor device capable of writing data at a high speed can be provided. In addition, according to one embodiment of the present invention, power consumption can be reduced. A semiconductor device can be provided.

[0032] The description of these effects does not preclude the existence of other effects. An embodiment does not necessarily have all of these effects. Effects other than these are described in the specification. The above will become apparent from the description, drawings, claims, etc. From the above description, it is possible to extract other effects. [Brief description of the drawings]

[0033] [Figure 1] 1A and 1B are a cross-sectional view and a band diagram of a transistor according to one embodiment of the present invention, a diagram illustrating crystals contained in a metal oxide according to one embodiment of the present invention, and a diagram illustrating the energy of the conduction band minimum of the crystals. [Diagram 2] A diagram explaining the layer structure of a metal oxide crystal, and the lattice vibration of metal oxide atoms and carrier transmission. [Diagram 3] A diagram explaining lattice vibration of metal oxide atoms and carrier transmission. [Figure 4] FIG. 1 is a perspective view of a transistor according to one embodiment of the present invention. [Diagram 5] 1A to 1C are cross-sectional views of a transistor according to one embodiment of the present invention and a diagram illustrating crystals contained in a metal oxide according to one embodiment of the present invention. [Figure 6] FIG. 1 is a cross-sectional view of a transistor according to one embodiment of the present invention. [Figure 7] FIG. 1 is a perspective view of a transistor according to one embodiment of the present invention. [Figure 8] FIG. 1 is a cross-sectional view of a transistor according to one embodiment of the present invention. [Figure 9] FIG. 1 is a perspective view of a transistor according to one embodiment of the present invention. [Figure 10] 1A to 1C are a cross-sectional view and a band diagram of a transistor according to one embodiment of the present invention, and a diagram illustrating crystals contained in a metal oxide according to one embodiment of the present invention. [Figure 11] 1A and 1B are a top view and a cross-sectional view of a semiconductor device according to one embodiment of the present invention. [Figure 12] FIG. 1 is a cross-sectional view of a semiconductor device according to one embodiment of the present invention. [Figure 13] Cross-sectional TEM image and planar TEM image of CAAC-OS, and their image analysis images. [Figure 14] Cross-sectional TEM image and local Fourier transform image of an oxide semiconductor. [Figure 15] 1A and 1B are a top view and a cross-sectional view of a semiconductor device according to one embodiment of the present invention. [Figure 16]1A and 1B are a top view and a cross-sectional view of a semiconductor device according to one embodiment of the present invention. [Figure 17] 1A and 1B are a top view and a cross-sectional view of a semiconductor device according to one embodiment of the present invention. [Figure 18] FIG. 1 is a cross-sectional view illustrating a configuration of a memory device according to one embodiment of the present invention. [Figure 19] FIG. 1 is a cross-sectional view illustrating a configuration of a memory device according to one embodiment of the present invention. [Figure 20] 1A and 1B are a block diagram and a schematic diagram illustrating a configuration example of a memory device of one embodiment of the present invention. [Figure 21] FIG. 1 is a circuit diagram illustrating a configuration example of a memory device according to one embodiment of the present invention. [Figure 22] 1A and 1B are schematic diagrams of a semiconductor device according to one embodiment of the present invention. [Diagram 23] FIG. 1 is a schematic diagram of a memory device according to one embodiment of the present invention. [Figure 24] 1A to 1C are diagrams illustrating electronic devices according to one embodiment of the present invention. [Diagram 25] 4 is a cross-sectional TEM image according to an embodiment of the present invention. [Figure 26] 4 is a cross-sectional TEM image according to an embodiment of the present invention. [Figure 27] 1A to 1C are diagrams illustrating a cross-sectional TEM image and an EDX line analysis of a sample according to an embodiment of the present invention. [Figure 28] 13A and 13B are graphs showing temperature dependence of VG-ID characteristics of a transistor. [Figure 29] FIG. 4 is a diagram for explaining a method of calculating an operating frequency. [Diagram 30] FIG. 13 is a diagram showing the calculation results of an operating frequency. [Diagram 31] FIG. 13 is a diagram showing the calculation results of an operating frequency. [Diagram 32] 1A and 1B are graphs showing carrier concentrations and Hall mobilities of oxide semiconductors according to one embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0034] Hereinafter, the embodiments will be described with reference to the drawings. It is understood that the present invention can be practiced in many different ways without departing from the spirit and scope of the present invention. It will be readily understood by those skilled in the art that various changes in form and details may be made. Therefore, the present invention should not be construed as being limited to the description of the following embodiment modes.

[0035] Also, in the drawings, the size, layer thickness, or area are exaggerated for clarity. Therefore, the drawings are not necessarily limited to the scale. The examples are shown in schematic form, and are not limited to the shapes or values ​​shown in the drawings. For example, In the actual manufacturing process, layers and resist masks are damaged by etching and other processes. However, in order to make it easier to understand, this is not reflected in the diagram. In the drawings, the same parts or parts having similar functions are designated by the same reference numerals in different drawings. In addition, when referring to similar functions, In such cases, the hatch patterns may be the same and no particular reference numbers may be used.

[0036] In addition, the invention is easily understood, particularly in top views (also called "plan views") and perspective views. In order to simplify the description, some of the components may be omitted. The above information may be omitted.

[0037] In addition, in this specification, ordinal numbers such as 1st, 2nd, etc. are used for convenience. It does not indicate the order of processes or stacking. For example, "first" may be changed to "second "the" or "third" can be used as appropriate. The ordinal numbers described herein may not coincide with the ordinal numbers used to identify an aspect of the present invention. There are cases where this is the case.

[0038] In addition, in this specification, the terms "above" and "below" that indicate an arrangement are used to refer to the relationship between components. The positional relationship is used for convenience in describing the drawings. The relationship changes accordingly depending on the direction in which each configuration is depicted. The terms are not limited to those described above, and may be rephrased appropriately depending on the situation.

[0039] For example, in the present specification, it is explicitly stated that X and Y are connected. The cases are when X and Y are electrically connected and when X and Y are functionally connected. The case where X and Y are directly connected and the case where X and Y are directly connected are disclosed in the present specification, etc. Therefore, the connection relationship is limited to a specific one, for example, the connection relationship shown in the figure or text. Connections other than those shown in the drawings or text are also disclosed in the drawings or text. It shall be so.

[0040] Here, X and Y are objects (e.g., devices, elements, circuits, wiring, electrodes, terminals, conductive films, layer, etc.).

[0041] In this specification, a transistor includes a gate, a drain, and a source. The drain terminal is a diode that has at least three terminals. Between the drain region or drain electrode and the source (source terminal, source region or source electrode) The channel forming region is formed in the channel. A current can be passed between the source and drain via the channel forming region. In this specification and the like, the channel formation region refers to a region through which current mainly flows.

[0042] In addition, the functions of the source and drain may differ depending on whether transistors of different polarities are used or the circuit In operation, when the direction of the current changes, the positions may be reversed. In the specification, the terms source and drain may be used interchangeably. do.

[0043] Note that the channel length is, for example, the length of a semiconductor (or transistor) in a top view of a transistor. When the transistor is on, the gate electrode overlaps with the semiconductor (the part through which current flows). A source (source region or source electrode) in a region where the source is formed or a channel forming region This refers to the distance between the drain (drain region or drain electrode) and the transistor. In a transistor, the channel length does not necessarily have the same value in all regions. The channel length of the transistor may not be determined to a single value. In the above, the channel length is a value, a maximum value, a minimum value, or a range of values ​​in the channel forming region. or the average value.

[0044] The channel width is, for example, the width of the semiconductor (or transistor) in a top view of the transistor. The area where the gate electrode overlaps with the semiconductor (the part where current flows in the semiconductor when the transistor is on). In the channel forming region, the channel is formed in a direction perpendicular to the channel length direction. The length of the formation region. Note that in one transistor, the channel width is the entire region. In other words, the channel width of a transistor does not always take the same value. Therefore, in this specification, the channel width is determined as the width of the channel forming region. The value is any one of the values, the maximum value, the minimum value or the average value.

[0045] In this specification and the like, depending on the structure of the transistor, the channel may not actually be formed. The channel width in the region where the transistor is The channel width shown in a top view of the star (hereinafter also referred to as the "apparent channel width") For example, if the gate electrode covers the side of the semiconductor, the effective When the channel width becomes larger than the apparent channel width and its effect cannot be ignored For example, in a transistor that is very small and has a gate electrode that covers the side of the semiconductor, The proportion of the channel formation region formed on the side may become large. In that case, the apparent The effective channel width is larger than the above channel width.

[0046] In such cases, it may be difficult to estimate the effective channel width through actual measurements. For example, to estimate the effective channel width from the design value, the shape of the semiconductor must be known. Therefore, if the shape of the semiconductor is not known accurately, Channel width is difficult to measure accurately.

[0047] In this specification, when the term "channel width" is used, it refers to the apparent channel width. In this specification and the like, when the term "channel width" is used, it means the effective channel width. In addition, channel length, channel width, effective channel width, apparent channel width, The channel width and other parameters can be determined by analyzing cross-sectional TEM images, etc. This can be done.

[0048] The impurities in a semiconductor are, for example, substances other than the main components that make up the semiconductor. Elements with a concentration of less than 0.1 atomic percent can be considered impurities. For example, This can cause problems such as an increase in the density of defect levels in semiconductors and a decrease in crystallinity. When the semiconductor is an oxide semiconductor, the impurities that change the characteristics of the semiconductor include, for example, , Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and oxides There are transition metals other than the main components of semiconductors, such as hydrogen, lithium, sodium, and silicon. In the case of oxide semiconductors, water also functions as an impurity. In the case of an oxide semiconductor, for example, oxygen vacancies caused by the inclusion of impurities can be eliminated. In addition, when the semiconductor is silicon, there are cases where a defect that changes the properties of the semiconductor is formed. The pure substances include, for example, oxygen, Group 1 elements excluding hydrogen, Group 2 elements, Group 13 elements, and Group 1 elements. Group 5 elements, etc.

[0049] In this specification and the like, silicon oxynitride refers to a material having a composition containing more oxygen than nitrogen. Silicon nitride oxide is a material that contains more oxygen than silicon. It has a high nitrogen content.

[0050] In addition, in this specification, the term "insulator" may be replaced with "insulating film" or "insulating layer." In addition, the term "conductor" can be replaced with "conductive film" or "conductive layer." In addition, the term "semiconductor" can be replaced with "semiconductor film" or "semiconductor layer." can.

[0051] In addition, in this specification, "parallel" means that two straight lines are at an angle of -10 degrees or more and 10 degrees or less. Therefore, it includes the case where the angle is between -5 degrees and 5 degrees. In addition, "approximately parallel" refers to a state in which two straight lines are arranged at an angle of -30 degrees or more and 30 degrees or less. "Perpendicular" refers to a state where two straight lines are arranged at an angle of 80 degrees or more and 100 degrees or less. Therefore, it includes the case where the angle is between 85 degrees and 95 degrees. "Perpendicular" refers to two straight lines that form an angle between 60 degrees and 120 degrees.

[0052] In this specification and the like, the term "barrier film" refers to a film that prevents the permeation of impurities such as water and hydrogen, and oxygen. If the barrier film is conductive, it is called a conductive barrier. It is sometimes called the rear membrane.

[0053] In this specification, the term "metal oxide" refers to metals in a broad sense. Metal oxides are oxide insulators and oxide conductors (including transparent oxide conductors). ), oxide semiconductor (also called oxide semiconductor or simply OS) For example, when a metal oxide is used for the semiconductor layer of a transistor, Such a metal oxide may be called an oxide semiconductor. In this case, the transistor can be referred to as a transistor including an oxide or an oxide semiconductor. Cut.

[0054] In this specification and the like, normally off means that no potential is applied to the gate, or The current per 1 μm of channel width that flows through a transistor when a ground potential is applied to the gate At room temperature, -20 A or less, 1×10 at 85℃ -18 A or below, or 1×10 at 125℃ -16 This means that it is A or lower.

[0055] (Embodiment 1) In this embodiment, a metal oxide according to one embodiment of the present invention and a semiconductor device having the metal oxide will be described. The transistor will be described with reference to FIGS.

[0056] <Example of transistor configuration> FIG. 1A is a cross-sectional view of a transistor 10 of one embodiment of the present invention in the channel length direction. do.

[0057] As shown in FIG. 1A, a transistor 10 is disposed on a substrate (not shown). An oxide 230, an insulator 250 disposed on the oxide 230, and a dielectric layer 260 disposed on the insulator 250. The oxide 230 also includes a conductor 260 disposed in the channel of the transistor 10. A region 234 which functions as a region in which a hole is formed (hereinafter also referred to as a channel formation region) , a region 231 (region 231a and region 231b) functioning as a source region or a drain region 231b). The insulator 250 functions as a gate insulating film. 260 functions as a gate electrode.

[0058] FIG. 1B shows a transistor shown in FIG. 1A at a point indicated by X1-X2. This is a model of the band diagram on the dashed line. In Fig. 1(B), we ignore the k-space. FIG. 1(B) shows a state where no voltage is applied between the gate and the source. The solid line on the conductor 260 indicates the position of the Fermi surface of the conductor 260. The solid line at 50 indicates the position of the conduction band minimum of the insulator 250. The solid line indicates the position of the conduction band minimum of the oxide 230.

[0059] The transistor 10 controls the resistance of the channel portion by applying a potential to the gate. That is, the potential applied to the gate can change the conduction between the source and drain. It is possible to control the state of conduction (transistor is on) or non-conduction (transistor is off). do.

[0060] The transistor 10 has an oxide 230 including a channel forming region, which functions as a semiconductor. It is preferable to use a metal oxide (hereinafter, also referred to as an oxide semiconductor). Compared to semiconductors made of silicon and other materials, the switching characteristics of the transistors are good, This is preferable because an extremely small off-current can be obtained.

[0061] In addition, a transistor including an oxide semiconductor in a channel formation region has a Since the leakage current (off-state current) is extremely small, a semiconductor device with low power consumption can be provided. In addition, oxide semiconductors can be formed into films by sputtering or the like, and therefore are suitable for use as highly integrated semiconductors. It can be used in transistors that make up devices.

[0062] In addition, in a transistor using an oxide semiconductor, insufficient charge is generated in a channel formation region in the oxide semiconductor. The presence of impurities and oxygen vacancies can cause electrical characteristics to fluctuate and reduce reliability. In addition, when oxygen vacancies are present in the channel formation region of an oxide semiconductor, Therefore, oxygen vacancies in the channel formation region are For example, the oxide 23 is formed by interposing an insulator 250 or the like therebetween. By supplying oxygen to the SiO2 layer, the oxygen vacancies can be compensated for. This suppresses the fluctuation of electrical characteristics, It is possible to provide a transistor having stable electrical characteristics and improved reliability. can.

[0063] In addition, it is preferable to use a metal oxide having a low carrier density for the oxide 230. Intrinsic or substantially high purity intrinsic metal oxides have fewer carrier sources, The carrier density can be reduced. Also, the material is intrinsic or substantially intrinsic. The metal oxide has a low defect state density, and therefore may have a low trap state density.

[0064] For example, the oxide 230 may be an In-M-Zn oxide (wherein the element M is aluminum or gallium). Sodium, Yttrium, Tin, Copper, Vanadium, Beryllium, Boron, Titanium, Iron, Nickel , Germanium, Zirconium, Molybdenum, Lanthanum, Cerium, Neodymium, Hafnium One or more of the following materials are selected from the group consisting of aluminum, tantalum, tungsten, magnesium, etc. Metal oxides are preferably used. In particular, the element M is aluminum (Al), gallium (Ga), etc. , yttrium (Y), or tin (Sn) may be used. In-Ga oxide and In-Zn oxide may also be used.

[0065] In addition, conductive layers functioning as source and drain electrodes are formed on and in contact with the oxide 230. In this case, an element contained in the conductive film absorbs oxygen of the oxide 230. When the oxide 230 has a function of forming a conductive film, the oxide 230 is preferably provided between the oxide 230 and the conductive film, or in the vicinity of the surface of the oxide 230. In this case, a low resistance region may be formed partially in the low resistance region. Impurities (hydrogen, nitrogen, metal elements, etc.) that enter the defects function as donors, increasing the carrier density. In addition, at least a part of the low resistance region may be a source region or It is included in the region 231 which functions as the drain region.

[0066] Oxide semiconductors (metal oxides) are classified into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. As a non-single crystal oxide semiconductor, for example, CAAC-OS (c- axis aligned crystalline oxide semiconductor ctor), polycrystalline oxide semiconductor, nc-OS (nanocrystalline ox ide semiconductor), pseudo amorphous oxide semiconductor (a-like OS : amorphous-like oxide semiconductor) and non and amorphous oxide semiconductors.

[0067] The channel formation region of the transistor is provided with a metal oxide that increases the on-state current of the transistor. In order to increase the on-state current of the transistor, it is preferable to use a It is preferable to increase the mobility of the metal oxide used in the transistor. improves the transmission of carriers or reduces the sources of scattering that affect the transmission of carriers It is necessary to.

[0068] Therefore, it is possible to use a crystalline metal oxide for the oxide 230 including the channel formation region. It is preferable that the crystal of the metal oxide has a first layer and a second layer. It is preferable that the first layer and the second layer are alternately laminated to form a crystal structure. The first layer preferably has a wider band gap than the second layer. In the literature, the first layer is referred to as having a wider band gap than the second layer. The second layer has a gap smaller than the first layer. The narrow gap is sometimes expressed as the second layer having a narrow gap. The crystalline metal oxide has a narrow gap and a wide gap. It is preferred to have the crystals sandwiched between a first layer having a first crystal.

[0069] The oxide 230 has a first layer and a second layer, which respectively form the channel of the transistor 10. The first and second layers of the oxide 230 are arranged approximately parallel to the longitudinal direction. are each approximately parallel to the channel length direction of the transistor 10. In addition, each of the first layer and the second layer of the oxide 230 is an oxide. It is preferable that the insulating layer 220 is disposed approximately parallel to the surface on which the oxide 230 is formed.

[0070] Examples of crystalline metal oxides include single-crystal oxide semiconductors and CAAC-OS. Crystalline metal oxides can improve the transport of carriers. The mobility of the metal oxide is increased, and the on-state current of a transistor using the metal oxide is increased. As a result, the electrical characteristics of the transistor can be improved.

[0071] [Carrier transmission model] In the following, a carrier transport model in crystalline metal oxides will be explained. As an example of a crystalline metal oxide, CAAC-OS is given. is a metal oxide composed of indium, element M, zinc, and oxygen (In-M-Zn Also called oxide.

[0072] CAAC-OS has a c-axis orientation and multiple nanocrystals (maximum 1000) in the ab-plane direction. The crystal structure is made up of interconnected crystal regions with a large diameter of less than 10 nm. The distortion occurs when multiple nanocrystals are connected to each other, resulting in a region with a uniform lattice arrangement and another region with a different lattice arrangement. This refers to a region where the lattice arrangement changes direction between a region where the lattice arrangement is uniform and a region where the lattice arrangement changes direction.

[0073] When the CAAC-OS is viewed from the c-axis direction, the nanocrystals are basically hexagonal, but The shape is not limited to regular hexagons, and may be non-regular hexagons. In CAAC-OS, the lattice arrangement may be a heptagon. Even in this case, it is difficult to identify clear grain boundaries. In other words, it is clear that the formation of grain boundaries is suppressed by the distortion of the lattice arrangement. This is because the arrangement of oxygen atoms in CAAC-OS is not dense in the ab-plane direction and The substitution of metal elements changes the bond distance between atoms, allowing for distortion. This is because it is possible.

[0074] In addition, the hexagonal shape of a crystalline metal oxide is due to the transmission from the c-axis direction of the metal oxide. Transmission Electron Microscope (TEM) This can be confirmed by observing the image using an optical microscope.

[0075] An enlarged view of region 51 of oxide 230 shown in FIG. 1(A) is shown in FIG. 1(C). The compound 230 is an In-M-Zn oxide having a CAAC structure. a, and the composition of the oxide 230 is In:M:Zn=1:1:1 [atomic ratio]. In FIG. 1(C), the c-axis (c-axis) of the In-M-Zn oxide having the CAAC structure is The s) direction is the up-down direction of the paper, and the ab-plane direction is the left-right direction and normal direction of the paper. In FIG. 1C, the oxide 230 has a composition of In:M:Zn=1:1:1. [Atomic ratio] In-M-Zn oxide with CAAC structure was shown, but it is not limited to this. The oxide 230 may be any crystalline metal oxide, for example, a metal oxide having a composition formula of In (1+ α) M (1-α) O3(ZnO) m (α is a real number between 0 and 1, and m is a real number between 0 and 1.) The In-M-Zn oxide may have a CAAC structure or a single crystal structure.

[0076] As shown in FIG. 1(C), the In-M-Zn oxide having the CAAC structure has indium and a layer having element M, zinc, and oxygen (hereinafter, InO layer), and a layer having element M, zinc, and oxygen ( Hereinafter, the (M,Zn)O layer) is laminated to form a layered crystal structure (also called layered crystal or layered structure). In this specification, the (M,Zn)O layer is an InO layer and the like. A layer is disposed between the InO layer and an adjacent InO layer in the c-axis direction, and contains an element M, zinc, and oxygen. Indium, element M, and zinc are mutually substitutable. Therefore, some of the indium may be contained in the (M,Zn)O layer. A portion of the element M or a portion of zinc may be contained in the InO layer.

[0077] In this specification and the like, the structure in which the first layer and the second layer are alternately laminated is referred to as a crystal structure. If the unit cell of the crystal structure can be expressed by a certain space group, the stacked structure The structure is sometimes called a crystal lattice. For example, In-M-Zn oxide with the CAAC structure In this case, the first layer is an (M,Zn)O layer and the second layer is an InO layer. The child does not have to be formed of two layers, but may be formed of three or more layers.

[0078] In addition, the larger the distance between the first layer and the second layer, the The interaction between the two atoms becomes weaker, and the crystal lattice becomes structurally unstable. It is preferable that the distance between the atoms constituting the first layer and the second layer is close to the distance between the atoms constituting the second layer. The distance is preferably 1 nm or less, more preferably 0.7 nm or less, and even more preferably 0.5 nm or less. In this way, the crystal lattice formed by the first layer and the second layer is more preferably becomes structurally stable.

[0079] As shown in FIG. 1C, the c-axis of the crystal of the CAAC-OS is aligned along the oxide 230 The direction of the electron beam is normal to the surface on which the electron beam is formed or the film surface. In the cross-sectional view, the c-axis of the crystal of the CAAC-OS is oriented in the vertical direction of the paper. In addition, the ab plane of the crystal of the CAAC-OS is the surface on which the oxide 230 is formed or the film surface. In other words, the InO layer and the (M,Zn)O layer are approximately parallel to the oxide 2 30 on which the CAAC-OS is formed. The ab plane of the crystal is parallel to the left-right direction of the paper and to the normal direction to the paper.

[0080] Here, in the band diagram model shown in FIG. 1(B), the conduction of the oxide 230 An enlarged view of region 52 at the lower end of the band is shown in FIG. 1(D). In FIG. 1(D), k-space is ignored. It should be noted that the region 52 corresponds to the region 51 in the real space.

[0081] The ratio of the constituent elements contained in the InO layer and the (M,Zn)O layer is different. In addition, the InO layer and the (M,Zn)O layer have different band gaps. The InO layer and the (M,Zn)O layer have different electron affinities. and have different differences in the difference between the vacuum level energy and the conduction band minimum energy Ec.

[0082] Gallium oxide is known to have a larger band gap than indium oxide. Therefore, when the element M is Ga, the band gap of the (M,Zn)O layer is It is estimated that the band gap of the (M,Zn)O layer is larger than that of the InO layer. The summation force is estimated to be smaller than the electron affinity of the InO layer. The difference between the vacuum level energy and the conduction band minimum energy is It is estimated that this is greater than the difference between the vacuum level energy and the conduction band minimum energy. Therefore, the conduction band minimum of the InO layer is lower than that of the (M,Zn)O layer. It is estimated that the (M,Zn)O layer is located in the band gap region closer to the InO layer. Because the gap is large, the (M,Zn)O layer is sometimes described as having a wide gap. In addition, the InO layer has a smaller band gap than the (M,Zn)O layer. The nO layer is sometimes said to have a narrow gap.

[0083] In addition, since the InO layer and the (M,Zn)O layer form a crystal lattice, The conduction band minimum and the conduction band minimum of the (M,Zn)O layer are at the boundary between the InO layer and the (M,Zn)O layer. Therefore, as shown in Figure 1(D), The conduction band minimum of the oxide 230 is equal to the conduction band minimum of the InO layer and the conduction band minimum of the (M,Zn)O layer. It is assumed that the edge of the band is a level that appears repeatedly. In the figure, the vicinity of the bottom of the conduction band of the (M,Zn)O layer is convex, and the conduction band of the InO layer is The bottom end is recessed. The InO layer and the (M,Zn)O layer are oriented in the ab-plane direction. Since the conduction band edge in the ab-plane direction is constant, the carriers are The electrons are more likely to be transmitted along the ab-plane direction of the InO layer, where the conduction band minimum is lower.

[0084] Carriers injected from the source are sandwiched between the (M,Zn)O layers with a wide gap. The focus is on the narrow-gap InO layer, which is shown in Fig. 1(C) and Fig. 1(D). D) The carrier transport direction, i.e., the direction from the source to the drain, is the InO layer. This roughly coincides with the ab-plane direction (the left-right direction of the paper and the normal direction of the paper). In other words, the main carrier transmission path is the InO layer. When excited, carriers are transported through the InO layer.

[0085] Carriers flow from the source to the drain through the channel forming region. To increase the transmission speed of the semiconductor memory, it is necessary to increase the channel formation region so that carriers can easily flow in the channel length direction. As described above, in the crystal of the In-M-Zn oxide, Therefore, the ab plane of the In-M-Zn oxide crystal is It is preferable to align the surface in the direction of carrier flow.

[0086] The layered structure also preferably extends to the region 231 of the oxide 230. In this way, the region 231a and the region 231b are separated by the channel forming region. This can facilitate the transmission of carriers.

[0087] It is estimated that the electrons are quantized and move in the ab-plane direction. The electrons contained in the InO layer are Since the (M,Zn)O layer blocks the electrons and there is no lattice scattering, the electrons are guided in the ab-plane direction of the InO layer. In other words, the mobility in the ab plane direction is estimated to be higher than that in the c-axis direction. do.

[0088] CAAC-OS is a highly crystalline metal oxide. Since it is difficult to confirm the grain boundaries, the trap level density due to the grain boundaries is low. The lower end spreads in the ab-plane direction (this specification refers to the large level). It is assumed that the electron mobility is unlikely to decrease. The crystallinity of metal oxides can be reduced by the inclusion of impurities or the generation of defects. AAC-OS can be said to be a metal oxide with few impurities and defects (such as oxygen vacancies). Therefore, the physical properties of the metal oxide having CAAC-OS are stable. Metal oxides having -OS are heat resistant and highly reliable.

[0089] In addition, the higher the temperature, the higher the mobility of metal oxides tends to be. This is due to the lattice dispersion. The thermal lattice vibration of atoms and the transmission of carriers are shown in Figure 1. 2 and 3.

[0090] FIG. 2(A) shows the crystal structure of an In-M-Zn oxide having a CAAC structure. In A), W_(M,Zn)O represents the thickness of the (M,Zn)O layer in the c-axis direction. , W_(M,Zn)O is the (M,Zn) band in the band diagram shown in Figure 1(D). It can also be said that W_InO is the width of the convex part of the conduction band minimum of the InO layer. In addition, W_InO is the In band diagram shown in FIG. This can also be referred to as the width of the depression at the bottom of the conduction band of the O layer.

[0091] In addition, Wa_(M,Zn)O shown in FIG. 2(B) is a temperature T that is a reference temperature (e.g., The thickness of the (M,Zn)O layer in the c-axis direction at room temperature (RT) 2B shows the temperature T as a reference temperature (for example, room temperature (R The thickness of the InO layer in the c-axis direction is shown in Fig. 1 when the thickness is almost the same as that of the InO layer in Fig. 2(C), Wb_(M,Zn)O is a material with temperature T being a reference temperature (e.g., room temperature (R. T)) , Wb_InO shown in FIG. 2(C) is a temperature T that is a reference temperature (for example, room temperature (RT 2 shows the thickness of the InO layer in the c-axis direction when the temperature is higher than that of the InO layer in the In (B) and (C), the wavy lines on the right side of the figure indicate the paths along which carriers are transmitted through the InO layer. This shows how it works.

[0092] The larger the mass number of an atom is, the smaller the lattice vibration caused by heat becomes. In the case of In-Ga-Zn oxide, the mass number of the atom is the largest, followed by Ga and Therefore, Ga and Zn have a higher thermal oxidation rate than In. The lattice vibration is large. Therefore, when the temperature increases, the (Ga,Zn The vibration of the atoms that make up the (Ga,Zn)O layer increases. In comparison, the atomic bonds between the InO layer and the (Ga,Zn)O layer are weaker, so Ga and Zn The lattice vibration in the c-axis direction is larger than that in the ab-plane direction. Ga_(Ga,Zn)O is larger than Wa_(Ga,Zn)O (see Figure 2(C)). Assuming that the lattice constant in the c-axis direction of the layered crystal does not change with temperature, Wb_(Ga As the (Zn)O layer becomes larger, the Wb_InO becomes relatively smaller (see Figure 2(C)). In other words, the higher the temperature, the smaller the thickness of the InO layer in the c-axis direction.

[0093] 3(A) to 3(C) are band diagrams of the crystal structure shown in FIG. 2(A). 3(A) to 3(C) are schematic diagrams showing the structure of the InO layer and how carriers are transmitted through the InO layer. In 3(C), the source is at the back of the paper and the drain is at the front of the paper. The left-right direction of the paper corresponds to the c-axis direction of CAAC-OS. In the figure, the wavy curved surface indicates the conduction band minimum of the CAAC-OS. In 3(C), the black circles represent carriers (e.g., electrons) and the dotted lines are schematic diagrams of the carriers. Show the trajectory.

[0094] Figure 3(A) shows a model with a temperature Ta that is almost the same as the reference temperature (e.g., room temperature (RT)). Wa_(M,Zn)O is the width of the convex part at the bottom of the conduction band of the (M,Zn)O layer. Wa_InO is the width of the depression at the bottom of the conduction band of the InO layer. The model shows a temperature Tb higher than the temperature at which the electrons are released (e.g., room temperature (RT)), and Wb_ (M,Zn)O is the width of the convex part at the bottom of the conduction band of the (M,Zn)O layer, and Wb_InO is the In The width of the depression at the bottom of the conduction band of the O layer is shown in Fig. 3(C). Wc_(M,Zn)O is the width of the convex part at the bottom of the conduction band in the (M,Zn)O layer. and Wc_InO is the width of the depression at the bottom of the conduction band of the InO layer.

[0095] As mentioned above, when the temperature increases, the (Ga,Zn)O layer is more oxidized than the InO layer. The vibration of the atoms in the (Ga,Zn)O layer is larger than that in the InO The bond between the (Ga,Zn)O layer and the (Ga,Zn)O layer is weak, so the lattice vibrations of Ga and Zn in the c-axis direction The lattice vibration in the ab plane direction is larger than that in the ab plane direction. Thus, Wc_(Ga,Zn)O>Wb_(Ga,Zn)O>Wa_(Ga,Zn)O, If we assume that the lattice constant in the c-axis direction of the layered crystal does not change with temperature, then W As the amount of Ga,Zn)O increases, the amount of W_InO becomes relatively small. As shown in FIG. 3(A) to (C), Wa_InO>Wb_InO>Wc_InO. In other words, the higher the temperature, the thinner the InO layer in the c-axis direction on the band diagram becomes. Become smaller.

[0096] As mentioned above, the main carrier transmission path is the InO layer. As the thickness of the InO layer in the c-axis direction on the band diagram decreases, the carriers The carriers are transmitted more planarly through the ab plane of the layer. The metal oxide has a higher mobility because the light is transmitted more linearly to the transistor. By using metal oxide in the channel formation region of the MOSFET, the frequency characteristics improve as the temperature increases. will improve.

[0097] As mentioned above, the higher the temperature, the more planar the carriers propagate along the ab plane of the InO layer. In other words, in crystalline metal oxides, the carriers are scattered by lattice vibration (so-called It is assumed that the phonon scattering is unlikely to occur. By narrowing the drain (also called shortening the channel), the drain electric field becomes stronger, and the carrier drift The improvement in drift velocity due to the shortened channel is due to phonon scattering. However, in crystalline metal oxides, phonon scattering is difficult to occur, The drift velocity increase due to the short channel is difficult to suppress. It is expected that metal oxides are less likely to exhibit short channel effects. It is possible to miniaturize a transistor using an oxide for a channel formation region. For example, Either or both of the channel length and the channel width of the transistor are set to 100n The area can be less than m.

[0098] In this specification, a narrow gap layer is sandwiched between a first layer having a wide gap. The transport of carriers along the ab plane in the second layer is called multi-layer conduction (MALT). -Atomic Layers Transport). The material in which T occurs is a layer with a narrow gap between the first and second layers. The semiconductor material is not limited to the first and second layers. Even if the carrier is selectively or preferentially transferred to either the first layer or the second layer, Examples of materials in which MALT occurs include graphene stacks. Examples of such graphite include

[0099] <Transistor modification 1> 4 is a perspective view of a transistor 10a according to one embodiment of the present invention. In the figure, some elements are omitted for clarity. Also, in Fig. 5(A) and Fig. 5(B), 5A is a cross-sectional view of a transistor 10a according to one embodiment of the present invention. FIG. 2 is a cross-sectional view of the transistor 10a taken along the line A1-A2; FIG. 5B is a cross-sectional view in the channel length direction. 1 is a cross-sectional view of a transistor 10a in the channel width direction of the transistor 10a. It is also a plan view.

[0100] As shown in FIG. 5A, the transistor 10a is disposed on a substrate (not shown). An insulator 224, an oxide 230b disposed on the insulator 224, and a metal oxide 230b disposed on the oxide 230b. an oxide 230c disposed on the insulating layer 230c; an insulator 250 disposed on the oxide 230c; and a conductor 260 disposed on the body 250.

[0101] As shown in FIG. 5B, the oxidized layer is formed in the channel width direction of the transistor 10a. The insulating material 230c is provided so as to cover the upper and side surfaces of the oxide 230b. The edge 250 is formed so as to cover the upper and side surfaces of the oxide 230b via the oxide 230c. The conductor 260 is provided through the oxide 230c and the insulator 250. It is provided to cover the top and side surfaces of oxide 230b.

[0102] The insulator 250 functions as a gate insulating film. The conductor 260 functions as a gate electrode. The oxide 230b also functions as a channel forming region of the transistor 10a. and a region 231 (region 232) that functions as a source region or a drain region. 1a, and region 231b). The channel forming region has oxide 230c. The insulating layer 20 may be formed as follows.

[0103] As shown in FIG. 5B, the transistor 10a has a first layer including an oxide 230b. Each of the second layers is approximately 100 nm to the surface on which the oxide 230b is formed (the upper surface of the insulator 224). The transistor 10 differs from the transistor 10 in that it is arranged vertically. The arrangement direction of the first layer and the second layer of the oxide 230b of a is determined by the surface on which the oxide 230b is formed. It can be said that the transistor 10 differs from the transistor 10 in that the transistor 10 is parallel to the surface. In the transistor 10a, the first and second layers of the oxide 230b are The transistor 10 is disposed approximately parallel to the channel length direction. The oxide 230b of the substrate 10a is formed by forming a first layer and a second layer. 10, except that the oxide 230 of the transistor 10 is disposed generally perpendicular to the growth surface. They have a similar configuration.

[0104] Here, an enlarged view of region 53 of oxide 230b shown in FIG. 5(B) is shown in FIG. 5(C). The oxide 230b shown in FIG. 5(C) is an In-M-Zn oxide having a CAAC structure. do.

[0105] As shown in FIG. 5C, in the oxide 230b of the transistor 10a, CAAC- The c-axis of the crystal of the OS is aligned with the surface on which the oxide 230b is formed or the film surface. Therefore, in FIG. 5B, the CAAC-OS has The c-axis of the crystal is oriented in the left-right direction of the paper. The b-plane is approximately parallel to the normal direction to the surface on which the oxide 230b is formed or the film surface. In other words, the InO layer and the (M,Zn)O layer are arranged approximately perpendicular to the surface on which they are formed. Therefore, in FIG. 5B, the ab plane of the crystal of CAAC-OS is It is parallel to the up-down direction of the paper and the normal direction of the paper.

[0106] When providing such an oxide 230b, for example, a structure is formed on the insulator 224, The oxide film 230b is formed on the side surface of the structure, and then the structure is removed. Here, it is preferable that the side surface of the structure is approximately perpendicular to the upper surface of the insulator 224. I wish.

[0107] In addition, in the channel width direction of the transistor 10a, At this time, the bottom surface of the conductor 260 in the region not overlapping with the oxide 230b is In particular, in the conductor 260, the oxide 230b overlaps the bottom surface of the oxide 230. The bottom surface of the first region that is not folded (which can also be called the bottom surface on the A3 side) and the conductor 260 In the figure, the bottom surface (A The bottom surface of the oxide 230b is preferably lower than the bottom surface of the oxide 230b. Here, the oxide 230b and the conductor 260 are preferably in a region where they do not overlap. The difference between the height of the bottom surface of 260 and the height of the bottom surface of the oxide 230b is 0 nm or more and 100 nm or less. or less, preferably 3 nm or more and 50 nm or less, more preferably 5 nm or more and 20 nm or less Let us assume that.

[0108] A conductor 260 functioning as a gate electrode is formed on the side of the oxide 230b in the channel forming region. The upper surface is covered with an oxide 230c and an insulator 250. As shown in Fig. 2B, the electric field of the conductor 260 is easily applied to the entire region 234 of the oxide 230b. In particular, by placing the bottom surface of the conductor 260 below the bottom surface of the oxide 230b, the conductor The electric field of body 260 can also be applied to the bottom surface of oxide 230b.

[0109] In this way, in the cross section of the transistor 10a in the channel width direction, the gate is exposed from almost the entire periphery. A ground field can be applied to region 234 of oxide 230b. Since a channel can be formed throughout region 234 of transistor 30b, The on-current can be increased and the frequency characteristics can be improved. By forming a channel in the entire region 234 of the transistor 10b, the off-current of the transistor 10a is It is also possible to reduce the

[0110] Here, the oxide 230b has a thickness and a length in the channel width direction of several nm to several tens of nm. It is preferable to form such an oxide 230b into a long and thin wire shape. As shown in FIG. 4 and FIG. 5, oxide 230b and oxide 2 30c, the insulator 250, and the conductor 260 can be formed into an elongated wire-like structure. These can also be called nanowires. As shown, the electric field of the conductor 260 can be applied to the entire region 234 of the oxide 230b. Therefore, they can also be called nanowire transistors.

[0111] The oxide 230b of the transistor 10a is as follows compared to the oxide 230 of the transistor 10: In this case, the metal oxide layer is rotated by 90 degrees around the axis of the channel length. The transistor 10a is nanowire-like, i.e., conductive across the region 234 of the oxide 230b. By applying an electric field to the conductive body 260, the metal oxide layer is Therefore, the metal oxide 230b is formed on the surface on which the oxide 230b is formed. Even if the angles of the layers of the oxide are different, the transistors 10a and 10 have the same characteristics. Then it can be regarded as.

[0112] In addition, the oxide 230c contains a metal oxide having a larger band gap than the oxide 230b. Alternatively, a metal oxide having a small electron affinity may be used. Metal oxides having a small difference between the energy of the vacant level and the energy of the conduction band minimum may be used. In this way, the probability that carriers can move to the gate electrode and the gate insulating film is can be reduced.

[0113] In addition, when the oxide 230c has a function of suppressing the diffusion of oxygen, the oxide 230b The oxide 230 can be prevented from diffusing into the gate insulating film or the gate electrode. When the oxide 230c has a function of suppressing the diffusion of impurities, the oxide 230c is formed above the oxide 230c. This can suppress the diffusion of impurities from the structure into the oxide 230b.

[0114] In addition, although the oxide 230c is illustrated as a single layer in FIG. 4 and FIG. 5, the oxide 230c is A laminated structure may also be used.

[0115] <Transistor modification 2> FIG. 6 shows a transistor 10b as a modification of the transistor 10a. 6B is a cross-sectional view of a transistor 10b according to one embodiment of the present invention. FIG. 6A is a cross-sectional view of the transistor 10b in the channel length direction. 1 is a cross-sectional view of a transistor 10b in a channel width direction.

[0116] In addition, in the transistor 10b, the transistor 10 and the transistor 10a are configured The same reference numerals are used for structures that have the same functions as those of the structures that form the same components. The materials constituting the transistor 10b are described in detail in the transistors 10 and 10a. The materials described in can be used.

[0117] The transistor 10b has an oxide 230b and a conductor 260 overlapping under the insulator 224. The transistor 10 has a conductor 205 overlapping at least a portion of the region. The transistor 10b is different from the transistor 10a. Compound 230c is not provided.

[0118] Here, the conductor 260 functions as a first gate (also called a top gate) electrode. The conductor 205 may also serve as a second gate (also called a back gate) electrode. In this case, the potential applied to the conductor 205 may be the potential applied to the conductor 260. By changing the potential applied to the transistor 10b independently of the potential applied to the transistor 10b, the threshold voltage The voltage (Vth) can be controlled. In particular, applying a negative potential to the conductor 205 This makes it possible to increase the Vth of the transistor 10b and reduce the off-current. Therefore, applying a negative potential to the conductor 205 is more effective than not applying a negative potential. The drain current when the potential applied to the conductor 260 is 0 V can be reduced.

[0119] The conductor 205 is provided to be larger than the channel formation region in the oxide 230b. In particular, as shown in FIG. 6B, the conductor 205 is formed in the channel of the oxide 230b. It is preferable that the film is stretched also in the region outside the end portion intersecting with the width direction. , a conductor 205 and a conductor It is preferable that 260 overlaps with an insulator 224 interposed therebetween.

[0120] By having the above-mentioned structure, as shown in FIG. 6(B), the first gate electrode The electric field of the conductor 260 and the electric field of the conductor 205, which functions as the second gate electrode, The oxide 230b can electrically surround the channel forming region. This electric field allows a stronger electric field to be applied to the bottom surface of the oxide 230b.

[0121] In this way, in the cross section of the transistor 10b in the channel width direction, the gate is exposed from almost the entire periphery. A ground field can be applied to region 234 of oxide 230b. Since a channel can be formed throughout the region 234 of transistor 30b, The on-current can be increased and the frequency characteristics can be improved. By forming a channel in the entire region 234 of the transistor 10b, the off-current of the transistor 10b is It is also possible to reduce the

[0122] In addition, like the transistor 10a, the transistor 10b has a conductor 260 and a conductor The electric field of the body 205 can be applied to the entire region 234 of the oxide 230b, so that the nano They can be called wire or nanowire transistors.

[0123] In this specification and the like, the electric field of the first gate electrode and the second gate electrode The structure of the transistor that electrically surrounds the channel formation region is called surrounded It can also be called a channel (S-channel) structure.

[0124] <Transistor modification 3> 7 and 8 show a transistor 10c as a modification of the transistor 10a. FIG. 7 is a perspective view of a transistor 10c according to one embodiment of the present invention. In order to clarify the figure, some elements are omitted. Also, in Figs. 8(A) and 8(B), FIG. 8A is a cross-sectional view of a transistor 10c according to one embodiment of the present invention. FIG. 1-A2 is a cross-sectional view of the transistor 10c; 8B is a cross-sectional view in the channel length direction. 1 is a cross-sectional view of a transistor 10c in the channel width direction. It is also a diagram.

[0125] In addition, in the transistor 10c, the transistor 10, the transistor 10a, and The same reference numerals are used to designate structures having the same functions as those constituting the transistor 10b. In this section, the constituent materials of the transistor 10c are the transistor 10, The materials described in detail for the transistors 10a and 10b can be used.

[0126] Transistor 10c has oxide 230a between insulator 224 and oxide 230b. The transistor 10a differs from the transistor 10a in that the oxide 230 is a Oxide 230a, oxide 230b on oxide 230a, and oxide 230b on oxide 230b. 30c.

[0127] It is preferable to use the same oxide as the oxide 230c for the oxide 230a. For example, The oxide 230a is made of a metal oxide having a larger band gap than the oxide 230b. Alternatively, a metal oxide having a small electron affinity may be used. Alternatively, a metal oxide having a small difference between the energy of the first gate and the energy of the bottom of the conduction band may be used. By doing so, the probability that carriers can move to the insulator 224 can be reduced.

[0128] The oxide 230a has an upper surface that is at least SiO 2 - ... It is preferable that the first oxide layer 230b contacts the first oxide layer 230b and the side surface of the first oxide layer 230c contacts the second oxide layer 230b. By this, in the region 234, the oxide 230b is separated from the oxide 230a and the oxide 230b. Thus, the oxide 230b can be covered by the insulator in the region 234. 224 and the insulator 250. This allows the oxide 230b to be isolated. This reduces the probability that carriers can move to the outside, and prevents oxygen from diffusing to the outside and from The diffusion of impurities can be suppressed.

[0129] <Modification of Transistor 4> 9 is a perspective view of a transistor 10d according to one embodiment of the present invention. In the figure, some elements are omitted for clarity. FIG. 10B is a cross-sectional view of a transistor 10d according to one embodiment of the present invention. FIG. 10 is a cross-sectional view of a transistor 10d taken along the line A1-A2 in FIG. FIG. 10(B) is a cross-sectional view of the channel length direction of 10d. FIG. 1 is a cross-sectional view of a transistor 10d in the direction shown, showing the channel width of the transistor 10d. It is also a cross-sectional view in the direction.

[0130] In addition, in the transistor 10d, the transistor 10, the transistor 10a, The structures having the same functions as the structures constituting the transistors 10b and 10c are designated by the same reference numerals. In this section, the material of the transistor 10d is Transistor 10, transistor 10a, transistor 10b and transistor 10c in detail The materials described in can be used.

[0131] As shown in FIG. 10A, the transistor 10d is disposed on a substrate (not shown). The insulator 224 is formed of an oxide 230b. The oxide 230b is formed on the insulator 224. an oxide 230c disposed on the insulating layer 230; an insulator 250 disposed on the oxide 230c; and a conductor 260 disposed on the edge 250.

[0132] As shown in FIG. 10B, the oxide is formed in the channel width direction of the transistor 10d. The oxide 230c is provided so as to cover the upper surface and side surfaces of the oxide 230b. The insulator 250 is formed so as to cover the upper and side surfaces of the oxide 230b via the oxide 230c. The conductor 260 is provided through the oxide 230c and the insulator 250. , which is provided to cover the top and side surfaces of oxide 230b.

[0133] The insulator 250 functions as a gate insulating film. The conductor 260 functions as a gate electrode. The oxide 230b also functions as a channel forming region of the transistor 10d. and a region 231 (region 232) that functions as a source region or a drain region. 1a, and region 231b). The channel forming region has oxide 230c. The second insulating layer 21 may be formed as follows.

[0134] In addition, in the channel width direction of the transistor 10d, At this time, the bottom surface of the conductor 260 in the region not overlapping with the oxide 230b is The conductor 260, which functions as a gate electrode, is preferably located at a position lower than the bottom surface of the channel 260. The side and top surfaces of the oxide 230b in the hole formation region are covered with the oxide 230c and the insulator 250. By covering the oxide 230b, the electric field of the conductor 260 is generated in the entire region 234 of the oxide 230b. This increases the on-state current of the transistor 10d and improves the frequency characteristics. In the region where the oxide 230b and the conductor 260 do not overlap, The difference between the height of the bottom surface of the conductor 260 and the height of the bottom surface of the oxide 230b is 0 nm or more and 10 0 nm or less, preferably 3 nm to 50 nm, more preferably 5 nm to 20 nm m or less.

[0135] At least one of the oxide 230b and the oxide 230c is made of a crystalline metal oxide. Specifically, it is preferable that at least the oxide 230b and the oxide 230c are One of the layers is preferably a single crystal oxide semiconductor or a CAAC-OS.

[0136] In addition, although the oxide 230b is illustrated as a single layer, it may have a laminated structure. When the oxide 230b has a two-layer laminate structure, the lower layer of the oxide 230b contacts the insulator 224 and The upper layer of the oxide 230b is in contact with the oxide 230c. Impurities from structures formed below the lower layer of the oxide 230b into the oxide 230b Diffusion can be suppressed.

[0137] Here, an enlarged view of the region 54 of the oxide 230b shown in FIG. 10(B) is shown in FIG. In addition, the region 55 of the oxide 230c shown in FIG. 10(B) is shown in FIG. 10(E). The oxide 230b and the oxide 230c are In-M-Zn oxides having a CAAC structure. It is.

[0138] As described above, when the oxide 230b is a CAAC-OS, the oxide 230b has The c-axis of the crystal is oriented in the normal direction to the surface on which the oxide 230b is formed or the film surface, and The -b plane is approximately parallel to the surface on which the oxide 230b is formed or the film surface. In the region 54 of the oxide 230b shown in FIG. 10(D), the c-axis of the crystal of the oxide 230b is The direction of the (c-axis) is the vertical direction of the paper. The ab-plane is parallel to the left-right direction of the paper and to the normal direction of the paper.

[0139] The c-axis of the crystal of the CAAC-OS is approximately oriented perpendicular to the surface on which the CAAC-OS is formed. The ab plane is approximately parallel to the surface on which the CAAC-OS is formed. In the case where a crystalline metal oxide is used for the oxide 230c, the oxide 23 shown in FIG. In the 0c region 55, the crystal c-axis of the oxide 230c is oriented as follows: The ab plane of the crystal of the oxide 230c is the top and bottom of the paper. direction, and is parallel to the normal direction to the paper surface.

[0140] From the above, it is found that the oxide 230b is active on the dashed line indicated by X5-X6 in FIG. 10(B). The c-axis direction of the crystal of the oxide 230c is different from the c-axis direction of the crystal of the oxide 230c.

[0141] [Carrier transmission model 2] Here, the oxide 230b and the oxide 230c are stacked in a transistor. Rear transmission will be explained using the carrier transmission model explained above.

[0142] FIG. 10C shows the transistor 10d shown in FIG. The band diagram model shown in Fig. 1 is on the dashed line indicated by X5-X6. FIG. 10(C) shows the state where a positive potential is applied to the gate electrode. The oxide 230b and the oxide 230c are made of metal oxides having the same conduction band minimum energy. Here is an example.

[0143] On the dashed line X5-X6 shown in FIG. 10B, inside the oxide 230b, The ab plane of the crystal of the compound 230b is approximately parallel to the substrate surface. The energy of the conduction band minimum of the oxide 230b on the dashed line indicated by X6 is constant. In addition, inside the oxide 230b, the electric field is oriented in the ab-plane direction of the crystal of the oxide 230b. In addition, the electric field inside the oxide 230b is stronger than that on the surface of the oxide 230b. Therefore, the bending of the conduction band minimum inside the oxide 230b is small.

[0144] On the other hand, in the oxide 230c, an electric field is generated in the c-axis direction of the crystal of the oxide 230c. Furthermore, the electric field generated by oxide 230c is greater than the electric field present within oxide 230b. Therefore, the band bending in the oxide 230c is large (see the dotted line in FIG. 10(C)). In addition, the ab plane of the crystal of the oxide 230c is located on the dashed line indicated by X5-X6. is approximately perpendicular to the substrate surface. Therefore, as shown in FIG. 10(C), On the dashed line, the conduction band minimum of the oxide 230c is different from the conduction band minimum of the InO layer ( The conduction band minimums originating from the (M,ZnO) layers appear alternately.

[0145] At this time, the carriers injected from the source flow through the oxide 230c, which has a lower conduction band edge. In addition, the carriers are transported between the source and drain. From the above, the main The carrier transmission path is the InO layer of the oxide 230b or the InO layer of the oxide 230c. become.

[0146] If the carriers are too concentrated, repulsion occurs between the carriers due to Coulomb forces, In the case of metal oxides having layered crystals, the transmission of carriers is suppressed as shown in FIG. As shown in the figure, there are multiple InO layers, which are the main carrier transmission paths, and therefore multiple carriers are Therefore, the carrier concentration is reduced and the carriers are dispersed among the InO layers. Therefore, repulsion due to Coulomb force is unlikely to occur, and carrier transmission is not inhibited.

[0147] The oxide 230c has a metal oxide having a larger band gap than the oxide 230b. Alternatively, a metal oxide having a small electron affinity may be used. Metal oxides having a small difference between the energy of the vacant level and the energy of the conduction band minimum may be used. In this way, the probability that carriers can move to the gate electrode and the gate insulating film is can be reduced.

[0148] 9 and 10, the oxide 230c is illustrated as a single layer, but it may have a laminated structure. For example, when the oxide 230c has a two-layer laminate structure, the lower layer of the oxide 230c is an oxide The upper layer of the oxide 230c contacts the insulator 250. The lower layer of the oxide 230c is made of a metal oxide having the same composition as the oxide 230b. The upper layer of 0c is preferably made of a metal oxide having a larger band gap than the oxide 230b. With this structure, carriers can move to the gate electrode and the gate insulating film. Alternatively, the upper layer of the oxide 230c may suppress the diffusion of oxygen. When the oxide 230b and the oxide 230c have a function, the oxide in the lower layer of the oxide 230b and the oxide in the lower layer of the oxide 230c form a gate insulating film. Alternatively, the diffusion of the oxide 230c to the gate electrode can be suppressed. When the layer has a function of suppressing the diffusion of impurities, it is formed above the upper layer of the oxide 230c. The diffusion of impurities from the structure thus formed to the lower layer of oxide 230c and oxide 230b is suppressed. It is possible.

[0149] The above-described examples of the transistor configuration and the modified examples of the transistor configuration may be appropriately combined with each other. It can be used.

[0150] As described above, a semiconductor device including a transistor with large on-state current can be provided. In addition, a semiconductor device having a transistor with high frequency characteristics can be provided. In addition, the fluctuation of electrical characteristics is suppressed, the electrical characteristics are stable, and the reliability is improved. In addition, a semiconductor device having a transistor with low off-state current can be provided. It is possible to provide a semiconductor device.

[0151] The configurations and methods shown in the present embodiment may be modified in any manner in accordance with the configurations and methods shown in other embodiments or examples. The method can be used in combination with other methods.

[0152] (Embodiment 2) An example of a specific structure of the semiconductor device described in the above embodiment will be described below with reference to FIGS. This will be explained with reference to FIG.

[0153] <Configuration Example 1 of Semiconductor Device> 11A to 11C illustrate a transistor 200 according to one embodiment of the present invention, and 1A and 1B are a top view and a cross-sectional view of a transistor 200 and its surroundings.

[0154] FIG. 11A is a top view of a semiconductor device including a transistor 200. 1(B) and 11(C) are cross-sectional views of the semiconductor device. FIG. 11A is a cross-sectional view of a portion indicated by a dashed line A1-A2 in FIG. FIG. 11(C) is a cross-sectional view of the channel length direction of 0. Also, FIG. 11(A) shows the A3-A FIG. 4 is a cross-sectional view of a portion indicated by a dashed line in FIG. 4, and is a cross-sectional view of a transistor 200 in a channel width direction. In addition, in the top view of FIG. 11(A), some elements are omitted for clarity. do.

[0155] The semiconductor device of one embodiment of the present invention includes a transistor 200 and an insulator serving as an interlayer film. 214, an insulator 280, an insulator 274, and an insulator 281. A conductor 240 (conductor 240a, and conductor 240b). Note that the conductor 240 functions as a plug. Insulators 241 (insulator 241a and insulator 241b) are provided.

[0156] In addition, the side walls of the openings of the insulators 254, 280, 274, and 281 An insulator 241 is provided in contact with the first conductor of the conductor 240. A second conductor of the conductor 240 is provided on the inner side. The height of the upper surface of the transistor 20 and the height of the upper surface of the insulator 281 can be made to be approximately the same. In FIG. 00, a first conductor of the conductor 240 and a second conductor of the conductor 240 are stacked. However, the present invention is not limited to this configuration. The structure may be a single layer or a laminated structure of three or more layers. If they have such structures, they may be distinguished by assigning ordinal numbers in the order of their formation.

[0157] [Transistor 200] As shown in FIG. 11, transistor 200 includes an insulating layer disposed on a substrate (not shown). The insulating body 216 is provided with a conductor 205 disposed so as to be embedded in the insulating body 216. 16 and on the conductor 205, and an insulator 222 disposed on the insulator 222. An insulator 224 is formed on the insulating layer 224, and an oxide 230 (oxide 230a, The oxide 230b and the oxide 230c) and the insulator 25 disposed on the oxide 230 0, and a conductor 260 (conductor 260a and conductor 260) disposed on the insulator 250. b), and conductors 242a and 242b in contact with a portion of the top surface of oxide 230b; A part of the upper surface of the insulator 222, a side surface of the insulator 224, a side surface of the oxide 230a, and an oxide 230 b, a side surface of the conductor 242a, an upper surface of the conductor 242a, a side surface of the conductor 242b, and and an insulator 254 disposed in contact with the upper surface of the conductor 242b.

[0158] The conductor 260 functions as a gate electrode of the transistor, and the conductors 242a and The body 242b functions as a source electrode or a drain electrode, respectively. In FIG. 00, a conductor 260 that functions as a gate electrode is formed on an insulator 280 or the like. The conductor 260 is formed in a self-aligned manner so as to fill the opening. conductor 260 is aligned in the region between conductor 242a and conductor 242b. The arrangement can be ensured without any distortion.

[0159] The conductor 260 is made up of a conductor 260a and a conductor 260b arranged on the conductor 260a. For example, the conductor 260a has a bottom surface 60b. It is preferable that the casing is arranged so as to wrap around the sides. The top surface of the conductor 260 is approximately flush with the top surface of the insulator 250 and the top surface of the oxide 230c. Note that although the conductor 260 in the transistor 200 has a two-layer structure, However, the present invention is not limited to this. For example, even if the conductor 260 has a single-layer structure, Alternatively, it may have a laminated structure of three or more layers.

[0160] The insulators 222, 254, and 274 are made of hydrogen (e.g., hydrogen atoms, hydrogen It is preferable that the insulating material has a function of suppressing the diffusion of at least one of the molecules. 222, insulator 254, and insulator 274 are oxygen (e.g., oxygen atoms, oxygen molecules, etc.) For example, the insulator 222 has a function of suppressing the diffusion of at least one of the above. , insulator 254, and insulator 274 have higher hydrogen and oxygen concentrations than insulator 224, respectively. It is preferable that one or both of the insulators have low permeability. The insulator 274 is more permeable to hydrogen and / or oxygen than the insulator 250. The insulators 222, 254, and 274 are preferably insulators having a low It is preferable that the permeability to one or both of hydrogen and oxygen is lower than that of the edge 280 .

[0161] The oxide 230 is made up of an oxide 230a disposed on the insulator 224 and an oxide 230b. and a second oxide layer 230b disposed on the second oxide layer 230b, the second oxide layer 230b being at least partially oxide-coated. It is preferable that the oxide 230c is in contact with the upper surface of the oxide 230b. As shown in FIG. 1C, in the channel width direction of the transistor 200, the oxide 230c It is preferable that the oxide 230b is provided so as to cover the top and side surfaces of the oxide 230b.

[0162] Here, the oxide 230, the insulator 250, the conductor 260, the insulator 224, and the conductor 2 05 is a transistor 10 or transistors 10a to 10c shown in the above embodiment. This corresponds to the configuration of the transistor 10d.

[0163] In the transistor 200, a region in which a channel is formed (hereinafter, a channel forming region ) and in the vicinity thereof, oxide 230a, oxide 230b, and oxide 2 30c are laminated, the present invention is not limited to this. For example, a single layer of oxide 230b, a two-layer structure of oxide 230a and oxide 230b, The structure may be a two-layer structure of the substrate 230b and the oxide 230c, or a laminate structure of four or more layers. In addition, each of the oxide 230a, the oxide 230b, and the oxide 230c may be two. It may have a laminated structure of more than one layer.

[0164] For example, the oxide 230c may be a multilayer structure of a first oxide and a second oxide on the first oxide. In the case of a layered structure, the first oxide has a composition similar to that of the oxide 230b, and the second oxide has a composition similar to that of the oxide 230c. The second oxide may have a similar composition to oxide 230a.

[0165] The transistor 200 also includes an oxide 230 (oxide 230a) including a channel formation region. , oxide 230b, and oxide 230c) are added with a metal oxide functioning as a semiconductor (hereinafter It is preferable to use a semiconductor material other than the insulating film (also referred to as an oxide semiconductor).

[0166] The transistor 200 having an oxide semiconductor in a channel formation region is in a non-conducting state. Since the leakage current (off-state current) is extremely small, a semiconductor device with low power consumption can be provided. In addition, oxide semiconductors can be formed into films by sputtering or the like, and therefore are suitable for use as highly integrated semiconductors. It can be used for the transistor 200 that constitutes the device.

[0167] For example, the oxide 230 may be an In-M-Zn oxide (wherein the element M is aluminum or gallium). Sodium, Yttrium, Tin, Copper, Vanadium, Beryllium, Boron, Titanium, Iron, Nickel , Germanium, Zirconium, Molybdenum, Lanthanum, Cerium, Neodymium, Hafnium One or more of the following materials are selected from the group consisting of aluminum, tantalum, tungsten, magnesium, etc. Metal oxides are preferably used. In particular, the element M is aluminum, gallium, yttrium, Alternatively, tin may be used. In-Ga oxide, In-Zn oxide, etc. may be used as the oxide 230. Alternatively, Ga-Zn oxide or Ga-Zn carbide may be used.

[0168] As described above, the oxide 230 corresponds to the oxide 230 shown in the previous embodiment. The oxide 230 including the channel forming region of the transistor 200 is formed of a crystalline metal oxide. It is preferable to use the crystals of the metal oxide. It is preferable that the first layer and the second layer are alternately laminated to form a crystal structure. It is also preferable that the first layer has a wider band gap than the second layer. Examples of crystalline metal oxides include single-crystal oxide semiconductors and CAAC-OS. Crystalline metal oxides can improve the transport of carriers. The mobility of the metal oxide is increased, and the on-state current of a transistor using the metal oxide is increased. As a result, the electrical characteristics of the transistor can be improved.

[0169] Furthermore, as described above, at least one of the oxide 230b and the oxide 230c is It is preferable to use a crystalline metal oxide. Specifically, the oxide 230b and the oxide At least one of 230c is a single crystal oxide semiconductor or a CAAC-OS. Here, FIG. 11C shows the channel of the transistor 200, similar to FIG. 10B. Therefore, for the region 54 of the oxide 230b shown in FIG. The corresponding region has the crystal structure shown in FIG. 10(D) and the oxide 230c shown in FIG. 10(B). The region corresponding to the region 55 has the crystal structure shown in FIG. Since the model of the schematic band diagram shown in FIG. 10(C) is satisfied, the This can prevent suppression of rear transmission.

[0170] As shown in FIG. 11B, a portion of the oxide 230c is located near the interface between the oxide 230c and the insulator 274. It is preferable that the region where the oxide 230 is formed and the channel forming region of the oxide 230 are physically separated from each other. In the vicinity of the interface between the oxide 230c and the insulator 274, the trap state density may be high. Therefore, the region located near the interface between the oxide 230c and the insulator 274 and the oxide By increasing the physical distance between the channel forming region of the object 230 and the transistor 200, Fluctuations in characteristics can be suppressed and reliability can be improved.

[0171] In addition, in a transistor using an oxide semiconductor, insufficient charge is generated in a channel formation region in the oxide semiconductor. The presence of impurities and oxygen vacancies can cause electrical characteristics to fluctuate and reduce reliability. In addition, when oxygen vacancies are present in the channel formation region of an oxide semiconductor, Therefore, oxygen vacancies in the channel formation region are For example, the oxide 230c or the insulator 250 is preferably as thin as possible. By supplying oxygen to the oxide 230 via a gas such as a gaseous electrolyte, the oxygen vacancies can be compensated for. A transistor with stable electrical characteristics and improved reliability, with reduced fluctuations in characteristics. The star can be provided.

[0172] In addition, the oxide 230 is provided in contact with the oxide 230 and functions as a source electrode and a drain electrode. The elements contained in the conductor 242 (conductor 242a and conductor 242b) are oxides. In the case where the oxide 230 has a function of absorbing oxygen, the oxide 230 is formed between the conductor 242 or between the oxide 230 and the conductor 242. In some cases, a low resistance region may be formed in the vicinity of the surface of the oxide 230. In the low resistance region, impurities (hydrogen, nitrogen, metal elements, etc.) that have entered oxygen vacancies act as donors. This can function to increase the carrier density.

[0173] 12A is an enlarged view of a part of the transistor 200 shown in FIG. As shown in FIG. 12A, a conductor 242 is provided on and in contact with an oxide 230. The oxide 230 has a low resistance region at its interface with the conductor 242 and in its vicinity. 243 (region 243a and region 243b) may be formed. The oxide 230 may be 2, a region 234 which functions as a channel formation region of the transistor 200 and a small region 243 A region 231 (region 232) that functions as a source region or a drain region 31a, and region 231b). Even when region 243 is not shown, a similar region 243 may be formed.

[0174] The region 243a and the region 243b are adjacent to the conductor 242 of the oxide 230b. In the example shown, the ion implantation layer is provided so as to diffuse in the depth direction, but the present invention is not limited to this. The regions 243a and 243b are appropriately selected according to the desired electrical characteristics of the transistor. In addition, the boundaries of the oxide regions 230 can be clearly detected. It can be difficult to distinguish between the elements detected in each region. Furthermore, the color may change continuously (also called gradation) within each region.

[0175] As shown in FIG. 11B, the insulator 254 is made of the conductor 242a and the conductor 24 conductor 242a and conductor 242b, and the opposing side surfaces of conductor 242a and conductor 242b. The side surfaces of the conductive body 242a and the conductive body 242b and the side surfaces of the oxide 230a and the oxide 230b It is preferable that the insulating layer 224 contacts the surface of the insulating material 222, the side surface of the insulating material 224, and a part of the upper surface of the insulating material 222. As a result, the insulator 280 is formed by the insulator 254, the oxide 230a, and oxide 230b. Therefore, hydrogen and the like contained in insulator 280 and the like impurities from being mixed into the insulator 224, the oxide 230a, and the oxide 230b. It is possible.

[0176] The insulator 274 is disposed on each of the conductor 260, the insulator 250, and the oxide 230c. In addition, the transistor 200 according to one embodiment of the present invention has a structure as shown in FIG. As shown in FIG. 1, the insulator 274 and the insulator 250 are in contact with each other. By this, impurities such as hydrogen contained in the insulator 281 are prevented from being mixed into the insulator 250. Therefore, the electrical characteristics and signal quality of the transistor can be improved. This can suppress the adverse effects on reliability.

[0177] 12A, the bottom surface of the insulator 224 is taken as a reference, and the area overlapping the area 234 is taken as a reference. The height of the bottom surface of the conductor 260 in the region is the height of the bottom surface of the conductor 242a and the bottom surface of the conductor 242b. For example, the height of the upper surface of the region overlapping the region 234 may be lower than the height of the upper surface of the region. The height of the bottom surface of the conductor 260 and the height of the top surfaces of the conductors 242a and 242b are The difference in height between the first and second electrodes is 0 nm or more and 30 nm or less, or 0 nm or more and 15 nm or less.

[0178] 11C is an enlarged view of a part of the transistor 200 shown in FIG. As in the previous embodiment, the insulating layer 202 is formed in the channel width direction of the transistor 200. Based on the bottom surface of the body 222, the area where the conductor 260 and the oxide 230b do not overlap is Preferably, the height of the bottom surface of the conductor 260 is lower than the height of the bottom surface of the oxide 230b. A conductor 260 functioning as a gate electrode is formed on the side and the oxide 230b of the channel forming region. The upper surface of the conductor 230 is covered with the oxide 230c and the insulator 250. 60 to the entire region 234 of the oxide 230b. The on-current of the gate 200 can be increased, and the frequency characteristics can be improved. a and oxide 230b, and conductor 260 in the region where they do not overlap. If the difference between the height of the bottom surface and the height of the bottom surface of the oxide 230b is T2, T2 is 0 nm or less. At most 100 nm, preferably at least 3 nm and at most 50 nm, more preferably at least 5 nm The thickness should be 20 nm or less.

[0179] As shown in FIG. 12B, the oxide is formed in the channel width direction of the transistor 200. The oxide 230c in the region that does not overlap the insulator 224 is the oxide 230b, the oxide 230a, and the insulator 224. At least a part of the insulating material 222 is preferably in contact with the insulating material 222. The oxygen contained in the oxide 230c flows through the insulator 224 to the outside of the transistor 200. In addition, the oxide 230b and the oxide 230a can be prevented from diffusing. Preventing oxygen from diffusing through the insulator 224 to the outside of the transistor 200 In addition, the area of ​​the insulator 224 is reduced, so that the amount of oxygen taken in by the insulator 224 is reduced. The amount of oxygen supplied to the oxide 230 can be reduced. The oxygen contained in the oxide 230c is efficiently converted into the oxide 230b and the oxide 230a. Therefore, the decrease in the resistance of the oxide 230 in the region 234 can be suppressed. Therefore, the fluctuation of the electrical characteristics of the transistor can be suppressed, and the transistor has stable electrical characteristics. At the same time, reliability can be improved.

[0180] In addition, by adopting the above-mentioned configuration, impurities such as hydrogen contained in the insulator 224 are oxidized. In other words, the oxide 230 is prevented from being mixed with the oxide 230. Therefore, the fluctuation of the electrical characteristics of the transistor can be suppressed, and the electrical characteristics can be stabilized. In addition, the oxide 230 can be formed on the surface of the insulating film 230. b, and removing the insulator 224 in the areas not overlapping the oxide 230a to form It is possible.

[0181] Also, the oxide 230b and the insulator 224 in the area not overlapping the oxide 230a are removed. As a result, as shown in FIG. 12B, in the channel width direction of the transistor 200, , the oxide 230a and the oxide 230b, and the conductor 222 are arranged on the basis of the bottom surface of the insulator 222. The height of the bottom surface of the conductor 260 in the region where the conductor 260 does not overlap with the bottom surface of the oxide 230b is Therefore, the on-current of the transistor 200 is increased. , the frequency characteristics can be improved.

[0182] As described above, a semiconductor device including a transistor with large on-state current can be provided. In addition, a semiconductor device having a transistor with high frequency characteristics can be provided. In addition, the fluctuation of electrical characteristics is suppressed, the electrical characteristics are stable, and the reliability is improved. In addition, a semiconductor device having a transistor with low off-state current can be provided. It is possible to provide a semiconductor device.

[0183] The following describes in detail the configuration of a semiconductor device including a transistor 200 according to one embodiment of the present invention. This article explains:

[0184] The conductor 205 is disposed so as to overlap the oxide 230 and the conductor 260. The conductor 205 is preferably embedded in the insulators 214 and 216. Here, it is preferable to improve the flatness of the upper surface of the conductor 205. For example, The average surface roughness (Ra) of the upper surface of 205 is 1 nm or less, preferably 0.5 nm or less, and more preferably This allows the insulating layer formed on the conductor 205 to be 0.3 nm or less. 224, and the oxide 230a, the oxide 230b, and the oxide 230c are bonded to each other. The crystallinity can be improved.

[0185] Here, the conductor 260 functions as a first gate (also called a top gate) electrode. The conductor 205 may also serve as a second gate (also called a back gate) electrode. In this case, the potential applied to the conductor 205 may be the potential applied to the conductor 260. By changing the potential of the transistor 200 independently of the potential of the transistor 202, the threshold voltage of the transistor 200 can be adjusted. The voltage (Vth) can be controlled. In particular, applying a negative potential to the conductor 205 This makes it possible to increase the Vth of the transistor 200 and reduce the off-current. Therefore, applying a negative potential to the conductor 205 is more effective than not applying a negative potential. The drain current when the potential applied to the conductor 260 is 0 V can be reduced.

[0186] As shown in FIG. 11(A), the conductor 205 is a channel-shaped oxide 230. In particular, as shown in FIG. 11C, the conductor 205 The oxide 230 extends beyond the end portion intersecting with the channel width direction. That is, on the outer side of the side surface of the oxide 230 in the channel width direction, It is preferable that the conductor 205 and the conductor 260 overlap with each other via an insulator.

[0187] With the above-mentioned configuration, the electric field of the conductor 260 functioning as the first gate electrode and the The electric field of the conductor 205, which acts as the gate electrode of the second, causes the oxide 230 to change its channel shape. The composite region can be electrically surrounded.

[0188] As shown in FIG. 11C, the conductor 205 is extended to function as a wiring. However, the present invention is not limited to this. In addition, the conductor 205 does not necessarily have to be provided for each transistor. For example, the conductor 205 may be shared by multiple transistors. This is also fine.

[0189] The conductor 205 is a conductive material mainly composed of tungsten, copper, or aluminum. Although the conductor 205 is illustrated as a single layer, it may be formed as a laminated structure. For example, a laminate of titanium, titanium nitride and the above conductive material may be used.

[0190] In addition, hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, and nitric oxide are present under the conductor 205. It has the function of suppressing the diffusion of impurities such as elementary molecules (N2O, NO, NO2, etc.) and copper atoms. Alternatively, a conductor that is impermeable to the above impurities may be provided. The material has a function of suppressing the diffusion of at least one of oxygen atoms, oxygen molecules, etc. (the oxygen is not allowed to penetrate the material) It is preferable to provide a conductor. The function of suppressing the diffusion of oxygen is to suppress either one or all of the above impurities or the above oxygen. The function is to suppress the spread of

[0191] By using a conductor having a function of suppressing the diffusion of oxygen under the conductor 205, It is possible to prevent the conductor 205 from being oxidized and the conductivity from decreasing. Examples of conductors having a function of controlling the temperature include tantalum, tantalum nitride, ruthenium, and It is preferable to use ruthenium oxide or the like for the conductive layer 205. In terms of the structure, the conductive material may be a single layer or a multilayer.

[0192] The conductor 205 is formed by a sputtering method, a chemical vapor deposition (CVD) method, or the like. cal Vapor Deposition method, Molecular Beam Epitaxy (MBE) Epitaxy (Epitaxy) method, Pulsed Laser Deposition (PLD) method d Laser Deposition (ALD) method or Atomic Layer Deposition (ALD) method This can be done using a method such as a layer deposition method.

[0193] In this embodiment, the conductor 205 is, for example, tantalum nitride, titanium nitride, tungsten nitride, or the like. A laminated film in which a conductive film is formed in the order of a stainless steel can be used.

[0194] The insulator 214 disposed on the substrate (not shown) prevents impurities such as water and hydrogen from entering the substrate. It is preferable that the insulating film functions as a barrier insulating film that suppresses diffusion of the insulating film from the side into the transistor 200. Therefore, the insulator 214 is preferably a hydrogen atom, a hydrogen molecule, a water molecule, a nitrogen atom, a nitrogen molecule, or the like. Suppresses the diffusion of impurities such as nitrogen oxide molecules (N2O, NO, NO2, etc.) and copper atoms. It is preferable to use an insulating material that has the function of preventing the impurities from penetrating. has a function of suppressing the diffusion of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, etc.). It is preferable to use an insulating material that is difficult for the oxygen to permeate.

[0195] For example, the insulator 214 is preferably made of aluminum oxide, silicon nitride, or the like. This allows impurities such as water and hydrogen to flow from the substrate side to the transistors rather than the insulator 214. It is possible to suppress the diffusion of the ferroelectric material to the insulator 224. This can suppress the oxygen from diffusing toward the substrate side relative to the insulator 214.

[0196] The insulator 214 can be formed by sputtering, CVD, MBE, PLD, or the like. This can be done by using an LD method or the like. In this embodiment, the insulator 214 is, for example, Alternatively, an aluminum oxide film formed by a sputtering method can be used.

[0197] The insulator 216 disposed on the insulator 214 functions as an interlayer film. The insulator 280 and the insulator 281 disposed on the insulating layer 54 also function as interlayer films. Here, the insulator 216, the insulator 280, and the insulator 281 functioning as interlayer films are It is preferable that the dielectric constant is lower than that of the insulator 214. Therefore, the parasitic capacitance between the wirings can be reduced. 80, and as the insulator 281, silicon oxide, silicon oxynitride, silicon nitride oxide , silicon nitride, silicon oxide doped with fluorine, silicon oxide doped with carbon, carbon and Silicon oxide doped with nitrogen, silicon oxide having vacancies, or the like may be used appropriately.

[0198] The insulator 216 may have a laminated structure. For example, the insulator 216 may have at least In either case, an insulator similar to the insulator 214 is provided at the portion in contact with the side surface of the conductor 205. With such a configuration, the oxygen contained in the insulator 216 may cause the conductor The conductor 205 can suppress the oxidation of the insulator 21. It is possible to suppress the absorption of oxygen contained in 6.

[0199] The insulator 216 can be formed by sputtering, CVD, MBE, PLD, or other methods. This can be done by using an LD method or the like. In this embodiment, the insulator 216 is, for example, Alternatively, a silicon oxynitride film formed by a CVD method can be used.

[0200] The insulator 222 and the insulator 224 function as gate insulators.

[0201] Here, it is preferable that the insulator 224 in contact with the oxide 230 is heated to release oxygen. In this specification, the oxygen released by heating is sometimes called excess oxygen. For example, The insulator 224 may be made of silicon oxide, silicon oxynitride, or the like. By providing an insulator in contact with the oxide 230, oxygen vacancies in the oxide 230 are reduced, The reliability of the transistor 200 can be improved.

[0202] Specifically, the insulator 224 is an oxide film from which part of the oxygen is released by heating. The oxide film which releases oxygen by heating is preferably a TDS (Thermal Desulfurization) film. The oxygen removal rate was calculated by oxygen atom conversion. The separation is 1.0×10 18 atoms / cm 3 More than 1.0×10 19 atom s / cm 3 More preferably, 2.0×10 19 atoms / cm 3 At least, or 3 .0×10 20 atoms / cm 3 The oxide film is as above. The surface temperature of the film is 100°C to 700°C or 100°C to 400°C. The lower range is preferred.

[0203] The insulator 224 may be formed by sputtering, CVD, MBE, PLD, or the like. This can be done by using an LD method or the like. In this embodiment, the insulator 224 is, for example, In this case, a silicon oxynitride film formed by a CVD method can be used. In the transistor 200 shown in FIG. 1, the insulator 224 is configured to have an island shape. For example, the insulator 224 may cover the entire surface of the insulator 222. It can also be made into a

[0204] The insulator 222 prevents impurities such as water and hydrogen from diffusing into the transistor 200 from the substrate side. For example, the insulator 222 is an insulating material. It is preferable that the insulator 222 and the insulator 254 have a lower hydrogen permeability than the insulator 224. Therefore, by surrounding the insulator 224, the oxide 230, etc., impurities such as water, hydrogen, etc. Diffusion from the outside into the insulator 224 and the oxide 230 can be suppressed.

[0205] Further, the insulator 222 is made of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, etc.). It is preferable that the material has a function of suppressing diffusion (i.e., the oxygen is less likely to permeate). For example, The insulator 222 preferably has a lower oxygen permeability than the insulator 224. The oxide 230 has a function of suppressing the diffusion of elements and impurities, so that the oxygen contained in the oxide 230 is In addition, the conductor 205 is preferably a material having a thickness of 100 nm or less, since it can reduce diffusion to the insulator 224 or the This can prevent the oxide 230 from reacting with the oxygen contained therein.

[0206] The insulator 222 is made of one or both of aluminum and hafnium, which are insulating materials. It is recommended to use an insulator containing oxide. Insulators containing oxides include aluminum oxide, hafnium oxide, aluminum and hafnium oxide, and It is preferable to use an oxide containing hafnium (hafnium aluminate). When the insulator 222 is formed using such a material, the insulator 222 is oxidized by the oxide 230. The emission of hydrogen and the diffusion of impurities such as hydrogen from the periphery of the transistor 200 into the oxide 230 are prevented. The insulator 222 functions as a layer that suppresses the electric field generated by the electric field. It is preferable to use hafnium oxide. For example, the insulator 222 is used as a gate insulating film. In this case, by using hafnium oxide for the insulator 222, the interface is more stable than that of aluminum oxide. The level density can be reduced in some cases.

[0207] Alternatively, for example, aluminum oxide, bismuth oxide, germanium oxide, etc. may be added to these insulators. tungsten oxide, yttrium oxide, Zirconium oxide may be added, or these insulators may be nitrided. Silicon oxide, silicon oxynitride or silicon nitride may be laminated on the insulator. .

[0208] The insulator 222 may be, for example, aluminum oxide, hafnium oxide, tantalum oxide, Zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrT These include so-called high-k materials such as (Ba,Sr)TiO3 (BST) or (Ba,Sr)TiO3 (BST). As miniaturization and high integration of transistors progresses, If the gate insulator is made thinner, problems such as leakage current may occur. By using a high-k material as the insulator, the physical thickness can be maintained while This makes it possible to reduce the gate potential during transistor operation.

[0209] The insulator 222 can be formed by sputtering, CVD, MBE, PLD, or the like. This can be done by using an LD method or the like. In this embodiment, the insulator 222 is, for example, Alternatively, hafnium oxide formed by the ALD method can be used.

[0210] As shown in FIG. 11C, the insulator 222 is formed in a region where it does not overlap with the oxide 230b. In some cases, the thickness of the oxide film in the insulator 222 may be thinner than that of the other regions. The thickness of the region not overlapping with the object 230b is determined when forming an opening in the insulator 280, etc. The thickness of the insulating film 216 or the conductive film 217 is sufficient to function as an etching stopper film. It is preferable that the film thickness is sufficient so that the surface of the conductive material 205 is not exposed.

[0211] The insulator 222 and the insulator 224 may have a laminated structure of two or more layers. In this case, the laminated structure is not limited to the same material, and may be made of different materials. For example, an insulator similar to the insulator 224 may be provided under the insulator 222. stomach.

[0212] The oxide 230 is made up of an oxide 230a, an oxide 230b on the oxide 230a, and an oxide 230b on the oxide 230a. The oxide 230c is located on the oxide 230b. The oxide 230a is located under the oxide 230b. As a result, impurities from the structure formed below the oxide 230a are transferred to the oxide 230b. The diffusion can be suppressed. In addition, by having the oxide 230c on the oxide 230b, Diffusion of impurities from structures formed above oxide 230c into oxide 230b can be suppressed.

[0213] The oxide 230 has a layered structure made of oxides having different atomic ratios of metal atoms. Specifically, in the metal oxide used for the oxide 230a, the constituent elements The atomic ratio of element M in the oxide 230b is the atomic ratio of element M in the metal oxide in the constituent elements. It is preferable that the atomic ratio of the metal oxide used for the oxide 230a is larger than that of the element M. In the metal oxide used for the oxide 230b, the atomic ratio of element M to In is It is preferable that the atomic ratio of element M to In is larger than that of element In. In the metal oxide used, the atomic ratio of In to the element M is It is preferable that the atomic ratio of In is larger than that of the element M in the metal oxide. The oxide 230c is a metal oxide that can be used for the oxide 230a or the oxide 230b. Things can be used.

[0214] In addition, it is preferable that the oxide 230b and the oxide 230c have crystallinity. For example, it is preferable to use CAAC-OS, which will be described later. The oxides used in this study have few impurities and defects (such as oxygen vacancies), high crystallinity, and a dense structure. Therefore, the oxygen from the oxide 230b by the source electrode or the drain electrode This makes it possible to suppress the pulling out of the oxide 230b even when a heat treatment is performed. Since oxygen extraction can be reduced, the transistor 200 can be manufactured at a high It is stable against high temperatures (so-called thermal budget).

[0215] In addition, the conduction band minimums of the oxides 230a and 230c are greater than the conduction band minimum of the oxide 230b. It is preferable that the oxide 230a and the oxide 230b are closer to the vacuum level than the lower end. It is preferable that the electron affinity of the oxide 230c is less than the electron affinity of the oxide 230b. In this case, the oxide 230c uses a metal oxide that can be used for the oxide 230a. Specifically, in the metal oxide used for the oxide 230c, it is preferable that the constituent elements The atomic ratio of element M in the metal oxide used for oxide 230b is It is preferable that the atomic ratio of M is larger than that of M. In addition, the metal oxide used for the oxide 230c is In the metal oxide used for the oxide 230b, the atomic ratio of element M to In is It is preferable that the atomic ratio of element M to In is larger than that of element In. In the metal oxides used in the present invention, the atomic ratio of In to element M is It is preferable that the atomic ratio of In to the element M in the metal oxide is larger than that of In.

[0216] Also, the oxide 230c is formed by the oxide 230c1 and the oxide 23 on the oxide 230c1. In the case of a laminated structure including oxide 230c2, the oxide 230a and the oxide 230c2 are in the conduction band below the conduction band. It is preferable that the edge is closer to the vacuum level than the conduction band minimum of the oxide 230b and the oxide 230c1. In other words, the electron affinity of the oxide 230a and the oxide 230c2 is preferably It is preferable that the electron affinity of the oxide 230c1 is smaller than that of the oxide 230b. In this case, the oxide 230c2 is made of a metal oxide that can be used for the oxide 230a. The material 230c1 is preferably a metal oxide that can be used for the oxide 230b. stomach.

[0217] Here, at the junctions of oxide 230a, oxide 230b, and oxide 230c, In other words, the oxide 230a, the oxide 230b, and The conduction band edge at the junction of the oxide 230c and the junction of the oxide 230c changes continuously or is called a continuous junction. In order to achieve this, the interface between the oxide 230a and the oxide 230b must be , and the defect levels of the mixed layer formed at the interface between oxide 230b and oxide 230c. It is better to reduce the density.

[0218] Specifically, oxide 230a and oxide 230b, and oxide 230b and oxide 230c, By having a common element other than oxygen (as the main component), a mixed layer with a low defect level density is formed. For example, when the oxide 230b is an In-Ga-Zn oxide, the oxide The material 230a and the oxide 230c are In-Ga-Zn oxide, Ga-Zn oxide, Gallium oxide may be used. In addition, the oxide 230c may be a mixture of the oxide 230c1 and the oxide In the case of forming a laminated structure with 230c2, for example, In-Ga-Zn oxide and the In-G A laminated structure of Ga-Zn oxide on a-Zn oxide, or In-Ga-Zn oxide and A laminated structure of gallium oxide on the In-Ga-Zn oxide can be used. Then, the laminated structure of the In-Ga-Zn oxide and the oxide not containing In was formed by the oxide 23 It may also be used as 0c.

[0219] Specifically, the oxide 230a is In:Ga:Zn=1:3:4 [atomic ratio], Alternatively, a metal oxide having an atomic ratio of In:Ga:Zn=1:1:0.5 may be used. , as the oxide 230b, In:Ga:Zn=4:2:3 [atomic ratio], or In:G A metal oxide having an atomic ratio of a:Zn=3:1:2 may be used. As the atomic ratio, In:Ga:Zn=1:3:4, In:Ga:Zn=4:2:3 atomic ratio], Ga:Zn=2:1[atomic ratio], or Ga:Zn=2:5[atomic ratio] In addition, a specific example of the oxide 230c having a laminated structure is as follows: The atomic ratio of In:Ga:Zn is 4:2:3 and the atomic ratio of In:Ga:Zn is 1:3:4. In:Ga:Zn=4:2:3 [atomic ratio] and Ga:Zn= 2:1 [atomic ratio], In:Ga:Zn=4:2:3 [atomic ratio], and Ga :Zn=2:5[atomic ratio], In:Ga:Zn=4:2:3[atomic ratio] and a laminated structure with gallium oxide.

[0220] At this time, the main path of the carriers is the oxide 230b or the oxide 230c. Alternatively, the oxide 230c may have a laminate structure including an oxide 230c1 and an oxide 230c2. In this case, not only the oxide 230b but also the oxide 230c1 becomes the main path of the carriers. By configuring the oxide 230a and the oxide 230c as described above, the oxide 23 At the interface between oxide 230a and oxide 230b, and at the interface between oxide 230b and oxide 230c This reduces the density of defect states at the interface, which reduces the effect of interface scattering on carrier conduction. The effect of the resistance change is reduced, and the transistor 200 can have a high on-state current and high frequency characteristics. In addition, when the oxide 230c has a laminated structure, the oxide 230b and the oxide In addition to the effect of reducing the defect state density at the interface with the oxide 230c, It is expected that the diffusion of the constituent elements of the insulating material 250 to the insulating material 250 side can be suppressed. In the present embodiment, the oxide 230c is formed into a laminated structure, and an oxide not containing In is positioned above the laminated structure. Therefore, it is possible to suppress the diffusion of In into the insulator 250. Because it functions as a gate insulator, if In gets mixed into the insulator 250, etc., it can cause transistor Therefore, by forming the oxide 230c in a laminated structure, the reliability can be improved. It is therefore possible to provide a semiconductor device having a high

[0221] The oxide 230 is preferably a metal oxide that functions as a semiconductor. For example, The metal oxide for the region 234 has a band gap of 2 eV or more, preferably 2.5 It is preferable to use metal oxides with a large band gap of 1.5 eV or more. By using such a material, the off-state current of a transistor can be reduced. By using a transistor, a semiconductor device with low power consumption can be provided.

[0222] The oxide 230a, the oxide 230b, and the oxide 230c are formed by sputtering. The deposition can be performed by using a deposition method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In the case of forming a film by a sputtering method, oxygen or It is preferable to use a mixed gas of nitrogen and a rare gas. This can improve the crystallinity of the oxide film.

[0223] In this embodiment, the oxide 230a is, for example, In:Ga:Zn=1:3:4[ The film was formed by sputtering using an In-Ga-Zn oxide target with a [atomic ratio]. The oxide 230b may be, for example, In: Using an In-Ga-Zn oxide target with an atomic ratio of Ga:Zn = 4:2:4.1 A metal oxide film formed by a sputtering method can be used. For example, In-Ga with an atomic ratio of In:Ga:Zn=4:2:4.1 is used as 30c1. -Zn oxide target was used to form a metal oxide film by sputtering. In addition, the oxide 230c2 may be, for example, In:Ga:Zn=1:3: 4 [atomic ratio] In-Ga-Zn oxide target was used for sputtering. A deposited metal oxide can be used.

[0224] On the oxide 230b, a conductor 242 is formed, which functions as a source electrode and a drain electrode. The thickness of the conductor 242 is, for example, For example, the thickness may be from 1 nm to 50 nm, and preferably from 2 nm to 25 nm.

[0225] The conductor 242 may be aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, etc. Ru, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, Magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium A metal element selected from rontium and lanthanum, or an alloy containing the above metal elements Alternatively, it is preferable to use an alloy of the above-mentioned metal elements. For example, titanium nitride tantalum, titanium nitride, tungsten, nitrides containing titanium and aluminum, tantalum and aluminum Ruthenium nitrides, ruthenium oxide, ruthenium nitride, strontium and ruthenium It is preferable to use an oxide containing lanthanum and nickel. Tantalum oxide, titanium nitride, titanium and aluminum nitride, tantalum and aluminum Nitrides containing ruthenium, ruthenium oxide, ruthenium nitride, and oxides containing strontium and ruthenium. The oxides containing lanthanum and nickel are conductive materials that are difficult to oxidize or absorb oxygen. This is preferable because it is a material that maintains its conductivity even when absorbed.

[0226] The conductor 242 may be formed by sputtering, CVD, MBE, PLD, or other suitable method. This can be done by using an LD method or the like. In this embodiment, the conductor 242 is, for example, Alternatively, a tantalum nitride film formed by a sputtering method can be used.

[0227] The insulator 254, like the insulator 214, is designed to prevent impurities such as water and hydrogen from entering the insulator 280. It is preferable that the insulating film functions as a barrier insulating film that suppresses diffusion of the insulating film from the side into the transistor 200. For example, insulator 254 preferably has a lower hydrogen permeability than insulator 224. Furthermore, as shown in FIG. 11(B), the insulator 254 is disposed on the upper and side surfaces of the conductor 242a. , the top and side surfaces of the conductor 242b, the side surfaces of the oxide 230a and the oxide 230b, It is preferable that the insulating material 224 contacts the side of the insulating material 224. 280 is separated from the insulator 224 and the oxide 230 by the insulator 254. As a result, hydrogen contained in the insulator 280 is converted into conductors 242a, 242b, and oxide. The oxide 230 extends from the top or sides of the insulator 224 to the oxide 230. Since the dissipation of the ions can be suppressed, the transistor 200 has good electrical characteristics and reliability. It can give you sex.

[0228] Further, the insulator 254 is made of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, etc.). It is preferable that the material has a function of suppressing diffusion (i.e., the oxygen is less likely to permeate). For example, Preferably, the rim 254 has a lower oxygen permeability than the insulator 280 or the insulator 224 .

[0229] The insulator 254 is preferably formed by sputtering. The insulating film of the insulator 224 is formed by depositing the insulating film by a sputtering method in an atmosphere containing oxygen. Oxygen can be added to the area adjacent to the body 254. This allows oxygen to be released from that area. Oxygen can be supplied to the oxide 230 through the insulator 224. 54 has the function of suppressing the upward diffusion of oxygen, so that oxygen is isolated from the oxide 230. The insulator 222 can prevent oxygen from diffusing downward to the insulator 280. By having the function of suppressing diffusion, it is possible to prevent oxygen from diffusing from the oxide 230 to the substrate side. In this way, oxygen is supplied to the channel forming region of the oxide 230. This reduces the oxygen vacancy in the oxide 230 and suppresses the normally-on state of the transistor. It can be controlled.

[0230] The insulator 254 may be, for example, an oxide of one or both of aluminum and hafnium. It is preferable to form a film of an insulator containing an oxide of aluminum or hafnium. Insulators containing both oxides include aluminum oxide, hafnium oxide, aluminum and It is preferable to use oxides containing hafnium (hafnium aluminate), etc. In this case, the insulator 254 is preferably deposited using an ALD method. Since this is a film formation method with good coating properties, the unevenness of the insulator 254 does not cause any step or other defects. This can be prevented.

[0231] In this manner, the insulator 254 having a barrier property against hydrogen prevents the insulator 224 and By covering the insulator 224 and the oxide 230, the insulator 280 is insulated from the insulator 224 and the oxide 230. This prevents impurities such as hydrogen from entering the transistor 200 from the outside. This can provide the transistor 200 with good electrical characteristics and reliability. It is possible.

[0232] The insulator 254 may be, for example, an insulator containing aluminum nitride. The insulator 254 is preferably made of AlNx (x is a real number greater than 0 and less than or equal to 2). It is preferable to use a nitride insulator that satisfies the following formula: This makes it possible to obtain a film with excellent insulation and thermal conductivity, This can improve the dissipation of heat generated when the transistor 200 is driven. Aluminum titanium nitride, titanium nitride, etc. can also be used as 254. In this case, the sputtering method is used for film formation, and the film formation gas contains oxidizing gas such as oxygen or ozone. This is preferable because it is possible to form the film without using a gas with high resistance. Silicon oxynitride or the like can also be used.

[0233] The insulator 254 may have a multi-layer structure of two or more layers. 4. The first layer is deposited using the sputtering method in an oxygen-containing atmosphere, and then the ALD method is The ALD method is a film formation method with good coating properties. Therefore, it is possible to prevent the formation of discontinuities due to the unevenness of the first layer. When the edge 254 has a multi-layer structure of two or more layers, the multi-layer structure may be made of different materials. For example, silicon oxide, silicon oxynitride, silicon nitride oxide or silicon nitride, A laminated structure with an insulator that functions to suppress the permeation of impurities such as hydrogen and oxygen. In addition, as an insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen, For example, an insulator containing oxides of one or both of aluminum and hafnium is used. It is possible.

[0234] The insulator 250 functions as a gate insulator. The insulator 250 is formed on the oxide 230c. The insulator 250 is preferably disposed in contact with the surface. , silicon oxynitride, silicon nitride, silicon oxide doped with fluorine, and oxide doped with carbon. silicon oxide, silicon oxide doped with carbon and nitrogen, silicon oxide with vacancies, etc. In particular, silicon oxide and silicon oxynitride are stable against heat. This is preferable.

[0235] The insulator 250 is made of an insulator that releases oxygen when heated, similar to the insulator 224. It is preferable to form the insulating material 250 as an insulating material from which oxygen is released by heating. By providing the oxide 230c on its upper surface, the region 234 of the oxide 230b is effectively In addition, like the insulator 224, the water in the insulator 250 can be supplied with oxygen. It is preferable that the concentration of impurities such as silicon is reduced. It is preferable that the upper limit is 20 nm or less.

[0236] The insulator 250 can be formed by sputtering, CVD, MBE, PLD, or other methods. This can be done by using an LD method or the like. In this embodiment, the insulator 250 is, for example, Alternatively, a silicon oxynitride film formed by a CVD method can be used.

[0237] A metal oxide may be provided between the insulator 250 and the conductor 260. The material preferably suppresses the diffusion of oxygen from the insulator 250 to the conductor 260. By providing a metal oxide that suppresses diffusion, the diffusion of oxygen from the insulator 250 to the conductor 260 is suppressed. In other words, the decrease in the amount of oxygen supplied to the oxide 230 can be suppressed. In addition, oxidation of the conductor 260 due to oxygen in the insulator 250 can be suppressed.

[0238] The metal oxide may function as a part of the gate insulator. Therefore, when silicon oxide or silicon oxynitride is used for the insulator 250, It is preferable to use a metal oxide, which is a high-k material with a high relative dielectric constant, as the oxide. By making the base insulator have a laminated structure of the insulator 250 and the above-mentioned metal oxide, the base insulator is stable against heat. Therefore, the physical properties of the gate insulator can be improved. It is possible to reduce the gate potential applied during transistor operation while maintaining the film thickness. In addition, it is possible to reduce the equivalent oxide thickness (EOT) of the insulator that functions as the gate insulator. do.

[0239] The metal oxide may also function as a part of the first gate. For example, The oxide semiconductor that can be used as the oxide 230 is used as the metal oxide. In this case, the conductor 260 is formed by a sputtering method, and the metal oxide This is called OC (Oxide Conductor). The electrode can be called an inductor.

[0240] By including the above metal oxide, the influence of the electric field from the conductor 260 is not weakened, and the It is possible to improve the on-current of the transistor 200. The physical thickness of the metal oxide maintains the distance between the conductor 260 and the oxide 230. This makes it possible to suppress leakage current between the conductor 260 and the oxide 230. By providing a laminated structure of the insulator 250 and the metal oxide, the conductor 260 and the oxide the physical distance between the conductor 260 and the oxide 230; and the electric field strength from the conductor 260 to the oxide 230. can be easily adjusted appropriately.

[0241] Specifically, hafnium, aluminum, gallium, yttrium, zirconium, tantalum, Selected from the group consisting of tinsten, titanium, tantalum, nickel, germanium, magnesium, etc. Metal oxides containing one or more of the above metals can be used. Aluminum oxide, which is an insulator containing oxides of either or both of aluminum and hafnium; Hafnium oxide, oxides containing aluminum and hafnium (hafnium aluminate In addition, an oxide semiconductor that can be used for the oxide 230 is preferably used. By lowering the resistance, it can be used as the metal oxide.

[0242] Although the conductor 260 is shown as having a two-layer structure in FIG. 11, it may have a single-layer structure or a three-layer structure. The above laminated structure may also be used.

[0243] The conductor 260a is a hydrogen atom, a hydrogen molecule, a water molecule, a nitrogen atom, a nitrogen molecule, or a nitrogen oxide molecule. (N2O, NO, NO2, etc.), conductive material with the function of suppressing the diffusion of impurities such as copper atoms It is preferable to use a material containing a small amount of oxygen (e.g., oxygen atoms, oxygen molecules, etc.). It is preferable to use a conductive material having a function of suppressing the diffusion of at least one of the above-mentioned elements.

[0244] In addition, the conductor 260a has a function of suppressing the diffusion of oxygen, so that the insulator 250 The oxygen contained therein can suppress the conductor 260b from being oxidized and the conductivity from decreasing. Examples of conductive materials that have the function of suppressing oxygen diffusion include tantalum, nitride, and the like. It is preferable to use tantalum chloride, ruthenium, ruthenium oxide, or the like.

[0245] In addition, since the conductor 260 also functions as wiring, a conductor with high conductivity should be used. For example, the conductor 260b is preferably made of tungsten, copper, or aluminum. The conductor 260b may have a laminated structure. For example, a laminated structure of titanium, titanium nitride and the above-mentioned conductive material may be used.

[0246] The conductor 260 can be formed by sputtering, CVD, MBE, PLD, or other methods. This can be done by using an LD method or the like. In this embodiment, the conductor 260a is, for example, For example, titanium nitride film formed by CVD is used, and the conductor 260b is, for example, C Titanium nitride formed by the VD method can be used.

[0247] The insulator 280 is formed by connecting the insulator 222, the insulator 224, the oxide 230, and the insulator 254. , and on the conductor 242. For example, the insulator 280 may be silicon oxide, oxide Silicon nitride, silicon oxide nitride, silicon oxide with fluorine, and oxide with carbon silicon oxide, silicon oxide doped with carbon and nitrogen, silicon oxide with vacancies, etc. In particular, silicon oxide and silicon oxynitride are thermally stable. In particular, silicon oxide, silicon oxynitride, silicon oxide having vacancies, etc. These materials are preferred because they can easily form regions containing oxygen that is desorbed by heating. It is.

[0248] It is preferable that the concentration of impurities such as water and hydrogen in the insulator 280 is reduced. The top surface of the insulator 280 may be planarized.

[0249] The insulator 280 can be formed by sputtering, CVD, MBE, PLD, or other methods. This can be done by using an LD method or the like. In this embodiment, the insulator 280 is, for example, Alternatively, a silicon oxynitride film formed by a CVD method can be used.

[0250] The insulator 274, like the insulator 214, is designed to insulate impurities such as water and hydrogen from above. It is preferable that the insulator 2 functions as a barrier insulating film that suppresses diffusion of the insulator 2 into the insulator 280. As the insulating material 74, for example, an insulating material that can be used for the insulating material 214, the insulating material 254, etc. is used. That's good.

[0251] The insulator 274 can be formed by sputtering, CVD, MBE, PLD, or the like. This can be done by using an LD method or the like. In this embodiment, the insulator 274 is, for example, Alternatively, an aluminum oxide film formed by a sputtering method can be used.

[0252] In addition, it is preferable to provide an insulator 281 that functions as an interlayer film on the insulator 274. The insulator 281, like the insulator 224, has a low concentration of impurities such as water and hydrogen in the film. It is preferable that the amount of the ion exchange rate is reduced.

[0253] The insulator 281 can be formed by sputtering, CVD, MBE, PLD, or A. This can be done by using an LD method or the like. In this embodiment, the insulator 281 is, for example, Alternatively, a silicon nitride film formed by a CVD method can be used.

[0254] Also, the insulating material 281, the insulating material 274, the insulating material 280, and the insulating material 254 are formed The conductor 240a and the conductor 240b are disposed in the opening. The conductor 240a and the conductor 240b are disposed opposite each other with the conductor 260 in between. The height of the upper surface of 240b may be flush with the upper surface of the insulator 281.

[0255] In addition, the side walls of the openings of the insulators 281, 274, 280, and 254 An insulator 241a is provided in contact with the first conductor of the conductor 240a. A conductor 242a is located at least partially on the bottom of the opening. conductor 240a contacts conductor 242a. Similarly, insulator 281, insulator 274, An insulator 241b is provided in contact with the edge 280 and the side wall of the opening of the insulator 254. A first conductor of the conductor 240b is formed in contact with the side surface of the opening. At least a part of the conductor 240b is located in the conductor 242b. do.

[0256] The conductors 240a and 240b are mainly made of tungsten, copper, or aluminum. It is preferable to use a conductive material having the above-mentioned components. 0b may have a laminated structure.

[0257] In addition, when the conductor 240 has a laminated structure, the oxide 230a, the oxide 230b, the conductor 242, insulator 254, insulator 280, insulator 274, and conductive member in contact with insulator 281 The body can be made of conductive materials that have the function of suppressing the permeation of impurities such as water and hydrogen. For example, tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, ruthenium oxide, etc. It is preferable to use ruthenium or the like. In addition, it is preferable to use a material that has a function of suppressing the permeation of impurities such as water and hydrogen. The conductive material having the function may be used in a single layer or a multilayer structure. The oxygen added to the insulator 280 is absorbed by the conductors 240a and 240b. In addition, impurities such as water and hydrogen contained in the layer above the insulator 281 can be prevented. from diffusing into the oxide 230 through the conductor 240a and the conductor 240b. It is possible.

[0258] The insulators 241a and 241b may be used, for example, as the insulator 254. The insulator 241a and the insulator 241b are made of an insulator 254. Since the insulator 280 is provided in contact with the conductor 270, impurities such as water and hydrogen contained in the insulator 280 can be easily absorbed by the conductor 270. 240a and the conductor 240b, the diffusion of the oxide 230 can be suppressed. In addition, oxygen contained in the insulator 280 is absorbed into the conductor 240a and the conductor 240b. In addition, the insulators 241a and 241b are formed by using a method such as the steps of: The LD method or the CVD method can be used.

[0259] Although not shown, a conductive material 240a and a conductive material 240b are disposed in contact with each other on the upper surface thereof. A conductor functioning as a line may be disposed. The conductor functioning as a wiring may be tungsten. It is preferable to use a conductive material containing copper or aluminum as a main component. The conductor may be a laminated structure, for example, a layer of titanium, titanium nitride, and the above-mentioned conductive material. The conductor may be formed so as to be embedded in an opening provided in an insulator. You may do so.

[0260] In addition, although not shown, a thin film having a resistivity of 1.0×10 13 Ωcm or more 1.0×10 15 Ωcm or less, preferably 5.0×10 13 Ωcm or more 5.0×10 14 It is preferable to provide an insulator having a resistivity of Ωcm or less on the conductor. By providing an insulator, the insulator can maintain insulation and The charge accumulated between the wiring of the conductor is dispersed, and the transistor or the transistor This is preferable because it can suppress characteristic defects and electrostatic damage in electronic devices having a transistor.

[0261] As described above, according to one embodiment of the present invention, a semiconductor device with large on-state current can be provided. According to one embodiment of the present invention, a semiconductor device having high frequency characteristics can be provided. According to one embodiment of the present invention, a highly reliable semiconductor device can be provided. According to one embodiment of the present invention, a semiconductor device that can be miniaturized or highly integrated can be provided. According to one embodiment of the present invention, a semiconductor device having favorable electrical characteristics can be provided. According to one embodiment of the present invention, a semiconductor device with low off-state current can be provided. According to one embodiment of the present invention, a semiconductor device with reduced power consumption can be provided. According to one embodiment of the present invention, a semiconductor device with high productivity can be provided. It is possible.

[0262] <Materials for semiconductor devices> The following describes constituent materials that can be used in the semiconductor device.

[0263] The following materials are deposited by sputtering, CVD, MBE, PLD, and A. This can be done using the LD method or the like.

[0264] The CVD method is a process that uses plasma (PECVD). Enhanced CVD method, Thermal CVD (TCVD) These methods are further classified into the VD method, which uses light, and the Photo CVD method, which uses light. Depending on the source gas, metal CVD (MCVD: Metal CVD) method, metal organic CVD method (MOCVD: Metal Organic CVD) method.

[0265] The plasma CVD method can produce high-quality films at relatively low temperatures. This is a film formation method that can suppress plasma damage to the workpiece because it does not use a plasma. For example, wiring, electrodes, elements (transistors, capacitors, etc.) included in a semiconductor device etc. may become charged up by receiving an electric charge from the plasma. Accumulated electric charges can destroy wiring, electrodes, elements, etc., contained in semiconductor devices. On the other hand, in the case of thermal CVD, which does not use plasma, such plasma damage does not occur. Therefore, the yield of the semiconductor device can be increased. Since no plasma damage occurs during deposition, a film with few defects can be obtained.

[0266] The ALD method is also a film formation method that can suppress plasma damage to the workpiece. Therefore, a film with few defects can be obtained. For this reason, films formed by ALD are not as good as those formed by other film formation methods. In some cases, the impurity content of the film may be higher than that of the film formed by the method described above. The quantitative analysis was carried out by X-ray photoelectron spectroscopy (XPS). This can be done using ectroscopy.

[0267] The CVD and ALD methods are deposition methods in which particles emitted from a target are deposited. It is a film forming method in which a film is formed by a reaction on the surface of the object to be treated. Therefore, this is a film forming method that is not easily affected by the shape of the workpiece and has good step coverage. In addition, the ALD method has excellent step coverage and thickness uniformity, making it ideal for achieving high aspect ratios. However, the ALD method is relatively slow in forming a film. Because the deposition rate is slow, it should be used in combination with other deposition methods such as CVD, which has a faster deposition rate. may be preferred.

[0268] In the CVD and ALD methods, the composition of the resulting film is controlled by the flow rate ratio of the source gases. For example, in the CVD and ALD methods, the flow rate ratio of the source gases can be adjusted to any value. In addition, for example, in the CVD method and the ALD method, the film formation By changing the flow rate ratio of the source gas while heating, a film with a continuously changing composition can be formed. When forming a film while changing the flow rate ratio of the source gas, multiple film forming chambers can be used. Compared to forming a film using a vacuum, the time required for film formation is shorter because there is no time required for transportation or pressure adjustment. Therefore, the productivity of the semiconductor device can be improved. There is.

[0269] The processing of the constituent material may be performed using a lithography method. Dry etching and wet etching can be used. Processing by this method is suitable for fine processing.

[0270] In the lithography method, first, the resist is exposed through a mask. The regions are removed or left using a developer to form a resist mask. By etching through a resist mask, conductors, semiconductors, insulators, etc. can be obtained as desired. For example, KrF excimer laser light, ArF excimer laser light, The resist is removed using ultraviolet (EUV) light, X-rays, and other light sources. A resist mask can be formed by exposing the substrate to light. A liquid immersion technique may be used in which the substrate is exposed to light by filling the substrate with liquid (e.g., water). Alternatively, an electron beam or an ion beam may be used. In this case, since the pattern is drawn directly on the resist, the above-mentioned mask for resist exposure is not required. The resist mask is then subjected to a dry etching process such as ashing, or a wet etching process. Etching is performed, wet etching is performed after dry etching, or can be removed by wet etching followed by dry etching, etc. Cut.

[0271] Moreover, instead of the resist mask, a hard mask made of an insulator or a conductor may be used. When a hard mask is used, an insulating film or a conductive film that is a hard mask material is formed on the constituent material. A resist mask is then formed thereon, and the hard mask material is etched. A hard mask of the desired shape can be formed. The etching of the component material is performed in a resist pattern. This may be performed after removing the resist mask, or may be performed while leaving the resist mask. In the latter case, the resist mask may disappear during etching. After the etching, the hard mask may be removed by etching. If there is no effect on the post-process or if it can be used in the post-process, the hard mask does not necessarily need to be removed. There's no need to.

[0272] The dry etching equipment is a capacitively coupled plasma (CCP) device with parallel plate electrodes. : Capacitively Coupled Plasma (CAP) etching equipment is used. The capacitively coupled plasma etching apparatus having parallel plate electrodes can Alternatively, a high frequency power source may be applied to one of the parallel plate type electrodes. A configuration in which a plurality of different high frequency power sources are applied to the electrodes may be used. Alternatively, a parallel plate electrode may be used. Alternatively, a high-density plasma source may be provided. A dry etching apparatus having a high density plasma source can be used. The plasma processing device is, for example, an inductively coupled plasma (ICP) type. A plasma etching apparatus or the like can be used.

[0273] <<Substrate>> The substrate on which the transistor 200 is formed may be, for example, an insulating substrate, a semiconductor substrate, or A conductive substrate may be used. Examples of insulating substrates include glass substrates, quartz substrates, and silicon substrates. Fire substrate, stabilized zirconia substrate (yttria stabilized zirconia substrate, etc.), resin substrate The semiconductor substrate may be, for example, a semiconductor such as silicon or germanium. Solid substrate, or silicon carbide, silicon germanium, gallium arsenide, indium phosphide Compound semiconductor substrates made of zinc oxide, gallium oxide, etc. A semiconductor substrate having an insulating region inside the substrate, such as SOI (Silicon On Insulator) Conductive substrates include graphite substrates, metal substrates, and alloy substrates. Substrates with metal nitrides, conductive resin substrates, etc. Further, there are substrates in which a conductor or a semiconductor is provided on an insulating substrate, A substrate in which a conductor or an insulator is provided on a semiconductor substrate, a substrate in which a semiconductor or an insulator is provided on a conductor substrate Alternatively, a substrate having an element provided thereon may be used. The elements provided on the substrate include a capacitance element, a resistance element, a switch element, a light-emitting element, a recording element, and a Memory elements, etc.

[0274] <<Insulators>> Insulators include oxides, nitrides, oxynitrides, nitride oxides, and metal oxides that have insulating properties. These include metal oxide nitrides, metal oxynitrides, and metal oxynitrides.

[0275] For example, as transistors become smaller and more highly integrated, the gate insulator becomes thinner. This can cause problems such as leakage current. By using high-k materials, the voltage required for transistor operation can be reduced while maintaining the same physical thickness. On the other hand, it is possible to use a material with a low relative dielectric constant for the insulator that functions as the interlayer film. This reduces the parasitic capacitance between the wirings. The material should be selected accordingly.

[0276] Insulators with high relative dielectric constants include gallium oxide, hafnium oxide, and zirconium oxide. Oxides containing aluminum, aluminum and hafnium, and oxides containing aluminum and hafnium oxide nitride having silicon and hafnium, oxide having silicon and hafnium Examples of suitable materials include oxynitrides with hafnium, or nitrides with silicon and hafnium.

[0277] Insulators with low dielectric constants include silicon oxide, silicon oxynitride, and silicon nitride oxide. Silicon, silicon nitride, silicon oxide with fluorine, silicon oxide with carbon, Silicon oxide doped with carbon and nitrogen, silicon oxide with voids, or resin, etc. be.

[0278] In addition, a transistor using an oxide semiconductor can suppress the permeation of impurities such as hydrogen and oxygen. Insulators having a function of controlling the temperature (insulator 214, insulator 222, insulator 254, and insulator By surrounding the transistor with a metal (such as 274), the electrical characteristics of the transistor can be stabilized. Examples of insulators that have the function of suppressing the permeation of impurities such as hydrogen and oxygen include HO. Uranium, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine , argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium Insulators including titanium, hafnium, or tantalum may be used in single or multilayer configurations. Specifically, the following insulators have the function of suppressing the permeation of impurities such as hydrogen and oxygen: Aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide tungsten oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or thorium oxide Metal oxides such as tantalum, aluminum nitride, aluminum titanium nitride, titanium nitride, and nitrogen Metal nitrides such as silicon oxide or silicon nitride can be used.

[0279] In addition, the insulator that functions as the gate insulator has a region that contains oxygen that is desorbed by heating. For example, it is preferable that the insulating material has a region containing oxygen that is desorbed by heating. By forming a structure in which silicon oxide or silicon oxynitride is in contact with the oxide 230, The oxygen deficiency of 230 can be compensated for.

[0280] <<Conductors>> Conductive materials include aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, and titanium. Tantalum, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium Sium, zirconium, beryllium, indium, ruthenium, iridium, strontium Metal elements selected from aluminum, lanthanum, etc., or alloys containing the above-mentioned metal elements It is preferable to use an alloy or the like that combines the above-mentioned metal elements. For example, tantalum nitride titanium nitride, tungsten, nitrides containing titanium and aluminum, tantalum and aluminum Ruthenium nitrides, ruthenium oxide, ruthenium nitride, strontium and ruthenium It is preferable to use an oxide containing lanthanum and nickel. Tantalum, titanium nitride, nitrides containing titanium and aluminum, tantalum and aluminum Ruthenium nitride, ruthenium oxide, ruthenium nitride, oxide containing strontium and ruthenium Oxides containing lanthanum and nickel are conductive materials that are difficult to oxidize or absorb oxygen. It is preferable because it is a material that maintains its conductivity even if it is oxidized. In addition, it does not contain impurity elements such as phosphorus. Highly conductive semiconductors, such as polycrystalline silicon, nickel silicide, etc. Silicide may also be used.

[0281] In addition, a plurality of conductive layers made of the above materials may be laminated. A laminated structure in which a material containing a metal element and a conductive material containing oxygen are combined may be used. In addition, a laminated material that combines the above-mentioned material containing a metal element and a conductive material containing nitrogen is In addition, the above-mentioned metal element-containing material, the conductive material containing oxygen, and the nitrogen A laminated structure in which the conductive material containing the element is combined with the conductive material containing the element may be used.

[0282] In the case where an oxide is used for the channel formation region of a transistor, The conductor that functions as a conductive material is a material containing the above-mentioned metal element and a conductive material containing oxygen. In this case, it is preferable to use a laminate structure in which an oxygen-containing conductive material is used as the It is preferable to provide the conductive material containing oxygen on the channel forming region side. This makes it easier for oxygen released from the conductive material to be supplied to the channel formation region.

[0283] In particular, the metal oxide in which the channel is formed is a conductor that functions as a gate electrode. It is preferable to use a conductive material containing oxygen and a metal element contained in the metal. Conductive materials containing metal elements and nitrogen may also be used, such as titanium nitride and tantalum nitride. In addition, a conductive material containing nitrogen such as indium tin oxide or tungsten oxide may be used. Indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, titanium oxide Indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide Indium tin oxide containing nitrogen may also be used. Mugallium zinc oxide may be used. By using such a material, the channel is formed In some cases, hydrogen can be captured from the metal oxide that is insulated from the outer In some cases, it may be possible to capture hydrogen that is mixed in from the surroundings, etc.

[0284] <<Metal oxides>> As the oxide 230, it is preferable to use a metal oxide that functions as an oxide semiconductor. Metal oxides applicable to the oxide 230 according to the present invention will be described below.

[0285] The metal oxide preferably contains at least indium or zinc. In addition to these, aluminum, gallium, and zinc are preferably included. It is preferable that the alloy contains boron, titanium, iron, or the like. , nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium , hafnium, tantalum, tungsten, magnesium, or Or multiple types may be included.

[0286] Here, the metal oxide is an In-M-Zn oxide having indium, element M and zinc. The element M can be aluminum, gallium, yttrium, or The element M can be tin, etc. Other elements that can be used for M include boron, titanium, iron, and nickel. Nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, halide Examples include fluorine, tantalum, tungsten, and magnesium. However, the element M is: In some cases, combinations of the aforementioned elements may be used.

[0287] In this specification, metal oxides containing nitrogen are also referred to as metal oxides. Metal oxides containing nitrogen are also called metal oxynitrides (MEs). It may also be called tal oxynitride.

[0288] [Metal oxide structures] Oxide semiconductors (metal oxides) are classified into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. As non-single crystal oxide semiconductors, for example, CAAC-OS, polycrystalline These include crystalline oxide semiconductors, nc-OS, a-like OS, and amorphous oxide semiconductors. do.

[0289] CAAC-OS has a c-axis orientation and multiple nanocrystals are connected in the ab-plane direction. The nanocrystals are connected together to form a distorted crystal structure. In a region, a lattice arrangement is formed between a region having a uniform lattice arrangement and another region having a uniform lattice arrangement. This refers to the point where the direction of the

[0290] Nanocrystals are basically hexagonal, but are not limited to regular hexagons and may have non-regular hexagonal shapes. In addition, the distortion may have lattice arrangements such as pentagons and heptagons. In addition, in the CAAC-OS, clear grain boundaries (grain bows) were observed even in the vicinity of the strain. It is difficult to confirm the presence of the lattice distortion. This is because the CAAC-OS has ab-plane orientation. In the case of the SiO2, the arrangement of oxygen atoms is not dense, and the bond distance between atoms is reduced by the substitution of metal elements. This is because distortion can be tolerated due to changes in the distance, etc.

[0291] CAAC-OS is a highly crystalline metal oxide. Since it is difficult to confirm the grain boundaries, the decrease in electron mobility caused by the grain boundaries is unlikely to occur. In addition, the crystallinity of metal oxides is reduced by the incorporation of impurities and the generation of defects. Therefore, CAAC-OS is designed to prevent impurities and defects (oxygen vacancies (V O :oxygen v It can also be said to be a metal oxide with low acancy. Metal oxides with CAAC-OS have stable physical properties. The metal oxides used are heat resistant and highly reliable.

[0292] FIG. 13(A) shows a C A high-resolution TEM image of the cross section of AAC-OS is shown. Using the Spherical Aberration Corrector function High-resolution TEM images using spherical aberration correction are specifically called Cs-corrected high-resolution TEM images. The Cs-corrected high-resolution TEM image was obtained using, for example, an atomic resolution analytical electron microscope manufactured by JEOL Ltd. It can be observed using instruments such as the JEM-ARM200F.

[0293] From FIG. 13(A), nanocrystals, which are regions in which metal atoms are arranged in layers, can be confirmed. The size of a single nanocrystal can be 1 nm or more, or 3 nm or more. The nanocrystals reflect the unevenness of the surface on which the CAAC-OS is formed or the top surface. It is parallel to the surface on which the AC-OS is formed or the top surface.

[0294] In addition, Fig. 13(B) and Fig. 13(C) show CA observed from a direction roughly perpendicular to the sample surface. Cs-corrected high-resolution TEM images of the AC-OS in plan view are shown in Fig. 13(D) and Fig. 13(E). are the images obtained by processing the images in Fig. 13(B) and Fig. 13(C), respectively. The processing method will be described. First, the image in FIG. 13B is subjected to a fast Fourier transform (FFT). Then, the FFT image is obtained by performing Fourier Transform (FT-FFT) processing. 2.8 nm based on the origin in the acquired FFT image -1 From 5.0 nm -1 Range between Next, the masked FFT image is subjected to an inverse fast Fourier transform (IFF By using Inverse Fast Fourier Transform (T) processing, The image obtained is called an FFT filtered image. The T-filtered image is an image in which periodic components are extracted from a Cs-corrected high-resolution TEM image. 1 shows a lattice arrangement.

[0295] In FIG. 13(D), the area where the lattice arrangement is disturbed is indicated by a dashed line. The dotted lines indicate the connections between the nanocrystals. The dashed lines indicate a hexagonal shape, which indicates that the nanocrystals are hexagonal. In contrast, when CAAC-OS is observed by TEM from the c-axis direction, hexagonal lattice points are observed. Therefore, the CAAC-OS is a layered crystal shown in FIG. The shape of the nanocrystal is not limited to a regular hexagon, but may be a non-hexagon. It may also be a regular hexagon.

[0296] In FIG. 13(E), a grid is formed between an area with a uniform lattice arrangement and an area with a different uniform lattice arrangement. The dotted lines indicate the changes in the orientation of the child array, and the dashed lines indicate the changes in the orientation of the lattice array. Even in the vicinity of the dotted line, no clear crystal grain boundaries can be confirmed. By connecting the surrounding lattice points around the center, a distorted hexagon, pentagon, or heptagon can be formed. In other words, it is clear that the formation of grain boundaries is suppressed by distorting the lattice arrangement. This is because the arrangement of oxygen atoms in CAAC-OS is not dense in the ab-plane direction and The substitution of metal elements changes the bond distance between atoms, allowing for distortion. This is thought to be because

[0297] In addition, Fig. 14(A) shows a high-resolution TEM image of a cross section of CAAC-OS, which is different from that in Fig. 13. FIG. 14(B) is a high-resolution TEM image of a cross section of FIG. 14(A) that is further enlarged. The atomic arrangement is highlighted for ease of understanding.

[0298] FIG. 14(C) shows the area surrounded by a circle (diameter approximately 4 mm) between AO-A' in FIG. 14(A). From Fig. 14(C), it is clear that the c-axis orientation is In addition, the c-axis orientation is different between the A-O and O-A' sections, so the different graphs are formed. The c-axis angles between the AOs are 14.3° and 16. 6°, 26.4°, and so on. Similarly, OA Between these, the c-axis angle gradually changes to -18.3°, -17.6°, and -15.9°. It is clear that things are changing.

[0299] High-resolution TEM images of the cross section and the plan view show that the nanocrystals of CAAC-OS It is clear that the crystals have an orientation.

[0300] From the above, it is considered that the CAAC-OS has a c-axis orientation as shown in the above embodiment. The c-axis is the normal vector of the CAAC-OS surface or the CAAC-OS film surface. It can be seen that the crystals are parallel to each other. Each layer of metal atoms arranged in a layered fashion is parallel to the ab plane of the nanocrystal.

[0301] nc-OS is a material that is used in microscopic regions (e.g., regions between 1 nm and 10 nm, especially regions between 1 nm and The atomic arrangement has periodicity in the region of 3 nm or less. There is no regularity in the crystal orientation between the crystals. Therefore, no orientation is observed throughout the film. Therefore, depending on the analysis method, nc-OS may be classified as a-like OS or amorphous oxide semiconductor. Sometimes it is indistinguishable from the body.

[0302] In addition, indium oxide, which is a type of metal oxide containing indium, gallium, and zinc, In the case of IGZO, the nanocrystals mentioned above make it stable. In particular, IGZO tends to have difficulty growing crystals in air. , small crystals (e.g., For example, the nanocrystals mentioned above may be structurally more stable.

[0303] The a-like OS is a metal oxide semiconductor that has a structure between the nc-OS and the amorphous oxide semiconductor. The a-like OS has voids or low density regions. The ke-OS has a lower crystallinity than the nc-OS and CAAC-OS.

[0304] Oxide semiconductors (metal oxides) have a variety of structures, each with different properties. The oxide semiconductor of one embodiment of the present invention can be an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, an a-li The ke-OS, nc-OS, and CAAC-OS may have two or more kinds.

[0305] [impurities] Here, the influence of each impurity in the metal oxide will be described.

[0306] When an alkali metal or alkaline earth metal is contained in a metal oxide, a defect level is formed, and Therefore, alkali metals or alkaline earth metals may be used. A transistor using the metal oxide for the channel formation region has normally-on characteristics. This makes it easier to reduce the concentration of alkali metals or alkaline earth metals in the metal oxide. Specifically, it is preferable to use a secondary ion mass spectrometry (SIMS) method. Al in metal oxides obtained by y-Ion Mass Spectrometry The concentration of potassium metal or alkaline earth metal (obtained by SIMS) is 1×10 1 8 atoms / cm 3 Less than or equal to 2 x 10 16 atoms / cm 3 To the following:

[0307] In addition, hydrogen contained in metal oxides reacts with oxygen that bonds with metal atoms to form water. When hydrogen enters the oxygen vacancy, the carrier In some cases, hydrogen atoms are formed by bonding with oxygen atoms that bond with metal atoms. Therefore, it is recommended to use metal oxides that contain hydrogen. Such a transistor is likely to have normally-on characteristics.

[0308] For this reason, it is preferable that the amount of hydrogen in the metal oxide is reduced as much as possible. is the hydrogen concentration obtained by SIMS in metal oxides, expressed as 1×10 20 atoms / cm 3 Less than 1 x 10 19 atoms / cm 3 Less than 5×1 0 18 atoms / cm 3 less than 1×10 18 atoms / cm 3 less than A metal oxide with sufficiently reduced impurities is used for the channel formation region of a transistor. By doing so, it is possible to impart stable electrical characteristics.

[0309] <Configuration Example 2 of Semiconductor Device> FIG. 15 illustrates a transistor 200A according to one embodiment of the present invention and a transistor 200A 5A and 5B are top and cross-sectional views of the periphery.

[0310] FIG. 15A is a top view of a semiconductor device including a transistor 200A. 15(B) and 15(C) are cross-sectional views of the semiconductor device. FIG. 15A is a cross-sectional view of a portion indicated by a dashed line A1-A2 in FIG. FIG. 15(C) is a cross-sectional view of the A3-A channel in the channel length direction. 4 is a cross-sectional view of a portion indicated by a dashed line in FIG. 4A, and is a cross-sectional view in the channel width direction of a transistor 200A. In addition, in the top view of FIG. 15(A), some elements are omitted for clarity. is.

[0311] In the semiconductor device shown in FIG. 15, the semiconductor device shown in <Configuration Example 1 of the Semiconductor Device> The structures having the same functions as those constituting the device are denoted by the same reference numerals.

[0312] The configuration of the semiconductor device will be described below with reference to FIG. The materials used for the semiconductor device are explained in detail in the "Semiconductor Device Configuration Example 1". It is possible.

[0313] [Transistor 200A] As shown in FIG. 15, a transistor 200A is disposed on a substrate (not shown). An insulator 216, a conductor 205 disposed so as to be embedded in the insulator 216, and an insulator An insulator 222 is disposed on the conductor 216 and on the conductor 205, and a An insulator 224 is placed on the insulating layer 222 and an oxide 230 (oxide 230a) is placed on the insulating layer 222. , oxide 230b, oxide 230c1, and oxide 230c2), and the top of oxide 230 250 disposed on the insulator 250, and a conductor 260 (conductor 260a, and conductor 260b), and conductor 242a and conductor 260b in contact with a portion of the top surface of oxide 230b. A barrier film 244a disposed on the conductor 242a and a conductor 242b. A barrier film 244b disposed on the insulator 222 and a side surface of the insulator 224 , the side of the oxide 230a, the side of the oxide 230b, the side of the conductor 242a, the barrier film 24 4a, the side of the conductor 242b, and the upper surface of the barrier film 244b. and an insulator 254 (insulator 254a and insulator 254b).

[0314] The insulator 254 is configured by laminating two layers of an insulator 254a and an insulator 254b. , and the oxide 230c is formed by stacking two layers of oxide 230c1 and oxide 230c2. The transistor 200 differs from the transistor 200 described above in that it has a structure similar to that of the transistor 200 described above. The different points will be explained.

[0315] As shown in FIG. 15, the insulator 254 is made up of an insulator 254a and a For example, the insulator 254a is a material that is resistant to impurities such as water and hydrogen. However, the insulator 280 functions as a barrier film to prevent the diffusion of the insulator 280 into the transistor 200A. In addition, for example, the insulator 254b is formed by insulating the oxygen in the oxide 230. It is preferable to suppress the diffusion of the fluorine-containing gas toward the side of the insulating layer 280. This can prevent hydrogen from being mixed into the channel formation region of the oxide 230. In addition, it is possible to prevent oxygen from being released from the channel formation region of the oxide 230. The insulator 254a is made of silicon nitride formed by sputtering. The insulator 254b may be an aluminum oxide film formed by ALD.

[0316] For example, the insulator 254a may be an insulating material having an excess oxygen region or An insulating material that is prone to forming an excess oxygen region is used as the insulator 254b. It is preferable to use an insulating material that easily forms an oxygen region. The insulator 254a is a silicon oxide film formed by a sputtering method, and the insulator 254b is a In this case, an aluminum oxide film formed by sputtering may be used. By laminating two layers, the excess oxygen in the insulator 254a is converted into the oxide 230. can be efficiently supplied to

[0317] In addition, when the insulator 254a contains excess oxygen, a barrier layer is formed on the upper surface of the conductor 242a. A film 244a is provided on the upper surface of the conductor 242b, and a barrier film 244b is provided in contact with the upper surface of the conductor 242b. The barrier film 244a and the barrier film 244b are preferably formed to prevent impurities such as water and hydrogen, and The oxide 230c and the insulator 250 have a function of suppressing the permeation of oxygen. Prevent excess oxygen in the conductive material from diffusing into the conductive material 242a and the conductive material 242b. In other words, the excess oxygen in the surroundings is used to oxidize the conductors 242a and 242b. In addition, the conductors 242a and 242b can be prevented from being oxidized. This prevents the electrical resistance of the conductor 242a and the conductor 242b from increasing. The electrical resistance of a conductor can be measured using the two-terminal method, etc. Cut.

[0318] The barrier film 244a and the barrier film 244b may be made of, for example, aluminum oxide, oxide, or the like. Magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide Metal oxides such as tantalum oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide; Silicon oxide, silicon nitride, or the like may be used.

[0319] In addition, the barrier film 244a and the barrier film 244b are made of a conductive material that is difficult for impurities to penetrate. A conductive material may be used for the barrier film 244a and the barrier film 244b. In this case, it is preferable to use a conductive material that is less likely to release or absorb oxygen. It is to be noted that the barrier film 244a and the barrier film 244b may not be provided.

[0320] The insulator 254 is not limited to a laminate of the insulators 254a and 254b. Alternatively, the insulators 254a, 254b, and 254c may be formed as a single layer. A three-layer laminate may be used. When a three-layer laminate is used, for example, the insulator 25 4a: Insulating material that has the function of suppressing the diffusion of impurities such as water and hydrogen, and oxygen As the insulator 254b, an insulating material having an excess oxygen region is used, and as the insulator 25 As 4c, it is preferable to use an insulating material having a function of suppressing the diffusion of oxygen. By stacking three layers, the excess oxygen in the insulator 254b is absorbed into the insulator 254a. In addition, the diffusion of the insulating material 254c to the outside can be suppressed. The excess oxygen contained in the body 254b can be efficiently supplied to the oxide 230.

[0321] In addition, when the insulator 254 is configured to have two or more layers, the insulating material used for the insulator 254 The combination of materials and the order of layers can be appropriately designed according to the desired transistor characteristics. stomach.

[0322] As shown in FIG. 15, the oxide 230c is made up of an oxide 230c1 and an oxide 230c2. and an oxide 230c2 disposed on the oxide 230c1. It is preferable that b contains at least one of the metal elements constituting the metal oxide, It is more preferable that all of the metal elements are contained. The defect level density at the interface with the oxide 230c2 can be reduced. The oxide 230c1 is preferably a metal oxide that suppresses the diffusion or permeation of oxygen. By providing the oxide 230c2 between the insulator 250 and the oxide 230c1, It is possible to suppress the oxygen contained in the insulator 280 from diffusing into the insulator 250. Therefore, the oxygen is easily supplied to the oxide 230 via the oxide 230c1.

[0323] In addition, the oxide 230c1 and the oxide 230c2 are preferably crystalline. More preferably, the oxide 230c2 has higher crystallinity than the oxide 230c1. It is preferable to use CAAC-OS as the oxide 230c1 and the oxide 230c2. Preferably, the c-axes of the crystals of the oxide 230c1 and the oxide 230c2 are the same as those of the oxide 230c1 and the oxide 230c2. 0c1 and the oxide 230c2 are oriented in a direction substantially perpendicular to the surface on which the oxide 230c2 is formed or the upper surface. It is preferable that the CAAC-OS has a property of making it difficult for oxygen to move in the c-axis direction. Therefore, by providing the oxide 230c2 between the oxide 230c1 and the insulator 250, The oxygen contained in the oxide 230c1 is prevented from diffusing into the insulator 250, and the oxygen is The oxide 230 can be efficiently supplied with the oxygen.

[0324] Specifically, the oxide 230c1 is In:Ga:Zn=4:2:3 [atomic ratio] A metal oxide was used, and the oxide 230c2 was In:Ga:Zn=1:3:4 [atomic ratio In the metal oxide used for the oxide 230c2, The atomic ratio of In in the metal oxide used for oxide 230c1 is By making the atomic ratio smaller than that of In, the diffusion of In into the insulator 250 is suppressed. Since the insulator 250 functions as a gate insulator, In is insulator 250. If the oxide 230c is mixed in the semiconductor device, the transistor characteristics will be deteriorated. By adopting this structure, it is possible to provide a highly reliable semiconductor device.

[0325] The insulator 280 may also be configured to have a two-layer laminate structure. Thus, the insulator 280 is made up of an insulator 280a and an insulator 280b disposed on the insulator 280a. 80b, the insulator 280a preferably has an excess oxygen region. The insulator 280a is physically closer to the channel forming region of the oxide 230 than the insulator 280b. Because the distance is short, the oxygen contained in the insulator 280 can be effectively transferred to the channel forming region of the oxide 230. It can be supplied efficiently.

[0326] Specifically, the insulator 280a is a silicon oxide film formed by sputtering. and silicon oxynitride formed by CVD is used as the insulator 280b. Note that the transistor 200A has a structure in which the insulator 280 is stacked. However, the present invention is not limited to this. For example, the insulator 280 may be a single layer or a three layer The above-mentioned laminated structure may be used.

[0327] As shown in FIG. 15, an insulator 282 is provided between the insulator 274 and the insulator 281. The insulator 282 has a function of suppressing the diffusion of impurities such as hydrogen and oxygen. For example, it is preferable to use an insulating film having a function of forming the insulating film by using a sputtering method or an ALD method. It is preferable to form a film of silicon nitride, aluminum oxide, or the like. By this, oxygen contained in the insulator 280, the insulator 250, etc. is diffused to the insulator 281 side. This can prevent the above from happening.

[0328] <Configuration Example 3 of Semiconductor Device> FIG. 16 illustrates a transistor 200B according to one embodiment of the present invention and a transistor 200B 5A and 5B are top and cross-sectional views of the periphery.

[0329] FIG. 16A is a top view of a semiconductor device including a transistor 200B. 16(B) to 16(D) are cross-sectional views of the semiconductor device. 16A is a cross-sectional view of a portion indicated by a dashed line A1-A2 in FIG. FIG. 16(C) is a cross-sectional view of the channel length direction of B. FIG. 16(C) is a cross-sectional view of the channel length direction of B in FIG. 4 is a cross-sectional view of a portion indicated by a dashed line in FIG. 4, and is a cross-section in the channel width direction of a transistor 200B. FIG. 16(D) is a diagram of the portion indicated by the dashed line A5-A6 in FIG. 16(A). FIG. 2 is a cross-sectional view of the vicinity of a region 243b that functions as a low-resistance region of a transistor 200B. In the top view of FIG. 16(A), some elements are omitted for clarity. is.

[0330] In the semiconductor device shown in FIG. 16, <Configuration Example 1 of the Semiconductor Device> or <Semiconductor Device The structures constituting the semiconductor device shown in the example 2 of the semiconductor device are designated by the same reference numerals. It is added.

[0331] The configuration of the semiconductor device will be described below with reference to FIG. For the materials constituting the semiconductor device, see <Configuration Example 1 of Semiconductor Device> or <Configuration Example of Semiconductor Device> The materials described in detail in 2> can be used.

[0332] [Transistor 200B] As shown in FIG. 16, the transistor 200B is disposed on a substrate (not shown). An insulator 216, a conductor 205 disposed so as to be embedded in the insulator 216, and an insulator An insulator 222 is disposed on the conductor 216 and on the conductor 205, and a An insulator 224 is placed on the insulating layer 222 and an oxide 230 (oxide 230a) is placed on the insulating layer 222. , oxide 230b, oxide 230c1, and oxide 230c2), and the top of oxide 230 and a conductor 260 (conductor 260) disposed on the insulator 250. a, and conductor 260b), a part of the top surface of insulator 222, the side surface of insulator 224, and oxide The oxide 230b is disposed on the side of the oxide 230a, the side of the oxide 230b, and the top surface of the oxide 230b. The insulating material 254 (insulator 254a and insulator 254b) is formed by the oxidation of the oxide. A region 243a and a region 243b are formed on the upper surface of the oxide 230b and are spaced apart from each other. It is being done.

[0333] The transistor 200B is different from the transistors described above in that the conductor 242 is not provided. The following describes the differences from the above-mentioned transistor 200. Reveal.

[0334] As shown in FIG. 16B, the region 243a and the region 243b sandwich the conductor 260. It is preferable that the upper surfaces of the insulating member 252 and the insulating member 254 are in contact with each other. The side surfaces of the region 243a and the region 243b on the side of the conductor 260 are the same as the side surfaces of the conductor 260. The region 243a and the region 243b are aligned with or overlap with the conductor 260. It is preferred.

[0335] In the transistor 200B shown in FIG. 16, for example, the carrier density of the oxide 230 By adding an element that can increase the resistance and reduce the resistance as a dopant, Then, the region 243 (region 243a and region 243b) may be formed.

[0336] The dopant is an element that forms an oxygen vacancy or an element that bonds with the oxygen vacancy. Representative examples of such elements include boron and phosphorus. In addition, hydrogen, carbon, nitrogen, fluorine, sulfur, chlorine, titanium, rare gases, etc. may also be used. Representative examples of rare gases include helium, neon, argon, krypton, and xenon. Also, aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, etc. Zn, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium nium, zirconium, beryllium, indium, ruthenium, iridium, strontium Add one or more metal elements selected from the group consisting of lanthanum, lanthanum, etc. Among the above, boron and phosphorus are preferable as the dopant. , when phosphorus is used as a dopant, amorphous silicon, or low-temperature polysilicon This allows the use of existing production line equipment, which reduces capital investment. The concentration of the above elements may be measured using SIMS or the like.

[0337] In particular, it is preferable to use an element that easily forms an oxide as the element to be added to the region 243. Representative examples of such elements include boron, phosphorus, aluminum, magnesium, and the like. The element added to the region 243 takes away oxygen from the oxide 230 to form the oxide. As a result, many oxygen vacancies are formed in the region 243. When the hydrogen in the oxide 230 is bonded to the SiO 2 , carriers are generated, resulting in an extremely low resistance region. Furthermore, since the element added to the region 243 exists in the region 243 in the form of a stable oxide, Even if a subsequent process requiring high temperatures is performed, the metal is unlikely to be desorbed from the region 243. That is, the element to be added to the region 243 is an element that easily forms an oxide. This allows the formation of a region in the oxide 230 that is resistant to high resistance even when subjected to high-temperature processes.

[0338] Here, the concentration of the above elements in the region 243 is the same as that in the region 243 where the oxide 230 is not formed. It is preferable that the concentration of the above elements in the region 2 is equal to or higher than that in the region 3. The amount of oxygen vacancies in 43 is determined by the amount of oxygen vacancies in the portion of the oxide 230 where the region 243 is not formed. It is preferable that the amount of the defect is equal to or greater than the amount of the defect. The carrier density is higher than that of the area 243 of the oxide 230 where the oxide 230 is not formed. , the resistance becomes lower.

[0339] Forming regions 243 in the oxide 230 to function as source or drain regions. Thus, the region 243 is provided without providing a source electrode and a drain electrode made of a metal. A conductor 240 can be connected which acts as a plug.

[0340] Furthermore, when the region 243 is formed by adding the dopant in this manner, the insulators 254a and The oxide 230b, the insulator 254b are also doped with dopants. 4a, and insulator 254b have an element contained in the dopant. When the insulator 254a and the insulator 254b have excess oxygen, the excess oxygen is transferred to the outside by the dopant. By forming such a region 243, the diffusion of the element can be suppressed. The on-current of the 200B is increased, and the S value (Subthreshold Swing, SS This improves the frequency characteristics.

[0341] When the region 243 is formed by adding a dopant, for example, the oxide 230c1, the oxide A dummy gate is formed at a position where the oxide 230c2, the insulator 250, and the conductor 260 are to be provided. Then, the dummy gate is used as a mask to add dopants. Therefore, the above elements are added to the oxide 230 in the region where the dummy gate does not overlap. A region 243 containing the ions can be formed.

[0342] The dopant addition method is ionization, in which the ionized source gas is mass-separated and added. The ion doping method, which adds ionized source gas without mass separation, The mass separation method can be used. When this is done, the type of ions to be added and their concentrations can be strictly controlled. If separation is not performed, a high concentration of ions can be added in a short time. Alternatively, an ion doping method may be used in which molecular clusters are generated and ionized. A dopant may also be referred to as an ion, a donor, an acceptor, an impurity, or an element. stomach.

[0343] In addition, an element that forms oxygen vacancies is added to the region 243 and heat treatment is performed to form a channel. The hydrogen contained in the region 234, which functions as a hole formation region, is transferred to the oxygen vacancy contained in the region 243. This gives the transistor 200B stable electrical characteristics, Reliability can be improved.

[0344] In addition, in FIG. 16, the oxide 230c is replaced with the oxide 23 The insulator 254 is shown as a stack of oxide 230c1 and oxide 230c2, and the insulator 254 is shown as an insulator 254a and an insulator 254b. The stack of oxide 230c and insulator 254b is shown, but is not limited to this. It may be a single layer or a laminated structure of three or more layers.

[0345] <Configuration Example 4 of Semiconductor Device> FIG. 17 illustrates a transistor 200C according to one embodiment of the present invention and a transistor 200C 5A and 5B are top and cross-sectional views of the periphery.

[0346] FIG. 17A is a top view of a semiconductor device including a transistor 200C. 17(B) and 17(C) are cross-sectional views of the semiconductor device. FIG. 17A is a cross-sectional view of a portion indicated by a dashed line A1-A2 in FIG. 17(C) is a cross-sectional view of the channel length direction of 0C. 4 is a cross-sectional view of a portion indicated by a dashed line in FIG. 4A, and is a cross-sectional view in the channel width direction of a transistor 200C. In addition, in the top view of FIG. 17(A), some elements are omitted for clarity. is.

[0347] In the semiconductor device shown in FIG. 17, the semiconductor device shown in <Configuration Example 1 of the Semiconductor Device> The structures having the same functions as those constituting the device are denoted by the same reference numerals.

[0348] The configuration of the semiconductor device will be described below with reference to FIG. The materials used for the semiconductor device are explained in detail in the "Semiconductor Device Configuration Example 1". It is possible.

[0349] [Transistor 200C] As shown in FIG. 17, the transistor 200C is disposed on a substrate (not shown). An insulator 216, a conductor 205 disposed so as to be embedded in the insulator 216, and an insulator An insulator 222 is disposed on the conductor 216 and on the conductor 205, and a An insulator 224 is placed on the insulating layer 222 and an oxide 230 (oxide 230a) is placed on the insulating layer 222. , oxide 230b, and oxide 230c), and an insulator 2 disposed on the oxide 230. 50, and a conductor 260 (conductor 260a and conductor 26 0b), and conductors 242a and 242b in contact with a portion of the top surface of oxide 230b. , a part of the upper surface of the insulator 222, a side surface of the insulator 224, a side surface of the oxide 230a, and the oxide 23 0b, a side of the conductor 242a, an upper surface of the conductor 242a, a side of the conductor 242b, an insulator 254 disposed in contact with the upper surface of the insulator 242b and a portion of the oxide 230c; and an insulator 273 disposed over the conductor 260.

[0350] The insulating layer 273 is formed of the oxide 230c, the insulating layer 250, and a portion of the conductor 260. The insulator 280 overlaps the oxide 230c, the insulator 250, and the conductor 26. The difference between the transistor 200 and the transistor 200 described above is that the transistor 200 is provided on the We will explain the differences from Sta 200.

[0351] In the transistor 200C, the conductor 260 is connected to the conductor 242 through the insulator 250. a and a region overlapping with the conductor 242b via the insulator 250. By forming the conductor 260 in such a shape, the conductor 260 has a margin for alignment. Therefore, the region between the conductor 242a and the conductor 242b of the oxide 230 can be The conductors 260 can be reliably overlapped to prevent the formation of offset regions.

[0352] The insulator 273, like the insulator 254, is made of oxygen (for example, oxygen atoms, oxygen molecules, etc.). It is preferable that the material has a function of suppressing the diffusion of at least one of the above oxygen (i.e., the material is less likely to transmit oxygen). For example, insulator 273 has a lower oxygen permeability than insulator 280 or insulator 224. It is preferable that the conductor 260 is covered with the insulator 273. It is possible to inhibit 60 from being oxidized.

[0353] In addition, the insulator 273, like the insulator 254, is a material that is not susceptible to impurities such as water and hydrogen. It is preferable that the insulating film functions as a barrier insulating film that suppresses diffusion from the conductor 280 side to the conductor 260. For example, it is preferable that the insulator 273 has a lower hydrogen permeability than the insulator 224.

[0354] In FIG. 17, the insulator 273 covers the conductor 260 and is disposed on the upper surface of the insulator 250. However, the present invention is not limited to this. For example, the insulator 273 may be The insulating layer 260 covers the insulating layer 250 and the oxide layer 230c, and is in contact with the insulating layer 254. This is also fine.

[0355] The configurations and methods shown in the present embodiment may be the same as those shown in other embodiments or examples. The method can be used in combination with other methods.

[0356] (Embodiment 3) In this embodiment, one mode of a semiconductor device will be described with reference to FIGS.

[0357] [Storage device 1] FIG. 18 shows an example of a semiconductor device (memory device) using a capacitor according to one embodiment of the present invention. In the semiconductor device according to one embodiment of the present invention, the transistor 200 is disposed above the transistor 300. The capacitor 100 is disposed above the transistor 300 and the transistor 200. The transistor 200 may be the transistor described in the previous embodiment. Sta200 etc. can be used.

[0358] The transistor 200 is a transistor in which a channel is formed in a semiconductor layer having an oxide semiconductor. The transistor 200 is used in a memory device because its off-state current is small. This makes it possible to retain the memory contents for a long period of time. Since no refresh operation is required or the frequency of refresh operations is extremely low, Power consumption can be reduced sufficiently.

[0359] In the semiconductor device shown in FIG. 18, a wiring 1001 is electrically connected to the source of a transistor 300. The wiring 1002 is electrically connected to the drain of the transistor 300. The wiring 1003 is electrically connected to one of the source and drain of the transistor 200. The wiring 1004 is electrically connected to the first gate of the transistor 200. 006 is electrically connected to the second gate of the transistor 200. The gate of the transistor 300 and the other of the source and drain of the transistor 200 are connected to a capacitor. The wiring 1005 is electrically connected to one of the electrodes of the capacitor 100. It is electrically connected to the other.

[0360] In addition, the memory device shown in FIG. 18 has a memory cell array arranged in a matrix. It can be configured.

[0361] <Transistor 300> The transistor 300 is provided on a substrate 311 and has a conductor 312 functioning as a gate electrode. 16, an insulator 315 acting as a gate insulator, a semiconductor region consisting of a portion of a substrate 311 313, and low resistance regions 314a functioning as source or drain regions, and low resistance region 314b. The transistor 300 may be a p-channel or n-channel. Either a filter type or a filter panel type may be used.

[0362] Here, the transistor 300 shown in FIG. 18 has a semiconductor region 313 ( A part of the substrate 311 has a convex shape. The side and top surfaces of the semiconductor region 313 are insulated. The conductor 316 is provided so as to cover the edge 315. Materials for adjusting the work function may be used. Since it uses a protruding part, it is also called a FIN type transistor. In addition, the insulating layer may have an insulating material that functions as a mask for forming the protrusions. Here, a case where a protrusion is formed by processing a part of a semiconductor substrate is shown, but a SOI substrate is also processed. A semiconductor film having a convex shape may be formed by the above-mentioned method.

[0363] Note that the transistor 300 shown in FIG. 18 is just an example, and the present invention is not limited to this structure. Appropriate transistors may be used depending on the configuration and driving method.

[0364] <Capacitive element 100> The capacitor 100 is provided above the transistor 200. A conductor 110 serving as the first electrode, a conductor 120 serving as the second electrode, and a conductor It has an insulator 130 that functions as a conductor.

[0365] Also, for example, the conductor 112 provided on the conductor 240 and the conductor 110 are formed at the same time. Note that the conductor 112 can be used for the capacitor 100, the transistor 200, and has a function as a plug or wiring that is electrically connected to the transistor 300 .

[0366] In FIG. 18, the conductor 112 and the conductor 110 are shown to have a single-layer structure. However, the present invention is not limited to this, and may be a laminated structure of two or more layers. For example, Conductors that have barrier properties between weak conductors and those with high electrical conductivity have good adhesion to conductors with high electrical conductivity. may form a highly conductive material.

[0367] The insulator 130 may be, for example, silicon oxide, silicon oxynitride, or silicon nitride oxide. , silicon nitride, aluminum oxide, aluminum oxide nitride, aluminum oxide nitride, nitrogen Aluminum oxide, hafnium oxide, hafnium oxynitride, hafnium nitride oxide, hafnium The conductive layer may be formed as a laminate or a single layer.

[0368] For example, the insulator 130 may be made of a material with high dielectric strength, such as silicon oxynitride, or a material with high dielectric strength. It is preferable to use a laminated structure with a high-k material. The element 100 has a high dielectric constant (high-k) insulator, so that it can ensure sufficient capacitance. By using an insulator having a large dielectric strength, the dielectric strength is improved, and the electrostatic breakdown of the capacitance element 100 is prevented. This can suppress the destruction.

[0369] In addition, oxide is an insulator for high dielectric constant (high-k) materials (materials with a high relative dielectric constant). Contains gallium, hafnium oxide, zirconium oxide, aluminum and hafnium Oxide, Oxynitride with Aluminum and Hafnium, Silicon and Hafnium oxides having silicon and hafnium; oxide nitrides having silicon and hafnium; Nitrides containing uranium.

[0370] On the other hand, materials with high dielectric strength (materials with low dielectric constant) include silicon oxide and oxynitride. Silicon oxide, silicon nitride, silicon nitride, silicon oxide doped with fluorine, carbon Doped silicon oxide, carbon and nitrogen doped silicon oxide, vacancy-containing silicon oxide Examples include gum and resin.

[0371] <Wiring layer> Between each structure, a wiring layer including an interlayer film, wiring, plugs, etc. may be provided. In addition, multiple wiring layers can be provided depending on the design. Conductors that function as lines may be grouped together and given the same symbol. In addition, in this specification and the like, the wiring and the plug electrically connected to the wiring are integrated. That is, when a part of the conductor functions as a wiring, or when a part of the conductor It may also function as a plug.

[0372] For example, on the substrate 311, an insulator 320, an insulator 322, an insulator 323, and an insulator 324 are provided as interlayer films. The insulating material 315 and the conductive material 326 are laminated in this order. The conductive body 316 is embedded in the insulator 320. , insulator 322, insulator 324, and insulator 326 are connected to the capacitive element 100 or the transformer. A conductor 328 and a conductor 330 are embedded in the insulating film 200. The conductor 328 and the conductor 330 are electrically connected to the insulating film 200. The conductor 328 and the conductor 330 function as plugs or wiring.

[0373] In addition, the insulator that functions as an interlayer film acts as a flattening film that covers the uneven shape underneath. For example, the top surface of the insulator 322 may be chemically mechanically polished ( The surface may be planarized by a planarization process using a chemical mechanical polishing (CMP) method or the like.

[0374] A wiring layer may be provided on the insulator 326 and the conductor 330. For example, in FIG. In the insulating layer 350, an insulator 352, and an insulator 354 are stacked in this order. In addition, a conductor 356 is formed on the insulators 350, 352, and 354. The conductor 356 functions as a plug or a wiring.

[0375] On the insulator 354 and the conductor 356, the insulators 210, 212, and 21 4, and an insulator 216 are laminated in this order. 12, insulator 214, and insulator 216 include conductor 218 and transistor 200. The conductor 218 is a capacitor. As a plug or wiring electrically connecting the element 100 or the transistor 300 Further, an insulator 150 is provided on the conductor 120 and the insulator 130. It is being done.

[0376] Insulators that can be used as the interlayer film include oxides, nitrides, and oxides having insulating properties. These include metal nitrides, nitride oxides, metal oxides, metal oxynitrides, and metal nitride oxides.

[0377] For example, by using a material with a low relative dielectric constant for the insulator that functions as an interlayer film, Therefore, depending on the function of the insulator, the material It is recommended to select:

[0378] For example, the insulators 212, 352, and 354 are made of insulators having a low relative dielectric constant. For example, the insulator may be silicon oxide, silicon oxynitride, or nitride. Silicon oxide, silicon nitride, silicon oxide doped with fluorine, silicon oxide doped with carbon Con, silicon oxide with added carbon and nitrogen, silicon oxide with voids, resin, etc. Alternatively, the insulator may be silicon oxide, silicon oxynitride, or nitride. Silicon oxide, silicon nitride, silicon oxide doped with fluorine, silicon oxide doped with carbon Silicon oxide with carbon and nitrogen added or silicon oxide with vacancies, and resin Silicon oxide and silicon oxynitride are preferably thermally degradable. It is thermally stable, so by combining it with resin, a laminated structure with low dielectric constant and thermal stability can be achieved. Examples of the resin include polyester, polyolefin, and polyamide. Examples include nylon, aramid, polyimide, polycarbonate, and acrylic.

[0379] In addition, the insulator 130 provided on the conductor 112 or the conductor 120, and the insulator 150 or both have a resistivity of 1.0×10 12 Ωcm or more 1.0×10 15 Ωc m or less, preferably 5.0×10 12 Ωcm or more 1.0×10 14 Ωcm or less, more preferred Or 1.0×10 13 Ωcm or more 5.0×10 13 It is preferable to use an insulator with a resistance of Ωcm or less. It is preferable that one or both of the insulators 130 and 150 have the resistivity as described above. By using an insulator having such a structure, the insulator can maintain its insulating properties while preventing the transistor 200 from being damaged. Between the transistor 300, the capacitor 100, and the wirings of the conductor 112, the conductor 120, etc. A transistor for dispersing accumulated charge and storing the charge, and a storage device having the transistor Such an insulator can suppress the deterioration of the characteristics and electrostatic breakdown. Silicon or silicon oxynitride can be used.

[0380] In addition, as an insulator having the above-mentioned resistivity, the insulator 140 is disposed under the conductor 112. In this case, the insulator 140 may be formed on the insulator 281. Openings are formed in the edge 281, the insulator 274, the insulator 280, the insulator 254, etc., and the openings The insulator 241 is formed in the opening, and the transistor 200 and the conductor 218 are electrically connected. The insulator 140 may be the insulator 130 or the insulator 1. Materials similar to those in 50 can be used.

[0381] In addition, a transistor using an oxide semiconductor can suppress the permeation of impurities such as hydrogen and oxygen. By surrounding the transistor with an insulator that has the function of suppressing the Therefore, impurities such as hydrogen and oxygen are contained in the insulators 210 and 350. An insulator having a function of suppressing the transmission of light may be used.

[0382] Examples of insulators that have a function of suppressing the permeation of impurities such as hydrogen and oxygen include: Boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, salt Argon, Gallium, Germanium, Yttrium, Zirconium, Lanthanum, Neo Insulators containing zinc, hafnium or tantalum may be used in single or multilayer configurations. Specifically, the following insulators have the function of suppressing the permeation of impurities such as hydrogen and oxygen: Aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide , Zirconium oxide, Lanthanum oxide, Neodymium oxide, Hafnium oxide, Tantalum oxide Metal oxides such as those mentioned above, silicon nitride oxide, silicon nitride, etc. can be used.

[0383] Conductors that can be used for wiring and plugs include aluminum, chromium, copper, silver, Gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium Sodium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium Materials containing one or more metal elements selected from the group consisting of ruthenium and lithium can be used. Semiconductors with high electrical conductivity, such as polycrystalline silicon containing impurity elements such as arsenic, A silicide such as nickel silicide may also be used.

[0384] For example, conductor 328, conductor 330, conductor 356, conductor 218, conductor 110, The conductors 112, 120, etc. may be made of the above-mentioned metal materials, alloy materials, Conductive materials such as metal nitride materials and metal oxide materials can be used in a single layer or in a laminated form. It is possible to use high-melting-point materials such as tungsten and molybdenum, which have both heat resistance and electrical conductivity. It is preferable to use tungsten. Alternatively, aluminum, copper, etc. It is preferable to form the wiring from a low resistance conductive material. The resistance can be reduced.

[0385] <<Wiring or plug of a layer in which an oxide semiconductor is provided>> When an oxide semiconductor is used for the transistor 200, excess An insulator having an oxygen region may be provided. In that case, the insulator having the excess oxygen region and an insulator having a barrier property is provided between the conductor and the insulator having the excess oxygen region. It is preferable to provide such a function.

[0386] For example, in FIG. 18, an insulator 280 and an insulator 281 are provided between the conductor 240 and the insulator 281. It is preferable to provide an insulating body 241. The insulating body 241 is connected to the insulating body 280 and the insulating body 281 and the conductive body. The insulator 280 and the insulator Absorption of oxygen contained in 281, that is, oxidation of the conductor 240, can be suppressed.

[0387] In other words, by providing the insulator 241, the excess oxygen contained in the insulator 280 is absorbed by the conductor 24 In addition, the insulator 241 can prevent impurities from being absorbed by the insulator 241. The hydrogen, which is a substance, is prevented from diffusing into the transistor 200 via the conductor 240. It is possible.

[0388] The insulator 241 has a function of suppressing the diffusion of impurities such as water and hydrogen, and oxygen. It is advisable to use insulating materials that have the above properties. For example, aluminum oxide, hafnium oxide, etc. In addition, for example, magnesium oxide, gallium oxide, oxide Germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, Metal oxides such as tantalum oxide, silicon nitride oxide, silicon nitride, etc. can be used. Cut.

[0389] The above is a description of the configuration example. By using this configuration, In a semiconductor device using a transistor, the fluctuation of electrical characteristics is suppressed and the reliability is improved. In addition, a transistor including an oxide semiconductor with high on-state current can be provided. In addition, a transistor including an oxide semiconductor and having a low off-state current can be provided. In addition, a semiconductor device with reduced power consumption can be provided.

[0390] [Storage device 2] FIG. 19 illustrates an example of a memory device using a semiconductor device according to one embodiment of the present invention. The memory device shown in FIG. 18 includes the transistor 200, the transistor 300, and the capacitor In addition to the semiconductor device having the capacitor 100 , a transistor 400 is also included.

[0391] The transistor 400 can control the second gate voltage of the transistor 200. For example, the first gate and the second gate of the transistor 400 are connected to the source and the diode. and connect the source of the transistor 400 and the second gate of the transistor 200. In this configuration, when the second gate of the transistor 200 is held at a negative potential, The first gate-source voltage and the second gate-source voltage of the transistor 400 are In the transistor 400, the second gate voltage and the first gate voltage Since the drain current at 0V is very small, the transistors 200 and Even if power is not supplied to the transistor 400, the negative potential of the second gate of the transistor 200 can be maintained for a long time. This allows the transistor 200 and the transistor 400 to be maintained for a certain period of time. A storage device having such a function is capable of retaining stored contents for a long period of time.

[0392] Therefore, in FIG. 19, the wiring 1001 is electrically connected to the source of the transistor 300. The wiring 1002 is electrically connected to the drain of the transistor 300. The wiring 1003 is electrically connected to one of the source and drain of the transistor 200. The wiring 1004 is electrically connected to the first gate of the transistor 200, and the wiring 1006 is The second gate of the transistor 200 is electrically connected to the second gate of the transistor 3 The gate of transistor 200 and the other of the source and drain of transistor 200 are connected to capacitance element 1 The wiring 1005 is electrically connected to one of the electrodes of the capacitor 100. The wiring 1007 is electrically connected to the source of the transistor 400. The wiring 1008 is electrically connected to the first gate of the transistor 400, and the wiring 1009 is electrically connected to the first gate of the transistor 400. is electrically connected to the second gate of the transistor 400, and the wiring 1010 is 400. Here, the wiring 1006, the wiring 1007, the wiring The line 1008 and the wiring 1009 are electrically connected.

[0393] The storage device shown in FIG. 19 is arranged in a matrix, similar to the storage device shown in FIG. By doing so, a memory cell array can be configured. 0 can control the second gate voltages of the plurality of transistors 200. It is preferable to provide fewer transistors 400 than transistors 200.

[0394] <Transistor 400> Transistor 400 is formed in the same layer as transistor 200 and is fabricated in parallel. The transistor 400 has a first gate electrode and a second gate electrode. A conductor 460 (conductor 460a and conductor 460b) that functions as a gate electrode and a second gate electrode Conductor 405 functions as a pole, insulator 222 functions as a gate insulator, and insulator 4 24a, insulator 424b, and insulator 450, and an oxide having a region in which a channel is to be formed. The oxide 430c, the conductor 442a functioning as either the source or the drain, and the oxide 4 31a, and oxide 431b, and conductor 4 serving as the other of the source or drain. 42b, oxide 432a, and oxide 432b, and conductor 440 (conductor 440a, and conductor 440b).

[0395] In the transistor 400, the conductor 405 is formed in the same layer as the conductor 205. The insulator 424a and the insulator 424b are formed in the same layer as the insulator 224. The oxide 431a and oxide 432a are formed in the same layer as the oxide 230a. The conductor 431b and the oxide 432b are formed in the same layer as the oxide 230b. 42 is formed in the same layer as the conductor 242. The oxide 430c is formed in the same layer as the oxide 230c. The insulator 450 is formed in the same layer as the insulator 250. 60 is formed in the same layer as the conductor 260 .

[0396] It should be noted that structures formed in the same layer can be formed simultaneously. For example, oxide 4 30c can be formed by processing an oxide film that will become oxide 230c.

[0397] The oxide 430c that functions as the active layer of the transistor 400 is the same as the oxide 230, etc. Similarly, oxygen vacancies are reduced, and impurities such as water and hydrogen are reduced. The threshold voltage of the transistor 400 is increased, the off-current is reduced, and the second gate voltage and When the first gate voltage is 0V, the drain current can be made very small.

[0398] <<Dicing line>> In the following, a large-area substrate is divided into individual semiconductor elements to produce multiple semiconductor devices. Dicing lines (scribe lines, dividing lines) are provided when extracting chips. The following describes the method of cutting the wire. First, grooves (dicing lines) for dividing the semiconductor elements are formed on the substrate, and then the dicing In some cases, the semiconductor device is cut at a grinding line and divided (divided) into a plurality of semiconductor devices.

[0399] The transistor 200 described in the previous embodiment and the transistor shown in this embodiment At the outer edge of 400, as shown in FIG. 19, the insulator 254 and the insulator 222 come into contact with each other. Therefore, the area where the insulator 254 and the insulator 222 contact each other is set as a dicing line. When designing the dicing line, the degree of freedom in designing the dicing line can be increased. Insulator 222 and insulator 254 may be formed using the same material and method. By providing the insulating material 254 using the same material and method, it is possible to improve adhesion. For example, it is preferable to use aluminum oxide.

[0400] With this structure, the insulator 222 and the insulator 254 are insulated from the insulator 224 and the transistor 200, and the transistor 400 can be encapsulated. The body 254 has a function of suppressing the diffusion of oxygen, hydrogen, and water. The substrate is divided into a plurality of chips by dividing the substrate into circuit regions each having a semiconductor element as shown in FIG. Even if the substrate is processed into a chip, impurities such as water and hydrogen can enter the chip from the side of the cut substrate and cause damage to the transistors. Therefore, diffusion to the transistor 200 and the transistor 400 can be prevented.

[0401] In addition, this structure allows excess oxygen in the insulator 224 to migrate to the insulator 254 and the insulator 222. Therefore, the excess oxygen in the insulator 224 can be prevented from diffusing out of the insulator 224. The oxide on which the channel of the transistor 200 or the transistor 400 is formed is The oxygen is supplied to the transistor 200 or the transistor 400. This reduces the oxygen vacancies in the oxide in which the channel is formed. The oxide on which the channel of the transistor 200 or 400 is formed is made defect-free. It is possible to obtain an oxide semiconductor having a low potential density and stable characteristics. The present invention suppresses the fluctuation of the electrical characteristics of the transistor 200 or the transistor 400 and improves reliability. It can be raised.

[0402] This embodiment mode may be appropriately combined with the configurations described in other embodiment modes and examples. It is possible to implement.

[0403] (Embodiment 4) In this embodiment, a semiconductor device using an oxide according to one embodiment of the present invention will be described with reference to FIGS. 20 and 21. A transistor used as a conductor (hereinafter, sometimes referred to as an OS transistor) and a capacitor A storage device to which the device is applied (hereinafter, sometimes referred to as an OS memory device) will be described. The OS memory device includes at least a capacitive element and an OS transistor that controls charging and discharging of the capacitive element. The off-state current of an OS transistor is extremely small, The OS memory device has excellent retention characteristics and can function as a non-volatile memory. .

[0404] <Storage device configuration example> FIG. 20A shows an example of the configuration of an OS memory device. The memory device 1400 includes a peripheral circuit 1 411, and a memory cell array 1470. The peripheral circuit 1411 includes a row circuit 142 0, column circuitry 1430, output circuitry 1440, and control logic circuitry 1460. do.

[0405] The column circuits 1430 include, for example, column decoders, precharge circuits, sense amplifiers, write The precharge circuit has a function of precharging the wiring. The amplifier has a function of amplifying the data signal read from the memory cell. The lines are wirings connected to memory cells in the memory cell array 1470. The amplified data signal is output via an output circuit 1440 as a data signal RDA TA to the outside of the memory device 1400. It has a decoder, a word line driver circuit, etc., and can select a row to be accessed.

[0406] The storage device 1400 is supplied with a low power supply voltage (VSS) from the outside as a power supply voltage, and a peripheral circuit 14 11, and the high power supply voltage (VIL) for the memory cell array 1470. The storage device 1400 also receives control signals (CE, WE, RE), address signals, and The address signal ADDR and the data signal WDATA are input from the outside. The data signal WDATA is input to the write circuit. do.

[0407] The control logic circuit 1460 receives control signals (CE, WE, R E) to generate control signals for the row decoder and column decoder. The control signal WE is a write enable signal, and the control signal R E is a read enable signal. The signal is not limited to this, and other control signals may be input as necessary.

[0408] The memory cell array 1470 includes a plurality of memory cells MC arranged in a matrix and a plurality of The wiring connecting the memory cell array 1470 and the row circuit 1420 is The number of lines is determined by the configuration of the memory cells MC, the number of memory cells MC in one row, etc. The number of wirings connecting the memory cell array 1470 and the column circuit 1430 is It is determined by the configuration of the recell MC, the number of memory cells MC in one row, etc.

[0409] In FIG. 20A, the peripheral circuit 1411 and the memory cell array 1470 are arranged on the same plane. Although an example of forming the insulating film on a surface has been shown, the present embodiment is not limited to this. For example, as shown in FIG. 20B, the memory cell array 1411 is provided on a part of the peripheral circuit 1411. 70 may be provided so as to overlap the memory cell array 1470. For example, In this way, a sense amplifier may be provided.

[0410] FIG. 21 illustrates an example of a memory cell configuration that can be applied to the above-mentioned memory cell MC.

[0411] [DOSRAM] 21A to 21C show examples of circuit configurations of memory cells in a DRAM. In this study, a DRAM using a memory cell of one OS transistor and one capacitor element type is called DOSRA. M (registered trademark) (Dynamic Oxide Semiconductor Rand The memory cell shown in Figure 21(A) is sometimes called a omniaccess memory. The filter 1471 includes a transistor M1 and a capacitance element CA. 1 has a gate (sometimes called a top gate) and a back gate.

[0412] A first terminal of the transistor M1 is connected to a first terminal of the capacitance element CA, and the transistor M The second terminal of the transistor M1 is connected to the wiring BIL, and the gate of the transistor M1 is connected to the wiring WOL. The back gate of the transistor M1 is connected to the wiring BGL. The second terminal of A is connected to the wiring CAL.

[0413] The wiring BIL functions as a bit line, and the wiring WOL functions as a word line. CAL functions as a wiring for applying a predetermined potential to the second terminal of the capacitive element CA. When writing and reading data, a low level potential is applied to the wiring CAL. The wiring BGL is preferably used for applying a potential to the back gate of the transistor M1. By applying an arbitrary potential to the wiring BGL, The threshold voltage of M1 can be increased or decreased.

[0414] In addition, the memory cell MC is not limited to the memory cell 1471, and the circuit configuration may be changed. For example, the memory cell MC can be a memory cell 1472 shown in FIG. In addition, the back gate of the transistor M1 is connected to the wiring WOL instead of the wiring BGL. For example, the memory cell MC may be a memory cell 14 shown in FIG. As shown in FIG. 73, a transistor having a single gate structure, i.e., a transistor without a back gate, The memory cell may be configured with a resistor M1.

[0415] When the semiconductor device described in the above embodiment is used for the memory cell 1471 or the like, The transistor 200 is used as M1, and the capacitance element 100 is used as the capacitance element CA. By using an OS transistor as the transistor M1, This makes it possible to make the leakage current of the transistor M1 very small. The transistor M1 allows the data to be retained for a long time, reducing the frequency of refreshing the memory cells. In addition, the refresh operation of the memory cells can be eliminated. In addition, since the leakage current is very small, the memory cells 1471 and 147 2. The memory cell 1473 can hold multi-value data or analog data. do.

[0416] In addition, in the DOSRAM, as described above, By providing a sense amplifier as described above, the bit line can be shortened. This reduces the bit line capacitance and the storage capacitance of the memory cell.

[0417] [NOSRAM] FIG. 21D to FIG. 21G show a gain cell type memory cell having two transistors and one capacitor. A circuit configuration example is shown in FIG. 21D. A memory cell 1474 shown in FIG. The transistor M2 is a top gate. In this specification, etc., The memory cell has a gain cell type memory cell using an OS transistor as the transistor M2. The memory device is NOSRAM (registered trademark) (Nonvolatile Oxide Semiconductor It is sometimes called RAM).

[0418] A first terminal of the transistor M2 is connected to a first terminal of the capacitance element CB, and the transistor M The second terminal of the transistor M2 is connected to the wiring WBL, and the gate of the transistor M3 is connected to the wiring WOL. The back gate of the transistor M2 is connected to the wiring BGL. The second terminal of the transistor M1 is connected to the wiring CAL. The first terminal of the transistor M2 is connected to the wiring R BL, the second terminal of the transistor M3 is connected to the line SL, and the second terminal of the transistor M The gate of 3 is connected to a first terminal of the capacitance element CB.

[0419] The wiring WBL functions as a write bit line, and the wiring RBL functions as a read bit line. The wiring WOL functions as a word line. The wiring CAL is connected to the second It functions as a wiring for applying a specific potential to the terminal. During the data read operation, a low level potential is applied to the wiring CAL. The wiring BGL is a wiring for applying a potential to the back gate of the transistor M2. By applying an arbitrary potential to the wiring BGL, The threshold voltage can be increased or decreased.

[0420] In addition, the memory cell MC is not limited to the memory cell 1474, and the circuit configuration may be appropriately changed. For example, the memory cell MC can be the memory cell 1475 shown in FIG. In this way, the back gate of the transistor M2 is connected to the wiring WOL instead of the wiring BGL. For example, the memory cell MC may be a memory cell shown in FIG. Like the 1476, it has a single-gate transistor, i.e. no back gate. The memory cell may be configured with a transistor M2. For example, the memory cell MC As shown in FIG. 21G, a memory cell 1477 is formed by connecting a wiring WBL and a wiring RBL together. The wiring BIL may be integrated.

[0421] When the semiconductor device described in the above embodiment is used for the memory cell 1474 or the like, The transistor 200 is used as M2, and the transistor 300 is used as M3. The capacitance element CB can be a capacitance element 100. By using an OS transistor, the leakage current of transistor M2 is made very small. This allows the written data to be stored for a long time by the transistor M2. Since the memory cells can be maintained at a constant level, the frequency of refreshing the memory cells can be reduced. In addition, the refresh operation of the memory cells can be eliminated. Since the memory cell 1474 is always small, it is possible to store multi-value data or analog data. The same can be said for memory cells 1475 to 1477.

[0422] The transistor M3 is a transistor having silicon in the channel formation region (hereinafter The conductivity type of the Si transistor may be The Si transistor may be an n-channel type or a p-channel type. In some cases, the field effect mobility is higher than that of the read transistor. A Si transistor may be used as the transistor M3 that functions as the By using a Si transistor for transistor M3, a transistor Since the memory cell can be provided with a transistor M2, the area occupied by the memory cell can be reduced, and the memory device can be made more efficient. Integration can be achieved.

[0423] The transistor M3 may be an OS transistor. When an OS transistor is used for the transistor M3, the memory cell array 1470 is The circuit can be constructed using only transistors.

[0424] FIG. 21(H) shows an example of a gain cell type memory cell having three transistors and one capacitor. The memory cell 1478 shown in FIG. 6, and a capacitor element CC. The capacitor element CC is provided as appropriate. is electrically connected to the wiring BIL, wiring RWL, wiring WWL, wiring BGL, and wiring GNDL. The wiring GNDL is a wiring that applies a low level potential. The wiring 478 may be electrically connected to the wiring RBL and the wiring WBL instead of the wiring BIL.

[0425] The transistor M4 is an OS transistor having a back gate. The back gate and gate of the transistor M4 are electrically connected to the wiring BGL. Alternatively, the transistor M4 may have a back gate. It's not necessary.

[0426] The transistors M5 and M6 are n-channel Si transistors. Alternatively, the transistors M4 to M5 may be p-channel Si transistors. The transistor M6 may be an OS transistor. In this case, the memory cell array 1470 is configured as an n-type transistor. The circuit can be constructed using only transistors.

[0427] When the semiconductor device described in the above embodiment is used for the memory cell 1478, the transistor M The transistor M4 is a transistor 200, and the transistors M5 and M6 are transistors The transistor 300 can be used as the capacitance element CC, and the capacitance element 100 can be used as the capacitance element CC. By using an OS transistor as transistor M4, the leakage current of transistor M4 is The flow can be very small.

[0428] The configurations of the peripheral circuit 1411, the memory cell array 1470, and the like shown in this embodiment are However, the above is not limited to the above. The arrangement or functions of road elements, etc. may be changed, deleted, or added as necessary.

[0429] The structure shown in this embodiment mode may be appropriately combined with structures shown in other embodiment modes, examples, etc. It can be used.

[0430] (Embodiment 5) In this embodiment, a chip 1200 on which the semiconductor device of the present invention is mounted is shown in FIG. An example of the chip 1200 is shown. A plurality of circuits (systems) are implemented on the chip 1200. The technology of integrating multiple circuits (systems) onto a single chip is called system-on-chip (SCC). This is sometimes called System on Chip (SoC).

[0431] As shown in FIG. 22A, the chip 1200 includes a CPU (Central Processor). ssing Unit) 1211, GPU (Graphics Processing a memory controller 1212, one or more analog arithmetic units 1213, controller 1214, one or more interfaces 1215, one or more networks It has a work circuit 1216 and the like.

[0432] The chip 1200 is provided with bumps (not shown), and as shown in FIG. Printed Circuit Board (PCB) 1201 No. 1 The first surface of the PCB 1201 is connected to the second surface of the PCB 1202. 1203 is provided and connected to the motherboard 1203 .

[0433] The motherboard 1203 is provided with storage devices such as a DRAM 1221 and a flash memory 1222. For example, the DRAM 1221 may be provided with a DOSR as shown in the previous embodiment. For example, the flash memory 1222 may be The NOSRAM shown in FIG.

[0434] The CPU 1211 preferably has multiple CPU cores. It is preferable that the CPU 1211 and the GPU 1 have multiple GPU cores. Each of the CP 212 may have a memory for temporarily storing data. A memory common to U1211 and GPU1212 is provided on chip 1200. The memory may be the above-mentioned NOSRAM or DOSRAM. In addition, the GPU1212 is suitable for parallel calculation of large amounts of data, and is ideal for image processing and multiply-and-accumulate operations. The GPU 1212 can be used as an image processing circuit or the like using the oxide semiconductor of the present invention. By providing a multiply-and-accumulate circuit, image processing and multiply-and-accumulate operations can be performed with low power consumption. This will be possible.

[0435] In addition, the CPU 1211 and GPU 1212 are integrated on the same chip, The wiring between the CPU1211 and the GPU1212 can be shortened, and the Data transfer from the CPU 1211 to the GPU 1212, memory of the CPU 1211 and the GPU 1212 After data transfer between GPU1212 and calculation in GPU1212, the data is transferred from GPU1212 to CPU12. The calculation results can be transferred to 11 at high speed.

[0436] The analog calculation unit 1213 includes an A / D (analog / digital) conversion circuit and a D / A (digital The analog calculation unit 1213 has one or both of a digital / analog conversion circuit and a digital / analog conversion circuit. The multiply-and-accumulate circuit may be provided in the

[0437] The memory controller 1214 is a circuit that functions as a controller for the DRAM 1221. and a circuit that functions as an interface with the flash memory 1222.

[0438] The interface 1215 includes a display device, a speaker, a microphone, a camera, a The controller has an interface circuit for connecting to external devices such as a Such interfaces include computers, mobile phones, keyboards, and game controllers. USB (Universal Serial Bus), HDMI (registered trademark) High-Definition Multimedia Interface) There can be.

[0439] The network circuit 1216 is a LAN (Local Area Network) or the like. It may also have a circuit for network security. stomach.

[0440] The above circuits (systems) can be formed in the chip 1200 in the same manufacturing process. Therefore, even if the number of circuits required for the chip 1200 increases, the manufacturing process can be increased. This eliminates the need for a soldering process, and the chip 1200 can be produced at low cost.

[0441] A PCB 1201 on which a chip 1200 having a GPU 1212 is provided, a DRAM 122 1, and the motherboard 1203 on which the flash memory 1222 is provided is a GPU module. It can be called module 1204.

[0442] The GPU module 1204 includes a chip 1200 using SoC technology. Its size can be reduced. Also, its excellent image processing capabilities make it a smart device. Phones, tablet devices, laptop PCs, portable (portable) game consoles, etc. It is suitable for use in portable electronic devices. Deep Neural Networks (DNNs), Convolutional Neural Networks (CNN), Recurrent Neural Network (RNN), Autoencoder, Deep Boltzmann It can implement techniques such as deep belief networks (DBNs) and deep learning machines (DBMs). Therefore, the chip 1200 is an AI chip, or the GPU module 1204 is an AI system module. It can be used as a module.

[0443] The structure shown in this embodiment mode may be appropriately combined with structures shown in other embodiment modes, examples, etc. It can be used.

[0444] (Embodiment 6) In this embodiment mode, an application example of a memory device using the semiconductor device described in the above embodiment will be described. The semiconductor device described in the above embodiment is used in, for example, various electronic devices (e.g., Terminals, computers, smartphones, e-book readers, digital cameras (including video cameras) The present invention can be applied to storage devices such as video recorders, video recorders, and navigation systems. Here, computers include tablet computers, notebook computers, desktop computers, etc. This includes desktop computers as well as large computers such as server systems. Alternatively, the semiconductor device described in the above embodiment may be used as a memory card (for example, an SD card). Various removable drives such as USB memory and SSD (Solid State Drive) FIG. 23 shows some configuration examples of removable storage devices. For example, the semiconductor device shown in the above embodiment is a packaged memory chip. It is processed and used in various storage devices and removable memory.

[0445] FIG. 23A is a schematic diagram of a USB memory. The USB memory 1100 is a housing 1101. 1102, a USB connector 1103, and a substrate 1104. 4 is housed in a housing 1101. For example, the substrate 1104 includes a memory chip 110 5, a controller chip 1106 is attached. The semiconductor device shown in the embodiment can be incorporated in the semiconductor device.

[0446] FIG. 23(B) is a schematic diagram of the external appearance of an SD card, and FIG. 23(C) is a schematic diagram of the inside of an SD card. The SD card 1110 includes a housing 1111, a connector 1112, and a base. The substrate 1113 is housed in a housing 1111. For example, the substrate 11 13 has a memory chip 1114 and a controller chip 1115 attached thereto. By providing a memory chip 1114 on the back side of the substrate 1113, The capacity can be increased. In addition, a wireless chip having a wireless communication function is provided on the substrate 1113. This allows the host device and the SD card 1110 to wirelessly communicate with each other. This allows data to be read from and written to the memory chip 1114. The semiconductor device described in the above embodiment can be incorporated into such a semiconductor device.

[0447] FIG. 23(D) is a schematic diagram of the external appearance of the SSD, and FIG. 23(E) is a schematic diagram of the internal structure of the SSD. The SSD 1150 includes a housing 1151, a connector 1152, and a substrate 1153. The substrate 1153 is housed in the housing 1151. For example, the substrate 1153 has a The memory chip 1154, memory chip 1155, and controller chip 1156 are installed. The memory chip 1155 is a working memory for the controller chip 1156. For example, a DOSRAM chip may be used. By providing the memory chip 115, the capacity of the SSD 1150 can be increased. The semiconductor device described in the above embodiment can be incorporated into the semiconductor device 4 or the like.

[0448] This embodiment may be implemented in appropriate combination with configurations described in other embodiments, examples, etc. It is possible to do so.

[0449] (Embodiment 7) A semiconductor device according to one aspect of the present invention is a processor such as a CPU or a GPU, or a chip. FIG. 24 shows a processor such as a CPU or a GPU according to an embodiment of the present invention. Specific examples of electronic devices equipped with the chip are given below.

[0450] <Electronic equipment and systems> A GPU or chip according to an embodiment of the present invention can be installed in various electronic devices. Examples of electronic devices include television sets, desktop or notebook computers, etc. Personal computers, computer monitors, digital signage tal Signage, large game machines such as pachinko machines, etc. In addition to electronic devices with large screens, digital cameras, digital video cameras, digital photos, Examples of the optical fiber include frames, mobile phones, portable game machines, personal digital assistants, and audio playback devices. Furthermore, by providing an integrated circuit or chip according to one embodiment of the present invention in an electronic device, It is possible to equip child devices with artificial intelligence.

[0451] The electronic device according to one embodiment of the present invention may include an antenna. By doing so, it is possible to display images and information on the display unit. And if a secondary battery is included, the antenna may be used for contactless power transmission.

[0452] The electronic device according to one embodiment of the present invention includes a sensor (force, displacement, position, velocity, acceleration, angular velocity, rotation Numbers, distance, light, liquids, magnetism, temperature, chemicals, sound, time, hardness, electric field, current, voltage, power (including the ability to measure radiation, flow rate, humidity, gradient, vibration, odor or infrared rays) It may have.

[0453] The electronic device according to one embodiment of the present invention can have various functions. Functions for displaying still images, videos, text images, etc. on the display, touch panel function, calendar Functions such as displaying date or time, running various software (programs) a function to read out a program or data recorded on a recording medium; The electronic device may have the following functions: FIG. 24 shows an example of the electronic device.

[0454] [mobile phone] FIG. 24(A) illustrates a mobile phone (smartphone), which is a type of information terminal. The information terminal 5500 includes a housing 5510 and a display unit 5511. As an interface, a touch panel is provided on the display unit 5511, and buttons are provided on the housing 551. It is provided at 0.

[0455] The information terminal 5500 uses artificial intelligence by applying the chip according to one embodiment of the present invention. It can run applications that use artificial intelligence. For example, an application that recognizes a conversation and displays the conversation content on the display unit 5511. The display unit 5511 recognizes characters, figures, etc. input by the user on the touch panel. The application to be displayed on the display unit 5511 and the application to perform biometric authentication such as fingerprint or voiceprint are displayed. Applications, etc.

[0456] [Information terminal] FIG. 24B shows a desktop information terminal 5300. The information terminal 5300 includes a main body 5301 of the information terminal, a display 5302, and a keyboard. The present invention has a first embodiment and a second embodiment.

[0457] The desktop information terminal 5300 is similar to the information terminal 5500 described above. By applying the chip of the present invention, it is possible to execute applications using artificial intelligence. Examples of applications that use artificial intelligence include design support software. , writing correction software, automatic menu generation software, etc. By using the laptop 5300, it is possible to develop new artificial intelligence.

[0458] In the above description, a smartphone and a desktop information terminal are used as examples of electronic devices. As shown in Fig. 24(A) and (B), the smartphone and desktop The present invention can be applied to information terminals other than personal information terminals. Examples of information terminals other than personal information terminals include PDAs (Personal Digital Assistants). Assistant), notebook type information terminal, and workstation.

[0459] [electric appliances] FIG. 24(C) shows an electric refrigerator-freezer 5800, which is an example of an electric appliance. The refrigerator 5800 includes a housing 5801, a door for a refrigerator compartment 5802, a door for a freezer compartment 5803, etc. do.

[0460] By applying the chip of one embodiment of the present invention to the electric refrigerator-freezer 5800, artificial intelligence By utilizing artificial intelligence, The Electric Freezer Refrigerator 5800 is a refrigerator that can store food and drink. It also has a function to automatically generate menus based on the expiration date of ingredients, and a function to automatically generate menus based on the expiration date of ingredients, and the ... It can also have a function to automatically adjust the temperature to suit the ingredients being cooked.

[0461] In this example, an electric refrigerator-freezer is described as an electrical appliance, but other electrical appliances may also be used. Examples include vacuum cleaners, microwave ovens, electric ovens, rice cookers, water heaters, and induction cookers. , water servers, heating and cooling appliances including air conditioners, washing machines, dryers, Examples include audiovisual equipment.

[0462] [Game consoles] FIG. 24(D) shows a portable game machine 5200, which is an example of a game machine. The computer 5200 includes a housing 5201, a display unit 5202, a button 5203, and the like.

[0463] By applying a GPU or chip according to one embodiment of the present invention to the portable game console 5200, It is possible to realize a portable game machine 5200 with low power consumption. In addition, the low power consumption allows: Since heat generation from the circuit can be reduced, the circuit itself, peripheral circuits, and The impact on the module can be reduced.

[0464] Furthermore, by applying a GPU or chip according to one embodiment of the present invention to the portable game machine 5200, This makes it possible to realize a portable game machine 5200 having artificial intelligence.

[0465] Originally, the game progress, the behavior of the creatures that appear in the game, the phenomena that occur in the game, etc. The expression is determined by the program that the game has, but the portable game machine 520 By applying artificial intelligence to 0, it is possible to express things in ways that are not limited to game programs. For example, the questions asked by the player, the game progress, and events occurring during the game The timing of occurrence, the words and actions of the characters in the game, etc. are limited to the game program. It is possible to express the image by changing it without changing the color.

[0466] In addition, when playing a game that requires multiple players on the portable game machine 5200, the artificial intelligence You can create anthropomorphic game players, so you can make your opponents artificially intelligent. By making the game a game player, you can play the game by yourself.

[0467] In FIG. 24(D), a portable game machine is illustrated as an example of a game machine. The game machine to which the GPU or chip of the present invention is applied is not limited to this. Examples of game machines that apply PU or chips include home game machines, Arcade game machines installed in entertainment facilities (game centers, amusement parks, etc.), sports facilities Examples include pitching machines for batting practice that will be installed in the stadium.

[0468] [Mobile object] The GPU or chip of one embodiment of the present invention is used in automobiles, which are moving objects, and in the vicinity of the driver's seat of the automobile. can be applied to.

[0469] FIG. 24(E1) shows an automobile 5700 as an example of a moving object, and FIG. 24(E2) shows an automobile FIG. 24(E2) is a diagram showing the area around the windshield in the interior of a vehicle. The display panels 5701, 5702, and 5703 are attached to the board. Also shown is a pillar mounted display panel 5704.

[0470] The display panels 5701 to 5703 display a speedometer, a tachometer, It provides various information by displaying the distance traveled, fuel gauge, gear status, air conditioning settings, etc. In addition, the display items and layout displayed on the display panel can be customized by the user. It can be changed as needed to suit your taste, making it possible to enhance the design. The panels 5701 to 5703 can also be used as lighting devices.

[0471] The display panel 5704 includes an imaging device (not shown) provided on the outside of the automobile 5700. By projecting images from the pillars, it is possible to complement the blind spots that are blocked by the pillars. That is, an image from an imaging device provided on the outside of the automobile 5700 can be displayed. This makes it possible to compensate for blind spots and increase safety. By displaying the image, safety checks can be performed more naturally and without discomfort. The lamp 5704 can also be used as a lighting device.

[0472] The GPU or chip of one embodiment of the present invention can be applied as a component of artificial intelligence, e.g. For example, the chip can be used in the autonomous driving system of the 5700 automobile. The chip can be used in systems that provide road guidance, risk prediction, etc. Display panel 57 The display panels 5701 to 5704 are configured to display information such as road guidance and risk prediction. Good too.

[0473] In the above description, an automobile is used as an example of a moving object. For example, the moving object may be a train, a monorail, a ship, an aircraft (helicopter, etc.) These include drones, unmanned aerial vehicles (drones), airplanes, and rockets. Applying the chip of one embodiment of the present invention to a moving object and providing a system using artificial intelligence can be done.

[0474] [Broadcasting System] The GPU or chip according to one embodiment of the present invention can be applied to a broadcasting system.

[0475] FIG. 24(F) shows a schematic diagram of data transmission in a broadcasting system. Specifically, FIG. 24(F) shows how radio waves (broadcast signals) transmitted from a broadcast station 5680 are received by televisions in each home. The diagram shows the path of the signal until it reaches the TV receiving device (TV) 5600. The broadcast signal received by the antenna 5650 is transmitted to the receiving device (not shown). The signal is then transmitted to the TV5600 via

[0476] In FIG. 24(F), the antenna 5650 is a UHF (Ultra High Frequency) The antenna shown is a BS 110°CS Antennas and CS antennas can also be applied.

[0477] Radio waves 5675A and 5675B are broadcast signals for terrestrial broadcasting, and radio tower 5670 The received radio wave 5675A is amplified and radio wave 5675B is transmitted. By receiving radio waves 5675B with the Na5650, you can watch terrestrial TV broadcasts with the TV5600. The broadcasting system is not limited to the terrestrial broadcasting shown in FIG. 24(F), but may be a broadcasting system for people. It may also be satellite broadcasting using an industrial satellite, data broadcasting via optical fiber lines, or the like.

[0478] The above-mentioned broadcasting system applies the chip according to one embodiment of the present invention to broadcast programs using artificial intelligence. The broadcasting station 5680 transmits broadcast data to the TV 5600 in each home. When the encoder is turned on, the broadcast data is compressed, and the antenna 5650 receives the broadcast data. When the data is received, the decoder of the receiving device included in the TV 5600 converts the broadcast data into By using artificial intelligence, for example, the compression method of the encoder can be improved. In motion compensation prediction, which is one of the methods, the recognition of display patterns contained in the displayed image It is also possible to perform intraframe prediction using artificial intelligence. For example, low-resolution broadcast data is received and the high-resolution TV5600 displays that broadcast data. When displaying the image, the decoder restores the broadcast data by performing up-conversion, etc. Image interpolation can be performed.

[0479] The AI-based broadcasting system described above is expected to be a key component of the ultra-high definition television broadcasting system, which is expected to have an increasing amount of broadcast data. It is suitable for revision (UHDTV: 4K, 8K) broadcasting.

[0480] In addition, as an application of artificial intelligence on the TV5600 side, for example, A recording device having the above-mentioned function may be provided. By having artificial intelligence learn the user's preferences, the system can automatically record programs that match the user's preferences. It is possible to draw

[0481] Electronic device described in the present embodiment, functions of the electronic device, application examples of artificial intelligence, and effects thereof etc. can be appropriately combined with the descriptions of other electronic devices.

[0482] This embodiment may be implemented in appropriate combination with configurations described in other embodiments, examples, etc. It is possible to do so. EXAMPLES

[0483] In this embodiment, a semiconductor device according to one embodiment of the present invention is a transistor shown in FIG. A transistor having a similar structure to the transistor 10d (hereinafter referred to as sample 1) was fabricated. The semiconductor device was observed under a scanning transmission electron microscope (STEM). The results of observations using a 3D transmission electron microscope The results will be explained.

[0484] First, the structure of sample 1 will be described. As shown in FIG. 9 and FIG. 10, sample 1 is a substrate. An insulator 224 is disposed on a plate (not shown) and an oxide is disposed on the insulator 224. 230b, an oxide 230c disposed on the oxide 230b, and an oxide 230c disposed on the oxide 230c. 2, has an insulator 250 disposed thereon and a conductor 260 disposed on the insulator 250. Although not shown in FIGS. 9 and 10, Sample 1 is a transistor 2 shown in FIG. Similar to 00, the oxide 230a is between the insulator 224 and the oxide 230b. The conductor 260 is a laminated film of a conductor 260a and a conductor 260b.

[0485] As the insulator 224, silicon oxynitride having a thickness of 35 nm was used.

[0486] The oxide 230a is an In film having a thickness of 5 nm formed by DC sputtering. In addition, the oxide 230a was formed using In:Ga:Zn=1 The oxide target was 3:4 atomic ratio, and the deposition gas was oxygen gas at 45 sccm. The deposition pressure was set to 0.7 Pa (measured by a miniature gauge MG-2 manufactured by Canon Anelva). The film formation power was 500 W, the substrate temperature was 200° C., and the target-substrate The distance between the plates was 60 mm.

[0487] The oxide 230b is a 15 nm thick I film formed by DC sputtering. The oxide 230b was formed using an n-Ga-Zn oxide. An oxide target with an atomic ratio of 4:2:4.1 was used, and argon gas was used as the deposition gas. The deposition pressure was 0.7 Pa (Canon Anelva) using 30 sccm of nitrogen gas and 15 sccm of oxygen gas. The measurement was performed using a miniature gauge MG-2 manufactured by Epson. The temperature was set to 200° C., and the target-substrate distance was set to 60 mm.

[0488] The oxide 230c is a laminated film. The In-Ga-Zn oxide film was 5 nm thick and was formed by the etching method. The lower layer of the object 230c was formed using an oxide film of In:Ga:Zn=4:2:4.1 [atomic ratio]. A nitride target was used, and the deposition gas was oxygen gas at 45sccm, with the deposition pressure at 0. 7 Pa (measured using a miniature gauge MG-2 manufactured by Canon Anelva). The power was 500 W, the substrate temperature was 200°C, and the target-substrate distance was 60 mm. Ta.

[0489] In addition, a film formed by using a DC sputtering method as the upper layer of the oxide 230c is A 5 nm thick In-Ga-Zn oxide was used. The upper layer of the oxide 230c was formed using , using an oxide target with In:Ga:Zn=1:3:4 [atomic ratio], other film formation conditions was the same as oxide 230a.

[0490] The insulator 250 is made of silicon oxynitride having a thickness of 10 nm. Titanium nitride with a thickness of 5 nm was used as the conductor 260a. Tungsten was used as the conductor 260b. We used

[0491] The sample 1 having the above-mentioned configuration has a channel length of 200 nm and a channel width of 60 nm. Note that, like the transistor 200, the sample 1 has the following configuration in addition to the above: Further, the insulator 214, the insulator 216, the conductor 205, the insulator 222, the conductor 242, the insulator The insulating member 254, the conductor 240, the insulator 280, the insulator 274, and the insulator 281 are included. do.

[0492] The prepared sample 1 was subjected to accelerating voltage The voltage was set to 200 kV, and cross-sectional TEM images were taken in Cs-TEM mode. The photographed result is shown in FIG. 25. FIG. 25 shows the channel near the channel formation region of the oxide 230. This is a cross-sectional TEM image in the width direction.

[0493] Further, Fig. 26 shows enlarged cross-sectional TEM images of regions A to F shown in Fig. 25. Region A includes oxide 230c that is in contact with the top surface of oxide 230b. Region B includes oxide Region C includes oxide 230c in contact with the top end of oxide 230b. Region D includes an oxide 230c that is in contact with the side of the insulator 224. Region E includes the oxide 230c that is in contact with the top surface of the insulator 224. Region F also includes oxide 230b.

[0494] In the regions A to E shown in FIGS. 25 and 26(A) to (E), the oxide 230 c was formed with a very thin film thickness of about 2 nm to 5 nm. However, 26(E), the oxide 230c has a layered structure in all regions. The CAAC-OS is formed. Here, the arrows shown in FIG. 26(A) to FIG. 26(E) indicate , the arrow indicates a direction approximately perpendicular to the oxide film 230c. This roughly coincides with the normal direction of the layered crystal, that is, the c-axis direction of the CAAC-OS. The CAAC-OS of the oxide 230c is formed on the surface on which the oxide 230c is formed or on the surface of the oxide 230c. It can be seen that the nanoparticles are aligned along the unevenness of the film surface.

[0495] As shown in FIG. 25 and FIG. 26(F), the layered crystals in the region F are also insulating. The oxide 230b is arranged approximately parallel to the upper surface of the edge 224. It can be seen that the oxide 230b is arranged along the surface on which it is formed or along the film surface.

[0496] From the above, in the sample 1, the region F corresponding to the region 54 in FIG. 10(B) has a crystal structure shown in FIG. 10(E), and a region C corresponding to the region 55 in FIG. It is assumed that the sample 1 has a crystal structure. Therefore, the bands of the sample 1 are roughly the same as those shown in FIG. Since the model in the diagram is satisfied, it is believed that the suppression of carrier transmission can be prevented. can be.

[0497] The configurations and methods shown in the present embodiment are at least partially described in this specification. The present invention can be implemented in appropriate combination with the embodiment modes and examples. EXAMPLES

[0498] In this example, the crystal structure of a metal oxide according to one embodiment of the present invention was evaluated. Specifically, a high-angle scattering annular dark-field scanning transmission electron microscope (STEM) was used to measure the surface roughness of the sample 2 on which the metal oxide was formed. Mirror(HAADF-STEM:High-Angle Annular Dark Fie ld Scanning Transmission Electron Micros cope images and energy dispersive X-ray spectroscopy (EDX) Elemental analysis was performed using ispersive X-ray spectroscopy. Ta.

[0499] First, a method for preparing Sample 2 will be described.

[0500] As metal oxides, sputtered onto yttria-stabilized zirconia (YSZ) substrates A 100 nm thick In-Ga-Zn oxide film was formed by the method. For the deposition of the oxide, an oxide target with an atomic ratio of In:Ga:Zn=4:2:4.1 was used. The oxygen gas flow rate was set to 30 sccm, the pressure to 0.4 Pa, and the DC power supply to 200 W. The substrate temperature was set to 300°C.

[0501] Next, a heat treatment was performed. The heat treatment was performed in an oxygen-containing atmosphere at a temperature of 1200° C. for 1 Time processing was performed.

[0502] In this manner, sample 2 was prepared.

[0503] A HAADF-STEM image of the prepared sample 2 was acquired. Acquisition of HAADF-STEM image An atomic resolution analytical electron microscope JEM-ARM200F manufactured by JEOL Ltd. was used for the analysis.

[0504] The brightness of a point observed in a HAADF-STEM image is the atomic number of the atom corresponding to that point. In other words, the points corresponding to atoms with higher atomic numbers are whiter. In In-Ga-Zn oxide, the atomic number is In. The largest is Ga and Zn, and the smallest is O. Therefore, the point corresponding to In is The brightness of the points corresponding to Ga and Zn is higher than that of the points corresponding to In. The brightness of the points corresponding to O is very low and appears darker than the points corresponding to In. Because the O is so low, it can be difficult to identify its location.

[0505] The cross-sectional HAADF-STEM image of sample 2 is shown on the right side of Figure 27. The normal direction of the oxide formation surface (YSZ substrate surface), and the left-right and normal directions of the paper. is a direction parallel to the surface on which the metal oxide is formed (the surface of the YSZ substrate).

[0506] The cross-sectional HAADF-STEM image shown on the right side of Figure 27 shows that the metal oxide formed on sample 2 It was confirmed that a layered structure was formed. Also, points with different brightness were observed. The points with relatively high brightness correspond to In, and the points with relatively low brightness correspond to Ga or It is estimated that the point corresponds to Zn. In addition, there are points with similar brightness in the left and right directions of the paper. The relatively bright spots lined up in the left and right direction of the paper were In The relatively low brightness points aligned horizontally on the page are the (Ga,Zn)O layer. In addition, it is estimated that the relatively bright points are aligned in a row on the left and right of the paper, and the relatively bright points are aligned in a row on the right and left of the paper. Rows of low intensity dots arranged horizontally on the paper surface were observed alternating with rows of low intensity dots arranged vertically on the paper surface. Therefore, in the metal oxide formed in sample 2, the InO layer and the (Ga, Zn)O layer are stacked. It was confirmed that a layered structure was formed.

[0507] Next, elemental analysis of sample 2 was performed using EDX. The process of measuring the area while doing so and evaluating it two-dimensionally is sometimes called EDX area analysis. From the EDX surface analysis, data on linear regions are extracted, and the distribution of atomic concentrations within the regions is evaluated. Evaluating the structure of a substance using EDX is sometimes called EDX line analysis.

[0508] The elemental analysis equipment used was an energy dispersive X-ray analyzer (JED) manufactured by JEOL Ltd. A Si drift detector was used to detect the X-rays emitted from the sample. Used.

[0509] The cross-sectional HAADF-STEM image shown on the right side of Figure 27 was taken in the same area. The results of the EDX analysis are shown on the left side of FIG. 27. In the left side of FIG. is the normal line of the surface on which the metal oxide is to be formed (YSZ substrate surface) from the reference position (0 nm). The horizontal axis indicates the distance in the direction (nm). Shows the composition ratio [atomic%].

[0510] As shown in Figure 27, the row with relatively high brightness points aligned horizontally on the page has the highest ratio of In. The lower brightness points are on the left and right sides of the page. The columns aligned in the direction of the SiO2 layer are considered to be (Ga,Zn)O layers because the ratio of Ga or Zn is high. In addition, the relatively low brightness points lined up in the left and right directions of the paper also indicate that the 15ato The detection of about .mic% In indicates that In is mixed in the (Ga,Zn)O layer. It was confirmed that:

[0511] From the above, in the In-Ga-Zn oxide, the InO layer and the (Ga, Zn)O layer are stacked. A layered structure was confirmed.

[0512] The configurations, methods, etc. shown in the present embodiment may be at least partially implemented in other embodiments described in this specification. The present invention can be implemented in appropriate combination with the embodiments and examples. EXAMPLES

[0513] In this example, the operating frequency was estimated for the DOSRAM shown in the fourth embodiment.

[0514] "Allowable voltage fluctuation," one of the specifications required for DOSRAM, is the capacity of DOSRAM. This is the tolerance for the amount of change in the voltage applied to the capacitance element after data is written. The "data retention time" of AM is the amount of voltage fluctuation applied to the capacitance element of DOSRAM. This is the time required to reach the allowable voltage fluctuation. In this embodiment, the "allowable voltage fluctuation" is set to 0. 2V, and the "data retention time" is the voltage applied to the capacitance element (retention capacity 3.5fF) The time required for the voltage to drop by 0.2 V from the state after writing is set as the time. If the data retention time of OSRAM is one hour, the voltage applied to the capacitance element of the DOSRAM is This means that it takes 1 hour for the voltage to drop by 0.2V after data is written. .

[0515] The data retention time of DOSRAM is determined by the cutoff voltage of the transistors in the DOSRAM. Here, the cut-off current of a transistor depends on the magnitude of the gate current of the transistor. Port voltage V G = 0V drain current I D (Hereafter, Icut.) For example, the data retention characteristics of the DOSRAM can be If the data retention time of DOSRAM depends only on the size of Icut of the DOS register, It is inversely proportional to the size of Icut of the transistors in the SRAM.

[0516] When the Icut of the transistors in the DOSRAM is known, the data of the DOSRAM is The data retention time is the amount of charge lost from the capacitance element during data retention (the retention capacitance of the capacitance element (3. 5fF) and the voltage drop across the capacitance element (0.2V), which is equivalent to 0.7fC. It can be calculated by dividing by Icut. By setting the retention time and dividing the charge amount 0.7 fC by the retention time, DOSRAM Estimate the value of Icut required for the transistor (hereinafter referred to as Icut0). If the retention time goal is one hour, the Icut required for the transistor is is about 200zA (200×10 -21 A). Icut0 shown in Figure 28 is 200z By adjusting the back gate voltage so that the value becomes A, the device has high data retention characteristics and This embodiment provides a DOSRAM having a high operating frequency over a wide temperature range. We evaluated the relationship between the backgate voltage and the operating frequency of DOSRAM.

[0517] In estimating the operating frequency of DOSRAM, the transistors shown in Figs. A transistor having a configuration similar to that of the transistor 10d (hereinafter referred to as sample 3) was fabricated, and its The parameters required for the estimation were extracted from the electrical characteristics. Assuming transistor 10d as transistor M1, estimate the operating frequency of DOSRAM. I did.

[0518] First, the structure of sample 3 will be described. As shown in FIGS. 9 and 10, sample 3 is a substrate. An insulator 224 is disposed on a plate (not shown) and an oxide is disposed on the insulator 224. 230b, an oxide 230c disposed on the oxide 230b, and an oxide 230c disposed on the oxide 230c. 2, has an insulator 250 disposed thereon and a conductor 260 disposed on the insulator 250. Although not shown in FIGS. 9 and 10, Sample 3 is a transistor 2 shown in FIG. Similar to 00, the oxide 230a is between the insulator 224 and the oxide 230b. The conductor 260 is a laminated film of a conductor 260a and a conductor 260b.

[0519] As the insulator 224, silicon oxynitride having a thickness of 35 nm was used.

[0520] The oxide 230a is an In film having a thickness of 5 nm formed by DC sputtering. In addition, the oxide 230a was formed using In:Ga:Zn=1 The oxide target was 3:4 atomic ratio, and the deposition gas was oxygen gas at 45 sccm. The deposition pressure was set to 0.7 Pa, the deposition power was set to 500 W, and the substrate temperature was set to 200° C. The distance between the target and the substrate was 60 mm.

[0521] The oxide 230b is a 20 nm thick I film formed by DC sputtering. The oxide 230b was formed using an n-Ga-Zn oxide. An oxide target with an atomic ratio of 4:2:4.1 was used, and argon gas was used as the deposition gas. The deposition pressure was 0.7 Pa, and the deposition power was 5 The power was set to 100 W, the substrate temperature was set to 200° C., and the distance between the target and the substrate was set to 60 mm.

[0522] The oxide 230c is a 5 nm thick In film formed by DC sputtering. In addition, the oxide 230c was formed using In:Ga:Zn=4 The oxide target was 2:4.1 atomic ratio, and the deposition gas was oxygen gas for 45 s. ccm, the deposition pressure was 0.7 Pa, the deposition power was 500 W, and the substrate temperature was 130 ° C., and the distance between the target and the substrate was 60 mm.

[0523] The insulator 250 is made of silicon oxynitride having a thickness of 8 nm. Titanium nitride having a thickness of 10 nm was used as the conductor 260b. We used

[0524] The sample 3 having the above-mentioned configuration has a channel length of 0.37 μm and a channel width of 0.24 μm. Note that, like the transistor 200, the sample 3 is a transistor having the above structure. In addition, the insulator 214, the insulator 216, the conductor 205, the insulator 222, the conductor 24 2, insulator 254, conductor 240, insulator 280, insulator 274, insulator 281, etc. do.

[0525] Next, in sample 3, the I D -V G Measurements were carried out. D -V G measurement The determination is made based on the drain potential V D to +1.08V, and the source potential V S to 0V, Terminal potential V G The back gate voltage was swept from -1.0 V to +3.3 V. V BG The measurement was performed at -7.1 V. The measurement temperatures were -40°C, 27°C, and 85°C. Specifically, a 5-inch square substrate on which a transistor to be measured is formed is heated to each of the above temperatures. The I of the transistor is measured while it is fixed on the thermo chuck. D -V G Measurements were carried out. Moreover, measurements were performed on three elements for each measurement temperature.

[0526] Obtained I D -V G From the curve, the transistor shift voltage (Vsh) and subthreshold The threshold swing value (Svalue) was calculated. Vsh is the I D - V G The tangent at the point on the curve where the slope is maximum is I D =1pA direct current V crossing a line G Also, Svalue is the drain current at a constant drain voltage. This refers to the amount of change in gate voltage in the subthreshold region that changes the current by one order of magnitude.

[0527] As described in the second embodiment, the transistor 10d has a channel formation region formed of a metal oxide A transistor using a metal oxide for the channel formation region is, for example, Compared to transistors that use Si in the junction formation region, the leakage current in the non-conducting state is extremely low. Therefore, the transistor that uses metal oxide for the channel formation region has a In the transistor 10d, Icut may be difficult to detect. Since it was difficult to measure the actual D -V G Vsh and Sval obtained from the curve From ue, Icut was estimated by extrapolation using equation (1). So the off-state current of the transistor is V G According to Svalue, I D is assumed to be monotonically decreasing.

[0528]

number

[0529] Next, the I D -V S Measurements were taken.

[0530] Here, a method for estimating the DOSRAM operating frequency will be described. The frequency is the reciprocal of the data write cycle time of DOSRAM. The data write cycle time is set based on the charging time of the capacitance element of the DOSRAM. In this embodiment, the data write cycle time of the DOSRAM is The time equivalent to 40% of the DOSRAM operating frequency (the inverse of the DOSRAM operating frequency) is The time required for the capacitance element to charge was set to 1.

[0531] The operating frequency of DOSRAM depends on the charging time of the capacitance element of DOSRAM. Therefore, when estimating the operating frequency of DOSRAM, the first thing to consider is the capacitance of the DOSRAM. In this embodiment, the charge time of the DOSRAM is known in advance. The state in which a potential of 0.52V or more is applied to the storage capacitor (3.5fF) is called the "charging" state. Therefore, in this embodiment, the data write operation of the DOSRAM is defined as "a state in which the data is written to the DOSRAM". The time from when the DO operation starts until the potential applied to the capacitance element reaches 0.52 V is This corresponds to the charging time of the capacitive element in the SRAM.

[0532] The charging time of the capacitance element of DOSRAM is , I of the transistor in DOSRAM D Therefore, in this embodiment, It is assumed that the transistors in the DOSRAM are affected when writing data to the DOSRAM. The potential (see FIG. 29A) of the transistor according to one embodiment of the present invention (L / W=0. 37 / 0.24μm) to reproduce the DOSRAM data write operation. At this time, the I D FIG. 29(A) shows the capacitance element of FIG. It is assumed that data is written to CA through transistor M1. D is the drain. where G represents the gate and S represents the source. The source potential of transistor Tr1 (the voltage applied to the capacitance element Cs) is V S By turning on the transistor Tr1, And the current I D Specifically, the gate voltage of the transistor The drain potential Vg is set to +2.97V, the drain potential Vd is set to +1.08V, and the source potential V S From 0V The transistor ID Measurements were performed. Backgate voltage V BG The measurement was performed at -7.1 V. The measurement was performed at three temperatures: -40°C, 27°C, and 85°C.

[0533] The DOSRAM has a channel length (L) of 60 nm and a channel width (W) of 60 nm. A configuration having a transistor and a capacitance element with a storage capacitance of 3.5 fF was assumed. I obtained from transistor 10d (L / W=0.37μm / 0.24μm) D The value of The size of the transistor (L / W=60 / 60nm) assumed to be used in DOSRAM is used as a compensation. Corrected.

[0534] DOSRAM starts charging and V S is the write decision voltage V CS Charging is complete when The time at this time is the charging time t W (See FIG. 29(B)). The charge stored in the capacitance element of the storage capacitance Cs [F] is Q [C], and the charging time is t W [sec ], and the potential applied to the capacitance element by charging is V CS (=Vs) [V], DOSRAM has The drain current of the transistor is I D When [A] is used, the following formula is used between each parameter. The relationship (2) holds.

[0535]

number

[0536] By modifying equation (2), the charging time t W The following formula (3) (see Figure 29(C)).

[0537]

number

[0538] In this embodiment, Cs in formula (3) is 3.5 fF, V CS +0.52V to the I D -V S The measured I D Substituting the above, the charging time of the capacitance element of the DOSRAM is t W Calculate Ta.

[0539] The operating frequency f and charging time t of the storage device 1400 W The relationship can be expressed by equation (4). .

[0540]

number

[0541] In formula (4), A is a coefficient. Since the time required for writing is estimated to be 40%, in this embodiment, coefficient A is set to 0.4. The operating frequency f was calculated.

[0542] In sample 3, the D when the power supply voltage was 3.3 V and the back gate voltage was -7.1 V The operating frequency of the OSRAM is shown in Fig. 30 and Fig. 31. In Fig. 30, the horizontal axis is the temperature (T The vertical axis indicates the operating frequency [MHz]. In 1, the horizontal axis is the inverse of temperature (1000 / Temperature) [K -1 ] The horizontal axis indicates the operating frequency [MHz]. As shown in Figs. 30 and 31, the higher the temperature, the It was confirmed that the operating frequency increases as the operating frequency increases. By extrapolating the wave number, it is estimated that the operating frequency at 200°C will be 1GHz or more. It was stolen.

[0543] From the above, we can say that metal oxide is used for the channel formation region of the transistor in DOSRAM. It was found that the higher the temperature, the higher the operating frequency of the DOSRAM.

[0544] The configurations, methods, etc. shown in the present embodiment may be at least partially implemented in other embodiments described in this specification. The present invention can be implemented in appropriate combination with the embodiments and examples. EXAMPLES

[0545] In this example, we evaluated the temperature dependence of the carrier concentration and Hall mobility of metal oxides. Specifically, the Hall effect was measured at different temperatures for sample 4, which was a metal oxide film. The carrier concentration and Hall effect of the metal oxide at each temperature are measured using the results. The mobility was calculated.

[0546] Here, the Hall effect measurement is performed by applying a magnetic field perpendicular to the direction of the current to an object through which current is flowing. By applying a magnetic field, an electromotive force appears in a direction perpendicular to both the current and the magnetic field. This is called the Hall effect. This method uses the results to measure electrical properties such as carrier density, mobility, and resistivity. Here, the Hall effect was measured using the Van der Pauw method. To measure the effectiveness, ResiTest manufactured by Toyo Corporation was used.

[0547] First, a method for preparing Sample 4 will be described.

[0548] Silicon nitride is deposited on a glass substrate to a thickness of 400 nm. A silicon oxynitride film was formed to a thickness of 50 nm.

[0549] Next, a sputtered metal oxide film was applied to the silicon oxynitride film. A 35 nm thick In-Ga-Zn oxide film was formed by the annealing method. The oxide target with the atomic ratio of In:Ga:Zn=1:1:1 was used for the deposition of the oxide. The argon gas flow rate is 20sccm, the oxygen gas flow rate is 10sccm, and the pressure is 0. The pressure was 4 Pa, the DC power supply was 200 W, and the substrate temperature was 300°C.

[0550] Next, a heat treatment was performed. The heat treatment was performed in a nitrogen-containing atmosphere at a temperature of 450° C. for 1 hour. Then, the material was treated for 1 hour at 450°C in an atmosphere containing oxygen and nitrogen. went.

[0551] In this manner, sample 4 was prepared.

[0552] For the prepared sample 4, the temperature range from 159°C to 239°C in increments of about 10°C was All efficacy measurements were performed.

[0553] FIG. 32(A) shows the change in carrier concentration of the metal oxide with respect to the measurement temperature. , the reciprocal of the measured temperature (1000 / Temperature) [K -1 ], and the vertical axis indicates the Carrier concentration of metal oxide [cm -3 ] is indicated.

[0554] From FIG. 32(A), the smaller the reciprocal of the measurement temperature (the higher the measurement temperature), the greater the catalytic activity of the metal oxide. It was found that the carrier concentration was high.

[0555] FIG. 32(B) shows the transition of the Hall mobility of the metal oxide with respect to the measurement temperature. The horizontal axis is the reciprocal of the measured temperature (1000 / Temperature) [K -1 ] and vertical The axis represents the Hall mobility of the metal oxide [cm 2 / (V s)].

[0556] From Figure 32(B), the smaller the inverse of the measurement temperature (the higher the measurement temperature), the greater the H It was found that the all mobility increased.

[0557] From the above, it was confirmed that the higher the temperature, the higher the mobility of metal oxides tends to be.

[0558] The configurations, methods, etc. shown in the present embodiment may be at least partially implemented in other embodiments described in this specification. The present invention can be implemented in appropriate combination with the embodiments and examples. [Explanation of symbols]

[0559] 10: transistor, 10a: transistor, 10b: transistor, 10c: transistor sta, 10d: transistor, 51: region, 52: region, 53: region, 54: region, 55 : Region, 100: Capacitive element, 110: Conductor, 112: Conductor, 120: Conductor, 130 : insulator, 140: insulator, 150: insulator, 200: transistor, 200A: trans 200B: transistor, 200C: transistor, 205: conductor, 210: Insulator, 212: Insulator, 214: Insulator, 216: Insulator, 218: Conductor, 222: Insulator, 224: insulator, 230: oxide, 230a: oxide, 230b: oxide, 23 0c: oxide, 230c1: oxide, 230c2: oxide, 231: region, 231a: region area, 231b: area, 234: area, 240: conductor, 240a: conductor, 240b: conductor conductor, 241: insulator, 241a: insulator, 241b: insulator, 242: conductor, 242 a: conductor, 242b: conductor, 243: region, 243a: region, 243b: region, 24 4a: Barrier film, 244b: Barrier film, 250: Insulator, 254: Insulator, 254a: Insulator Edge, 254b: insulator, 254c: insulator, 260: conductor, 260a: conductor, 26 0b: conductor, 273: insulator, 274: insulator, 280: insulator, 280a: insulator, 280b: insulator, 281: insulator, 282: insulator, 300: transistor, 311: Substrate, 313: semiconductor region, 314a: low resistance region, 314b: low resistance region, 315: insulating region Insulator, 316: conductor, 320: insulator, 322: insulator, 324: insulator, 326: insulator 328: conductor, 330: conductor, 350: insulator, 352: insulator, 354: insulator Insulator, 356: conductor, 400: transistor, 405: conductor, 424a: insulator, 4 24b: insulator, 430c: oxide, 431a: oxide, 431b: oxide, 432a: Oxide, 432b: oxide, 440: conductor, 440a: conductor, 440b: conductor, 4 42: conductor, 442a: conductor, 442b: conductor, 450: insulator, 460: conductor , 460a: conductor, 460b: conductor, 1001: wiring, 1002: wiring, 1003: Wiring, 1004: Wiring, 1005: Wiring, 1006: Wiring, 1007: Wiring, 1008: Wiring, 1009: Wiring, 1010: Wiring

Claims

1. A crystalline metal oxide; A transistor having a gate, a source, and a drain, the crystalline metal oxide has a first layer and a second layer; The first layer has a wider band gap than the second layer, the first layer and the second layer form a crystal lattice; A transistor in which, as the temperature increases, the crystalline metal oxide reduces the c-axis thickness of the second layer.

2. In claim 1, the crystalline metal oxide comprises a first metal oxide, a second metal oxide on the first metal oxide, and a third metal oxide on the second metal oxide; The first metal oxide, the second metal oxide, and the third metal oxide each have the first layer and the second layer.

3. In claim 2, A transistor in which the first layer of the second metal oxide and the second layer of the second metal oxide are each arranged approximately parallel to a surface on which the second metal oxide is formed.

Images