METAL ZERO POWER GROUND STUB ROUTE FOR REDUCING CELL AREA AND IMPROVING CELL PLACEMENT AT CHIP LEVEL

Abstract

Efficient method and system for laying out power grid connections for standard cells - Patents.com In one embodiment, a standard cell includes power and ground posts in Metal 0 130. The Metal 0 posts do not include vias to upper metal layers. Some variations of the standard cell have the power and ground posts routed in Metal 0 to the bounding edges of the standard cell. The layout rules are modified to allow for this type of routing. The power and ground posts in Metal 0 are connected by joining to the power and ground posts in Metal 0 of adjacent cells. The place-and-route tool does not need to perform an additional routing step after placing the cell. In other variations, the power and ground posts are not routed to the bounding edges, and the place-and-route tool routes the power and ground connections in Metal 0 between the standard cell and the adjacent cell.

Description

Background Art

[0001] As semiconductor manufacturing processes have advanced and the on-die geometric dimensions have shrunk, semiconductor chips provide more functions and performance while consuming less space. Although many advancements have been made, design problems still occur in modern techniques of processing and integrated circuit design that limit the potential benefits. For example, capacitive coupling, electromigration, leakage current, and process yield are some of the problems that affect the placement of devices and the routing of signals across the entire die of a semiconductor chip. Therefore, these problems can delay the completion of the design and potentially affect the time to market.

[0002] To shorten the design cycle of semiconductor chips, manual full-custom design is automated as much as possible. Designers provide descriptions of functional units or composite gates in high-level description languages such as Verilog and VHDL. The synthesis tool receives the logic description and provides a logic netlist. The logic netlist is used by a placement and routing (PNR) tool to provide a physical layout. The placement and routing tool uses a cell layout library to provide a physical layout.

[0003] A cell layout library contains multiple standard cell layouts to provide various functions used in semiconductor chips. In some cases, standard cell layouts are manually generated. Therefore, each new standard cell layout or the original standard cell layout being modified is manually generated. In other cases, cell generation is automated by adjusting the rules used by the place and route tool. However, the automated process may not meet the rules directed towards performance, power consumption, signal integrity, process yield, local and external signal routing including internal cross-coupled connections, cell height and width dimensions to match other cells, pin access, power rail design, etc. Therefore, designers manually generate these cells to improve the results of various characteristics or to rewrite the rules of the place and route tool.

[0004] Generally, a standard cell layout uses at least one power rail for power supply voltage connections, also known as the VDD power rail, and one power rail for ground connections, also known as the VSS power rail. In some cases, the power and ground rails use relatively long wires that utilize multiple metal layers (e.g., horizontal metal 0, vertical metal 1, horizontal metal 2, vertical metal 3, etc.) in addition to the corresponding vias. In other cases, fixed location posts are used within the standard cell to make power and ground connections.

[0005] Before power and ground connections are generated, some layout cell libraries within the layout cell library must be expanded to create space for connections and satisfy several design rule checks (DRCs). Expanding the cell layout increases the on-die area consumed by these cells. If a significant portion of the chip design uses these cells, the overall chip area will increase considerably.

[0006] Considering the above, an efficient method and system for laying out power grid connections for standard cells is desired.

[0007] The advantages of the methods and mechanisms described herein can be better understood by referring to the following description in conjunction with the accompanying drawings. [Brief explanation of the drawing]

[0008] [Figure 1] This is a generalized diagram of a plan view of a standard cell layout for an inverter. [Figure 2] This is a generalized plan view of a standard cell layout of an inverter arranged with adjacent compound logic gates. [Figure 3] This is a generalized plan view of a standard cell layout of an inverter having power and ground connections for metal 1 and metal 2. [Figure 4] This is a generalized diagram of a plan view of a standard cell layout for an inverter. [Figure 5] This is a generalized diagram of how to generate power grid connections for a standard cell layout. [Figure 6] This is a generalized diagram of how to generate power grid connections for a standard cell layout. [Modes for carrying out the invention]

[0009] While the present invention is open to various modifications and alternative forms, specific embodiments are shown in the drawings as examples and described in detail herein. However, it should be understood that the drawings and their detailed description are not intended to limit the present invention to any specific form disclosed, but rather, the present invention encompasses all modifications, equivalents, and alternatives that fall within the scope of the invention as defined by the appended claims.

[0010] The following description includes many specific details to provide a full understanding of the methods and mechanisms presented herein. However, those skilled in the art should recognize that various embodiments may be carried out without these specific details. In some examples, well-known structures, components, signals, computer program instructions and techniques are not shown in detail to avoid obscuring the approach described herein. For simplicity and clarity of explanation, it will be understood that the elements shown in the figures are not necessarily drawn to scale. For example, the dimensions of some elements may be exaggerated in comparison to others.

[0011] Systems and methods for laying out power grid connections for standard cells are conceivable. In various embodiments, a cell includes one or more input nodes in metal 1, one or more output nodes in metal 1, and each of the power posts and ground reference posts in metal 0 below the posts in metal 1. In one embodiment, the cell is a standard cell from a cell layout library. In another embodiment, the cell is a custom cell generated for a specific area of ​​chip design. The power posts and ground posts do not include vias to the upper metal layer. In some embodiments, the power posts and ground posts in metal 0 are routed to the boundary edge of the cell. The layout rules are modified to allow this type of routing. The power posts and ground posts in metal 0 are connected by abutments to the power posts and ground posts in metal 0 of adjacent cells. The place and route tool does not require any further routing steps after the cell has been placed.

[0012] In other embodiments, power and ground connections are routed in metal 0 from the cell boundary edge to a threshold distance. The placement and routing tool places the cell next to an adjacent cell that has power and ground posts in metal 0 aligned with the tracks of power and ground posts in metal 0 within that cell. After placement, the placement and routing tool routes metal 0, rather than metal 2, between the cell and the adjacent cell. In various embodiments, cells selected to have power and ground posts in metal 0 without vias to the upper metal layer include cells having fewer metal gates than the sum of one or more input nodes, one or more output nodes, and power and ground connections.

[0013] Referring to Figure 1, generalized block diagrams of the plan views of cell layouts 102 and 104 are shown. Here, for ease of illustration, the active regions are not shown in cell layouts 102 and 104. In the illustrated embodiment, cell layout 102 for an inverter without metal 1 (i.e., M1) posts for power and ground connections is shown on the left. Cell layout 102 has an input pin labeled "IN" on metal 1 (M1) 150, an output pin labeled "OUT" on M1 150, a power pin labeled "VDD" on metal 0 (M0) 130, and a ground reference pin labeled "GND" on M0 130. Cell layout 102 does not include posts for power and ground connections on M1 150.

[0014] The cell layout 104 shown on the right is another embodiment of an inverter in which metal 1(M1) posts for power and ground connections are not provided. Cell layout 104 utilizes the same number of vertical metal gates 110 as cell layout 102. In some embodiments, cell layouts 102 and 104 are part of a cell layout library. In other embodiments, cell layouts 102 and 104 are custom layout cells for specific areas of chip design. A cell layout of an inverter with an inefficient arrangement of metal 1(M1) posts for power and ground connections is shown in the standard cell layout 300 (Figure 3) described later, which has additional metal gates 110 to provide area for adding posts to M1 150.

[0015] In the illustrated embodiment, each of cell layouts 102 and 104 has posts in metal 0 130 that do not include vias to the upper metal layer. Global routing of cell layouts 102 and 104 in a floor plan with adjacent cells typically uses metal 0 130 rather than metal 2 170. Although cell layout 102 includes routing for power connections with adjacent cells, cell layout 104 has the same amount of on-die area as cell layout 102. Typically, vertical metal 1(M1) 150 is used for routing to provide flexible connections to horizontal metal 2(M2) 170 to generate power and ground connections with adjacent cells. However, here, cell layout 104 does not use either vertical posts in metal 1 150 or horizontal posts in metal 2 170 for power connections. In the case of cell layout 104, the power posts within M0 130 of cell layout 104 extend to the boundary edge of the inverter's cell layout 104, enabling routing to adjacent cells within M0. By using the M0 extension 132, in one embodiment, routing in M0 130 is achieved by connecting to the power reference post within M0 130 of the adjacent cell.

[0016] The layout design rule check (DRC) is modified to allow the use of the M0 extension 132. The software layout tool that performs the layout modifies the DRC. The place and route tool places the cells so that they join with each other, but does not verify the layout within the cells. Typically, the horizontal route of metal 0 130 terminates before the cell boundary edge and at least a non-zero threshold distance from the cell boundary edge.

[0017] While cell layout 104 illustrates an inverter layout technique, this technique can be used in other standard cells to suppress the increase in on-die area when power connections are added. For example, the layout technique can be used in any standard cell in a layout library that has a layout with a pin count greater than the number of metal gates 110. In other words, the layout technique can be used in any standard cell that has one or more input nodes, one or more output nodes, and a number of metal gates less than the sum of the power and ground connections.

[0018] At the top of each of the cell layouts 102 and 104, p-type metal oxide semiconductor (PMOS) field-effect transistors (FETs) (pfets) are arranged. N-type MOS FETs (nfets) are arranged at the bottom of each of the cell layouts 102 and 104. Thus, each of the cell layouts 102 and 104 uses a power pin labeled "VDD" at the top and a ground pin labeled "GND" at the bottom. In some embodiments, devices of the standard cell layout 100 are manufactured by any of the following techniques: immersion lithography, double patterning, extreme ultraviolet lithography (EUV), and digitally assembled (DSA) lithography. In some embodiments, EUV technology offers more flexibility for via and contact modules compared to other techniques.

[0019] In various embodiments, the devices (transistors) within cell layouts 102 and 104 are non-planar devices (transistors). Non-planar transistors are a recent development in semiconductor processing to reduce short-channel effects. Tri-gate transistors, Finn field-effect transistors (FETs), and gate-all-around (GAA) transistors are examples of non-planar transistors. As illustrated, cell layouts 102 and 104 use a vertical metal gate 110, vertical trench silicide contacts 120 for the source and drain regions, a horizontal metal O(M0) 130 for local interconnection, a contact 140 for connecting the metal gate 110 to the metal O 130, and a contact 142 for connecting the trench silicide contact 120 to the metal O 130.

[0020] In various embodiments, titanium nitride (TiN) is used for the metal gate 110. In the manufacturing process, the metal gate 110 is provided around the nanowires of the non-planar transistor by a chemical-mechanical polishing step following deposition. Cell layouts 102 and 104 use metal 1(M1)150 for vertical local interconnects and vias 152 to connect horizontal interconnect metal 0 130 to vertical interconnect metal 1 150. Vias 160 are used to connect vertical metal 1 150 to horizontal metal 2 170. However, cell layouts 102 and 104 do not use vias 160 or metal 2 170.

[0021] As described above, cell layout 102 has four pins: the input pin "IN" of metal 1 (M1) 150, the output pin "OUT" of M1 150, the power supply voltage pin "VDD" of metal 0 (M0) 130, and the ground reference pin "GND" of M0 130. Cell layout 102 has three metal gates 110. The ratio of the total number of pins to the metal gates 110 is greater than 1, since there are four pins for three metal gates 110. Routing the power reference pin to adjacent cells is still required for cell layout 102. Typically, the power reference pin is routed within M1 150. For example, a software place-and-route tool places a copy of cell layout 102 onto the die of a chip design, then places a vertical post within metal 1 150 for VDD, places vias 160 to connect the vertical power post of metal 1 150 to horizontal metal 2 170, and then routes the power horizontal metal 2 170 to the power horizontal metal 2 170 of an adjacent cell. Similar steps are performed by the place-and-route tool for ground reference connections. However, standard cells such as cell layout 102 do not have enough vertical metal 1 (M1) channels to add power posts to metal 1 150 without expanding the layout and on-die area by adding extra metal gates 110 to create extra vertical M1 channels.

[0022] Cell layout 104, like cell layout 102, has four pins: an input pin "IN" for metal 1 (M1) 150, an output pin "OUT" for M1 150, a power supply voltage pin "VDD" for metal 0 (M0) 130 extending to the cell boundary, and a ground reference pin "GND" for M0 130 extending to the cell boundary. Cell layout 104 also has three metal gates 110. The ratio of the total number of pins to the metal gates 110 is greater than 1, since there are four pins for three metal gates 110. Routing the power reference post to an adjacent cell in cell layout 104 is done by extending the M0 post 132 to the cell boundary, rather than using horizontal metal 1 170 to route the power reference post to an adjacent cell.

[0023] Since the power supply posts of M1 150 are not added to the cell layout 104 for routing the power reference pins labeled "VDD" and "GDD", an additional metal gate 110 is not added to expand the on-die area of the cell layout 104 to include the power supply posts of M1 150. When vertical posts of M1 150 are added to connect the power to the horizontal posts of Metal 2 170, an additional metal gate 1110 is added to meet the design rules. The design rules prevent the vertical posts of M1 150 from being within the threshold distance of the cell boundary edge. Further, the vertical posts of M1 150 need to be within the threshold distance of the vertical metal gate 110. The design rules are set by the manufacturing process. The additional metal gate 110 provides an additional distance between the vertical posts of M1 150 and the cell boundary edge. The type of routing that uses the extensions of the horizontal posts of Metal 0 130 is shown in the cell layout 200 (of FIG. 2).

[0024] Referring to FIG. 2, a generalized block diagram of a plan view of the cell layout 200 is shown. The same reference numerals are assigned to the layout elements described above. Similar to the cell layouts 102, 104, the post positions for power connections are at the top and the post connections for ground connections are at the bottom. As shown, the cell layout 200 includes an inverter on the left side and one of various composite gates as an adjacent cell on the right side. In various embodiments, each of the inverter and the adjacent cell is a standard cell within a cell layout library. In other embodiments, one or more of the inverter and the adjacent cell are custom design cells separate from the cell layout library.

[0025] Here, in layout 200, each of the inverter and the adjacent cells has power tracks and ground reference tracks that are aligned with each other at the horizontal posts of metal 0 130. In various embodiments, the software placement and routing tool places the inverter to the left of the composite gate on the die of the chip design. In one embodiment, the inverter already has horizontal M0 extensions 132 for power and ground connections. The design rule check (DRC) performed by the layout tool is modified to allow the use of M0 extensions 132. When the software placement and routing tool places the inverter to the left side, the power and ground connections are made by a junction between the left-side inverter and the right-side composite gate.

[0026] In another embodiment, the cell layout of the inverter does not include horizontal M0 extensions 132 for power and ground connections. However, the horizontal power and ground tracks of metal 0 130 are aligned with the horizontal power and ground tracks of metal 0 130 within the composite gate. Thus, the placement and routing tool is modified to place the inverter to the left of the composite gate and add additional horizontal routes of metal 0 130 instead of horizontal metal 2 170 between the power connection of the inverter and the composite gate. Further, the placement and routing tool adds additional horizontal routes of metal 0 130 instead of horizontal metal 2 170 between the ground connection of the inverter and the composite gate.

[0027] In some embodiments, the layout rules allow power connections to be placed on horizontal tracks below the currently used metal 0 130 horizontal tracks shown in cell layout 200. Also in some embodiments, the layout rules allow ground connections to be placed on horizontal tracks above the currently used metal 0 130 horizontal tracks shown in cell layout 200. Thus, four different variations of the inverter cell layout are possible for arranging power and ground connections. However, some cells in the layout cell library do not have metal 0 tracks available to reach the cell boundary edge. Power and ground connections need to be routed in an upper metal layer, such as a metal 2 150 post.

[0028] The cell layout library also uses additional cell layouts for inverters that utilize metal 2 150 posts. Therefore, a fifth variation of the inverter cell layout is possible for the placement of power and ground connections. In one embodiment, the placement rules of the placement and routing tool are modified to determine which of the five variations of the inverter cell is placed adjacent to a particular composite gate, based on the power and ground connections of the composite gate. In other embodiments, where the number of additional available metal 0 130 tracks for power and ground connections is greater than two, the number of possible variations of the inverter cell layout increases.

[0029] Once determined, the placement and routing tool selects one of several variations of inverter cells to be positioned to the left of the composite gate so that the power and ground connections are aligned between the inverter and the composite gate. In one embodiment, the inverter cell layout uses the horizontal extension 132 of metal 0, and routing is performed by joining. In another embodiment, the inverter cell layout does not use the horizontal extension 132 of metal 0, and routing is performed by the placement and routing tool, which adds an additional horizontal route of metal 0 130 between the inverter power connections and the composite gate, rather than the horizontal metal 2 170.

[0030] As described above, the layout and placement / routing techniques described above describe inverters, but these techniques can also be used for other standard cells in the layout library. For example, these techniques can also be used for other standard cells that have more pins than the number of metal gates 110. Other examples of standard cells in the layout cell library that have a proportion greater than 1 are the 2-input Boolean NAND gate and the 2-input Boolean NOR gate. In one example, there are three logic gates, and each gate has four combinations regarding the placement of power and ground connections. Thus, the layout library supports 12 different standard cell layouts, and in each standard cell layout, horizontal posts of metal 0 130 are used for power connections instead of horizontal posts of metal 2 170.

[0031] Referring to Figure 3, a generalized block diagram of the plan view of the multi-cell layout 300 is shown. The layout elements described above are denoted by the same reference numerals. Similar to cell layouts 102, 104, and 200, the post locations for power connections are located at the top, and the post connections for ground connections are located at the bottom. In contrast to the inverter cell layouts in cell layouts 102, 104, and 200, cell layout 300 has power tracks and ground reference tracks in the horizontal posts of metal 2 170. Via 160 is used to connect a vertical power post of metal 1 150 to a horizontal post of metal 2 170 that can be routed to another power post in the horizontal metal 2 170 of an adjacent cell (not shown). Via 160 is used similarly for ground connections.

[0032] Without using extensions of metal 0 130 and without using modifications to the placement and routing tools, additional metal gates 110 are placed to create space for tracks of metal 1(M1) 150 for routing power and ground connections. As shown in the figure, cell layout 300 has an area increase of distance 302 compared to the inverter of cell layouts 102, 104, and 200 above. Distance 302 is the distance between the left end of the additional metal gate 110 and the original leftmost metal gate 110. Additional trench silicide contacts 120 are also placed. The additional metal gate 110 meets the DRC based on the manufacturing process which specifies the minimum distance between the vertical post of metal 1 150 and the metal gate 110. Distance 304 indicates the threshold distance between the boundary edge 306 of cell layout 300 and the end of the horizontal track of metal 0 130.

[0033] Referring to Figure 4, a generalized block diagram of the plan view of cell layout 400 is shown. The layout elements described above are denoted by the same reference numerals. Similar to cell layouts 102 and 104, the post positions for power connections are located at the top, and the post connections for ground connections are located at the bottom. As shown, cell layout 400 includes an inverter on the left and any of the various composite gates as adjacent cells on the right. In various embodiments, each of the inverter and adjacent cells is a standard cell from the cell layout library. In other embodiments, one or more of the inverter and adjacent cells are custom-designed cells separate from the cell layout library. Here, in layout 400, the inverter and adjacent cells have power tracks and ground reference tracks aligned with each other on horizontal posts of metal 0 130. For example, the tracks labeled "Power Track 1" and "Ground Track 1" indicate the alignment of the inverter and composite gate.

[0034] In various embodiments, the software placement and routing tool positions the inverter to the left of the composite gate on the die of the chip design. In one embodiment, the inverter already has a horizontal M0 extension 132 for power and ground connections. A layout design rule check (DRC) performed by the layout tool is modified to allow the use of the M0 extension 132. As shown in the figure, the cell layout 400 includes two other tracks for routing the power and ground connections. In one embodiment, another modification of the inverter uses other tracks labeled “power track 2” and “ground track 2” for the power and ground connections. As described above, there may be several different variations of the inverter cell layout for arranging the power and ground connections.

[0035] Referring to Figure 5, one embodiment of a method 500 for generating power grid connections for a cell layout is shown. For illustrative purposes, the steps in this embodiment (as in Figure 6) are shown in order. However, in other embodiments, some steps occur in a different order than illustrated, some steps are performed simultaneously, some steps are combined with others, and some steps are absent.

[0036] A cell suitable for using metal 0 for power and ground connections is determined (block 502). In one embodiment, a standard or custom cell is eligible if it has fewer metal gates than the sum of one or more input nodes, one or more output nodes, and the power and ground connections of the cell. In some embodiments, an eligible cell includes one or more inverters, two-input Boolean NAND gates, and two-input Boolean NOR gates.

[0037] To route the power and earth connections within metal 0, several variations are determined for each eligible cell (block 504). In various embodiments, each post of metal 0 (M0) for power and earth connections has multiple available tracks for routing. The number of variations is equal to the number of combinations used to route the power and earth connections using the available tracks. For example, if there are two available tracks of metal 0 for power within an eligible cell and two available tracks of metal 0 for earth reference within an eligible cell, there are four possible variations for the appropriate cell to route the power and earth connections of metal 0.

[0038] For each appropriate cell variation, power and ground connections within metal 0 are routed to the cell boundary edge (block 506). In one embodiment, the cell layout library is updated with the new standard cell. The next step concerns floor planning of the chip design. Using the place and route tool, a standard cell is selected from the library, the standard cell is placed next to adjacent cells, and power and ground connections are routed globally. If no appropriate cell variation is required for placement in the chip floor plan (condition block 508: No), placement and routing are completed using a cell that uses a metal layer other than metal 0 for power and ground connections (block 510). For example, in some embodiments, the metal 2 (M2) layer is used for power and ground connections.

[0039] If any of the eligible cell variations is required for placement in the chip floor plan (condition block 508: Yes), one of the multiple variations is selected based on the adjacent cells in the floor plan (block 512). The selected variation of the eligible cell is placed next to the adjacent cell, and the placement routing tool moves to the next cell placement without further routing of power and ground (block 514). Power and ground connections are formed in metal 0 by the junction of the selected eligible cell and its adjacent cell.

[0040] Referring to Figure 6, an embodiment of another method 600 for generating a power grid for a standard cell layout is shown. Cells suitable for using metal 0 for power and ground connections are determined (block 602). As described above, in one embodiment, a standard or custom cell is eligible if it has one or more input nodes, one or more output nodes, and fewer metal gates than the sum of the power and ground connections of the standard cell. In some embodiments, an eligible cell includes one or more inverters, two-input Boolean NAND gates, and two-input Boolean NOR gates. In various embodiments, the number of times a standard cell is used with respect to inverters, two-input Boolean NAND gates, and two-input Boolean NOR gates in a chip floor plan can be considerable in many designs.

[0041] To route the power and ground connections for Metal 0, several variations are determined for each eligible cell (block 604). As mentioned above, the number of variations is equal to the number of combinations used to route the power and ground connections using the available tracks. For example, if there are two available tracks for Metal 0 for power and two available tracks for Metal 0 for installation criteria within an eligible cell, there are four possible variations for the appropriate cell to route the power and ground connections for Metal 0.

[0042] For each appropriate cell variation, power and ground connections within Metal 0 are routed from the cell boundary edge to a threshold distance (block 606). In one embodiment, the cell layout library is updated with the new standard cell. In the next step, the place and route tool selects a standard cell from the library, places the standard cell next to adjacent cells, and routes the power and ground connections globally. If no eligible cell variation is required for placement in the chip floor plan (condition block 608: No), placement and routing are completed using a cell that uses a metal layer other than Metal 0 for power and ground connections (block 610). For example, in some embodiments, the Metal 2 (M2) layer is used for power and ground connections.

[0043] If any of the eligible cell variations are required for placement in the chip floor plan (condition block 608: Yes), one of the multiple variations is selected based on the adjacent cells in the floor plan (block 612). The selected variation of the eligible cell is placed next to the adjacent cell, and the placement and routing tool routes the metal 0 connection between the eligible cell and the adjacent cell and moves on to the next cell placement (block 614).

[0044] It should be noted that one or more of the embodiments described above include software. In such embodiments, program instructions for implementing the method and / or mechanism are transmitted to or stored on a computer-readable medium. Many types of media configured to store program instructions are available, and these include hard disks, floppy disks, CD-ROMs, DVDs, flash memory, programmable ROM (PROM), random access memory (RAM), and various other forms of volatile or non-volatile storage devices. Generally speaking, a computer-accessible storage medium includes any storage medium that a computer can access while in use to provide instructions and / or data to the computer. For example, a computer-accessible storage medium includes, for example, magnetic or optical media such as disks (fixed or removable), tapes, CD-ROMs, DVD-ROMs, CD-Rs, CD-RWs, DVD-Rs, DVD-RWs, and Blu-Ray® discs. The storage medium further includes volatile or non-volatile storage media such as RAM (e.g., synchronous dynamic RAM (SDRAM), double data rate (DDR, DDR2, DDR3, etc.) SDRAM, low power DDR (LPDDR2, etc.) SDRAM, Rambus DRAM (RDRAM), static RAM (SRAM), etc.), ROM, flash memory, and non-volatile memory (e.g., flash memory) accessible via peripheral interfaces such as USB interfaces. The storage medium also includes microelectromechanical systems (MEMS) and storage media accessible via communication media such as networks and / or wireless links.

[0045] In various embodiments, program instructions include operational-level or register-transfer-level (RTL) descriptions of hardware functions in high-level programming languages ​​such as C, design languages ​​(HDL) such as Verilog and VHDL, or database formats such as GDS II Stream Format (GDSII). In some cases, the descriptions are read by a synthesis tool, which synthesizes the descriptions to generate a netlist from a synthesis library containing a list of gates. The netlist contains a set of gates representing the functions of the hardware, including the system. The netlist is then arranged and routed to generate a dataset describing the geometric shapes applied to the mask. The mask is then used in various semiconductor manufacturing processes to produce one or more semiconductor circuits corresponding to the system. Alternatively, instructions on a computer-accessible storage medium may be a netlist (with or without a synthesis library) or a dataset, as needed. Furthermore, instructions are used for emulation purposes by hardware-based emulators from vendors such as Cadence®, EVE®, and Mentor Graphics®.

[0046] Although the embodiments described above have been explained in considerable detail, many variations and modifications will become apparent to those skilled in the art if the above disclosure is fully understood. The attached claims are intended to be construed to encompass all such variations and modifications.

Claims

1. a first cell adjacent to a first neighboring cell, the first cell configured to provide a first function, a power post aligned between the first cell and the first neighboring cell on a first power track; a second cell adjacent to a second adjacent cell, the second cell configured to provide the first function, a power post aligned between the second cell and the second adjacent cell on a second power track different from the first power track; Semiconductor integrated circuit.

2. the first neighboring cell is configured to provide a second function different from the first function.

2. The semiconductor integrated circuit of claim 1.

3. the second neighboring cell is configured to provide a third function different from the second function.

3. The semiconductor integrated circuit of claim 2.

4. the second cell contains a copy of the layout of the first cell; 2. The semiconductor integrated circuit of claim 1.

5. the second cell has one or more power posts on a different power track than the first cell; 2. The semiconductor integrated circuit of claim 1.

6. One or more of the first cell and the second cell are a first end of the power post routed in only a predetermined direction to a boundary edge of a corresponding cell layout in a metal layer; a second end of the power post that is not routed to a boundary edge of the corresponding cell layout.

2. The semiconductor integrated circuit of claim 1.

7. the power posts are routed in a metal layer used for local interconnect in only one direction; 2. The semiconductor integrated circuit of claim 1.

8. a first cell adjacent to a first neighboring cell providing a first function, a power post being aligned between the first cell and the first neighboring cell in a first power track; a second cell adjacent to a second adjacent cell providing the first function, wherein a power post is aligned between the second cell and the second adjacent cell on a second power track different from the first power track; method.

9. the first neighboring cell further comprising providing a second functionality different from the first functionality.

9. The method of claim 8.

10. the second neighboring cell further comprising providing a third function different from the second function.

10. The method of claim 9.

11. the second cell contains a copy of the layout of the first cell; 9. The method of claim 8.

12. and further comprising one or more power posts of the second cell providing a power supply voltage on a different power track than the first cell.

9. The method of claim 8.

13. one or more power posts of one or more of the first cell and the second cell further provide a power supply voltage; Each of the one or more power posts: a first end of the power post routed in only a predetermined direction to a boundary edge of a corresponding cell layout in a metal layer; a second end of the power post that is not routed to a boundary edge of the corresponding cell layout.

9. The method of claim 8.

14. the power posts routed in a metal layer used for local interconnect in only a predetermined direction provide a power supply voltage; 9. The method of claim 8.

15. 1. A semiconductor manufacturing method for manufacturing an integrated circuit having a plurality of cells, comprising: a first plurality of devices having non-planar metal gates configured to provide a first function of the first cell; a first power post of the first cell, the first power post being aligned with a second power post of a first adjacent cell adjacent to the first cell in a first power track; a second plurality of devices having non-planar metal gates configured to provide the first function of a second cell; a third power post of the second cell, the third power post being aligned with a fourth power post of a second adjacent cell adjacent to the second cell in a second power track different from the first power track; in the plurality of cells using lithographic techniques. Semiconductor manufacturing methods.

16. the first neighboring cell is configured to provide a second function different from the first function. The semiconductor manufacturing method of claim 15.

17. the second neighboring cell is configured to provide a third function different from the second function.

17. The semiconductor manufacturing method of claim 16.

18. forming a layout of the second cell as a copy of the layout of the first cell; The semiconductor manufacturing method of claim 15.

19. further comprising locating one or more power posts of the second cell on a different power track than the first cell. The semiconductor manufacturing method of claim 15.

20. a first end of the power post routed in only a predetermined direction to a boundary edge of a corresponding cell layout in a metal layer; a second end of the power post that is not routed to a boundary edge of the corresponding cell layout; in one or more of the first cell and the second cell. The semiconductor manufacturing method of claim 15.

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