Signal generator and emphasis switching method using same

Abstract

To provide a signal generator and an emphasis switching method using the same that can flexibly increase the number of taps while achieving high-speed emphasis switching.SOLUTION: A signal generator 1 includes an emphasis adding circuit 5 including at least one FIR filter portion that adds emphasis to a PAM signal pattern consisting of di- or more multi-values to generate an emphasis waveform pattern, and a tap value setting portion 9 that switches and sets M tap values C(0), C(-1), ..., and C(1-M) for each FIR filter portion in response to an emphasis switching request from a DUT 100, and each FIR filter portion is configured on an FPGA or an ASIC.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a signal generating device and an emphasis switching method using the same. [Background technology]

[0002] In compliance tests to check whether a device under test (DUT) complies with communication standards such as PCIe (registered trademark) (Peripheral Component Interconnect Express) and 400 GbE (Gigabit Ethernet), the emphasis of the test signal needs to be set to ensure quality as the bit rate of the test signal output from the transmitting signal generator (Pulse Pattern Generator: PPG) to the DUT increases. In this case, the waveform of the test signal needs to be switched quickly in response to a request to switch the emphasis from the DUT. For example, the PCIe standard requires that the waveform of the test signal be switched in a switching time of 1 μs or less.

[0003] In a PPG that generates test signals such as NRZ (Non Return to Zero) signals and PAM4 (Pulse Amplitude Modulation 4) signals, the emphasis adding circuit that adds emphasis to the patterns of these test signals typically has a FIR (Finite Impulse Response) filter structure and is configured in an IC (Integrated Circuit) closest to the DUT (see, for example, Patent Document 1).

[0004] 8 is a circuit diagram showing a schematic configuration of an FIR filter 60 used for adding emphasis. The FIR filter 60 is a circuit that delays an input pattern by 1 UI (Unit Interval) and outputs the result after performing a product-sum operation with a tap value for adding emphasis. For example, the FIR filter 60 includes four stages of delay circuits 61a to 61d that sequentially delay the input pattern by 1 UI and output the delayed result, and five tap values ​​C(-4), C(-3), C(-2), C(-1), and C(0) that are used to calculate the n-th to n+4-th data a of the input pattern. n ~a n+4 and four adders 63a to 63d that add the output values ​​of the five multipliers 62a to 62e and output the result as a pattern with emphasis. Note that the number of each calculator is merely an example.

[0005] In the FIR filter 60, the delay circuits 61a to 61d are configured, for example, with D flip-flops, and each outputs the same value as the input value at the rising or falling timing of the input clock.

[0006] Here, the multiplier 62a multiplies the n+4th data a n+4 The multiplier 62b multiplies the n+3th data a of the pattern delayed by 1 UI by the delay circuit 61a. n+3 The multiplier 62c multiplies the n+2-th data a of the pattern delayed by 2UI by the delay circuits 61a and 61b. n+2 The multiplier 62d multiplies the n+1-th data a of the pattern delayed by 3 UI by the delay circuits 61a to 61c. n+1 The multiplier 62e multiplies the n-th data a of the pattern delayed by 4 UI by the delay circuits 61a to 61d by the tap value C(−1). n and the tap value C(0).

[0007] Furthermore, adder 63d adds the output value of multiplier 62d to the output value of multiplier 62e. Adder 63c adds the output value of adder 63d to the output value of multiplier 62c. Adder 63b adds the output value of adder 63c to the output value of multiplier 62b. Adder 63a adds the output value of adder 63b to the output value of multiplier 62a, thereby outputting a value obtained by adding together all of the output values ​​of multipliers 62a to 62e. [Prior art documents] [Patent documents]

[0008] [Patent Document 1] Patent No. 5496940 Summary of the Invention [Problem to be solved by the invention]

[0009] However, in the structure disclosed in Patent Document 1, the number of taps is determined by the design of the IC, and therefore there is a problem in that the number of taps once determined cannot be increased later in response to changes in standards.

[0010] Furthermore, in the structure disclosed in Patent Document 1, a hardware switch is introduced to switch the emphasis, which increases the overall mounting area of ​​the FIR filter, making it difficult to realize multiple taps and making it difficult to flexibly switch the tap values.

[0011] Furthermore, in the above-mentioned configuration of the FIR filter 60, it is necessary to prepare a clock with a frequency that is, for example, half the output bit rate. However, if the FIR filter 60 is configured on an FPGA (Field Programmable Gate Array), since the FPGA operates only at a clock of several hundreds of MHz, there is a problem that a one-clock, one-output circuit such as the FIR filter 60 cannot handle high-speed bit rates such as 112G.

[0012] The present invention has been made to solve such conventional problems, and has an object to provide a signal generating device that can flexibly increase the number of taps while achieving high-speed emphasis switching, and an emphasis switching method using the same. [Means for solving the problem]

[0013] In order to achieve the above object, a signal generating device according to the present invention comprises an emphasis adding circuit having at least one FIR filter section which adds emphasis to a PAM signal pattern consisting of two or more values ​​to generate an emphasis waveform pattern, and a tap value setting section which switches and sets M tap values ​​C(0), C(-1), . . . , C(1-M) in each of the FIR filter sections in response to an emphasis switching request from a device under test, and each of the FIR filter sections selects the n+1th to n+M-1th data out of the nth to n+M-1th data constituting the pattern of the PAM signal. the nth data to the n+M-1th data output from the delay unit by the tap values ​​C(0), C(-1), . . . , C(1-M) output from the delay unit, respectively; and a plurality of multipliers that multiply the nth data to the n+M-1th data output from the delay unit by the tap values ​​C(0), C(-1), . . . , C(1-M) output from the delay unit, respectively, and a plurality of adders that add up output values ​​of the plurality of multipliers to generate the emphasis waveform pattern, and each of the FIR filter units is configured on an FPGA (Field Programmable Gate Array) or an ASIC (Application Specific Integrated Circuit).

[0014] With this configuration, the signal generator according to the present invention can add emphasis to a PAM signal pattern consisting of two or more values, using at least one FIR filter unit. The signal generator according to the present invention can switch the final output waveform at high speed by switching M tap values ​​C(0), C(-1), . . . , C(1-M) input to each FIR filter unit. The signal generator according to the present invention can flexibly increase the number of taps M and the number of output bits N while realizing high-speed emphasis switching, when the number of required taps increases due to future standard trends, by configuring an emphasis adding circuit having at least one FIR filter unit on an FPGA or ASIC.

[0015] Furthermore, in the signal generating device according to the present invention, the tap value setting section may include an emphasis setting table that stores a plurality of sets of the tap values ​​C(0), C(-1),...,C(1-M) defined by a standard, and an emphasis switching instruction section that selects, in response to the switching request from the device under test, from the emphasis setting table, tap values ​​C(0), C(-1),...,C(1-M) to be newly set in each of the FIR filter sections, and outputs the selected tap values ​​C(0), C(-1),...,C(1-M) from the emphasis setting table.

[0016] With this configuration, the signal generating device according to the present invention can select tap values ​​C(0), C(-1),...,C(1-M) from the emphasis setting table in response to a switching request from the device under test, and set the selected tap values ​​C(0), C(-1),...,C(1-M) to each FIR filter section.

[0017] Furthermore, in the signal generating device according to the present invention, the plurality of multipliers and the plurality of adders may be configured within a DSP (Digital Signal Processor).

[0018] With this configuration, the signal generating device according to the present invention has each FIR filter section configured using a DSP, making it possible to efficiently utilize FPGA or ASIC resources, and if the number of required taps increases due to future standard trends, it is possible to flexibly increase the number of taps M and the number of output bits N.

[0019] Moreover, the signal generating device according to the present invention further comprises an N-bit DAC that outputs an analog signal corresponding to the emphasis waveform pattern output from the emphasis adding circuit to the device under test, and the FIR filter section adjusts the output values ​​of the plurality of multipliers added by the plurality of adders from 0 to 2. N The emphasis waveform pattern may further include an N-bit conversion unit that converts the emphasis waveform pattern into an integer value in the range of −1 to generate an N-bit emphasis waveform pattern.

[0020] With this configuration, the signal generating device of the present invention is configured to input an N-bit emphasis waveform pattern from the emphasis adding circuit to an N-bit DAC to generate a test signal for the device under test, thereby achieving both faster bit rates and emphasis addition, and realizing a signal generating device with high waveform performance that supports multi-values.

[0021] Further, an emphasis adding method according to the present invention includes an emphasis adding step in which at least one FIR filter section configured on an FPGA (Field Programmable Gate Array) or ASIC (Application Specific Integrated Circuit) adds emphasis to a PAM signal pattern consisting of two or more values ​​to generate an emphasis waveform pattern, and a tap value setting step in which, in response to an emphasis switching request from a device under test, M tap values ​​C(0), C(-1), . . . , C(1-M) are switched and set in each of the FIR filter sections, and the emphasis adding step includes, among the nth to n+M-1th data constituting the pattern of the PAM signal, setting the n+1th to n+M-1th data in the order of the nth to n+M-1th data. the nth to n+M-1th data output from the delay step by a predetermined delay amount, and outputting the tap values ​​C(0), C(-1), . . . , C(1-M) at the same timing as the nth to n+M-1th data, respectively; a multiplication step multiplying the nth to n+M-1th data output from the delay step by the tap values ​​C(0), C(-1), . . . , C(1-M) output from the delay step by the nth to n+M-1th data output from the delay step, respectively, and an addition step adding output values ​​from the multiplication step to generate the emphasis waveform pattern.

[0022] Furthermore, in the emphasis adding method according to the present invention, the tap value setting step may be configured to select, in response to the switching request from the device under test, tap values ​​C(0), C(-1),...,C(1-M) to be newly set in each of the FIR filter sections from an emphasis setting table that stores a plurality of sets of the tap values ​​C(0), C(-1),...,C(1-M) defined by a standard, and output the selected tap values ​​C(0), C(-1),...,C(1-M) from the emphasis setting table. Effect of the Invention

[0023] The present invention provides a signal generator that can flexibly increase the number of taps while realizing high-speed emphasis switching, and an emphasis switching method using the same. [Brief description of the drawings]

[0024] [Figure 1] 1 is a block diagram showing a configuration of a signal generating device according to an embodiment of the present invention. [Diagram 2] 1 is a circuit diagram (part 1) showing a schematic configuration of an FIR filter section of an emphasis adding circuit included in a signal generating device according to an embodiment of the present invention. [Diagram 3] 2 is a circuit diagram showing a schematic configuration of a DSP included in an FIR filter unit. FIG. [Figure 4] 2 is a circuit diagram (part 2) showing a schematic configuration of an FIR filter section of an emphasis adding circuit included in a signal generating device according to an embodiment of the present invention. FIG. [Diagram 5] FIG. 2 is a block diagram showing a configuration of an emphasis adding circuit. [Figure 6] 13 is a table for explaining an output for each clock of an emphasis adding circuit. [Figure 7] 5 is a flowchart showing the process of an emphasis switching method using a signal generating device according to an embodiment of the present invention. [Figure 8] FIG. 1 is a circuit diagram showing a schematic configuration of an FIR filter used for adding emphasis in the related art. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0025] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, preferred embodiments of a signal generating device and an emphasis switching method using the same according to the present invention will be described with reference to the accompanying drawings.

[0026] 1 includes a pattern generating circuit 2, an encoding circuit 3, a symbol level converting section 4, an emphasis adding circuit 5, an output transceiver 6, a multiplexer (MUX) 7, an N-bit DAC (N-bit Digital Analog Converter) 8, a tap value setting section 9, an operation section 10, and a control section 11. Note that the pattern generating circuit 2, the encoding circuit 3, the symbol level converting section 4, the emphasis adding circuit 5, the output transceiver 6, and the tap value setting section 9 are configured on, for example, an FPGA or an ASIC (Application Specific Integrated Circuit), but the following description will be given assuming that they are configured on an FPGA.

[0027] The pattern generation circuit 2 generates a PAM signal pattern consisting of two or more multi-values ​​K (K is an integer of 2 or more) synchronized with a clock of a predetermined period based on pattern information input from the control unit 11. The pattern generation circuit 2 generates a PAM signal pattern consisting of any multi-value K, such as an NRZ signal (K=2), a PAM3 signal (K=3), a PAM4 signal (K=4), a PAM5 signal (K=5), a PAM6 signal (K=6), a PAM7 signal (K=7), or a PAM8 signal (K=8). Here, the pattern information is information on the pattern of the PAM signal, such as the value of K and the type of pattern (for example, a Pseudo Random Binary Sequence (PRBS) pattern, a Short Stress Pattern Random Quaternary (SSPRQ) pattern, or any pattern), and can be set by a user's operation input to the operation unit 10.

[0028] The encoding circuit 3 performs coding such as gray coding and precoding on the PAM symbols constituting the pattern of the PAM signal generated by the pattern generation circuit 2 based on coding information input from the control unit 11. Here, the coding information is information indicating whether or not gray coding or precoding is to be performed, and can be set by a user's operation input to the operation unit 10.

[0029] For example, the encoding circuit 3 performs gray coding on the PAM symbol when the gray coding process for the PAM symbol is set to ON in advance by a user's operation input to the operation unit 10. On the other hand, the encoding circuit 3 does not perform gray coding on the PAM symbol when the gray coding process is set to OFF in advance by a user's operation input to the operation unit 10. Similarly, the encoding circuit 3 performs precoding on the PAM symbol when the precoding process is set to ON in advance by a user's operation input to the operation unit 10. On the other hand, the encoding circuit 3 does not perform precoding on the PAM symbol when the precoding process is set to OFF in advance by a user's operation input to the operation unit 10.

[0030] The symbol level converter 4 converts the PAM symbols constituting the pattern of the PAM signal output from the encoding circuit 3 into data a having an amplitude value ranging from -1 to 1, for example, based on the amplitude information input from the controller 11. nHere, the amplitude information is information that, for example, in the case of a PAM4 signal (K=4), associates PAM symbol "00" with amplitude value "-1", PAM symbol "01" with amplitude value "-0.33", PAM symbol "10" with amplitude value "0.33", and PAM symbol "11" with amplitude value "1", and can be set by a user's operation input to operation unit 10. In other words, the amplitude ratio of the eye of the PAM signal finally output from N-bit DAC 8 changes depending on the magnitude of the amplitude value determined by the amplitude information.

[0031] The emphasis adding circuit 5 includes at least one FIR filter section 50 (see FIGS. 2 and 4) that adds emphasis to the pattern of the PAM signal output from the symbol level conversion section 4 to generate an emphasis waveform pattern.

[0032] As shown in Fig. 2, the FIR filter unit 50 has M taps, and includes M-1 delay circuits 51_1 to 51_M-1 constituting a delay unit 51, and M+1 DSPs (Digital Signal Processors) 52_0 to 52_M. The number of taps M is limited by the capacity of the FPGA, but can be any value. The M+1 DSPs 52_0 to 52_M may all have the same configuration, and in the following description, each DSP may be indicated by the reference symbol 52. Each FIR filter unit 50 is configured on, for example, an FPGA or an ASIC.

[0033] The delay circuits 51_1 to 51_M-1 respectively receive the n-th to (n+M-1)-th PAM symbol data a output from the symbol level converter 4 at the same clock timing. n ,a n+1 ,···,a n+M-1 Of these, data a from n+1 to n+M-1 n+1 ,a n+2 ,···,a n+M-1 The previous data a n ,a n+1 ,···,a n+M-2The delay unit 51 delays each of the n-th to (n+M-1)-th data a by a predetermined amount and outputs the delayed data. n ,a n+1 ,···,a n+M-1 The delay circuits 51_1, 51_2, . . . , 51_M-1 are each configured with, for example, a D flip-flop.

[0034] 3, the DSP 52 includes a multiplier 53 that outputs a value a×b obtained by multiplying an input value a by an input value b, a delay unit 54 that outputs an input value c with a delay of 0 UI or 1 UI, and an adder 55 that outputs a value d obtained by adding the output value a×b of the multiplier 53 to the output value c of the delay unit 54. The multiplication process of the multiplier 53 and the addition process of the adder 55 both require a time period of 2 clocks, that is, 2 UI.

[0035] That is, when the delay amount of the delay unit 54 is 0 UI, the output value d of the DSP 52 is delayed by 4 clocks from the input of the input values ​​a and b, and is delayed by 2 clocks from the input of the input value c. On the other hand, when the delay amount of the delay unit 54 is 1 UI, the output value d of the DSP 52 is delayed by 4 clocks from the input of the input values ​​a and b, and is delayed by 3 clocks from the input of the input value c.

[0036] 2 is a circuit diagram showing the configuration of the FIR filter unit 50 when the delay amount of the delay unit 54 of the DSP 52 is 0 UI. In the configuration shown in FIG. 2, the multipliers 53 of the DSPs 52_0 to 52_M-1 multiply the data a of the n-th to (n+M-1)-th PAM symbols output from the delay unit 51. n ,a n+1 ,···,a n+M-1 by the tap values ​​C(0), C(-1), . . . , C(1-M) output from the delay unit 51, and output the result. Here, the tap values ​​C(0), C(-1), . . . , C(1-M) are each values ​​in the range from -1 to 1, and the sum of their absolute values ​​is 1.

[0037] The delay circuit 51_1 receives the data a of the (n+1)th PAM symbol. n+1 Similarly, the delay circuit 51_M-1 delays the data a of the (n+M-1)th PAM symbol by 2 UI. n+M-1 and delay the tap value C(1-M) by 2(M-1) UI.

[0038] The multiplier 53 of DSP52_0 multiplies the data a of the nth PAM symbol without delay. n The multiplier 53 of the DSP 52_1 multiplies the data a of the (n+1)th PAM symbol delayed by 2 UI by the delay circuit 51_1. n+1 Similarly, the multiplier 53 of the DSP 52_M-1 multiplies the data a of the (n+M-1)-th PAM symbol delayed by the delay circuit 51_M-1 by 2(M-1) UI. n+M-1 and the tap value C(1-M).

[0039] The adder 55 of the DSP 52_0 adds a constant 1 to the output value of the multiplier 53 of the DSP 52_0. The constant 1 added by the adder 55 of the DSP 52_0 is calculated by multiplying the output from the FIR filter unit 50, i.e., the input to the N-bit DAC 8 by 0 to 2. N This is a value for adjusting the output value from the FIR filter unit 50 to an integer in the range of 0 to 2. N When the constant is set to an integer other than the range of -1, the constant added by the adder 55 of the DSP 52_0 may be set to another appropriate value.

[0040] The adders 55 of DSP52_0 to 52_M-1 are adapted to add the output values ​​of the multipliers 53 of DSP52_0 to 52_M-1 to generate an emphasis waveform pattern. The adder 55 of DSP52_1 adds the output value of the adder 55 of DSP52_0 to the output value of the multiplier 53 of DSP52_1. Similarly, the adder 55 of DSP52_M-1 adds the output value of the adder 55 of DSP52_M-2 to the output value of the multiplier 53 of DSP52_M-1.

[0041] The multiplier 53 of DSP52_M multiplies the output value of the adder 55 of DSP52_M-1 by a constant 2 N-1 The adder 55 of the DSP 52_M adds a constant −0.5 to the output value of the multiplier 53 of the DSP 52_M to obtain the N-bit emphasis waveform pattern data b n Further, the DSP52_M obtains the data b n is expanded to N lanes and output.

[0042] The above constant 2 is input to DSP52_M N-1 and -0.5 means that the input to the N-bit DAC8 goes from 0 to 2 N This is a value for adjusting the output value from the FIR filter unit 50 to an integer in the range of 0 to 2. N To set it to an integer other than -1, use the constant 2 above. N-1 Here, the DSPs 52_M and 52_0 convert the output values ​​of the multipliers 53 of the M DSPs 52_0 to 52_M-1, which are added by the adders 55 of the M DSPs 52_0 to 52_M-1, into a value ranging from 0 to 2. N An N-bit conversion unit is configured to convert the input signal into an integer value in the range of -1 and generate an N-bit emphasis waveform pattern.

[0043] Data a of the nth to n+M-1th PAM symbols n ,a n+1 ,···,a n+M-1 When the timing at which the DSP52_0 is output from the symbol level conversion unit 4 is taken as a reference, the delay amount of the output value of the adder 55 of the DSP52_0 is 4 clocks, and the delay amount of the output value of the adder 55 of the DSP52_1 is 6 clocks. Similarly, the delay amount of the output value of the adder 55 of the DSP52_M-1 is (M+1)×2 clocks. Furthermore, the delay amount of the output value of the adder 55 of the DSP52_M is (M+3)×2 clocks. In other words, the delay amount of the entire FIR filter unit 50 shown in FIG. 2 is (M+3)×2 clocks.

[0044] Fig. 4 is a circuit diagram showing the configuration of the FIR filter unit 50 when the delay amount of the delay unit 54 of the DSP 52 is 1 UI. The configurations of Fig. 2 and Fig. 4 are similar except that the delay amount of the delay unit 54 of the DSP 52 and the delay amounts of the delay circuits 51_1 to 51_M-1 are different.

[0045] In the configuration shown in FIG. 4, the delay circuit 51_1 delays the data a n+1 Similarly, the delay circuit 51_M-1 delays the data a of the (n+M-1)th PAM symbol by 3 UI. n+M-1 and delay the tap value C(1-M) by 3(M-1) UI.

[0046] Data a of the nth to n+M-1th PAM symbols n ,a n+1 ,···,a n+M-1 When the timing at which the DSP52_0 is output from the symbol level conversion unit 4 is used as a reference, the delay amount of the output value of the adder 55 of the DSP52_0 is 4 clocks, and the delay amount of the output value of the adder 55 of the DSP52_1 is 7 clocks. Similarly, the delay amount of the output value of the adder 55 of the DSP52_M-1 is (M+1)×3-2 clocks. Furthermore, the delay amount of the output value of the adder 55 of the DSP52_M is (M+1)×3+2 clocks. In other words, the delay amount of the entire FIR filter unit 50 shown in FIG. 4 is (M+1)×3+2 clocks.

[0047] According to the configuration of the FIR filter unit 50 shown in FIG. 2 and FIG. 4, the data b n The first term of data b0 is data a0, a1, . . ., a M-1 It is expressed by the following formula (1) using

[0048]

number

[0049] Similarly, data b1 is stored in data a1, a2, . . . , a M It is expressed by the following formula (2) using

[0050]

number

[0051] Therefore, data b n The general term of data a n ,a n+1 ,···,a n+M-1 Here, the data b n is 0 to 2 N It is an integer in the range -1.

[0052]

number

[0053] 2 and 4, the FIR filter unit 50 receives data a n ,a n+1 ,···,a n+M-1 5, the emphasis adding circuit 5 can be configured as a plurality of FIR filter units 50 in FIG. 2 and FIG. 4 arranged in parallel in accordance with the FPGA resources. n ,b n+1 ,b n+2 It is possible to output a plurality of data constituting a pattern after emphasis has been added, such as , . . ., at the same clock timing.

[0054] For example, the number of output lanes N of the emphasis adding circuit 5, that is, the data b n If the number of bits N is 4 and the number of bits B processed in one clock for each output lane is 8 bits, the data b nThe output of the emphasis adding circuit 5 is as shown in FIG. n The N bits constituting the data are distributed one bit at a time to N lanes, and B data b i×B ~b i×B+B-1 DAC8 simultaneously outputs i, where i is an integer equal to or greater than 0. Note that the number of bits N is not limited to the above value, and may be any value according to the number of input bits of the N-bit DAC8.

[0055] The output transceiver 6 shown in FIG. 1 receives the N-bit emphasis waveform pattern data b generated by the emphasis adding circuit 5. n is expanded into N×X lanes and output, where X is an integer equal to or greater than 2. In this embodiment, the output transceiver 6 is an output section of the FPGA, and outputs a digital signal of 0 or 1 from each output lane.

[0056] The MUX 7 is provided to increase the bit rate of the multi-value K PAM signal output from the N-bit DAC 8 in the subsequent stage, and multiplexes the output of the N×X lanes of the output transceiver 6 into N lanes to generate N-bit emphasis waveform pattern data b n Since the output of the N×X lanes of the output transceiver 6 is a digital signal of 0 or 1, the emphasis added to the PAM signal pattern by the emphasis adding circuit 5 does not disappear when the MUX7 takes in this digital signal at a specified clock.

[0057] The N-bit DAC8 receives the N-bit emphasis waveform pattern data b n The MUX 7 and the N-bit DAC 8 output an analog signal corresponding to the Kth value, that is, a multi-value K PAM signal, to the DUT 100. The MUX 7 and the N-bit DAC 8 may be separate entities or may be integrated. The PAM signal output from the N-bit DAC 8 is input to the DUT 100 as a test signal.

[0058] The DUT 100 is adapted to receive a test signal output from the signal generating device 1. The DUT 100 is also adapted to be capable of outputting a switching request for switching the emphasis added to the input test signal. The switching request is represented, for example, by the timing at which a switching request signal, which has two values, 0 level and 1 level, rises from 0 level to 1 level, or the timing at which it falls from 1 level to 0 level.

[0059] Examples of standards supported by the DUT100 include PCIe Gen1 to 6, USB3.1 to 4, DP1.4 to 2, CEI (Common Electrical Interface), IEEE802.3, InfiniBand, etc. For example, if the DUT100 is equipped with a Link Training and Status State Machine (LTSSM), the DUT100 is configured to output a switching request when a specific state transition occurs in the LTSSM.

[0060] Since a normal N-bit DAC can generate an arbitrary waveform like an arbitrary waveform generator (AWG), it is also possible to output a pattern of a PAM signal with emphasis added directly from the N-bit DAC 8 without using the emphasis adding circuit 5 of this embodiment. In this case, emphasis can be switched by rewriting the value of the RAM directly connected to the N-bit DAC. However, although it depends on the pattern length to be set, writing an emphasis waveform pattern to the RAM takes a considerable amount of time, on the order of several seconds to several tens of seconds, so in a configuration using an N-bit DAC as an AWG, emphasis cannot be switched at high speed.

[0061] In contrast, if the signal generating device 1 of this embodiment is used, it becomes possible to perform high-speed emphasis switching within 1 μs. Hereinafter, a configuration for switching the emphasis in the signal generating device 1 of this embodiment, that is, for switching the tap value, will be described.

[0062] 1 switches and sets M tap values ​​C(0), C(-1), . . . , C(1-M) for each FIR filter section 50 in response to an emphasis switching request from a DUT 100 to which a test signal has been input. The tap value setting section 9 includes an input transceiver 21, an emphasis switching instruction section 22, an emphasis setting table 23, and an emphasis changeover switch 24.

[0063] The input transceiver 21 outputs the switching request output from the DUT 100 to an emphasis switching instruction section 22 .

[0064] The emphasis setting table 23 stores a plurality of sets of tap values ​​C(0), C(-1), . . . , C(1-M) defined in the standard that the DUT 100 complies with. The emphasis setting table 23 may also store a set of tap values ​​C(0), C(-1), . . . , C(1-M) that are arbitrarily set by a user through an operation input to the operation unit 10.

[0065] The emphasis switching instruction unit 22 selects from the emphasis setting table 23 tap values ​​C(0), C(-1), ..., C(1-M) to be newly set in each FIR filter unit 50 in response to a switching request input from the DUT 100 via the input transceiver 21, and outputs the selected tap values ​​C(0), C(-1), ..., C(1-M) from the emphasis setting table 23.

[0066] For example, when the DUT 100 is equipped with an LTSSM, the emphasis switching instruction unit 22 may be configured to grasp from which state to which state the LTSSM has transitioned based on a switching request output from the DUT 100. In this case, the emphasis switching instruction unit 22 can output tap values ​​C(0) to C(1-M) corresponding to a specific state transition of the LTSSM from the emphasis setting table 23.

[0067] When the operation mode of the signal generating device 1 is set to the standard mode by a user's operation input to the operation unit 10, the emphasis changeover switch 24 outputs the tap values ​​C(0) to C(1-M) output from the emphasis setting table 23 to each FIR filter section 50 at a timing based on a switching request output from the DUT 100. As a result, new tap values ​​C(0) to C(1-M) are set in each FIR filter section 50.

[0068] On the other hand, when the operation mode of the signal generating device 1 is set to the user-defined mode by a user's operational input to the operation unit 10, the emphasis changeover switch 24 outputs the tap values ​​C(0) to C(1-M) arbitrarily set by the user's operational input to the operation unit 10 to each FIR filter section 50 at a timing arbitrarily set by the user's operational input to the operation unit 10. As a result, new tap values ​​C(0) to C(1-M) are set in each FIR filter section 50.

[0069] The data of the PAM symbols from nth to n+M-1th a n ~a n+M-1 are input to the DSP 52_0 and delay circuits 51_1 to 51_M-1 of each FIR filter unit 50 at the same clock timing. Also, M tap values ​​C(0) to C(1-M) are input to the data a of the n-th to (n+M-1)-th PAM symbols when the tap value setting unit 9 sets the tap values. n ~a n+M-1 The constant 1 input to the DSP 52_0 and the delay circuits 51_1 to 51_M-1 are input at the same timing as the constant 2 input to the DSP 52_0 and the delay circuits 51_1 to 51_M-1, and are continuously input to the DSP 52_0 and the delay circuits 51_1 to 51_M-1 until a new switching request occurs. N-1 and -0.5 are always input to DSP52_0 and DSP52_M.

[0070] The time required for switching the emphasis by the signal generating device 1 of this embodiment will be described below.

[0071] First, the output transceiver 6 receives the N-bit emphasis waveform pattern data b n into N×X lanes and output. Also, it takes about four clocks for the input transceiver 21 to output the switching request output from the DUT 100 to the emphasis switching instruction unit 22.

[0072] It takes about three clock cycles for the emphasis switching instruction section 22 to output the tap values ​​C(0) to C(1-M) to be set in each FIR filter section 50 from the emphasis setting table 23 after receiving a switching request from the input transceiver 21.

[0073] Furthermore, if the delay amount of the delay unit 54 of the DSP 52 is 1 UI and the number of taps M of the FIR filter unit 50 is 5, the total delay amount of the FIR filter unit 50 is (M+1)×3+2 clocks=20 clocks.

[0074] That is, the time required for switching the emphasis in the FPGA of the signal generating device 1 is about 31 clocks. Therefore, for example, if the test signal is a 32 Gbaud PAM4 signal and the operating clock frequency in the FPGA for this test signal is 125 MHz, the time for the above about 31 clocks is about 248 ns. In addition, there are delay times in hardware parts such as the MUX 7, the N-bit DAC 8, and the signal transmission / reception part of the DUT 100, but the delay time is about several ns to 10 ns even if all of them are added together. Therefore, the delay time considering the delay time in the FPGA and the delay time in the hardware part is estimated to be about 300 ns at most. Therefore, the signal generating device 1 of this embodiment can realize high-speed emphasis switching that satisfies the switching time of 1 μs or less required by PCIe.

[0075] Furthermore, the signal generating device 1 of this embodiment uses an FPGA with a higher operating clock frequency, which further reduces the processing time within the FPGA and enables even faster emphasis switching.

[0076] The operation unit 10 is for accepting operation input by a user, and is configured, for example, as a touch panel having a touch sensor for detecting a contact position by a touch operation on an input surface corresponding to a display screen of a display device. Alternatively, the operation unit 10 may be configured to include an input device such as a keyboard or a mouse. The operation input to the operation unit 10 is detected by a control unit 11. For example, the operation unit 10 allows a user to arbitrarily set the pattern information input to the pattern generation circuit 2, the coding information input to the encoding circuit 3, the amplitude information input to the symbol level conversion unit 4, the tap values ​​C(0), C(-1), . . . , C(1-M) input to the FIR filter unit 50, the selection of an operation mode, the selection of a standard compatible with the DUT 100, and the like.

[0077] The control unit 11 is composed of, for example, a microcomputer or a personal computer including a CPU (Central Processing Unit), a ROM (Read Only Memory), a RAM (Random Access Memory), and a HDD (Hard Disk Drive), and controls the operation of each of the above-mentioned components constituting the signal generating device 1 in accordance with a program pre-stored in the ROM.

[0078] An example of the process of an emphasis switching method using the signal generating device 1 of this embodiment will be described below with reference to the flowchart of FIG.

[0079] First, in response to a user's operation input to the operation unit 10, the control unit 11 performs initial settings for the pattern information to be input to the pattern generation circuit 2, the coding information to be input to the encoding circuit 3, the amplitude information to be input to the symbol level conversion unit 4, and the tap values ​​C(0), C(-1), . . . , C(1-M) to be input to the FIR filter unit 50 (step S1).

[0080] Next, in step S2, the pattern generation circuit 2 generates a PAM signal pattern consisting of a multi-value K of two or more values ​​based on the pattern information set in step S1. The encoding circuit 3 performs gray coding or precoding on the PAM symbols that constitute the pattern of the PAM signal generated by the pattern generation circuit 2 based on the coding information set in step S1. The symbol level conversion unit 4 converts the PAM symbols output from the encoding circuit 3 into data a with amplitude values ​​ranging from -1 to 1 based on the amplitude information set in step S1. n Convert to.

[0081] Next, the emphasis adding circuit 5 calculates the amplitude value data a in step S2 based on the tap value set in step S1 or in step S6 described later. n Then, emphasis is added to the converted PAM signal pattern using each FIR filter unit 50 to generate an emphasis waveform pattern (emphasis adding step S3).

[0082] The above emphasis adding step S3 includes a delay step, a multiplication step, an addition step, and an N-bit conversion step.

[0083] The delay step is the data a of the PAM symbols from the nth to the n+M-1th that make up the PAM signal pattern. n ~a n+M-1 Of these, data a from n+1 to n+M-1 n+1 ~a n+M-1 The previous data a n ~a n+M-2The data are delayed by a predetermined amount and output, and M tap values ​​C(0), C(-1), . . . , C(1-M) are output as data a n ~a n+M-1 These are steps in which the signals are output at the same timing.

[0084] The multiplication step is performed by multiplying the data a of the nth to (n+M-1)th PAM symbols output from the delay step. n ~a n+M-1 , C(1-M) output from the delay step.

[0085] The addition step is a step of generating an emphasis waveform pattern by adding the output values ​​of the multiplication step. The N-bit conversion step converts the output value of the multiplication step added by the addition step into an N-bit value from 0 to 2. N This is a step of converting the input signal into an integer value in the range of -1 to generate an N-bit emphasis waveform pattern.

[0086] Next, in step S4, the output transceiver 6 expands the N-bit emphasis waveform pattern output from the emphasis adding circuit 5 into N×X lanes and outputs it. The MUX 7 multiplexes the output of the output transceiver 6 into N lanes to restore the N-bit emphasis waveform pattern and outputs it to the N-bit DAC 8. The N-bit DAC 8 outputs an analog signal according to the N-bit emphasis waveform pattern restored by the MUX 7 to the DUT 100.

[0087] Next, the emphasis switching instruction section 22 determines whether or not a switching request has been output from the DUT 100 (step S5).

[0088] When a switching request is output from the DUT 100, the emphasis switching instruction unit 22 selects new M tap values ​​C(0), C(-1), . . . , C(1-M) to be set in each FIR filter unit 50 from the emphasis setting table 23, and causes the emphasis setting table 23 to output the selected new tap values ​​C(0), C(-1), . . . , C(1-M) and sets them in each FIR filter unit 50 (tap value setting step S6). That is, in the tap value setting step S6, the emphasis switching instruction unit 22 switches the tap values ​​C(0), C(-1), . . . , C(1-M) already set in each FIR filter unit 50 to the new tap values ​​C(0), C(-1), . . . , C(1-M) in response to the switching request and sets them in each FIR filter unit 50. When the tap value setting step S6 is executed, the processes from step S3 onwards are executed again.

[0089] As described above, the signal generating device 1 according to the present embodiment can add emphasis to a PAM signal pattern consisting of two or more values ​​by using at least one FIR filter section 50. Moreover, the signal generating device 1 according to the present embodiment can switch the final output waveform at high speed by switching M tap values ​​C(0), C(-1), . . . , C(1-M) input to each FIR filter section 50. Moreover, the signal generating device 1 according to the present embodiment can flexibly increase the number of taps M and the number of output bits N while realizing high-speed emphasis switching when the number of required taps increases due to future standard trends by configuring the emphasis adding circuit 5 having at least one FIR filter section 50 on an FPGA or ASIC.

[0090] Furthermore, the signal generating device 1 of this embodiment can select tap values ​​C(0), C(-1), ..., C(1-M) from the emphasis setting table 23 in response to a switching request from the DUT 100, and set the selected tap values ​​C(0), C(-1), ..., C(1-M) to each FIR filter section 50.

[0091] Furthermore, in the signal generating device 1 according to this embodiment, each FIR filter section 50 is configured using a DSP 52, so that FPGA or ASIC resources can be utilized efficiently, and if the number of required taps increases due to future standard trends, the number of taps M and the number of output bits N can be flexibly increased.

[0092] Furthermore, the signal generating device 1 according to this embodiment is configured to input an N-bit emphasis waveform pattern from the emphasis adding circuit 5 to an N-bit DAC 8 to generate a test signal for the DUT 100. This makes it possible to realize a signal generating device that achieves both faster bit rates and the addition of emphasis, and has high waveform performance compatible with multi-values. [Explanation of symbols]

[0093] 1. Signal Generator 2 Pattern generation circuit 3 Encoding Circuit 4 Symbol level conversion section 5 Emphasis adding circuit 6 Output Transceiver 7 MUX 8 N-bit DAC 9 Tap value setting section 10 Control section 11 Control section 21 Input Transceiver 22 Emphasis switching indicator 23 Emphasis setting table 24 Emphasis switch 50 FIR filter section 51 Delay section 51_1~51_M-1 Delay circuit 52,52_0~52_M DSP 53 Multiplier 54 Delay Unit 55 Adder 60 FIR Filters 100 DUT

Claims

1. an emphasis adding circuit (5) including at least one FIR filter section (50) for adding emphasis to a PAM signal pattern having two or more values ​​to generate an emphasis waveform pattern; a tap value setting unit (9) for switching and setting M tap values ​​C(0), C(−1), ..., C(1-M) in each of the FIR filter units in response to an emphasis switching request from the device under test (100); Each of the FIR filter units includes: a delay unit (51) which delays the n+1th to n+M-1th data out of the nth to n+M-1th data constituting the pattern of the PAM signal by a predetermined delay amount with respect to the previous data, and outputs the tap values ​​C(0), C(-1), ..., C(1-M) at the same timing as the nth to n+M-1th data, respectively; a plurality of multipliers (53) for multiplying the n-th to (n+M-1)-th data output from the delay unit by the tap values ​​C(0), C(-1), ..., C(1-M) output from the delay unit, respectively, and outputting the result; and a plurality of adders (55) for adding output values ​​of the plurality of multipliers to generate the emphasis waveform pattern, A signal generating device, wherein each of the FIR filter sections is configured on an FPGA (Field Programmable Gate Array) or an ASIC (Application Specific Integrated Circuit).

2. The tap value setting unit an emphasis setting table (23) that stores a plurality of sets of the tap values ​​C(0), C(−1), . . . , C(1-M) defined by a standard; an emphasis switching instruction unit (22) that selects, in response to the switching request from the device under test, tap values ​​C(0), C(-1), ..., C(1-M) to be newly set in each of the FIR filter units from the emphasis setting table, and outputs the selected tap values ​​C(0), C(-1), ..., C(1-M) from the emphasis setting table.

3. 3. The signal generating device according to claim 1, wherein the plurality of multipliers and the plurality of adders are configured within a DSP (Digital Signal Processor) (52).

4. An N-bit DAC (8) that outputs an analog signal corresponding to the emphasis waveform pattern output from the emphasis adding circuit to the device under test, The FIR filter unit includes: The output values ​​of the multipliers added by the adders are between 0 and 2. Ｎ 3. The signal generating device according to claim 1, further comprising an N-bit conversion unit (52_M, 52_0) for converting the emphasis waveform pattern of N bits into an integer value in the range of -1.

5. an emphasis adding step (S3) in which at least one FIR filter unit (50) configured on an FPGA (Field Programmable Gate Array) or an ASIC (Application Specific Integrated Circuit) adds emphasis to a PAM signal pattern consisting of two or more values ​​to generate an emphasis waveform pattern; A tap value setting step (S6) of switching and setting M tap values ​​C(0), C(−1), ..., C(1-M) in each of the FIR filter sections in response to an emphasis switching request from the device under test (100), The emphasis adding step includes: a delay step of delaying the n+1th to n+M-1th data out of the nth to n+M-1th data constituting the pattern of the PAM signal by a predetermined delay amount with respect to the previous data, and outputting the tap values ​​C(0), C(-1), ..., C(1-M) at the same timing as the nth to n+M-1th data, respectively; a multiplication step of multiplying the n-th to (n+M-1)-th data output from the delay step by the tap values ​​C(0), C(-1), ..., C(1-M) output from the delay step, respectively, and outputting the result; an adding step of adding output values ​​of the multiplication step to generate the emphasis waveform pattern.

6. The tap value setting step includes:

6. The emphasis switching method according to claim 5, further comprising the steps of: selecting tap values ​​C(0), C(-1), ..., C(1-M) to be newly set in each of the FIR filter sections from an emphasis setting table (23) that stores a plurality of sets of the tap values ​​C(0), C(-1), ..., C(1-M) defined by a standard, in response to the switching request from the device under test; and outputting the selected tap values ​​C(0), C(-1), ..., C(1-M) from the emphasis setting table.

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