Protecting semiconductor switches in switching power converters

Abstract

To provide driver circuitry for protecting semiconductor switches in switching power converters.SOLUTION: In a switch control system, a switch controller 106 includes: a drive signal generator 126 coupled to a control input of a power switch 102 and configured to provide a drive signal UD 431 to the control input; a sense terminal 183 coupled to a main terminal of the power switch; a current mirror coupled to the sense terminal and configured to mirror a current input into the sense terminal during turn-off; and a switch fault detector 125 having a first current comparator configured to compare a current signal received from the current mirror with a first current threshold and output a first signal representative of a result of the comparison, and a second comparator configured to compare a signal received from the sense terminal with a turn-on threshold and output a second signal representative of a result of the comparison. The turn-on threshold represents a highest voltage of the main terminal during turn-on, and the first current threshold represents a highest voltage of the main terminal during turn-off.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates generally to protecting semiconductor switches in switching power converters. [Background technology]

[0002] Electronic devices use power for operation. Switching power converters are generally used to convert an unregulated or loosely regulated input to a more tightly regulated output by controlling the transfer of power across an energy transfer element. In addition to the energy transfer element, a switching power converter generally includes at least one power switch and a controller that controls the power switch. The controller switches the power switch to control the transfer of energy in the energy transfer element to achieve the regulated output. The controller generally receives a feedback signal representative of the output and varies one or more switching parameters in a closed-loop control scheme to regulate the output to a desired amount. In different embodiments, the desired output can be achieved, for example, by varying the switching duty cycle (the ratio of the on-time of the switch to the total switching period), varying the switching frequency, and / or varying the number of on-time pulses per unit time of the power switch.

[0003] There are many circumstances that can result in failure of a switching power converter. For example, in many applications, high voltages are applied to a power switch and large currents are conducted between its main terminals. If the power switch is not properly designed to withstand the high voltages or carry the large currents, the power switch may be damaged. Furthermore, even properly designed power switches may be damaged under improper operating conditions, including power crosses, electrostatic discharge events, power surges, lightning strikes, and others. Depending on the operating circumstances, failure of the power switch may not only lead to failure of the power converter, but also to failure of other equipment and loss of property and life.

[0004] Non-limiting and non-exhaustive embodiments of the present invention are described with reference to the following figures, in which like reference numerals in different figures refer to like parts unless otherwise specified. [Brief description of the drawings]

[0005] [Figure 1] 1 illustrates an example switch control system including a switch control device including a switch anomaly detector according to one embodiment of the present disclosure. [Figure 2A] 4 illustrates example waveforms for drive signals and switch voltages under normal conditions and short circuit or overcurrent conditions according to one embodiment of the present disclosure. [Figure 2B] 4 illustrates example waveforms for drive signals and switch voltages under normal and overvoltage conditions according to one embodiment of the present disclosure. [Figure 3A] 2 illustrates an example switch anomaly detector for detecting an over-voltage condition of the switch control device of FIG. 1 according to one embodiment of the disclosure. [Figure 3B] 3B illustrates a timing diagram of example waveforms of various signals of FIG. 3A in accordance with one embodiment of the present disclosure. [Figure 3C] 2 illustrates an example switch fault detector for detecting an over-voltage condition and blanking circuit of the switch control device of FIG. 1 according to one embodiment of the disclosure. [Figure 4A] 2 illustrates an example switch anomaly detector for detecting an overcurrent or short circuit condition of the switch control device of FIG. 1 according to one embodiment of the disclosure. [Figure 4B] 2 illustrates another example switch anomaly detector for detecting an overcurrent or short circuit condition of the switch control device of FIG. 1 in accordance with one embodiment of the present disclosure. [Figure 4C] 4C shows a timing diagram of example waveforms of various signals in FIG. 4A and FIG. 4B according to one embodiment of the present disclosure. [Figure 4D]2 illustrates a discharge circuit and another exemplary switch fault detector for detecting an overcurrent or short circuit condition of the switch control device of FIG. 1 according to one embodiment of the present disclosure. [Diagram 5] 1 illustrates an example lead frame of an integrated circuit package showing an example inductive coupling between dies according to one embodiment of the present disclosure. [Figure 6] 1 illustrates an example power converter using a switch control device including a switch anomaly detector according to one embodiment of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0006] Corresponding reference characters indicate corresponding components throughout the several views of the drawings. It should be understood that similarly named and numbered elements combine and function similarly. Those skilled in the art will appreciate that the elements in the figures are drawn for simplicity and clarity, and have not necessarily been drawn to scale. For example, the dimensions of some elements in the figures may be exaggerated relative to other elements to facilitate a better understanding of the various embodiments of the present invention. Furthermore, common but well-understood elements that are useful or necessary in commercially suitable embodiments are often not drawn in order to avoid cluttering the figures of these various embodiments of the present invention.

[0007] An example of a switch anomaly detector for a switch control device is described herein. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, it will be apparent to one skilled in the art that the specific details may not necessarily be used in implementing the present invention. In other instances, well-known materials or methods have not been described in detail to avoid obscuring the present invention.

[0008] Reference herein to "one embodiment," "embodiment," "one example," or "example" means that a particular feature, structure, or characteristic described in connection with the embodiment or example is included in at least one embodiment of the invention. Thus, the use of the phrases "in one embodiment," "in an embodiment," "one example," or "example" in various places herein does not necessarily all refer to the same embodiment or example. Furthermore, particular features, structures, or characteristics may be combined in any suitable combination and / or subcombination in one or more embodiments or examples. Particular features, structures, or characteristics may be included in an integrated circuit, electronic circuit, combinational logic circuit, or other suitable component that provides the described functionality. In addition, it is understood that the figures provided herewith are for illustrative purposes to persons skilled in the art and that the drawings are not necessarily drawn to scale.

[0009] In a switching power converter, a controller may set a power switch to a more conductive ON (i.e., closed) state or a substantially non-conductive OFF (i.e., open) state. Controllers are generally used in conjunction with protection circuitry that detects and / or prevents various conditions that may damage the power switches and power converter. Overvoltage and overcurrent conditions are examples.

[0010] Overvoltage conditions generally occur when the power switch is off or during turn-off (i.e., transition from on to off). Active clamping aims to prevent overvoltages from occurring across the power switch by active control of the power switch or a circuit associated with the power switch. For example, in some embodiments, a drive signal input to the control terminal (e.g., gate or base) of the power switch can be actively controlled to limit the voltage at the main terminal (e.g., collector or drain) during turn-off. In many embodiments, it is common to use a transient voltage suppressor (TVS) diode connected between the collector / drain and the gate. There are also active clamping techniques that use a capacitively compensated resistive divider to provide the detected power switch voltage to a gate driver. The divided voltage, which serves as the detected power switch voltage, is compared to a voltage threshold by a comparator that controls the current / voltage provided to the control terminal of the power switch to reduce the turn-off overvoltage of the power switch.

[0011] An overcurrent or short circuit condition generally occurs when the power switch is on or during turn-on (i.e., transition from off to on). In some cases, the current flowing between the main terminals of the power switch is estimated by measuring the voltage across the main terminals of the power switch. Under normal operating conditions, the voltage across the main terminals of the power switch should drop quickly to a relatively low level during turn-on and remain at the low level while the power switch is on. However, under a short circuit or overcurrent condition, the voltage across the power switch may drop initially but then rise after some period of time. In other overcurrent conditions, the voltage across the power switch may drop during turn-on, but the rate of drop may be lower than under normal operating conditions. An overcurrent condition thermally stresses the power switch and may damage it after a relatively short period of time.

[0012] As mentioned above, the control device is generally used in combination with a protection circuit that detects and / or responds to an overvoltage or overcurrent condition, or avoids an overvoltage or overcurrent condition and protects the power switch from damage. However, as the operating voltage of the power converter increases, it becomes more difficult to provide overvoltage and overcurrent protection. In particular, an overcurrent or short circuit is generally detected when the voltage across the main terminals of the power switch is low, or even approaching zero. When the voltage across the power switch is excessively high, an overvoltage is inevitably detected. By way of illustration, modern high-voltage IGBTs can withstand voltages of 3.3 kV or more, and overvoltages are still higher in this context. The protection circuit must therefore be able to tolerate a very wide range of operating parameters. As a result, the protection circuit is often complex and has a low level of integration. Furthermore, transient voltage suppressor (TVS) diodes are generally expensive.

[0013] In one embodiment, the switch control device includes a switch fault detector that both detects and responds to an overcurrent or short circuit condition and actively clamps the voltage across the power switch to prevent an overvoltage condition. In some implementations, the fault detector may receive a signal - at a single detection terminal - representative of the current flowing through the power switch and the voltage across the main terminals of the power switch. When the power switch is off, the signal received at the detection terminal represents the voltage across the power switch and the switch fault detector prevents the overvoltage condition. When the power switch is on, the signal received at the detection terminal represents the current flowing through the power switch and the switch fault detector detects the overcurrent and / or short circuit condition and responds accordingly.

[0014] For example, in some embodiments, the signal representative of the voltage across the main terminal of the power switch is a current signal received at the sense terminal. The sensed current signal representative of the voltage across the power switch is compared to a variable current reference. When the sensed current signal is greater than the current reference, the switch fault detector outputs a clamp signal to control the control current of the power switch. Thus, the switch controller provides an active clamp for overvoltage conditions.

[0015] As another example, in some embodiments, the signal representative of the current through the switch is a voltage signal received at the detection terminal. This voltage signal is compared to a voltage reference. When the detection voltage signal is greater than the voltage reference, the switch fault detector outputs a fault signal to turn off the power switch. Thus, the switch control device provides overcurrent and / or short circuit protection.

[0016] 1 shows an example switch control system 100 including a switch controller 106 and a power switch 102. The switch controller 106 includes a switch anomaly detector 125. The switch control system 100 may be part of a power converter that receives an input voltage and transfers electrical energy from the input to a load through an energy transfer element by controlling the switching of the power switch 102.

[0017] In the illustrated example, the power switch 102 is an insulated-gate bipolar transistor (IGBT). Other power switches may be used in other embodiments. For example, metal-oxide-semiconductor field-effect transistors (MOSFETs), bipolar transistors, injection enhancement gate transistors (IEGTs), and gate turn-off thyristors (GTOs) may be used. Additionally, the switch control system 100 may be used with power switches based on silicon (Si), gallium nitride (GaN) semiconductors, or silicon carbide (SiC) semiconductors.

[0018] The system controller 104 is configured to receive a system input 108 and to provide an input signal U to the switch controller 106. IN 110. The input signal U IN 110 is received at an input terminal IN117 of the switch controller 106. IN 110 may be a command signal that instructs the switch controller 106 to turn on the power switch 102 or to turn off the power switch 102. For example, the input signal U IN 110 may be a square pulse waveform with logic high and logic low sections of different durations. A logic high section may indicate, for example, that the power switch 102 is to be turned on, whereas a logic low section may indicate that the power switch 102 is to be turned off.

[0019] The switch controller 106 controls the power switch 102 and includes a driver interface 112 and a drive circuit 116. In some cases, both the driver interface 112 and the system controller 104 are referenced to a primary reference potential 122, while the drive circuit 116 is referenced to a secondary reference potential 123. The driver interface 112 and the drive circuit 114 are communicatively coupled through a communication link 114. The communication link 114 galvanically isolates the driver interface 112 and the drive circuit 116. In the illustrated embodiment, the communication link 114 is bidirectional. In other embodiments, communication between the driver interface 112 and the drive circuit 114 may be unidirectional. In some embodiments, the communication link 114 is implemented using, for example, a signal transformer, a coupled inductor, or other inductive coupling.

[0020] In operation, the driver interface 112 receives an input signal U from the system controller 104. IN 110. Based on the interpretation, the driver interface 112 transmits a command signal to the drive circuit 116 via a communication link 114. The command signal may, for example, instruct the drive circuit 116 to drive the power switch 102 on or off. The drive circuit 116 transmits the drive signal U to control the switching of the power switch 102. D131. The illustrated embodiment of the driver circuit 116 includes a transceiver 124, a switch fault detector 125, and a drive signal generator 126. The transceiver 124 receives and interprets communications from the driver interface 112 and provides a drive status signal 127 to the switch fault detector 125 and the drive signal generator 126. The drive status signal 127 instructs the drive signal generator 126 to control the power switch 102 on or off. For example, the drive status signal 127 can be a square pulse waveform with logic high and logic low sections of variable duration. In this example, the power switch 102 is switched on by the drive signal generator 126 when the drive status signal 127 is logic high and is switched off when the drive status signal 127 is logic low. In the illustrated example, the drive status signal 127 is a single signal in a single channel. In other examples, the drive status signal 127 may be communicated as multiple signals and / or on multiple channels, for example, one signal on one channel may instruct the drive signal generator 126 to turn the power switch 102 on and another signal on another channel may instruct the drive signal generator 126 to turn the power switch 102 off.

[0021] As will be further described, the transceiver 124 is coupled to receive a fault signal 133 indicative of an overcurrent or short circuit from the switch fault detector 125. The transceiver 124 relays notification of the fault to the driver interface 112 via the communication link 114.

[0022] The drive signal generator 126 is coupled to receive the drive status signal 127 and is coupled to output a gate high signal UH129 and a gate low signal UL130 to control the switching of the power switch 102. The gate high signal UH129 is output from a gate high terminal GH119 of the switch controller 106 to switch the power switch 102 on. The gate low signal UL130 is output from a gate low terminal GL120 of the switch controller 106 to switch the power switch 102 off. The gate high signal UH129 and the gate low signal UL130 can be voltage signals or current signals. The drive signal UD131 is a combination of the gate high signal UH129 and the gate low signal UL130. The resistor 135 and the resistor 136 are coupled to the gate high terminal GH119 and the gate low terminal GL120, respectively. The off-switching current I GL 160 is shown as the current into the gate low terminal GL 120. In other words, the off switching current IGL 160 is the gate current of the power switch 120 when the power switch 102 is off.

[0023] The illustrated embodiment of switch controller 106 further includes a return terminal COM 121 and an emitter terminal VEE 168. Return terminal COM 121 is coupled to secondary return 123 and provides a return reference for circuitry coupled to the secondary side of switch controller 106. Emitter terminal VEE 168 is coupled to the emitter / source of power switch 102. In the illustrated embodiment, power switch 102 is an IGBT, which includes collector, emitter, and gate terminals. However, other power switches may include drain, source, and gate terminals, or collector, emitter, and base terminals.

[0024] The switch fault detector 125 is coupled to receive the drive status signal 127 and a detection signal from the detection terminal SNS 118 of the switch controller 106. The detection signal may be a voltage signal (i.e., a voltage VSNS at the detection terminal SNS 118) or a current signal (i.e., a detection current I SNS161). The switch fault detector 125 outputs a fault signal 133 and a clamp signal 134 based on the detection signal at the detection terminal SNS 118 and the drive state 127. As described in more detail below, when the switch fault detector 125 is monitoring for an overcurrent or a short circuit, i.e., when the power switch 102 is in an on state or is turning on, the impedance of the detection terminal SNS 118 is high. In contrast, when the switch fault detector 125 is involved in active clamping of the power switch 102, i.e., when the power switch 102 is in an off state or is turning off, the impedance of the detection terminal SNS 118 is low. For example, in some embodiments, when the power switch 102 is in an OFF state or is being switched OFF, the input impedance of the sense terminal SNS 118 is less than 200 kilohms (e.g., less than 10 kilohms), whereas when the power switch 102 is in an ON state or is being switched ON, the input impedance of the sense terminal SNS 118 is greater than 10 megahms (e.g., greater than 100 megahms). The switch control system 100 further includes a resistor RC1 137 coupled between the sense terminal SNS 118 and the collector / drain of the power switch 102. In operation, the voltage VCE 141 across the power switch 102 drives a current through the resistor RC1 137. At least a portion of the current through the resistor RC1 137 is a sense current I SNS 161 into the sense terminal SNS 118. The switch control system 100 further includes a resistor RC2 138. One end of the resistor RC2 138 is coupled between the sense terminal SNS 118 and the resistor RC1 137. The other end is coupled to the return terminal COM 121 or the emitter terminal VEE 168. Resistors RC1 137 and RC2 138 together form a voltage divider that converts the voltage across the power switch 102 into a sense signal.

[0025] Optionally, the power switch 102 may include a sense terminal 183 (indicated by a dashed line). The sense terminal 183 detects a current IESNS 192. If the power switch 102 includes a sense terminal 183, resistors RS1 139 and RS2 140 may be coupled to the sense terminal 183. The voltage across resistor RS1 139 is proportional to the total switch current IC 142. Resistor RS2 is used to couple the voltage across RS1 to the sense terminal SNS 118. In the embodiment shown, resistor RS1 139 is coupled to the sense terminal 183 and the emitter / source of the power switch 102. Resistor RS2 140 is coupled to the sense terminal 183 of the power switch 102 between resistor RC1 137 and the sense terminal SNS 118 of the switch controller 106. During overcurrent and / or short circuit detection, the input impedance of the sense terminal SNS 118 is high and the voltage at the SNS terminal 118 is proportional to the switch current I C 142. Furthermore, the detection voltage VSNS at the detection terminal 183 is ESNS 192 and the switch current I C 142. In embodiments where sense terminal 183 and resistors RS1 129 and RS2 140 are used, resistor RC2 138 is optional.

[0026] During operation, switch fault detector 125 monitors the voltage or current at detection terminal SNS 118 to determine if an over-voltage, over-current, or short circuit condition occurs.

[0027] Overvoltage Protection

[0028] When the drive status signal 127 indicates that the power switch 102 should be off, the switch fault detector 125 detects a current I flowing into the detection terminal SNS 118. SNS 161 is coupled to detect an overvoltage condition. The sense terminal SNS 118 has a low input impedance. Resistor RC1 137 couples the voltage VCE 141 across the power switch 102 to the sensed current I SNSIf an overvoltage condition is detected, the switch fault detector 125 uses a clamp signal 134 to clamp the voltage across the power switch 102 and slow down the turn-off speed of the power switch 102. In response to an indication in the clamp signal 134, the drive signal generator 126 uses a gate low signal UL 130 to lower the voltage VCE 141 across the power switch 102.

[0029] The value of resistor RC1 137 is selected to select the level of voltage VCE141 across the power switch 102 that triggers clamp signal 134 (i.e., adjusts the clamp level of switch voltage VCE141). In particular, switch fault detector 125 may be provided with a fixed preset threshold level, and resistor RC1 137 may specify the voltage of voltage VCE141 above this fixed threshold. Thus, switch fault detector 125 may be used in different operating conditions and / or in combination with different power switches 102.

[0030] As described above, when the switch fault detector 125 is monitoring for an overvoltage, the input impedance of the switch controller 106 at the detection terminal SNS 118 is low. In other words, when the drive state 127 indicates that the power switch 102 should be off, the impedance of the detection terminal SNS 118 is low. A resistance for resistor RC2 138 may be selected such that the impedance of resistor RC2 138 is much greater than the input impedance of the switch controller 106 at the detection terminal SNS 118. For example, the input impedance of the switch controller 106 may be approximately 4-5 kilohms and the impedance of resistor RC2 138 is approximately 22-82 kilohms. In one example, resistor RC1 may be approximately 1-2 megahms.

[0031] Overcurrent or short circuit protection

[0032] When the drive status signal 127 indicates that the power switch 102 should be on, the switch fault detector 125 is coupled to detect an overcurrent and / or short circuit condition based on the voltage at the sense terminal SNS 118. When the power switch 102 is on or turning on, the impedance of the sense terminal SNS 118 is high and the voltage VSNS is proportional to the switch current I C 142. In an embodiment in which the power switch 102 includes a sense terminal 183, the current I ESNS 192 shifts the potential across resistors RCS1 139 and RS2 140 to a corresponding level, changing the voltage SNS at the sense terminal SNS 118. Again, the current I ESNS 192 is the switch current I C 142. In an embodiment in which the power switch 102 does not include a sense terminal 183, the relatively low switch voltage VCE 141 drives a current through resistor RC1 137. The current through resistor RC1 137 also faces impedance provided by the input impedance of the switch controller 106 and resistor RC2 138, decreasing the switch current I C 142. In the on-state, the switch voltage VCE 141 is proportional to the on-state impedance of the power switch 102 and the switch current I C It is related to the product with 142.

[0033] If an overcurrent or short circuit is detected, the switch fault detector 125 outputs a fault signal 133 to the transceiver 124. In response to the fault signal 133, the transceiver 124 changes the drive status signal 127 to instruct the drive signal generator 126 to switch the power switch 102 off. In response, the drive signal generator 126 switches the power switch 102 off. The transceiver 124 may further output the fault signal 133 to the driver interface 112. The driver interface 112 relays an indication of the fault to the system controller 104.

[0034] The impedance of resistors RC1 137 and RC2 138 (or, optionally, RS1 139 and RS2 140) may be selected based in part on the internal voltage reference V1 of the switch anomaly detector 125 and the desired desaturation level of the power switch 102. The high input impedance of the detection terminal SNS 118 is in parallel with resistor RC2 138 (or in parallel with resistors RS1 139 and RS2 140). Resistors RC1 137 and RC2 138 are used to provide the detection voltage SNS, and the value of resistor RC2 138 adjusts the desaturation level with respect to the internal reference voltage V1 of the switch anomaly detector 125. An example is further described in relation to FIG. 4A. The larger the value of resistor RC2 138, the lower the desaturation level of the power switch 102. In other words, the larger the value of resistor RC2 138, the smaller the switch current IC 142 that triggers the anomaly signal 133. Similarly, when resistors RS1 139 and RS2 140 provide the detection voltage SNS, resistor RS2 140 adjusts the desaturation level for the power switch 102 relative to an internal reference voltage V1 of the switch anomaly detector 125, and resistor RS1 139 converts the current IENSN 192 to a voltage within a voltage range for a Safe Operation Area (SOA) specification for each of the power switches 102. An example is further described in connection with FIG.

[0035] Monitoring for both overcurrent and overvoltage at the same detection terminal SNS 118 is a very challenging task. For overcurrent detection, the detection voltage VSNS, which represents the switch current IC 142, may range from 0.2V to 0.5V during turn-on and during the ON state of the power switch 102. However, for overvoltage detection, the threshold for triggering the overvoltage may be on the order of several thousand volts, e.g., 1050V, during turn-off and during the OFF state of the power switch 102. Thus, the detection terminal 118 is exposed to a wide voltage range. By detecting the switch voltage VCE 141 as a current signal ISNS 161 during turn-off and during the OFF state, the speed of the control scheme may be increased.

[0036] FIG. 2A shows a timing diagram 200 including example waveforms for the drive signal 231 and the switch voltage VCE 241 under normal, short-circuit, and overcurrent conditions during an OFF-to-ON transition of a power switch.

[0037] The upper waveform shows an exemplary drive signal UD 231 that controls the switching on and off of the power switch. During the off period, the drive signal UD 231 is substantially equal to the off voltage VOFF 244. During the on period, the drive signal UD 231 is substantially equal to the on voltage VON 243.

[0038] The switch voltage VCE241 (i.e., the voltage across the power switch) is shown at the bottom of the timing diagram 200. The bottom left portion shows an example switch voltage VCE241 under normal conditions, while the bottom right portion shows an example switch voltage VCE241 under short circuit and overcurrent conditions. As shown in the bottom left portion of the timing diagram 200, after the power switch transitions from off to on, the switch voltage VCE241 drops rapidly to substantially zero. In contrast, under a short circuit condition, the switch voltage VCE241 may initially drop but then rise again after a period of time. In one example, the switch voltage VCE241 may drop to its value during normal conditions but then rise. Under an overcurrent condition, the switch voltage VCE241 may drop, albeit at a much slower rate than under normal conditions.

[0039] 2B shows a timing diagram 201 including example waveforms for the drive signal 231 and the switch voltage VCE241 during a transition from on to off of the power switch, under normal and overcurrent conditions. The upper waveform shows an example drive signal UD231 that controls the switching on and off of the power switch. During the on period, the drive signal UD231 is substantially equal to the on voltage VON243. During the off period, the drive signal UD231 is substantially equal to the off voltage VOFF244.

[0040] The switch voltage VCE241 (i.e., the voltage across the power switch) is shown at the bottom of the timing diagram 200. The bottom left portion shows an example switch voltage VCE241 under normal conditions, while the bottom right portion shows an example switch voltage VCE241 under an overvoltage condition. As shown in the bottom left portion of the timing diagram 201, during an ON-to-OFF transition, the switch voltage VCE241 rises from approximately 0 volts but remains below the reference level 246. In this example, a switch voltage VCE241 greater than the reference level 246 indicates an overvoltage condition. As shown in the bottom right portion of the timing diagram 201, under an overvoltage condition, the switch voltage VCE241 rises from 0 volts to a level greater than the reference level 246, indicating an overvoltage condition.

[0041] 3A shows an example of circuitry within switch fault detector 325 for detecting an over-voltage condition, and an example of the coupling between such circuitry and drive signal generator 326. Note that in addition to circuitry for detecting an over-voltage condition, switch fault detector 325 further includes circuitry for detecting and protecting against over-current and short-circuit conditions. For purposes of illustration, such circuitry is not shown in FIG. 3A. However, the circuitry for detecting an over-voltage condition in FIG. 3A may be combined with circuitry for detecting over-current and short-circuit conditions, for example, as shown in FIG. 4A.

[0042] The circuitry within the switch controller 306 includes a drive signal generator 326 and a switch fault detector 325. The drive signal generator 326 includes an on switch 349 and an off switch 350. Both the on switch 349 and the off switch 350 are shown as n-type transistors. One end of the on switch 349 is coupled to a source voltage VISO, and the other end is coupled to a gate high terminal GH 319. The on switch 349 is controlled by a drive status signal 327 via a driver 351. In operation, when the drive status signal 327 indicates that the power switch 302 is switched on (e.g., the drive status signal 327 is logic high), the driver 351 controls the on switch 349 to a conductive state and provides a gate high signal UH 329 to the gate high terminal GH 319 and the resistor 335. At the same time, the off switch 350 is controlled to be off, and the drive signal 331 is substantially equal to the gate high signal UH 329. In response, the power switch 302 is turned on.

[0043] The off switch 350 is coupled to the gate low terminal GL 320 and to the return COM, and is controlled by the drive state signal 327 via an inverter 385 and a current source 348. The inverter 385 receives the drive state signal 327 and controls the current source 348 based on the drive state signal 327. As shown, the current source 348 is coupled to a control terminal of the off switch 350. In operation, when the drive state signal 327 indicates that the power switch 302 is switched off (e.g., the drive state signal 327 is logic low), the inverter 385 controls the current source 348 to provide a current to switch the off switch 350 on. The off switch 350 provides the gate low signal UL 330 to the gate low terminal 320 and to the resistor 336. The on switch 349 is controlled to be off. The drive signal U D 331 becomes substantially equal to the gate low signal UL 330. The power switch 302 turns off in response. Note that the current into the gate low terminal 320 may be referred to as the gate low current IGL 360.

[0044] The drive signal generator 326 further includes transistors 352 and 353 coupled together as a current mirror. The drain of the transistor 352 is coupled to receive the clamp signal 334 from the switch anomaly detector 325. The drain of the transistor 353 is coupled to a control terminal (e.g., gate) of the off switch 350. As will be further explained, the transistors 352 and 353 mirror the clamp signal 334 and sink current from the control (e.g., gate) terminal of the off switch 350. Because less current is input to the control terminal of the off switch 350, the gate current IGL 360 is reduced. This in turn reduces the rate at which the power switch 302 switches off and the rate of change of the switch voltage VCE 341.

[0045] The switch fault detector 325 shown detects an over-voltage condition, and when an over-voltage condition is detected, the switch fault detector 325 and the drive signal generator 326 actively clamp the switch voltage VCE341. More specifically, the switch fault detector 325 receives a detection signal at a detection terminal SNS318. For over-voltage detection, the switch voltage VCE341 is converted to a current signal shown as a detection current ISNS361. A resistor RC1 337 is coupled to the detection terminal SNS318 and the collector / drain of the power switch 302 to convert the switch voltage VCE241.

[0046] The switch fault detector 325 includes a current source 358, transistors M1 354, M2 355, M3 356, and M4 357, and a current driver 359. The current source 358 is a variable current source and is coupled to receive the drive status signal 327 and the clamp signal 334. The current source 358 further generates a current I in response to the drive status signal 327 and the clamp signal 334. REF Change the magnitude of the current I from the current source 358. REF Details regarding the changes in are provided in the description of FIG. 3B.

[0047] Transistors M1 354, M2 355, M3 356, and M4 357 are coupled together to form a current mirror that can be switched on or off depending on the state of the drive status signal 327. In particular, transistors M1 354, M2 355, and M4 357 are n-type transistors, while transistor M3 356 is a p-type transistor. The gates of transistors M1 354 and M2 355 and the drains of transistors M3 356 and M4 357 are coupled together. The drain of transistor M1 354 and the source of transistor M3 356 are coupled to sense terminal SNS 318, and the drain of transistor M2 355 is coupled to current source 358 and current driver 359. Additionally, the sources of transistors M1 354, M2 355, and M4 357 are coupled to return COM. The gates of transistors M3 356 and M4 357 are coupled together and coupled to receive the drive status signal 327.

[0048] The current driver 359 is an amplifier and / or current buffer coupled to output a version of the difference between the current IREF and the mirrored sensed current through transistor M2 355. In operation, the switch fault detector 325 receives a drive status signal 327 at the gates of transistors M3 356 and M4 357. The drive status 327 specifies whether the switch fault detector 325 detects an over-voltage or over-current / short circuit condition. In particular, when the drive status signal 327 is logic low - indicating that the power switch 302 is going or switching off - transistor M3 356 is on and transistor M4 357 is off. A low input impedance current mirror is formed by transistors M1 354, M2 355, and M3 356. This low input impedance current mirror is "seen" from the sense terminal SNS 318. The current flowing through the sense terminal SNS 318 and the current mirror is used in the active clamping process. In contrast, when the drive status signal 327 is logic how-indicating that the power switch 302 is to turn on or be switched on-transistor M3 356 is off and transistor M4 357 is on. Transistors M1 354, M2 355, and M3 356 do not form a current mirror and a high input impedance is "seen" from the sense terminal SNS 318. Other circuitry, such as that shown in Figures 4A, 4B, and 4D, detects and protects against overcurrent and short-circuit conditions.

[0049] In the embodiment shown, when the drive status signal 327 indicates that the power switch 302 should be off or should be switched off, the switch fault detector 325 is coupled to detect the over-voltage condition using a current ISNS 361 into the sense terminal SNS 318. Transistors M1 354, M2 355, and M3 356 mirror the received sense current ISNS 361. The mirrored sense current (i.e., the current flowing through transistor M2 355) is subtracted from a reference current IREF output by a current source 358. A current driver 359 buffers and / or amplifies the difference between the mirrored sense current and the reference current I REF , and outputs a clamp signal 334 based on the difference between the reference current I REF When the clamp signal 334 is less than VCE141, the clamp signal 334 is substantially zero. The drive signal generator 326 receives the clamp signal 334. Transistors 352 and 353 mirror the clamp signal 334 to control how much current the off switch 350 conducts. As shown, the off switch 350 varies the gate low current IGL 360 such that the rate of change of the switch voltage VCE141 is reduced, effectively clamping the switch voltage VCE141. The off switch 350 initially operates in a linear mode during the off-switching transition. The off switch 350 enters a saturation mode once to clamp the switch voltage VCE341.

[0050] Additionally, the values ​​of resistors RC1 337, RC2 338 are set to determine the switch voltage V that triggers the switch fault detector 325 to assert the clamp signal 334. CE 341. The larger the value of resistor RC1 337, the lower the switch voltage V that triggers the active clamp. CE In other words, the higher the value for resistor RC1 337, the higher the voltage V that triggers switch fault detector 325 to assert clamp signal 334. CE341 is higher.

[0051] Note that when the power switch 302 should be off or should be switched off and when an overvoltage condition is detected, the input impedance of the sense terminal SNS 318 is low. Transistors M1 354, M2 355, and M3 356 form a low impedance path to the return COM. The value of resistor RC2 338 may be selected such that the impedance of resistor RC2 338 is much greater than the input impedance of the sense terminal SNS 318 during overvoltage detection. For example, the input impedance of the sense terminal SNS 318 during overvoltage detection may be approximately 4-5 kOhms, and the impedance of resistor RC2 338 is approximately 22-82 kOhms. In one example, resistor RC1 337 may be approximately 1-2 megohms. Such a relationship ensures that nearly all of the current flowing through resistor RC1 337 also flows into the sense terminal SNS 318.

[0052] Note that in the example shown, resistor RC2 338 is coupled to the return terminal COM 321. Alternatively, resistor RC2 338 can be coupled to the emitter terminal, for example, as shown in FIG.

[0053] 3B shows a timing diagram 301 illustrating various waveforms that may occur when the power switch 302 is switching off and when it should be off. In particular, the drive status signal 327, the reference current signal I REF 358, detection current I SNS Waveforms are shown for the gate low current IGL 361, the clamp signal 334, and the gate low current IGL 360. The drive status signal 327 is a square pulse waveform with logic high and logic low sections of variable duration. In the example shown, a logic high indicates that the power switch should be on and a logic low indicates that the power switch should be off.

[0054] At time t0362, the drive status signal 327 transitions to a logic low value. In response, the switch fault detector 325 is coupled to detect the overvoltage condition and receives a detection current ISNS 361 representative of the switch voltage VCE 341. In response to the drive status signal 327, the current source 358 generates a reference current ISNS 361. REF to a first threshold I 365. Additionally, the drive signal generator 326 drives the off switch 350 to a conductive state such that the gate low signal UL 330 switches the power switch 302 off. As shown, the gate low current I GL 360 increases to a value that switches off the power switch 302. Between time t0 362 and time t1 363, the detected current I SNS 361- and the switch voltage it represents V CE 341-- is still relatively low, and the reference current I REF 358. Thus, the clamp signal 334 is substantially zero and the gate low current IGL 360 is a substantially constant non-zero value.

[0055] At time t1363, the detected current I SNS 361 starts to rise and the switch voltage V CE 341 further increases. However, the detection current I SNS 361 is the reference current I REF 358. Thus, the clamp signal 334 remains substantially equal to zero, and the gate low current I GL 360 is a substantially constant non-zero value.

[0056] However, at time t2 364, the sense current ISNS 361 reaches the reference current IREF 358, which indicates that the power switch 302 is in an overvoltage condition. The clamp signal 334 begins to rise, and the gate low current IGL 360 decreases. In the waveforms shown, the gate low current IGL 360 is an inverted version of the clamp signal 334. As the clamp signal 334 rises, the gate low current IGL 360 decreases. The magnitude of the decrease in the gate low current IGL 360 is proportional to (but typically not equal to) the magnitude of the rise in the clamp signal 334. At time t2 364, the rise in the clamp signal 334 triggers the current source 358 to increase the reference current IREF 358 from a first threshold I1 365 to a second threshold I2 366. REF Increase the reference current I REF 358 reaches a second threshold I2 366 within a reference period TREF 367. In one example, the first threshold I1 365 of the reference current IREF 358 can have a lower value to avoid control overshoot. In one example, the reference current IREF 358 can vary between 200 uA and 800 uA. The value for the reference current IREF 358 can be selected high enough so that the control scheme responds with sufficient speed, but low enough to avoid high power dissipation.

[0057] Between time t2 364 and time t4 387, the switch abnormality detector 325 and the drive signal generator 326 actively control the off switch 350 to increase the detection current I SNS In particular, between time t2 364 and time t3 386, the sensed current I SNS 361 is the reference current I REF 358, the clamp signal 334 is rising, and the gate low current IGL 360 is decreasing. At time t3386, the sense current ISNS 361 reaches its peak value. The clamp signal 334 also reaches its peak value, and the gate low current IGL 360 has already reached its minimum value. In the embodiment shown, the gate low current I GLThe minimum value of I 360 is shown as zero. This is coincidental and not generally the case. The switch anomaly detector 325 and drive signal generator 326 require the time between time t2 364 and time t338 to bring the switch voltage V CE 341 under control. The active clamp that occurs allows the switch controller 306 to slowly reduce the switch voltage V CE 341. Between time t3 386 and time t4 387, the detected current I SNS 361 decreases, but the reference current I REF 358. The clamp signal 334, while still non-zero, drops from its peak value. The gate low current I GL 360 increases from its trough value.

[0058] At time t4387, the detection current ISNS361 is equal to the reference current I REF 358 and remains there for the entire period that power switch 302 is off for the example shown. The clamp signal 334 drops to zero and the gate low current IGL 360 returns to a constant non-zero value. After time t4 387, the gate voltage drops to zero and the gate low current IGL 360 decreases to zero.

[0059] In Figure 3C, the switch fault detector 325 and the drive signal generator 326 are coupled as described above with reference to Figure 3A and function as described above with reference to Figure 3A. However, Figure 3C shows additional circuitry coupled to the detection terminal SNS 318. As shown, a resistor 390 and a capacitance 345 are coupled together in parallel and in series with a Zener diode 347. These components are coupled between the detection terminal SNS 318 and the return COM. As shown, the parallel coupled resistor 390 and capacitance 345 are coupled to the cathode of the Zener diode 347, while the anode of the Zener diode 347 is coupled to the return COM.

[0060] In operation, when the voltage VSNS at the SNS terminal 318 is less than the Zener voltage of the Zener diode 347, the Zener diode 347 disconnects the capacitance 345 and the resistor 390 from the SNS terminal 318. The capacitance 345 slows down the rate of rise of the voltage VSNS at the sense terminal SNS 318, while the resistor 390 discharges the capacitance 345. During the transition between turning on and turning off the power switch 302, there is some delay to the effective turning off transition due to the discharging of the sense terminal SNS 318. Furthermore, the Zener diode 347 disconnects the capacitance 345 and the resistor 390 when the drive status signal 327 indicates that the power switch 302 should be off (i.e., the drive status signal 327 is logic low), and the switch fault detector 325 will detect an overvoltage condition. As will be further described, during the on-switching transition, the switch anomaly detector 325 detects overcurrent and short circuit conditions using a detection voltage VSNS at the detection terminal SNS 318). The switch anomaly detector 325 includes a blanking circuit that prevents the switch anomaly detector 325 from responding to a false anomaly within the blanking period. The capacitance 345 slows down the rate of rise of the voltage VSNS at the SNS terminal 318, effectively acting as an externally set blanking period for the switch anomaly detector 325. It should be noted that the switch anomaly detector 325 may further include an internal blanking period. In some cases, the internal blanking period of the switch anomaly detector 325 may be set to a minimum level for operation with a fast switching power switch 302. For example, the internal blanking period of the switch anomaly detector 325 may be set to 500 ns in view of the SOA standard for the SiC power switch 302. However, such a relatively short blanking period may be too short for other power switches 302, such as IGBTs. For example, the IGBT power switch 30 may require approximately 1 to 1.5 us before the switch voltage VCE341 begins to drop. A blanking period that is too short (e.g., 500 ns) may trigger a false fault.Capacitance 345 slows the rate of rise of voltage VSNS at SNS terminal 318, extending the effective blanking period.

[0061] Fig. 4A shows an example of a circuit within the switch anomaly detector 425 for detecting an overcurrent or short circuit condition of the switch control device 402. The circuit for detecting an overcurrent or short circuit condition in Fig. 4A may be combined with the circuit for detecting overcurrent and short circuit conditions shown in Figs. 3A and 3C, for example.

[0062] The circuitry within the switch controller 406 includes a transceiver 424, a drive signal generator 426, and a switch anomaly detector 425. In the illustrated example, the transceiver 424 includes a latch 489 and an inverter 491. The latch 489 includes two reset inputs R1 and R2. The inverter 291 is coupled between the set input and the second reset input R2. The transceiver 424 is coupled to receive a command signal CMD 488 to switch the power switch 402 on or off. The command signal CMD 488 may be received from a driver interface and represents a command from the system controller. In one example, the command may be a square pulse waveform with logic high and logic low sections of variable duration. The transceiver 424 generates a drive status signal 427 based on the on command signal CMD 488. As shown, the latch 489 receives the command signal CMD488 at its set input and an inverted version of the command signal CMD488 at its second reset input R2. A leading edge in the command signal CMD488 may indicate that the power switch 402 is switched on. A trailing edge may indicate that the power switch 402 is switched off. In operation, the latch 489 outputs a logic high value at the leading edge of the command signal CMD488 (i.e., the drive status signal 427 is logic high) and outputs a logic low value at the trailing edge of the command signal CMD488 (i.e., the drive status signal 427 is logic low). Other implementations may, of course, use other forms of the command signal CMD488 and / or the drive status signal 427 may be generated using other circuitry.

[0063] The transceiver 424 is further coupled to receive a fault signal 433 from a switch fault detector 425. As shown, the fault signal 433 is received at a first reset input R1 of a latch 489. As described in more detail below, the switch fault detector 425 asserts the fault signal 433 in response to a detected overcurrent or short circuit condition. In response to the fault signal 433 being asserted, the latch 489 is reset and the drive status signal 427 transitions to a logic low.

[0064] The drive signal generator 426 includes an on switch 449 and an off switch 450. Both the on switch 449 and the off switch 450 are shown as n-type transistors. One end of the on switch 449 is coupled to the source voltage VISO, while the other end is coupled to the gate high terminal GH 419. The on switch 449 is controlled by the drive state signal 427 via a driver 451. In operation, when the drive state signal 427 indicates that the power switch 402 is switched on (i.e., the drive state signal 427 is logic high), the driver 451 controls the on switch 449 to be switched on and provides a gate high signal UH 429 to the gate high terminal GH 419 and the resistor 435. The off switch 450 is further controlled to be off. The drive signal 431 is substantially the same as the gate high signal UH 429, and the power switch 402 is switched on.

[0065] The off switch 450 is coupled between the gate low terminal GL 420 and the return COM. The off switch 450 is controlled by the drive state signal 427 via an inverter 485 and a current source 448. The inverter 485 receives the drive state signal 427 and controls the current source 448. As shown, the current source 448 is coupled to control the off switch 450. In operation, when the drive state signal 427 indicates that the power switch 402 is switched off (i.e., the drive state signal 427 is logic low), the inverter 485 controls the current source 448 to provide sufficient current to switch the off switch 450 on. The off switch 450 couples the gate low terminal 420 to the return COM. And the gate low signal UL 430 flows through the off switch 450 and the resistor 436. The on switch 449 is off and the power switch 402 is switched off. The current into the gate low terminal 420 may be referred to as the gate low current IGL 460.

[0066] The illustrated embodiment of the switch fault detector 425 includes transistors M1 454, M2 455, M3 456, and M4 457, a voltage source 469 that outputs a voltage V1, a comparator 470, and a blanking circuit 471. Transistors M1 454, M2 455, M3 456, and M4 457 are identical to transistors M1 354, M2 355, M3 356, and M4 357 (FIGS. 3A, 3C) and are coupled together to form a current mirror that can be switched on or off depending on the state of the drive status signal 427. The comparator 470 includes an inverting input and a non-inverting input. The inverting input is coupled to receive the voltage V1 output by the voltage source 469. The non-inverting input is coupled to the detection terminal SNS 418 and receives the voltage VSNS 418. The output of the comparator 470 is coupled to the blanking circuit 471. As described in detail below, the blanking circuit 471 is coupled to blank the output of the comparator 470 for an internal blanking period after the power switch 402 is switched on. The depicted switch fault detector 425 is for detecting an overcurrent and / or short circuit condition. In response to detecting an overcurrent or short circuit condition, the switch fault detector 425, the transceiver 424, and the drive signal generator 426 switch the power switch 402 off. The switch fault detector 425 receives a detection signal at the detection terminal SNS 418. Upon overcurrent and / or short circuit detection, the switch current IC 442 is read as a voltage signal, i.e., the detection voltage VSNS 418. A resistor RC1 437 is coupled between the detection terminal SNS 418 and the collector / drain of the power switch 402. A resistor RC2 438 is coupled between the detection terminal SNS 418 and the return COM or emitter / source voltage VEE. Resistors RC1 437 and RC2 438 form a voltage divider that provides the voltage at the sense terminal VSNS 418. Although only single resistors are shown for RC1 437 and RC2 438, it should be understood that multiple resistors may be used.

[0067] In operation, switch fault detector 425 receives drive status signal 427 at the gates of transistor M3 456 and transistor M4 457. In operation, the state of drive status signal 427 indicates whether switch fault detector 425 detects an over-voltage or over-current / short circuit condition.

[0068] When the drive status signal 427 indicates that the power switch 402 is to be turned on (i.e., when the drive status signal 427 is logic high), the switch fault detector 425 is coupled to detect an overcurrent and / or short circuit condition using the voltage VSNS at the detection terminal SNS 418. When the drive status signal 427 is logic high. The transistor M3 456 is off and the transistor M4 457 is on. The transistors M1 454 and M2 455 do not operate as a current mirror. Because the transistors M1 454 and M2 455 do not operate as a current mirror, the impedance observed at the detection terminal SNS 418 is the input impedance of the comparator 470, and therefore the input impedance of the detection terminal SNS 418 is high. The comparator 470 receives the voltage SNS at the detection terminal SNS 418 and compares the detection voltage VSNS to the sum of the voltages V1 and VEE. If the detected voltage VSNS exceeds the sum of the voltages V1 and VEE, the comparator 470 outputs an indication of a fault. The output of the comparator 470 is received by the blanking circuit 471. The blanking circuit 417 blanks the output of the comparator 470 for an internal blanking period after the power switch 402 is turned on. After the internal blanking period has elapsed, the output of the blanking circuit 471 includes any indication of a fault and is represented as a fault signal 433 in the embodiment shown. Thus, when the detected voltage VSNS is greater than the sum of the voltages V1 469 and VEE 468 after the internal blanking period has elapsed, the fault signal 433 is asserted. The asserted fault signal 433 resets the latch 489 and the drive status signal 427 transitions to a logic low value to switch the on switch 449 off and to switch the off switch 450 on. In response, the power switch 402 is turned off.

[0069] The values ​​of resistors RC1 437 and RC2 438 are determined in part by the internal voltage reference V1 of the voltage source 469 and the desired desaturation level of the power switch 402. Additionally, the sense terminal SNS 418 has a high input impedance in parallel with resistor RC2 438. In the illustrated example of FIG. 4A , the value of resistor RC2 438 may be selected to adjust the desaturation level relative to the internal reference V1 of the voltage source 469. The higher the value of resistor RC2 438, the lower the desaturation level and the smaller the value of switch current IC442 that triggers the switch anomaly detector 425 to detect an anomaly.

[0070] In Fig. 4B, the switch anomaly detector 425, the transceiver 424, and the drive signal generator 426 are substantially the same as those shown in Fig. 4A. However, Fig. 4B includes a power switch 402 that includes a detection terminal 483 (indicated by a dashed line). The detection terminal 483 may be, for example, a tap terminal of the IGBT power switch 402, and outputs a current that is a small percentage of the current I C flowing through the power switch 402. Furthermore, resistors RS1 439 and RS2 440 are coupled to the detection terminal 483 that provide a detection signal. In addition, resistor RC2 438 has been removed.

[0071] The sense terminal 482 of the power switch 402 outputs a current IESNsN 492. The current IESNsN 492 is a small percentage of the switch current IC 442. Resistors RS1 439 and RS2 440 are coupled together as a voltage divider to provide a sense voltage VSNS to the sense terminal SNS 418. The sense voltage VSNS represents the current IESNsN 492. As shown, resistor RS1 439 is coupled to the sense terminal 483 and the emitter / source of the power switch 402. Resistor RS2 440 is coupled to the sense terminal 483 of the power switch 402 and to the sense terminal SNS 418 of the switch controller 406. The voltage across resistor RS1 139 is proportional to the total switch current IC 142. Resistor RS2 is used to couple the voltage across RS1 to the sense terminal SNS 118.

[0072] Similar to RC1, RS1, and RS2 in FIG. 4A, resistor RS2 adjusts the desaturation level for the internal reference voltage V1. Resistor RS2 couples the low voltage across RS1 to the detection terminal SNS 418. The value of RS1 is generally less than 50 ohms, for example, typically about 10-20 ohms. Resistor RS2 is about 100 kOhms. Resistor RS2 440 adjusts the desaturation level for the power switch 402 for the current source's internal reference voltage V1. The higher the value of resistor RS2 440, the lower the desaturation level that triggers the switch anomaly detector 425 to detect an anomaly. Resistor RS1 439 converts the current I ESNS 492 to a voltage higher than the voltage range of the SOA of the power switch 402. In one example, the voltage range of the power switch 402 can be 0.2V to 0.6V for SOA compliance.

[0073] 4C is a timing diagram 401 illustrating various waveforms that may occur when the power switch 402 is switching on and should be on. In particular, the waveforms of the drive status signal 427, the sense voltage VSNS 418, and the fault signal 433 are shown. At time t0 462, the drive status signal 427 transitions from logic low (indicating the power switch 402 is turning off) to logic high (indicating the power switch 402 is turning on). The sense voltage VSNS 418 - which represents the switch current IC 442 - further rises. Between time t0 462 and time t1 463, the sense voltage VSNS 418 remains below the sum of the voltage V1 and the emitter voltage VEE. The fault signal 433 remains at logic low (not asserted).

[0074] At time t1 463, the detection voltage VSNS 418 reaches a threshold value set by the sum of the voltage V1 and the emitter voltage VEE. However, the abnormal signal 433 does not rise within the internal blanking period T set by the blanking circuit 471. B At time t2464, the sense voltage VSNS418 remains above the threshold set by the sum of the voltage V1 and the emitter voltage VEE, and the blanking period T B471 has elapsed. The fault signal 433 is asserted and transitions to a logic high value. In response, the drive status signal 427 transitions to a logic low value and the power switch 402 is turned off. The switch current IC 442 decreases and the sense voltage VSNS 418 decreases. In one example, the threshold set by the voltage V1 and the emitter voltage VEE may be between 200 mV and 500 mV. The threshold may be selected to allow both sense-IGBT and MOSFET to be monitored.

[0075] The dashed box shown in FIG. 4C indicates the sensed voltage VSNS 418 for FIGS. 4A and 4B.

[0076] In the case of FIG. 4A where resistor RC2 438 is coupled to emitter VEE 464, the sensed voltage VSNS 418 is substantially as follows:

[0077]

number

[0078] In the case of FIG. 4A where resistor RC2 438 is coupled to return COM 421, the sensed voltage VSNS 418 is substantially as follows:

[0079]

number

[0080] In the case of FIG. 4B, the sensed voltage VSNS 418 is substantially as follows:

[0081]

number

[0082] In Figure 4D, the switch fault detector 425, the transceiver 424, and the drive signal generator 426 are substantially the same as those shown in Figures 4A and 4B. However, Figure 4D includes additional circuitry coupled to the detection terminal SNS 418. As shown, a resistor 490 and a capacitance 445 are coupled together in parallel. The parallel combined resistor 490 and capacitance 445 are coupled in series to a Zener diode 447. These components are coupled between the detection terminal SNS 418 and the cathode of the Zener diode 447. The anode of the Zener diode 447 is coupled to the return COM.

[0083] In operation, the Zener diode 447 disconnects the capacitance 445 from the SNS terminal 418 in response to the voltage VSNS at the SNS terminal 418 dropping below the Zener voltage of the Zener diode 447. The capacitance 445 slows down the rise of the voltage VSNS at the sense terminal SNS 418. The resistor 490 discharges the capacitance 445. During the transition between the on and off states of the power switch 402, there is some delay due to discharging the sense terminal SNS 418. Additionally, the Zener diode 447 disconnects the capacitance 445 and the resistor 490 when the drive status signal 427 indicates that the power switch 402 is to be turned off (i.e., when the drive status signal 427 is logic low).

[0084] During turn-on, the switch fault detector 425 detects overcurrent and short circuit conditions using the detection voltage VSNS418. The blanking circuit 471 prevents the switch fault detector 425 from responding to a false fault within the internal blanking period TB. The capacitance 450 slows down the rise rate of the detection voltage VSNS418. Thus, the effective blanking period of the switch fault detector 425 can be extended using an external circuit. For example, the internal blanking period TB of the switch fault detector 425 can be set to 500ns to comply with the SOA standard for the SiC power switch 402. However, this blanking period of 500ns may be too short for the IGBT power switch 402. For example, the IGBT power switch 402 may require 1-1.5us before the switch voltage VCE441 starts to drop. The effective blanking period of 500ns may be too short to trigger a false fault. The capacitance 445 slows down the rate of rise of the voltage VSNS 418 and extends the effective blanking period of the switch fault detector 425 .

[0085] 5 illustrates an example inductive coupling between a transmitter 508 and a receiver 510 in an integrated circuit package. The driver interface may be an example of a transmitter, and the driver circuit may be an example of a receiver. The inductive coupling illustrated in FIG. 5 may be an example of the communication link 114 described above (FIG. 1).

[0086] In FIG. 5, the inductive coupling includes a transmitter loop 511 and a receiver loop 513 defined in a lead frame 500 of an integrated circuit package. The lead frame 500 is located substantially within an encapsulated portion 563 of the integrated circuit package. In the embodiment shown, the lead frame 500 includes a first conductor including the transmitter loop 511 and a second conductor including the receiver loop 513. The second conductor of the lead frame is galvanically isolated from the first conductor. The transmitter conductive loop 511 is located near the receiver conductive loop 513 to provide a magnetically coupled communication link between the transmitter conductive loop 511 and the receiver conductive loop 513. In addition, a lead 551 and a lead 552 are coupled to respective die attach pads 553 and 554. The elements within the encapsulation member 563 are located within the encapsulated portion of the integrated circuit package. Further shown in FIG. 5 are transmitter 508, receiver 510, pads 555, 556, 558, and 557, and bond wires 559, 560, 561, and 562.

[0087] In one example, the transmitter 508 and the receiver 510 are implemented as circuits in an integrated circuit die contained within an encapsulated portion of an integrated circuit package. A die attach pad 553 that is part of a first conductor of the lead frame 560 is shown in FIG. 5 with diagonal hatching and represents the portion of the lead frame 500 on which the transmitter 508 is mounted. Similarly, a die attach pad 554 that is part of a second conductor of the lead frame 500 is shaded in FIG. 5 with diagonal hatching and represents the portion of the lead frame 500 on which the receiver 510 is mounted. In one example, the transmitter 508 and the receiver 510 are attached to the respective spaced first and second conductors of the lead frame 500 using an adhesive. The adhesive may be non-conductive. In another example, the adhesive may be conductive.

[0088] Leads 551 and 552 represent portions of leadframe 500 that may be coupled to circuitry outside the integrated circuit package (in other words, outside outline 563). Although not shown, various bond wires may couple transmitter 508 or receiver 510 to any of leads 551 or 552.

[0089] 5 corresponds to the transmitter conductive loop 511. A portion of the lead frame 500 and bond wire 559 and bond wire 560 complete the transmitter conductive loop 511. Bond wire 559 and bond wire 560 are attached to the portion of the lead frame 500 corresponding to the transmitter conductive loop 511 using wire bonding techniques. Additionally, bond wire 559 is coupled to the transmitter 508 through pad 555, while bond wire 560 is coupled to the transmitter 508 through pad 556.

[0090] The portion of lead frame 500 shaded with densely packed dots in FIG. 5 corresponds to receiver conductive loop 513. Bond wire 561 and bond wire 562 are attached to the portion of lead frame 500 corresponding to receiver conductive loop 513 using wire bonding techniques. Bond wire 561 and bond wire 562 couple the portion of lead frame 500 corresponding to receiver conductive loop 513 to receiver 510 via pads 558 and 557, respectively. The use of galvanically isolated magnetically coupled conductive loops of a lead frame to provide a communication link between the transmitter results in very little additional cost. Additionally, using a lead frame may further reduce the overall size of the switch control device and lower packaging costs.

[0091] As mentioned above, the driver interface may be an example of a transmitter 508, and the drive circuit may be an example of a receiver 510. The driver interface may send communications to the drive circuit, such as a command signal to turn a power switch on or off, which is sent by an inner loop 511 (transmit loop 511) and received by an outer loop 513 (receiver loop 513). The drive circuit may send communications to the driver interface, such as an abnormal signal, which is sent by an outer loop 513 (receiver loop 513) and received by the inner loop 511 (transmit loop 511). Thus, the inductive coupling shown in FIG. 5 may also be an example of a two-way communicator.

[0092] FIG. 6 illustrates an exemplary power converter 600 including a switch control device in accordance with an example of the present invention. The power converter 600 provides electrical energy to a load 610. The power converter 600 includes two power switches 606 and 606 coupled in series. In addition, the power converter 600 receives an input voltage 602 (U IN ) Power converter 600 is designed to transfer electrical energy from an input to a load 610 by controlling the switching of power switches 604 and 606. In different embodiments, power converter 600 may control the voltage, current, or power level of the energy output to the load.

[0093] 6, power switch 604 and power switch 606 are n-channel IGBTs. However, examples of the invention may be used in combination with other power switches. For example, metal-oxide-semiconductor field effect transistors (MOSFETs), bipolar transistors, injection-enhanced gate transistors (IEGTs), and gate turn-off thyristors (GTOs) may be used. In addition, power converter 600 may be used with power switches based on gallium nitride (GaN) semiconductors or silicon carbide (SiC) semiconductors.

[0094] The power switch 604 and the power switch 606 are respectively controlled by a first switch controller 618 and a second switch controller 620. The first switch controller 618 and the second switch controller 620 may include the switch controllers described hereinabove. The first switch controller 618 and the second switch controller 620 provide a first gate driver signal 630 and a second gate driver signal 632 (U DR1 , U DR2 6 provides a power supply for a power supply 616. The two control circuits 618 and 620 may optionally be controlled by a system controller 614. Such a system controller may include an input for receiving a system input signal 616. In the example shown in Figure 6, two power semiconductor switches are shown in a half-bridge configuration; however, other topologies may be used.

[0095] The above description of examples shown for the present invention, including those matters described in the Abstract, is not intended to be exhaustive or to be limited to the precise forms disclosed. Specific embodiments and examples of the present invention are described herein for illustrative purposes, but various equivalent modifications are possible without departing from the broader spirit and scope of the present invention. Indeed, it will be understood that specific and exemplary voltages, currents, frequencies, power range values, times, and the like are presented for purposes of illustration, and that other values ​​may be used in other embodiments and examples in accordance with the teachings of the present invention.

[0096] These modifications may be applied to examples of the invention in light of the above detailed description. The terms used in the following claims should not be construed to limit the invention to the specific embodiments disclosed in the specification and claims. Rather, the scope is to be defined entirely by the following claims, which are to be construed in accordance with established principles of claim interpretation. The specification and figures are therefore to be regarded as illustrative rather than limiting.

[0097] While the present invention is defined in the claims, it should be understood that the invention can be alternatively defined in accordance with the following embodiments.

[0098] Embodiment 1. A driver circuit for driving a power semiconductor switch, the power semiconductor switch including a control input and a main terminal, the driver circuit comprising: a control terminal driver circuit configured to be coupled to the control input of the power semiconductor switch and to provide a drive signal to the control input; a detection terminal configured to be coupled to the main terminal of the power semiconductor switch; a first current comparator coupled to compare a signal received from the detection terminal with an off-switching threshold during off-switching and to output a first signal representative of the comparison, the off-switching threshold representing a highest voltage of the main terminal during off-switching; and a second comparator coupled to compare a signal received from the detection terminal with an on-switching threshold during on-switching and to output a second signal representative of the comparison, the on-switching threshold representing a highest voltage of the main terminal during on-switching.

[0099] Embodiment 2. The driver circuit of embodiment 1, further comprising a switching circuit switchable to couple the first current comparator to the detection terminal during off switching and in an off state, and to decouple the first current comparator from the detection terminal during on switching and in an on state.

[0100] Embodiment 3. The driver circuit of embodiment 2, wherein the switching circuit is coupled to receive a drive state signal indicative of whether the power semiconductor switch is to be in an off state or an on state.

[0101] Embodiment 4. The driver circuit of any one of the preceding embodiments, wherein the OFF-switching threshold further represents a maximum voltage at the main terminals in an OFF state; and the ON-switching threshold further represents a maximum voltage at the main terminals in an ON state.

[0102] Embodiment 5. The driver circuit of any one of the preceding embodiments, wherein the control terminal driver circuit responds to reduce the switching-off rate in response to a first signal indicating that the voltage at the main terminal during switching-off has exceeded a switching-off threshold.

[0103] Embodiment 6. The driver circuit of any one of the preceding embodiments, wherein the driver circuit further comprises a current mirror coupled between the sense terminal and the first comparator.

[0104] Embodiment 7. The driver circuit of any one of the preceding embodiments, further comprising a timer circuit for timing a duration during which the second signal indicates that the signal received from the detection terminal exceeded a switch-on threshold during switch-on.

[0105] Embodiment 8. The driver circuit of any one of the preceding embodiments, wherein the first comparator, the second comparator and the switching circuit are in a single semiconductor package, and the detection terminal is a terminal of the package.

[0106] Embodiment 9. The driver circuit of any one of the preceding embodiments, wherein the switch-off threshold is a variable threshold.

[0107] Embodiment 10. The driver circuit of any one of the preceding embodiments, wherein the input impedance of the detection terminal is relatively smaller during off-switching than during on-switching, e.g., in which the input impedance of the detection terminal is less than 200 kilohms during off-switching and greater than 10 megahms during on-switching, e.g., in which the input impedance of the detection terminal is less than 10 kilohms during off-switching and greater than 100 megahms during on-switching.

[0108] Embodiment 11. A driver circuit for driving a power semiconductor switch, the power semiconductor switch including a control input and a main terminal, the driver circuit comprising: a control terminal driver circuit configured to be coupled to the control input of the power semiconductor switch and to provide a drive signal to the control input; a detection terminal configured to be coupled to the main terminal of the power semiconductor switch; a current mirror coupled to the detection terminal to mirror a current input to the detection terminal during an OFF switch; a first current comparator coupled to compare a current signal received from the current mirror with a first current threshold and to output a first signal representative of a result of the comparison, the first current threshold representing a maximum voltage of the main terminal during an OFF switch; and a second comparator coupled to compare a signal received from the detection terminal with an ON switch threshold and to output a second signal representative of a result of the comparison, the ON switch threshold representing a maximum voltage of the main terminal during an ON switch.

[0109] Embodiment 12. The driver circuit of embodiment 11, further comprising a switching circuit switchable to couple the current mirror to the detection terminal during off switching and in an off state, and to decouple the current mirror from the detection terminal during on switching and in an on state.

[0110] Embodiment 13. The driver circuit of embodiment 12, wherein the switching circuit is coupled to receive a drive state signal indicative of whether the power semiconductor switch is to be in an off state or an on state.

[0111] Embodiment 14. The driver circuit of any one of embodiments 11 to 13, wherein the first current threshold further represents a maximum voltage at the main terminals in an off state, and the on-switching threshold further represents a maximum voltage at the main terminals in an on state.

[0112] Embodiment 15. The driver circuit of any one of embodiments 11 to 14, wherein the control terminal driver circuit responds to reduce the turn-off rate in response to a first signal indicating that the voltage at the main terminal during turn-off has exceeded a first current threshold.

[0113] Embodiment 16. The driver circuit of any one of embodiments 11 to 15, further comprising a timer circuit for timing the duration during which the second signal indicates that the signal received from the detection terminal exceeds the on-switching threshold during on-switching.

[0114] Embodiment 17. The driver circuit of any one of embodiments 11 to 16, wherein the first comparator, the second comparator and the switching circuit are in a single semiconductor package, and the detection terminal is a terminal of the package.

[0115] Embodiment 18. The driver circuit of any one of embodiments 11 to 17, wherein the first current threshold is a variable threshold.

[0116] Embodiment 19. A driver circuit of any one of embodiments 11 to 18, wherein the input impedance of the detection terminal is relatively smaller during off switching than during on switching, for example, in this case, the input impedance of the detection terminal is less than 200 kilohms during off switching and greater than 10 megahms during on switching, for example, in this case, the input impedance of the detection terminal is less than 10 kilohms during off switching and greater than 100 megahms during on switching.

Claims

1. 1. A driver circuit for driving a power semiconductor switch, the power semiconductor switch including a control input and a main terminal; The driver circuit includes: a control terminal driver circuit coupled to the control input of the power semiconductor switch and configured to provide a drive signal to the control input; a detection terminal configured to be coupled to the main terminal of the power semiconductor switch; a switch fault detector circuit for detecting an overvoltage condition, an overcurrent condition, and a short circuit condition; Equipped with The switch abnormality detector circuit includes: a first current comparator coupled to compare a signal received from the detection terminal with a switch-off threshold during switch-off and to output a first signal representative of a result of the comparison, the switch-off threshold representing a maximum voltage at the main terminal during switch-off and the first signal indicating an overvoltage fault; a second comparator coupled to compare the signal received from the detection terminal with a switch-on threshold during switch-on and to output a second signal representative of a result of the comparison, the switch-on threshold representing a maximum voltage of the main terminal during switch-on and the second signal indicating an overcurrent fault and / or a short circuit condition fault; Equipped with the driver circuit further comprises a switching circuit switchable to couple the first current comparator to the sense terminal during switching off and in an off state, and to decouple the first current comparator from the sense terminal during switching on and in an on state. Driver circuit.

2. the switching circuit is coupled to receive a drive status signal indicative of whether the power semiconductor switch is to be in an off state or an on state; 2. The driver circuit of claim 1.

3. the off-switching threshold further represents the maximum voltage at the main terminals in an off-state; the on-switching threshold further represents the maximum voltage at the main terminals in an on-state; 3. A driver circuit according to claim 1 or 2.

4. the control terminal driver circuit responds to the first signal indicating that a voltage at the main terminal during turn-off has exceeded the turn-off threshold by decreasing a turn-off rate. A driver circuit according to any one of claims 1 to 3.

5. the driver circuit further comprising a current mirror coupled between the sense terminal and the first current comparator; A driver circuit according to any one of claims 1 to 4.

6. a timer circuit configured to time a duration during which the second signal indicates that the signal received from the detection terminal exceeds the turn-on threshold during a turn-on period. A driver circuit as claimed in any one of claims 1 to 5.

7. the first current comparator, the second comparator and the switching circuit are in a single semiconductor package, and the detection terminal is a terminal of the semiconductor package. A driver circuit according to any one of claims 1 to 6.

8. the switch-off threshold is a variable threshold; A driver circuit as claimed in any preceding claim.

9. an input impedance of the sense terminal is relatively smaller during an OFF switch than during an ON switch, and the first signal is a clamp signal coupled to slow down the OFF switch speed of the power semiconductor switch. A driver circuit as claimed in any preceding claim.

10. The input impedance of the detection terminal is less than 200 kilohms during an OFF switch and greater than 10 megahms during an ON switch.

10. A driver circuit as claimed in claim 9.

11. The input impedance of the detection terminal is less than 10 kilohms during an OFF switch and greater than 100 megahms during an ON switch.

11. A driver circuit as claimed in claim 10.

12. the second comparator is a voltage comparator; A driver circuit according to any one of claims 1 to 11.

13. the first current comparator and the second comparator are part of the switch abnormality detector circuit; the first signal indicates an overvoltage fault; the second signal being indicative of an overcurrent fault and / or a short circuit condition fault; A driver circuit according to any one of claims 1 to 12.

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