Solid-state imaging device

Abstract

To provide a solid-state imaging element in which the potential of a multilayer substrate can be fixed while the space for arranging transistors is secured.SOLUTION: A solid-state imaging element includes a first semiconductor substrate including a photoelectric conversion element, and a second semiconductor substrate facing the first semiconductor substrate through an insulating film. The second semiconductor substrate includes, on a first main surface, an amplifier transistor that amplifies an electric signal output from the photoelectric conversion element, and on a second main surface on the side opposite to the first main surface, includes a region with lower resistance than the second semiconductor substrate and is grounded through the region.SELECTED DRAWING: Figure 25

Description

[Technical field]

[0001] The present disclosure relates to a solid-state imaging device. [Background technology]

[0002] There is a three-dimensional packaging technology for stacking multiple semiconductor substrates. For example, in a solid-state imaging device, a configuration is known in which a first semiconductor substrate on which a pixel region is formed and a second semiconductor substrate on which a logic circuit is formed are stacked (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2010-245506 A Summary of the Invention [Problem to be solved by the invention]

[0004] In the solid-state imaging device disclosed in Patent Document 1, it is not possible to secure a sufficient space for arranging pixel transistors. Therefore, for example, it is conceivable to stack a substrate on which a photoelectric conversion element is formed and a substrate on which a pixel transistor is formed separately.

[0005] However, in such a configuration, the potential of the substrate on which the pixel transistors are formed is not fixed, making the operation of the pixel transistors unstable.

[0006] In view of this, the present disclosure proposes a solid-state imaging element capable of fixing the potential of the laminated substrate while ensuring a space for arranging transistors. [Means for solving the problem]

[0007] A solid-state imaging element according to the present disclosure comprises a first semiconductor substrate having a photoelectric conversion element, and a second semiconductor substrate facing the first semiconductor substrate via an insulating film, the second semiconductor substrate having an amplifying transistor on a first main surface for amplifying an electrical signal output from the photoelectric conversion element, a region having a lower resistance than the second semiconductor substrate on a second main surface opposite the first main surface, and being grounded via the region. [Brief description of the drawings]

[0008] [Figure 1] FIG. 1 is a diagram illustrating an example of a schematic configuration of a solid-state imaging element applied to each embodiment of the present disclosure. [Diagram 2] 2 is a diagram illustrating an example of a sensor pixel and a readout circuit of FIG. [Diagram 3] 2 is a diagram illustrating an example of a sensor pixel and a readout circuit of FIG. [Figure 4] 2 is a diagram illustrating an example of a sensor pixel and a readout circuit of FIG. [Diagram 5] 2 is a diagram illustrating an example of a sensor pixel and a readout circuit of FIG. [Figure 6] 1 is a diagram illustrating an example of a connection mode between a plurality of readout circuits and a plurality of vertical signal lines. [Figure 7] 2 is a diagram illustrating an example of a horizontal cross-sectional configuration of the solid-state imaging element of FIG. 1. [Figure 8] 2 is a diagram illustrating an example of a horizontal cross-sectional configuration of the solid-state imaging element of FIG. 1. [Figure 9] 2 is a diagram illustrating an example of a wiring layout in a horizontal plane of the solid-state imaging element of FIG. 1. [Figure 10] 2 is a diagram illustrating an example of a wiring layout in a horizontal plane of the solid-state imaging element of FIG. 1. [Figure 11] 2 is a diagram illustrating an example of a wiring layout in a horizontal plane of the solid-state imaging element of FIG. 1. [Figure 12] 2 is a diagram illustrating an example of a wiring layout in a horizontal plane of the solid-state imaging element of FIG. 1. [Figure 13] 2 is a diagram illustrating a modification of the horizontal cross-sectional configuration of the solid-state imaging element of FIG. 1. [Figure 14] 2 is a diagram illustrating a modification of the horizontal cross-sectional configuration of the solid-state imaging element of FIG. 1. [Figure 15] 2 is a diagram illustrating a modification of the horizontal cross-sectional configuration of the solid-state imaging element of FIG. 1. [Figure 16] 2 is a diagram illustrating a modification of the horizontal cross-sectional configuration of the solid-state imaging element of FIG. 1. [Figure 17] 2 is a diagram illustrating a modification of the horizontal cross-sectional configuration of the solid-state imaging element of FIG. 1. [Figure 18] 2 is a diagram illustrating a modification of the horizontal cross-sectional configuration of the solid-state imaging element of FIG. 1. [Figure 19] 2 is a diagram illustrating a modification of the horizontal cross-sectional configuration of the solid-state imaging element of FIG. 1. [Figure 20] 2 is a diagram illustrating a modification of the circuit configuration of a solid-state imaging device according to the configuration in FIG. 1 and a modification of the configuration. [Figure 21] 21 is a diagram illustrating an example in which the solid-state imaging element of FIG. 20 is configured by stacking three substrates. [Figure 22] 13 is a diagram illustrating an example in which a logic circuit is formed separately on a substrate on which sensor pixels are provided and on a substrate on which a readout circuit is provided. FIG. [Diagram 23] FIG. 13 is a diagram illustrating an example in which a logic circuit is formed on a third substrate. [Figure 24] 1 is a diagram showing a part of a cross section of a solid-state imaging element according to a first embodiment of the present disclosure. [Diagram 25] 1 is a schematic diagram showing the vicinity of a bonding position of a substrate of a solid-state imaging element according to a first embodiment of the present disclosure. [Figure 26] FIG. 2 is a flow chart showing an example of a manufacturing process procedure of the solid-state imaging device according to the first embodiment of the present disclosure. [Figure 27] FIG. 2 is a flow chart showing an example of a manufacturing process procedure of the solid-state imaging device according to the first embodiment of the present disclosure. [Figure 28] FIG. 2 is a flow chart showing an example of a manufacturing process procedure of the solid-state imaging device according to the first embodiment of the present disclosure. [Figure 29] 1 is a diagram comparing solid-state imaging devices according to the first embodiment of the present disclosure and comparative examples 1 and 2. FIG. [Diagram 30] 1 is a diagram showing the arrangement of pixel transistors of solid-state imaging devices according to a first embodiment and a second comparative example of the present disclosure. [Diagram 31] 1 is a schematic diagram showing the vicinity of a bonding position of a solid-state imaging element according to Modification 1 of Embodiment 1 of the present disclosure. FIG. [Diagram 32] 11 is a schematic diagram showing the vicinity of a bonding position of a solid-state imaging element according to Modification 2 of Embodiment 1 of the present disclosure. FIG. [Diagram 33] 11 is a diagram showing a part of a cross section of a solid-state imaging element according to a third modification of the first embodiment of the present disclosure. FIG. [Diagram 34] 13 is a diagram showing a part of a cross section of a solid-state imaging element according to a fourth modified example of the first embodiment of the present disclosure. FIG. [Diagram 35] 11 is a schematic diagram showing the vicinity of a bonding position of a solid-state imaging element according to a second embodiment of the present disclosure. FIG. [Diagram 36] FIG. 11 is a flow chart showing an example of a manufacturing process procedure of a solid-state imaging device according to a second embodiment of the present disclosure. [Figure 37] FIG. 11 is a flow chart showing an example of a manufacturing process procedure of a solid-state imaging device according to a second embodiment of the present disclosure. [Figure 38] 11 is a diagram comparing solid-state imaging devices according to the second embodiment of the present disclosure and comparative examples 1 and 2. FIG. [Figure 39] 13 is a diagram showing the arrangement of pixel transistors of solid-state imaging devices according to a second embodiment of the present disclosure and a second comparative example. FIG. [Diagram 40] FIG. 11 is a diagram showing connections between elements of a solid-state imaging device according to a second embodiment of the present disclosure. [Diagram 41] 11 is a schematic diagram showing the vicinity of a bonding position of a solid-state imaging element according to Modification 1 of Embodiment 2 of the present disclosure. FIG. [Diagram 42] 11 is a schematic diagram showing the vicinity of a bonding position of a solid-state imaging element according to Modification 2 of Embodiment 2 of the present disclosure. FIG. [Diagram 43] 11 is a diagram comparing solid-state imaging devices according to the second embodiment of the present disclosure, its modified example 2, and comparative examples 1 and 2. FIG. [Diagram 44]13 is a schematic diagram showing the vicinity of a bonding position of a solid-state imaging element according to Modification 3 of Embodiment 2 of the present disclosure. FIG. [Diagram 45] FIG. 11 is a diagram showing a portion of a solid-state imaging element according to a third embodiment of the present disclosure. [Figure 46] 11 is a comparison diagram in which the configurations of the first and second embodiments of the present disclosure and the configuration of the second comparative example are applied to the solid-state imaging device according to the third embodiment. FIG. [Figure 47] 11 is a schematic diagram showing the vicinity of a bonding position of substrates when the configuration of the first embodiment of the present disclosure is applied to a semiconductor device according to a fourth embodiment. FIG. [Figure 48] 13 is a schematic diagram showing the vicinity of a bonding position of substrates when the configuration of the second embodiment of the present disclosure is applied to a semiconductor device according to a fourth embodiment. FIG. [Figure 49] 13 is a schematic diagram showing the vicinity of a bonding position of a substrate in a semiconductor device according to Modification 1 of Embodiment 4 of the present disclosure. FIG. [Figure 50] 13 is a schematic diagram showing the vicinity of a bonding position of a substrate in a semiconductor device according to Modification 2 of Embodiment 4 of the present disclosure. FIG. [Figure 51] 13 is a longitudinal sectional view showing the vicinity of a bonding position of a substrate of a solid-state imaging element according to a fifth embodiment of the present disclosure. FIG. [Figure 52] 13 is a cross-sectional view including the vicinity of the bonding position of the substrates of the solid-state imaging element according to the fifth embodiment of the present disclosure. FIG. [Figure 53] FIG. 11 is a perspective view showing a portion of a solid-state imaging element according to a fifth embodiment of the present disclosure. [Figure 54] FIG. 11 is a flow chart showing an example of a manufacturing process procedure of a solid-state imaging device according to a fifth embodiment of the present disclosure. [Figure 55] FIG. 11 is a flow chart showing an example of a manufacturing process procedure of a solid-state imaging device according to a fifth embodiment of the present disclosure. [Figure 56] FIG. 11 is a flow chart showing an example of a manufacturing process procedure of a solid-state imaging device according to a fifth embodiment of the present disclosure. [Figure 57] FIG. 11 is a flow chart showing an example of a manufacturing process procedure of a solid-state imaging device according to a fifth embodiment of the present disclosure. [Figure 58]FIG. 13 is a flowchart showing an example of a manufacturing process procedure for a solid-state imaging device according to a first modified example of the fifth embodiment of the present disclosure. [Figure 59] FIG. 13 is a flowchart showing an example of a manufacturing process procedure for a solid-state imaging device according to a first modified example of the fifth embodiment of the present disclosure. [Figure 60] FIG. 13 is a flowchart showing an example of a manufacturing process procedure for a solid-state imaging device according to Modification 2 of Embodiment 5 of the present disclosure. [Figure 61] FIG. 1 is a diagram illustrating an example of a schematic configuration of an imaging system including the above solid-state imaging device. [Figure 62] 62 is a diagram showing an example of an imaging procedure in the imaging system of FIG. 61. [Figure 63] 1 is a block diagram showing an example of a schematic configuration of a vehicle control system; [Figure 64] 4 is an explanatory diagram showing an example of the installation positions of an outside-vehicle information detection unit and an imaging unit; FIG. [Figure 65] 1 is a diagram illustrating an example of a schematic configuration of an endoscopic surgery system. [Figure 66] 2 is a block diagram showing an example of a functional configuration of a camera head and a CCU. FIG. [Figure 67] FIG. 13 is a block diagram illustrating an example of a functional configuration of an imaging device according to a seventh embodiment of the present disclosure. [Figure 68] 68 is a plan view showing a schematic configuration of the imaging device shown in FIG. 67. [Figure 69] 69 is a schematic diagram showing a cross-sectional configuration along line III-III' shown in FIG. 68. [Figure 70] FIG. 68 is an equivalent circuit diagram of the pixel sharing unit shown in FIG. 67. [Figure 71] 10 is a diagram illustrating an example of a connection mode between a plurality of pixel sharing units and a plurality of vertical signal lines. [Figure 72] 70 is a schematic cross-sectional view showing an example of a specific configuration of the imaging device shown in FIG. 69. [Figure 73A] 73 is a schematic diagram illustrating an example of a planar configuration of a main part of the first substrate shown in FIG. 72. [Figure 73B] 73B is a schematic diagram showing a planar configuration of a pad portion together with a main portion of the first substrate shown in FIG. 73A. [Figure 74] 73 is a schematic diagram illustrating an example of a planar configuration of the second substrate (semiconductor layer) illustrated in FIG. 72. FIG. [Figure 75] 73 is a schematic diagram showing an example of a planar configuration of a pixel circuit and a main part of a first substrate together with the first wiring layer shown in FIG. 72. [Figure 76] 73 is a schematic diagram illustrating an example of a planar configuration of the first wiring layer and the second wiring layer illustrated in FIG. 72. [Figure 77] 73 is a schematic diagram illustrating an example of a planar configuration of the second wiring layer and the third wiring layer illustrated in FIG. 72. [Figure 78] 73 is a schematic diagram illustrating an example of a planar configuration of the third wiring layer and the fourth wiring layer illustrated in FIG. 72. [Figure 79] 70 is a schematic diagram for explaining the path of an input signal to the imaging device shown in FIG. 69. FIG. [Figure 80] FIG. 70 is a schematic diagram for explaining a signal path of a pixel signal in the imaging device shown in FIG. 69. [Figure 81] 75 is a schematic diagram illustrating a modified example of the planar configuration of the second substrate (semiconductor layer) shown in FIG. 74. FIG. [Figure 82] 82 is a schematic diagram showing the planar configuration of the pixel circuit shown in FIG. 81 as well as the first wiring layer and the main part of the first substrate. [Figure 83] 83 is a schematic diagram showing an example of a planar configuration of a second wiring layer together with the first wiring layer shown in FIG. 82. [Figure 84] FIG. 84 is a schematic diagram showing an example of a planar configuration of a third wiring layer together with the second wiring layer shown in FIG. 83. [Figure 85] 85 is a schematic diagram showing an example of a planar configuration of a fourth wiring layer together with the third wiring layer shown in FIG. 84. [Figure 86] FIG. 73B is a schematic diagram illustrating a modified example of the planar configuration of the first substrate shown in FIG. 73A. [Figure 87] 87 is a schematic diagram showing an example of a planar configuration of a second substrate (semiconductor layer) laminated on the first substrate shown in FIG. 86. FIG. [Figure 88] FIG. 88 is a schematic diagram showing an example of a planar configuration of a first wiring layer together with the pixel circuit shown in FIG. 87. [Figure 89] 89 is a schematic diagram showing an example of a planar configuration of the second wiring layer together with the first wiring layer shown in FIG. 88. [Figure 90] 89. FIG. 90 is a schematic diagram showing an example of a planar configuration of a third wiring layer together with the second wiring layer shown in FIG. [Figure 91] 91 is a schematic diagram showing an example of a planar configuration of a fourth wiring layer together with the third wiring layer shown in FIG. 90. [Figure 92] 87 is a schematic diagram illustrating another example of the planar configuration of the first substrate shown in FIG. 86. [Figure 93] 93 is a schematic diagram showing an example of a planar configuration of a second substrate (semiconductor layer) laminated on the first substrate shown in FIG. 92. FIG. [Figure 94] FIG. 94 is a schematic diagram showing an example of the planar configuration of a first wiring layer together with the pixel circuit shown in FIG. 93. [Figure 95] 95 is a schematic diagram showing an example of a planar configuration of the second wiring layer together with the first wiring layer shown in FIG. 94. [Figure 96] 96 is a schematic diagram showing an example of a planar configuration of a third wiring layer together with the second wiring layer shown in FIG. 95. [Figure 97] 97 is a schematic diagram showing an example of a planar configuration of a fourth wiring layer together with the third wiring layer shown in FIG. 96. [Figure 98] 70 is a schematic cross-sectional view illustrating another example of the imaging device shown in FIG. 69. [Figure 99] FIG. 99 is a schematic diagram for explaining the path of an input signal to the imaging device shown in FIG. 98. [Figure 100] FIG. 99 is a schematic diagram for explaining the signal path of pixel signals in the imaging device shown in FIG. 98. [Figure 101] 73 is a schematic cross-sectional view illustrating another example of the imaging device shown in FIG. 72. [Figure 102] FIG. 71 is a diagram illustrating another example of the equivalent circuit shown in FIG. 70. [Figure 103] FIG. 73B is a schematic plan view illustrating another example of the pixel separating portion shown in FIG. 73A etc. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. In the following embodiments, the same components are designated by the same reference numerals, and duplicated descriptions will be omitted.

[0010] [Example of schematic configuration of solid-state imaging element] An example of a schematic configuration of a solid-state imaging device will be described with reference to FIGS.

[0011] (Example of circuit configuration of solid-state imaging element) 1 is a diagram showing an example of a schematic configuration of a solid-state imaging device 1 applied to each embodiment of the present disclosure. The solid-state imaging device 1 converts received light into an electrical signal and outputs it as a pixel signal. In this example, the solid-state imaging device 1 is configured as a CMOS (Complementary Metal Oxide Semiconductor) image sensor.

[0012] 1, the solid-state imaging element 1 includes three substrates: a first substrate 10, a second substrate 20, and a third substrate 30. The solid-state imaging element 1 is an imaging device having a three-dimensional structure formed by bonding these three substrates together. The first substrate 10, the second substrate 20, and the third substrate 30 are stacked in this order.

[0013] The first substrate 10 has a plurality of sensor pixels 12 that perform photoelectric conversion on a semiconductor substrate 11. The plurality of sensor pixels 12 are arranged in a matrix in a pixel region 13 on the first substrate 10. The second substrate 20 has a readout circuit 22 that outputs a pixel signal based on the charge output from the sensor pixel 12, one for every four sensor pixels 12, on a semiconductor substrate 21. The second substrate 20 has a plurality of pixel driving lines 23 extending in the row direction and a plurality of vertical signal lines 24 extending in the column direction. The third substrate 30 has a logic circuit 32 that processes pixel signals on a semiconductor substrate 31. The logic circuit 32 has, for example, a vertical driving circuit 33, a column signal processing circuit 34, a horizontal driving circuit 35, and a system control circuit 36. The logic circuit 32, more specifically, the horizontal driving circuit 35 outputs an output voltage Vout for each sensor pixel 12 to the outside. In the logic circuit 32, for example, a CoSi layer is formed on the surface of the impurity diffusion region in contact with the source electrode and the drain electrode by using a self-aligned silicide (SALICIDE) process. 2 Alternatively, a low resistance region made of silicide such as NiSi may be formed.

[0014] The vertical drive circuit 33, for example, sequentially selects the plurality of sensor pixels 12 on a row-by-row basis. The column signal processing circuit 34, for example, performs correlated double sampling (CDS) processing on pixel signals output from each sensor pixel 12 in the row selected by the vertical drive circuit 33. The column signal processing circuit 34, for example, performs CDS processing to extract a signal level of the pixel signal and holds pixel data according to the amount of light received by each sensor pixel 12. The horizontal drive circuit 35, for example, sequentially outputs the pixel data held in the column signal processing circuit 34 to the outside. The system control circuit 36, for example, controls driving of each block of the vertical drive circuit 33, the column signal processing circuit 34, and the horizontal drive circuit 35 in the logic circuit 32.

[0015] 2 to 5 are diagrams showing an example of a sensor pixel 12 and a readout circuit 22. In the following, a case where four sensor pixels 12 share one readout circuit 22 will be described. Here, "sharing" refers to the outputs of the four sensor pixels 12 being input to a common readout circuit 22. However, the sharing unit does not matter in terms of the number of pixels. For example, as in the first and second embodiments described below, the output of one sensor pixel 12 may be input to one readout circuit 22. Also, similar to this example, as in the third embodiment, the output of four sensor pixels 12 may be input to one readout circuit 22.

[0016] As shown in Fig. 2, the sensor pixels 12 have components in common with each other. In Fig. 2, in order to distinguish the components of each sensor pixel 12 from each other, identification numbers 1, 2, 3, and 4 are added to the end of the reference numerals of the components of each sensor pixel 12. In the following, when it is necessary to distinguish the components of each sensor pixel 12 from each other, an identification number is added to the end of the reference numerals of the components of each sensor pixel 12. When it is not necessary to distinguish the components of each sensor pixel 12 from each other, the identification number at the end of the reference numerals of the components of each sensor pixel 12 is omitted.

[0017] Each sensor pixel 12 has, for example, a photodiode PD, a transfer transistor TR electrically connected to the photodiode PD, and a floating diffusion FD that temporarily holds the charge output from the photodiode PD via the transfer transistor TR. The photodiode PD corresponds to a specific example of a "photoelectric conversion element" in the present disclosure. The photodiode PD performs photoelectric conversion to generate a charge according to the amount of received light. The cathode of the photodiode PD is electrically connected to the source of the transfer transistor TR, and the anode of the photodiode PD is electrically connected to a reference potential line such as a ground line (GND). The drain of the transfer transistor TR is electrically connected to the floating diffusion FD, and the gate of the transfer transistor TR is electrically connected to a pixel drive line 23 (see FIG. 1). The transfer transistor TR is, for example, a CMOS transistor.

[0018] The floating diffusions FD of the sensor pixels 12 sharing one readout circuit 22 are electrically connected to each other and to an input terminal of the common readout circuit 22. The readout circuit 22 has, for example, a reset transistor RST, a selection transistor SEL, and an amplification transistor AMP. The selection transistor SEL may be omitted as necessary. The source of the reset transistor RST, which is the input terminal of the readout circuit 22, is electrically connected to the floating diffusion FD, and the drain of the reset transistor RST is electrically connected to a power supply line VDD and the drain of the amplification transistor AMP. The gate of the reset transistor RST is electrically connected to a pixel drive line 23 (see FIG. 1). The source of the amplification transistor AMP is electrically connected to the drain of the selection transistor SEL, and the gate of the amplification transistor AMP is electrically connected to the source of the reset transistor RST. The source of the selection transistor SEL, which is the output terminal of the readout circuit 22, is electrically connected to a vertical signal line 24, and the gate of the selection transistor SEL is electrically connected to the pixel drive line 23 (see FIG. 1).

[0019] When the transfer transistor TR is turned on, the charge of the photodiode PD is transferred to the floating diffusion FD. The reset transistor RST resets the potential of the floating diffusion FD to a predetermined potential. When the reset transistor RST is turned on, the potential of the floating diffusion FD is reset to the potential of the power supply line VDD. The selection transistor SEL controls the output timing of the pixel signal from the readout circuit 22. The amplification transistor AMP generates a signal having a voltage corresponding to the level of the charge held in the floating diffusion FD as the pixel signal. The amplification transistor AMP constitutes a source follower type amplifier and outputs a pixel signal having a voltage corresponding to the level of the charge generated in the photodiode PD. When the selection transistor SEL is turned on, the amplification transistor AMP amplifies the potential of the floating diffusion FD and outputs a voltage corresponding to the potential to the column signal processing circuit 34 via the vertical signal line 24. The reset transistor RST, the amplification transistor AMP, and the selection transistor SEL are, for example, CMOS transistors.

[0020] As shown in Fig. 3, the selection transistor SEL may be provided between the power supply line VDD and the amplification transistor AMP. In this case, the drain of the reset transistor RST is electrically connected to the power supply line VDD and the drain of the selection transistor SEL. The source of the selection transistor SEL is electrically connected to the drain of the amplification transistor AMP, and the gate of the selection transistor SEL is electrically connected to the pixel drive line 23 (see Fig. 1). The source of the amplification transistor AMP, which is the output end of the readout circuit 22, is electrically connected to the vertical signal line 24, and the gate of the amplification transistor AMP is electrically connected to the source of the reset transistor RST.

[0021] Also, as shown in FIG. 4 and FIG. 5, the FD transfer transistor FDG may be provided between the source of the reset transistor RST and the gate of the amplification transistor AMP. The FD transfer transistor FDG is used when switching the conversion efficiency. In general, the pixel signal is small when shooting in a dark place. Based on Q=CV, when performing charge-voltage conversion, if the FD capacitance C of the floating diffusion FD is large, the voltage V when converted by the amplification transistor AMP becomes small. On the other hand, in a bright place, the pixel signal becomes large, so if the FD capacitance C is not large, the floating diffusion FD cannot receive the charge of the photodiode PD. Furthermore, the FD capacitance C needs to be large so that the voltage V when converted by the amplification transistor AMP does not become too large. In light of this, when the FD transfer transistor FDG is turned on, the gate capacitance of the FD transfer transistor FDG increases, so the overall FD capacitance C becomes large. On the other hand, when the FD transfer transistor FDG is turned off, the overall FD capacitance C becomes small. In this way, by switching the FD transfer transistor FDG on / off, the FD capacitance C can be made variable and the conversion efficiency can be switched.

[0022] 6 is a diagram showing an example of a connection mode between a plurality of readout circuits 22 and a plurality of vertical signal lines 24. When a plurality of readout circuits 22 are arranged side by side in a column direction, which is the extension direction of the vertical signal lines 24, a plurality of vertical signal lines 24 may be assigned to each readout circuit 22. For example, as shown in FIG. 6, when four readout circuits 22 are arranged side by side in the extension direction of the vertical signal lines 24, a plurality of vertical signal lines 24 may be assigned to each readout circuit 22. In FIG. 6, identification numbers 1, 2, 3, and 4 are added to the end of the reference numerals of the vertical signal lines 24 in order to distinguish each vertical signal line 24.

[0023] (Example of the physical configuration of a solid-state imaging element) 7 and 8 are diagrams showing an example of a cross-sectional configuration in the horizontal direction of the solid-state imaging device 1. The upper diagrams of FIG. 7 and FIG. 8 are diagrams showing an example of a cross-sectional configuration in the horizontal direction of the first substrate 10 of FIG. 1. The lower diagrams of FIG. 7 and FIG. 8 are diagrams showing an example of a cross-sectional configuration in the horizontal direction of the second substrate 20 of FIG. 1. FIG. 7 illustrates a configuration in which two sets of four 2×2 sensor pixels 12 are arranged in the second direction H, and FIG. 8 illustrates a configuration in which four sets of four 2×2 sensor pixels 12 are arranged in the first direction V and the second direction H. In the upper cross-sectional views of FIG. 7 and FIG. 8, a diagram showing an example of a surface configuration of the semiconductor substrate 11 is superimposed on a diagram showing an example of a cross-sectional configuration in the horizontal direction of the first substrate 10 of FIG. 1. In addition, in the lower cross-sectional views of FIG. 7 and FIG. 8, a diagram showing an example of a surface configuration of the semiconductor substrate 21 is superimposed on a diagram showing an example of a cross-sectional configuration in the horizontal direction of the second substrate 20 of FIG. 1.

[0024] As shown in FIG. 7 and FIG. 8, the plurality of through wirings 54, the plurality of through wirings 48, and the plurality of through wirings 47 are arranged in a strip shape in a first direction V, which is the vertical direction in FIG. 7, or a second direction H, which is the horizontal direction in FIG. 8, in the plane of the first substrate 10. Note that FIG. 7 and FIG. 8 illustrate a case in which the plurality of through wirings 54, the plurality of through wirings 48, and the plurality of through wirings 47 are arranged in two columns in the first direction V or the second direction H. The first direction V or the second direction H is parallel to, for example, the column direction, which is one of the two arrangement directions of the plurality of sensor pixels 12 arranged in a matrix shape, that is, the row direction and the column direction. In the four sensor pixels 12 sharing the readout circuit 22, the four floating diffusions FD are arranged close to each other, for example, via the pixel separation portion 43. In the four sensor pixels 12 sharing the readout circuit 22, the gate electrodes TG of the four transfer transistors TR are arranged so as to surround the four floating diffusions FD, and for example, the four gate electrodes TG form a ring shape.

[0025] The insulating layer 53 present in the portion of the semiconductor substrate 21 through which the through-wires 54 penetrate is composed of a plurality of blocks extending in the first direction V or the second direction H. The semiconductor substrate 21 is composed of a plurality of island-shaped blocks 21A extending in the first direction V or the second direction H and arranged in the first direction V or the second direction H perpendicular to each other via the insulating layer 53. Each block 21A is provided with, for example, a plurality of sets of a reset transistor RST, an amplification transistor AMP, and a selection transistor SEL. One readout circuit 22 shared by four sensor pixels 12 is composed of, for example, a reset transistor RST, an amplification transistor AMP, and a selection transistor SEL in an area facing the four sensor pixels 12. One readout circuit 22 shared by four sensor pixels 12 is composed of, for example, an amplification transistor AMP in the block 21A to the left of the insulating layer 53, and a reset transistor RST and a selection transistor SEL in the block 21A to the right of the insulating layer 53.

[0026] 9 to 12 are diagrams showing an example of a wiring layout in a horizontal plane of the solid-state imaging device 1. In FIG. 9 to FIG. 12, a case is illustrated in which one readout circuit 22 shared by four sensor pixels 12 is provided in a region facing the four sensor pixels 12. The wirings shown in FIG. 9 to FIG. 12 are provided, for example, in different layers of a wiring layer (not shown) provided on the above-mentioned pixel transistor. The wiring layer has, for example, a plurality of pixel driving lines 23 and a plurality of vertical signal lines 24, and a pad electrode (not shown) exposed on the surface of the wiring layer and used for electrical connection between the second substrate 20 and the third substrate 30.

[0027] 9, the four adjacent through-wires 54 are electrically connected to a connection wire 55. The four adjacent through-wires 54 are further electrically connected to the gate of the amplification transistor AMP included in the block 21A on the left side of the insulating layer 53 and the gate of the reset transistor RST included in the block 21A on the right side of the insulating layer 53, for example, via the connection wire 55 and a connection portion 59.

[0028] The power supply line VDD is disposed at a position facing each of the readout circuits 22 arranged side by side in the second direction H, as shown in FIG. 10. The power supply line VDD is electrically connected to the drain of the amplification transistor AMP and the drain of the reset transistor RST of each of the readout circuits 22 arranged side by side in the second direction H, for example, via a connection portion 59. Two pixel driving lines 23 are disposed at a position facing each of the readout circuits 22 arranged side by side in the second direction H, for example. One pixel driving line 23 is, for example, a wiring RSTG electrically connected to the gate of the reset transistor RST of each of the readout circuits 22 arranged side by side in the second direction H. The other pixel driving line 23 is, for example, a wiring SELG electrically connected to the gate of the selection transistor SEL of each of the readout circuits 22 arranged side by side in the second direction H. In each readout circuit 22, the source of the amplification transistor AMP and the drain of the selection transistor SEL are electrically connected to each other, for example, via a wiring 25.

[0029] As shown in FIG. 11, the two power supply lines VSS are arranged at positions facing the readout circuits 22 arranged side by side in the second direction H, for example. Each power supply line VSS is electrically connected to a plurality of through-wires 47 at positions facing the sensor pixels 12 arranged side by side in the second direction H, for example. Four pixel drive lines 23 are arranged at positions facing the readout circuits 22 arranged side by side in the second direction H, for example. Each of the four pixel drive lines 23 is a line TRG electrically connected to the through-wire 48 of one of the four sensor pixels 12 corresponding to each readout circuit 22 arranged side by side in the second direction H, for example. That is, the four pixel drive lines 23 functioning as control lines are electrically connected to the gate electrodes TG of the transfer transistors TR of the sensor pixels 12 arranged side by side in the second direction H. In FIG. 11, in order to distinguish each line TRG, identifiers 1, 2, 3, and 4 are added to the end of each line TRG.

[0030] 12, the vertical signal line 24 is disposed, for example, at a position facing each of the readout circuits 22 arranged side by side in the first direction V. The vertical signal line 24 functioning as an output line is electrically connected, for example, to the source of the amplification transistor AMP which is the output end of each of the readout circuits 22 arranged side by side in the first direction V.

[0031] (Variation 1) 13 and 14 are diagrams showing a modified horizontal cross-sectional configuration of the solid-state imaging device 1. The upper diagrams of FIG. 13 and FIG. 14 show a modified horizontal cross-sectional configuration of the first substrate 10 of FIG. 1, and the lower diagram of FIG. 13 shows a modified horizontal cross-sectional configuration of the second substrate 20 of FIG. 1. In the upper cross-sectional views of FIG. 13 and FIG. 14, a diagram showing a modified surface configuration of the semiconductor substrate 11 of FIG. 1 is superimposed on a diagram showing a modified horizontal cross-sectional configuration of the first substrate 10 of FIG. 1. In the lower cross-sectional views of FIG. 13 and FIG. 14, a diagram showing a modified surface configuration of the semiconductor substrate 21 is superimposed on a diagram showing a modified horizontal cross-sectional configuration of the second substrate 20 of FIG. 1.

[0032] As shown in FIG. 13 and FIG. 14, the through wirings 54, the through wirings 48, and the through wirings 47, which are shown as dots arranged in a matrix in the figures, are arranged in a strip-like manner in the second direction H, which is the left-right direction in FIG. 13 and FIG. 14, within the plane of the first substrate 10. Note that FIG. 13 and FIG. 14 illustrate a case in which the through wirings 54, the through wirings 48, and the through wirings 47 are arranged in two rows in the second direction H. In the four sensor pixels 12 sharing the readout circuit 22, the four floating diffusions FD are arranged close to each other, for example, via the pixel separation portion 43. In the four sensor pixels 12 sharing the readout circuit 22, the four transfer gates TG1, TG2, TG3, and TG4 are arranged to surround the four floating diffusions FD, and for example, the four transfer gates TG form a ring shape.

[0033] The insulating layer 53 is composed of a plurality of blocks extending in the second direction H. The semiconductor substrate 21 is composed of a plurality of island-shaped blocks 21A extending in the second direction H and arranged side by side in a first direction V perpendicular to the second direction H via the insulating layer 53. Each block 21A is provided with, for example, a reset transistor RST, an amplification transistor AMP, and a selection transistor SEL. One readout circuit 22 shared by four sensor pixels 12 is, for example, not arranged directly opposite the four sensor pixels 12 but arranged shifted in the first direction V.

[0034] 13, one readout circuit 22 shared by four sensor pixels 12 is configured with a reset transistor RST, an amplification transistor AMP, and a selection transistor SEL located in an area of ​​the second substrate 20 shifted in the first direction V from an area facing the four sensor pixels 12. One readout circuit 22 shared by the four sensor pixels 12 is configured with, for example, an amplification transistor AMP, a reset transistor RST, and a selection transistor SEL in one block 21A.

[0035] 14, one readout circuit 22 shared by four sensor pixels 12 is configured with a reset transistor RST, an amplification transistor AMP, a selection transistor SEL, and an FD transfer transistor FDG located in an area of ​​the second substrate 20 shifted in the first direction V from an area facing the four sensor pixels 12. One readout circuit 22 shared by the four sensor pixels 12 is configured with, for example, an amplification transistor AMP, a reset transistor RST, a selection transistor SEL, and an FD transfer transistor FDG in one block 21A.

[0036] In this modification, one readout circuit 22 shared by four sensor pixels 12 is not disposed directly opposite the four sensor pixels 12, but is disposed shifted in the first direction V from a position directly opposite the four sensor pixels 12. In this case, the wiring 25 (see FIG. 10) can be shortened, or the wiring 25 can be omitted and the source of the amplification transistor AMP and the drain of the selection transistor SEL can be configured with a common impurity region. As a result, the size of the readout circuit 22 can be reduced, or the size of other parts in the readout circuit 22 can be increased.

[0037] (Variation 2) 15 is a diagram showing a modified horizontal cross-sectional configuration of the solid-state imaging device 1. In FIG. 15, a modified cross-sectional configuration of FIG.

[0038] In this modification, the semiconductor substrate 21 is composed of a plurality of island-shaped blocks 21A arranged side by side in the first direction V and the second direction H with an insulating layer 53 interposed therebetween. Each block 21A is provided with, for example, a set of a reset transistor RST, an amplifying transistor AMP, and a selection transistor SEL. In this case, crosstalk between adjacent readout circuits 22 can be suppressed by the insulating layer 53, and degradation of image quality due to a decrease in resolution and color mixing on a reproduced image can be suppressed.

[0039] (Variation 3) 16 is a diagram showing a modified horizontal cross-sectional configuration of the solid-state imaging device 1. In FIG. 16, a modified cross-sectional configuration of FIG.

[0040] In this modification, one readout circuit 22 shared by four sensor pixels 12 is not disposed directly opposite the four sensor pixels 12, but is disposed shifted in the first direction V. In this modification, similar to the modification 2, the semiconductor substrate 21 is further configured with a plurality of island-shaped blocks 21A arranged in the first direction V and the second direction H with an insulating layer 53 interposed therebetween. Each block 21A is provided with, for example, a set of a reset transistor RST, an amplification transistor AMP, and a selection transistor SEL. In this modification, a plurality of through wirings 47 and a plurality of through wirings 54 are also arranged in the second direction H. Specifically, the plurality of through wirings 47 are disposed between four through wirings 54 sharing a certain readout circuit 22 and four through wirings 54 sharing another readout circuit 22 adjacent to the readout circuit 22 in the second direction H. In this case, crosstalk between adjacent readout circuits 22 can be suppressed by the insulating layer 53 and the through wirings 47, and degradation of image quality due to a decrease in resolution and color mixing on a reproduced image can be suppressed.

[0041] (Variation 4) 17 is a diagram showing an example of a horizontal cross-sectional configuration of the above-mentioned solid-state imaging device 1. In FIG. 17, a modified example of the cross-sectional configuration of FIG.

[0042] In this modification, the first substrate 10 has a photodiode PD and a transfer transistor TR for each sensor pixel 12, and a floating diffusion FD is shared by every four sensor pixels 12. Therefore, in this modification, one through wiring 54 is provided for every four sensor pixels 12.

[0043] In the plurality of sensor pixels 12 arranged in a matrix, the four sensor pixels 12 corresponding to an area obtained by shifting a unit area corresponding to four sensor pixels 12 sharing one floating diffusion FD in the first direction V by one sensor pixel 12 will be referred to as four sensor pixels 12A for convenience. In this modification, the first substrate 10 shares the through wiring 47 with each of the four sensor pixels 12A. Therefore, in this modification, one through wiring 47 is provided for each of the four sensor pixels 12A.

[0044] In this modification, the first substrate 10 has a pixel separation section 43 that separates the photodiode PD and the transfer transistor TR for each sensor pixel 12. The pixel separation section 43 does not completely surround the sensor pixel 12 when viewed from the normal direction of the semiconductor substrate 11, and has gaps that are unformed regions near the through wiring 54 connected to the floating diffusion FD and near the through wiring 47. The gaps allow four sensor pixels 12 to share one through wiring 54, and four sensor pixels 12A to share one through wiring 47. In this modification, the second substrate 20 has a readout circuit 22 for each of the four sensor pixels 12 that share the floating diffusion FD.

[0045] Fig. 18 is a diagram showing an example of a horizontal cross-sectional configuration of a solid-state imaging element 1 according to this modified example. Fig. 18 shows a modified example of the cross-sectional configuration of Fig. 15. In this modified example, the first substrate 10 has a photodiode PD and a transfer transistor TR for each sensor pixel 12, and a floating diffusion FD is shared by every four sensor pixels 12. Furthermore, the first substrate 10 has a pixel separation section 43 that separates the photodiode PD and the transfer transistor TR for each sensor pixel 12.

[0046] Fig. 19 is a diagram showing an example of a horizontal cross-sectional configuration of a solid-state imaging element 1 according to this modified example. Fig. 19 shows a modified example of the cross-sectional configuration of Fig. 16. In this modified example, the first substrate 10 has a photodiode PD and a transfer transistor TR for each sensor pixel 12, and a floating diffusion FD is shared by every four sensor pixels 12. Furthermore, the first substrate 10 has a pixel separation section 43 that separates the photodiode PD and the transfer transistor TR for each sensor pixel 12.

[0047] (Variation 5) 20 is a diagram showing an example of a circuit configuration of a solid-state imaging device 1 according to a modified example. The solid-state imaging device 1 according to this modified example is a CMOS image sensor equipped with a column-parallel ADC.

[0048] As shown in Figure 20, the solid-state imaging element 1 of this modified example has a pixel area 13 in which a plurality of sensor pixels 12, each including a photoelectric conversion element, are arranged two-dimensionally in a matrix, as well as a vertical driving circuit 33, a column signal processing circuit 34, a reference voltage supply unit 38, a horizontal driving circuit 35, a horizontal output line 37, and a system control circuit 36.

[0049] In this system configuration, the system control circuit 36 ​​generates clock signals and control signals that serve as standards for the operation of the vertical drive circuit 33, the column signal processing circuit 34, the reference voltage supply unit 38, and the horizontal drive circuit 35, etc., based on the master clock MCK, and provides these signals to the vertical drive circuit 33, the column signal processing circuit 34, the reference voltage supply unit 38, and the horizontal drive circuit 35, etc.

[0050] The vertical drive circuit 33 is formed on the first substrate 10 together with each sensor pixel 12 in the pixel region 13, and is also formed on the second substrate 20 on which the readout circuit 22 is formed. The column signal processing circuit 34, the reference voltage supply unit 38, the horizontal drive circuit 35, the horizontal output line 37, and the system control circuit 36 ​​are formed on the third substrate 30.

[0051] Although not shown here, the sensor pixel 12 may have, for example, a configuration including a photodiode PD and a transfer transistor TR that transfers the charge obtained by photoelectric conversion in the photodiode PD to the floating diffusion FD. Although not shown here, the readout circuit 22 may have, for example, a three-transistor configuration including a reset transistor RST that controls the potential of the floating diffusion FD, an amplification transistor AMP that outputs a signal according to the potential of the floating diffusion FD, and a selection transistor SEL that selects pixels.

[0052] In the pixel region 13, the sensor pixels 12 are arranged two-dimensionally, and pixel drive lines 23 are wired for each row in this pixel arrangement of m rows and n columns, and vertical signal lines 24 are wired for each column. One end of each of the pixel drive lines 23 is connected to an output terminal corresponding to each row of a vertical drive circuit 33. The vertical drive circuit 33 is composed of a shift register or the like, and controls row addresses and row scanning of the pixel region 13 via the pixel drive lines 23.

[0053] The column signal processing circuit 34 has, for example, ADCs (analog-to-digital conversion circuits) 34-1 to 34-m provided for each pixel column in the pixel region 13, i.e., for each vertical signal line 24, and converts analog signals output for each column from each sensor pixel 12 in the pixel region 13 into digital signals and outputs them.

[0054] The reference voltage supply unit 38 has, for example, a DAC (digital-analog conversion circuit) 38A as a method for generating a reference voltage Vref having a so-called ramp waveform whose level changes in a sloping manner as time passes. Note that the method for generating the reference voltage Vref having a ramp waveform is not limited to the DAC 38A.

[0055] The DAC 38A generates a reference voltage Vref having a ramp waveform based on a clock CK provided from the system control circuit 36 ​​under the control of a control signal CS1 provided from the system control circuit 36, and supplies the reference voltage Vref to the ADCs 34-1 to 34-m of the column processing unit 15.

[0056] Each of the ADCs 34-1 to 34-m is configured to selectively perform AD conversion operations corresponding to each operation mode, namely, a normal frame rate mode in a progressive scanning system in which information of all the sensor pixels 12 is read out, and a high frame rate mode in which the exposure time of the sensor pixels 12 is set to 1 / N and the frame rate is increased to N times, for example, 2 times, compared to the normal frame rate mode. This switching of the operation mode is executed under the control of control signals CS2 and CS3 provided from the system control circuit 36. Also, an external system controller (not shown) provides the system control circuit 36 ​​with instruction information for switching between the normal frame rate mode and the high frame rate mode.

[0057] The ADCs 34-1 to 34-m all have the same configuration, and here, the ADC 34-m will be described as an example. The ADC 34-m has a comparator 34A, a counting means such as an up / down counter (U / DCNT) 34B, a transfer switch 34C, and a memory device 34D.

[0058] The comparator 34A compares the signal voltage Vx of the vertical signal line 24 corresponding to the signal output from each sensor pixel 12 in the nth column of the pixel area 13 with a ramp-wave reference voltage Vref supplied from the reference voltage supply unit 38, and, for example, when the reference voltage Vref is greater than the signal voltage Vx, the output Vco becomes an “H” level, and when the reference voltage Vref is equal to or lower than the signal voltage Vx, the output Vco becomes an “L” level.

[0059] The up / down counter 34B is an asynchronous counter, and under the control of a control signal CS2 provided from the system control circuit 36, a clock CK is provided from the system control circuit 36 ​​simultaneously with the DAC 18A, and the up / down counter 34B measures the comparison period from the start of the comparison operation in the comparator 34A to the end of the comparison operation by counting down (DOWN) or counting up (UP) in synchronization with the clock CK.

[0060] Specifically, in the normal frame rate mode, in the readout operation of a signal from one sensor pixel 12, the comparison time during the first readout operation is measured by counting down during the first readout operation, and the comparison time during the second readout operation is measured by counting up during the second readout operation.

[0061] On the other hand, in the high-speed frame rate mode, the count result for the sensor pixels 12 in a certain row is retained as is, and then, for the sensor pixels 12 in the next row, counting down from the previous count result during the first read operation is performed to measure the comparison time during the first read operation, and counting up during the second read operation is performed to measure the comparison time during the second read operation.

[0062] In the normal frame rate mode, under the control of a control signal CS3 provided from the system control circuit 36, the transfer switch 34C turns on (closed) when the counting operation of the up / down counter 34B for a certain row of sensor pixels 12 is completed, and transfers the counting result of the up / down counter 34B to the memory device 34D.

[0063] On the other hand, at a high frame rate of, for example, N=2, the up / down counter 34B remains in the off (open) state when it completes its counting operation for the sensor pixels 12 in a certain row, and then turns on when it completes its counting operation for the sensor pixels 12 in the next row, and transfers the counting result of the up / down counter 34B for two vertical pixels to the memory device 34D.

[0064] In this manner, the analog signals supplied for each column from each sensor pixel 12 in the pixel area 13 via the vertical signal line 24 are converted into N-bit digital signals by the operation of each of the comparators 34A and the up / down counters 34B in the ADCs 34-1 to 34-m, and stored in the memory device 34D.

[0065] The horizontal drive circuit 35 is configured with a shift register and the like, and controls the column addresses and column scanning of the ADCs 34-1 to 34-m in the column signal processing circuit 34. Under the control of the horizontal drive circuit 35, the N-bit digital signals AD converted by each of the ADCs 34-1 to 34-m are sequentially read out to a horizontal output line 37 and output as imaging data via the horizontal output line 37.

[0066] In addition, although not specifically shown because it is not directly related to the present disclosure, it is also possible to provide circuits, etc. that perform various types of signal processing on the imaging data output via the horizontal output line 37 in addition to the above-mentioned components.

[0067] In the solid-state imaging element 1 equipped with a column-parallel ADC according to this modified example of the above configuration, the count result of the up / down counter 34B can be selectively transferred to the memory device 34D via the transfer switch 34C, so that it is possible to independently control the count operation of the up / down counter 34B and the read operation of the count result of the up / down counter 34B to the horizontal output line 37.

[0068] FIG. 21 shows an example in which the solid-state imaging element 1 of FIG. 20 is configured by laminating three substrates, a first substrate 10, a second substrate 20, and a third substrate 30. In FIG.

[0069] In this modification, a pixel region 13 including a plurality of sensor pixels 12 is formed in the central portion of a first substrate 10, and a vertical drive circuit 33 is formed around the pixel region 13.

[0070] Furthermore, in the second substrate 20, a readout circuit region 15 including a plurality of readout circuits 22 is formed in the central portion, and a vertical drive circuit 33 is formed around the readout circuit region 15.

[0071] Moreover, on the third substrate 30, a column signal processing circuit 34, a horizontal drive circuit 35, a system control circuit 36, a horizontal output line 37, and a reference voltage supply unit 38 are formed.

[0072] 1 and its modified example, the above configuration prevents the chip size from increasing and prevents miniaturization of the area per pixel due to the structure electrically connecting the substrates. As a result, it is possible to provide a solid-state imaging device 1 with a three-layer structure that does not prevent miniaturization of the area per pixel with the same chip size as before. The vertical drive circuit 33 may be formed only on the first substrate 10 or only on the second substrate 20.

[0073] (Variation 6) Fig. 22 shows a modified example of the cross-sectional configuration of the solid-state imaging element 1 according to this modified example. In the configuration of Fig. 1 and its modified example, the solid-state imaging element 1 is configured by stacking three substrates, the first substrate 10, the second substrate 20, and the third substrate 30. However, in the configuration of Fig. 1 and its modified example, the solid-state imaging element 1 may be configured by stacking two substrates, the first substrate 10 and the second substrate 20.

[0074] At this time, the logic circuit 32 is formed separately on the first substrate 10 and the second substrate 20, for example, as shown in FIG. 22. Here, in the logic circuit 32, the circuit 32A provided on the first substrate 10 side is provided with a transistor having a gate structure in which a high dielectric constant film made of a material (e.g., high-k) that can withstand high temperature processes and a metal gate electrode are laminated. On the other hand, in the circuit 32B provided on the second substrate 20 side, a CoSi 2In this case, a low resistance region made of silicide such as NiSi or NiAl is formed. The low resistance region made of silicide is thus formed of a compound of the material of the semiconductor substrate and a metal.

[0075] This allows a high-temperature process such as thermal oxidation to be used when forming the sensor pixels 12. In addition, in the logic circuit 32, when the circuit 32B provided on the second substrate 20 side is provided with a low-resistance region 26 made of silicide on the surface of the impurity diffusion region in contact with the source electrode and the drain electrode, the contact resistance can be reduced. As a result, the operation speed of the logic circuit 32 can be increased.

[0076] 23 shows a modification of the cross-sectional configuration of the solid-state imaging device 1 according to the configuration shown in FIG. 1 and its modifications. In the logic circuit 32 of the third substrate 30 according to the configuration shown in FIG. 1 and its modifications, a CoSi 2 A low-resistance region 37 made of a silicide such as NiSi or NiAl may be formed. This allows a high-temperature process such as thermal oxidation to be used when forming the sensor pixel 12. Furthermore, when the low-resistance region 37 made of a silicide is provided on the surface of the impurity diffusion region in contact with the source electrode and the drain electrode in the logic circuit 32, the contact resistance can be reduced. As a result, the operation speed in the logic circuit 32 can be increased.

[0077] [Embodiment 1] The solid-state imaging device of the first embodiment will be described with reference to FIGS.

[0078] (Example of the overall configuration of a solid-state imaging device) Fig. 24 is a diagram showing a part of a cross section of the solid-state imaging element 100 according to the first embodiment of the present disclosure. As shown in Fig. 24, the solid-state imaging element 100 has a structure in which a substrate 200, a substrate 300, and a substrate 400 are bonded together. A surface 501 shown in Fig. 24 indicates the surface where the substrate 200 and the substrate 300 are bonded together. Furthermore, a surface 502 shown in Fig. 24 indicates the surface where the substrate 300 and the substrate 400 are bonded together. These substrates 200 to 400 are electrically connected to each other.

[0079] The substrate 200, which is a semiconductor substrate such as a silicon substrate, includes a plurality of photoelectric conversion elements 102. The photoelectric conversion elements 102 convert received light into an electrical signal according to the amount of received light through photoelectric conversion. One photoelectric conversion element 102 corresponds to one pixel. The photoelectric conversion element 102 is composed of, for example, a PN junction photodiode. One photoelectric conversion element 102 may include a plurality of photodiodes. In the example of FIG. 24, the photoelectric conversion element 102 is composed of an N-type semiconductor region 201 of the substrate 200 and a P-type semiconductor region 202 formed so as to cover the side surface of the N-type semiconductor region 201. The respective photoelectric conversion elements 102 are electrically separated by pixel separation sections 203 that separate the pixels. The pixel separation sections 203 are made of a material such as a metal, an insulating film (e.g., SiO 2 etc.), or a combination of these.

[0080] The lower end of the photoelectric conversion element 102, i.e., the lower surface of the substrate 200, is covered with an insulating film 211. The insulating film 211 is composed of, for example, a film having a fixed charge. A planarization film 213, which is an insulating film, may be further disposed on the lower end of the insulating film 211. The insulating film 211 is, for example, a metal oxide film such as hafnium oxide, tantalum oxide, or aluminum oxide. The planarization film 213 is, for example, an insulating film such as silicon oxide or silicon nitride. The insulating film 211 and the planarization film 213 may each be provided in a plurality of layers.

[0081] A color filter 212 is disposed below the insulating film 211. An on-chip lens 214 is disposed below the color filter 212. The on-chip lens 214 collects the irradiated light. The collected light is guided to the photoelectric conversion element 102 via the color filter 212.

[0082] A P-type semiconductor region 204 (P well) is formed on the photoelectric conversion element 102. In the example of Fig. 24, the P-type semiconductor region 202 constituting the photoelectric conversion element 102 protrudes so as to cover a part of the side surface of the semiconductor region 204. However, the depth of the P-type semiconductor region 202 is arbitrary. For example, the upper surface of the semiconductor region 202 and the lower surface of the semiconductor region 204 may be at the same height.

[0083] An N-type transfer transistor 103 is disposed further above the photoelectric conversion element 102. Specifically, an N-type drain region 221 and an N-type source region 222 are formed near the surface of the semiconductor region 204. A gate electrode 223 is formed between the N-type drain region 221 and the N-type source region 222 on the semiconductor region 204. The drain region 221, the source region 222, and the gate electrode 223 constitute the transfer transistor 103.

[0084] 24, the gate electrode 223 is connected to the N-type semiconductor region 201 that constitutes the photoelectric conversion element 102. In this manner, one transfer transistor 103 is provided for one photoelectric conversion element 102. The transfer transistor 103 transfers an electrical signal output from the photoelectric conversion element 102 to the pixel transistor.

[0085] The source region 222 of the transfer transistor 103 functions as a floating diffusion (FD). The floating diffusion temporarily holds an electrical signal output from the photoelectric conversion element 102. The transfer transistor 103 including the source region 222 as a floating diffusion is covered with an insulating film 240. A substrate 300 is disposed on the insulating film 240.

[0086] The substrate 300, which is a semiconductor substrate such as a P-type silicon substrate, is provided with pixel transistors including a plurality of N-type amplification transistors 104. One pixel transistor such as the amplification transistor 104 is provided for one transfer transistor 103. The pixel transistor performs a process of reading out an electrical signal according to the amount of light received by the photoelectric conversion element 102. For example, the amplification transistor 104 amplifies and outputs the electrical signal transferred from the photoelectric conversion element 102 by the transfer transistor 103.

[0087] A wiring D1 is connected to the gate electrode 313 of the amplification transistor 104. The wiring D1 is connected to the source region 222 of the transfer transistor 103, which serves as a floating diffusion, via a contact Cfd.

[0088] 24, wirings D1 to D4 are formed across four layers on the substrate 300. The wiring D1 is a wiring formed in the bottom layer of the first layer. The wiring D4 is a wiring formed in the top layer of the fourth layer. The number of wiring layers is not limited to four and can be changed arbitrarily depending on design conditions, etc. The amplification transistor 104 and the wirings D1 to D4 are covered with an insulating film 340.

[0089] The substrate 400, which is a semiconductor substrate such as a silicon substrate, is inverted and bonded onto the wiring D4 of the substrate 300. In the example of FIG. 24, a junction 503 between the wiring D4 and the wiring of the substrate 400 overlaps a pixel region where pixels are arranged. A plurality of logic transistors Tr are connected to the wiring of the substrate 400. The wiring and the logic transistors Tr of the substrate 400 are covered with an insulating film 440. The wiring of the substrate 400 and the logic transistors Tr form a logic circuit as a signal processing circuit. The logic circuit corresponds to a peripheral circuit of the solid-state imaging element 100 that processes electric signals generated by the photoelectric conversion element 102, etc.

[0090] (Example of detailed configuration of solid-state imaging element) Next, a detailed configuration example of the solid-state imaging element 100 of the first embodiment will be described with reference to FIG. 25. FIG. 25 is a schematic diagram showing the vicinity of the bonding position of the substrates 200 and 300 of the solid-state imaging element 100 according to the first embodiment of the present disclosure. FIG. 25(a) is a cross-sectional view showing the vicinity of the bonding position of the substrates 200 and 300, and (b) is a top view of the substrate 300. However, in FIG. 25(a), the position of the contact Cg is shifted. Also, in FIG. 25(b), the insulating film 340 and the wiring D1 are omitted. Also, in FIG. 25, the amplification transistor 104 is shown as an example of a pixel transistor.

[0091] 25, the solid-state imaging element 100 includes a substrate 200 as a first semiconductor substrate having a photoelectric conversion element 102, and a substrate 300 as a second semiconductor substrate facing the substrate 200 via an insulating film 240. The substrate 200 is grounded. That is, the potential of the substrate 200 is fixed to 0V. The substrate 200 includes a transfer transistor 103 including a gate electrode 223 and an N-type source region 222 as a floating diffusion. The transfer transistor 103 is configured as, for example, a MOS (Metal Oxide Semiconductor) type field effect transistor (MOSFET).

[0092] The substrate 300 has an amplifier transistor 104 that amplifies an electric signal output from the photoelectric conversion element 102 on a main surface MSa as a first main surface. The amplifier transistor 104 is configured as, for example, a MOSFET. The amplifier transistor 104 has an N-type source region 312 and an N-type drain region 311 provided on the substrate 300. A gate electrode 313 of the amplifier transistor 104 is disposed on the substrate 300 between the source region 312 and the drain region 311. The source region 312 is provided with a contact Cs that is connected to an upper layer wiring (not shown). The drain region 311 is provided with a contact Cd that is connected to a wiring D1a such as Cu. The gate electrode 313 is provided with a contact Cg that is connected to a wiring D1 such as Cu. A contact Cfd is connected to the wiring D1. The other end of the contact Cfd is connected to the source region 222 of the transfer transistor 103.

[0093] The substrate 300 has a substrate contact layer 302 as a region with a lower resistance than the substrate 300 on a principal surface MSb as a second principal surface opposite to the principal surface MSa. Specifically, the substrate 300 has a certain conductivity type, for example, P type, and the substrate contact layer 302 contains impurities at a higher concentration than other regions 301 of the substrate 300. An N-type source region 312 and an N-type drain region 311 of the amplifier transistor 104 provided on the principal surface MSa, and a P-type drain region 312 and an N-type drain region 313 of the amplifier transistor 104 provided on the principal surface MSb are formed on the principal surface MSa. + The substrate contact layer 302 is separated from the substrate contact layer 302 by another region 301 of the substrate 300. Here, the substrate contact layer 302 does not necessarily have to have a low resistance as a whole, nor does it have to contain a high concentration of impurities. It is sufficient that at least a part of the substrate contact layer 302 has a lower resistance than the other region 301 of the substrate 300 and contains a high concentration of impurities. Therefore, the impurity concentration in the substrate contact layer 302 does not have to be uniform throughout the substrate contact layer 302.

[0094] The substrate 300 is grounded via the substrate contact layer 302. Specifically, the solid-state imaging element 100 includes a contact Csub extending from the substrate contact layer 302 of the substrate 300 toward the substrate 200. More specifically, the substrate 300 is disposed with the main surface MSb facing the substrate 200, and the solid-state imaging element 100 includes a contact Csub connecting the substrate contact layer 302 of the substrate 300 to the substrate 200. As a result, the substrate 300 is grounded via the substrate contact layer 302 and the substrate 200. That is, the potential of the substrate 300 is fixed to 0V.

[0095] (Example of manufacturing process for solid-state imaging device) Next, an example of a manufacturing process of the solid-state imaging element 100 of embodiment 1 will be described with reference to Figs. 26 to 28. Figs. 26 to 28 are flow charts showing an example of a procedure of the manufacturing process of the solid-state imaging element 100 according to embodiment 1 of the present disclosure. The left figures in Figs. 26 to 28 are cross-sectional views in the manufacturing process of the solid-state imaging element 100. The right figures in Figs. 26 to 28, excluding Fig. 26(a2), are top views in the manufacturing process of the solid-state imaging element 100.

[0096] 26(a1), a photoelectric conversion element 102 including an N-type semiconductor region 201, a P-type semiconductor region 204, a gate electrode 223 of a transfer transistor 103, and a source region 222 as a floating diffusion are formed on a substrate 200. The gate electrode 223 and the source region 222 are covered with an insulating film 240. A through hole is formed through the insulating film 240 to reach the substrate 200, and a conductive material such as W is embedded in the through hole to form a contact Csub.

[0097] 26(a2), a substrate contact layer 302 is formed on a main surface MSb of a substrate 300, which is a P-type silicon substrate or the like. The substrate contact layer 302 can be formed by, for example, an ion implantation method, a solid-phase diffusion method, a plasma doping method, or the like.

[0098] When using ion implantation, for example, 1×10 16 / cm 3 ~1×1020 / cm 3 Boron is implanted into the main surface MSb of the substrate 300 at a dose of about 1000 nm, and a heat treatment is performed at a temperature of about 600° C. to 900° C., whereby the substrate contact layer 302 is formed.

[0099] When using the solid-phase diffusion method, a silicon oxide film such as a borosilicate glass (BSG) film is doped with B by low-pressure chemical vapor deposition (LP-CVD). 2 H 6 / SiH 4 / O 2 A film is formed on the main surface MSb of the substrate 300 using a gas. Then, a heat treatment is performed at about 900° C. to diffuse boron toward the substrate 300. Thereafter, the BSG film is removed using hydrofluoric acid, thereby forming the substrate contact layer 302.

[0100] When using the plasma doping method, B 2 H 6 The / He mixed gas is excited into plasma to diffuse boron into the main surface MSb side of the substrate 300, thereby forming a substrate contact layer 302.

[0101] As shown in FIGS. 26(b1) and 26(b2), the substrate 300 on which the substrate contact layer 302 has been formed is bonded to the substrate 200 of FIG. 26(a1) with the main surface MSb side facing the substrate 200. At this time, a pressure of 0.1 MPa to several MPa is applied, and a heat treatment of about 350° C. to 600° C. is performed. As a result, the substrates 300 and 200 are bonded via the insulating film 240. Before bonding the substrates 300 and 200, O is applied to the bonding surface of the substrate 300 and the bonding surface of the substrate 200, respectively. 2 A plasma treatment may be performed.

[0102] As shown in FIGS. 27(a1) and (a2), the substrate 300 is ground to a thickness of several tenths of a micrometer to several micrometers by chemical mechanical polishing (CMP).

[0103] 27(b1) and (b2), element isolation is performed on the substrate 300, leaving behind an area where pixel transistors such as the amplifying transistor 104 are to be formed. Specifically, a resist pattern is formed by photolithography in the area where the pixel transistors are to be formed, and other areas are etched by dry etching. After ashing the resist pattern, an insulating film 340 such as a silicon oxide film is formed by a CVD method to backfill the area where the substrate 300 was etched away. Excess insulating film 340 is removed by CMP to expose the surface of the substrate 300.

[0104] 28(a1) and 28(a2), an amplifying transistor 104 is formed on a main surface MSa of a substrate 300. Specifically, a gate oxide film (not shown) is formed on the surface of the substrate 300 by thermal oxidation. A polysilicon film or the like is formed by CVD, a resist pattern is formed by photolithography, the polysilicon film is etched, and the resist pattern is ashed to form a gate electrode 313. Phosphorus or arsenic is implanted by ion implantation into the substrate 300 on both sides of the gate electrode 313, and a heat treatment is performed by high temperature rapid annealing (RTA) to form a source region 312 and a drain region 311.

[0105] As shown in Fig. 28(b1) and (b2), contacts Cg, Cs, Cd, and Cfd are formed. Specifically, an insulating film 340 that covers the amplifying transistor 104 is further formed by a CVD method, and the surface of the insulating film 340 is planarized by CMP. A resist pattern is formed on the surface of the insulating film 340 by photolithography, and through holes reaching the gate electrode 313, the source region 312, the drain region 311, and the substrate 200 are formed by dry etching. After removing the resist pattern by ashing, a W film or the like is filled into each through hole by a CVD method, and excess W film is removed by CMP.

[0106] Thereafter, the wirings D1 to D4 are formed, and the substrate 400 on which the logic transistors Tr and the wirings are formed is bonded, completing the manufacturing process of the solid-state imaging device 100.

[0107] (Comparative Example) Next, the configurations of Comparative Examples 1 and 2 will be compared with the configuration of Embodiment 1 using Fig. 29. Fig. 29 is a diagram for comparing the solid-state imaging elements according to Embodiment 1 and Comparative Examples 1 and 2 of the present disclosure.

[0108] In the solid-state imaging device of Patent Document 1, a semiconductor substrate on which a pixel region is formed is joined to a semiconductor substrate on which a logic circuit is formed. That is, the photoelectric conversion element and the pixel transistor are formed on the same semiconductor substrate. However, in this configuration, it is difficult to secure a sufficient space for arranging the pixel transistor. If the size of the amplification transistor among the pixel transistors is small, it is difficult to sufficiently reduce the noise level of RTS (Random Telegraph Signal) noise and the like.

[0109] Therefore, for example, it is conceivable to separate the substrate on which the photoelectric conversion element is formed from the substrate on which the pixel transistor is formed and to join them. Such a configuration is shown in FIG. 29 as Comparative Example 1. Here, the substrate on which the pixel transistor is formed is joined to the other substrate via an insulating film, so that it is a floating substrate with an unfixed substrate potential. If the substrate potential is unstable, the operation of the pixel transistor becomes unstable. To improve this, for example, as in Comparative Example 2 shown in FIG. 29, it is conceivable to provide a substrate contact layer 302' separated from the region where the amplifying transistor is formed by the element isolation region STI. The substrate contact layer 302' can be connected to the ground line in the upper layer to fix the substrate potential. However, in the configuration of Comparative Example 2, the size of the amplifying transistor must be reduced due to the pressure from the element isolation region STI and the substrate contact layer 302', and the effect of separating the substrates is lost.

[0110] In the solid-state imaging device 100 of the first embodiment, a substrate contact layer 302 for fixing the potential of the substrate 300 is disposed on the main surface MSb of the substrate 300 opposite to the side on which the amplification transistor 104 is formed. This prevents the area on the main surface MSa side from being reduced by the substrate contact layer 302. In addition, there is no need to provide a separate element isolation layer for isolating the substrate contact layer 302. This makes it possible to fix the potential of the substrate 300 while ensuring a space for arranging the amplification transistor 104.

[0111] In comparison with each configuration, the size of the amplification transistor (AMP Tr size) is Comparative Example 1: Comparative Example 2: Embodiment 1 = 3:1:3, and the same size is obtained in the embodiment 1 as in the comparative example 1. As a result, the noise level of the RTS noise is Comparative Example 1: Comparative Example 2: Embodiment 1 = 0.33:1:0.33, and is sufficiently reduced in the embodiment 1.

[0112] With the above-described configuration, the solid-state imaging device 100 of the first embodiment can fully utilize the advantages of separating the photoelectric conversion element 102 and the pixel transistors onto the separate substrates 200, 300. In other words, the areas of both the photoelectric conversion element 102 and the pixel transistors can be enlarged compared to when the photoelectric conversion element and the pixel transistors are arranged on the same substrate. In addition, the number of pixels per unit area can be increased.

[0113] Furthermore, in the solid-state imaging device 100 of the first embodiment, the substrate 200 and the substrate 300 are connected via the contact Cfd. Also, the substrate 300 and the substrate 400 are connected by the wiring D4 of the substrate 300 and the wiring of the substrate 400. With these configurations, the area required for connecting the substrates can be smaller than when, for example, the substrates are connected by through silicon vias (TSVs) provided in the peripheral regions of the substrates. Therefore, the chip size of the solid-state imaging device 100 can be reduced. Alternatively, the pixel region can be expanded with the same chip size.

[0114] In addition, in the solid-state imaging device 100 of the first embodiment, the contact Cfd and the junction point 503 between the wiring D4 of the substrate 300 and the wiring of the substrate 400 are disposed within the pixel region. This makes it possible to further reduce the chip size or enlarge the pixel region.

[0115] FIG. 30 shows a more detailed top view of each component.

[0116] Fig. 30 is a diagram showing the arrangement of pixel transistors of solid-state imaging devices according to the first embodiment and the second comparative example of the present disclosure. Fig. 30(a) is a top view of a substrate on which pixel transistors of the second comparative example are formed, (b) is a top view of the substrate 300 of the first embodiment, and (c) is a top view of the substrate 200 of the first embodiment. However, part of the insulating film is omitted in Fig. 30.

[0117] 30(c), the gate electrode 223 of the transfer transistor 103 is formed in a substantially U-shaped crank shape. Both ends of the U-shaped gate electrode 223 are disposed on two photoelectric conversion elements 102, respectively, so that the transfer transistor 103 can receive an electrical signal from the photoelectric conversion element 102 and transfer it to the amplification transistor 104. The gate electrode 223 of the transfer transistor 103 is connected to upper layer wiring via contacts Ctga and Ctgb.

[0118] 30(b), the substrate 300 of the first embodiment includes an amplification transistor 104, a selection transistor 106, and a reset transistor 105. Up until now, only the amplification transistor 104 has been shown as an example of a pixel transistor, but as described above, the pixel transistor also includes the reset transistor 105, the selection transistor 106, and the like.

[0119] The selection transistor 106 selects whether or not to transmit an electrical signal to the upper layer wirings D1 to D4 in order to process the electrical signal amplified by the amplification transistor 104. The selection transistor 106 has a gate electrode 323, a source region 322, and a drain region 321. The gate electrode 323 of the selection transistor 106 is arranged in parallel with the gate electrode 313 of the amplification transistor 104, and is connected to the upper layer wirings D1 to D4 via a contact Csg. The source region 322 of the selection transistor 106 is connected to the upper layer wirings D1 to D4 via a contact Css. The drain region 321 of the selection transistor 106 is connected to the source region 312 of the amplification transistor 104.

[0120] The reset transistor 105 resets (initializes) the potential of the gate of the amplification transistor 104 to the power supply potential. The reset transistor 105 also resets the potential of the floating diffusion. The reset transistor 105 has a gate electrode 333, a source region 332, and a drain region 331. The gate electrode 333 of the reset transistor 105 is arranged in series with the gate electrode 323 of the selection transistor 106, and is connected to the upper wirings D1 to D4 via a contact Crg. The source region 332 of the reset transistor 105 is connected to the gate electrode 313 of the amplification transistor 104 via contacts Crs, Cag, and the wiring D1. The drain region 331 of the reset transistor 105 is connected to the upper wirings D1 to D4 via a contact Crd.

[0121] A gate electrode 313 of the amplification transistor 104 is connected to the floating diffusion, which is the source region 222 of the transfer transistor 103, via contacts Cag and Cfd and a wiring D1. A drain region 311 of the amplification transistor 104 is connected to upper wirings D1 to D4 via a contact Cad.

[0122] 30(a), the amplifier transistor 104' and the select transistor 106' are arranged in parallel, and the select transistor 106' and the reset transistor 105' are arranged in series, also in the configuration of Comparative Example 2. However, since a part of the area on the substrate is occupied by the substrate contact layer 302' and the element isolation region STI, the size of the amplifier transistor 104' is limited.

[0123] In this way, even in the detailed diagram showing pixel transistors other than the amplification transistor, it is clear that the configuration of the first embodiment has an advantage over the configuration of the second comparative example.

[0124] (Variation 1) Next, a solid-state imaging element according to Modification 1 of the first embodiment will be described with reference to Fig. 31. Fig. 31 is a schematic diagram showing the vicinity of the bonding position of the substrates 200 and 300 of the solid-state imaging element according to Modification 1 of the first embodiment of the present disclosure.

[0125] 31, the solid-state imaging element of the first modification includes a contact Csub with at least one wiring D0 such as W interposed therebetween. This allows the connection position between the substrate 200 and the substrate contact layer 302 of the substrate 300 to be appropriately adjusted. In other words, the connection positions between the substrate 200 and the substrate contact layer 302 of the substrate 300 do not need to overlap in the vertical direction.

[0126] Such a configuration increases the degree of freedom in the relative positions of the substrates 200 and 300 and in the arrangement of the elements within the substrates 200 and 300.

[0127] (Variation 2) Next, a solid-state imaging element according to Modification 2 of Embodiment 1 will be described with reference to Fig. 32. Fig. 32 is a schematic diagram showing the vicinity of the bonding position of the substrates 200 and 300a of the solid-state imaging element according to Modification 2 of Embodiment 1 of the present disclosure.

[0128] 32, the solid-state imaging element of the second modification has a substrate contact layer 302a on a part of the main surface MSb of the substrate 300a. In this manner, the substrate contact layer 302a does not need to cover the entire main surface MSb of the substrate 300a. In principle, the substrate contact layer 302a only needs to have an area that takes into account the cross-sectional area required by the contact Csub and the amount of misalignment that occurs when the contact Csub is connected.

[0129] (Variation 3) Next, a solid-state imaging element 110 according to Modification 3 of the first embodiment will be described with reference to Fig. 33. Fig. 33 is a diagram showing a part of a cross section of the solid-state imaging element 110 according to Modification 3 of the first embodiment of the present disclosure.

[0130] 33, in the solid-state imaging element 110 of the second modification, the gate electrode 223 of the transfer transistor 103 is disposed on the semiconductor region 204 without being connected to the photoelectric conversion element 102. In other words, the transfer transistor 103 may have the gate electrode 223 as a planar transfer gate.

[0131] (Variation 4) Next, a solid-state imaging element 120 according to Modification 4 of the first embodiment will be described with reference to Fig. 34. Fig. 34 is a diagram showing a part of a cross section of the solid-state imaging element 120 according to Modification 4 of the first embodiment of the present disclosure.

[0132] 34, in the solid-state imaging element 120 of the fourth modification, the substrate 300 and the substrate 400 are electrically connected to each other in a region of the substrate 200 facing the peripheral region 14. The peripheral region 14 corresponds to a frame region of the substrate 200, and is provided on the periphery of the pixel region 13. The substrate 300 has a plurality of pad electrodes 58 in a region facing the peripheral region 14, and the substrate 400 has a plurality of pad electrodes 64 in a region facing the peripheral region 14. The substrates 300 and 400 are electrically connected to each other by bonding the pad electrodes 58, 64 provided in the region facing the peripheral region 14.

[0133] In this way, since the substrates 300 and 400 are connected by bonding the pad electrodes 58, 64 together, the chip size can be reduced or the pixel area can be enlarged compared to, for example, a case in which the substrates are connected together by TSVs provided in the peripheral regions of the substrates.

[0134] [Embodiment 2] Next, a solid-state imaging element according to the second embodiment will be described with reference to Fig. 35 to Fig. 44. The solid-state imaging element according to the second embodiment differs from that according to the first embodiment in the shape of the substrate contact layer 302b.

[0135] (Example of detailed configuration of solid-state imaging element) Fig. 35 is a schematic diagram showing the vicinity of the bonding position of the substrates 200 and 300b of the solid-state imaging element according to the second embodiment of the present disclosure. Fig. 35(a) is a cross-sectional view showing the vicinity of the bonding position of the substrates 200 and 300b, and (b) is a top view of the substrate 300b. However, in Fig. 35(a), the position of the contact Cg is shifted. Also, in Fig. 35(b), the insulating film 340 and the wiring D1 are omitted. Also, in Fig. 35, an amplification transistor 104b is shown as an example of a pixel transistor.

[0136] 35, the substrate 300b has a substrate contact layer 302b as a region having a lower resistance than the substrate 300b on a main surface MSb as a second main surface opposite to a main surface MSa as a first main surface. Specifically, the substrate 300b has a certain conductivity type, for example, P type, and the substrate contact layer 302b contains a higher concentration of impurities than the other region 301b of the substrate 300b. That is, the substrate contact layer 302b is P + Here, it is sufficient that at least a portion of the substrate contact layer 302b has a lower resistance than the other region 301b of the substrate 300b and contains a high concentration of impurities.

[0137] The substrate contact layer 302b of the substrate 300b has an extension 303 that extends in a direction along the substrate 300b toward the outside of the substrate 300b. The direction along the substrate 300b includes a direction horizontal to the substrate 300b. In other words, the extension 303 extends toward the outside of the substrate 300b in a direction horizontal or substantially horizontal to the substrate 300b. In other words, the extension 303 protrudes from the side surface of the substrate 300b.

[0138] The substrate 300b is grounded via the substrate contact layer 302b. Specifically, the solid-state imaging device of the second embodiment includes a contact Csubb extending from the substrate contact layer 302b of the substrate 300b to the side opposite to the substrate 200. More specifically, the extension 303 has a main surface MSc as a third main surface facing the same side as the main surface MSa of the substrate 300b, and includes a contact Csubb whose one end is connected to the main surface MSc of the extension 303 and whose other end is grounded. Other regions 301b and the like of the substrate 300b are not present on the main surface MSc of the extension 303. Therefore, the contact Csubb connected to the main surface MSc of the extension 303 can be extended upward and connected to the wiring D1 and the like. This allows the substrate 300b to be grounded by connecting to a ground line via the substrate contact layer 302b, the contact Csubb, and the wirings D1 to D4. That is, the potential of the substrate 300b is fixed to 0V.

[0139] The substrate 300b has an amplifier transistor 104b on the main surface MSa for amplifying an electric signal output from the photoelectric conversion element 102. The amplifier transistor 104b is configured as, for example, a MOSFET. The amplifier transistor 104b has an N-type source region 312b and an N-type drain region 311b provided on the substrate 300b. A gate electrode 313b of the amplifier transistor 104b is disposed on the substrate 300b between the source region 312b and the drain region 311b. The area of ​​the main surface MSa of the substrate 300b is reduced by, for example, the area of ​​the extension portion 303 of the substrate contact layer 302b. Accordingly, the size of the amplifier transistor 104b is also slightly reduced. The size of the amplifier transistor 104b is smaller than that of the amplifier transistor 104 of the first embodiment and larger than that of the amplifier transistor of the second comparative example.

[0140] (Example of manufacturing process for solid-state imaging device) Next, an example of a manufacturing process of the solid-state imaging element of the second embodiment will be described with reference to Figs. 36 and 37. Figs. 36 and 37 are flow diagrams showing an example of a procedure of the manufacturing process of the solid-state imaging element according to the second embodiment of the present disclosure. The left diagrams of Figs. 36 and 37 are cross-sectional views in the manufacturing process of the solid-state imaging element. The right diagrams of Figs. 36 and 37 are top views in the manufacturing process of the solid-state imaging element.

[0141] The solid-state imaging device of the second embodiment undergoes the same manufacturing process as that of the first embodiment from Figure 26 to Figure 27. Here, an example of the manufacturing process thereafter will be described.

[0142] 36(a1) and (a2), an extension 303 is formed in a substrate contact layer 302b of a substrate 300b that has been subjected to element isolation. Specifically, a resist pattern having an opening corresponding to the extension 303 of the substrate 300b is formed by photolithography, the substrate 300b at the opening is etched by dry etching, and the resist pattern is ashed. As a result, the main surface MSc of the extension 303 is exposed.

[0143] 36(b1) and (b2), an insulating film 340 such as a silicon oxide film is formed by CVD on the main surface MSc of the extension portion 303 to backfill the portion where the substrate 300b has been etched away. Excess insulating film 340 is removed by CMP to expose the surface of the substrate 300b.

[0144] As shown in FIGS. 37(a1) and (a2), an amplifying transistor 104b is formed on the main surface MSa of the substrate 300b by a method similar to that for the amplifying transistor 104 of the first embodiment.

[0145] 37(b1) and (b2), contacts Cg, Cs, Cd, and Cfd are formed in the same manner as in embodiment 1. In addition, contact Csubb can also be formed in the same manner as other contacts Cg, Cs, Cd, and Cfd.

[0146] Thereafter, the wirings D1 to D4 are formed, and the substrate 400 on which the logic transistors Tr and the wirings are formed is bonded, completing the manufacturing process of the solid-state imaging element of the second embodiment.

[0147] (Comparative Example) Next, the configurations of the above-described comparative examples 1 and 2 will be compared with the configuration of embodiment 2 using Fig. 38. Fig. 38 is a diagram for comparing the solid-state imaging elements according to embodiment 2 of the present disclosure and comparative examples 1 and 2.

[0148] In the solid-state imaging element of the second embodiment, the contact Csubb is connected to the main surface MSc side of the substrate contact layer 302b arranged on the main surface MSb, which faces the same side as the main surface MSa. Therefore, although the amplification transistor 104b is reduced in size by the extension portion 303 of the substrate contact layer 302b, the solid-state imaging element of the second embodiment is still superior to the first and second comparative examples.

[0149] The size of the amplification transistor (AMP Tr size) is Comparative Example 1: Comparative Example 2: Embodiment 2 = 3:1:2, and a larger size is obtained in Embodiment 2 than in Comparative Example 2. As a result, the noise level of the RTS noise is Comparative Example 1: Comparative Example 2: Embodiment 2 = 0.33:1:0.5, and is sufficiently reduced in Embodiment 2 as well.

[0150] FIG. 39 shows a more detailed top view of each component.

[0151] Fig. 39 is a diagram showing the arrangement of pixel transistors of solid-state imaging devices according to embodiment 2 of the present disclosure and comparative example 2. Fig. 39(a) is a top view of a substrate on which pixel transistors of comparative example 2 are formed, (b) is a top view of substrate 300b of embodiment 2, and (c) is a top view of substrate 200 of embodiment 2. However, part of the insulating film is omitted in Fig. 39.

[0152] As shown in FIG. 39(c), the solid-state imaging device of the second embodiment also includes a substrate 200 having a similar configuration to that of the first embodiment.

[0153] 39(b), the solid-state imaging element of the second embodiment also includes an amplifying transistor 104b, a selecting transistor 106, and a reset transistor 105, which are arranged in a manner similar to that of the first embodiment. The solid-state imaging element of the second embodiment differs from the first embodiment in that an extension 303 of a substrate contact layer 302b occupies a part of the region of a substrate 300b, and the amplifying transistor 104b is reduced in size accordingly.

[0154] FIG. 40 shows cross-sectional views of each part of FIG.

[0155] Fig. 40 is a diagram showing connections between the elements of a solid-state imaging device according to embodiment 2 of the present disclosure, Fig. 40(a) is a top view of a substrate 300b according to embodiment 2, (b) is a cross-sectional view taken along line A-A' in (a), (c) is a cross-sectional view taken along line B-B' in (a), and (d) is a cross-sectional view taken along line C-C' in (a).

[0156] 40(b), the substrate contact layer 302b is connected to the upper wirings D1 to D4 via a contact Csubb in the extension 303 and is grounded. The drain region 311b of the amplification transistor 104b is connected to the upper wirings D1 to D4 via a contact Cad. The source region 322 of the selection transistor 106 is connected to the upper wirings D1 to D4 via a contact Css.

[0157] As shown in FIG. 40(c), the source region 222 as a floating diffusion of the transfer transistor 103 is connected to a wiring D1 via a contact Cfd. Although not shown, the wiring D1 is connected to a gate electrode 313b of the amplification transistor 104b. The gate electrode 223 of the transfer transistor 103 is connected to a wiring D0 such as W via a contact Ctga. The wiring D0 is connected to an upper layer wiring via a contact Ctgb.

[0158] 40(d), the source region 332 of the reset transistor 105 is connected to the wiring D1 via a contact Crs. Although not shown, as described above, the wiring D1 is connected to the gate electrode 313b of the amplification transistor 104b. The drain region 331 of the reset transistor 105 is connected to the upper wirings D1 to D4 via a contact Crd.

[0159] (Variation 1) Next, a solid-state imaging element according to Modification 1 of Embodiment 2 will be described with reference to Fig. 41. Fig. 41 is a schematic diagram showing the vicinity of the bonding position of the substrates 200 and 300c of the solid-state imaging element according to Modification 1 of Embodiment 2 of the present disclosure.

[0160] As shown in FIG. 41, the solid-state imaging element of the first modification includes a contact Csubc that passes through the extension 303c, has one end connected to the substrate 200, and has the other end grounded. That is, the substrate contact layer 302c of the substrate 300c has an extension 303c that passes through the contact Csubc. The contact Csubc is connected to a ground line via upper layer wirings D1 to D4. The substrate 200 is grounded via the contact Csubc. The substrate 300c is grounded via the extension 303c of the substrate contact layer 302c and the contact Csubc.

[0161] With this configuration, the substrate 200 and the substrate 300c can be grounded using a common configuration, which can simplify the wiring structure and reduce the volume occupied by the configuration related to grounding.

[0162] (Variation 2) Next, a solid-state imaging element according to Modification 2 of Embodiment 2 will be described with reference to Fig. 42 and Fig. 43. Fig. 42 is a schematic diagram showing the vicinity of the bonding position of the substrates 200 and 300d of the solid-state imaging element according to Modification 2 of Embodiment 2 of the present disclosure.

[0163] 42, the solid-state imaging element of the second modification includes a contact Csubd, one end of which is connected to a side surface of an extension 303d and the other end of which is grounded. That is, the substrate contact layer 302d of the substrate 300d has an extension 303d to which the contact Csubd is connected on a side surface. The contact Csubd is connected to a ground line via upper layer wirings D1 to D4. The substrate 300d is grounded via the extension 303d of the substrate contact layer 302d and the contact Csubd.

[0164] The substrate 300d has an amplifier transistor 104d that amplifies an electrical signal output from the photoelectric conversion element 102 on a main surface MSa as a first main surface. The amplifier transistor 104d is configured as, for example, a MOSFET. The amplifier transistor 104d has an N-type source region 312d and an N-type drain region 311d provided on the substrate 300d. A gate electrode 313d of the amplifier transistor 104d is disposed on the substrate 300d between the source region 312d and the drain region 311d.

[0165] With this configuration, the extension 303d of the substrate contact layer 302d does not need to have an area that takes into account the cross-sectional area of ​​the contact Csubd plus the amount of misalignment during connection, and the extension 303d can be configured to be smaller than the extension 303 in the second embodiment. Accordingly, the size of the amplification transistor 104d can be slightly larger. The size of the amplification transistor 104d is smaller than the amplification transistor 104 in the first embodiment and larger than the amplification transistor 104b in the second embodiment.

[0166] The configurations of the above-described Comparative Examples 1 and 2 will be compared with the configuration of Modification 2 using Fig. 43. Fig. 43 is a diagram for comparing solid-state imaging elements according to the second embodiment of the present disclosure, its Modification 2, and Comparative Examples 1 and 2.

[0167] In the solid-state imaging element of Modification 2, the contact Csubd is connected to the side surface of the substrate contact layer 302d disposed on the main surface MSb. Therefore, compared with Comparative Examples 1 and 2, this solid-state imaging element has an advantage over the solid-state imaging element of Embodiment 2.

[0168] The size of the amplification transistor (AMP Tr size) is Comparative Example 1: Comparative Example 2: Embodiment 2: Modification 2 = 3:1:2:2.5, and Modification 2 has a larger size than that of Embodiment 2. As a result, the noise level of the RTS noise is Comparative Example 1: Comparative Example 2: Embodiment 2: Modification 2 = 0.33:1:0.5:0.4, and Modification 2 has an even better noise level than that of Embodiment 2.

[0169] (Variation 3) Next, a solid-state imaging element according to Modification 3 of Embodiment 2 will be described with reference to Fig. 44. Fig. 44 is a schematic diagram showing the vicinity of the bonding position of the substrates 200e and 300e of the solid-state imaging element according to Modification 3 of Embodiment 2 of the present disclosure.

[0170] As shown in the cross-sectional view of Figure 44(a) and the top view of (b), in the solid-state imaging element of variant example 3, the number of amplifying transistors 104e can be increased according to the number of photoelectric conversion elements 102 and the corresponding transfer transistors 103.

[0171] Specifically, the substrate 200e has a photoelectric conversion element 102-1 and a corresponding transfer transistor 103-1, a photoelectric conversion element 102-2 and a corresponding transfer transistor 103-2, and a photoelectric conversion element 102-3 and a corresponding transfer transistor 103-3.

[0172] The substrate 300e has an amplification transistor 104e-1 corresponding to the photoelectric conversion element 102-1 and the transfer transistor 103-1. The substrate 300e also has an amplification transistor 104e-2 corresponding to the photoelectric conversion element 102-2 and the transfer transistor 103-2. The substrate 300e also has an amplification transistor 104e-3 corresponding to the photoelectric conversion element 102-3 and the transfer transistor 103-3.

[0173] The regions where the amplification transistors 104e-1 to 104e-3 are provided are connected by a substrate contact layer 302e on the bottom surface of the substrate 300e. The region where the amplification transistor 104e-1 is provided and the region where the amplification transistor 104e-2 is provided are connected by an extension 303e-2 of the substrate contact layer 302e. The region where the amplification transistor 104e-2 is provided and the region where the amplification transistor 104e-3 is provided are connected by an extension 303e-3 of the substrate contact layer 302e.

[0174] A contact Csube-1 that grounds the substrate 300e is connected to the extension 303e-1 near the amplifier transistor 104e-1. A contact Csube-2 that grounds the substrate 300e is connected to the extension 303e-2 near the amplifier transistor 104e-2. A through hole 303th-2 is provided in the extension 303e-2, which passes through Cfd-1 that connects the floating diffusion of the transfer transistor 103-1 and the gate electrode of the amplifier transistor 104e-1. A contact Csube-3 that grounds the substrate 300e is connected to the extension 303e-3 near the amplifier transistor 104e-3. A through hole 303th-3 is provided in the extension 303e-3, which passes through Cfd-2 that connects the floating diffusion of the transfer transistor 103-2 and the gate electrode of the amplifier transistor 104e-2.

[0175] With this configuration, even if the numbers of photoelectric conversion elements 102 and transfer transistors 103 increase, the number of amplification transistors 104e can be increased accordingly. In the example of Fig. 44, three photoelectric conversion elements 102, three transfer transistors 103, and three amplification transistors 104e are in one-to-one correspondence, but the number of these elements is not limited to three. The number of these elements may be two, or four or more.

[0176] [Embodiment 3] Next, a solid-state imaging element 100f according to the third embodiment will be described with reference to Fig. 45 and Fig. 46. The solid-state imaging element 100f according to the third embodiment differs from the first and second embodiments in that a plurality of photoelectric conversion elements 102 are integrated into one.

[0177] Fig. 45 is a diagram showing a part of a solid-state imaging element 100f according to the third embodiment of the present disclosure, in which (a) is a diagram showing a part of the upper surface of the substrate 200, and (b) is a diagram showing a part of a cross section of the solid-state imaging element 100f.

[0178] 45(a), in the substrate 200, four transfer transistors 103 corresponding to the four photoelectric conversion elements 102 respectively are arranged near the center where the four photoelectric conversion elements 102 are gathered. In addition, the source regions 222 which are floating diffusions of the four transfer transistors 103 are surrounded by the four transfer transistors 103 and arranged close to each other.

[0179] 45(a) and (b), these four source regions 222 are collected into one by a wiring Dx above the substrate 200. Specifically, the wiring Dx has four legs Df connected to the respective source regions 222. In addition, one contact Cfd is connected to the upper portion of the wiring Dx. The other end of the contact Cfd is connected to the wiring D1.

[0180] The substrate 300f has one pixel transistor corresponding to each of the four photoelectric conversion elements 102 and the four transfer transistors 103. That is, the substrate 300f has one amplification transistor 104f, one reset transistor 105f, and one selection transistor (not shown) for the four photoelectric conversion elements 102 and the four transfer transistors 103.

[0181] The wiring D1 to which the contact Cfd is connected is connected to the gate electrode 313f of the amplifier transistor 104f. The wiring D1 also connects the gate electrode 313f of the amplifier transistor 104f and the source region 332f of the reset transistor 105f.

[0182] The configurations of the above-described embodiments 1 and 2 can be applied to the solid-state imaging device 100f as well. Fig. 46 is a comparison diagram in which the configurations of the embodiments 1 and 2 and the comparative example 2 of the present disclosure are applied to the solid-state imaging device 100f according to embodiment 3.

[0183] As shown in FIG. 46, the sizes of the amplifying transistors (AMP Tr sizes) are Comparative Example 2:Embodiment 1:Embodiment 2=1:2:1.5, and the noise levels of the RTS noise are Comparative Example 2:Embodiment 1:Embodiment 2=1:0.5:0.67.

[0184] Thus, the application example of Embodiment 1 to Embodiment 3 is superior in both the size of the amplifying transistor and the noise level of the RTS noise compared to the application example of Comparative Example 2. The application example of Embodiment 2 to Embodiment 3 is superior in both the size of the amplifying transistor and the noise level of the RTS noise compared to the application example of Comparative Example 2. The application example of Embodiment 1 to Embodiment 3 is even superior to the application example of Embodiment 2 in both the size of the amplifying transistor and the noise level of the RTS noise.

[0185] [Embodiment 4] The configurations of the above-mentioned embodiments 1 and 2 can also be applied to a semiconductor device having a transistor such as a MOSFET. Examples of application are shown in Figures 47 and 48.

[0186] FIG. 47 is a schematic diagram showing the vicinity of the bonding position of the substrates 500 and 600a when the configuration of the first embodiment of the present disclosure is applied to the semiconductor device according to the fourth embodiment.

[0187] As shown in FIG. 47, the semiconductor device of the fourth embodiment includes a substrate 500 as a first semiconductor substrate having a transistor 530 as a first transistor. The substrate 500, which is a silicon substrate or the like, is grounded. That is, the potential of the substrate 500 is fixed to 0V. The transistor 530 is configured as, for example, a MOSFET. The transistor 530 includes a gate electrode 533, an N-type source region 532, and an N-type drain region 531. The gate electrode 533 is provided with a contact 533c connected to an upper layer wiring. The source region 532 is provided with a contact 532c connected to an upper layer wiring. The drain region 531 is provided with a contact 531c connected to an upper layer wiring. The substrate 500 includes a P-type transistor 530 that is separated from the region in which the transistor 530 is disposed by an element isolation region 520. + The semiconductor device has a substrate contact layer 510 of the same type.

[0188] The semiconductor device of the fourth embodiment also includes a substrate 600a as a second semiconductor substrate facing the substrate 500 via an insulating film 580. That is, the substrate 600a and the substrate 500 are bonded together. A surface 561 shown in FIG. 47 indicates the surface where the substrate 600a and the substrate 500 are bonded together.

[0189] The substrate 600a has a transistor 630 as a second transistor on a main surface MSa as a first main surface. The transistor 630 is configured as, for example, a MOSFET. The transistor 630 includes a gate electrode 633, an N-type source region 632, and an N-type drain region 631. The gate electrode 633 is provided with a contact 633c connected to an upper layer wiring. The source region 632 is provided with a contact 632c connected to an upper layer wiring. The drain region 631 is provided with a contact 631c connected to an upper layer wiring. The transistor 630 is covered with an insulating film 681.

[0190] The substrate 600a has a substrate contact layer 611 as a region with a lower resistance than the substrate 600a on a main surface MSb as a second main surface opposite to the main surface MSa. Specifically, the substrate 600a has a certain conductivity type, for example, P type, and the substrate contact layer 611 contains impurities at a higher concentration than other regions 634 of the substrate 600a. That is, an N-type source region 632 and an N-type drain region 631 of a transistor 630 provided on the main surface MSa and a P-type drain region 632 provided on the main surface MSb are + The second region 634 of the substrate 600a is separated from the second region 611 of the substrate 600a by another region 634 of the substrate 600a. Here, it is sufficient that at least a part of the substrate contact layer 611 has a lower resistance than the other region 634 of the substrate 600a and contains a high concentration of impurities.

[0191] The substrate 600a is grounded via the substrate contact layer 611. Specifically, the semiconductor device of the fourth embodiment includes a contact 611c extending from the substrate contact layer 611 of the substrate 600a toward the substrate 500. More specifically, the substrate 600a is disposed with the main surface MSb facing the substrate 500, and the semiconductor device includes a contact 611c connecting the substrate contact layer 611 of the substrate 600a to the substrate contact layer 510 of the substrate 500. As a result, the substrate 600a is grounded via the substrate contact layer 611 and the substrate 500. That is, the potential of the substrate 600a is fixed to 0V.

[0192] FIG. 48 is a schematic diagram showing the vicinity of the bonding position of the substrates 500 and 600b when the configuration of the second embodiment of the present disclosure is applied to the semiconductor device according to the fourth embodiment.

[0193] 48, the semiconductor device of the fourth embodiment includes a substrate 600b as a second semiconductor substrate facing the substrate 500 via an insulating film 580. That is, the substrate 600b and the substrate 500 are bonded together. A surface 562 shown in FIG. 48 indicates the surface where the substrate 600b and the substrate 500 are bonded together.

[0194] The substrate 600b has a transistor 640 as a second transistor on a main surface MSa as a first main surface. The transistor 640 is configured as, for example, a MOSFET. The transistor 640 includes a gate electrode 643, an N-type source region 642, and an N-type drain region 641. The gate electrode 643 is provided with a contact 643c connected to an upper layer wiring. The source region 642 is provided with a contact 642c connected to an upper layer wiring. The drain region 641 is provided with a contact 641c connected to an upper layer wiring. The transistor 640 is covered with an insulating film 682.

[0195] The substrate 600b has a substrate contact layer 612 as a region with a lower resistance than the substrate 600b on a main surface MSb as a second main surface opposite to the main surface MSa. Specifically, the substrate 600b has a certain conductivity type, for example, P type, and the substrate contact layer 612 contains impurities at a higher concentration than other regions 644 of the substrate 600b. That is, an N-type source region 642 and an N-type drain region 641 of a transistor 640 provided on the main surface MSa and a P-type drain region 642 of a transistor 640 provided on the main surface MSb are + The second region 644 of the substrate 600b is separated from the second region 612 of the substrate 600b. At least a portion of the substrate contact layer 612 has a lower resistance than the second region 644 of the substrate 600b and contains a high concentration of impurities.

[0196] The substrate contact layer 612 of the substrate 600b has an extension 613 that extends to the outside of the substrate 600b in a direction along the substrate 600b.

[0197] The substrate 600b is grounded via the substrate contact layer 612. Specifically, the semiconductor device of the fourth embodiment includes a contact 612c extending from the substrate contact layer 612 of the substrate 600b to the side opposite to the substrate 500. More specifically, the extension 613 has a main surface MSc as a third main surface facing the same side as the main surface MSa of the substrate 600b, and includes a contact 612c having one end connected to the main surface MSc of the extension 613 and the other end grounded. As a result, the substrate 600b is grounded via the substrate contact layer 612, the contact 612c, the upper layer wiring, and the like. That is, the potential of the substrate 600b is fixed to 0V.

[0198] In the semiconductor device of the fourth embodiment, the transistor 530 of the substrate 500 and the transistors 630, 640 of the substrates 600a, 600b can be used for different purposes. The transistor 530 is suitable for applications requiring high-speed processing. The transistors 630, 640 are slower in operation than the transistor 530 of the substrate 500, but are suitable for applications requiring low noise. Thus, for example, the transistor 530 can be used as a transistor constituting a logic circuit or the like. Also, the transistors 630, 640 can be used as transistors constituting an analog circuit or the like.

[0199] (Variation 1) Next, a semiconductor device according to Modification 1 of the fourth embodiment will be described with reference to Fig. 49. Fig. 49 is a schematic diagram showing the vicinity of the bonding position of the substrates 500c, 600c of the semiconductor device according to Modification 1 of the fourth embodiment of the present disclosure. The semiconductor device according to Modification 1 differs from the fourth embodiment in that N-type transistors 530, 640 and P-type transistors 540, 650 are mixed.

[0200] As shown in the cross-sectional view of FIG. 49(a), the semiconductor device of the first modification includes a substrate 500c as a first semiconductor substrate having a transistor 530. The substrate 500c includes a transistor 540 as a fourth transistor having a different conductivity type from the transistor 530, for example, a P-type, which is separated from the transistor 530 by an element isolation region 520. The transistor 540 is configured as, for example, a MOSFET. The transistor 540 includes a gate electrode 543, a P-type source region 542, and a P-type drain region 541. The gate electrode 543 is provided with a contact 543c connected to an upper layer wiring. The source region 542 is provided with a contact 542c connected to an upper layer wiring. The drain region 541 is provided with a contact 541c connected to an upper layer wiring.

[0201] The semiconductor device of the first modification includes a substrate 600c as a second semiconductor substrate facing the substrate 500c via an insulating film 583. That is, the substrates 600c and 500c are bonded together. A surface 563 shown in FIG. 49 indicates the surface where the substrates 600c and 500c are bonded together.

[0202] As shown in the cross-sectional view of FIG. 49(a) and the top view of FIG. 49(b), the substrate 600c has a transistor 640 on the main surface MSa. The substrate 600c also has a transistor 650 as a fifth transistor of a different conductivity type, for example, P type, from the transistor 640, separated by element isolation regions 602 and 603. The transistor 650 is configured as, for example, a MOSFET. The transistor 650 includes a gate electrode 653, a P-type source region 652, and a P-type drain region 651. The gate electrode 653 is provided with a contact 653c connected to an upper layer wiring. The source region 652 is provided with a contact 652c connected to an upper layer wiring. The drain region 651 is provided with a contact 651c connected to an upper layer wiring. The element isolation region 602 also functions as a through hole that passes the contacts 531c to 533c from the lower substrate 500c to the upper layer wiring side. The element isolation region 603 also functions as a through hole that passes through the contacts 541c-543c from the lower substrate 500c to the upper wiring side. The substrate 600c including the transistors 640 and 650 is entirely covered with an insulating film 683.

[0203] The substrate 600c has a substrate contact layer 612 at a position on the main surface MSb corresponding to the transistor 640, the substrate contact layer 612 having a lower resistance than a region 644 of the substrate 600c near the transistor 640. That is, the region 644 of the substrate 600c is, for example, a P-type, and the substrate contact layer 612 is, for example, a P-type. + The substrate contact layer 612 has an extension 613 that extends to the outside of the substrate 600c in a direction along the substrate 600c.

[0204] The substrate 600c has a substrate contact layer 622 at a position on the main surface MSb corresponding to the transistor 650, the substrate contact layer 622 having a lower resistance than a region 654 of the substrate 600c near the transistor 650. That is, the region 654 of the substrate 600c is, for example, an N-type, and the substrate contact layer 622 is, for example, an N-type. + Here, it is sufficient that at least a portion of the substrate contact layer 622 has a lower resistance than the region 654 of the substrate 600c and contains a high concentration of impurities.

[0205] The substrate contact layer 622 has an extension 623 extending outward from the substrate 600c in a direction along the substrate 600c. The extension 623 has a main surface MSc as a third main surface facing the same side as the main surface MSa of the substrate 600c, and includes a contact 622c having one end connected to the main surface MSc of the extension 623 and the other end grounded.

[0206] The substrate 600c is grounded through substrate contact layers 612 and 622.

[0207] (Variation 2) Next, a semiconductor device according to Modification 2 of the fourth embodiment will be described with reference to Fig. 50. Fig. 50 is a schematic diagram showing the vicinity of the bonding position of the substrates 500c, 700c, and 600c of the semiconductor device according to Modification 2 of the fourth embodiment of the present disclosure. The semiconductor device according to Modification 2 differs from the above-mentioned Modification 1 in that a substrate 700c is interposed between the substrates 500c and 600c.

[0208] As shown in Fig. 50, the semiconductor device of the second modification further includes a substrate 700c as a third semiconductor substrate which is a floating substrate facing the substrate 500c in addition to the configuration of the first modification. That is, the substrate 700c which is a silicon substrate or the like is bonded to the substrate 500c. A surface 570 shown in Fig. 50 indicates the surface where the substrates 500c and 700c are bonded. Furthermore, the substrate 600c is bonded to the substrate 700c. A surface 760 shown in Fig. 50 indicates the surface where the substrates 700c and 600c are bonded.

[0209] The substrate 500c is grounded and has a fixed potential of 0 V. The substrate 600c has substrate contact layers 612 and 622, and is grounded via contacts 612c and 622c connected thereto, and has a fixed potential of 0 V. The substrate 700c does not have a substrate contact layer or the like and is not grounded. In other words, the substrate 700c is a floating substrate with an indefinite substrate potential.

[0210] The substrate 700c has transistors 730 and 740 as third transistors. The transistors 730 and 740 are configured as, for example, MOSFETs. The transistor 730 has a gate electrode 733, an N-type source region 732, an N-type drain region 731, and a P-type region 734 sandwiched between these regions. The transistor 730 has a fully depleted silicon-on-insulator (FD-SOI) structure in which an insulating film 583 is disposed directly under a body of an NPN structure. The transistor 740 has a gate electrode 743, a P-type source region 742, a P-type drain region 741, and an N-type region 744 sandwiched between these regions. The transistor 740 has an FD-SOI structure in which an insulating film 583 is disposed directly under a body of a PNP structure.

[0211] By configuring the transistors 730, 740 of the substrate 700c in this way, the transistors 730, 740 can be miniaturized, and the parasitic capacitance can be suppressed to obtain high-speed transistors 730, 740.

[0212] In order to achieve a noise reduction effect, a substrate contact layer may be provided on the substrate 700c, similar to the substrate 600c, to fix the potential of the substrate 700c.

[0213] In addition, in the above-mentioned modified examples 1 and 2, an example in which the configuration of embodiment 2 as shown in FIG. 48 is applied has been described. However, in modified examples 1 and 2, the configuration of embodiment 1 shown in FIG. 47 may also be applied.

[0214] [Embodiment 5] In a solid-state imaging device having a plurality of types of pixel transistors, how to suppress variations in the threshold voltage of each pixel transistor is also an issue.

[0215] In the fifth embodiment, a solid-state imaging device capable of adjusting the threshold voltage of a pixel transistor is proposed.

[0216] (Example of detailed configuration of solid-state imaging element) Fig. 51 is a longitudinal sectional view showing the vicinity of the bonding position of the substrates 200, 300g of the solid-state imaging element 100g according to the fifth embodiment of the present disclosure. Fig. 52 is a transverse sectional view including the vicinity of the bonding position of the substrates 200, 300g of the solid-state imaging element 100g according to the fifth embodiment of the present disclosure. Fig. 52(a) is a transverse sectional view of the substrate 300g from which the insulating film 340 is omitted. Fig. 52(b) is a transverse sectional view of the insulating film 240. Fig. 52(c) is a transverse sectional view of the substrate 200 from which the insulating film 240 is omitted.

[0217] As shown in FIG. 51, a solid-state imaging element 100g of the fifth embodiment has a configuration in which a substrate 200 and a substrate 300g are bonded together.

[0218] The substrate 200 as the first substrate has, for example, the same configuration as the substrate 200 shown in the above-mentioned embodiment 1. In FIG. 51, a cross section of a range different from that shown in the above-mentioned embodiment 1 is shown. That is, the substrate 200 has a plurality of transfer transistors 103 in a surface layer portion of a P-type semiconductor region 204, sandwiching a pixel separation portion 203. A P-type diffusion region 230 is provided in a region of the surface layer portion of the P-type semiconductor region 204, which is away from the formation region of the transfer transistors 103. The diffusion region 230 is connected to, for example, a contact C2vs, and the contact C2vs is connected to a wiring D1vss. The semiconductor region 204 of the substrate 200 is grounded via the contact C2vs, the wiring D1vss, and the like.

[0219] 51 and 52(c), the transfer transistor 103 includes a gate electrode 223 and an N-type source region 222 as a floating diffusion. The gate electrode 223 is connected to a contact Ctg. The source region 222 is connected to a contact Cfd.

[0220] 51, a substrate 300g serving as a second substrate has a P-type semiconductor region 301 having a main surface MSa serving as a first main surface and a main surface MSb serving as a second main surface. The distance between the main surfaces MSa and MSb, that is, the thickness of the semiconductor region 301, is, for example, 100 nm or less. The main surface MSb of the substrate 300g is bonded to the substrate 200 via an insulating film 240 that covers the entire transfer transistor 103 and the like of the substrate 200. The thickness of the insulating film 240 is, for example, about 350 nm.

[0221] The substrate 300g has a pixel transistor on the main surface MSa side. The pixel transistor processes an electrical signal output from a photoelectric conversion element including an N-type semiconductor region 201 of the substrate 200. Fig. 51 shows a cross section including a selection transistor 106 and a reset transistor 105 as an example of a pixel transistor.

[0222] A P-type diffusion region 330 is provided in a surface portion of the P-type semiconductor region 301, in an area away from the areas where the select transistor 106, the reset transistor 105, etc. are formed. The diffusion region 330 is connected to, for example, a contact C3vs, and the contact C3vs is connected to a wiring D1vss. The semiconductor region 301 of the substrate 300 is grounded via the contact C3vs and the wiring D1vss, etc.

[0223] In the substrate 300g, the selection transistor 106, the reset transistor 105, etc. are entirely covered with an insulating film 340. The thickness of the insulating film 340 is, for example, about 350 nm.

[0224] 51 and 52(a), the selection transistor 106 has a gate electrode 323, an N-type source region 322, and an N-type drain region 321. The gate electrode 323 is connected to a contact Csg. The source region 322 is connected to a contact Css, and the contact Css is connected to a source line (not shown) via a wiring D1vsl. The drain region 321 is connected to a contact Csd.

[0225] The reset transistor 105 has a gate electrode 333, an N-type source region 332, and an N-type drain region 331. The gate electrode 333 is connected to a contact Crg. The source region 332 is connected to a contact Crs, and the contact Crs is connected to the source region 222 of the transfer transistor 103 via a wiring D1 and a contact Cfd. The drain region 331 is connected to a contact Crd, and the contact Crd is connected to a power supply (not shown) via a wiring D1vdd.

[0226] 52(a), the amplification transistor 104 has a gate electrode 313, an N-type source region 312, and an N-type drain region 311. The gate electrode 313 is connected to a contact Cag, which is connected to the source region 222 of the transfer transistor 103 via a wiring D1 and a contact Cfd. The source region 312 is connected to a contact Cas. The contact Cas is connected to a contact Csd which is connected to the drain region 321 of the selection transistor 106. The drain region 311 of the amplification transistor 104 is connected to a contact Cad.

[0227] As shown in FIGS. 51 and 52(a), the selection transistor 106, the reset transistor 105, and the amplification transistor 104 are isolated from each other by element isolation regions STI formed around each of them.

[0228] As shown in Figures 51 and 52(b), near the main surface MSb side of the semiconductor region 301 of the substrate 300g, backgate electrodes 251s, 251r, and 251a, each made of polysilicon or the like, are arranged at positions corresponding to the selection transistor 106, the reset transistor 105, and the amplification transistor 104.

[0229] That is, a backgate electrode 251s serving as a second electrode is disposed on the back surface of the selection transistor 106. In this case, the backgate electrode 251s is provided at a position overlapping at least the gate electrode 323, the source region 322, and the drain region 321 of the selection transistor 106 in a top view, and preferably so as to completely cover these gate electrode 323, the source region 322, and the drain region 321.

[0230] In addition, a backgate electrode 251r serving as a third electrode is disposed on the back surface of the reset transistor 105. In this case, the backgate electrode 251r is provided at a position overlapping at least the gate electrode 333, the source region 332, and the drain region 331 of the reset transistor 105 in a top view, and preferably so as to completely cover these gate electrode 333, the source region 332, and the drain region 331.

[0231] Further, a backgate electrode 251a serving as a first electrode is disposed on the back surface of the amplification transistor 104. In this case, the backgate electrode 251a is provided at a position overlapping at least the gate electrode 313, the source region 312, and the drain region 311 of the amplification transistor 104 in a top view, and preferably so as to completely cover these gate electrode 313, the source region 312, and the drain region 311.

[0232] The distance between the backgate electrodes 251s, 251r, and 251a and the main surface MSb of the semiconductor region 301 of the substrate 300g is, for example, 10 nm or less. Between the backgate electrodes 251s, 251r, and 251a and the main surface MSb of the semiconductor region 301, for example, an insulating film 240 is interposed with a thickness of 10 nm or less.

[0233] As shown in Fig. 52(b), the back gate electrodes 251s, 251r, and 251a are connected to contacts Cbgs, Cbgr, and Cbga, respectively. As shown in Fig. 52(a), these contacts Cbgs, Cbgr, and Cbga are connected to the back bias line BBL, respectively.

[0234] The back bias line BBL is configured to be able to apply a voltage to the back gate electrodes 251s, 251r, and 251a via the contacts Cbgs, Cbgr, and Cbga. This allows a back bias to be applied from the back gate electrodes 251s, 251r, and 251a to the selection transistor 106, the reset transistor 105, and the amplification transistor 104. The back bias is a bias generated by the difference between the gate voltages of the back gate electrodes 251s, 251r, and 251a and the threshold voltages of the selection transistor 106, the reset transistor 105, and the amplification transistor 104.

[0235] (Example of operation of solid-state imaging device) Next, an operation example of the solid-state imaging device 100g according to the fifth embodiment will be described with reference to Fig. 53. Fig. 53 is a perspective view showing a part of the solid-state imaging device 100g according to the fifth embodiment of the present disclosure. In Fig. 53, the insulating films 240, 340, etc. are omitted.

[0236] An electric signal from the photoelectric conversion element is transferred to the amplifying transistor 104 provided in the solid-state imaging device 100g by the transfer transistor 103. A voltage according to the magnitude of the electric signal from the photoelectric conversion element is applied to the gate electrode 313 of the amplifying transistor 104. At this time, a predetermined voltage is also applied to the back gate electrode 251a arranged on the back surface of the amplifying transistor 104 via the contact Cbga, and the threshold voltage of the amplifying transistor 104 is adjusted. This makes it possible to turn on the amplifying transistor 104 at a desired voltage value, and the electric signal from the photoelectric conversion element is amplified.

[0237] In the selection transistor 106 included in the solid-state imaging device 100g, a voltage is applied to the gate electrode 323 via the contact Csg. At this time, a predetermined voltage is also applied to the back gate electrode 251s arranged on the back surface of the selection transistor 106 via the contact Cbgs, and the threshold voltage of the selection transistor 106 is adjusted. This allows the selection transistor 106 to be turned on at a desired voltage value, and the electrical signal from the photoelectric conversion element amplified by the amplification transistor 104 is transferred via the wiring D1vsl.

[0238] Furthermore, in the selection transistor 106, the backgate electrode 251s can reduce the channel resistance, i.e., the on-resistance, of the selection transistor 106, and can advance the timing at which the selection transistor 106 turns on. Since it takes time for the source line potential VSL to rise due to the resistance of the contact Css, the wiring D1vsl, etc., by advancing the on-timing of the selection transistor 106, the time required to wait for the source line potential VSL to rise can be shortened.

[0239] In the reset transistor 105 included in the solid-state imaging device 100g, a voltage is applied to the gate electrode 333 via the contact Crg. At this time, a predetermined voltage is also applied to the back gate electrode 251r arranged on the back surface of the reset transistor 105 via the contact Cbgr, and the threshold voltage of the reset transistor 105 is adjusted. This allows the reset transistor 105 to be turned on at a desired voltage value, and the potentials of the gate electrode 313 of the amplification transistor 104 and the source region 222 of the transfer transistor 103, which is a floating diffusion, are reset to the power supply potential VDD.

[0240] 52 and 53, the back gate electrodes 251s and 251r corresponding to the selection transistor 106 and the reset transistor 105 are connected to a common back bias line BBL, but may be connected to separate back bias lines. This allows the threshold voltages of the selection transistor 106, the reset transistor 105, and the amplification transistor 104 to be individually controlled by applying different voltages to the back gate electrodes 251s, 251r, and 251a, for example.

[0241] (Example of manufacturing process for solid-state imaging device) Next, an example of a manufacturing process of the solid-state imaging device 100g according to the fifth embodiment will be described with reference to Fig. 54 to Fig. 57. Fig. 54 to Fig. 57 are a flow chart showing an example of a procedure of the manufacturing process of the solid-state imaging device 100g according to the fifth embodiment of the present disclosure.

[0242] 54(a), a photoelectric conversion element including an N-type semiconductor region 201, a P-type semiconductor region 204, a gate electrode 223 of a transfer transistor 103, and a source region 222 as a floating diffusion are formed on a substrate 200. A P-type diffusion region 230 is formed at a position away from the transfer transistor 103. The semiconductor region 204 including the gate electrode 223 and the source region 222 is covered with an insulating film 240. A polysilicon film 250 is formed on the insulating film 240 by, for example, a CVD method.

[0243] As shown in FIG. 54(b), an N-type polysilicon film 251 is formed by doping (ion implantation) an N-type impurity into the polysilicon film 250.

[0244] 54(c), a part of the polysilicon film 51 is etched to form a backgate electrode 251s at a position that will later correspond to the selection transistor 106, and a backgate electrode 251r at a position that will later correspond to the reset transistor 105. At this time, a backgate electrode 251a (not shown) is also formed at a position that will later correspond to the amplification transistor 104.

[0245] As shown in FIG. 54(d), an insulating film 240 is further formed so as to cover the back gate electrodes 251s and 251r with a thickness of, for example, 10 nm or less.

[0246] As shown in FIG. 55( a ), a thick substrate 300 g , that is, a substrate before being thinned, is attached to an insulating film 240 with the main surface MSb facing the insulating film 240 .

[0247] As shown in FIG. 55(b), the substrate 300g is ground with a grinder G or the like to form the semiconductor region 301 so that the thickness thereof is, for example, 100 nm or less.

[0248] As shown in FIG. 56(a), the semiconductor region 301 is removed from the portion where the contacts Cfd, C2vs, etc. connected to the substrate 200 are to be disposed.

[0249] As shown in FIG. 56(b), the select transistor 106 and the reset transistor 105 are formed on the main surface MSa of the semiconductor region 301. Specifically, a gate oxide film (not shown) is formed on the main surface MSa of the semiconductor region 301 by thermal oxidation. A polysilicon film or the like is formed by CVD, and a portion of it is etched to form the gate electrodes 323, 333 of the select transistor 106 and the reset transistor 105. N-type impurities are ion-implanted into the semiconductor region 301 on both sides of the gate electrodes 323, 333 to form the source regions 322, 332 and the drain regions 321, 331. The amplifier transistor 104 (not shown) is also formed in parallel in the same manner.

[0250] Thereafter, an element isolation region STI is formed around the selection transistor 106, the reset transistor 105, and the like by a technique such as shallow trench isolation.

[0251] As shown in FIG. 57(a), an insulating film 340 is formed so as to cover the selection transistor 106, the reset transistor 105, and the like.

[0252] As shown in Fig. 57(b), contacts Csg, Crg, Css, Crs, Csd, Crd, C3vs, C2vs, and Cfd are formed. Specifically, through holes reaching the gate electrodes 323, 333, the source regions 322, 332, the drain regions 321, 33, and the substrate 200 are formed by dry etching, and W film or the like is filled into each through hole by the CVD method, and excess W film is removed by CMP. A contact connected to the amplification transistor 104 (not shown) is also formed in parallel in the same manner.

[0253] Thereafter, wirings D1, D1dd, D1vsl, D1vss, etc. to which the contacts Csg, Crg, Css, Crs, Csd, Crd, C3vs, C2vs, and Cfd are connected are formed.

[0254] Thereafter, upper layer wiring (not shown) is further formed, and the substrate on which the logic transistors and wiring are formed is bonded, completing the manufacturing process of the solid-state imaging device 100g.

[0255] (Comparative Example) The solid-state imaging device includes a plurality of pixel transistors, such as a selection transistor, a reset transistor, and an amplification transistor. These pixel transistors are manufactured in the form of a whole wafer and then separated into individual pieces. In the solid-state imaging device of the comparative example, the threshold voltage of each pixel transistor may vary due to variations in processing conditions within the wafer. In other words, the threshold voltage of the pixel transistor may vary between chips or within the chip of the solid-state imaging device.

[0256] In the solid-state imaging element 100g of the fifth embodiment, back gate electrodes 251s, 251r, and 251a for applying a back bias are provided on the back surfaces of the selection transistor 106, the reset transistor 105, and the amplification transistor 104. This makes it possible to adjust the threshold voltages of the selection transistor 106, the reset transistor 105, and the amplification transistor 104 and suppress variations in the threshold voltages. This reduces noise.

[0257] In addition, by dividing the back bias line BBL for applying a voltage to each of the back gate electrodes 251s, 251r, and 251a, different voltages can be applied to the back gate electrodes 251s, 251r, and 251a, respectively. This further improves the controllability of the threshold voltages of the selection transistor 106, the reset transistor 105, and the amplification transistor 104.

[0258] In the solid-state imaging element 100g of the fifth embodiment, a back bias is applied by the back gate electrodes 251s, 251r, and 251a when a voltage is applied to the gate electrodes 323, 333, and 313 of the selection transistor 106, the reset transistor 105, and the amplification transistor 104. This allows the operation margins of the selection transistor 106, the reset transistor 105, and the amplification transistor 104 to be widened, improving reliability.

[0259] In the solid-state imaging element 100g of the fifth embodiment, the back gate electrode 251s reduces the on-resistance of the selection transistor 106, and advances the timing at which the selection transistor 106 turns on. This makes it possible to shorten the rise wait time of the source line potential VSL.

[0260] In the solid-state imaging device 100g of the fifth embodiment, the distance between the back gate electrodes 251s, 251r, 251a and the main surface MSb of the substrate 300g is, for example, 10 nm or less. Also, the thickness of the semiconductor region 301 of the substrate 300g is, for example, 100 nm or less. In this way, the distance between the back gate electrodes 251s, 251r, 251a and the selection transistor 106, the reset transistor 105, and the amplification transistor 104 is sufficiently close, so that a back bias effect sufficient for adjusting the threshold voltage can be obtained.

[0261] (Variation 1) Next, a solid-state imaging element according to Modification 1 of the fifth embodiment will be described with reference to Figures 58 and 59. The solid-state imaging element according to Modification 1 differs from the above-described fifth embodiment in that it is manufactured using an SOI substrate 300h.

[0262] 58 and 59 are a flowchart showing an example of a manufacturing process procedure of a solid-state imaging device according to the first modification of the fifth embodiment of the present disclosure.

[0263] As shown in Fig. 58(a), an SOI (Silicon On Insulator) substrate 300h is prepared as a second substrate. The SOI substrate 300h includes a support substrate 301hdl, which is, for example, a P-type silicon substrate, a BOX layer 301box, which is, for example, a silicon oxide layer on the support substrate 301hdl, and an active layer 301act, which is, for example, a P-type silicon layer on the BOX layer 301box. The thicknesses of the BOX layer 301box and the active layer 301act are, for example, about several tens of µm each.

[0264] As shown in FIG. 58(b), the SOI substrate 300h is ground from the side of the support substrate 301hdl by a grinder G or the like, so that the BOX layer 301box remains at a thickness of 10 nm or less.

[0265] As shown in FIG. 59(a), an active layer 301act having a BOX layer 301box of 10 nm or less is bonded to an insulating film 240 of a substrate 200 with the BOX layer 301box side facing the insulating film 240 side.

[0266] As shown in FIG. 59(b), the surface of the active layer 301act is ground by a grinder G or the like until the thickness becomes 100 nm or less.

[0267] Thereafter, the same processes as those shown in FIGS. 56 and 57 of the above-mentioned fifth embodiment are carried out to manufacture the solid-state imaging device of the first modified example.

[0268] The solid-state imaging element of the first modification uses an SOI substrate 300h, which allows precise control of the distance between the back-gate electrodes 251s, 251r, and 251a and the active layer 301act that is the semiconductor region in which various pixel transistors are formed.

[0269] (Variation 2) Next, a solid-state imaging element according to Modification 2 of the fifth embodiment will be described with reference to Fig. 60. In the solid-state imaging element according to Modification 2, back gate electrodes 252s, 252r, etc. are formed using a material different from that of the fifth embodiment described above.

[0270] FIG. 60 is a flowchart showing an example of a manufacturing process procedure of a solid-state imaging device according to Modification 2 of Embodiment 5 of the present disclosure.

[0271] As shown in FIG. 60(a), a trench 252tr is formed in the surface layer of the insulating film 240 covering the semiconductor region 204 by etching or the like.

[0272] 60(b), a metal film 252 such as a Cu film is formed by, for example, a CVD method on the insulating film 240. At this time, the inside of the groove 252tr is also filled with the metal film 252.

[0273] 60(c), the metal film 252 on the insulating film 240 is removed by, for example, a CMP method. At this time, by leaving the metal film 252 in the groove 252tr, a backgate electrode 252s is formed at a position that will later correspond to the selection transistor, and a backgate electrode 252r is formed at a position that will later correspond to the reset transistor. At this time, a backgate electrode (not shown) is also formed at a position that will later correspond to the amplification transistor.

[0274] Thereafter, the same processes as those in the above-mentioned fifth embodiment or the first modification of the fifth embodiment are carried out to manufacture the solid-state imaging device of the second modification.

[0275] In the solid-state imaging element of the second modification, the back gate electrodes 252s, 252r, etc. are formed using the metal film 252. This makes it possible to obtain the back gate electrodes 252s, 252r, etc. with lower resistance.

[0276] [Embodiment 6] 61 is a diagram showing an example of a schematic configuration of an imaging system 2 equipped with any of the solid-state imaging elements according to the first to third and fifth embodiments and their modified examples. That is, any of the solid-state imaging elements according to the first to third embodiments and their modified examples can be mounted on the imaging system 2. In the following description, the imaging system 2 equipped with the solid-state imaging element 100 according to the first embodiment will be taken as an example.

[0277] The imaging system 2 is, for example, an electronic device such as an imaging device such as a digital still camera or a video camera, or a mobile terminal device such as a smartphone or a tablet terminal. The imaging system 2 includes, for example, the solid-state imaging element 100 of the first embodiment, a DSP circuit 141, a frame memory 142, a display unit 143, a storage unit 144, an operation unit 145, and a power supply unit 146. In the imaging system 2, the solid-state imaging element 100, the DSP circuit 141, the frame memory 142, the display unit 143, the storage unit 144, the operation unit 145, and the power supply unit 146 are connected to each other via a bus line 147.

[0278] The solid-state imaging element 100 outputs image data corresponding to incident light. The DSP circuit 141 is a signal processing circuit that processes image data, which is a signal output from the solid-state imaging element 100. The frame memory 142 temporarily holds the image data processed by the DSP circuit 141 on a frame-by-frame basis. The display unit 143 is a panel-type display device such as a liquid crystal panel or an organic EL (Electro Luminescence) panel, and displays a moving image or a still image captured by the solid-state imaging element 100. The storage unit 144 records image data of the moving image or the still image captured by the solid-state imaging element 100 in a recording medium such as a semiconductor memory or a hard disk. The operation unit 145 issues operation commands for various functions of the imaging system 2 according to the user's operation. The power supply unit 146 appropriately supplies various power sources that serve as operating power sources for the solid-state imaging element 100, the DSP circuit 141, the frame memory 142, the display unit 143, the storage unit 144, and the operation unit 145 to these supply targets.

[0279] Next, the imaging procedure in the imaging system 2 will be described.

[0280] 62 shows an example of a flowchart of the imaging operation in the imaging system 2. The imaging system 2 accepts the start of imaging by a user's operation of the operation unit 145 or the like (step S101). Then, the operation unit 145 transmits an imaging command to the solid-state imaging element 100 (step S102). When the system control circuit (see the system control circuit 36 ​​in FIG. 1, etc.) of the solid-state imaging element 100 receives the imaging command, it executes imaging in a predetermined imaging method (step S103).

[0281] The solid-state imaging device 100 outputs image data obtained by imaging to the DSP circuit 141. Here, the image data refers to data for all pixels of pixel signals generated based on charges temporarily stored in the floating diffusion FD. The DSP circuit 141 performs predetermined signal processing, such as noise reduction processing, based on the image data input from the solid-state imaging device 100 (step S104). The DSP circuit 141 stores the image data that has been subjected to the predetermined signal processing in the frame memory 142, and the frame memory 142 stores the image data in the storage unit 144 (step S105). In this manner, imaging is performed in the imaging system 2.

[0282] Since the imaging system 2 is equipped with a solid-state imaging element 100 that is compact or has high definition, it is possible to provide a compact or high definition imaging system 2.

[0283] (Application example 1) The technology according to the present disclosure can be applied to various products. For example, the technology according to the present disclosure may be realized as a device mounted on any type of moving object, such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, a personal mobility device, an airplane, a drone, a ship, or a robot.

[0284] FIG. 63 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a moving object control system to which the technology according to the present disclosure can be applied.

[0285] The vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001. In the example shown in Fig. 63, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside-vehicle information detection unit 12030, an inside-vehicle information detection unit 12040, and an integrated control unit 12050. Also, as functional configurations of the integrated control unit 12050, a microcomputer 12051, an audio / video output unit 12052, and an in-vehicle network I / F (interface) 12053 are illustrated.

[0286] The drivetrain control unit 12010 controls the operation of devices related to the drivetrain of the vehicle according to various programs. For example, the drivetrain control unit 12010 functions as a control device for a drive force generating device for generating a drive force of the vehicle, such as an internal combustion engine or a drive motor, a drive force transmission mechanism for transmitting the drive force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, and a braking device for generating a braking force of the vehicle.

[0287] The body system control unit 12020 controls the operation of various devices mounted on the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window device, or various lamps such as head lamps, back lamps, brake lamps, turn signals, and fog lamps. In this case, radio waves or signals of various switches transmitted from a portable device that replaces a key may be input to the body system control unit 12020. The body system control unit 12020 receives the input of these radio waves or signals and controls the door lock device, power window device, lamps, and the like of the vehicle.

[0288] The outside-vehicle information detection unit 12030 detects information outside the vehicle equipped with the vehicle control system 12000. For example, an imaging unit 12031 is connected to the outside-vehicle information detection unit 12030. The outside-vehicle information detection unit 12030 causes the imaging unit 12031 to capture an image outside the vehicle and receives the captured image. The outside-vehicle information detection unit 12030 may perform object detection processing such as detection of people, cars, obstacles, signs, or characters on the road surface, or distance detection processing based on the received image.

[0289] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal according to the amount of light received. The imaging unit 12031 can output the electrical signal as an image, or as distance measurement information. The light received by the imaging unit 12031 may be visible light or invisible light such as infrared light.

[0290] The in-vehicle information detection unit 12040 detects information inside the vehicle. For example, a driver state detection unit 12041 that detects the state of the driver is connected to the in-vehicle information detection unit 12040. The driver state detection unit 12041 includes, for example, a camera that captures an image of the driver, and the in-vehicle information detection unit 12040 may calculate the degree of fatigue or concentration of the driver based on the detection information input from the driver state detection unit 12041, or may determine whether the driver is dozing.

[0291] The microcomputer 12051 can calculate control target values ​​for the driving force generating device, steering mechanism, or braking device based on the information inside and outside the vehicle acquired by the outside-of-vehicle information detection unit 12030 or the inside-vehicle information detection unit 12040, and output a control command to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing the functions of an ADAS (Advanced Driver Assistance System), including vehicle collision avoidance or impact mitigation, following driving based on the inter-vehicle distance, vehicle speed maintenance driving, vehicle collision warning, vehicle lane departure warning, etc.

[0292] In addition, the microcomputer 12051 can perform cooperative control for the purpose of autonomous driving, which allows the vehicle to travel autonomously without relying on the driver's operation, by controlling the driving force generating device, steering mechanism, braking device, etc., based on information about the surroundings of the vehicle acquired by the outside vehicle information detection unit 12030 or the inside vehicle information detection unit 12040.

[0293] Furthermore, the microcomputer 12051 can output a control command to the body system control unit 12020 based on the information outside the vehicle acquired by the outside-vehicle information detection unit 12030. For example, the microcomputer 12051 can control the headlamps according to the position of a preceding vehicle or an oncoming vehicle detected by the outside-vehicle information detection unit 12030, and perform cooperative control for the purpose of preventing glare, such as switching from high beams to low beams.

[0294] The audio / video output unit 12052 transmits at least one output signal of audio and video to an output device capable of visually or audibly notifying information to passengers in the vehicle or the outside of the vehicle. In the example of Fig. 63, an audio speaker 12061, a display unit 12062, and an instrument panel 12063 are exemplified as the output device. The display unit 12062 may include at least one of an on-board display and a head-up display, for example.

[0295] FIG. 64 is a diagram showing an example of the installation position of the imaging unit 12031.

[0296] In FIG. 64, a vehicle 12100 has imaging units 12101, 12102, 12103, 12104, and 12105 as an imaging unit 12031.

[0297] The imaging units 12101 to 12105 are provided at positions such as the front nose, side mirrors, rear bumper, back door, and the upper part of the windshield in the vehicle interior of the vehicle 12100. The imaging unit 12101 provided at the front nose and the imaging unit 12105 provided at the upper part of the windshield in the vehicle interior mainly acquire images of the front of the vehicle 12100. The imaging units 12102 and 12103 provided at the side mirrors mainly acquire images of the sides of the vehicle 12100. The imaging unit 12104 provided at the rear bumper or back door mainly acquires images of the rear of the vehicle 12100. The images of the front acquired by the imaging units 12101 and 12105 are mainly used to detect a preceding vehicle, a pedestrian, an obstacle, a traffic light, a traffic sign, a lane, or the like.

[0298] 64 shows an example of the imaging ranges of the imaging units 12101 to 12104. Imaging range 12111 indicates the imaging range of the imaging unit 12101 provided on the front nose, imaging ranges 12112 and 12113 indicate the imaging ranges of the imaging units 12102 and 12103 provided on the side mirrors, respectively, and imaging range 12114 indicates the imaging range of the imaging unit 12104 provided on the rear bumper or back door. For example, an overhead image of the vehicle 12100 viewed from above is obtained by superimposing the image data captured by the imaging units 12101 to 12104.

[0299] At least one of the imaging units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera made up of a plurality of solid-state imaging elements, or may be a solid-state imaging element having pixels for detecting a phase difference.

[0300] For example, the microcomputer 12051 can extract, as a preceding vehicle, a three-dimensional object that is the closest to the vehicle 12100 on the travel path of the vehicle 12100 and travels in the same direction as the vehicle 12100 at a predetermined speed, for example, 0 km / h or more, by calculating the distance to each three-dimensional object in the image capture ranges 12111-12114 and the change in the distance over time, that is, the relative speed with respect to the vehicle 12100, based on the distance information obtained from the image capture units 12101-12104. Furthermore, the microcomputer 12051 can set a vehicle distance to be secured in advance in front of the preceding vehicle, and perform automatic braking control including a following stop control, automatic acceleration control including a following start control, and the like. In this way, cooperative control can be performed for the purpose of automatic driving that travels autonomously without relying on the driver's operation.

[0301] For example, the microcomputer 12051 classifies and extracts three-dimensional object data on three-dimensional objects, such as two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects, based on the distance information obtained from the imaging units 12101 to 12104, and can use the data for automatic obstacle avoidance. For example, the microcomputer 12051 distinguishes obstacles around the vehicle 12100 into obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see. Then, the microcomputer 12051 determines a collision risk indicating the degree of danger of collision with each obstacle, and when the collision risk is equal to or greater than a set value and there is a possibility of collision, the microcomputer 12051 can provide driving assistance for collision avoidance by outputting an alarm to the driver via the audio speaker 12061 or the display unit 12062, or by performing forced deceleration or avoidance steering via the drive system control unit 12010.

[0302] At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 can recognize a pedestrian by determining whether or not a pedestrian is present in the captured images of the imaging units 12101 to 12104. The recognition of such a pedestrian is performed, for example, by a procedure of extracting feature points in the captured images of the imaging units 12101 to 12104 as infrared cameras, and a procedure of performing pattern matching processing on a series of feature points that indicate the contour of an object to determine whether or not the object is a pedestrian. When the microcomputer 12051 determines that a pedestrian is present in the captured images of the imaging units 12101 to 12104 and recognizes the pedestrian, the audio / image output unit 12052 controls the display unit 12062 to superimpose a rectangular contour line for emphasis on the recognized pedestrian. The audio / image output unit 12052 may also control the display unit 12062 to display an icon or the like indicating a pedestrian at a desired position.

[0303] An example of a mobile object control system to which the technology according to the present disclosure can be applied has been described above. The technology according to the present disclosure can be applied to the imaging unit 12031 among the configurations described above. Specifically, the solid-state imaging elements according to the above-mentioned embodiments 1 to 3 and their modified examples can be applied to the imaging unit 12031. By applying the technology according to the present disclosure to the imaging unit 12031, a high-definition captured image with little noise can be obtained, and therefore, high-precision control using the captured image can be performed in the mobile object control system.

[0304] (Application example 2) FIG. 65 is a diagram showing an example of a schematic configuration of an endoscopic surgery system to which the technology according to the present disclosure can be applied.

[0305] 65 shows a state in which an operator 11131 such as a doctor is performing surgery on a patient 11132 on an examination table 11133 using an endoscopic surgery system 11000. As shown in the figure, the endoscopic surgery system 11000 is composed of an endoscope 11100, other surgical tools 11110 such as an insufflation tube 11111 and an energy treatment tool 11112, a support arm device 11120 that supports the endoscope 11100, and a cart 11200 on which various devices for endoscopic surgery are mounted.

[0306] The endoscope 11100 is composed of a lens barrel 11101, a region of a predetermined length from the tip of which is inserted into a body cavity of a patient 11132, and a camera head 11102 connected to the base end of the lens barrel 11101. In the illustrated example, the endoscope 11100 is configured as a so-called rigid scope having a rigid lens barrel 11101, but the endoscope 11100 may be configured as a so-called flexible scope having a flexible lens barrel.

[0307] An opening into which an objective lens is fitted is provided at the tip of the lens barrel 11101. A light source device 11203 is connected to the endoscope 11100, and light generated by this light source device 11203 is guided to the tip of the lens barrel 11101 by a light guide extending inside the lens barrel 11101, and is irradiated via the objective lens toward an observation target in the body cavity of the patient 11132. The endoscope 11100 may be a direct-viewing endoscope, an oblique-viewing endoscope, or a side-viewing endoscope.

[0308] An optical system and any one of the solid-state imaging elements according to the above-mentioned embodiments 1 to 3 and their modifications are provided inside the camera head 11102, and the reflected light from the observation object, i.e., the observation light, is collected on the solid-state imaging element by the optical system. The observation light is photoelectrically converted by the solid-state imaging element to generate an electrical signal corresponding to the observation light, i.e., an image signal corresponding to the observation image. The image signal is transmitted to a camera control unit (CCU) 11201 as RAW data.

[0309] The CCU 11201 is configured with a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), etc., and performs overall control of the operations of the endoscope 11100 and the display device 11202. Furthermore, the CCU 11201 receives an image signal from the camera head 11102, and performs various types of image processing on the image signal, such as development processing (demosaic processing), for displaying an image based on the image signal.

[0310] Under the control of the CCU 11201, the display device 11202 displays an image based on an image signal that has been subjected to image processing by the CCU 11201.

[0311] The light source device 11203 is composed of a light source such as an LED (Light Emitting Diode), and supplies the endoscope 11100 with irradiation light when photographing an operation site or the like.

[0312] The input device 11204 is an input interface for the endoscopic surgery system 11000. A user can input various information and instructions to the endoscopic surgery system 11000 via the input device 11204. For example, the user inputs an instruction to change imaging conditions such as the type of light irradiated by the endoscope 11100, magnification, and focal length.

[0313] The treatment tool control device 11205 controls the driving of the energy treatment tool 11112 for cauterizing tissue, incising, sealing blood vessels, etc. The insufflation device 11206 sends gas into the body cavity of the patient 11132 via the insufflation tube 11111 to inflate the body cavity of the patient 11132 for the purpose of securing the field of view of the endoscope 11100 and securing the working space of the surgeon 11131. The recorder 11207 is a device capable of recording various information related to the surgery. The printer 11208 is a device capable of printing various information related to the surgery in various formats such as text, image, or graph.

[0314] The light source device 11203 that supplies irradiation light to the endoscope 11100 when photographing the surgical site can be composed of a white light source composed of, for example, an LED, a laser light source, or a combination of these. When the white light source is composed of a combination of RGB laser light sources, the output intensity and output timing of each wavelength for each color can be controlled with high precision, so that the light source device 11203 can adjust the white balance of the captured image. In this case, it is also possible to capture images corresponding to each of the RGB colors in a time-division manner by irradiating the observation target with laser light from each of the RGB laser light sources in a time-division manner and controlling the driving of the solid-state imaging element of the camera head 11102 in synchronization with the irradiation timing. According to this method, a color image can be obtained without providing a color filter to the solid-state imaging element.

[0315] The light source device 11203 may be controlled to change the intensity of the light it outputs at predetermined time intervals. By controlling the driving of the solid-state image sensor of the camera head 11102 in synchronization with the timing of the change in the light intensity to obtain images in a time-division manner and synthesizing the images, it is possible to generate an image with a high dynamic range that is free of so-called blackout and whiteout.

[0316] The light source device 11203 may be configured to supply light of a predetermined wavelength band corresponding to the special light observation. In the special light observation, for example, by utilizing the wavelength dependency of light absorption in body tissue, a specific tissue such as blood vessels on the surface of the mucosa is photographed with high contrast by irradiating light of a narrow band compared to white light, which is the irradiating light during normal observation, so-called narrow band imaging is performed. Alternatively, the special light observation may be performed in which an image is obtained by fluorescence generated by irradiating excitation light. In the fluorescence observation, it is possible to perform autofluorescence observation in which excitation light is irradiated to the body tissue and the fluorescence from the body tissue is observed, or to locally inject a reagent such as indocyanine green (ICG) into the body tissue and irradiate the body tissue with excitation light corresponding to the fluorescence wavelength of the reagent to obtain a fluorescent image. The light source device 11203 may be configured to supply at least one of narrow band light and excitation light corresponding to such special light observation.

[0317] FIG. 66 is a block diagram showing an example of the functional configuration of the camera head 11102 and the CCU 11201 shown in FIG.

[0318] The camera head 11102 has a lens unit 11401, an imaging unit 11402, a drive unit 11403, a communication unit 11404, and a camera head control unit 11405. The CCU 11201 has a communication unit 11411, an image processing unit 11412, and a control unit 11413. The camera head 11102 and the CCU 11201 are connected to each other by a transmission cable 11400 so as to be able to communicate with each other.

[0319] The lens unit 11401 is an optical system provided at the connection portion with the lens barrel 11101. Observation light taken in from the tip of the lens barrel 11101 is guided to the camera head 11102 and enters the lens unit 11401. The lens unit 11401 is configured by combining a plurality of lenses including a zoom lens and a focus lens.

[0320] The imaging unit 11402 is composed of a solid-state imaging element. The solid-state imaging element constituting the imaging unit 11402 may be one of a so-called single-plate type, or may be a plurality of so-called multi-plate type. When the imaging unit 11402 is composed of a multi-plate type, for example, each solid-state imaging element may generate an image signal corresponding to each of RGB, and a color image may be obtained by combining the image signals. Alternatively, the imaging unit 11402 may be configured to have a pair of solid-state imaging elements for acquiring image signals for the right eye and the left eye corresponding to 3D (Dimensional) display. By performing 3D display, the surgeon 11131 can more accurately grasp the depth of the biological tissue in the surgical site. Note that when the imaging unit 11402 is composed of a multi-plate type, the lens unit 11401 may also be provided in a plurality of systems corresponding to each solid-state imaging element.

[0321] Furthermore, the imaging unit 11402 does not necessarily have to be provided in the camera head 11102. For example, the imaging unit 11402 may be provided inside the lens barrel 11101, immediately behind the objective lens.

[0322] The driving unit 11403 is configured by an actuator, and moves the zoom lens and focus lens of the lens unit 11401 by a predetermined distance along the optical axis under the control of the camera head control unit 11405. This allows the magnification and focus of the image captured by the imaging unit 11402 to be appropriately adjusted.

[0323] The communication unit 11404 is configured by a communication device for transmitting and receiving various information to and from the CCU 11201. The communication unit 11404 transmits the image signal obtained from the imaging unit 11402 to the CCU 11201 via the transmission cable 11400 as RAW data.

[0324] Furthermore, the communication unit 11404 receives control signals for controlling the driving of the camera head 11102 from the CCU 11201, and supplies the control signals to the camera head control unit 11405. Such control signals include information on the imaging conditions, such as information specifying the frame rate of the captured image, information specifying the exposure value at the time of capturing the image, information specifying the magnification and focus of the captured image, and the like.

[0325] The image capturing conditions such as the frame rate, exposure value, magnification, and focus may be appropriately specified by a user, or may be automatically set by the control unit 11413 of the CCU 11201 based on an acquired image signal. In the latter case, the endoscope 11100 is equipped with a so-called AE (Auto Exposure) function, AF (Auto Focus) function, and AWB (Auto White Balance) function.

[0326] The camera head control unit 11405 controls the driving of the camera head 11102 based on a control signal received from the CCU 11201 via the communication unit 11404.

[0327] The communication unit 11411 is configured with a communication device for transmitting and receiving various information to and from the camera head 11102. The communication unit 11411 receives an image signal transmitted from the camera head 11102 via the transmission cable 11400.

[0328] Furthermore, the communication unit 11411 transmits, to the camera head 11102, a control signal for controlling the driving of the camera head 11102. The image signal and the control signal can be transmitted by electrical communication, optical communication, or the like.

[0329] The image processing unit 11412 performs various types of image processing on the image signal, which is RAW data sent from the camera head 11102 .

[0330] The control unit 11413 performs various controls related to imaging of the surgical site etc. by the endoscope 11100 and display of the captured image obtained by imaging the surgical site etc. For example, the control unit 11413 generates a control signal for controlling the driving of the camera head 11102.

[0331] Further, the control unit 11413 causes the display device 11202 to display the captured image showing the surgical site, etc., based on the image signal that has been image-processed by the image processing unit 11412. At this time, the control unit 11413 may recognize various objects in the captured image using various image recognition techniques. For example, the control unit 11413 can recognize the surgical tool 11110 such as forceps, a specific living body part, bleeding, mist when the energy treatment tool 11112 is used, etc., by detecting the shape and color of the edge of the object included in the captured image. When the control unit 11413 causes the display device 11202 to display the captured image, it may use the recognition result to superimpose various types of surgery support information on the image of the surgical site. By superimposing and presenting the surgery support information to the surgeon 11131, the burden on the surgeon 11131 can be reduced and the surgeon 11131 can proceed with the surgery reliably.

[0332] The transmission cable 11400 connecting the camera head 11102 and the CCU 11201 is an electrical signal cable for communication of electrical signals, an optical fiber for optical communication, or a composite cable of these.

[0333] Here, in the illustrated example, communication is performed wired using a transmission cable 11400, but communication between the camera head 11102 and the CCU 11201 may also be performed wirelessly.

[0334] An example of an endoscopic surgery system to which the technology according to the present disclosure can be applied has been described above. Of the configurations described above, the technology according to the present disclosure can be suitably applied to the imaging unit 11402 provided in the camera head 11102 of the endoscope 11100. By applying the technology according to the present disclosure to the imaging unit 11402, the imaging unit 11402 can be made smaller or have higher resolution, so that a small or high-resolution endoscope 11100 can be provided.

[0335] [Embodiment 7] In describing the seventh embodiment, terms have been selected and symbols have been assigned from a different perspective than in the above-described embodiments. Therefore, the configurations indicated by the following terms and symbols may differ from the configurations indicated by the similar terms and symbols in the above-described embodiments. (Functional configuration of imaging device 1) FIG. 67 is a block diagram showing an example of a functional configuration of an imaging device (imaging device 1) according to the seventh embodiment of the present disclosure.

[0336] The imaging device 1 in FIG. 67 includes, for example, an input section 510A, a row driver section 520, a timing control section 530, a pixel array section 540, a column signal processing section 550, an image signal processing section 560, and an output section 510B.

[0337] In the pixel array section 540, pixels 541 are repeatedly arranged in an array. More specifically, a pixel sharing unit 539 including a plurality of pixels is a repeating unit, and this is repeatedly arranged in an array having a row direction and a column direction. In this embodiment, for convenience, the row direction may be called the H direction, and the column direction perpendicular to the row direction may be called the V direction. In the example of FIG. 67, one pixel sharing unit 539 includes four pixels (pixels 541A, 541B, 541C, and 541D). Each of the pixels 541A, 541B, 541C, and 541D has a photodiode PD (illustrated in FIG. 72, etc., which will be described later). The pixel sharing unit 539 is a unit that shares one pixel circuit (pixel circuit 210 in FIG. 69, which will be described later). In other words, one pixel circuit (pixel circuit 210, which will be described later) is included for every four pixels (pixels 541A, 541B, 541C, and 541D). By operating this pixel circuit in a time-division manner, pixel signals of the pixels 541A, 541B, 541C, and 541D are sequentially read out. The pixels 541A, 541B, 541C, and 541D are arranged in, for example, 2 rows and 2 columns. In the pixel array section 540, a plurality of row driving signal lines 542 and a plurality of vertical signal lines (column readout lines) 543 are provided in addition to the pixels 541A, 541B, 541C, and 541D. The row driving signal line 542 drives the pixels 541 included in each of a plurality of pixel sharing units 539 arranged in a row direction in the pixel array section 540. The row driving signal line 542 drives each pixel arranged in a row direction among the pixel sharing units 539. As will be described in detail later with reference to FIG. 70, the pixel sharing unit 539 is provided with a plurality of transistors. In order to drive each of these transistors, a plurality of row driving signal lines 542 are connected to one pixel sharing unit 539. The pixel sharing unit 539 is connected to the vertical signal line (column readout line) 543. Pixel signals are read out via the vertical signal line (column readout line) 543 from each of the pixels 541A, 541B, 541C, and 541D included in the pixel sharing unit 539.

[0338] The row driving unit 520 includes, for example, a row address control unit that determines the position of the row for pixel driving, in other words, a row decoder unit, and a row driving circuit unit that generates signals for driving the pixels 541A, 541B, 541C, and 541D.

[0339] The column signal processing unit 550 includes, for example, a load circuit unit that is connected to the vertical signal line 543 and forms a source follower circuit together with the pixels 541A, 541B, 541C, and 541D (pixel sharing units 539). The column signal processing unit 550 may include an amplifier circuit unit that amplifies a signal read out from the pixel sharing unit 539 via the vertical signal line 543. The column signal processing unit 550 may include a noise processing unit. In the noise processing unit, for example, a system noise level is removed from the signal read out from the pixel sharing unit 539 as a result of photoelectric conversion.

[0340] The column signal processing unit 550 has, for example, an analog-to-digital converter (ADC). In the analog-to-digital converter, the signal read from the pixel sharing unit 539 or the analog signal that has been subjected to the noise processing is converted into a digital signal. The ADC includes, for example, a comparator unit and a counter unit. In the comparator unit, the analog signal to be converted is compared with a reference signal to be compared therewith. In the counter unit, the time until the comparison result in the comparator unit is inverted is measured. The column signal processing unit 550 may include a horizontal scanning circuit unit that controls scanning of the readout column.

[0341] The timing control section 530 supplies signals for controlling timing to the row driving section 520 and the column signal processing section 550 based on a reference clock signal and a timing control signal input to the device.

[0342] The image signal processing unit 560 is a circuit that performs various signal processing on data obtained as a result of photoelectric conversion, in other words, data obtained as a result of the imaging operation in the imaging device 1. The image signal processing unit 560 includes, for example, an image signal processing circuit unit and a data holding unit. The image signal processing unit 560 may also include a processor unit.

[0343] One example of signal processing executed by the image signal processing unit 560 is a tone curve correction process that imparts more gradation to the AD converted imaging data when the data is of a dark subject, and reduces the gradation when the data is of a bright subject. In this case, it is desirable to store in advance in the data storage unit of the image signal processing unit 560 characteristic data of the tone curve based on which the gradation of the imaging data is to be corrected.

[0344] The input section 510A is for inputting, for example, the above-mentioned reference clock signal, timing control signal, characteristic data, and the like from outside the device to the imaging device 1. The timing control signal is, for example, a vertical synchronization signal and a horizontal synchronization signal. The characteristic data is, for example, for storage in a data holding section of the image signal processing section 560. The input section 510A includes, for example, an input terminal 511, an input circuit section 512, an input amplitude changing section 513, an input data conversion circuit section 514, and a power supply section (not shown).

[0345] The input terminal 511 is an external terminal for inputting data. The input circuit unit 512 is for taking in the signal input to the input terminal 511 into the inside of the imaging device 1. The input amplitude change unit 513 changes the amplitude of the signal taken in by the input circuit unit 512 to an amplitude that is easily used inside the imaging device 1. The input data conversion circuit unit 514 changes the arrangement of the data string of the input data. The input data conversion circuit unit 514 is composed of, for example, a serial-parallel conversion circuit. In this serial-parallel conversion circuit, a serial signal received as input data is converted into a parallel signal. Note that, in the input unit 510A, the input amplitude change unit 513 and the input data conversion circuit unit 514 may be omitted. The power supply unit supplies power set to various voltages required inside the imaging device 1 based on a power source supplied from the outside to the imaging device 1.

[0346] When the imaging device 1 is connected to an external memory device, the input unit 510A may be provided with a memory interface circuit that receives data from the external memory device. The external memory device may be, for example, a flash memory, an SRAM, or a DRAM.

[0347] The output unit 510B outputs image data to the outside of the device. This image data is, for example, image data captured by the imaging device 1 and image data signal-processed by the image signal processing unit 560. The output unit 510B includes, for example, an output data conversion circuit unit 515, an output amplitude change unit 516, an output circuit unit 517, and an output terminal 518.

[0348] The output data conversion circuit unit 515 is configured, for example, by a parallel-serial conversion circuit, and the output data conversion circuit unit 515 converts the parallel signal used inside the imaging device 1 into a serial signal. The output amplitude change unit 516 changes the amplitude of the signal used inside the imaging device 1. The signal with the changed amplitude can be easily used by an external device connected to the outside of the imaging device 1. The output circuit unit 517 is a circuit that outputs data from inside the imaging device 1 to the outside of the device, and the output circuit unit 517 drives a wiring outside the imaging device 1 connected to an output terminal 518. The output terminal 518 outputs data from the imaging device 1 to the outside of the device. In the output unit 510B, the output data conversion circuit unit 515 and the output amplitude change unit 516 may be omitted.

[0349] When the imaging device 1 is connected to an external memory device, the output unit 510B may be provided with a memory interface circuit that outputs data to the external memory device. The external memory device may be, for example, a flash memory, an SRAM, or a DRAM.

[0350] (Schematic configuration of imaging device 1) FIG. 68 and FIG. 69 show an example of a schematic configuration of the imaging device 1. The imaging device 1 includes three substrates (a first substrate 100, a second substrate 200, and a third substrate 300). FIG. 68 shows a schematic planar configuration of each of the first substrate 100, the second substrate 200, and the third substrate 300, and FIG. 69 shows a schematic cross-sectional configuration of the first substrate 100, the second substrate 200, and the third substrate 300 stacked on top of each other. FIG. 69 corresponds to the cross-sectional configuration along line III-III' shown in FIG. 68. The imaging device 1 is a three-dimensional imaging device formed by bonding three substrates (the first substrate 100, the second substrate 200, and the third substrate 300). The first substrate 100 includes a semiconductor layer 100S and a wiring layer 100T. The second substrate 200 includes a semiconductor layer 200S and a wiring layer 200T. The third substrate 300 includes a semiconductor layer 300S and a wiring layer 300T. Here, the combination of the wiring included in each of the first substrate 100, the second substrate 200, and the third substrate 300 and the interlayer insulating film around it is called the wiring layer (100T, 200T, 300T) provided on each substrate (the first substrate 100, the second substrate 200, and the third substrate 300) for convenience. The first substrate 100, the second substrate 200, and the third substrate 300 are stacked in this order, and the semiconductor layer 100S, the wiring layer 100T, the semiconductor layer 200S, the wiring layer 200T, the wiring layer 300T, and the semiconductor layer 300S are arranged in this order along the stacking direction. The specific configurations of the first substrate 100, the second substrate 200, and the third substrate 300 will be described later. The arrow shown in FIG. 69 indicates the incident direction of the light L to the imaging device 1. In this embodiment, for convenience, in the following cross-sectional views, the light incident side of the imaging device 1 may be called "bottom", "lower side", or "downward", and the side opposite the light incident side may be called "upper side", "upper side", or "upper". Also, in this embodiment, for convenience, with respect to a substrate having a semiconductor layer and a wiring layer, the wiring layer side may be called the front side, and the semiconductor layer side may be called the back side. Note that the description in the specification is not limited to the above names. The imaging device 1 is, for example, a back-illuminated imaging device in which light is incident from the back side of the first substrate 100 having a photodiode.

[0351] The pixel array section 540 and the pixel sharing unit 539 included in the pixel array section 540 are both configured using both the first substrate 100 and the second substrate 200. The first substrate 100 is provided with a plurality of pixels 541A, 541B, 541C, and 541D that the pixel sharing unit 539 has. Each of these pixels 541 has a photodiode (a photodiode PD described later) and a transfer transistor (a transfer transistor TR described later). The second substrate 200 is provided with a pixel circuit (a pixel circuit 210 described later) that the pixel sharing unit 539 has. The pixel circuit reads out pixel signals transferred from the photodiodes of the pixels 541A, 541B, 541C, and 541D via the transfer transistors, or resets the photodiodes. In addition to such pixel circuits, the second substrate 200 has a plurality of row driving signal lines 542 extending in the row direction and a plurality of vertical signal lines 543 extending in the column direction. The second substrate 200 further has a power supply line 544 extending in the row direction. The third substrate 300 has, for example, an input section 510A, a row driver 520, a timing control section 530, a column signal processing section 550, an image signal processing section 560, and an output section 510B. The row driver 520 is provided, for example, in a region partially overlapping the pixel array section 540 in the stacking direction (hereinafter simply referred to as the stacking direction) of the first substrate 100, the second substrate 200, and the third substrate 300. More specifically, the row driver 520 is provided in a region overlapping the vicinity of an end of the pixel array section 540 in the H direction in the stacking direction (FIG. 68). The column signal processing section 550 is provided, for example, in a region partially overlapping the pixel array section 540 in the stacking direction. More specifically, the column signal processing section 550 is provided in a region overlapping with the vicinity of an end portion in the V direction of the pixel array section 540 in the stacking direction (FIG. 68). Although not shown, the input section 510A and the output section 510B may be provided in a portion other than the third substrate 300, for example, on the second substrate 200. Alternatively, the input section 510A and the output section 510B may be provided on the back surface (light incident surface) side of the first substrate 100.The pixel circuits provided on the second substrate 200 may also be called pixel transistor circuits, pixel transistor groups, pixel transistors, pixel readout circuits, or readout circuits. In this embodiment, the term pixel circuits is used.

[0352] The first substrate 100 and the second substrate 200 are electrically connected by, for example, through electrodes (through electrodes 120E, 121E in FIG. 72 described later). The second substrate 200 and the third substrate 300 are electrically connected by, for example, contact portions 201, 202, 301, 302. The second substrate 200 is provided with contact portions 201, 202, and the third substrate 300 is provided with contact portions 301, 302. The contact portion 201 of the second substrate 200 contacts the contact portion 301 of the third substrate 300, and the contact portion 202 of the second substrate 200 contacts the contact portion 302 of the third substrate 300. The second substrate 200 has a contact region 201R in which a plurality of contact portions 201 are provided, and a contact region 202R in which a plurality of contact portions 202 are provided. The third substrate 300 has a contact region 301R in which a plurality of contact parts 301 are provided, and a contact region 302R in which a plurality of contact parts 302 are provided. The contact regions 201R, 301R are provided between the pixel array section 540 and the row driver section 520 in the stacking direction (FIG. 69). In other words, the contact regions 201R, 301R are provided, for example, in a region where the row driver section 520 (third substrate 300) and the pixel array section 540 (second substrate 200) overlap in the stacking direction, or in a region adjacent thereto. The contact regions 201R, 301R are disposed, for example, at the end in the H direction of such a region (FIG. 68). In the third substrate 300, for example, the contact region 301R is provided at a position overlapping a part of the row driver section 520, specifically, the end in the H direction of the row driver section 520 (FIGS. 68 and 69). The contact sections 201 and 301 connect, for example, the row driving section 520 provided on the third substrate 300 and the row driving line 542 provided on the second substrate 200. The contact sections 201 and 301 may connect, for example, the input section 510A provided on the third substrate 300 to a power supply line 544 and a reference potential line (a reference potential line VSS described later). The contact regions 202R and 302R are provided between the pixel array section 540 and the column signal processing section 550 in the stacking direction (FIG. 69).In other words, the contact regions 202R and 302R are provided in, for example, a region where the column signal processing section 550 (the third substrate 300) and the pixel array section 540 (the second substrate 200) overlap in the stacking direction, or in a region adjacent thereto. The contact regions 202R and 302R are arranged, for example, at the end in the V direction of such a region (FIG. 68). In the third substrate 300, for example, the contact region 301R is provided in a position overlapping a part of the column signal processing section 550, specifically, an end in the V direction of the column signal processing section 550 (FIGS. 68 and 69). The contact sections 202 and 302 are for connecting, for example, pixel signals (signals corresponding to the amount of charge generated as a result of photoelectric conversion in the photodiodes) output from each of the multiple pixel sharing units 539 of the pixel array section 540 to the column signal processing section 550 provided on the third substrate 300. The pixel signals are sent from the second substrate 200 to the third substrate 300.

[0353] FIG. 69 is an example of a cross-sectional view of the imaging device 1 as described above. The first substrate 100, the second substrate 200, and the third substrate 300 are electrically connected via wiring layers 100T, 200T, and 300T. For example, the imaging device 1 has an electrical connection portion that electrically connects the second substrate 200 and the third substrate 300. Specifically, the contact portions 201, 202, 301, and 302 are formed with electrodes formed of a conductive material. The conductive material is formed of a metal material such as copper (Cu), aluminum (Al), and gold (Au). The contact regions 201R, 202R, 301R, and 302R electrically connect the second substrate and the third substrate by directly joining wirings formed as electrodes, for example, to each other, thereby enabling input and / or output of signals between the second substrate 200 and the third substrate 300.

[0354] The electrical connection portion that electrically connects the second substrate 200 and the third substrate 300 can be provided at a desired location. For example, as described as the contact regions 201R, 202R, 301R, and 302R in FIG. 69, the electrical connection portion may be provided in a region that overlaps with the pixel array section 540 in the stacking direction. The electrical connection portion may also be provided in a region that does not overlap with the pixel array section 540 in the stacking direction. Specifically, the electrical connection portion may be provided in a region that overlaps with a peripheral portion disposed outside the pixel array section 540 in the stacking direction.

[0355] The first substrate 100 and the second substrate 200 are provided with, for example, connection holes H1 and H2. The connection holes H1 and H2 penetrate the first substrate 100 and the second substrate 200 (FIG. 69). The connection holes H1 and H2 are provided outside the pixel array section 540 (or a portion overlapping the pixel array section 540) (FIG. 68). For example, the connection hole H1 is disposed outside the pixel array section 540 in the H direction, and the connection hole H2 is disposed outside the pixel array section 540 in the V direction. For example, the connection hole H1 reaches the input section 510A provided on the third substrate 300, and the connection hole H2 reaches the output section 510B provided on the third substrate 300. The connection holes H1 and H2 may be hollow or may contain a conductive material at least in part. For example, there is a configuration in which a bonding wire is connected to an electrode formed as the input section 510A and / or the output section 510B. Alternatively, there is a configuration in which an electrode formed as the input section 510A and / or the output section 510B is connected to a conductive material provided in the connection holes H1, H2. The conductive material provided in the connection holes H1, H2 may be embedded in a part or all of the connection holes H1, H2, or the conductive material may be formed on the side walls of the connection holes H1, H2.

[0356] 69 shows a structure in which the input section 510A and the output section 510B are provided on the third substrate 300, but the present invention is not limited to this. For example, the input section 510A and / or the output section 510B can be provided on the second substrate 200 by sending a signal of the third substrate 300 to the second substrate 200 via the wiring layers 200T and 300T. Similarly, the input section 510A and / or the output section 510B can be provided on the first substrate 100 by sending a signal of the second substrate 200 to the first substrate 1000 via the wiring layers 100T and 200T.

[0357] FIG. 70 is an equivalent circuit diagram showing an example of the configuration of the pixel sharing unit 539. The pixel sharing unit 539 includes a plurality of pixels 541 (four pixels 541, 541A, 541B, 541C, and 541D, are shown in FIG. 70), one pixel circuit 210 connected to the plurality of pixels 541, and a vertical signal line 5433 connected to the pixel circuit 210. The pixel circuit 210 includes, for example, four transistors, specifically, an amplification transistor AMP, a selection transistor SEL, a reset transistor RST, and an FD conversion gain switching transistor FD. As described above, the pixel sharing unit 539 is configured to sequentially output pixel signals of the four pixels 541 (pixels 541A, 541B, 541C, and 541D) included in the pixel sharing unit 539 to the vertical signal line 543 by operating one pixel circuit 210 in a time-division manner. A state in which one pixel circuit 210 is connected to multiple pixels 541 and the pixel signals of the multiple pixels 541 are output in a time-division manner by the single pixel circuit 210 is said to be "multiple pixels 541 sharing one pixel circuit 210."

[0358] The pixels 541A, 541B, 541C, and 541D have components in common with each other. Hereinafter, in order to distinguish the components of the pixels 541A, 541B, 541C, and 541D from each other, the identification number 1 is added to the end of the reference numeral of the component of the pixel 541A, the identification number 2 is added to the end of the reference numeral of the component of the pixel 541B, the identification number 3 is added to the end of the reference numeral of the component of the pixel 541C, and the identification number 4 is added to the end of the reference numeral of the component of the pixel 541D. When it is not necessary to distinguish the components of the pixels 541A, 541B, 541C, and 541D from each other, the identification numbers at the end of the reference numerals of the components of the pixels 541A, 541B, 541C, and 541D are omitted.

[0359] The pixels 541A, 541B, 541C, and 541D each have, for example, a photodiode PD, a transfer transistor TR electrically connected to the photodiode PD, and a floating diffusion FD electrically connected to the transfer transistor TR. In the photodiodes PD (PD1, PD2, PD3, and PD4), the cathode is electrically connected to the source of the transfer transistor TR, and the anode is electrically connected to a reference potential line (for example, ground). The photodiode PD photoelectrically converts incident light and generates a charge according to the amount of light received. The transfer transistors TR (transfer transistors TR1, TR2, TR3, and TR4) are, for example, n-type CMOS (Complementary Metal Oxide Semiconductor) transistors. In the transfer transistor TR, the drain is electrically connected to the floating diffusion FD, and the gate is electrically connected to a drive signal line. This drive signal line is a part of a plurality of row drive signal lines 542 (see FIG. 67) connected to one pixel sharing unit 539. The transfer transistor TR transfers the charge generated in the photodiode PD to the floating diffusion FD. The floating diffusion FD (floating diffusions FD1, FD2, FD3, FD4) is an n-type diffusion layer region formed in a p-type semiconductor layer. The floating diffusion FD is a charge holding means that temporarily holds the charge transferred from the photodiode PD, and is also a charge-voltage conversion means that generates a voltage according to the amount of charge.

[0360] The four floating diffusions FD (floating diffusions FD1, FD2, FD3, and FD4) included in one pixel shared unit 539 are electrically connected to each other and to the gate of the amplification transistor AMP and the source of the FD conversion gain switching transistor FDG. The drain of the FD conversion gain switching transistor FDG is connected to the source of the reset transistor RST, and the gate of the FD conversion gain switching transistor FDG is connected to a drive signal line. This drive signal line is a part of a plurality of row drive signal lines 542 connected to one pixel shared unit 539. The drain of the reset transistor RST is connected to a power supply line VDD, and the gate of the reset transistor RST is connected to the drive signal line. This drive signal line is a part of a plurality of row drive signal lines 542 connected to one pixel shared unit 539. The gate of the amplification transistor AMP is connected to the floating diffusion FD, the drain of the amplification transistor AMP is connected to the power supply line VDD, and the source of the amplification transistor AMP is connected to the drain of the selection transistor SEL. The source of the selection transistor SEL is connected to a vertical signal line 543, and the gate of the selection transistor SEL is connected to the drive signal line. This drive signal line is part of a plurality of row drive signal lines 542 connected to one pixel sharing unit 539 .

[0361] When the transfer transistor TR is turned on, the transfer transistor TR transfers the charge of the photodiode PD to the floating diffusion FD. The gate (transfer gate TG) of the transfer transistor TR includes, for example, a so-called vertical electrode, and is provided extending from the surface of the semiconductor layer (semiconductor layer 100S in FIG. 72 described later) to a depth reaching the PD, as shown in FIG. 72 described later. The reset transistor RST resets the potential of the floating diffusion FD to a predetermined potential. When the reset transistor RST is turned on, the potential of the floating diffusion FD is reset to the potential of the power supply line VDD. The selection transistor SEL controls the output timing of the pixel signal from the pixel circuit 210. The amplification transistor AMP generates, as the pixel signal, a signal of a voltage according to the level of the charge held in the floating diffusion FD. The amplification transistor AMP is connected to the vertical signal line 543 via the selection transistor SEL. In the column signal processing unit 550, the amplification transistor AMP configures a source follower together with a load circuit unit (see FIG. 67) connected to the vertical signal line 543. When the selection transistor SEL is turned on, the amplification transistor AMP outputs the voltage of the floating diffusion FD to the column signal processing unit 550 via the vertical signal line 543. The reset transistor RST, the amplification transistor AMP, and the selection transistor SEL are, for example, n-type CMOS transistors.

[0362] The FD conversion gain switching transistor FDG is used to change the gain of the charge-voltage conversion in the floating diffusion FD. In general, the pixel signal is small when shooting in a dark place. Based on Q=CV, when performing charge-voltage conversion, if the capacitance (FD capacitance C) of the floating diffusion FD is large, V when converted to voltage by the amplification transistor AMP will be small. On the other hand, in a bright place, the pixel signal becomes large, so if the FD capacitance C is not large, the floating diffusion FD cannot receive the charge of the photodiode PD. Furthermore, the FD capacitance C needs to be large so that V when converted to voltage by the amplification transistor AMP does not become too large (in other words, so that it becomes small). In consideration of this, when the FD conversion gain switching transistor FDG is turned on, the gate capacitance of the FD conversion gain switching transistor FDG increases, so the overall FD capacitance C becomes large. On the other hand, when the FD conversion gain switching transistor FDG is turned off, the overall FD capacitance C becomes small. In this way, by switching the FD conversion gain switching transistor FDG on and off, the FD capacitance C can be made variable and the conversion efficiency can be switched. The FD conversion gain switching transistor FDG is, for example, an n-type CMOS transistor.

[0363] It is also possible to configure the pixel circuit 210 without providing the FD conversion gain switching transistor FDG. In this case, for example, the pixel circuit 210 is composed of three transistors, for example, an amplification transistor AMP, a selection transistor SEL, and a reset transistor RST. The pixel circuit 210 has at least one pixel transistor, for example, an amplification transistor AMP, a selection transistor SEL, a reset transistor RST, and an FD conversion gain switching transistor FDG.

[0364] The selection transistor SEL may be provided between the power supply line VDD and the amplification transistor AMP. In this case, the drain of the reset transistor RST is electrically connected to the power supply line VDD and the drain of the selection transistor SEL. The source of the selection transistor SEL is electrically connected to the drain of the amplification transistor AMP, and the gate of the selection transistor SEL is electrically connected to the row drive signal line 542 (see FIG. 67). The source of the amplification transistor AMP (the output terminal of the pixel circuit 210) is electrically connected to the vertical signal line 543, and the gate of the amplification transistor AMP is electrically connected to the source of the reset transistor RST. Although not shown, the number of pixels 541 sharing one pixel circuit 210 may be other than four. For example, two or eight pixels 541 may share one pixel circuit 210.

[0365] FIG. 71 shows an example of a connection between a plurality of pixel sharing units 539 and a vertical signal line 543. For example, four pixel sharing units 539 arranged in a column direction are divided into four groups, and a vertical signal line 543 is connected to each of the four groups. For the sake of simplicity, FIG. 71 shows an example in which each of the four groups has one pixel sharing unit 539, but each of the four groups may include a plurality of pixel sharing units 539. In this way, in the imaging device 1, a plurality of pixel sharing units 539 arranged in a column direction may be divided into groups including one or more pixel sharing units 539. For example, a vertical signal line 543 and a column signal processing circuit 550 are connected to each of the groups, so that pixel signals can be read out simultaneously from each group. Alternatively, in the imaging device 1, one vertical signal line 543 may be connected to a plurality of pixel sharing units 539 arranged in a column direction. In this case, pixel signals are read out sequentially in a time-division manner from the plurality of pixel sharing units 539 connected to one vertical signal line 543.

[0366] (Specific Configuration of Imaging Device 1) FIG. 72 shows an example of a cross-sectional configuration perpendicular to the main surfaces of the first substrate 100, the second substrate 100, and the third substrate 300 of the imaging device 1. FIG. 72 is a schematic representation for making it easier to understand the positional relationship of the components, and may differ from the actual cross section. In the imaging device 1, the first substrate 100, the second substrate 200, and the third substrate 300 are stacked in this order. The imaging device 1 further has a light receiving lens 401 on the back side (light incident surface side) of the first substrate 100. A color filter layer (not shown) may be provided between the light receiving lens 401 and the first substrate 100. The light receiving lens 401 is provided, for example, for each of the pixels 541A, 541B, 541C, and 541D. The imaging device 1 is, for example, a back-illuminated imaging device. The imaging device 1 has a pixel array section 540 arranged in the center and a peripheral section 540B arranged outside the pixel array section 540.

[0367] The first substrate 100 has, in order from the light receiving lens 401 side, an insulating film 111, a fixed charge film 112, a semiconductor layer 100S, and a wiring layer 100T. The semiconductor layer 100S is made of, for example, a silicon substrate. The semiconductor layer 100S has, for example, a p-well layer 115 in a part of the surface (the surface on the wiring layer 100T side) and in the vicinity thereof, and has an n-type semiconductor region 114 in the other region (region deeper than the p-well layer 115). For example, the n-type semiconductor region 114 and the p-well layer 115 form a pn junction type photodiode PD. The p-well layer 115 is a p-type semiconductor region.

[0368] Fig. 73A shows an example of a planar configuration of the first substrate 100. Fig. 73A mainly shows the planar configuration of the pixel separation portion 117, the photodiode PD, the floating diffusion FD, the VSS contact region 118, and the transfer transistor TR of the first substrate 100. The configuration of the first substrate 100 will be described using Fig. 73A together with Fig. 72.

[0369] A floating diffusion FD and a VSS contact region 118 are provided near the surface of the semiconductor layer 100S. The floating diffusion FD is composed of an n-type semiconductor region provided in the p-well layer 115. The floating diffusions FD (floating diffusions FD1, FD2, FD3, FD4) of the pixels 541A, 541B, 541C, and 541D are provided close to each other in the center of the pixel shared unit 539 (FIG. 73A). Although details will be described later, the four floating diffusions (floating diffusions FD1, FD2, FD3, FD4) included in this shared unit 539 are electrically connected to each other via electrical connection means (pad portion 120 described later) in the first substrate 100 (more specifically, in the wiring layer 100T). Furthermore, the floating diffusion FD is connected from the first substrate 100 to the second substrate 200 (more specifically, from the wiring layer 100T to the wiring layer 200T) via an electrical means (a through electrode 120E described below). In the second substrate 200 (more specifically, inside the wiring layer 200T), the floating diffusion FD is electrically connected to the gate of the amplification transistor AMP and the source of the FD conversion gain switching transistor FDG by this electrical means.

[0370] The VSS contact region 118 is a region electrically connected to the reference potential line VSS, and is arranged apart from the floating diffusion FD. For example, in the pixels 541A, 541B, 541C, and 541D, the floating diffusion FD is arranged at one end of each pixel in the V direction, and the VSS contact region 118 is arranged at the other end (FIG. 73A). The VSS contact region 118 is, for example, composed of a p-type semiconductor region. The VSS contact region 118 is connected to, for example, a ground potential or a fixed potential. This allows a reference potential to be supplied to the semiconductor layer 100S.

[0371] The first substrate 100 is provided with a transfer transistor TR together with a photodiode PD, a floating diffusion FD, and a VSS contact region 118. The photodiode PD, the floating diffusion FD, the VSS contact region 118, and the transfer transistor TR are provided in each of the pixels 541A, 541B, 541C, and 541D. The transfer transistor TR is provided on the front surface side (the side opposite to the light incident surface side, the second substrate 200 side) of the semiconductor layer 100S. The transfer transistor TR has a transfer gate TG. The transfer gate TG includes, for example, a horizontal portion TGb facing the front surface of the semiconductor layer 100S and a vertical portion TGa provided in the semiconductor layer 100S. The vertical portion TGa extends in the thickness direction of the semiconductor layer 100S. One end of the vertical portion TGa is in contact with the horizontal portion TGb, and the other end is provided in the n-type semiconductor region 114. By configuring the transfer transistor TR with such a vertical transistor, transfer failure of pixel signals is less likely to occur, and the readout efficiency of pixel signals can be improved.

[0372] The horizontal part TGb of the transfer gate TG extends from a position facing the vertical part TGa toward, for example, the center of the pixel sharing unit 539 in the H direction (FIG. 73A). This allows the H direction position of the through electrode (through electrode TGV described below) that reaches the transfer gate TG to be closer to the H direction positions of the through electrodes (through electrodes 120E, 121E described below) connected to the floating diffusion FD and the VSS contact region 118. For example, the multiple pixel sharing units 539 provided on the first substrate 100 have the same configuration (FIG. 73A).

[0373] The semiconductor layer 100S is provided with a pixel separator 117 that separates the pixels 541A, 541B, 541C, and 541D from one another. The pixel separator 117 is formed extending in a normal direction (perpendicular to the surface of the semiconductor layer 100S) of the semiconductor layer 100S. The pixel separator 117 is provided to separate the pixels 541A, 541B, 541C, and 541D from one another, and has, for example, a lattice-like planar shape (FIGS. 73A and 73B). The pixel separator 117 electrically and optically separates the pixels 541A, 541B, 541C, and 541D from one another, for example. The pixel separator 117 includes, for example, a light-shielding film 117A and an insulating film 117B. The light-shielding film 117A is made of, for example, tungsten (W) or the like. The insulating film 117B is provided between the light shielding film 117A and the p-well layer 115 or the n-type semiconductor region 114. The insulating film 117B is made of, for example, silicon oxide (SiO). The pixel separator 117 has, for example, a full trench isolation (FTI) structure and penetrates the semiconductor layer 100S. Although not shown, the pixel separator 117 is not limited to an FTI structure that penetrates the semiconductor layer 100S. For example, it may have a deep trench isolation (DTI) structure that does not penetrate the semiconductor layer 100S. The pixel separator 117 extends in the normal direction of the semiconductor layer 100S and is formed in a partial region of the semiconductor layer 100S.

[0374] The semiconductor layer 100S is provided with, for example, a first pinning region 113 and a second pinning region 116. The first pinning region 113 is provided near the back surface of the semiconductor layer 100S, and is disposed between the n-type semiconductor region 114 and the fixed charge film 112. The second pinning region 116 is provided on a side surface of the pixel separating section 117, specifically, between the pixel separating section 117 and the p-well layer 115 or the n-type semiconductor region 114. The first pinning region 113 and the second pinning region 116 are formed of, for example, a p-type semiconductor region.

[0375] A fixed charge film 112 having a negative fixed charge is provided between the semiconductor layer 100S and the insulating film 111. A first pinning region 113 of the hole accumulation layer is formed at the interface on the light-receiving surface (rear surface) side of the semiconductor layer 100S due to an electric field induced by the fixed charge film 112. This suppresses the generation of dark current due to the interface state on the light-receiving surface side of the semiconductor layer 100S. The fixed charge film 112 is formed, for example, of an insulating film having a negative fixed charge. Examples of materials for the insulating film having a negative fixed charge include hafnium oxide, zirconium oxide, aluminum oxide, titanium oxide, and tantalum oxide.

[0376] A light-shielding film 117A is provided between the fixed charge film 112 and the insulating film 111. This light-shielding film 117A may be provided continuously with the light-shielding film 117A constituting the pixel separating section 117. The light-shielding film 117A between the fixed charge film 112 and the insulating film 111 is selectively provided, for example, at a position facing the pixel separating section 117 in the semiconductor layer 100S. The insulating film 111 is provided so as to cover this light-shielding film 117A. The insulating film 111 is made of, for example, silicon oxide.

[0377] The wiring layer 100T provided between the semiconductor layer 100S and the second substrate 200 has an interlayer insulating film 119, pad portions 120 and 121, a passivation film 122, an interlayer insulating film 123, and a bonding film 124 in this order from the semiconductor layer 100S side. The horizontal portion TGb of the transfer gate TG is provided in this wiring layer 100T, for example. The interlayer insulating film 119 is provided over the entire surface of the semiconductor layer 100S and is in contact with the semiconductor layer 100S. The interlayer insulating film 119 is made of, for example, a silicon oxide film. The configuration of the wiring layer 100T is not limited to the above, and may be any configuration having wiring and an insulating film.

[0378] FIG. 73B shows the configuration of the pad sections 120 and 121 together with the planar configuration shown in FIG. 73A. The pad sections 120 and 121 are provided in selective regions on the interlayer insulating film 119. The pad section 120 is for connecting the floating diffusions FD (floating diffusions FD1, FD2, FD3, and FD4) of the pixels 541A, 541B, 541C, and 541D to each other. The pad section 120 is disposed, for example, in the center of the pixel sharing unit 539 in plan view for each pixel sharing unit 539 (FIG. 73B). The pad section 120 is disposed so as to straddle the pixel separating section 117, and is disposed so as to overlap at least a portion of each of the floating diffusions FD1, FD2, FD3, and FD4 (FIGS. 72 and 73B). Specifically, the pad section 120 is formed in a region that overlaps at least a portion of each of the plurality of floating diffusions FD (floating diffusions FD1, FD2, FD3, FD4) that share the pixel circuit 210 and at least a portion of the pixel separation section 117 formed between the plurality of photodiodes PD (photodiodes PD1, PD2, PD3, PD4) that share the pixel circuit 210 in a direction perpendicular to the surface of the semiconductor layer 100S. The interlayer insulating film 119 is provided with a connection via 120C for electrically connecting the pad section 120 and the floating diffusions FD1, FD2, FD3, FD4. The connection via 120C is provided in each of the pixels 541A, 541B, 541C, 541D. For example, a portion of the pad section 120 is embedded in the connection via 120C, so that the pad section 120 and the floating diffusions FD1, FD2, FD3, FD4 are electrically connected.

[0379] The pad portion 121 is for connecting the multiple VSS contact regions 118 to each other. For example, the VSS contact regions 118 provided in the pixels 541C and 541D of one pixel sharing unit 539 adjacent to each other in the V direction and the VSS contact regions 118 provided in the pixels 541A and 541B of the other pixel sharing unit 539 are electrically connected by the pad portion 121. The pad portion 121 is provided, for example, so as to straddle the pixel separation portion 117, and is arranged so as to overlap at least a part of each of the four VSS contact regions 118. Specifically, the pad portion 121 is formed in a region that overlaps at least a part of each of the multiple VSS contact regions 118 and at least a part of the pixel separation portion 117 formed between the multiple VSS contacts 118 in a direction perpendicular to the surface of the semiconductor layer 100S. The interlayer insulating film 119 is provided with a connection via 121C for electrically connecting the pad portion 121 and the VSS contact region 118. The connection via 121C is provided in each of the pixels 541A, 541B, 541C, and 541D. For example, a part of the pad portion 121 is embedded in the connection via 121C, thereby electrically connecting the pad portion 121 to the VSS contact region 118. For example, the pad portion 120 and the pad portion 121 of each of the multiple pixel sharing units 539 aligned in the V direction are disposed at approximately the same position in the H direction ( FIG. 73B ).

[0380] By providing the pad section 120, it is possible to reduce the wiring for connecting each floating diffusion FD to the pixel circuit 210 (for example, the gate electrode of the amplification transistor AMP) in the entire chip. Similarly, by providing the pad section 121, it is possible to reduce the wiring for supplying a potential to each VSS contact region 118 in the entire chip. This makes it possible to reduce the area of ​​the entire chip, suppress electrical interference between wiring in miniaturized pixels, and / or reduce costs by reducing the number of components.

[0381] The pads 120 and 121 can be provided at desired positions on the first substrate 100 and the second substrate 200. Specifically, the pads 120 and 121 can be provided on either the wiring layer 100T or the insulating region 212 of the semiconductor layer 200S. When provided on the wiring layer 100T, the pads 120 and 121 may be directly in contact with the semiconductor layer 100S. Specifically, the pads 120 and 121 may be directly connected to at least a part of each of the floating diffusion FD and / or the VSS contact region 118. Alternatively, the pads 120 and 121 may be provided at desired positions in the insulating region 2112 of the wiring layer 100T and the semiconductor layer 200S by providing connection vias 120C and 121C from each of the floating diffusion FD and / or the VSS contact region 118 connected to the pads 120 and 121.

[0382] In particular, when the pad portions 120, 121 are provided in the wiring layer 100T, it is possible to reduce the number of wirings connected to the floating diffusion FD and / or the VSS contact region 118 in the insulating region 212 of the semiconductor layer 200S. This makes it possible to reduce the area of ​​the insulating region 212 for forming the through wiring for connecting the floating diffusion FD to the pixel circuit 210, among the second substrate 200 for forming the pixel circuit 210. Therefore, it is possible to secure a large area for the second substrate 200 for forming the pixel circuit 210. By securing the area for the pixel circuit 210, it is possible to form a large pixel transistor, which can contribute to improving image quality by reducing noise, etc.

[0383] In particular, when an FTI structure is used for the pixel separation section 117, it is preferable to provide a floating diffusion FD and / or a VSS contact region 118 in each pixel 541, and therefore, by using the configuration of the pad sections 120, 121, the wiring connecting the first substrate 100 and the second substrate 200 can be significantly reduced.

[0384] 73B, for example, the pad section 120 to which the floating diffusions FD are connected and the pad section 121 to which the VSS contacts 118 are connected are alternately arranged in a straight line in the V direction. The pad sections 120 and 121 are formed in positions surrounded by the photodiodes PD, the transfer gates TG, and the floating diffusions FD. This allows elements other than the floating diffusions FD and the VSS contact regions 118 to be freely arranged on the first substrate 100 on which the elements are formed, and the layout of the entire chip can be made more efficient. In addition, symmetry in the layout of the elements formed in each pixel sharing unit 539 is ensured, and the variation in the characteristics of each pixel 541 can be suppressed.

[0385] The pad parts 120 and 121 are made of, for example, polysilicon (Poly Si), more specifically, doped polysilicon to which impurities are added. The pad parts 120 and 121 are preferably made of a conductive material with high heat resistance, such as polysilicon, tungsten (W), titanium (Ti), and titanium nitride (TiN). This makes it possible to form the pixel circuit 210 after bonding the semiconductor layer 200S of the second substrate 200 to the first substrate 100. The reason for this will be explained below. In the following explanation, the method of forming the pixel circuit 210 after bonding the semiconductor layer 200S of the first substrate 100 to the semiconductor layer 200S of the second substrate 200 is called the first manufacturing method.

[0386] Here, it is also conceivable to form the pixel circuits 210 on the second substrate 200 and then bond it to the first substrate 100 (hereinafter referred to as the second manufacturing method). In this second manufacturing method, electrodes for electrical connection are formed in advance on the surface of the first substrate 100 (surface of the wiring layer 100T) and the surface of the second substrate 200 (surface of the wiring layer 200T). When the first substrate 100 and the second substrate 200 are bonded together, the electrodes for electrical connection formed on the surfaces of the first substrate 100 and the second substrate 200 come into contact with each other at the same time. As a result, an electrical connection is formed between the wiring included in the first substrate 100 and the wiring included in the second substrate 200. Therefore, by configuring the imaging device 1 using the second manufacturing method, it is possible to manufacture the imaging device using an appropriate process according to the configuration of each of the first substrate 100 and the second substrate 200, for example, and it is possible to manufacture a high-quality, high-performance imaging device.

[0387] In such a second manufacturing method, when the first substrate 100 and the second substrate 200 are bonded together, an alignment error may occur due to a manufacturing device for bonding. In addition, the first substrate 100 and the second substrate 200 have a diameter of, for example, several tens of centimeters, and when the first substrate 100 and the second substrate 200 are bonded together, the substrates may expand and contract in microscopic regions of the first substrate 100 and the second substrate 200. This expansion and contraction of the substrates is caused by a slight difference in the timing at which the substrates contact each other. Due to such expansion and contraction of the first substrate 100 and the second substrate 200, an error may occur in the position of the electrodes for electrical connection formed on the surface of the first substrate 100 and the surface of the second substrate 200. In the second manufacturing method, it is preferable to take measures so that the electrodes of the first substrate 100 and the second substrate 200 contact each other even if such an error occurs. Specifically, at least one, and preferably both, of the electrodes of the first substrate 100 and the second substrate 200 are made large in consideration of the above-mentioned error. Therefore, when the second manufacturing method is used, for example, the size (size in the substrate planar direction) of the electrode formed on the surface of the first substrate 100 or the second substrate 200 becomes larger than the size of the internal electrode extending in the thickness direction from the inside of the first substrate 100 or the second substrate 200 to the surface.

[0388] On the other hand, by forming the pad parts 120, 121 from a heat-resistant conductive material, it becomes possible to use the first manufacturing method. In the first manufacturing method, after forming the first substrate 100 including the photodiode PD and the transfer transistor TR, the first substrate 100 and the second substrate 200 (semiconductor layer 2000S) are bonded together. At this time, the second substrate 200 is in a state in which the patterns of the active elements and wiring layers constituting the pixel circuits 210 have not yet been formed. Since the second substrate 200 is in a state before the patterns are formed, even if an error occurs in the bonding position when the first substrate 100 and the second substrate 200 are bonded together, this bonding error does not cause an error in the alignment between the pattern of the first substrate 100 and the pattern of the second substrate 200. This is because the pattern of the second substrate 200 is formed after the first substrate 100 and the second substrate 200 are bonded together. When forming a pattern on the second substrate, for example, an exposure device for pattern formation performs pattern formation while using the pattern formed on the first substrate as a target for alignment. For the above reasons, errors in the bonding positions of the first substrate 100 and the second substrate 200 do not pose a problem in manufacturing the imaging device 1 in the first manufacturing method. For the same reason, errors caused by expansion and contraction of the substrates in the second manufacturing method do not pose a problem in manufacturing the imaging device 1 in the first manufacturing method.

[0389] In the first manufacturing method, after the first substrate 100 and the second substrate 200 (semiconductor layer 200S) are bonded together in this manner, active elements are formed on the second substrate 200. After that, the through electrodes 120E, 121E and the through electrodes TGV (FIG. 72) are formed. In forming the through electrodes 120E, 121E, and TGV, for example, a pattern of the through electrodes is formed from above the second substrate 200 using reduced projection exposure by an exposure device. Since reduced exposure projection is used, even if an error occurs in the alignment between the second substrate 200 and the exposure device, the magnitude of the error is only a fraction (the reciprocal of the reduced exposure projection magnification) of the error in the second substrate 200 in the second manufacturing method. Therefore, by configuring the imaging device 1 using the first manufacturing method, it becomes easier to align the elements formed on the first substrate 100 and the second substrate 200, and a high-quality, high-performance imaging device can be manufactured.

[0390] The imaging device 1 manufactured using such a first manufacturing method has different characteristics from the imaging device manufactured using the second manufacturing method. Specifically, in the imaging device 1 manufactured using the first manufacturing method, for example, the through electrodes 120E, 121E, and TGV have a substantially constant thickness (size in the substrate plane direction) from the second substrate 200 to the first substrate 100. Alternatively, when the through electrodes 120E, 121E, and TGV have a tapered shape, they have a tapered shape with a constant inclination. The imaging device 1 having such through electrodes 120E, 121E, and TGV makes it easy to miniaturize the pixels 541.

[0391] Here, when the imaging device 1 is manufactured by the first manufacturing method, since the active elements are formed on the second substrate 200 after bonding the first substrate 100 and the second substrate 200 (semiconductor layer 200S), the first substrate 100 is also affected by the heat treatment required for forming the active elements. For this reason, as described above, it is preferable to use a conductive material with high heat resistance for the pad parts 120, 121 provided on the first substrate 100. For example, it is preferable to use a material with a higher melting point (i.e., higher heat resistance) for the pad parts 120, 121 than at least a part of the wiring material included in the wiring layer 200T of the second substrate 200. For example, a conductive material with high heat resistance such as doped polysilicon, tungsten, titanium, or titanium nitride is used for the pad parts 120, 121. This makes it possible to manufacture the imaging device 1 by using the first manufacturing method described above.

[0392] The passivation film 122 is provided over the entire surface of the semiconductor layer 100S so as to cover the pad portions 120 and 121 (FIG. 72). The passivation film 122 is made of, for example, a silicon nitride (SiN) film. The interlayer insulating film 123 covers the pad portions 120 and 121 with the passivation film 122 therebetween. This interlayer insulating film 123 is provided over the entire surface of the semiconductor layer 100S. The interlayer insulating film 123 is made of, for example, a silicon oxide (SiO) film. The bonding film 124 is provided on the bonding surface between the first substrate 100 (specifically, the wiring layer 100T) and the second substrate 200. That is, the bonding film 124 is in contact with the second substrate 200. This bonding film 124 is provided over the entire main surface of the first substrate 100. The bonding film 124 is made of, for example, a silicon nitride film.

[0393] The light receiving lens 401 faces, for example, the semiconductor layer 100S with the fixed charge film 112 and the insulating film 111 therebetween (FIG. 72). The light receiving lens 401 is provided, for example, at a position facing the photodiode PD of each of the pixels 541A, 541B, 541C, and 541D.

[0394] The second substrate 200 has a semiconductor layer 200S and a wiring layer 200T in this order from the first substrate 100 side. The semiconductor layer 200S is made of a silicon substrate. In the semiconductor layer 200S, a well region 211 is provided across the thickness direction. The well region 211 is, for example, a p-type semiconductor region. In the second substrate 20, a pixel circuit 210 arranged for each pixel sharing unit 539 is provided. For example, the pixel circuit 210 is provided on the front surface side (the wiring layer 200T side) of the semiconductor layer 200S. In the imaging device 1, the second substrate 200 is bonded to the first substrate 100 such that the back surface side (the semiconductor layer 200S side) of the second substrate 200 faces the front surface side (the wiring layer 100T side) of the first substrate 100. That is, the second substrate 200 is bonded to the first substrate 100 face-to-back.

[0395] 74 to 78 show an example of the planar configuration of the second substrate 200. FIG. 74 shows the configuration of the pixel circuit 210 provided near the surface of the semiconductor layer 200S. FIG. 75 shows the configuration of the wiring layer 200T (specifically, the first wiring layer W1 described later), the semiconductor layer 200S connected to the wiring layer 200T, and each part of the first substrate 100. FIG. 76 to FIG. 78 show an example of the planar configuration of the wiring layer 200T. Hereinafter, the configuration of the second substrate 200 will be described with reference to FIG. 72 and FIG. 74 to FIG. 78. In FIG. 74 and FIG. 75, the outline of the photodiode PD (the boundary between the pixel isolation portion 117 and the photodiode PD) is shown by a dashed line, and the boundary between the semiconductor layer 200S and the element isolation region 213 or the insulating region 214 in the portion overlapping the gate electrode of each transistor constituting the pixel circuit 210 is shown by a dotted line. In the portion overlapping the gate electrode of the amplifying transistor AMP, a boundary between the semiconductor layer 200S and the element isolation region 213 and a boundary between the element isolation region 213 and the insulating region 213 are provided on one side in the channel width direction.

[0396] The second substrate 200 is provided with an insulating region 212 that divides the semiconductor layer 200S, and an element isolation region 213 provided in a part of the semiconductor layer 200S in the thickness direction (FIG. 72). For example, in the insulating region 212 provided between two pixel circuits 210 adjacent to each other in the H direction, the through electrodes 120E, 121E and through electrodes TGV (through electrodes TGV1, TGV2, TGV3, TGV4) of two pixel sharing units 539 connected to the two pixel circuits 210 are arranged (FIG. 75).

[0397] The insulating region 212 has approximately the same thickness as the semiconductor layer 200S (FIG. 72). The semiconductor layer 200S is divided by this insulating region 212. The through electrodes 120E, 121E and the through electrodes TGV are arranged in this insulating region 212. The insulating region 212 is made of, for example, silicon oxide.

[0398] The through electrodes 120E, 121E are provided penetrating the insulating region 212 in the thickness direction. The upper ends of the through electrodes 120E, 121E are connected to the wirings (first wiring W1, second wiring W2, third wiring W3, and fourth wiring W4 described later) of the wiring layer 200T. The through electrodes 120E, 121E are provided penetrating the insulating region 212, the bonding film 124, the interlayer insulating film 123, and the passivation film 122, and the lower ends are connected to the pad parts 120, 121 (FIG. 72). The through electrodes 120E are for electrically connecting the pad part 120 and the pixel circuit 210. That is, the floating diffusion FD of the first substrate 100 is electrically connected to the pixel circuit 210 of the second substrate 200 by the through electrodes 120E. The through electrode 121E is for electrically connecting the pad portion 121 and the reference potential line VSS of the wiring layer 200T. That is, the through electrode 121E electrically connects the VSS contact region 118 of the first substrate 100 to the reference potential line VSS of the second substrate 200.

[0399] The through electrode TGV is provided penetrating the insulating region 212 in the thickness direction. The upper end of the through electrode TGV is connected to the wiring of the wiring 200T. This through electrode TGV is provided penetrating the insulating region 212, the bonding film 124, the interlayer insulating film 123, the passivation film 122, and the interlayer insulating film 119, and its lower end is connected to the transfer gate TG (FIG. 72). Such a through electrode TGV is for electrically connecting the transfer gate TG (transfer gates TG1, TG2, TG3, TG4) of each of the pixels 541A, 541B, 541C, 541D to the wiring of the wiring layer 200T (a part of the row driving signal line 542, specifically, the wirings TRG1, TRG2, TRG3, TRG4 in FIG. 77 described later). That is, the transfer gate TG of the first substrate 100 is electrically connected to the wiring TRG of the second substrate 200 by the through electrode TGV, so that a drive signal is sent to each of the transfer transistors TR (transfer transistors TR1, TR2, TR3, TR4).

[0400] The insulating region 212 is a region for providing the through electrodes 120E, 121E and the through electrodes TGV for electrically connecting the first substrate 100 and the second substrate 200 insulated from the semiconductor layer 200S. For example, the through electrodes 120E, 121E and the through electrodes TGV (through electrodes TGV1, TGV2, TGV3, TGV4) connected to the two pixel circuits 210 (shared units 539) adjacent to each other in the H direction are provided in the insulating region 212 provided between the two pixel circuits 210 (shared units 539). The insulating region 212 is provided, for example, extending in the V direction (FIGS. 74 and 75). Here, the position of the through electrodes TGV in the H direction is arranged closer to the position of the through electrodes 120E, 121E in the H direction than the position of the vertical part TGa by devising the arrangement of the horizontal part TGb of the transfer gate TG (FIGS. 73A and 75). For example, the through electrode TGV is disposed at approximately the same position as the through electrodes 120E, 120E in the H direction. This allows the through electrodes 120E, 121E and the through electrode TGV to be provided together in the insulating region 212 extending in the V direction. As another arrangement example, it is possible to provide the horizontal part TGb only in the region overlapping the vertical part TGa. In this case, the through electrode TGV is formed approximately directly above the vertical part TGa, and the through electrode TGV is disposed, for example, in the approximately center of each pixel 541 in the H direction and the V direction. At this time, the position of the through electrode TGV in the H direction and the position of the through electrodes 120E, 121E in the H direction are largely shifted. For example, an insulating region 212 is provided around the through electrodes TGV and the through electrodes 120E, 121E to electrically insulate them from the adjacent semiconductor layer 200S. When the position of the through electrode TGV in the H direction is significantly separated from the positions of the through electrodes 120E, 121E in the H direction, it is necessary to provide an insulating region 212 independently around each of the through electrodes 120E, 121E, and TGV. This results in the semiconductor layer 200S being divided into small pieces. In contrast, a layout in which the through electrodes 120E, 121E and the through electrode TGV are collectively disposed in the insulating region 212 extending in the V direction can increase the size of the semiconductor layer 200S in the H direction. This makes it possible to secure a large area for the semiconductor element formation region in the semiconductor layer 200S.This makes it possible, for example, to increase the size of the amplification transistor AMP and suppress noise.

[0401] As described with reference to FIG. 70, the pixel sharing unit 539 has a structure in which the floating diffusions FD provided in the respective pixels 541 are electrically connected to each other, and the pixels 541 share one pixel circuit 210. The floating diffusions FD are electrically connected to each other by a pad section 120 provided on the first substrate 100 (FIGS. 72 and 73B). The electrical connection section (pad section 120) provided on the first substrate 100 and the pixel circuit 210 provided on the second substrate 200 are electrically connected to each other via one through electrode 120E. As another structural example, it is also possible to provide the electrical connection section between the floating diffusions FD on the second substrate 200. In this case, the pixel sharing unit 539 is provided with four through electrodes connected to the floating diffusions FD1, FD2, FD3, and FD4, respectively. Therefore, in the second substrate 200, the number of through electrodes penetrating the semiconductor layer 200S increases, and the insulating region 212 that insulates the periphery of these through electrodes becomes larger. In comparison, the structure in which the pad portion 120 is provided in the first substrate 100 (FIGS. 72 and 73B) can reduce the number of through electrodes and make the insulating region 212 smaller. Thus, a large area can be secured for the semiconductor element formation region in the semiconductor layer 200S. This makes it possible, for example, to increase the size of the amplification transistor AMP and suppress noise.

[0402] The element isolation region 213 is provided on the surface side of the semiconductor layer 200S. The element isolation region 213 has an STI (Shallow Trench Isolation) structure. In the element isolation region 213, the semiconductor layer 200S is dug in the thickness direction (perpendicular to the main surface of the second substrate 200), and an insulating film is embedded in the dug portion. The insulating film is made of, for example, silicon oxide. The element isolation region 213 isolates a plurality of transistors constituting the pixel circuit 210 according to the layout of the pixel circuit 210. The semiconductor layer 200S (specifically, the well region 211) extends below the element isolation region 213 (deep in the semiconductor layer 200S).

[0403] Here, with reference to Figures 73A, 73B, and 74, the difference between the outer shape (outer shape in the substrate planar direction) of the pixel sharing unit 539 on the first substrate 100 and the outer shape of the pixel sharing unit 539 on the second substrate 200 will be described.

[0404] In the imaging device 1, a pixel sharing unit 539 is provided across both the first substrate 100 and the second substrate 200. For example, the outer shape of the pixel sharing unit 539 provided on the first substrate 100 and the outer shape of the pixel sharing unit 539 provided on the second substrate 200 are different from each other.

[0405] 73A and 73B, the outlines of the pixels 541A, 541B, 541C, and 541D are indicated by dashed lines, and the outline shape of the pixel sharing unit 539 is indicated by a thick line. For example, the pixel sharing unit 539 of the first substrate 100 is configured with two pixels 541 (pixels 541A and 541B) adjacent to each other in the H direction and two pixels 541 (pixels 541C and 541D) adjacent to each other in the V direction. That is, the pixel sharing unit 539 of the first substrate 100 is configured with four pixels 541 arranged in two rows and two columns adjacent to each other, and the pixel sharing unit 539 of the first substrate 100 has a substantially square outline shape. In the pixel array section 540, such pixel sharing units 539 are arranged adjacent to each other at a two pixel pitch in the H direction (a pitch equivalent to two pixels 541) and at a two pixel pitch in the V direction (a pitch equivalent to two pixels 541).

[0406] In Fig. 74 and Fig. 75, the outlines of the pixels 541A, 541B, 541C, and 541D are indicated by dashed lines, and the outline shape of the pixel sharing unit 539 is indicated by a thick line. For example, the outline shape of the pixel sharing unit 539 of the second substrate 200 is smaller than that of the pixel sharing unit 539 of the first substrate 100 in the H direction, and is larger than that of the pixel sharing unit 539 of the first substrate 100 in the V direction. For example, the pixel sharing unit 539 of the second substrate 200 is formed with a size (area) equivalent to one pixel in the H direction, and is formed with a size equivalent to four pixels in the V direction. That is, the pixel sharing unit 539 of the second substrate 200 is formed with a size equivalent to adjacent pixels arranged in one row x four columns, and the pixel sharing unit 539 of the second substrate 200 has a substantially rectangular outline shape.

[0407] For example, in each pixel circuit 210, the selection transistor SEL, the amplification transistor AMP, the reset transistor RST, and the FD conversion gain switching transistor FDG are arranged in this order in the V direction (FIG. 74). By providing the outer shape of each pixel circuit 210 in a substantially rectangular shape as described above, it is possible to arrange four transistors (the selection transistor SEL, the amplification transistor AMP, the reset transistor RST, and the FD conversion gain switching transistor FDG) in one direction (the V direction in FIG. 74). This allows the drain of the amplification transistor AMP and the drain of the reset transistor RST to be shared in one diffusion region (the diffusion region connected to the power supply line VDD). For example, it is also possible to provide the formation region of each pixel circuit 210 in a substantially square shape (see FIG. 87 described later). In this case, two transistors are arranged along one direction, and it becomes difficult to share the drain of the amplification transistor AMP and the drain of the reset transistor RST in one diffusion region. Therefore, by providing the formation region of the pixel circuit 210 in a substantially rectangular shape, it becomes easier to arrange the four transistors closely to each other, and the formation region of the pixel circuit 210 can be made smaller. That is, the pixel can be miniaturized. Furthermore, when it is not necessary to reduce the formation area of ​​the pixel circuit 210, it is possible to increase the formation area of ​​the amplification transistor AMP and suppress noise.

[0408] For example, in addition to the selection transistor SEL, the amplification transistor AMP, the reset transistor RST, and the FD conversion gain switching transistor FDG, a VSS contact region 218 connected to the reference potential line VSS is provided near the surface of the semiconductor layer 200S. The VSS contact region 218 is, for example, configured of a p-type semiconductor region. The VSS contact region 218 is electrically connected to the VSS contact region 118 of the first substrate 100 (semiconductor layer 100S) via the wiring of the wiring layer 200T and the through electrode 121E. This VSS contact region 218 is provided, for example, at a position adjacent to the source of the FD conversion gain switching transistor FDG with the element isolation region 213 therebetween (FIG. 74).

[0409] Next, with reference to Fig. 73B and Fig. 74, the positional relationship between the pixel sharing unit 539 provided on the first substrate 100 and the pixel sharing unit 539 provided on the second substrate 200 will be described. For example, one of the two pixel sharing units 539 arranged in the V direction of the first substrate 100 (for example, the upper side of the paper in Fig. 73B) is connected to one of the two pixel sharing units 539 arranged in the H direction of the second substrate 200 (for example, the left side of the paper in Fig. 74). For example, the other of the two pixel sharing units 539 arranged in the V direction of the first substrate 100 (for example, the lower side of the paper in Fig. 73B) is connected to the other of the two pixel sharing units 539 arranged in the H direction of the second substrate 200 (for example, the right side of the paper in Fig. 74).

[0410] For example, of two pixel sharing units 539 arranged in the H direction of the second substrate 200, the internal layout (arrangement of transistors, etc.) of one pixel sharing unit 539 is substantially equal to a layout obtained by inverting the internal layout of the other pixel sharing unit 539 in the V direction and H direction. The effects obtained by this layout will be described below.

[0411] In two pixel sharing units 539 aligned in the V direction of the first substrate 100, each pad section 120 is disposed at the center of the outer shape of the pixel sharing unit 539, that is, the center of the pixel sharing unit 539 in the V direction and the H direction (FIG. 73B). On the other hand, since the pixel sharing unit 539 of the second substrate 200 has an outer shape that is substantially rectangular and elongated in the V direction as described above, for example, the amplification transistor AMP connected to the pad section 120 is disposed at a position shifted upward from the center of the pixel sharing unit 539 in the V direction on the paper. For example, when the internal layouts of two pixel sharing units 539 aligned in the H direction of the second substrate 200 are the same, the distance between the amplification transistor AMP of one pixel sharing unit 539 and the pad section 120 (for example, the pad section 120 of the pixel sharing unit 539 on the upper side of the paper in FIG. 73B) becomes relatively short. However, the distance between the amplification transistor AMP of the other pixel sharing unit 539 and the pad section 120 (for example, the pad section 120 of the pixel sharing unit 539 on the lower side of the paper surface of FIG. 73B) becomes longer. Therefore, the area of ​​the wiring required to connect this amplification transistor AMP and the pad section 120 becomes larger, and there is a concern that the wiring layout of the pixel sharing unit 539 becomes complicated. This may affect the miniaturization of the imaging device 1.

[0412] In contrast, by inverting the internal layouts of the two pixel sharing units 539 arranged in the H direction of the second substrate 200 at least in the V direction, the distance between the amplification transistors AMP and the pad section 120 of both of these two pixel sharing units 539 can be shortened. Therefore, compared with a configuration in which the internal layouts of the two pixel sharing units 539 arranged in the H direction of the second substrate 200 are the same, it is easier to miniaturize the imaging device 1. Note that the planar layout of each of the multiple pixel sharing units 539 of the second substrate 200 is symmetrical within the range shown in FIG. 74, but becomes asymmetrical when the layout of the first wiring layer W1 shown in FIG. 75 described later is included.

[0413] In addition, it is preferable that the internal layouts of the two pixel sharing units 539 arranged in the H direction of the second substrate 200 are also inverted with respect to each other in the H direction. The reason for this will be described below. As shown in FIG. 75, the two pixel sharing units 539 arranged in the H direction of the second substrate 200 are connected to the pad portions 120, 121 of the first substrate 100. For example, the pad portions 120, 121 are disposed in the center portions in the H direction of the two pixel sharing units 539 arranged in the H direction of the second substrate 200 (between the two pixel sharing units 539 arranged in the H direction). Therefore, by inverting the internal layouts of the two pixel sharing units 539 arranged in the H direction of the second substrate 200 with respect to each other in the H direction, the distance between each of the multiple pixel sharing units 539 of the second substrate 200 and the pad portions 120, 121 can be reduced. That is, it becomes easier to miniaturize the imaging device 1.

[0414] In addition, the position of the outline of the pixel sharing unit 539 of the second substrate 200 does not have to be aligned with the position of any of the outlines of the pixel sharing unit 539 of the first substrate 100. For example, of the two pixel sharing units 539 arranged in the H direction of the second substrate 200, in one pixel sharing unit 539 (for example, the left side of the paper in FIG. 75), the outline of one side in the V direction (for example, the upper side of the paper in FIG. 75) is disposed outside the outline of one side in the V direction of the corresponding pixel sharing unit 539 of the first substrate 100 (for example, the upper side of the paper in FIG. 73B). In addition, of the two pixel sharing units 539 arranged in the H direction of the second substrate 200, in the other pixel sharing unit 539 (for example, the right side of the paper in FIG. 75), the outline of the other side in the V direction (for example, the lower side of the paper in FIG. 75) is disposed outside the outline of the other side in the V direction of the corresponding pixel sharing unit 539 of the first substrate 100 (for example, the lower side of the paper in FIG. 73B). In this way, by disposing the pixel sharing unit 539 of the second substrate 200 and the pixel sharing unit 539 of the first substrate 100 relative to each other, it is possible to shorten the distance between the amplification transistor AMP and the pad section 120. Therefore, it becomes easier to miniaturize the imaging device 1.

[0415] Furthermore, the positions of the outlines of the multiple pixel sharing units 539 on the second substrate 200 do not need to be aligned with each other. For example, two pixel sharing units 539 aligned in the H direction of the second substrate 200 are arranged with the positions of the outlines in the V direction shifted from each other. This makes it possible to shorten the distance between the amplification transistor AMP and the pad section 120. This makes it easier to miniaturize the imaging device 1.

[0416] With reference to FIG. 73B and FIG. 75, the repeated arrangement of the pixel sharing units 539 in the pixel array section 540 will be described. The pixel sharing unit 539 of the first substrate 100 has a size equivalent to two pixels 541 in the H direction and a size equivalent to two pixels 541 in the V direction (FIG. 73B). For example, in the pixel array section 540 of the first substrate 100, the pixel sharing units 539 having a size equivalent to four pixels 541 are repeatedly arranged adjacent to each other at a two pixel pitch (a pitch equivalent to two pixels 541) in the H direction and at a two pixel pitch (a pitch equivalent to two pixels 541) in the V direction. Alternatively, the pixel array section 540 of the first substrate 100 may be provided with a pair of pixel sharing units 539 in which two pixel sharing units 539 are arranged adjacent to each other in the V direction. In the pixel array section 540 of the first substrate 100, for example, a pair of pixel sharing units 539 are repeatedly arranged adjacent to each other at a two pixel pitch (a pitch equivalent to two pixels 541) in the H direction and a four pixel pitch (a pitch equivalent to four pixels 541) in the V direction. The pixel sharing unit 539 of the second substrate 200 has a size of one pixel 541 in the H direction and a size of four pixels 541 in the V direction ( FIG. 75 ). For example, the pixel array section 540 of the second substrate 200 is provided with a pair of pixel sharing units 539 including two pixel sharing units 539 each having a size equivalent to four pixels 541. The pixel sharing units 539 are arranged adjacent to each other in the H direction and offset from each other in the V direction. In the pixel array section 540 of the second substrate 200, for example, a pair of pixel sharing units 539 are repeatedly arranged adjacent to each other with no gaps at a two pixel pitch (a pitch equivalent to two pixels 541) in the H direction and at a four pixel pitch (a pitch equivalent to four pixels 541) in the V direction. By repeatedly arranging the pixel sharing units 539 in this way, it is possible to arrange the pixel sharing units 539 without any gaps. This makes it easier to miniaturize the imaging device 1.

[0417] It is preferable that the amplification transistor AMP has a three-dimensional structure, such as a Fin type (FIG. 72). This increases the effective gate width, making it possible to suppress noise. The selection transistor SEL, the reset transistor RST, and the FD conversion gain switching transistor FDG have, for example, a planar structure. The amplification transistor AMP may have a planar structure. Alternatively, the selection transistor SEL, the reset transistor RST, or the FD conversion gain switching transistor FDG may have a three-dimensional structure.

[0418] The wiring layer 200T includes, for example, a passivation film 221, an interlayer insulating film 222, and a plurality of wirings (a first wiring layer W1, a second wiring layer W2, a third wiring layer W3, and a fourth wiring layer W4). The passivation film 221 is in contact with, for example, the surface of the semiconductor layer 200S, and covers the entire surface of the semiconductor layer 200S. This passivation film 221 covers the gate electrodes of the selection transistor SEL, the amplification transistor AMP, the reset transistor RST, and the FD conversion gain switching transistor FDG. The interlayer insulating film 222 is provided between the passivation film 221 and the third substrate 300. This interlayer insulating film 222 separates the plurality of wirings (the first wiring layer W1, the second wiring layer W2, the third wiring layer W3, and the fourth wiring layer W4). The interlayer insulating film 222 is made of, for example, silicon oxide.

[0419] In the wiring layer 200T, for example, from the semiconductor layer 200S side, a first wiring layer W1, a second wiring layer W2, a third wiring layer W3, a fourth wiring layer W4, and contact parts 201, 202 are provided in this order, and these are insulated from each other by an interlayer insulating film 222. In the interlayer insulating film 222, a plurality of connection parts are provided to connect the first wiring layer W1, the second wiring layer W2, the third wiring layer W3, or the fourth wiring layer W4 to the layers below them. The connection parts are parts in which a conductive material is embedded in connection holes provided in the interlayer insulating film 222. For example, in the interlayer insulating film 222, a connection part 218V is provided to connect the first wiring layer W1 and the VSS contact region 218 of the semiconductor layer 200S. For example, the hole diameter of such a connection part that connects elements of the second substrate 200 to each other is different from the hole diameters of the through electrodes 120E, 121E and the through electrodes TGV. Specifically, the diameter of the connection hole connecting the elements of the second substrate 200 is preferably smaller than the diameter of the through electrodes 120E, 121E and the through electrode TGV. The reason for this will be described below. The depth of the connection part (connection part 218V, etc.) provided in the wiring layer 200T is smaller than the depth of the through electrodes 120E, 121E and the through electrode TGV. Therefore, the connection part can be filled with a conductive material more easily than the through electrodes 120E, 121E and the through electrode TGV. By making the diameter of the connection part smaller than the diameter of the through electrodes 120E, 121E and the through electrode TGV, it becomes easier to miniaturize the imaging device 1.

[0420] For example, the first wiring layer W1 connects the through electrode 120E to the gate of the amplification transistor AMP and the source of the FD conversion gain switching transistor FDG (specifically, a connection hole reaching the source of the FD conversion gain switching transistor FDG). The first wiring layer W1 connects, for example, the through electrode 121E to the connection portion 218V, thereby electrically connecting the VSS contact region 218 of the semiconductor layer 200S to the VSS contact region 118 of the semiconductor layer 100S.

[0421] Next, the planar configuration of the wiring layer 200T will be described with reference to Figs. 76 to 78. Fig. 76 shows an example of the planar configuration of the first wiring layer W1 and the second wiring layer W2. Fig. 77 shows an example of the planar configuration of the second wiring layer W2 and the third wiring layer W3. Fig. 78 shows an example of the planar configuration of the third wiring layer W3 and the fourth wiring layer W4.

[0422] For example, the third wiring layer W3 includes wirings TRG1, TRG2, TRG3, TRG4, SELL, RSTL, and FDGL extending in the H direction (row direction) (FIG. 77). These wirings correspond to the row driving signal lines 542 described with reference to FIG. 70. The wirings TRG1, TRG2, TRG3, and TRG4 are for sending driving signals to the transfer gates TG1, TG2, TG3, and TG4, respectively. The wirings TRG1, TRG2, TRG3, and TRG4 are connected to the transfer gates TG1, TG2, TG3, and TG4 via the second wiring layer W2, the first wiring layer W1, and the through-electrode 120E, respectively. The wiring SELL is for sending a driving signal to the gate of the selection transistor SEL, the wiring RSTL is for sending a driving signal to the gate of the reset transistor RST, and the wiring FDGL is for sending a driving signal to the gate of the FD conversion gain switching transistor FDG, respectively. The wirings SELL, RSTL, and FDGL are each connected to the gates of the selection transistor SEL, the reset transistor RST, and the FD conversion gain switching transistor FDG via the second wiring layer W2, the first wiring layer W1, and a connection portion.

[0423] For example, the fourth wiring layer W4 includes a power supply line VDD, a reference potential line VSS, and a vertical signal line 543 extending in the V direction (column direction) (FIG. 78). The power supply line VDD is connected to the drain of the amplification transistor AMP and the drain of the reset transistor RST via the third wiring layer W3, the second wiring layer W2, the first wiring layer W1, and a connection part. The reference potential line VSS is connected to the VSS contact region 218 via the third wiring layer W3, the second wiring layer W2, the first wiring layer W1, and a connection part 218V. The reference potential line VSS is also connected to the VSS contact region 118 of the first substrate 100 via the third wiring layer W3, the second wiring layer W2, the first wiring layer W1, the through electrode 121E, and the pad part 121. The vertical signal line 543 is connected to the source (Vout) of the selection transistor SEL via the third wiring layer W3, the second wiring layer W2, the first wiring layer W1, and a connection part.

[0424] The contact parts 201 and 202 may be provided at positions overlapping the pixel array part 540 in a plan view (for example, FIG. 69), or may be provided in the outer peripheral part 540B of the pixel array part 540 (for example, FIG. 72). The contact parts 201 and 202 are provided on the surface of the second substrate 200 (surface on the wiring layer 200T side). The contact parts 201 and 202 are made of metal such as Cu (copper) and Al (aluminum). The contact parts 201 and 202 are exposed on the surface of the wiring layer 200T (surface on the third substrate 300 side). The contact parts 201 and 202 are used for electrical connection between the second substrate 200 and the third substrate 300 and for bonding the second substrate 200 and the third substrate 300 together.

[0425] 72 shows an example in which a peripheral circuit is provided in the peripheral portion 540B of the second substrate 200. This peripheral circuit may include a part of the row driving section 520 or a part of the column signal processing section 550. Also, as shown in FIG. 69, the peripheral circuit may not be arranged in the peripheral portion 540B of the second substrate 200, and the connection holes H1 and H2 may be arranged in the vicinity of the pixel array section 540.

[0426] The third substrate 300 has, for example, a wiring layer 300T and a semiconductor layer 300S in this order from the second substrate 200 side. For example, the surface of the semiconductor layer 300S is provided on the second substrate 200 side. The semiconductor layer 300S is made of a silicon substrate. A circuit is provided on the surface side of the semiconductor layer 300S. Specifically, for example, at least a part of the input unit 510A, the row driver 520, the timing control unit 530, the column signal processing unit 550, the image signal processing unit 560, and the output unit 510B is provided on the surface side of the semiconductor layer 300S. The wiring layer 300T provided between the semiconductor layer 300S and the second substrate 200 includes, for example, an interlayer insulating film, a plurality of wiring layers separated by the interlayer insulating film, and contact units 301 and 302. The contact parts 301 and 302 are exposed on the surface (surface on the second substrate 200 side) of the wiring layer 300T, and the contact part 301 is in contact with the contact part 201 of the second substrate 200, and the contact part 302 is in contact with the contact part 202 of the second substrate 200. The contact parts 301 and 302 are electrically connected to circuits (for example, at least one of the input part 510A, the row driving part 520, the timing control part 530, the column signal processing part 550, the image signal processing part 560, and the output part 510B) formed in the semiconductor layer 300S. The contact parts 301 and 302 are made of metals such as Cu (copper) and aluminum (Al). For example, the external terminal TA is connected to the input part 510A via the connection hole part H1, and the external terminal TB is connected to the output part 510B via the connection hole part H2.

[0427] Here, the features of the imaging device 1 will be described.

[0428] In general, an imaging device mainly consists of a photodiode and a pixel circuit. Increasing the area of ​​the photodiode increases the charge generated as a result of photoelectric conversion, thereby improving the signal-to-noise ratio (S / N ratio) of the pixel signal, and enabling the imaging device to output better image data (image information). On the other hand, increasing the size of the transistors (especially the size of the amplifying transistors) included in the pixel circuit reduces the noise generated in the pixel circuit, thereby improving the S / N ratio of the imaging signal, and enabling the imaging device to output better image data (image information).

[0429] However, in an imaging device in which a photodiode and a pixel circuit are provided on the same semiconductor substrate, if the area of ​​the photodiode is increased within the limited area of ​​the semiconductor substrate, the size of the transistor in the pixel circuit may be reduced, and if the size of the transistor in the pixel circuit is increased, the area of ​​the photodiode may be reduced.

[0430] To solve these problems, for example, the imaging device 1 of the present embodiment uses a structure in which a plurality of pixels 541 share one pixel circuit 210, and the shared pixel circuit 210 is arranged so as to overlap the photodiode PD. This makes it possible to maximize the area of ​​the photodiode PD and to maximize the size of the transistor provided in the pixel circuit 210 within the limited area of ​​the semiconductor substrate. This improves the S / N ratio of the pixel signal, and enables the imaging device 1 to output better image data (image information).

[0431] When realizing a structure in which a plurality of pixels 541 share one pixel circuit 210 and this is arranged to overlap the photodiode PD, a plurality of wirings connected to one pixel circuit 210 extend from the floating diffusion FD of each of the plurality of pixels 541. In order to secure a large area of ​​the semiconductor substrate 200 in which the pixel circuit 210 is formed, for example, a connection wiring can be formed that connects the plurality of extending wirings to each other and combines them into one. Similarly, for the plurality of wirings extending from the VSS contact region 118, a connection wiring can be formed that connects the plurality of extending wirings to each other and combines them into one.

[0432] For example, if a connection wiring that interconnects the multiple wirings extending from the floating diffusion FD of each of the multiple pixels 541 is formed in the semiconductor substrate 200 that forms the pixel circuit 210, it is conceivable that the area for forming the transistors included in the pixel circuit 210 will be reduced. Similarly, if a connection wiring that interconnects the multiple wirings extending from the VSS contact region 118 of each of the multiple pixels 541 and combines them into one is formed in the semiconductor substrate 200 that forms the pixel circuit 210, it is conceivable that the area for forming the transistors included in the pixel circuit 210 will be reduced.

[0433] In order to solve these problems, for example, the imaging device 1 of this embodiment can have a structure in which a plurality of pixels 541 share one pixel circuit 210, and the shared pixel circuit 210 is arranged superimposed on a photodiode PD, and the first substrate 100 can be provided with a connection wiring that interconnects and combines the floating diffusions FD of the plurality of pixels 541, and a connection wiring that interconnects and combines the VSS contact regions 118 provided in each of the plurality of pixels 541.

[0434] Here, when the above-mentioned second manufacturing method is used as a manufacturing method for providing the first substrate 100 with the connection wiring for connecting the floating diffusions FD of the plurality of pixels 541 to one another and the connection wiring for connecting the VSS contact regions 118 of the plurality of pixels 541 to one another, for example, the first substrate 100 and the second substrate 200 can be manufactured using an appropriate process according to the configuration of each substrate, and a high-quality, high-performance imaging device can be manufactured. In addition, the connection wiring of the first substrate 100 and the second substrate 200 can be formed by a simple process. Specifically, when the above-mentioned second manufacturing method is used, an electrode connected to the floating diffusion FD and an electrode connected to the VSS contact region 118 are provided on the surface of the first substrate 100 and the surface of the second substrate 200, which are the bonding interface between the first substrate 100 and the second substrate 200. Furthermore, it is preferable to make the electrodes formed on the surfaces of the two substrates large so that the electrodes can contact each other even if a positional deviation occurs between the electrodes provided on the surfaces of the two substrates when the first substrate 100 and the second substrate 200 are bonded together. In this case, it may become difficult to arrange the electrodes within the limited area of ​​each pixel of the imaging device 1.

[0435] In order to solve the problem of needing a large electrode at the bonding interface between the first substrate 100 and the second substrate 200, for example, the imaging device 1 of this embodiment can use the first manufacturing method described above as a manufacturing method in which a plurality of pixels 541 share one pixel circuit 210 and the shared pixel circuit 210 is arranged so as to overlap the photodiode PD. This makes it easy to align the elements formed on the first substrate 100 and the second substrate 200, respectively, and allows the manufacturing of a high-quality, high-performance imaging device. Furthermore, it is possible to have a unique structure that is generated by using this manufacturing method. That is, the structure has a semiconductor layer 100S and wiring layer 100T of the first substrate 100 and a semiconductor layer 200S and wiring layer 200T of the second substrate 200 stacked in this order, in other words, a structure in which the first substrate 100 and the second substrate 200 are stacked face-to-back, and has through electrodes 120E, 121E that pass from the surface side of the semiconductor layer 200S of the second substrate 200, through the semiconductor layer 200S and the wiring layer 100T of the first substrate 100, and reach the surface of the semiconductor layer 100S of the first substrate 100.

[0436] In a structure in which a first substrate 100 is provided with connection wiring that interconnects and combines the floating diffusions FD of the multiple pixels 541 into one, and connection wiring that interconnects and combines the VSS contact regions 118 of the multiple pixels 541 into one, if this structure is stacked on a second substrate 200 using the first manufacturing method to form a pixel circuit 210 on the second substrate 200, there is a possibility that the influence of the heating process required when forming the active elements provided in the pixel circuit 210 will extend to the connection wiring formed on the first substrate 100.

[0437] Therefore, in order to solve the problem that the connection wiring is affected by the heat treatment when forming the active element, in the imaging device 1 of the present embodiment, it is desirable to use a conductive material with high heat resistance for the connection wiring that connects the floating diffusions FD of the respective pixels 541 to each other and combines them into one, and for the connection wiring that connects the VSS contact regions 118 of the respective pixels 541 to each other and combines them into one. Specifically, the conductive material with high heat resistance can be a material with a higher melting point than at least a part of the wiring material included in the wiring layer 200T of the second substrate 200.

[0438] In this manner, for example, the imaging device 1 of the present embodiment has: (1) a structure in which the first substrate 100 and the second substrate 200 are stacked face-to-back (specifically, a structure in which the semiconductor layer 100S and the wiring layer 100T of the first substrate 100 and the semiconductor layer 200S and the wiring layer 200T of the second substrate 200 are stacked in this order); (2) a structure in which through-electrodes 120E, 121E are provided from the front surface side of the semiconductor layer 200S of the second substrate 200, penetrating the semiconductor layer 200S and the wiring layer 100T of the first substrate 100, and reaching the front surface of the semiconductor layer 100S of the first substrate 100; and (3) a structure in which the floating diffusions FD provided in each of the plurality of pixels 541 are provided. By providing a structure in which the first substrate 100 and the second substrate 200 have a connection wiring that interconnects the floating diffusions FD of the respective pixels 541 and combines them into one, and a connection wiring that interconnects the VSS contact regions 118 of the respective pixels 541 and combines them into one, and a structure in which the connection wiring is formed from a conductive material with high heat resistance, it is possible to provide the first substrate 100 with the connection wiring that interconnects the floating diffusions FD of the respective pixels 541 and combines them into one, and the connection wiring that connects the VSS contact regions 118 of the respective pixels 541 and combines them into one, without providing a large electrode at the interface between the first substrate 100 and the second substrate 200.

[0439] (Operation of imaging device 1) Next, the operation of the imaging device 1 will be described with reference to Figs. 79 and 80. Figs. 79 and 80 are diagrams in which arrows representing the paths of each signal have been added to Fig. 69. Fig. 79 shows the paths of the input signal input from the outside to the imaging device 1, the power supply potential, and the reference potential with arrows. Fig. 80 shows the signal paths of the pixel signals output from the imaging device 1 to the outside with arrows. For example, an input signal (e.g., a pixel clock and a synchronization signal) input to the imaging device 1 via the input section 510A is transmitted to the row driver 520 of the third substrate 300, and a row drive signal is generated in the row driver 520. This row drive signal is sent to the second substrate 200 via the contact sections 301 and 201. Furthermore, this row drive signal reaches each of the pixel shared units 539 of the pixel array section 540 via a row drive signal line 542 in the wiring layer 200T. Among the row driving signals that reach the pixel sharing unit 539 of the second substrate 200, the driving signals other than the transfer gate TG are input to the pixel circuit 210, and each transistor included in the pixel circuit 210 is driven. The driving signal of the transfer gate TG is input to the transfer gates TG1, TG2, TG3, and TG4 of the first substrate 100 via the through electrode TGV, and the pixels 541A, 541B, 541C, and 541D are driven (FIG. 79). In addition, the power supply potential and the reference potential supplied to the input section 510A (input terminal 511) of the third substrate 300 from the outside of the imaging device 1 are sent to the second substrate 200 via the contact sections 301 and 201, and are supplied to the pixel circuits 210 of each pixel sharing unit 539 via the wiring in the wiring layer 200T. The reference potential is also supplied to the pixels 541A, 541B, 541C, and 541D of the first substrate 100 via the through electrode 121E. Meanwhile, pixel signals photoelectrically converted by the pixels 541A, 541B, 541C, and 541D of the first substrate 100 are sent to the pixel circuit 210 of the second substrate 200 for each pixel sharing unit 539 via the through-electrode 120E. A pixel signal based on this pixel signal is sent from the pixel circuit 210 to the third substrate 300 via the vertical signal line 543 and the contact units 202 and 302. This pixel signal is processed by the column signal processing unit 550 and the image signal processing unit 560 of the third substrate 300, and then output to the outside via the output unit 510B.

[0440] [effect] In this embodiment, the pixels 541A, 541B, 541C, and 541D (pixel sharing unit 539) and the pixel circuit 210 are provided on different substrates (first substrate 100 and second substrate 200). This allows the areas of the pixels 541A, 541B, 541C, and 541D and the pixel circuit 210 to be enlarged compared to when the pixels 541A, 541B, 541C, and 541D and the pixel circuit 210 are formed on the same substrate. As a result, it is possible to increase the amount of pixel signals obtained by photoelectric conversion and reduce the transistor noise of the pixel circuit 210. This improves the signal-to-noise ratio of the pixel signals, and the imaging device 1 can output better pixel data (image information). In addition, it is possible to miniaturize the imaging device 1 (in other words, reduce the pixel size and make the imaging device 1 smaller). The imaging device 1 can increase the number of pixels per unit area by reducing the pixel size, and output a high-quality image.

[0441] In addition, in the imaging device 1, the first substrate 100 and the second substrate 200 are electrically connected to each other by the through electrodes 120E, 121E provided in the insulating region 212. For example, a method of connecting the first substrate 100 and the second substrate 200 by bonding pad electrodes to each other, or a method of connecting by through wiring (for example, TSV (Thorough Si Via)) that penetrates a semiconductor layer can be considered. Compared to such methods, by providing the through electrodes 120E, 121E in the insulating region 212, the area required for connecting the first substrate 100 and the second substrate 200 can be reduced. This reduces the pixel size, and the imaging device 1 can be made more compact. In addition, the resolution can be increased by further miniaturizing the area per pixel. When it is not necessary to reduce the chip size, the formation area of ​​the pixels 541A, 541B, 541C, 541D and the pixel circuit 210 can be expanded. As a result, it is possible to increase the amount of pixel signals obtained by photoelectric conversion and reduce noise in the transistors provided in the pixel circuits 210. This improves the signal-to-noise ratio of the pixel signals, enabling the imaging device 1 to output better pixel data (image information).

[0442] Furthermore, in the imaging device 1, the pixel circuit 210, the column signal processing section 550, and the image signal processing section 560 are provided on different substrates (the second substrate 200 and the third substrate 300). This allows the area of ​​the pixel circuit 210 and the areas of the column signal processing section 550 and the image signal processing section 560 to be enlarged compared to a case in which the pixel circuit 210, the column signal processing section 550, and the image signal processing section 560 are formed on the same substrate. This allows noise generated in the column signal processing section 550 to be reduced, and allows the image signal processing section 560 to be equipped with a more advanced image processing circuit. This improves the signal-to-noise ratio of the pixel signal, and enables the imaging device 1 to output better pixel data (image information).

[0443] In the imaging device 1, the pixel array section 540 is provided on the first substrate 100 and the second substrate 200, and the column signal processing section 550 and the image signal processing section 560 are provided on the third substrate 300. The contact sections 201, 202, 301, and 302 that connect the second substrate 200 and the third substrate 300 are formed above the pixel array section 540. Therefore, the contact sections 201, 202, 301, and 302 can be freely laid out without being interfered with in the layout by various wirings provided in the pixel array. This makes it possible to use the contact sections 201, 202, 301, and 302 for electrical connection between the second substrate 200 and the third substrate 300. By using the contact sections 201, 202, 301, and 302, for example, the column signal processing section 550 and the image signal processing section 560 have a high degree of freedom in layout. This makes it possible to reduce noise generated in the column signal processing unit 550 and to incorporate a more advanced image processing circuit in the image signal processing unit 560. Therefore, the signal-to-noise ratio of the pixel signals is improved, and the imaging device 1 can output better pixel data (image information).

[0444] Furthermore, in the imaging device 1, the pixel separator 117 penetrates the semiconductor layer 100S. This makes it possible to suppress color mixing between the pixels 541A, 541B, 541C, and 541D even if the distance between adjacent pixels (pixels 541A, 541B, 541C, and 541D) is reduced due to miniaturization of the area per pixel. This improves the signal-to-noise ratio of the pixel signal, enabling the imaging device 1 to output better pixel data (image information).

[0445] Furthermore, in the imaging device 1, a pixel circuit 210 is provided for each pixel sharing unit 539. This allows the formation area of ​​the transistors (amplification transistor AMP, reset transistor RST, selection transistor SEL, FD conversion gain switching transistor FDG) that constitute the pixel circuit 210 to be larger than when a pixel circuit 210 is provided for each of the pixels 541A, 541B, 541C, and 541D. For example, by increasing the formation area of ​​the amplification transistor AMP, it is possible to suppress noise. This improves the signal-to-noise ratio of the pixel signal, and enables the imaging device 1 to output better pixel data (image information).

[0446] Furthermore, in the imaging device 1, the pad section 120 that electrically connects the floating diffusions FD (floating diffusions FD1, FD2, FD3, FD4) of the four pixels (pixels 541A, 541B, 541C, 541D) is provided on the first substrate 100. This makes it possible to reduce the number of through electrodes (through electrodes 120E) that connect the first substrate 100 and the second substrate 200, compared to the case where such a pad section 120 is provided on the second substrate 200. Therefore, it is possible to reduce the insulating region 212 and ensure a sufficient size of the formation region (semiconductor layer 200S) of the transistors that constitute the pixel circuit 210. This makes it possible to reduce noise of the transistors provided in the pixel circuit 210, improve the signal-to-noise ratio of the pixel signal, and enable the imaging device 1 to output better pixel data (image information).

[0447] The following describes modified examples of the imaging device 1 according to the above-described embodiment 7. In the following modified examples, components common to the above-described embodiment 7 are denoted by the same reference numerals.

[0448] (Variation 1) 81 to 85 show a modified example of the planar configuration of the imaging device 1 according to the seventh embodiment. FIG. 81 shows a schematic planar configuration of the vicinity of the surface of the semiconductor layer 200S of the second substrate 200, and corresponds to FIG. 74 described in the seventh embodiment. FIG. 82 shows a schematic configuration of the first wiring layer W1 and the semiconductor layer 200S and each part of the first substrate 100 connected to the first wiring layer W1, and corresponds to FIG. 75 described in the seventh embodiment. FIG. 83 shows an example of the planar configuration of the first wiring layer W1 and the second wiring layer W2, and corresponds to FIG. 76 described in the seventh embodiment. FIG. 84 shows an example of the planar configuration of the second wiring layer W2 and the third wiring layer W3, and corresponds to FIG. 77 described in the seventh embodiment. FIG. 85 shows an example of the planar configuration of the third wiring layer W3 and the fourth wiring layer W4, and corresponds to FIG. 78 described in the seventh embodiment.

[0449] In this modification, as shown in Fig. 82, of two pixel sharing units 539 arranged in the H direction of the second substrate 200, the internal layout of one pixel sharing unit 539 (e.g., the right side of the paper) is configured to be inverted only in the H direction from the internal layout of the other pixel sharing unit 539 (e.g., the left side of the paper). Also, the deviation in the V direction between the outline of one pixel sharing unit 539 and the outline of the other pixel sharing unit 539 is larger than the deviation (Fig. 75) described in the seventh embodiment above. In this way, by increasing the deviation in the V direction, it is possible to reduce the distance between the amplification transistor AMP of the other pixel sharing unit 539 and the pad section 120 connected ...

Claims

1. a first semiconductor substrate having a photoelectric conversion element; a second semiconductor substrate facing the first semiconductor substrate via an insulating film; Equipped with The second semiconductor substrate comprises: a first region of a first conductivity type on a second main surface opposite to the first main surface, and the first region is grounded via the first region; the second semiconductor substrate is disposed with the second main surface side facing the first semiconductor substrate, the first region is located below the amplifying transistor and covers a part of the second main surface but not the entire second main surface; a contact that connects the first region of the second semiconductor substrate and the first semiconductor substrate; Solid-state imaging element.

2. The first region is located directly below the amplification transistor. The solid-state imaging device according to claim 1 .

3. The amplifying transistor has a source region and a drain region provided in the second semiconductor substrate, the second semiconductor substrate further includes a second region separating the source region and the drain region and having a higher resistance than the first region; The first region is in contact with the second region and is located directly below the second region. The solid-state imaging device according to claim 2 .

4. the contact connects the first region of the second semiconductor substrate and a semiconductor region of the first semiconductor substrate; 4. The solid-state imaging device according to claim 1.

5. The first semiconductor substrate comprises: a transfer transistor provided in the semiconductor region and configured to transfer the electrical signal output from the photoelectric conversion element to the amplification transistor; The contact is connecting the first region of the second semiconductor substrate and the semiconductor region of the first semiconductor substrate to each other while avoiding the transfer transistor; The solid-state imaging device according to claim 4 .

6. a first contact connected to the transfer transistor; A wiring provided above the amplifying transistor; Further equipped with the first contact connects the transfer transistor and the wiring; The solid-state imaging device according to claim 5 .

7. the first contact extends adjacent to the amplifying transistor; The solid-state imaging device according to claim 6 .

8. a second contact connected to the amplifying transistor; the second contact connects the amplifying transistor and the wiring; The solid-state imaging device according to claim 6 .

9. the semiconductor region of the first semiconductor substrate includes a contact layer; the contact connects the first region of the second semiconductor substrate and the contact layer; The solid-state imaging device according to claim 4 .

Images