Semiconductor Device

Abstract

To provide a fine transistor, a transistor with small parasitic capacitance, a transistor with high frequency characteristics, and a method for manufacturing a semiconductor device having the transistor.SOLUTION: In a method for manufacturing a semiconductor device having first to third openings, the first to third openings are formed by performing first etching and second etching. The first etching includes etching a first insulator 408 to form the first to third openings, the second etching includes etching an insulator 410, an insulator 412, an insulator 406c, an insulator 402, an electron capture layer 303, an insulator 302, and a conductor 310b to form the first opening, etching the insulator 410, the insulator 412, the insulator 406c, and a conductor 416a1 to form the second opening, and etching the insulator 410, the insulator 412, the insulator 406c, and a conductor 416a2 to form the third opening.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to, for example, a transistor and a semiconductor device, and a method for manufacturing the same. Alternatively, the present invention may be applied to, for example, a display device, a light-emitting device, a lighting device, a power storage device, a storage device, a processor, or a display device, a liquid crystal display device, a light-emitting device, a storage device, The present invention relates to a method for manufacturing an electronic device, a semiconductor device, a display device, a liquid crystal display device, and a light-emitting device. The present invention relates to a memory device and a method for driving an electronic device.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. The technical field of one aspect relates to an article, a method, or a manufacturing method. One aspect of the present invention is a process, machine, manufacture, or composition. It is about the nature of matter.

[0003] In this specification and the like, a semiconductor device is a device that can function by utilizing semiconductor characteristics. Display devices, light-emitting devices, lighting devices, electro-optical devices, semiconductor circuits, and electronic devices may include a semiconductor device. [Background technology]

[0004] In recent years, transistors using oxide semiconductors have been attracting attention. Since the film can be formed by a deposition method, it is possible to form the semiconductor of the transistor that constitutes a large display device. In addition, a transistor using an oxide semiconductor can be used in an amorphous silicon It is possible to improve and use some of the production equipment for transistors using Another benefit is reduced investment.

[0005] In addition, a transistor including an oxide semiconductor has an extremely low leakage current in an off-state. For example, it is known that the leakage current of a transistor using an oxide semiconductor is low. A low-power CPU that utilizes this characteristic has been disclosed (see Patent Document 1). .

[0006] In addition, a transistor using an oxide semiconductor is manufactured by embedding a gate electrode in an opening. Methods for this purpose have been disclosed (see Patent Documents 2 and 3). [Prior art documents] [Patent documents]

[0007] [Patent Document 1] JP 2012-257187 A [Patent Document 2] JP 2014-241407 A [Patent Document 3] JP 2014-240833 A Summary of the Invention [Problem to be solved by the invention]

[0008] One of the objects is to provide a fine transistor. One of the objectives is to provide a transistor with high frequency characteristics. Another object of the present invention is to provide a transistor having favorable electrical characteristics. Another object of the present invention is to provide a transistor having stable electrical characteristics. Another object of the present invention is to provide a transistor with a small current when off. Another object of the present invention is to provide a novel transistor. Another object of the present invention is to provide a semiconductor device having a high operating speed. Another object of the present invention is to provide a novel semiconductor device. Another object of the present invention is to provide a module including the semiconductor device. It is an object of the present invention to provide an electronic device having the semiconductor device or the module. do.

[0009] The description of these problems does not preclude the existence of other problems. It is not necessary for the embodiment to solve all of these problems. The above will become apparent from the description in the specification, drawings, claims, etc. It is possible to extract other issues from the descriptions in the patent, claims, etc. [Means for solving the problem]

[0010] (1) One aspect of the present invention is a method for manufacturing a semiconductor device comprising: a first insulator; a second insulator on the first insulator; and a second insulator on the second insulator. a buried first conductor and a third insulator on the second insulator and on the first conductor; a first metal oxide on the third insulator, a fourth insulator on the first metal oxide, and a fourth insulator on the fourth insulator. A fifth insulator on the insulator, an oxide semiconductor on the fifth insulator, and a second conductor on the oxide semiconductor. on the fourth insulator, on the second conductor, on the third conductor and on the acid A sixth insulator on the oxide semiconductor, a seventh insulator on the sixth insulator, and a third insulator on the seventh insulator. a fourth conductor, a second metal oxide on the sixth insulator and on the fourth conductor, and a second metal The eighth insulator on oxide, the eighth insulator, the second metal oxide, the seventh insulator, the sixth insulator through the edge, the fourth insulator, the first metal oxide and the third insulator to the first conductor. a first opening including an eighth insulator, a second metal oxide, a seventh insulator, and a sixth insulator; a second opening through the eighth insulator and the second metal oxide to the second conductor; a third opening passing through the first opening and reaching a fourth conductor, A fifth conductor is deposited on the eighth insulator, a ninth insulator is deposited on the fifth conductor, and a ninth A resist mask is formed on the insulator by lithography, and the ninth insulator and the A part of the fifth conductor is etched to form a ninth insulator and a hard disk having the fifth conductor. A hard mask layer is formed, and the first etching and the second etching are performed using the hard mask layer as a mask. By performing etching, a first opening, a second opening and a third opening are formed, and the first Etching the eighth insulator to form a first opening, and etching the second Etch the eighth insulator to form an opening, and etch the third insulator to form an opening. , an eighth etch of the insulator, and a second etch to form the first opening; The second metal oxide, the seventh insulator, the sixth insulator, the fourth insulator, the first metal oxide and and etching the second metal oxide, the first insulator, and the third insulator to form a second opening. The seventh insulator and the sixth insulator are etched to form a third opening. This is a method for manufacturing a semiconductor device by etching a metal oxide.

[0011] (2) Alternatively, one aspect of the present invention is a first conductor, a second conductor, a third conductor and a fourth conductor. The semiconductor device according to (1), characterized in that the conductor is a film of a conductor having the same conductor. This is a method for producing the above.

[0012] (3) Alternatively, one aspect of the present invention is a first conductor, a second conductor, a third conductor, a fourth conductor and the fifth conductor is characterized in that a conductor having the same conductor is formed as a film (1). A method for manufacturing the semiconductor device according to (2).

[0013] (4) Alternatively, in one aspect of the present invention, in the first etching step, a ninth insulator is etched. The etching rate of the eighth insulator is lower than the etching rate of the eighth insulator (1) to (3). ) is a method for manufacturing a semiconductor device according to the present invention.

[0014] (5) Alternatively, in one aspect of the present invention, in the first etching step, the etching of the second metal oxide The etching rate of the eighth insulator is lower than the etching rate of the eighth insulator (1) to (5). A method for manufacturing the semiconductor device according to (4).

[0015] (6) Alternatively, in one aspect of the present invention, in the second etching step, the fourth conductor is etched. The etching rate of the first metal oxide is lower than the etching rates of the second metal oxide. The present invention relates to a method for manufacturing a semiconductor device, comprising the steps of:

[0016] (7) Alternatively, one aspect of the present invention is a semiconductor device comprising a first insulator, a second insulator on the first insulator, and a second A first conductor embedded in an insulator and a third insulator on the second insulator and on the first conductor. a first metal oxide on the third insulator; and a fourth insulator on the first metal oxide. A fifth insulator on the fourth insulator, an oxide semiconductor on the fifth insulator, and a A second conductor and a third conductor, and a fourth insulator, a second conductor, and a third conductor. and a sixth insulator on the oxide semiconductor, a seventh insulator on the oxide semiconductor, and a seventh insulator. an eighth insulator on the body, a fourth conductor on the eighth insulator, and a seventh insulator on the sixth insulator; a ninth insulator on the conductor, the eighth insulator and the fourth conductor, and a second insulator on the ninth insulator. a metal oxide, a tenth insulator on the second metal oxide, and a tenth insulator on the second metal oxide. oxide, ninth insulator, sixth insulator, fourth insulator, first metal oxide and third insulator a first opening through the first insulating material, a second metal oxide, and a third insulating material; a second opening passing through the ninth insulator and the sixth insulator to the second conductor; a third opening through the insulator, the second metal oxide, and the ninth insulator to the fourth conductor; A method for manufacturing a semiconductor device having a tenth insulator, comprising: forming a fifth conductor on the tenth insulator. Then, an eleventh insulator is formed on the fifth conductor, and a lithography method is used to form a film on the eleventh insulator. A resist mask is then formed, and a portion of the eleventh insulator and the fifth conductor is etched. A hard mask layer having an eleventh insulator and a fifth conductor is formed by etching the hard mask layer. The first etching and the second etching are performed using the mask layer as a mask, thereby forming a first forming a first opening, a second opening and a third opening, the first etching forming the first opening etch the tenth insulator to form a second opening; Etch the tenth insulator to form a third opening. and a second etch is performed to form a first opening, a second metal oxide, and a first The ninth insulator, the sixth insulator, the fourth insulator, the first metal oxide and the third insulator are etched. and forming a second opening by etching a second metal oxide, a ninth insulator, and a sixth insulator. 3. Etch the insulator of the second metal oxide and the ninth metal oxide to form a third opening. The present invention relates to a method for manufacturing a semiconductor device, in which an insulator is etched.

[0017] (8) Alternatively, one aspect of the present invention is a first conductor, a second conductor, a third conductor and a fourth conductor. The semiconductor device according to (7), characterized in that the conductor is a film of a conductor having the same conductor. This is a method for producing the above.

[0018] (9) Alternatively, one aspect of the present invention is a first conductor, a second conductor, a third conductor, a fourth conductor and the fifth conductor is characterized in that a conductor having the same conductor is deposited (7). A method for manufacturing the semiconductor device according to (8).

[0019] (10) Alternatively, in one aspect of the present invention, in the first etching step, the etch of the eleventh insulator is The etching rate of the insulating material is lower than the etching rate of the insulating material of the tenth embodiment. A method for manufacturing the semiconductor device according to (9).

[0020] (11) Alternatively, in one aspect of the present invention, in the first etching step, the etching of the second metal oxide The etching rate of the tenth insulator is lower than that of the tenth insulator. The present invention relates to a method for manufacturing a semiconductor device.

[0021] (12) Alternatively, in one aspect of the present invention, in the second etching step, the fourth conductor is etched. The etching rate of the first metal oxide is lower than the etching rates of the second metal oxide. The method for manufacturing a semiconductor device according to any one of (7) to (11) above is characterized in that:

[0022] In the method for manufacturing a semiconductor device according to one embodiment of the present invention, the oxide semiconductor may be replaced with another semiconductor. It is acceptable to replace it with. Effect of the Invention

[0023] It is possible to provide a fine transistor or a transistor with a small parasitic capacitance. Alternatively, a transistor having high frequency characteristics can be provided. Alternatively, a transistor having good electrical characteristics can be provided. It is possible to provide a stable transistor. Or, it is possible to provide a transistor with a small current when off. Alternatively, a novel transistor can be provided. Alternatively, a semiconductor device having the transistor can be provided. It is possible to provide a fast semiconductor device. Alternatively, it is possible to provide a novel semiconductor device. Alternatively, a module having the semiconductor device can be provided. It is possible to provide a semiconductor device or an electronic device having the module.

[0024] The description of these effects does not preclude the existence of other effects. An embodiment does not necessarily have all of these effects. Effects other than these may be included in the description, This is self-evident from the description in the specification, drawings, claims, etc. It is possible to extract other effects from any of the descriptions. [Brief description of the drawings]

[0025] [Figure 1] 1A and 1B are a top view and a cross-sectional view illustrating a transistor according to one embodiment of the present invention. [Diagram 2] 1A and 1B are a top view and a cross-sectional view illustrating a transistor according to one embodiment of the present invention. [Diagram 3] 1A and 1B are a top view and a cross-sectional view illustrating a transistor according to one embodiment of the present invention. [Figure 4] 1A and 1B are a top view and a cross-sectional view illustrating a transistor according to one embodiment of the present invention. [Diagram 5] FIG. 1 is a cross-sectional view illustrating a part of a transistor according to one embodiment of the present invention. [Figure 6] FIG. 1 is a cross-sectional view illustrating a transistor according to one embodiment of the present invention. [Figure 7] Cs-corrected high-resolution TEM image of a cross section of CAAC-OS, and a schematic cross-sectional diagram of CAAC-OS. [Figure 8] Cs-corrected high-resolution TEM image of the CAAC-OS in the plane. [Figure 9] 13A to 13C show structural analyses of a CAAC-OS and a single-crystal oxide semiconductor by XRD. [Figure 10] Electron diffraction pattern of CAAC-OS. [Figure 11] FIG. 1 shows the change in the crystal part of an In-Ga-Zn oxide due to electron irradiation. [Figure 12] 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a transistor according to one embodiment of the present invention. [Figure 13] 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a transistor according to one embodiment of the present invention. [Figure 14] 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a transistor according to one embodiment of the present invention. [Figure 15] 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a transistor according to one embodiment of the present invention. [Figure 16] 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a transistor according to one embodiment of the present invention. [Figure 17] 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a transistor according to one embodiment of the present invention. [Figure 18] 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a transistor according to one embodiment of the present invention. [Figure 19] 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a transistor according to one embodiment of the present invention. [Figure 20] 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a transistor according to one embodiment of the present invention. [Figure 21] 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a transistor according to one embodiment of the present invention. [Figure 22] 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a transistor according to one embodiment of the present invention. [Figure 23] 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a transistor according to one embodiment of the present invention. [Figure 24] 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a transistor according to one embodiment of the present invention. [Diagram 25] 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a transistor according to one embodiment of the present invention. [Figure 26] 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a transistor according to one embodiment of the present invention. [Figure 27] 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a transistor according to one embodiment of the present invention. [Figure 28] 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a transistor according to one embodiment of the present invention. [Figure 29] 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a transistor according to one embodiment of the present invention. [Diagram 30] 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a transistor according to one embodiment of the present invention. [Diagram 31] 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a transistor according to one embodiment of the present invention. [Diagram 32] 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a transistor according to one embodiment of the present invention. [Diagram 33] 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a transistor according to one embodiment of the present invention. [Diagram 34]1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a transistor according to one embodiment of the present invention. [Diagram 35] 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a transistor according to one embodiment of the present invention. [Diagram 36] 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a transistor according to one embodiment of the present invention. [Figure 37] 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a transistor according to one embodiment of the present invention. [Figure 38] 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a transistor according to one embodiment of the present invention. [Figure 39] 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a transistor according to one embodiment of the present invention. [Diagram 40] 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a transistor according to one embodiment of the present invention. [Diagram 41] 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a transistor according to one embodiment of the present invention. [Diagram 42] 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a transistor according to one embodiment of the present invention. [Diagram 43] 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a transistor according to one embodiment of the present invention. [Diagram 44] 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a transistor according to one embodiment of the present invention. [Diagram 45] 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a transistor according to one embodiment of the present invention. [Diagram 46] 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a transistor according to one embodiment of the present invention. [Figure 47] 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a transistor according to one embodiment of the present invention. [Figure 48] FIG. 1 is a circuit diagram of a memory device according to one embodiment of the present invention. [Figure 49] FIG. 1 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. [Figure 50] FIG. 1 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. [Figure 51]1A and 1B are a circuit diagram and a cross-sectional view illustrating a semiconductor device of one embodiment of the present invention. [Figure 52] FIG. 2 is a block diagram showing a CPU according to an embodiment of the present invention. [Diagram 53] FIG. 1 is a circuit diagram of a memory element according to one embodiment of the present invention. [Figure 54] FIG. [Figure 55] FIG. 2 is a plan view showing pixels of the imaging device. [Figure 56] FIG. [Figure 57] FIG. [Figure 58] FIG. 2 is a diagram for explaining an example of the configuration of an RF tag. [Figure 59] 1A to 1C are a circuit diagram, a top view, and a cross-sectional view illustrating a semiconductor device according to the present invention. [Figure 60] 1A and 1B are a circuit diagram and a cross-sectional view showing a semiconductor device according to the present invention; [Figure 61] FIG. 2 is a diagram illustrating a display module. [Figure 62] FIG. 1 is a perspective view showing a cross-sectional structure of a package using a lead frame type interposer. [Figure 63] 1A to 1C are diagrams illustrating electronic devices according to one embodiment of the present invention. [Figure 64] 1A to 1C are diagrams illustrating electronic devices according to one embodiment of the present invention. [Figure 65] 1A to 1C are diagrams illustrating electronic devices according to one embodiment of the present invention. [Figure 66] 1 shows an example of the use of an RF tag according to the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0026] The present invention will be described in detail with reference to the drawings. The present invention is not limited to the above, and various modifications in form and detail can be easily made by those skilled in the art. It is understood that the present invention should not be construed as being limited to the description of the following embodiments. In explaining the configuration of the invention using the drawings, the same reference numerals are used in different The hatch pattern is used in common among drawings. In some cases, no particular symbol is attached.

[0027] In the figures, the size, thickness of the film (layer), or area is exaggerated for clarity. There may be cases where

[0028] In this specification, the shape of an object may be expressed, for example, as a "diameter," "particle size," "size," or "diameter." When specifying the size or width of an object, the length of one side of the smallest cube that the object can fit into, or may be read as the equivalent circle diameter in a cross section of an object. refers to the diameter of a perfect circle whose area is equal to that of a cross-section of an object.

[0029] Note that a voltage is a voltage between a certain potential and a reference potential (such as the ground potential (GND) or source potential). Therefore, it is possible to say "voltage" as "potential". .

[0030] The ordinal numbers such as 1st and 2nd are used for convenience and do not indicate the order of steps or stacking. Therefore, for example, "the first" should not be changed to "the second" or "the third" etc. In addition, the ordinal numbers described in this specification and the like can be replaced with the following words: The ordinal numbers used to identify an aspect of the present invention may not be consistent.

[0031] The impurities in a semiconductor are, for example, those other than the main components that make up the semiconductor. For example, Elements with a concentration of less than 0.1 atomic percent are considered impurities. The formation of DOS (Density of State) in the body and the carrier mobility In some cases, the semiconductor may become an oxide semiconductor, or the crystallinity may decrease. In the case of a semiconductor, impurities that change the properties of the semiconductor include, for example, Group 1 elements, Group 2 elements, Elements, Group 14 elements, Group 15 elements, transition metals other than the main component, etc., in particular, for example, Hydrogen (also found in water), lithium, sodium, silicon, boron, phosphorus, carbon, nitrogen In the case of oxide semiconductors, for example, oxygen vacancies are formed due to the inclusion of impurities such as hydrogen. In addition, if the semiconductor is a silicon film, there may be a defect that changes the properties of the semiconductor. The pure substances include, for example, oxygen, Group 1 elements excluding hydrogen, Group 2 elements, Group 13 elements, and Group 1 elements. Group 5 elements, etc.

[0032] Note that the channel length is, for example, the length of a semiconductor (or transistor) in a top view of a transistor. When the transistor is on, the gate electrode (the part of the semiconductor through which current flows) overlaps with the The source region or source potential in the region where the This refers to the distance between the drain (drain region or drain electrode) and the In a transistor, the channel length does not necessarily have the same value in all regions. The channel length of each transistor may not be determined to a single value. In the document, the channel length is defined as any one value, maximum value, or The minimum or average value.

[0033] The channel width is the width of the semiconductor (or transistor) when it is in the on state. The region where the current flows and the gate electrode overlap, or the region where the channel is formed. This refers to the length of the part where the source and drain face each other in the region. In a transistor, the channel width does not necessarily have the same value in all regions. The channel width of each transistor may not be determined to be a single value. In the document, the channel width is defined as any one value, maximum value, or The minimum or average value.

[0034] Depending on the structure of the transistor, the channel in the region where the channel is actually formed may vary. The effective channel width (hereinafter referred to as the effective channel width) shown in the top view of the transistor The channel width (hereinafter referred to as the apparent channel width) may be different. For example, In a transistor having a three-dimensional structure, the effective channel width is The effect of the channel width becomes larger than the apparent channel width shown in For example, in transistors with a fine, three-dimensional structure, In some cases, the ratio of the channel formation region to the total area may be increased. The effective channel width is smaller than the apparent channel width shown by the The width will be larger.

[0035] By the way, in a transistor having a three-dimensional structure, the effective channel width is For example, it may be difficult to estimate the effective channel width from the design value. In order to obtain this, it is necessary to assume that the shape of the semiconductor is known. Unless k is precisely known, it is difficult to accurately measure the effective channel width.

[0036] In this specification, therefore, in a top view of a transistor, a semiconductor and a gate electrode are not mutually connected. The apparent length of the overlapping area between the source and drain The channel width of the In this specification, it is sometimes referred to as the "channel width". In some cases, this may refer to the enclosed channel width or apparent channel width; or In this specification, when simply referring to a channel width, it may refer to an effective channel width. In addition, the channel length, channel width, effective channel width, apparent channel width, and enclosure The width of the inclusion channel can be determined by acquiring a cross-sectional TEM image and analyzing the image. Thus, the value can be determined.

[0037] In addition, the field effect mobility of the transistor and the current value per channel width are calculated. In some cases, the effective channel width is calculated using the enclosed channel width. The value may differ from that calculated using the channel width.

[0038] In this specification, when it is stated that A has a shape protruding from B, it is to be understood that the shape is not limited to a top view. or in a cross-sectional view, at least one end of A is outside at least one end of B. Therefore, it may be described as having a shape in which A protrudes more than B. For example, in the top view, one end of A is outside one end of B. It can be read as having.

[0039] In this specification, "parallel" means that the angle between two straight lines is between -10° and 10°. Therefore, it includes the case where the angle is between -5° and 5°. "Perpendicular" means that two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, this also includes cases where the angle is between 85° and 95°.

[0040] In this specification, when the crystal is a trigonal or rhombohedral crystal, it is represented as a hexagonal crystal system. .

[0041] (Embodiment 1) <Transistor structure 1> A structure of a transistor included in a semiconductor device according to one embodiment of the present invention will be described below. do.

[0042] 1A, 1B, and 1C are a top view and a cross-sectional view of a semiconductor device according to one embodiment of the present invention. FIG. 1(A) is a top view. FIG. 1(B) is a cross-sectional view of the one-dot chain line A1 shown in FIG. 1(A). FIG. 1(C) is a cross-sectional view corresponding to the dashed line A3-A4 shown in FIG. 1(A). 1A is a top view of the corresponding cross-sectional view. Note that in the top view of FIG. 1A, some elements are omitted for clarity. is omitted in the figure.

[0043] In FIG. 1B and FIG. 1C, the transistor includes an insulator 401 on a substrate 400; An insulator 301 on an insulator 401, the insulator 301 having an opening, and a conductive layer in the opening The insulator 301 and the conductor 310a and the conductor 310b are disposed on the insulator 301 and and an insulator 302 on the conductor 310b, an electron trapping layer 303 on the insulator 302, and an electron trapping layer 304 on the conductor 310b. An insulator 402 on the layer 303, an insulator 406a on the insulator 402, and an insulator 406a on the insulator 406a. a semiconductor 406b, a conductor 416a1 having a region in contact with the top surface of the semiconductor 406b, and The conductor 416a2, the insulator 402, the side surface of the insulator 406a, the side surface of the semiconductor 406b, The upper surface of the semiconductor 406b, the side surface of the conductor 416a1, the upper surface of the conductor 416a1, and the conductor 41 an insulator 406c having an area in contact with the side surface of the conductor 416a2 and the top surface of the conductor 416a2; The insulator 412 on the edge 406c and the semiconductor 406b overlap each other via the insulator 412. A conductor 404 having a region, an insulator 408 on the insulator 412 and on the conductor 404; An insulator 410 on the insulator 408, an insulator 410, an insulator 408, an insulator 412, an insulator 406c, through the insulator 402, the electron capture layer 303 and the insulator 302 to the conductor 310b. a first opening that reaches the insulator 410, the insulator 408, the insulator 412, and the insulator 406; A second opening through the insulator 410, the insulator 408, the insulator a third opening through the body 412 and the insulator 406c to the conductor 416a2; 410 and a fourth opening through the insulator 408 to the conductor 404; and the first opening, The conductor 433 and the conductor 431 are embedded in the second opening, the third opening, and the fourth opening. , the conductor 429, the conductor 437, and the area in contact with the conductor 433 on the insulator 410 are A conductor 434 having a region in contact with the conductor 431 on the insulator 410 and a conductor 43 2, a conductor 430 having an area in contact with the conductor 429 on the insulator 410, and an insulator 41 0 and a conductor 438 having an area in contact with the conductor 437 on the substrate 431.

[0044] The cross-sectional shape of the opening according to the embodiment of the present invention is shown in FIGS. 5(A), (B) and (C) are schematic diagrams showing the opening of the transistor shown in FIG. FIG. 5(A) is an enlarged cross-sectional view of a portion of the first opening. FIG. FIG. 5(B) shows an enlarged view of the second opening, and FIG. 5(C) shows an enlarged view of the fourth opening. For convenience, the thickness direction of the insulator 410 is shown thin.

[0045] The cross-sectional shape of the opening shown in Fig. 1(B) and (C) is a straight line, but Fig. 5(A) As shown in (B) and (C), the openings are located above, below, above or below the opening diameter. The layer may have a shape having a wider portion, narrower portion or constricted portion than the layer on which it is placed. The first opening shown in FIG. 5A includes an insulator 410, an insulator 412, an insulator 402, and an insulator 413. The opening diameter of the edge 302 is wider than the layers above, below, above or below it. In other words, the opening diameters of the insulator 408, the insulator 406c and the electron capture layer 303 are The insulator 408, the insulator 406c and the electron trapping layer 408 are narrower than the underlying layers. The opening of the capture layer 303 is constricted. In the second opening shown in FIG. 5(B), the insulator 410 and The opening diameter of the insulator 412 is wider than the layers above, below, or underneath it. In other words, the opening diameters of the insulators 408 and 406c are located above, below, or above the Alternatively, the opening diameter of the insulator 408 and the insulator 406c is narrower than that of the layer in which the insulator 408 is placed. In the fourth opening shown in FIG. 5C, the opening diameter of the insulator 410 is located below the opening. In other words, the opening diameter of the insulator 408 is wider than the layer above it. Or the opening diameter of the insulator 408 is narrower than that of the insulator 408. , the etching rate of the insulator 410 is higher than that of the insulator 406a and the electron trapping layer 303. In the case where the etching rates of the insulators 412, 402, and 302 are high, It may have a shape like this.

[0046] In addition, at the bottom of the opening in FIG. 5B, a part of the upper surface of the conductor 416a1 is recessed. This is because the time required for the first opening to be formed is different from the time required for the second opening to be formed. During the time from when the second opening is formed to when the first opening is formed, the conductor 416a1 This is because the conductor 416a1 is over-etched and a part of the conductor 416a1 is etched. Similarly, at the bottom of the opening in FIG. 5C, a part of the upper surface of the conductor 404 is recessed. This is because the time required for the first opening to be formed is different from the time required for the fourth opening to be formed. During the time from when the fourth opening is formed to when the first opening is formed, the conductor 404 is over. This is because the conductor 404 is partially etched. In (B) and (C), the diameter of the opening is wider than the layers above and below it. The figures show examples of the recesses in the conductive film, but the size of the spreading parts and the recesses in the conductive film varies. This is not limited to this.

[0047] The semiconductor 406b is connected to the upper surface of the semiconductor 406b, the conductor 416a1, and the conductor 416 a2.

[0048] In this transistor, the conductor 404 functions as a first gate electrode. The conductor 404 may have a laminated structure with a conductor having a function of being difficult to permeate oxygen. For example, by forming a conductive material that is difficult for oxygen to pass through as a lower layer, the oxidation of the conductive material 404 can be prevented. The increase in electrical resistance can be prevented. The insulator 412 functions as a gate insulator. do.

[0049] The conductor 416a1 and the conductor 416a2 serve as a source electrode and a drain electrode. In addition, the conductor 416a1 and the conductor 416a2 have a function of preventing oxygen from passing through. For example, a conductive material that is difficult for oxygen to pass through can be used as a laminated structure. By forming a film on the upper layer, the electric resistance due to oxidation of the conductor 416a1 and the conductor 416a2 is reduced. The electrical resistance of a conductor can be measured using the two-terminal method, etc. It can be measured by

[0050] The resistance of the semiconductor 406b can be controlled by applying a potential to the conductor 404. That is, the potential applied to the conductor 404 causes the conductor 416a1 and the conductor 416a2 to It is possible to control the conduction or non-conduction between the electrodes.

[0051] As shown in FIGS. 1B and 1C, the top surface of the semiconductor 406b is covered with a conductor 416a1 and a The conductor 401a functions as a first gate electrode. The electric field of 4 can electrically surround the insulator 406a and the semiconductor 406b. The structure of a transistor that electrically surrounds the semiconductor by the electric field of the gate electrode is called su This is called a rounded channel (s-channel) structure. In some cases, a channel is formed throughout the entire body 406b. A large current can flow between the source and drain of the transistor, and the current when it is conductive (on-current) In addition, the insulator 406a and the semiconductor 406b can increase the Since it is surrounded by the electric field of 4, the current when it is not conducting (off current) is small. It is possible.

[0052] The conductor 310a also functions as a second gate electrode. a may be a multi-layer film including a conductive film having a function of being difficult to permeate oxygen. By forming a multi-layer film including a conductive film having a function of being difficult to pass through, the conductive material 310a is prevented from being oxidized. The insulator 302, the electron trapping layer 303 and the insulator 402 are It functions as a second gate insulating film. The threshold voltage of the transistor can be controlled. The threshold voltage of the transistor is controlled by injecting electrons into the electron trap layer 303 using the potential. Furthermore, by electrically connecting the first gate electrode and the second gate electrode, In addition, the function of the first gate electrode is The functions of the first gate electrode and the second gate electrode may be interchanged.

[0053] FIG. 6(A) shows an example in which the first gate electrode and the second gate electrode are electrically connected. The opening through the body 410 to the conductor 404 has a conductor 440 embedded therein. The upper surface of the conductor 440 and the conductor 444 formed on the insulator 410 are electrically connected. On the other hand, the insulators 410, 408, 412, 406c, and 402 The opening through the electron capture layer 303 and the insulator 302 to the conductor 310c has a conductor The conductive body 442 is embedded in the conductive body 444, and the upper surface of the conductive body 442 and the conductive body 444 are electrically connected to each other. That is, the conductor 404 having the function of the first gate electrode is 40, the conductor 444 and the conductor 442 function as a second gate electrode. The conductor 310c is electrically connected to the conductor 310a.

[0054] The transistor is made of an insulator that has a function of blocking impurities such as hydrogen and oxygen. By surrounding the transistor with an insulator, the electrical characteristics of the transistor can be stabilized. 408 is an insulator that has the function of blocking impurities such as hydrogen and oxygen. Good.

[0055] Examples of insulators that have the function of blocking impurities such as hydrogen and oxygen include boron. Element, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, Argon, Gallium, Germanium, Yttrium, Zirconium, Lanthanum, Neodymium Insulators containing hafnium or tantalum may be used in a single layer or in a multilayer.

[0056] For example, the insulator 408 may be aluminum oxide, magnesium oxide, or gallium oxide. , germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide metal oxides such as oxydimium, hafnium oxide or tantalum oxide, silicon oxide nitride or Silicon nitride or the like may be used. Note that the insulator 408 may contain aluminum oxide. For example, the insulator 408 can be formed by using a plasma containing oxygen. Oxygen can be added to the insulator 412 that is the underlayer of 408. The added oxygen acts as an insulating The insulator 408 has aluminum oxide, which results in excess oxygen in the insulator 412. It is possible to prevent impurities such as hydrogen from being mixed into the body 406b. The insulator 408 has aluminum oxide, so that the excess acid added to the insulator 412 described above can be The out-diffusion of elements can be reduced.

[0057] The insulator 401 may be aluminum oxide, magnesium oxide, silicon nitride oxide, or nitride. Silicon, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, acid Lanthanum oxide, neodymium oxide, hafnium oxide or tantalum oxide may be used. The insulator 401 preferably comprises aluminum oxide or silicon nitride. The insulator 401 includes aluminum oxide or silicon nitride, so that the semiconductor 406b In addition, for example, the insulator 40 can be prevented from being contaminated by impurities such as hydrogen. The aluminum oxide or silicon nitride in the first layer reduces outward diffusion of oxygen. This can be done.

[0058] The insulator 301 may be, for example, boron, carbon, nitrogen, oxygen, fluorine, magnesium, or aluminium. Aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium , zirconium, lanthanum, neodymium, hafnium or tantalum, For example, the insulator 301 may be silicon oxide or oxide. It is preferable to have silicon nitride.

[0059] The electron capture layer 303 may include, for example, boron, carbon, nitrogen, oxygen, fluorine, or magnesium. , aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium Insulators containing tungsten, zirconium, lanthanum, neodymium, hafnium or tantalum For example, a metal oxide film may be used as the electron capture layer 303. Preferably, the layer comprises silicon nitride, hafnium oxide or aluminum oxide.

[0060] The insulators 302 and 402 may include, for example, boron, carbon, nitrogen, oxygen, and fluorine. , magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium tungsten, yttrium, zirconium, lanthanum, neodymium, hafnium or tantalum For example, the insulator 402 may be an oxide film. It is preferred that the layer comprises silicon oxynitride or silicon oxynitride.

[0061] It is preferable that the insulator 410 has a low dielectric constant. 410 is silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, fluorine silicon oxide doped with , silicon oxide doped with carbon, silicon oxide doped with carbon and nitrogen It is preferable that the material includes silicon, silicon oxide having voids, or resin. Alternatively, The insulator 410 may be silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, Fluorine-doped silicon oxide, carbon-doped silicon oxide, carbon and nitrogen-doped silicon oxide The laminated structure may include a silicon oxide layer or a silicon oxide layer having voids, and a resin layer. Silicon oxide and silicon oxynitride are preferred because they are thermally stable and can be easily combined with resin. By combining these resins, it is possible to obtain a laminated structure that is thermally stable and has a low relative dielectric constant. For example, polyester, polyolefin, polyamide (nylon, aramid, etc.) , polyimide, polycarbonate or acrylic.

[0062] The insulator 412 may be, for example, boron, carbon, nitrogen, oxygen, fluorine, magnesium, or aluminium. Aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium , zirconium, lanthanum, neodymium, hafnium or tantalum, For example, the insulator 412 may be a silicon oxide or an oxide film. It is preferable to have silicon nitride.

[0063] It is preferable that the insulator 412 has a high relative dielectric constant. For example, 412 is a gallium oxide, hafnium oxide, and oxide with aluminum and hafnium. oxide nitrides with aluminum and hafnium, oxide nitrides with silicon and hafnium It is preferred to have a silicon oxide having hafnium or an oxide nitride having silicon and hafnium. Alternatively, the insulator 412 may be a material having a dielectric constant of silicon oxide or silicon oxynitride. It is preferable to have a laminate structure of silicon oxide and silicon oxynitride. Since PO is thermally stable, it can be combined with an insulator with a high dielectric constant to produce a thermally stable Moreover, it is possible to obtain a laminated structure with a high relative dielectric constant. By having hafnium oxide or silicon oxide on the insulator 406c side, It is possible to prevent silicon contained in silicon nitride from being mixed into the semiconductor 406b. In addition, for example, silicon oxide or silicon oxynitride can be used on the insulator 406c side. Thus, aluminum oxide, gallium oxide or hafnium oxide and silicon oxide or A trap center may be formed at the interface with the silicon oxynitride. The center shifts the threshold voltage of the transistor in the positive direction by capturing electrons. It may be possible.

[0064] The conductor 416a1 and the conductor 416a2 may include, for example, boron, nitrogen, oxygen, fluorine, etc. Elements, silicon, phosphorus, aluminum, titanium, chromium, manganese, cobalt, nickel, Copper, zinc, gallium, yttrium, zirconium, molybdenum, ruthenium, platinum A single layer of conductor containing one or more of silver, indium, tin, tantalum and tungsten. For example, an alloy film or a compound film may be used, and an aluminum film may be used. Conductors containing copper and titanium, conductors containing copper and manganese, indium Conductors containing titanium, tin and oxygen, or conductors containing titanium and nitrogen, etc. good.

[0065] Conductor 310a, Conductor 310b, Conductor 310c, Conductor 404, Conductor 429, Conductor Conductor 430, conductor 431, conductor 432, conductor 433, conductor 434, conductor 437, The conductor 438, the conductor 440, the conductor 442, and the conductor 444 may be, for example, Uron, nitrogen, oxygen, fluorine, silicon, phosphorus, aluminum, titanium, chromium, manganese , Cobalt, Nickel, Copper, Zinc, Gallium, Yttrium, Zirconium, Molybdenum Conductive material containing one or more of ruthenium, silver, indium, tin, tantalum and tungsten The film may be a single layer or a laminate. For example, the film may be an alloy film or a compound film. Conductors containing aluminum, conductors containing copper and titanium, conductors containing copper and manganese Conductors containing indium, tin and oxygen, or titanium and nitrogen. Either may be used.

[0066] Conductor 429, Conductor 430, Conductor 431, Conductor 432, Conductor 433, Conductor 43 4. The conductor 437 and the conductor 438 may be, for example, boron, nitrogen, oxygen, fluorine, Silicon, phosphorus, aluminum, titanium, chromium, manganese, cobalt, nickel, copper, Zinc, gallium, yttrium, zirconium, molybdenum, ruthenium, silver, indium Conductors containing one or more of aluminum, tin, tantalum and tungsten are used in a single layer or multilayer. For example, an alloy film or a compound film may be used, and a conductor containing aluminum, Conductors containing copper and titanium, conductors containing copper and manganese, conductors containing indium, tin and A conductor containing oxygen, or a conductor containing titanium and nitrogen, etc. may also be used.

[0067] The semiconductor 406b is preferably an oxide semiconductor. (including silicon), germanium, silicon germanium, silicon carbide, gallium arsenide, Aluminum gallium arsenide, indium phosphide, gallium nitride, or organic semiconductors There are cases where this is acceptable.

[0068] The insulator 406a and the insulator 406c are formed of an element other than oxygen that constitutes the semiconductor 406b. It is preferable to use an oxide composed of one or more elements, or two or more elements. Silicon (including distorted silicon), germanium, silicon germanium, silicon carbide, gallium aluminum gallium arsenide, indium phosphide, gallium nitride or organic semiconductor etc. may be used.

[0069] <Transistor structure 2> Here, a transistor having a different structure from that shown in FIG. 1 will be described with reference to FIG. 2. 1A, 1B, and 1C are a top view and a cross-sectional view of a semiconductor device according to one embodiment of the present invention. FIG. 2(A) is a top view. FIG. 2(B) is a cross-sectional view of the cross-section of the dashed line A1-A2 shown in FIG. 2(A). 2(C) is a corresponding cross-sectional view of the dashed line A3-A4 shown in FIG. In the top view of FIG. 2(A), some elements are omitted for clarity. Illustrated.

[0070] As shown in FIGS. 2(A), (B) and (C), a first gate electrode The conductor 404 and the conductor 416a1 function as a source electrode or a drain electrode. The area where there is no overlapping area with the area where the function of the 416a2 is the same as that shown in FIG. This is different from the configuration of a transistor.

[0071] A conductor 404 functions as a first gate electrode and a conductor 405 functions as a source electrode. The conductive layer 416a1 and the conductive layer 416a2 functioning as a drain electrode are overlapped with each other. Since the conductor 404 does not have a region, the conductor 404 functions as a gate electrode and the source electrode a conductor 416a1 functioning as a drain electrode or a conductor 416 Since there is no parasitic capacitance between the electrodes of a2, this is favorable for high-speed operation of the transistor. A conductor 404 having a function as a gate electrode and a conductor 405 having a function as a source electrode The current between the two electrodes of the body 416a1 or the drain electrode 416a2 is For other configurations, please refer to the above.

[0072] <Transistor structure 3> Here, a transistor having a different structure from that shown in FIG. 2 will be described with reference to FIG. 3. 1A, 1B, and 1C are a top view and a cross-sectional view of a semiconductor device according to one embodiment of the present invention. FIG. 3(A) is a top view. FIG. 3(B) is a cross-sectional view of the cross-section of the dashed line A1-A2 shown in FIG. 3(A). 3(C) is a corresponding cross-sectional view of the dashed line A3-A4 shown in FIG. In the top view of FIG. 3(A), some elements are omitted for clarity. Illustrated.

[0073] As shown in FIGS. 3A, 3B, and 3C, a conductor 41 having a function as a source electrode is provided. 6a1 or the conductor 416a2 having a function as a drain electrode, and a region 407a1 having a function as a drain region or a region 40 7a2, the insulator 410, the insulator 408, the insulator 412, the region 407a1 and the semiconductor An opening extending through body 406b to insulator 406a, insulator 410, insulator 408, insulator An opening is formed through the body 412, the region 407a2, and the semiconductor 406b to the insulator 406a. The difference from the transistor configuration shown in FIG. Please take the above into consideration.

[0074] <Transistor structure 4> Here, a transistor having a different structure from that shown in FIG. 1 will be described with reference to FIG. 4. 1A, 1B, and 1C are a top view and a cross-sectional view of a semiconductor device according to one embodiment of the present invention. FIG. 4(A) is a top view. FIG. 4(B) is a cross-sectional view of the cross-section of the dashed line A1-A2 shown in FIG. 4(A). 4(C) is a corresponding cross-sectional view of the dashed line A3-A4 shown in FIG. In the top view of FIG. 4(A), some elements are omitted for clarity. Illustrated.

[0075] In FIG. 4B and FIG. 4C, the transistor includes an insulator 401 on a substrate 400; An insulator 301 on an insulator 401, the insulator 301 having an opening, and a conductive layer in the opening The insulator 301 and the conductor 310a and the conductor 310b are disposed on the insulator 301 and and an insulator 302 on the conductor 310b, an electron trapping layer 303 on the insulator 302, and an electron trapping layer 304 on the conductor 310b. An insulator 402 on the layer 303, an insulator 406a on the insulator 402, and an insulator 406a on the insulator 406a. a semiconductor 406b, a conductor 416a1 having a region in contact with the top surface of the semiconductor 406b, and The conductor 416a2 and the insulators in contact with the upper surface of the conductor 416a1 and the upper surface of the conductor 416a2 The insulator 406c contacts the upper surface of the semiconductor 406b, and the insulating layer 406b on the insulator 406c. The insulating layer 412 is disposed on the semiconductor 406b via the insulating layer 412 and the insulating layer 406c. A conductor 404, an insulator 410, a conductor 404, an insulator 412, and a conductor 404. insulator 418 on top, insulator 408 on insulator 418, and insulator 428 on insulator 408 , the insulator 428, the insulator 408, the insulator 418, the insulator 410, the insulator 402, the electron trap A first opening passes through the trap layer 303 and the insulator 302 to the conductor 310b, and a second opening passes through the insulator 4. 28, through insulator 408, insulator 418 and insulator 410 to conductor 416a1 Through the second opening, through the insulator 428, the insulator 408, the insulator 418 and the insulator 410 A third opening reaching the conductor 416a2 and an insulator 428, an insulator 408 and an insulator 440 are formed. 18 to the conductor 404; and the first opening, the second opening, the third opening, The opening, the conductor 433 embedded in the fourth opening, the conductor 431, the conductor 429, and and a conductor 437, and a conductor 434 having an area in contact with the conductor 433 on the insulator 428. A conductor 432 having a region in contact with the conductor 431 on the insulator 428, and a conductor 432 on the insulator 428 A conductor 430 having an area in contact with the conductor 429, and a conductor 437 on the insulator 428. and a conductor 438 having a contacting region.

[0076] The cross-sectional shape of the opening according to the embodiment of the present invention is shown in FIGS. 5(D), (E) and (F). 5(D), (E) and (F) show the openings of the transistor shown in FIG. FIG. 5(D) is an enlarged cross-sectional view of the first opening. FIG. 5(E) shows an enlarged view of the second opening, and FIG. 5(F) shows an enlarged view of the fourth opening. For convenience, the thickness direction of the insulator 410 is shown thin.

[0077] The cross-sectional shape of the opening shown in Fig. 4(B) and (C) is a straight line, but in Fig. 5(D), As shown in (E) and (F), the openings are positioned above, below, above or below the opening diameter. The layer may have a shape having a wider portion, narrower portion or constricted portion than the layer on which it is placed. In the first opening shown in FIG. 5D, the insulator 428, the insulator 418, the insulator 410, and the insulator The opening diameter of the body 402 and the insulator 302 is different from the layers located above and below it. In other words, the opening diameter of the insulator 408 and the electron capture layer 303 is also enlarged. or the openings in the insulator 408 and the electron-trapping layer 303 are narrower than the underlying layers. In the second opening shown in FIG. 5(E), the insulator 428, the insulator 418, and The opening diameter of the insulator 410 is wider than the layers located above and below it. In other words, the opening diameter of the insulator 408 is narrower than the layers above and below it. Alternatively, the opening of the insulator 408 is constricted. In the fourth opening shown in FIG. 5(F), 428 and the opening diameter of the insulator 418 is wider than the layer located above or below it. In other words, the opening diameter of the insulator 408 is narrower than the layers above and below it. Alternatively, the opening of the insulator 408 is constricted. This is because the insulator 408 and the electron capture layer 3 Compared to the etching rate of 03, the insulator 428, the insulator 418, the insulator 410, the insulator This shape occurs when the etching rates of the substrate 402 and the insulator 302 are high. There is.

[0078] In addition, the bottom of the opening in FIG. 5(E) is a recess in the upper surface of the conductor 416a1. The time required for forming the first opening and the time required for forming the second opening are different from each other. During the time from when the second opening is formed to when the first opening is formed, the conductor 416a1 is over This is because the conductor 416a1 is partially etched away. 5(F) The bottom of the opening is partially recessed from the upper surface of the conductor 404. This is the first opening. The time for forming the fourth opening is different from the time for forming the fourth opening. During the time from when the first opening is formed to when the first opening is formed, the conductor 404 is over-etched. This is because a part of the conductor 404 is etched. ) shows an example of an opening portion having a larger diameter than the layers above and below it, or a conductive film recess. However, the size of the spreading portion and the recessed portion in the conductive film are not limited to this.

[0079] The semiconductor 406b is connected to the upper surface of the semiconductor 406b, the conductor 416a1, and the conductor 416 a2.

[0080] In this transistor, the conductor 404 functions as a first gate electrode. The conductor 404 may have a laminated structure with a conductor having a function of being difficult to permeate oxygen. For example, by forming a conductive material that is difficult for oxygen to pass through as a lower layer, the oxidation of the conductive material 404 can be prevented. The increase in electrical resistance can be prevented. The insulator 412 functions as a gate insulator. do.

[0081] The conductor 416a1 and the conductor 416a2 serve as a source electrode and a drain electrode. In addition, the conductor 416a1 and the conductor 416a2 have a function of preventing oxygen from passing through. For example, a conductive material that is difficult for oxygen to pass through can be used as a laminated structure. By forming a film on the upper layer, the electric resistance due to oxidation of the conductor 416a1 and the conductor 416a2 is reduced. This can prevent an increase in resistance.

[0082] The resistance of the semiconductor 406b can be controlled by applying a potential to the conductor 404. That is, the potential applied to the conductor 404 causes the conductor 416a1 and the conductor 416a2 to It is possible to control the conduction or non-conduction between the electrodes.

[0083] In this transistor, a region functioning as a gate electrode is formed of an insulator 410 or the like. Since it is formed in a self-aligned manner to fill the opening, SA s-channel FET(Trench Gate Self Align It can also be called an s-channel FET.

[0084] In FIG. 4B, the bottom surface of the conductor 404 having a function as a gate electrode is insulated from the insulator 4 The length of the region facing parallel to the upper surface of the semiconductor 406b through the insulator 406c is The gate line width is defined as the width of the opening of the insulator 410 that reaches the semiconductor 406b. That is, the gate line width can be made smaller than the minimum processing dimension. Specifically, the gate line width is set to 5 nm or more and 60 nm or less, preferably 5 nm or more. It can be 30 nm or less.

[0085] If the electric field from the gate electrode is blocked by another conductor, the transistor will switch In this transistor, the insulator 406c and the insulator 412 The positional relationship between the conductor 404, the conductor 416a1, and the conductor 416a2 is determined by the thickness of the conductor 404. That is, the conductor 416 having the function of the source electrode and the drain electrode is a1 and the thickness of the conductor 416a2 and the insulator 412 functioning as a gate insulating film It is understood that the film thickness influences the electrical characteristics of the transistor.

[0086] In FIG. 4B, the insulator 4 in the region between the conductor 416a1 and the conductor 416a2 12 is set to be equal to or smaller than the thickness of the conductor 416a1 or the thickness of the conductor 416a2, The electric field from the gate electrode is applied to the entire channel formation region, so the transistor operates well. It is more preferable that the insulator 412 in the region between the conductor 416a1 and the conductor 416a2 is The thickness is set to 30 nm or less, preferably 10 nm or less.

[0087] In addition, the structure of this transistor is different depending on the thickness of the conductor 416a1 or the thickness of the conductor 416a2. The end of the conductor 416a1 is connected to the insulator 406c and the insulator 406b. The conductor 416a has an area facing the conductor 404 through the edge 412. The end of the second electrode 402 faces the conductor 404 through the insulator 406c and the insulator 412. However, the area of ​​these regions is smaller. The parasitic capacitance of these regions is kept small.

[0088] The conductor 310a also functions as a second gate electrode. a may be a multi-layer film including a conductive film having a function of being difficult to permeate oxygen. By forming a multi-layer film including a conductive film having a function of being difficult to pass through, the conductive material 310a is prevented from being oxidized. The insulator 302, the electron trapping layer 303 and the insulator 402 are It functions as a second gate insulating film. The threshold voltage of the transistor can be controlled. The threshold voltage of the transistor is controlled by injecting electrons into the electron trap layer 303 using the potential. Furthermore, by electrically connecting the first gate electrode and the second gate electrode, In addition, the function of the first gate electrode is The functions of the first gate electrode and the second gate electrode may be interchanged.

[0089] FIG. 6B shows an example in which the first gate electrode and the second gate electrode are electrically connected. The opening through the body 428, the insulator 408, and the insulator 418 to the conductor 404 includes: The conductor 440 is embedded, and a conductive layer is formed on the upper surface of the conductor 440 and on the insulator 428. On the other hand, the insulator 428, the insulator 408, and the insulator 444 are electrically connected to each other. 18, conduction through the insulator 410, the insulator 402, the electron capture layer 303 and the insulator 302 A conductor 442 is embedded in the opening that reaches the body 310c. and the conductor 444 are electrically connected. That is, the function of the first gate electrode The conductor 404 having the first through the conductor 440, the conductor 444 and the conductor 442. The second gate electrode 310c is electrically connected to the second conductor 310c which functions as the second gate electrode.

[0090] The insulators 418 and 428 may include, for example, boron, carbon, nitrogen, oxygen, and fluorine. , magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium tungsten, yttrium, zirconium, lanthanum, neodymium, hafnium or tantalum For example, the insulator 301 may be an oxide film. It is preferable that the silicon oxide layer has silicon oxynitride or silicon oxynitride. For other configurations, refer to the above. do.

[0091] Note that one embodiment of the present invention has been described in this embodiment. An embodiment of the present invention will be described below. However, the embodiment of the present invention is not limited to these. That is, various inventive aspects are described in this and other embodiments. Therefore, one embodiment of the present invention is not limited to a specific embodiment. For example, a channel formation region of a transistor may include an oxide semiconductor. Although an example in which a transistor includes an oxide semiconductor has been described, one embodiment of the present invention is In some cases, or depending on the circumstances, various aspects of the present invention may be used. The transistors may comprise a variety of semiconductors. Therefore, various transistors in one embodiment of the present invention may be made of, for example, silicon, germanium, , silicon germanium, silicon carbide, gallium arsenide, aluminum gallium arsenide, At least one of indium phosphide, gallium nitride, or organic semiconductors may be included. Alternatively, for example, in some cases or depending on the circumstances, Various transistors do not necessarily include an oxide semiconductor.

[0092] This embodiment may be appropriately combined with at least a part of other embodiments described in this specification. It can be implemented together.

[0093] (Embodiment 2) <Structure of oxide semiconductor> The structure of an oxide semiconductor will be described below.

[0094] Oxide semiconductors are classified into single-crystal oxide semiconductors and non-single-crystal oxide semiconductors. As a non-single-crystal oxide semiconductor, CAAC-OS (C Axis Aligned Crystalline Oxide Semiconductor, polycrystalline oxide semiconductor Conductor, nc-OS (nanocrystalline oxide semiconductor) ctor), pseudo-amorphous oxide semiconductor (a-like OS: amorphous li ke oxide semiconductor), and amorphous oxide semiconductor.

[0095] From another point of view, the oxide semiconductor is classified into an amorphous oxide semiconductor and a crystalline oxide semiconductor other than the amorphous oxide semiconductor. Crystalline oxide semiconductors are classified into single crystal oxide semiconductors, CAAC-O S, polycrystalline oxide semiconductor, and nc-OS.

[0096] The definition of an amorphous structure is generally that it is not fixed in a metastable state and is isotropic. It is known that the bond angles are flexible and the bond length is short. In other words, it is a structure that has order but does not have long-range order.

[0097] On the other hand, in the case of an essentially stable oxide semiconductor, It cannot be called an oxide semiconductor. The oxide semiconductor (for example, having a periodic structure in a microscopic region) is transformed into a completely amorphous oxide. It cannot be called a semiconductor. However, a-like OS is a periodic Although it has a structure, it has voids and is an unstable structure. Its physical properties are similar to those of an amorphous oxide semiconductor.

[0098] <caac-os> First, let me explain about CAAC-OS.

[0099] CAAC-OS is an oxide semiconductor that has multiple crystal parts (also called pellets) aligned along the c-axis. It is a conductor.

[0100] Transmission Electron Microscope (TEM) A composite analysis image (high resolution) of the bright-field image and the diffraction pattern of CAAC-OS was obtained by using a scope. When observing the high-resolution TEM image, multiple pellets can be confirmed. In the high-resolution TEM image, the boundaries between the pellets, i.e., grain boundaries, are not clearly visible. Therefore, it is not possible to clearly confirm the presence of the CAAC-OS. Therefore, it can be said that the decrease in electron mobility caused by the above phenomenon is unlikely to occur.

[0101] The following describes the CAAC-OS observed by TEM. The high-resolution TEM image of the cross section of CAAC-OS observed from a direction approximately parallel to the sample surface is shown. For high-resolution TEM image observation, spherical aberration correction is required. The spherical aberration corrector function was used. The acquisition of Cs-corrected high-resolution TEM images is carried out by, for example, This is carried out using an atomic resolution analytical electron microscope such as the JEM-ARM200F manufactured by Denshi Co., Ltd. can be done.

[0102] An enlarged Cs-corrected high-resolution TEM image of region (1) in Figure 7(A) is shown in Figure 7(B). From (B), it can be seen that the metal atoms are arranged in layers in the pellet. The arrangement of each atomic layer is determined by the surface on which the CAAC-OS film is formed (also called the surface on which the film is formed). It reflects the unevenness of the surface and is parallel to the surface on which the CAAC-OS is formed or the top surface.

[0103] As shown in Figure 7(B), CAAC-OS has a characteristic atomic arrangement. The characteristic atomic arrangement is shown by auxiliary lines. The size of each pellet can be 1 nm or more or 3 nm or more. It can be seen that the size of the gap caused by the inclination with the target is about 0.8 nm. The pellets may also be referred to as nanocrystals (nc). CAAC-OS, CANC(C-Axis Aligned nanocrystal The semiconductor may also be referred to as an oxide semiconductor having a structure including a metal oxide layer.

[0104] Here, based on the Cs-corrected high-resolution TEM image, the pellet of CAAC-OS on the substrate 5120 was The layout of the 5100 is shown diagrammatically as a stack of bricks or blocks. (See FIG. 7(D)). The inclination between the pellets observed in FIG. 7(C) The location where this occurs corresponds to the region 5161 shown in FIG.

[0105] In addition, Fig. 8(A) shows the Cs compensation of the plane of the CAAC-OS observed from a direction almost perpendicular to the sample surface. The positive high-resolution TEM images are enlarged views of areas (1), (2), and (3) in Fig. 8(A). The Cs-corrected high-resolution TEM images are shown in Fig. 8(B), Fig. 8(C), and Fig. 8(D), respectively. As shown in Fig. 8(B), Fig. 8(C) and Fig. 8(D), the pellet has metal atoms arranged in a triangular shape. However, it can be seen that the different pentagons are arranged in a square, rectangular or hexagonal shape. There is no regularity in the arrangement of metal atoms between the reds.

[0106] Next, the CA analyzed by X-ray diffraction (XRD) Explain AC-OS. For example, InGaZnO 4 CAAC-OS with crystals of When structural analysis is performed using the out-of-plane method, the result is as shown in Figure 9(A). A peak may appear at a diffraction angle (2θ) of around 31°. This peak is due to the InGaZn O 4 Since the crystal orientation of CAAC-OS is attributed to the (009) plane of the crystal, it is considered that the crystal of CAAC-OS has a c-axis orientation. It can be seen that the c-axis is oriented in a direction substantially perpendicular to the surface on which the film is formed or the upper surface.

[0107] In addition, in the out-of-plane structural analysis of CAAC-OS, 2θ is 31° In addition to the peaks around 2θ of 36°, a peak may also appear around 2θ of 36°. The peaks near the c-axis indicate that some of the CAAC-OS contains crystals that do not have the c-axis orientation. The more preferable CAAC-OS is the structure solution by the out-of-plane method. In the analysis, a peak is observed at 2θ of approximately 31°, but no peak is observed at 2θ of approximately 36°.

[0108] On the other hand, in-plan X-ray irradiation is performed on CAAC-OS in a direction perpendicular to the c-axis. When the structure is analyzed by the δ method, a peak appears at 2θ of about 56°. This peak is due to In GaZnO 4 In the case of CAAC-OS, the 2θ is set to 56 The sample was rotated around the normal vector of the sample surface as the axis (φ axis) while performing the analysis. Even if a φ scan is performed, no clear peak appears as shown in FIG. 9(B). , InGaZnO 4 In the case of a single crystal oxide semiconductor, 2θ is fixed at around 56° and φ is When the ion beam was scanned, a peak was observed that was assigned to a crystal plane equivalent to the (110) plane, as shown in FIG. Therefore, the structure analysis using XRD shows that CAAC-OS has a-axis It can be seen that the orientation of the b axis is irregular.

[0109] Next, we will explain the CAAC-OS analyzed by electron diffraction. nO 4 For CAAC-OS with a crystal of 100 nm, a probe with a diameter of 300 nm was placed parallel to the sample surface. When an electron beam is incident, a diffraction pattern (selected area transmission electron diffraction) like that shown in Figure 10(A) is obtained. This diffraction pattern may appear due to the InGaZnO 4 of This includes spots due to the (009) plane of the crystal. Therefore, even with electron diffraction, The pellets contained in the CAAC-OS have a c-axis orientation, and the c-axis is approximately aligned on the surface to be formed or the upper surface. On the other hand, the same sample was probed perpendicular to the sample surface. The diffraction pattern when an electron beam with a diameter of 300 nm was incident is shown in FIG. (B) shows a ring-shaped diffraction pattern. Therefore, by electron diffraction, It is seen that the a-axis and b-axis of the pellets contained in the CAAC-OS have no orientation. The first ring in FIG. 10(B) is made of InGaZnO 4 The (010) plane of the crystal and This is thought to be due to the (100) surface and the like. The second ring in Figure 10(B) This is thought to be due to the (110) plane, etc.

[0110] As described above, the CAAC-OS is an oxide semiconductor with high crystallinity. Crystallinity can be reduced by the inclusion of impurities or the formation of defects, so the opposite view is taken. CAAC-OS can be said to be an oxide semiconductor with few impurities and defects (such as oxygen vacancies).

[0111] The impurities are elements other than the main components of the oxide semiconductor, such as hydrogen, carbon, silicon, and transition metals. For example, oxygen is more abundant than metal elements such as silicon that constitute oxide semiconductors. Elements with strong bonding strength with the oxide semiconductor remove oxygen from the oxide semiconductor, thereby changing the atomic arrangement of the oxide semiconductor. In addition, heavy metals such as iron and nickel, argon, and nitrogen Carbon oxide and other elements have a large atomic radius (or molecular radius), so they can easily arrange the atoms of oxide semiconductors. This causes the crystallinity to decrease.

[0112] When an oxide semiconductor has impurities or defects, its characteristics may change due to light, heat, etc. For example, impurities contained in an oxide semiconductor can become carrier traps or can displace carriers. In addition, oxygen vacancies in oxide semiconductors can become carrier traps. In some cases, they act as carrier generation sources by capturing hydrogen.

[0113] CAAC-OS, which has few impurities and oxygen vacancies, is an oxide semiconductor with low carrier density. Specifically, 8×10 11 pieces / cm 3 Less than 1 x 10 11 pieces / cm 3 less than , and more preferably 1×10 10 pieces / cm 3 Less than 1 x 10 -9 pieces / cm 3 The above Such an oxide semiconductor can be obtained by using a high-purity pure oxide semiconductor. CAAC-OS is a highly pure or substantially intrinsic oxide semiconductor with low impurity concentration. In other words, it can be said that the oxide semiconductor has stable characteristics.

[0114] <nc-os> Next, we will explain nc-OS.

[0115] In the high-resolution TEM image, the nc-OS is divided into two groups: one where the crystals can be confirmed, and the other where the crystals can be clearly confirmed. The nc-OS has regions where no crystalline parts can be confirmed. The size is often between 1 nm and 10 nm, or between 1 nm and 3 nm. An oxide semiconductor having a crystal size of 10 nm or more and 100 nm or less is called a microcrystalline oxide. For example, in high-resolution TEM images, nc-OS shows grain boundaries. In addition, the nanocrystals are different from the pellets in CAAC-OS. Therefore, in the following, the crystalline part of nc-OS is called pellets. There may be cases where this happens.

[0116] The nc-OS is a nano-sized area (e.g., an area of ​​1 nm to 10 nm, especially 1 nm to 3 nm). The nc-OS has periodic atomic arrangement in the sub-nm region. There is no regularity in the crystal orientation between the dots. Therefore, no orientation is observed throughout the film. Therefore, depending on the analysis method, nc-OS may be considered to be a-like OS or amorphous oxide semiconductor. For example, for nc-OS, the X-shaped pellets with a diameter larger than that of the pellets may not be distinguishable. When using the line, the peaks showing the crystal planes were not detected by the out-of-plane method. In addition, for nc-OS, a probe diameter larger than the pellet (e.g. 50n When electron diffraction is performed using an electron beam of 1000 nm or more, a halo-like diffraction pattern is observed. On the other hand, for nc-OS, the size of the pellet is close to or smaller than that of the pellet. When performing nanobeam electron diffraction using an electron beam with a diameter of n When nanobeam electron diffraction is performed on c-OS, bright spots appear in a circular (ring-like) pattern. In some cases, a ring-shaped area may be observed. In addition, multiple spots may be observed within the ring-shaped area. There are cases.

[0117] In this way, the crystal orientation between the pellets (nanocrystals) is not regular, so nc- OS with RANC (Random Aligned nanocrystals) oxide semiconductors, or NANCs (Non-Aligned Nanocrystals) ) can also be referred to as an oxide semiconductor.

[0118] The nc-OS is an oxide semiconductor with higher order than an amorphous oxide semiconductor. The nc-OS has a lower density of defect states than the a-like OS and amorphous oxide semiconductors. However, the crystal orientation of nc-OS is not regular among different pellets. , the nc-OS has a higher density of defect states than the CAAC-OS.

[0119] <a-like OS> The a-like OS is an oxide semiconductor that has a structure between the nc-OS and the amorphous oxide semiconductor. It is a conductor.

[0120] In a-like OS, pores may be observed in high-resolution TEM images. In the high-resolution TEM image, there are areas where crystals can be clearly seen and areas where crystals cannot be seen. and areas where it is not possible to

[0121] Because of the porosity, the a-like OS is an unstable structure. To demonstrate that the OS has a less stable structure compared with CAAC-OS and nc-OS. , shows the change in structure due to electron irradiation.

[0122] The samples to be irradiated with electrons were a-like OS (referred to as sample A), nc-OS ( Sample B) and CAAC-OS (sample C) are prepared. The sample in is also an In-Ga-Zn oxide.

[0123] First, high-resolution cross-sectional TEM images of each sample are obtained. It can be seen that each of the samples has a crystalline portion.

[0124] The determination of which part is regarded as one crystal part can be made as follows. For example, InGaZnO 4 The unit cell of this crystal has three In-O layers and one Ga-Zn-O layer. It is known that the structure has a total of nine layers, including six layers, stacked in layers in the c-axis direction. The spacing between adjacent layers is approximately the same as the lattice spacing (also called the d value) of the (009) plane. The value is calculated to be 0.29 nm from crystal structure analysis. The areas where the spacing is 0.28 nm or more and 0.30 nm or less are InGaZnO 4 The crystal part of The lattice fringes can be formed by InGaZnO 4 This corresponds to the ab plane of the crystal.

[0125] Figure 11 shows an example of the average size of the crystal parts (22 to 45 places) of each sample. However, the length of the lattice fringes mentioned above is the size of the crystal part. It can be seen that the crystal part of eOS becomes larger according to the cumulative dose of electron irradiation. As shown by (1) in Fig. 11, the initial size of the TEM observation was about 1.2 nm. The crystal part (also called the initial nucleus) was 4.2×10 in size, but the cumulative irradiation dose was 4.2×10 8 e - / nm 2 On the other hand, in the nc-OS, the size of the nanoparticles grows to about 2.6 nm. For CAAC-OS, the cumulative electron dose from the start of electron irradiation was 4.2 × 10 8 e - / nm 2 It can be seen that there is no change in the size of the crystals within the range of As shown in (2) and (3) in Fig. 11, the nc-OS and The sizes of the crystal parts of the CAAC-OS and CAAC-OS are about 1.4 nm and 2.1 nm, respectively. I realize something.

[0126] Thus, in a-like OS, the growth of crystals can be observed by electron irradiation. On the other hand, the growth of the crystals in the nc-OS and CAAC-OS was hardly observed by electron irradiation. In other words, a-like OS is not seen in nc-OS and CAAC-OS. It can be seen that compared with S, it has a less stable structure.

[0127] In addition, because of the porosity, a-like OS is more resistant to vascular endothelial cell proliferation than nc-OS and CAAC-OS. Specifically, the density of the a-like OS is lower than that of a single crystal of the same composition. The density of nc-OS is 78.6% or more and less than 92.3% of that of CAAC. The density of the -OS is 92.3% or more and less than 100% of the density of a single crystal of the same composition. It is difficult to form an oxide semiconductor film having a density of less than 78% of that of the oxide semiconductor film.

[0128] For example, in an oxide semiconductor with an atomic ratio of In:Ga:Zn=1:1:1, Single-crystal InGaZnO with a helical crystal structure 4 The density of is 6.357g / cm 3 It becomes. For example, in an oxide semiconductor having an atomic ratio of In:Ga:Zn=1:1:1, , the density of a-like OS is 5.0g / cm 3 More than 5.9g / cm 3 It is less than. For example, in an oxide semiconductor having an atomic ratio of In:Ga:Zn=1:1:1, The density of nc-OS and that of CAAC-OS are 5.9 g / cm 3 More than 6.3g / cm 3 It will be less than.

[0129] In some cases, single crystals with the same composition do not exist. In such cases, the composition may differ in any ratio. By combining single crystals, we estimate the density equivalent to a single crystal of the desired composition. The density corresponding to a single crystal of a desired composition can be obtained by combining single crystals of different compositions. The weighted average of the proportion of It is preferable to estimate by combining different types of single crystals.

[0130] As described above, oxide semiconductors have various structures, each of which has various characteristics. The oxide semiconductor may be, for example, an amorphous oxide semiconductor, an a-like OS, an nc-OS, A multilayer film having two or more kinds of CAAC-OS may be used.

[0131] Describe oxides that can be used for the insulator 406a, the semiconductor 406b, the insulator 406c, etc. do.

[0132] The semiconductor 406b is, for example, an oxide semiconductor containing indium. For example, the inclusion of indium increases carrier mobility (electron mobility). 406b preferably contains the element M. The element M is preferably aluminum, gallium, or the like. , yttrium, or tin. Other elements that can be used for M include ho, Uranium, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, la Examples include tantalum, cerium, neodymium, hafnium, and tungsten. In some cases, the element M may be a combination of the above elements. For example, it is an element with a high bond energy with oxygen. Alternatively, the element M may be, for example, an element having an energy density higher than that of an oxide semiconductor. It is an element that has a function of increasing the gap. In addition, the semiconductor 406b preferably contains zinc. When an oxide semiconductor contains zinc, it may be easily crystallized.

[0133] However, the semiconductor 406b is not limited to an oxide semiconductor containing indium. 6b is an indium oxide, such as zinc tin oxide, gallium tin oxide, or gallium oxide; oxide semiconductor containing zinc, oxide semiconductor containing gallium, oxide semiconductor containing tin It may be a semiconductor or the like.

[0134] The semiconductor 406b is made of, for example, an oxide having a large energy gap. The energy gap of b is, for example, 2.5 eV or more and 4.2 eV or less, preferably 2.8 The excitation voltage is preferably from 3 eV to 3.5 eV, and more preferably from 3 eV to 3.8 eV.

[0135] For example, the insulator 406a and the insulator 406c are made of a material other than oxygen constituting the semiconductor 406b. It is an oxide composed of one or more elements. The insulators 406a and 406c are composed of one or more elements other than oxygen. Therefore, the interface between the insulator 406a and the semiconductor 406b and the interface between the semiconductor 406b and the insulator 406a are At the interface with the body 406c, an interface state is unlikely to be formed.

[0136] When the insulator 406a, the semiconductor 406b, and the insulator 406c contain indium, When the insulator 406a is an In-M-Zn oxide, the sum of In and M is When 100 atomic %, In is preferably less than 50 atomic % and M is preferably less than 50 atomic %. More preferably, In is less than 25 atomic % and M is 75 atomic % or more. When the semiconductor 406b is an In-M-Zn oxide, the In When the sum of and M is 100 atomic %, preferably In is 25 atomic % More preferably, M is less than 75 atomic %, and In is more preferably 34 atomic % or more. The insulator 406c is an In-M-Zn oxide. In the case of a compound, when the sum of In and M is 100 atomic %, preferably In is 5 0 atomic %, M is higher than 50 atomic %, and more preferably In is 25 atomic %, and M is higher than 75 atomic %. The same type of oxide as the insulator 406a may be used.

[0137] The semiconductor 406b is an oxide having a larger electron affinity than the insulator 406a and the insulator 406c. For example, the semiconductor 406b is made of a material selected from the insulators 406a and 406c. The electron affinity is 0.07 eV to 1.3 eV, preferably 0.1 eV to 0.7 eV. It is more preferable to use an oxide having a larger molecular weight by 0.15 eV or more and 0.4 eV or less. Electron affinity is the energy difference between the vacuum level and the bottom of the conduction band.

[0138] Indium gallium oxide has a small electron affinity and a high oxygen blocking property. Therefore, it is preferable that the insulator 406c contains indium gallium oxide. The atomic ratio [Ga / (In+Ga)] is, for example, 70% or more, preferably 80% or more, and Preferably, the ratio is 90% or more.

[0139] However, the insulator 406a and / or the insulator 406c may be gallium oxide. For example, when gallium oxide is used as the insulator 406c, the conductor 416a1 or It is possible to reduce the leakage current occurring between the conductor 416a2 and the conductor 404. That is, the off-state current of the transistor can be reduced.

[0140] At this time, when a gate voltage is applied, the insulator 406a, the semiconductor 406b, and the insulator 406c Of these, a channel is formed in the semiconductor 406b having the larger electron affinity.

[0141] Here, between the insulator 406a and the semiconductor 406b, In addition, between the semiconductor 406b and the insulator 406c, The semiconductor 406b may have a mixed region of the insulator 406c. Therefore, the power density of the insulator 406a, the semiconductor 406b, and the insulator 406c is reduced. In the laminate, the energy changes continuously near each interface (also called continuous junction). ) band diagram.

[0142] At this time, the electrons flow into the semiconductor 406b, not into the insulator 406a and the insulator 406c. Therefore, the electrons at the interface between the insulator 406a and the semiconductor 406b move mainly through the The interface state density at the interface between the semiconductor 406b and the insulator 406c is reduced. By doing so, the movement of electrons in the semiconductor 406b is not hindered, and the transistor This allows the on-state current of the transistor to be increased.

[0143] In addition, when the transistor has an s-channel structure, the entire semiconductor 406b is Therefore, the thicker the semiconductor 406b, the larger the channel area. That is, the thicker the semiconductor 406b, the higher the on-state current of the transistor. For example, 10 nm or more, preferably 20 nm or more, more preferably 40 nm or more, A semiconductor 4 having a region preferably having a thickness of 60 nm or more, more preferably 100 nm or more However, in the case where the productivity of a semiconductor device having a transistor decreases, Therefore, for example, the thickness is 300 nm or less, preferably 200 nm or less, and more preferably 1 The semiconductor 406b may have a thickness of 50 nm or less. As the area shrinks, the thinner the semiconductor 406b, the better the electrical characteristics of the transistor. Therefore, the thickness of semiconductor 406b may be less than 10 nm.

[0144] In addition, in order to increase the on-state current of the transistor, the thickness of the insulator 406c is preferably as small as possible. For example, it is less than 10 nm, preferably 5 nm or less, and more preferably 3 nm or less. On the other hand, the insulator 406c may have a region where a channel is formed. The semiconductor 406b is then subjected to a thermal treatment using an element other than oxygen (such as hydrogen or silicon) that constitutes the adjacent insulator. Therefore, the insulator 406c has a function of blocking the intrusion of certain For example, the thickness is 0.3 nm or more, preferably 1 nm or more. More preferably, the insulator 406c has a region having a thickness of 2 nm or more. The insulator 406c is provided to suppress outward diffusion of oxygen released from the insulator 402, etc. It is preferable that the material has oxygen blocking properties.

[0145] In order to increase reliability, the insulator 406a is thick and the insulator 406c is thin. For example, it is preferably 10 nm or more, more preferably 20 nm or more, and even more preferably 40 nm or more. More preferably, the insulator 406a may have a region having a thickness of 60 nm or more. By increasing the thickness of the insulator 406a, the insulator 406a can be prevented from being heated at the interface between the insulator 406a and the adjacent insulator. The distance from the transistor 406b to the semiconductor 406b where the channel is formed can be increased. For example, when the device is 200 nm or less, the productivity of the semiconductor device having the transistor may decrease. , preferably having a region with a thickness of 120 nm or less, more preferably 80 nm or less The field can be designated as 406a.

[0146] For example, silicon in an oxide semiconductor can become a carrier trap or a carrier generation source. Therefore, the lower the silicon concentration of the semiconductor 406b, the more preferable it is. Between the insulating layer 406b and the insulating layer 406a, for example, a secondary ion mass spectrometry (SIMS) Ondary Ion Mass Spectrometry (IonMass Spectrometry) 19 atoms / cm 3 Less than 5 x 10 18 atoms / cm 3 Less than or equal to Or 2×10 18 atoms / cm 3 and Between the semiconductor 406b and the insulator 406c, 1×10 19 atoms / cm 3 Less than 5 x 10 18 atoms / cm 3 Less than 2× 10 18 atoms / cm 3 The silicon concentration is less than 100 nm.

[0147] In order to reduce the hydrogen concentration in the semiconductor 406b, the insulator 406a and the insulator 406 It is preferable to reduce the hydrogen concentration in the insulator 406a and the insulator 406c by SIMS. In, 2×10 20 atoms / cm 3 Less than or equal to 5×10 19 atoms / cm 3 Less than or equal to 1×10 19 atoms / cm 3 Less than 5, more preferably ×10 18 atoms / cm 3 The semiconductor 406 has a region with a hydrogen concentration of 1000 to 15000 . In order to reduce the nitrogen concentration of b, the nitrogen concentration of the insulators 406a and 406c is reduced. Insulator 406a and insulator 406c are preferably 5×10 19 atoms / cm 3 Less than 5 x 10 18 atoms / cm 3 The following is better Preferably 1×10 18 atoms / cm 3 Less than 5×10, more preferably 17 atom s / cm 3 The nitrogen concentration ranges as follows:

[0148] Note that when copper is mixed into an oxide semiconductor, electron traps may be generated. The flip-flop may cause the threshold voltage of the transistor to shift in the positive direction. The copper concentration on or inside the semiconductor 406b is preferably as low as possible. 06b has a copper concentration of 1×10 19 atoms / cm 3 Below, 5 x 10 18 atoms / c m 3 or less, or 1×10 18 atoms / cm 3 It is preferred to have a region where:

[0149] The three-layer structure described above is an example. For example, a two-layer structure without the insulator 406a or the insulator 406c Alternatively, the insulating layer 406 may be formed on or under the insulating layer 406a or on the insulating layer 406c. The insulator 406a, the semiconductor 406b, and the insulator 406c are illustrated above and below. It may be a four-layer structure having either an insulator or a semiconductor. Either above insulator 406a, below insulator 406a, above insulator 406c, or below insulator 406c The insulating layer 406 is formed in two or more places. The insulating layer 406 is formed in the insulating layer 406. It may also be an n-layer structure (n is an integer of 5 or more) having either an insulating layer or a semiconductor layer. .

[0150] The substrate 400 may be, for example, an insulating substrate, a semiconductor substrate, or a conductive substrate. Examples of the insulating substrate include a glass substrate, a quartz substrate, a sapphire substrate, and a stabilized zirconia substrate. There are also semiconductor substrates, such as zirconia substrates stabilized with yttria, and resin substrates. The substrate may be, for example, a single semiconductor substrate such as silicon or germanium, or a silicon carbide substrate. Silicon, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, gallium oxide Furthermore, there are compound semiconductor substrates made of insulating material. A semiconductor substrate having, for example, an SOI (Silicon On Insulator) substrate Conductive substrates include graphite substrates, metal substrates, alloy substrates, conductive resin substrates, etc. Alternatively, there are substrates having metal nitrides, substrates having metal oxides, etc. Further, a substrate in which a conductor or a semiconductor is provided on an insulating substrate, a substrate in which a conductor or a semiconductor is provided on a semiconductor substrate, There are substrates with an insulator, and substrates with a semiconductor or insulator on a conductor substrate. Alternatively, a substrate having elements provided thereon may be used. Examples of the elements include a capacitance element, a resistance element, a switch element, a light-emitting element, and a memory element.

[0151] A flexible substrate may be used as the substrate 400. The method of providing the transistor is to fabricate the transistor on a non-flexible substrate and then Alternatively, the resistor may be peeled off and transferred to the flexible substrate 400. A peeling layer may be provided between the non-flexible substrate and the transistor. Alternatively, a sheet, film, or foil having woven fibers may be used. The substrate 400 may be stretchable. Also, the substrate 400 may be designed to retain its original shape when the bending or pulling is stopped. The substrate 4 may have a property of returning to its original shape. Alternatively, the substrate 4 may have a property of not returning to its original shape. 00 is, for example, 5 μm or more and 700 μm or less, preferably 10 μm or more and 500 μm or less; More preferably, the substrate 400 has a region having a thickness of 15 μm or more and 300 μm or less. By making the substrate thinner, the weight of the semiconductor device having the transistor can be reduced. By making 00 thinner, it can be stretched even when using glass, and can be easily folded or folded. It may have the property of returning to its original shape when you stop pulling it. Therefore, it is possible to reduce the impact applied to the semiconductor device on the substrate 400. It is possible to provide a semiconductor device.

[0152] The substrate 400, which is a flexible substrate, may be made of, for example, a metal, an alloy, a resin, or a glass. The substrate 400, which is a flexible substrate, has a linear expansion coefficient of 1.0. The lower the coefficient of thermal expansion, the more preferable it is because deformation due to the environment is suppressed. For example, the linear expansion coefficient is 1×10 -3 / K or less, 5×10 -5 / K or less, or 1×1 0 -5 The resin may be, for example, polyester or polystyrene. Olefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, Acrylic, etc. In particular, aramid has a low linear expansion coefficient, so it is suitable for flexible substrates. 400 is preferable.

[0153] This embodiment may be appropriately combined with at least a part of other embodiments described in this specification. It can be implemented together.

[0154] (Embodiment 3) <Transistor manufacturing method 1> A method for manufacturing the transistor of FIG. 1 according to the present invention will be described below with reference to FIGS. do.

[0155] First, a substrate 400 is prepared.

[0156] Next, the insulator 401 is formed. The insulator 401 is formed by a sputtering method, a chemical vapor deposition method, or the like. Chemical Vapor Deposition (CVD) method, molecular beam epitaxy Molecular Beam Epitaxy (MBE) method or pulse laser Pulsed Laser Deposition (PLD), Atomic Layer Deposition ( This can be done using methods such as ALD (Atomic Layer Deposition). can.

[0157] The CVD method is a method that uses plasma CVD (PECVD: Plasma ECVD). enhanced CVD method, and thermal CVD (TCVD: Thermal CVD) method D) method, photo CVD method, etc. Depending on the source gas, metal CVD (MCVD) method, metal organic CVD ( MOCVD (Metal Organic CVD) method.

[0158] The plasma CVD method can produce high-quality films at relatively low temperatures. This is a film formation method that can reduce plasma damage to the workpiece because it does not use a plasma. For example, wiring, electrodes, elements (transistors, capacitors, etc.) included in a semiconductor device etc. may become charged up by receiving an electric charge from the plasma. Accumulated electric charges can destroy wiring, electrodes, elements, etc., contained in semiconductor devices. On the other hand, in the case of thermal CVD, which does not use plasma, such plasma damage does not occur. Therefore, the yield of the semiconductor device can be increased. Since no plasma damage occurs during deposition, a film with few defects can be obtained.

[0159] In addition, the ALD method is also a film formation method that can reduce plasma damage to the workpiece. In addition, the ALD method does not cause plasma damage during film formation, so films with fewer defects can be produced. Obtained.

[0160] The CVD and ALD methods are deposition methods in which particles emitted from a target are deposited. Unlike the conventional method, this is a film formation method in which a film is formed by a reaction on the surface of the object to be treated. This is a film forming method that is less susceptible to the shape of the workpiece and has good step coverage. The ALD method has excellent step coverage and thickness uniformity, making it suitable for the production of films with high aspect ratios. However, the ALD method has a relatively low deposition rate. Because the deposition rate is slow, it can be used in combination with other deposition methods such as CVD, which has a high deposition rate. In some cases this is preferable.

[0161] In the CVD and ALD methods, the composition of the resulting film can be controlled by the flow rate ratio of the source gases. For example, in the CVD and ALD methods, the flow rate ratio of the source gases can be adjusted to any desired value. In addition, for example, in the CVD method and the ALD method, the film formed can be By changing the flow rate ratio of the source gas while maintaining the temperature, a film with a continuously changing composition can be formed. When forming a film while changing the flow rate ratio of the source gas, multiple film forming chambers can be used. Compared to deposition by a vacuum, the time required for deposition is shortened by the time required for transportation and pressure adjustment. Therefore, the productivity of the semiconductor device can be increased in some cases.

[0162] Next, the insulator 301 is formed on the insulator 401. The insulator 301 is formed by sputtering. The deposition can be performed by using a deposition method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

[0163] Next, a groove is formed in the insulator 301 so as to reach the insulator 401. The groove may be, for example, a hole or an opening. The grooves may be formed by wet etching, but dry etching is also preferred. In addition, the insulator 401 is preferably used for etching the insulator 301. It is preferable to select an insulator that functions as an etching stopper film when forming a groove. For example, when a silicon oxide film is used for the insulator 301 forming the groove, the insulator 40 The film 1 may be a silicon nitride film, an aluminum oxide film, or a hafnium oxide film.

[0164] After the grooves are formed, a conductor that will become the conductor 310a or the conductor 310b is formed. The conductor to be the conductor 10a or the conductor 310b includes a conductor having a function of being difficult to permeate oxygen. For example, tantalum nitride, tungsten nitride, titanium nitride, etc. Alternatively, tantalum, tungsten, titanium, molybdenum, aluminum, The conductor 310a may be a laminated film of copper or a molybdenum tungsten alloy. The conductive material to be the conductive material 310b is formed by sputtering, CVD, MBE or P This can be done using the LD method, the ALD method, or the like.

[0165] Next, Chemical Mechanical Polishing 3. By performing the chemical mechanical polishing (CMP), a conductor 310a or a conductor 310b is formed on the insulator 301. The conductor is removed. As a result, the conductor 310a and the conductor 310b remain only in the groove. By doing so, it is possible to form a wiring layer having a flat upper surface.

[0166] Next, the insulator 302 is formed on the insulator 301, the conductor 310a, and the conductor 310b. The insulator 302 is formed by a sputtering method, a CVD method, an MBE method, a PLD method, or an A method. This can be done by using the LD method, etc. An electron capture layer 303 is formed on an insulator 302 . The electron capture layer 303 preferably has a function of being difficult to permeate impurities such as oxygen and hydrogen. For example, a silicon nitride film, an aluminum oxide film, or a hafnium oxide film is preferably used. The electron capture layer 303 may be formed by sputtering, CVD, MBE or This can be carried out by using a PLD method, an ALD method, or the like.

[0167] Next, the insulator 402 is formed on the electron trap layer 303. The insulator 402 is formed by sputtering. This can be done using a laser deposition method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. Next, a process for adding oxygen to the insulator 402 may be performed. Examples of the method include ion implantation and plasma treatment. The removed oxygen becomes excess oxygen.

[0168] Next, the insulator 406a_1 is deposited on the insulator 402. The insulator 406a_1 is deposited as follows: This is done using the sputtering method, CVD method, MBE method, PLD method, ALD method, etc. can be done.

[0169] Next, a process for adding oxygen to the insulator 406a_1 may be performed. The process includes, for example, an ion implantation method, a plasma treatment method, etc. The oxygen added to the layer corresponding to the insulator 406a_1 becomes excess oxygen. Next, a semiconductor film 406b_1 is formed on the insulator 406a_1. do.

[0170] Next, a first heat treatment is preferably performed at a temperature of 250° C. or higher and 650° C. or lower. , preferably 450°C or higher and 600°C or lower, and more preferably 520°C or higher and 570°C or lower. The first heat treatment is performed in an inert gas atmosphere or an oxidizing gas atmosphere having a concentration of 10 ppm or more. The first heat treatment is carried out in an atmosphere containing 1% or more or 10% or more of fluorine. Alternatively, the first heat treatment may be performed in an inert gas atmosphere, followed by desorbing oxygen. To compensate for this, heat in an atmosphere containing oxidizing gas at 10 ppm or more, 1% or more, or 10% or more. The first heat treatment can increase the crystallinity of the semiconductor 406b_1. In addition, impurities such as hydrogen and water can be removed. In the above, a plasma treatment including oxygen may be performed under a reduced pressure. For example, a device having a power source that generates high density plasma using microwaves can be used. It is preferable to use a power source that applies RF (Radio Frequency) to the substrate side. By using high density plasma, high density oxygen radicals can be generated. By applying RF to the substrate side, oxygen radicals generated by high density plasma can be It is possible to efficiently introduce the inert gas into the semiconductor 406b_1. In order to compensate for the oxygen that is desorbed after the plasma treatment containing oxygen, You may go.

[0171] Next, a conductor 414 is formed on the semiconductor 406b_1. The deposition can be performed by using a deposition method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. (See Figures 12(A), (B) and (C)).

[0172] Next, the conductor 414 is processed by lithography or the like to form a conductor 415 . (See Figures 13(A), (B) and (C)).

[0173] Next, the insulator 406a_1, the semiconductor 406b_1, and the conductor 415 are formed by a lithography method. The insulating material 406a, the semiconductor 406b, the conductor 416a1, and the conductor A multilayer film having a conductor 416a2 is formed. Here, when the conductor is formed, the semiconductor 406b is formed. Region 407 is formed by damaging the top surface of the semiconductor. Since the conductive body 406b has a region with a low resistance, the contact between the conductive body 415 and the semiconductor 406b is The tact resistance is reduced. When the multilayer film is formed, the insulator 402 is also etched. In other words, the insulator 402 may have a protrusion in the area in contact with the multilayer film. In some cases, the shape may have a portion (see Figs. 14(A), (B) and (C)).

[0174] In the lithography method, first, the resist is exposed through a mask. The resist mask is formed by removing or leaving the areas that have been exposed using a developer. By etching through the resist mask, a conductor, a semiconductor, an insulator, etc. It can be processed into the desired shape. For example, KrF excimer laser light, ArF excimer Laser light, EUV (Extreme Ultraviolet) light, etc. are used to create a resist A resist mask can be formed by exposing the substrate to light. A liquid immersion technique may be used, in which the substrate is exposed to light by filling it with liquid (e.g., water). In addition, an electron beam or an ion beam may be used. In this case, the mask is not necessary. The resist mask can be removed by ashing or other methods. Dry etching or wet etching or dry etching A wet etching process is performed after the etching process, or a dry etching process is performed after the wet etching process. A dry etching process can be carried out.

[0175] The dry etching equipment is a capacitively coupled plasma (CCP) device with parallel plate electrodes. Capacitively Coupled Plasma (CAP) etching equipment is used. The capacitively coupled plasma etching apparatus having parallel plate electrodes can be A high-frequency power source may be applied to one of the electrodes. A configuration in which a plurality of different high frequency power sources are applied to the electrodes may be used. Alternatively, a high-frequency power source having the same frequency may be applied to each of the parallel plate electrodes. Alternatively, a high-frequency power source having a high-density plasma source may be used. Dry etching equipment with a high density plasma source can be used. The device is, for example, an inductively coupled plasma (ICP) d Plasma etching equipment or the like can be used.

[0176] Next, the insulator 406c is formed. The insulator 406c is formed by a sputtering method, a CVD method, or the like. The method can be performed by using a method such as a method for growing an insulating layer 4, a method for growing an insulating layer 5, a method for growing an insulating layer 6, a method for growing an insulating layer 7, a method for growing an insulating layer 8, a method for growing an insulating layer 9, a method for growing an insulating layer 10, a method for growing an insulating layer 11, a method for growing an insulating layer 12, a method for growing an insulating layer 13, a method for growing an insulating layer 14, a The insulator 412 is deposited on the substrate 06c. The deposition of the insulator 412 can be performed by a sputtering method, a CVD method, or the like. The deposition can be performed by using a deposition method, an MBE method, a PLD method, an ALD method, or the like.

[0177] A film of a conductor that will become the conductor 404 is formed. The film of the conductor that will become the conductor 404 is formed by sputtering. The deposition can be performed by using a deposition method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. Next, the conductor that will become the conductor 404 is processed by a lithography method or the like. (See Figs. 15(A), (B) and (C)).

[0178] Next, the insulator 408 is formed. The insulator 408 is formed by a sputtering method, a CVD method, or the like. This can be done by using the MBE method, PLD method, ALD method, etc. Preferably, 408, a film of aluminum oxide is formed using plasma containing oxygen, The oxygen in the plasma can be added to the top surface of the insulator 412 as excess oxygen.

[0179] Next, the insulator 410 is deposited on the insulator 408. The deposition of the insulator 410 is carried out by sputtering. This can be done by using a deposition method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. Alternatively, the method may be a spin coat method, a dip method, a droplet ejection method (such as an inkjet method), or a printing method (such as a Clean printing, offset printing, etc.), doctor knife method, roll coater method or car This can be done using a ten-coater method or the like.

[0180] The insulator 410 may be formed so that the upper surface is flat. For example, the insulator 410 may be Alternatively, the insulator 410 may have a flat upper surface immediately after deposition. Later, the insulation is removed from the top surface so that it is parallel to the reference surface, such as the back surface of the board. Such a process is called a flattening process. However, the upper surface of the insulator 410 may be flat. This is not necessary (see Figures 16(A), (B) and (C)).

[0181] From here, the first opening, the second opening, the third opening, and the fourth opening according to the present invention will be described. A method for producing the part will now be described in detail.

[0182] First, the conductor 417a is formed on the insulator 410. The conductor 417a is formed by sputtering. This can be done using a laser deposition method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. Next, an insulator 419a is formed on the conductor 417a. This can be done using methods such as CVD, MBE, PLD, and ALD. (See Figures 17(A), (B) and (C)).

[0183] Next, a resist mask 420 is formed on the insulator 419a by lithography or the like. Although not shown, an organic coating film is formed on the insulator 419a, and lithography is performed on the organic coating film. A resist mask 420 may be formed by a photolithography method or the like. a and the resist mask 420, the insulator 419a and the resist mask 42 The adhesion to the SiO2 film may be improved through the organic coating film (Figures 18(A), (B) and See (C). ).

[0184] Next, the insulator 419a is removed by dry etching using the resist mask. The first processing is performed until the upper surface of the conductor 417a is reached, forming an insulator 419. When the coating film is formed on the insulator 419a, a dry etching method or the like is performed before the first processing. The organic coating film can be processed by, for example, B 4 F 6 Gas, C. 2 F 8 Gas, CF 4 Gas, SF 6 Gas or CHF 3 Using gas etc. It is possible.

[0185] The gas used in the first process is, for example, C 4 F 6 Gas, C. 2 F 8 Gas, CF 4 Gas, SF 6 Gas or CHF 3 The gases can be used alone or in combination of two or more gases. Alternatively, oxygen gas, helium gas, argon gas, hydrogen gas, etc. may be added to the above gas as appropriate. Dry etching is used for processing the organic coating film and the insulator 419. The etching equipment can be the above-mentioned dry etching equipment, but it is also possible to use parallel plate electrodes. It is preferable to use a dry etching apparatus in which high frequency power sources with different frequencies are connected to each of the electrodes. (See Figures 19(A), (B) and (C)).

[0186] Next, the conductor 417a is removed by dry etching until it reaches the top surface of the insulator 410. A second process is performed to form a conductor 417. The gas used for dry etching is, for example, B, C 4 F 6 Gas, C. 2 F 8 Gas, CF 4 Gas, SF 6 Gas, CHF 3 Gas, Cl 2 gas , BCl 3 Gas or SiCl 4 Gases can be used alone or in combination with two or more gases. Alternatively, the above gas may be oxygen gas, helium gas, argon gas or hydrogen gas. Gas or the like can be added as appropriate. At this time, the resist mask 420 is etched. The dry etching equipment is the same as that of the first process described above. In this manner, a hard mask having the conductor 417 and the insulator 419 is formed. (See Figures 20(A), (B) and (C)).

[0187] The hard mask may be a single layer of the conductor 417. A resist mask 420 is formed on the second substrate 17 by lithography or the like. The resist mask 420 is etched and removed by the second process. Alternatively, only the resist mask 420 or the organic coating may be used without a hard mask. In some cases, a two-layer mask of the film and resist mask 420 may be used.

[0188] Next, the hard mask having the conductor 417 and the insulator 419 is used as a mask to form the insulator 4 10 is subjected to a dry etching method to form a first opening, a second opening, a third opening, and The fourth opening is processed by the third process until it reaches the top surface of the insulator 408. The gas used may be the same as that used in the first process described above. Dry etching The processing device may be the same as that used in the first processing.

[0189] When the upper surface of the insulator 410 is flat, the thickness of the insulator 410 differs at each opening. In order of thickness, the first opening is the thickest, followed by the fourth opening, then the second opening, and then the third opening. This becomes an opening.

[0190] That is, in the third process, first, the insulator 410 in the second opening and the third opening is The insulating layer 408 is then etched down to the insulating layer 410 in the fourth opening. The insulating layer 408 is then etched away. Finally, the insulating layer 410 in the first opening is etched away. The second opening, the third opening, and the third opening are guided to the insulator 408. the time from when the 4 opening reaches the insulator 408 to when the first opening reaches the insulator 408; The insulator 408 in the second opening, the third opening, and the fourth opening is over-etched. This will be the case.

[0191] Therefore, the third processing condition is to set the etching rate of the insulator 408 to the etching rate of the insulator 410. In other words, the etching rate of the insulator 408 is small compared to the etching rate of the insulator 408. By increasing the ratio of the etching rates of the insulator 410, the second opening and the third opening The progress of etching of the insulator 408 at the mouth can be minimized. The ratio of the etching rate of the insulator 408 to the etching rate of the insulator 410 is The etching rate of the insulator 410 is set to 5 or more, with the etching rate being set to 1. 10 or more (see Figures 21(A), (B) and (C)).

[0192] Next, the insulator 408 is dry-etched to form the first opening, the second opening, and The third opening is machined down to the insulator 412, and the fourth opening is machined down to the conductor 404. The fourth processing step is carried out until the

[0193] Next, the insulator 412 is etched by a dry etching method to form the first opening, the second opening, and The third opening is processed by a fifth process until it reaches the insulator 406c. The fourth opening is processed by a fourth process. The processing reaches the conductor 404, and the conductor 404 in the fourth opening is overdone by the fifth processing. -etched (see Figures 22(A), (B) and (C)).

[0194] Next, the insulator 406c is dry-etched so that the first opening reaches the insulator 402. The second opening and the third opening are processed until the conductor 416a1 or the conductor 41 The sixth process is performed until 6a2 is reached. The fourth opening is formed by the fourth process until the conductor 404 is reached. The sixth process involves further over-etching.

[0195] Next, the insulator 402 is dry-etched to the seventh layer 303. The second opening or the third opening is processed by the sixth processing. The fourth conductor 416a2 is reached and is over-etched by the seventh process. The opening reaches the conductor 404 in the fourth process and is further extended by the seventh process. (See Figs. 23(A), (B) and (C)).

[0196] Next, the electron capture layer 303 is dry-etched to expose the first opening in the insulator 302. The eighth process is performed until the second opening or the third opening is the conductor in the sixth process. 416a1 or the conductor 416a2 is reached, and over-etching is performed by the eighth process. The fourth opening reaches the conductor 404 in the fourth processing step and is closed by the eighth processing step. Further over-etching occurs.

[0197] Next, the insulator 302 is dry-etched so that the first opening reaches the conductor 310b. The ninth process is performed until the conductor 4 is inserted into the second opening or the third opening. 16a1 or conductor 416a2, and the ninth process further over-edges the The fourth opening reaches the conductor 404 in the fourth process and is cut by the ninth process. This results in further over-etching.

[0198] The fourth machining condition, the fifth machining condition, the sixth machining condition, the seventh machining condition, the eighth machining condition, and The ninth and third processing conditions can be the same processing conditions. The gas may be the same as that used in the first process. The same equipment as in the first processing can be used.

[0199] The fourth machining condition, the fifth machining condition, the sixth machining condition, the seventh machining condition, the eighth machining condition, and The ninth processing condition is the etching rate of the conductor 404, the etching rate of the conductor 416a1, The etching rate of the conductor 416a2 and the etching rate of the conductor 310b Increasing the ratio of the etching rates of the grate to the insulator 408 and the electron capture layer 303 As a result, the conductor 404, the conductor 416a1, and the conductor 416a2 are overetched. The etching rate of the conductor 404 and the progress of the etching can be suppressed. The etching rate of conductor 416a1, the etching rate of conductor 416a2, and the etching rate of conductor 31 The etching rate of the insulator 408 and the electron capture layer 303 is set to 1 when the etching rate of the insulator 408 is 1. The ratio is 5 or more, and preferably 10 or more.

[0200] In addition, the third processing condition, the fourth processing condition, the fifth processing condition, the sixth processing condition, the seventh processing condition, In the first, eighth and ninth processing conditions, the insulator 41 as a hard mask is used. 9 and the etching rate of the conductor 417 and the insulators 410, 408, and 412 , the insulator 406c, the insulator 402, the electron capture layer 303 and the etching layer of the insulator 302. By increasing the ratio of the insulator 419 and the conductor 417 as a hard mask, This suppresses changes in shape and prevents abnormalities in the shape of the opening. The etching rates of the insulator 419 and the conductor 417 can be reduced by 1, the insulator 410, the insulator 408, the insulator 412, the insulator 406c, the insulator 402, The etching rate of the electron capture layer 303 and the insulator 302 is set to 5 or more, preferably 1 Must be 0 or greater.

[0201] The first to ninth processes were performed continuously using the same dry etching equipment. Alternatively, the dry etching apparatus may have a plurality of etching chambers. If you use a vacuum, you can process the board without exposing it to the air for each process. This prevents corrosion, contamination, and adhesion of dirt to the board, and improves productivity. preferable.

[0202] For example, if the dry etching apparatus has two etching chambers, the first After the first and second processes are performed in succession in the chamber, the second chamber is The plate may be moved to perform the third to ninth processes in succession. If the gas type is different, for example, if the chamber is divided into two types, one containing chlorine and the other containing fluorine, This is advantageous for the stability of the tin rate, etc. The first chamber performs the first through ninth processes, and the second chamber performs the first through ninth processes in the same way. Parallel processing can be used to improve productivity. Thus, a first opening, a second opening, a third opening and a fourth opening can be formed. (See Figures 24(A), (B) and (C).)

[0203] Next, the conductor 422a is formed. The conductor 422a is formed by a sputtering method or a CVD method. The deposition can be performed by using an MBE method, a PLD method, an ALD method, or the like. The insulating film 410 is formed so as to fill the openings formed by the insulating film 410. It is preferable to use the VD method (particularly the MCVD method). In order to improve the adhesion of the conductor to be formed, the conductor formed by the ALD method or other method is In some cases, it may be preferable to form a multilayer film with a conductor formed by the VD method. For example, titanium nitride and A multilayer film in which tungsten and silicon are deposited in this order may be used (FIGS. 25(A) and 25(B)). ) and (C).

[0204] Next, the conductor 422a is subjected to a first CMP process until it reaches the top surface of the insulator 419. A body 422 is formed (see Figures 26(A), (B) and (C)).

[0205] Next, the conductor 422, the insulator 419, and the conductor 417 are heated until they reach the top surface of the insulator 410. Then, a second CMP process is performed at 200° C. As a result, the first opening is filled with a conductor 433, The second opening is filled with a conductor 431, and the third opening is filled with a conductor 429. A conductor 437 is embedded in the fourth opening (FIGS. 27(A), (B) and (C)). reference.).

[0206] Next, the insulator 410, the conductor 433, the conductor 431, the conductor 429, and the conductor A conductor is formed on the substrate 437, and a part of the conductor is etched by lithography. This forms the conductor 434, the conductor 432, the conductor 430, and the conductor 438. In this manner, the transistor shown in FIG. 1 can be manufactured (FIGS. 28(A), (B) and See (C).

[0207] <Transistor manufacturing method 2> A method for fabricating the transistor of FIG. 4 according to the embodiment of the present invention will be described below with reference to FIGS. This will be explained using: The steps up to the step of forming the conductor 414 are the same as those of the above-described method 1 for fabricating a transistor. (See Figures 29(A), (B) and (C)).

[0208] Next, the insulator 406a_1, the semiconductor 406b_1, and the conductor 414 are formed by a lithography method. The multilayer structure includes an insulator 406a, a semiconductor 406b, and a conductor 415. Here, when the conductor 414 is formed, damage is not caused to the upper surface of the semiconductor 406b_1. By applying the current, a region 407 is formed. The region 407 is formed by applying the current to the semiconductor 406b, which is made to have a low resistance. Since the semiconductor 406b has a region, the contact resistance between the conductor 415 and the semiconductor 406b is reduced. When the multilayer film is formed, the insulator 402 is also etched and some regions become thin. That is, the insulator 402 may have a shape having a convex portion in the region in contact with the multilayer film. (See Figures 30(A), (B) and (C)).

[0209] Next, the insulator 410a is formed. The insulator 410a is formed by a method such as sputtering or CVD. The deposition can be performed by using a method such as a spin deposition method, an MBE method, a PLD method, or an ALD method. Coating method, dip method, droplet ejection method (inkjet method, etc.), printing method (screen printing , offset printing, etc.), doctor knife method, roll coater method or curtain coater This can be done using the method.

[0210] The insulator 410a may be formed so that the upper surface is flat. For example, the insulator 410 The insulator 410a may have a flat upper surface immediately after deposition. After deposition, the insulators are removed from the top surface so that the surface is parallel to the reference surface, such as the back surface of the substrate. Such a process is called a flattening process. The flattening process may be , CMP, dry etching, etc. However, if the top surface of the insulator 410a is flat, It does not have to have gender.

[0211] Next, a resist mask 411 is formed on the insulator 410a by lithography or the like. In order to improve the adhesion between the upper surface of the insulator 410a and the resist mask, for example, For example, an organic coating film may be provided between the insulator 410a and the resist mask 411. A single layer of a conductor or a laminated film of a conductor and an insulator is formed on the edge 410a, and then lithography is performed. A hard mask may be formed by a deposition method (see Figures 31(A), (B) and (C)). .).

[0212] Next, the insulator 410a is first etched by a dry etching method or the like until it reaches the insulator 402. The insulator 410 is formed by processing the insulator 402 on the electron capture layer 303. The etching may be performed until the etching gas reaches the first step. For example, C 4 F 6 Gas, CF 4 Gas, SF 6 Gas or CHF 3 Using gas, etc. Alternatively, the above gas may be mixed with oxygen gas, helium gas, argon gas, or hydrogen gas. etc. can be added appropriately. Here, C 4 F 6 Use gas with oxygen added. It is preferable to use the above-mentioned dry etching equipment as the dry etching equipment. However, a configuration in which high-frequency power sources with different frequencies are connected to each parallel plate electrode is used. The use of a light etching apparatus is preferred.

[0213] Next, the conductor 415 is subjected to a second process such as dry etching to form a conductor The conductor 416a1 and the conductor 416a2 are separated. For example, C 4 F 6 Gas, CF 4 Gas, SF 6 Gas, Cl 2 Gas, BCl 3 Gas, S. iCl 4 The gases can be used alone or in combination of two or more. Oxygen gas, helium gas, argon gas or hydrogen gas may be added as appropriate. , C.F. 4 Gas, Cl 2 It is recommended to use a mixture of fluorine gas and oxygen gas. The apparatus may be the dry etching apparatus described above in the first process.

[0214] At this time, the semiconductor 406b has an exposed area. Region 407 may be removed by the second processing described above (FIGS. 32(A) and (B) and See also (C).

[0215] When the first and second processes are performed by dry etching, the exposed area of ​​the semiconductor 406b is Impurities such as residual components of the etching gas may adhere to the etching area. If chlorine gas is used as the gas, chlorine may adhere to the surface. If a hydrocarbon gas is used as the gas source, carbon and hydrogen may adhere to the surface. If the substrate is later exposed to the atmosphere, the exposed areas of the semiconductor 406b may corrode. By continuously performing a plasma treatment using oxygen gas after the second processing, the above impurities can be removed. This is preferable because it can prevent corrosion of the exposed areas of the semiconductor 406b, etc.

[0216] Alternatively, the impurities can be reduced by, for example, a cleaning treatment using diluted hydrofluoric acid or ozone. A cleaning treatment using a cleaning agent such as a cleaning agent may be performed. A plurality of cleaning treatments may be combined. As a result, the exposed region of the semiconductor 406b, in other words the channel formation region, becomes highly resistive. do.

[0217] On the other hand, the conductors 416a1 and 416a2 and the upper surface of the semiconductor 406b are in contact with each other. The overlapping region 407 is formed by the conductors 416a1 and 416a2 and the semiconductor 4 06b, the contact resistance between the first and second electrodes is low, and good transistor characteristics can be obtained. It is.

[0218] Next, an insulator that will become the insulator 406c is formed, and the insulator 4 is deposited on the insulator that will become the insulator 406c. The insulators that will become the insulators 406c and 412 are then deposited. The film formation of the substrate is performed by sputtering, CVD, MBE, PLD, ALD, etc. The insulator that becomes the insulator 406c and the insulator that becomes the insulator 412 can be used. 4 is an opening formed by the insulator 410, the conductor 416a1, and the conductor 416a2. Therefore, it is preferable to use the ALD method. stomach.

[0219] Next, a film of a conductor that will become the conductor 404 is formed. This can be done using methods such as CVD, MBE, PLD, and ALD. The conductor that becomes the conductor 404 fills the opening formed by the insulator 410 or the like. Therefore, it is preferable to use the CVD method (particularly the MCVD method). In addition, in order to improve the adhesion between the insulator 410 and the conductor formed by the MCVD method, a method such as ALD is used. In some cases, it is preferable to form a multilayer film of a conductor formed by a method such as a CVD method and a conductor formed by a CVD method. For example, a multilayer film in which titanium nitride and tungsten are deposited in this order may be used. That's good.

[0220] Next, the conductor 404, the insulator 412, and the conductor 404 are removed from the upper surface of the conductor 404. The insulator that will become the insulator 406c is then removed by CMP or the like from the top surface of the insulator 410. This is done by polishing and planarizing the conductive layer that functions as the gate electrode. The body 404 can be formed in a self-aligning manner without using a lithography method. 412 and insulator 406c.

[0221] A conductor 404 having a function as a gate electrode and a Without considering the alignment accuracy of the functional conductor 416a1 and the conductor 416a2, Since the conductor 404 having the function of a gate electrode can be formed, the area of ​​the semiconductor device can be reduced. In addition, the lithography process is no longer necessary, which simplifies the production process. It is expected that this will result in improved performance (see Figures 33(A), (B) and (C)).

[0222] Next, an insulator 418 is deposited over the insulators 410, 412, and 406c. The insulator 418 is formed by sputtering, CVD, MBE or PLD, or AL. Next, the insulator 408 is formed on the insulator 418. The insulating film 408 is formed by a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method. Preferably, the insulator 408 is a plasma having oxygen. By forming an aluminum oxide film using argon, the oxygen in the plasma is treated as excess oxygen, A dopant may be added to the top surface of the insulator 418 .

[0223] At some point after the formation of the insulator that will become the insulator 408, a second heat treatment is performed. By performing a second heat treatment, the excess oxygen in the insulator 418 is removed. moves through the insulator 410, the insulator 402, and the insulator 406a to the semiconductor 406b. In addition, excess oxygen contained in the insulator 418 may cause the insulator 412 and / or the insulator 40 to 6c to the semiconductor 406b. In this way, excess oxygen passes through two routes. Since the oxygen ions move to the semiconductor 406b, the defects (oxygen vacancies) in the semiconductor 406b can be reduced. can.

[0224] Note that the second heat treatment is performed to remove excess oxygen (oxygen) contained in the insulator 418 from the semiconductor 406b. For example, the description of the first heat treatment may be referred to. Alternatively, the second heat treatment is preferably performed at a temperature lower than that of the first heat treatment. The temperature difference between the heat treatment and the second heat treatment is 20° C. or more and 150° C. or less, preferably 40° C. or more and 150° C. or less. 00° C. or less. This prevents excess oxygen (oxygen) from being released from the insulator 402. The second heat treatment can suppress the heat generation during the deposition of each layer. This may not be necessary if heat can be used to achieve both.

[0225] Next, the insulator 428 is deposited over the insulator 408. The insulator 428 is deposited by a sputtering method. The deposition can be performed by using a CVD method, an MBE method, a PLD method, an ALD method, or the like (FIG. 34 See (A), (B) and (C).

[0226] From now on, the first opening, the second opening, the third opening and the A method for forming the fourth opening will be described in detail below.

[0227] First, the conductor 417a is formed on the insulator 428. The conductor 417a is formed by sputtering. This can be done using a laser deposition method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. Next, an insulator 419a is formed on the conductor 417a. This can be done using methods such as CVD, MBE, PLD, and ALD. (See Figures 35(A), (B) and (C).)

[0228] Next, a resist mask 420 is formed on the insulator 419a by lithography or the like. Although not shown, an organic coating film is formed on the insulator 419a, and lithography is performed on the organic coating film. A resist mask 420 may be formed by a photolithography method or the like. a and the resist mask 420, the insulator 419a and the resist mask 42 The adhesion to the SiO2 film may be improved through the organic coating film (Figures 36(A), (B) and See (C). ).

[0229] Next, the insulator 419a is removed by dry etching using the resist mask. The first processing is performed until the top surface of the conductor 417a is reached to form the insulator 419. When the fabric film is formed on the insulator 419a, a method such as a dry etching method may be used before the first processing. The organic coating film can be processed by the following gas. C 4 F 6 Gas, C. 2 F 8 Gas, CF 4 Gas, SF 6 Gas or CHF 3 Using gas etc. It is possible.

[0230] The gas used in the first process is, for example, C 4 F 6 Gas, C. 2 F 8 Gas, CF 4 Gas, SF 6 Gas or CHF 3 The gases can be used alone or in combination of two or more gases. Alternatively, oxygen gas, helium gas, argon gas, hydrogen gas, etc. may be added to the above gas as appropriate. Dry etching is used for processing the organic coating film and the insulator 419. The etching equipment can be the above-mentioned dry etching equipment, but it is also possible to use parallel plate electrodes. It is preferable to use a dry etching apparatus in which high frequency power sources with different frequencies are connected to each of the electrodes. (See Figures 37(A), (B) and (C)).

[0231] Next, the conductor 417a is first etched by a dry etching method until it reaches the top surface of the insulator 428. 2 to form the conductor 417. The gas used for dry etching is, for example, C 4 F 6 Gas, C. 2 F 8 Gas, CF 4 Gas, SF 6 Gas, CHF 3 Gas, Cl 2 Gas, B. Cl 3 Gas or SiCl 4 Gases can be used alone or in combination with two or more gases. Alternatively, the above gas may be mixed with oxygen gas, helium gas, argon gas, or hydrogen gas. At this time, the resist mask 420 is etched away. The dry etching equipment is the same as that of the first process. In this manner, a hard mask having the conductor 417 and the insulator 419 is formed. (See Figures 38(A), (B) and (C).)

[0232] The hard mask may be a single layer of the conductor 417. A resist mask 420 is formed on the substrate 17a by lithography or the like, and then the second The resist mask 420 is etched and removed by the second process. Alternatively, only the resist mask 420 or the organic coating may be used without a hard mask. In some cases, a two-layer mask of the film and resist mask 420 may be used.

[0233] Next, the hard mask having the conductor 417 and the insulator 419 is used as a mask to form the insulator 4 28 is subjected to a dry etching method to form a first opening, a second opening, a third opening, and The fourth opening is processed by the third process until it reaches the top surface of the insulator 408. The gas used may be the same as that used in the first process described above. Dry etching The processing device may be the same as that used in the first processing (FIGS. 39(A), (B) and See (C). ).

[0234] Next, the insulator 408 is etched by a dry etching method to form the first opening, the second opening, the third opening, and the fourth opening. A fourth machining is performed to form the first opening and the fourth opening until the top surface of the insulator 418 is reached.

[0235] Next, the insulator 418 is dry-etched to form the first opening, the second opening, and The third opening is processed in a fifth process until it reaches the insulator 410, and the fourth opening is processed in a fourth process until it reaches the conductor 4 Perform the fifth processing step until it reaches 04.

[0236] Next, the insulator 410 is dry-etched to form a first opening that reaches the insulator 402. The sixth processing is performed until the second opening reaches the conductor 416a1. Then, the sixth processing is performed until the third opening reaches the conductor 416a2. Since the fifth process does not have the edge 410 and the conductor 404 has already been reached, the sixth process The conductor 404 is over-etched by this processing (FIGS. 40(A), (B) and See (C). ).

[0237] Since the top surface of the insulator 410 is flattened by a CMP process or the like, the first opening and The thickness of the insulator 410 is different between the second opening and the third opening. , the first opening, then the second opening and the third opening. The fourth opening is an insulating The body 410 does not have a

[0238] That is, in the sixth process, first, the insulator 410 in the second opening and the third opening is The etching reaches the conductor 416a1 or the conductor 416a2. Next, The insulator 410 in the first opening is etched down to the insulator 402. The second opening and the third opening reach the conductor 416a1 or the conductor 416a2. The time from when the first opening reaches the insulator 402 to when the second opening and the third opening The conductor 416a1 or the conductor 416a2 is over-etched. Alternatively, the fourth opening is formed by over-etching the conductor 404 during the sixth processing. will be done.

[0239] Next, the insulator 402 and the electron capture layer 303 are dry etched to form a first opening. The seventh processing is performed until the portion reaches the insulator 302. The second opening and the third opening are the first opening. Since the processing of 6 has already reached the conductor 416a1 or the conductor 416a2, The seventh process further over-etches the conductor 416a1 or the conductor 416a2. Since the fourth opening has already reached the conductor 404 by the fifth processing, The seventh process further over-etches the conductor 404 (FIG. 41(A), ( See (B) and (C).

[0240] Next, the insulator 302 is dry-etched to form a first opening extending to the conductor 310b. The eighth process is performed until the second opening and the third opening are completely closed by the sixth process. Since the conductor 416a1 or the conductor 416a2 has already been reached, the eighth processing step The conductive body 416a1 or the conductive body 416a2 is further over-etched. Since the portion has already reached the conductor 404 by the fifth process, the conductor 404 is not reached by the eighth process. The dielectric 404 is further over-etched (see FIGS. 42(A), (B) and (C)). .).

[0241] The fourth processing condition, the fifth processing condition, the sixth processing condition, the seventh processing condition and the eighth processing condition The gas used for dry etching is the same as that described above. The same gases as in the first process can be used. The dry etching equipment is the same as in the first process. A similar device can be used.

[0242] The fourth processing condition, the fifth processing condition, the sixth processing condition, the seventh processing condition and the eighth processing condition The conditions are the etching rate of the conductor 404, the etching rate of the conductor 416a1, The etching rate of the conductor 416a2 and the etching rate of the conductor 310b and the insulator By increasing the ratio of the etching rates of the conductor 408 and the electron capture layer 303, 4. Etching due to over-etching of the conductor 416a1 and the conductor 416a2 The etching rate of the conductor 404 and the etching rate of the conductor 416a1 can be suppressed. The etching rate of the conductor 416a2 and the etching rate of the conductor 310b The etching rate of the insulator 408 and the electron capture layer 303 is set to 5 or more with respect to the etching rate of the insulator 408 being 1. It is preferably 10 or more.

[0243] In addition, the third processing condition, the fourth processing condition, the fifth processing condition, the sixth processing condition, the seventh processing condition, In the first and second processing conditions, the insulator 419 and the conductor 4 17 etch rate and insulator 428, insulator 418, insulator 408, insulator 410, Increasing the ratio of the etching rates of the insulator 402, the electron trap layer 303 and the insulator 302 This suppresses changes in shape of the insulator 419 and the conductor 417 serving as a hard mask. This prevents the opening from becoming abnormally shaped. Specifically, it prevents the opening from expanding at the top. The etching rate of the insulator 419 and the conductor 417 is set to 1, and the etching rate of the insulator 42 is set to 1. 8, insulator 418, insulator 408, insulator 410, insulator 402, electron capture layer 303 and The etching rate of the insulator 302 is set to 5 or more, and preferably 10 or more.

[0244] Next, the conductor 422a is formed. The conductor 422a is formed by a sputtering method or a CVD method. The deposition can be performed by using an MBE method, a PLD method, an ALD method, or the like. The insulating film 410 is formed so as to fill the openings formed by the insulating film 410. It is preferable to use the VD method (particularly the MCVD method). In order to improve the adhesion of the conductor formed by the ALD method, It may be preferable to form a multilayer film with a conductor formed by CVD. For example, titanium nitride A multilayer film in which tungsten and tungsten are deposited in this order may be used (FIG. 43(A), ( See (B) and (C).

[0245] Next, a first CMP process is performed on the conductor 422a until it reaches the top surface of the insulator 419. Conductor 422 is formed (see Figures 44(A), (B) and (C)).

[0246] Next, the conductor 422, the insulator 419, and the conductor 417 are heated until they reach the top surface of the insulator 428. Then, a second CMP process is performed at 200° C. As a result, the first opening is filled with a conductor 433, The second opening is filled with a conductor 431, and the third opening is filled with a conductor 429. A conductor 437 is embedded in the fourth opening (FIGS. 45(A), (B) and (C)). reference.).

[0247] Next, the insulator 428, the conductor 433, the conductor 431, the conductor 429, and the conductor A conductor is formed on the substrate 437, and a part of the conductor is etched by lithography. This forms the conductor 434, the conductor 432, the conductor 430, and the conductor 438. In this manner, the transistor shown in FIG. 4 can be manufactured (FIG. 46(A), (B) and See (C).

[0248] As described above, when forming the insulator 410, the insulator 410a is formed by dry etching. The first processing is performed until the insulator 402 is reached, and the insulator 410 is formed. At this time, the insulator 402 may be etched until it reaches the electron capture layer 303. In this case, the transistor has the structure shown in Figures 47(A), (B) and (C). The above embodiment may be appropriately combined with at least a part of the other embodiments described in this specification. This can be implemented.

[0249] (Embodiment 4) <Storage device 1> A transistor according to one embodiment of the present invention is used to retain stored contents even when power is not supplied FIG. 48 shows an example of a semiconductor device (memory device) that can hold data and has no limit on the number of times it can be written. As shown in.

[0250] The semiconductor device shown in FIG. 48A includes a transistor 3200 using a first semiconductor and a The semiconductor device includes a transistor 3300 and a capacitor 3400. The transistor 3300 can be any of the transistors described above.

[0251] The transistor 3300 is preferably a transistor having a low off-state current. For example, a transistor including an oxide semiconductor can be used as the transistor 00. The small off-state current of the capacitor 3300 allows for long-term recording at a specific node of the semiconductor device. The contents of the memory can be retained, i.e., no refresh operation is required, or This allows the frequency of refresh operations to be reduced significantly, resulting in a semiconductor with low power consumption. It becomes a body device.

[0252] In FIG. 48A, a first wiring 3001 is electrically connected to the source of a transistor 3200. The second wiring 3002 is electrically connected to the drain of the transistor 3200. The third wiring 3003 is electrically connected to one of the source and drain of the transistor 3300. The fourth wiring 3004 is electrically connected to the gate of the transistor 3300. The gate of the transistor 3200 and the source of the transistor 3300 are connected to each other. The other of the drains is electrically connected to one of the electrodes of the capacitor 3400 and is connected to the fifth wiring 30 05 is electrically connected to the other electrode of the capacitor 3400 .

[0253] The semiconductor device shown in FIG. 48A can hold a gate potential of the transistor 3200. This property makes it possible to write, hold, and read information, as shown below. do.

[0254] The writing and holding of information will be described. First, the potential of the fourth wiring 3004 is changed by a transistor. The transistor 3300 is set to a potential at which the transistor 3300 is turned on. As a result, the potential of the third wiring 3003 is applied to the gate of the transistor 3200 and the The signal is applied to a node FG electrically connected to one electrode of the capacitance element 3400. A predetermined charge is applied to the gate of the transistor 3200 (write). Charges that give two potential levels (hereinafter referred to as low-level charge and high-level charge) Then, the potential of the fourth wiring 3004 is applied to the transistor. By setting the potential at which the transistor 3300 is in a non-conducting state, the transistor 3300 is in a non-conducting state. As a result, charge is held at the node FG (retention).

[0255] Since the off-state current of the transistor 3300 is small, the charge of the node FG is retained for a long period of time. It will be held.

[0256] Next, reading of information will be described. A predetermined potential (constant potential) is applied to the first wiring 3001. When an appropriate potential (read potential) is applied to the fifth wiring 3005 in this state, 3002 takes a potential according to the amount of charge held in the node FG. This is the transistor If 3200 is an n-channel type, a high-level charge is applied to the gate of transistor 3200. The apparent threshold voltage V th_H is the transistor 3200 The apparent threshold voltage V when a low-level charge is applied to the gate th_L Yo Here, the apparent threshold voltage is the voltage at which the transistor 3200 is This refers to the potential of the fifth wiring 3005 required to make it in a "conductive state." Then, the potential of the fifth wiring 3005 is V th_H and V th_L The potential V between 0 By doing so For example, in a write, the charge applied to node FG can be determined. When a high-level charge is applied to the fifth wiring 3005, the potential of the fifth wiring 3005 becomes V 0 (> V th_H ), the transistor 3200 is in a "conducting state." On the other hand, the node FG When a low-level charge is applied to the fifth wiring 3005, the potential of the fifth wiring 3005 becomes V 0 ( <V th_L ), transistor 3200 remains in a "non-conducting state." By determining the potential of the second wiring 3002, the data stored in the node FG is read. It can be put out.

[0257] When memory cells are arranged in an array, the information of a desired memory cell is read. For example, in memory cells that do not read information, The voltage applied to the FG terminal is such that the transistor 3200 is in a "non-conducting state." V th_H By applying a lower potential to the fifth wiring 3005, a desired memory It is sufficient to have a configuration in which only the information in the cell can be read. Alternatively, the memory cell from which information is not read can be configured. In this case, the transistor 3200 is in a "conducting state" regardless of the charge applied to the node FG. That is, V th_L Applying a higher potential to the fifth wiring 3005 It is only necessary to have a configuration in which only the information in a desired memory cell can be read out.

[0258] <Semiconductor device structure 1> 49 is a cross-sectional view of the semiconductor device corresponding to FIG. 48(A). The semiconductor memory device includes a transistor 3200, a transistor 3300, and a capacitor 3400. The transistor 3300 and the capacitor 3400 are disposed above the transistor 3200. The transistor 3300 is the transistor shown in FIG. However, the semiconductor device according to one embodiment of the present invention is not limited to this example. Therefore, the above description of the transistors should be referred to as appropriate.

[0259] The transistor 3200 shown in FIG. 49 is a transistor using a semiconductor substrate 450. The transistor 3200 includes a region 474a in the semiconductor substrate 450 and a region 474b in the semiconductor substrate 450. 0, an insulator 462, and a conductor 454.

[0260] In transistor 3200, regions 474a and 474b are source and The insulator 462 functions as a gate insulator. The conductor 454 also functions as a gate electrode. The resistance of the channel forming region can be controlled by applying a potential to the body 454. That is, the electric potential applied to the conductor 454 causes a conduction line between the region 474a and the region 474b. The non-conduction can be controlled.

[0261] The semiconductor substrate 450 may be, for example, a single semiconductor substrate such as silicon or germanium. or silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide A compound semiconductor substrate made of gallium oxide or the like may be used. A single crystal silicon substrate is used as 450.

[0262] The semiconductor substrate 450 is a semiconductor substrate having impurities that impart n-type conductivity. The semiconductor substrate 450 is a semiconductor substrate having an impurity that imparts p-type conductivity. In that case, the region that will become the transistor 3200 is given n-type conductivity. Alternatively, even if the semiconductor substrate 450 is an i-type, That's fine.

[0263] The upper surface of the semiconductor substrate 450 preferably has a (110) surface. The on-characteristics of the transistor 3200 can be improved.

[0264] Regions 474a and 474b are regions having impurities that impart p-type conductivity. In this manner, transistor 3200 constitutes a p-channel transistor.

[0265] Although the transistor 3200 is a p-channel transistor, The transistor 3200 may be an n-channel transistor.

[0266] Note that transistor 3200 is isolated from adjacent transistors by regions 460, etc. The region 460 is an insulating region.

[0267] The semiconductor device shown in FIG. 49 includes an insulator 464, an insulator 466, an insulator 468, and an insulator 470, insulator 472, insulator 475, insulator 402, insulator 410, and insulator 418, insulator 408, insulator 428, insulator 465, insulator 467, and insulator 469, insulator 498, conductor 480a, conductor 480b, conductor 480c, Conductor 478a, conductor 478b, conductor 478c, conductor 476a, and conductor 4 76b, conductor 476c, conductor 479a, conductor 479b, and conductor 479c. , conductor 477a, conductor 477b, conductor 477c, conductor 484a, and conductor 484b, conductor 484c, conductor 484d, conductor 483a, and conductor 483b. , a conductor 483c, a conductor 483d, a conductor 483e, a conductor 483f, and a conductor Conductor 485a, conductor 485b, conductor 485c, conductor 485d, and conductor 487. a, conductor 487b, conductor 487c, conductor 488a, conductor 488b, and conductor Conductor 488c, conductor 490a, conductor 490b, conductor 489a, and conductor 48 9b, a conductor 491a, a conductor 491b, a conductor 491c, a conductor 492a, Conductor 492b, conductor 492c, conductor 494, conductor 496, and insulator 406 a, a semiconductor 406b, and an insulator 406c.

[0268] An insulator 464 is disposed on the transistor 3200. Also, an insulator 466 is disposed on the insulator 4 64. Insulator 468 is disposed on insulator 466. Insulator 4 70 is disposed on the insulator 468. Also, insulator 472 is disposed on the insulator 470. In addition, the insulator 475 is disposed over the insulator 472. The transistor 3300 is also The insulator 418 is disposed on the transistor 3300. The insulator 408 is disposed on the insulator 418. The insulator 428 is disposed on the insulator 418. 08. In addition, the insulator 465 is disposed on the insulator 428. In addition, the capacitive element The capacitor 3400 is disposed on the insulator 465. The insulator 469 is disposed on the capacitor 3400. is placed on top.

[0269] The insulator 464 has an opening reaching the region 474a, an opening reaching the region 474b, and a conductive The openings each include a conductor 480a, a conductor 480b, and an opening that reaches the conductor 454. The conductive body 480b or the conductive body 480c is embedded therein.

[0270] In addition, the insulator 466 has an opening that reaches the conductor 480a and an opening that reaches the conductor 480b. The openings each have a conductor 480c. 478a, conductor 478b or conductor 478c is embedded therein.

[0271] Further, the insulator 468 has an opening that reaches the conductor 478a and an opening that reaches the conductor 478b. The openings each have a conductor 478c. 476a, conductor 476b or conductor 476c is embedded.

[0272] In addition, a conductor 479a in contact with the conductor 476a, a conductor 476b, and a The conductor 479b is in contact with the conductor 476c, and the conductor 479c is in contact with the conductor 476c. Insulator 472 has an opening through insulator 470 to conductor 479a and an opening through insulator 470 to conductor 479b. an opening through insulator 470 to conductor 479b and an opening through insulator 470 to conductor 479c The openings each include a conductor 477a, a conductor 477b, and a has a conductor 477c embedded therein.

[0273] The insulator 475 has an opening overlapping a channel formation region of the transistor 3300 and a conductive An opening reaching conductor 477a, an opening reaching conductor 477b, and an opening reaching conductor 477c. The openings are provided with openings that reach the insulator 472 and openings that reach the insulator 473. The conductor 484a, the conductor 484b, the conductor 484c, or the conductor 484d is embedded. There are.

[0274] The conductor 484d also functions as a bottom gate electrode of the transistor 3300. Alternatively, for example, a constant potential may be applied to the conductor 484d. Alternatively, the electrical characteristics of the transistor 3300, such as the threshold voltage, may be controlled. The conductor 484d and the top gate electrode of the transistor 3300 may be electrically connected. This makes it possible to increase the on-state current of the transistor 3300. In addition, the punch-through phenomenon can be suppressed, so that the transistor 3300 is in the saturation region. This makes it possible to stabilize the electrical characteristics in the

[0275] Further, the insulator 402 has an opening that reaches the conductor 484a and an opening that reaches the conductor 484b. 484c and an opening that reaches conductor 484c.

[0276] In addition, the insulator 428 is a conductor that is formed by combining the insulators 408, 418, 410, and 402. An opening through the insulator 408, the insulator 418, and the insulator 410 and an opening through insulator 402 to conductor 484c, insulator 408, insulator 4 18 and through the insulator 410 to the source or drain electrode of the transistor 3300 The two openings reach one of the conductors of the transistor through the insulator 408 and the insulator 418. An opening reaching the conductor of the gate electrode of the transistor 3300, an insulator 408, an insulator 418, and an opening through insulator 410 and insulator 402 to conductor 484b. The openings are provided with a conductor 483a, a conductor 483b, a conductor 483c, and a conductor 483e, conductor 483f, or conductor 483d is embedded.

[0277] In addition, a conductor 485a in contact with the conductors 483a and 483e and a conductor A conductor 485b in contact with the conductor 483b, a conductor 485c in contact with the conductor 483f, and a conductor 485b in contact with the conductor 483c and the conductor 483f The insulator includes a conductor 485c and a conductor 485d in contact with the conductor 483d. 465 has an opening that reaches the conductor 485a, an opening that reaches the conductor 485b, and a conductor The openings are provided with conductors 487a and 485c. Electrical conductor 487b or electrical conductor 487c is embedded therein.

[0278] In addition, a conductor 488a in contact with the conductor 487a and a conductor 488b in contact with the conductor 487b are provided on the insulator 465. The conductor 488b is in contact with the conductor 487c, and the conductor 488c is in contact with the conductor 487c. The edge 467 has an opening that reaches the conductor 488a and an opening that reaches the conductor 488b. In addition, a conductor 490a or a conductor 490b is embedded in the opening. The conductor 488c is in contact with the conductor 494 of one electrode of the capacitor 3400. There are.

[0279] In addition, a conductor 489a in contact with the conductor 490a, a conductor 490b, and a The insulator 469 has an opening that reaches the conductor 489a and a conductor 489b that contacts the conductor 489a. an opening that reaches the conductor 489b; and a conductor that is the other electrode of the capacitor 3400. The openings each include a conductor 491a and a conductor 496. The conductive body 491b or the conductive body 491c is embedded therein.

[0280] In addition, a conductor 492a in contact with the conductor 491a and a conductor 491b are provided on the insulator 469. conductor 492b in contact with conductor 491c, and conductor 492c in contact with conductor 491c.

[0281] Insulator 464, insulator 466, insulator 468, insulator 470, insulator 472, insulator 47 5, insulator 402, insulator 410, insulator 408, insulator 428, insulator 465, insulator The insulator 467, the insulator 469 and the insulator 498 may be, for example, boron, carbon, nitrogen, oxygen, etc. , fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, Germanium, yttrium, zirconium, lanthanum, neodymium, hafnium or tantalum For example, the insulator 401 may be made of a single layer or a multilayer structure containing tantalum. Examples include aluminum oxide, magnesium oxide, silicon oxide, silicon oxynitride, and oxynitride. Silicon oxide, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, Zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide or tantalum oxide That's good.

[0282] Insulator 464, insulator 466, insulator 468, insulator 470, insulator 472, insulator 47 5, insulator 402, insulator 410, insulator 408, insulator 428, insulator 465, insulator One or more of the insulators 467, 469, and 498 are used to filter impurities such as hydrogen and oxygen. It is preferable to have an insulator having a locking function. By disposing an insulator that has the function of blocking impurities such as hydrogen and oxygen, This allows the electrical characteristics of the transistor 3300 to be stable.

[0283] Examples of insulators that have the function of blocking impurities such as hydrogen and oxygen include boron. Element, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, Argon, Gallium, Germanium, Yttrium, Zirconium, Lanthanum, Neodymium Insulators containing hafnium or tantalum may be used in a single layer or in a multilayer.

[0284] Conductor 480a, conductor 480b, conductor 480c, conductor 478a, conductor 478b , conductor 478c, conductor 476a, conductor 476b, conductor 476c, conductor 479a , conductor 479b, conductor 479c, conductor 477a, conductor 477b, conductor 477c , conductor 484a, conductor 484b, conductor 484c, conductor 484d, conductor 483a , conductor 483b, conductor 483c, conductor 483d, conductor 483e, conductor 483 f, conductor 485a, conductor 485b, conductor 485c, conductor 485d, conductor 487 a, conductor 487b, conductor 487c, conductor 488a, conductor 488b, conductor 488 c, conductor 490a, conductor 490b, conductor 489a, conductor 489b, and conductor 4 91a, conductor 491b, conductor 491c, conductor 492a, conductor 492b, conductor 4 92c, the conductor 494 and the conductor 496 are, for example, boron, nitrogen, oxygen, fluorine, Elements, silicon, phosphorus, aluminum, titanium, chromium, manganese, cobalt, nickel, Copper, zinc, gallium, yttrium, zirconium, molybdenum, ruthenium, silver, indium Conductors containing one or more of tungsten, tin, tantalum and tungsten are used in a single layer or laminate. For example, the layer may be an alloy or a compound, and may be a conductor containing aluminum, Conductors containing copper and titanium, conductors containing copper and manganese, conductors containing indium, tin and Conductors containing oxygen, conductors containing titanium and nitrogen, etc. may also be used.

[0285] The semiconductor 406b is preferably an oxide semiconductor. (including silicon), germanium, silicon germanium, silicon carbide, gallium arsenide, Aluminum gallium arsenide, indium phosphide, gallium nitride, or organic semiconductors There are cases where this is acceptable.

[0286] The insulator 406a and the insulator 406c are formed of an element other than oxygen that constitutes the semiconductor 406b. It is preferable to use an oxide composed of one or more elements, or two or more elements. Silicon (including distorted silicon), germanium, silicon germanium, silicon carbide, gallium aluminum gallium arsenide, indium phosphide, gallium nitride or organic semiconductor etc. may be used.

[0287] The source or drain of transistor 3200 is connected to conductor 480a and conductor 478a. , conductor 476a, conductor 479a, conductor 477a, conductor 484a, and conductor The transistor 3300 is connected to the source 483a, the conductor 485a, and the conductor 483e. It is electrically connected to a conductor that is either the source electrode or the drain electrode of a transistor. The conductor 454, which is the gate electrode of the transistor 3200, is made up of a conductor 480c, a conductor 478c, and Conductor 476c, conductor 479c, conductor 477c, conductor 484c, and conductor 4 The source of the transistor 3300 is connected to the source of the transistor 3300 via the conductor 83c, the conductor 485c, and the conductor 483f. The electrode is electrically connected to the other conductor, which is the source electrode or the drain electrode.

[0288] The capacitor 3400 is connected to one of the source electrode and the drain electrode of the transistor 3300. 483c, 485c, 487c, and 488c. A conductor 494 electrically connected to one electrode of the capacitor 3400 through an insulator 498 and a conductor 496 which is the other electrode of the capacitor 3400. 400 is formed above or below the transistor 3300, thereby reducing the size of the semiconductor device. This is advantageous because it can reduce the size.

[0289] For other structures, please refer to the descriptions in Figure 4 etc. as appropriate.

[0290] The semiconductor device shown in FIG. 50 is the same as the transistor 3200 of the semiconductor device shown in FIG. Only the structure is different. Therefore, the semiconductor device shown in FIG. Please refer to the description of the semiconductor device. Specifically, the semiconductor device shown in FIG. The transistor 200 is a Fin type. As a result, the effective channel width is increased, improving the on-characteristics of the transistor 3200. In addition, the contribution of the electric field of the gate electrode can be increased, The off-characteristics of the transistor 3200 can be improved. may be either a p-channel transistor or an n-channel transistor.

[0291] In this embodiment, a transistor 3300 is provided over a transistor 3200. Although an example of a semiconductor device having a capacitor element 3400 on a transistor 3300 has been shown, A structure having one or more transistors having a semiconductor similar to the transistor 3300 on the substrate 200. Such a configuration can further increase the integration degree of the semiconductor device. can be done.

[0292] <Storage device 2> The semiconductor device shown in FIG. 48B differs from the semiconductor device shown in FIG. 48A in that it does not include the transistor 3200. In this case, the operation is the same as that of the semiconductor device shown in FIG. This makes it possible to write and retain information more easily.

[0293] The reading of data in the semiconductor device shown in FIG. When the capacitor 3300 is turned on, the third wiring 3003 and the capacitor element 3400, which are in a floating state, The third wiring 3003 and the capacitor 3400 are electrically connected to each other, and electric charges are redistributed between the third wiring 3003 and the capacitor 3400. As a result, the potential of the third wiring 3003 changes. The amount of change in the potential of the third wiring 3003 is expressed by the capacitance The potential of one electrode of the element 3400 (or the charge stored in the capacitor element 3400) , take different values.

[0294] For example, the potential of one electrode of the capacitor 3400 is V, the capacitance of the capacitor 3400 is C, The capacitance component of the third wiring 3003 before the charge is redistributed is CB. If the potential is VB0, the potential of the third wiring 3003 after the charge is redistributed is (CB× VB0+C×V) / (CB+C). Therefore, the state of the memory cell is If the potential of one electrode of the element 3400 is in two states, V1 and V0 (V1>V0), , the potential of the third wiring 3003 when the potential V1 is held (=(CB×VB0+C×V 1) / (CB+C)) is the potential of the third wiring 3003 when the potential V0 is held (= It can be seen that it is higher than (CB×VB0+C×V0) / (CB+C)).

[0295] Then, the potential of the third wiring 3003 is compared with a predetermined potential, thereby reading out information. can be done.

[0296] In this case, the transistor in which the first semiconductor is applied to a driving circuit for driving the memory cell. A transistor in which a second semiconductor is applied is used as the transistor 3300. The structure may be such that the electrodes are stacked on the driving circuit.

[0297] The above-described semiconductor device uses a transistor including an oxide semiconductor and has low off-state current. By doing so, it is possible to retain the memory contents for a long period of time. This eliminates the need for refresh operations or makes it possible to reduce the frequency of refresh operations significantly. Therefore, a semiconductor device with low power consumption can be realized. Even if the potential is fixed, it is possible to store the potential for a long period of time. It is possible to maintain the capacity.

[0298] In addition, the semiconductor device does not require a high voltage to write information, so that deterioration of the elements does not occur. For example, unlike conventional non-volatile memory, injection of electrons into the floating gate Since electrons are not introduced or removed from the floating gate, there is no risk of degradation of the insulator. That is, the semiconductor device according to one embodiment of the present invention does not have the problem of a conventional nonvolatile memory. A semiconductor device with dramatically improved reliability, without the problematic limit on the number of times it can be rewritten Furthermore, information is written depending on whether the transistor is conductive or non-conductive. This embodiment is at least partially described in the present specification. The present invention can be implemented in appropriate combination with other embodiments described above.

[0299] (Embodiment 5) <Structure of semiconductor device 2> In this embodiment, an example of a circuit using a transistor of one embodiment of the present invention is shown in FIG. Please refer to the following for explanation. <Cross-sectional structure> 51A and 51B are cross-sectional views of a semiconductor device according to one embodiment of the present invention. In FIG. 51(B), the X1-X2 direction is the channel length direction, and in FIG. 51(B), the Y1-Y2 direction is The semiconductor device shown in Figures 51(A) and (B) has a first semiconductor layer at the bottom. A transistor 2200 made of a conductive material is provided on top of a transistor made of a second semiconductor material. In FIG. 51(A) and (B), the second semiconductor material is used. As the transistor 2100, the transistor illustrated in FIG. 4 is used. .

[0300] The first and second semiconductor materials preferably have different band gaps. For example, the first semiconductor material may be a semiconductor material other than an oxide semiconductor (silicon (including strained silicon)). (including germanium, silicon germanium, silicon carbide, gallium arsenide, aluminum arsenide) The second semiconductor is a The body material can be an oxide semiconductor. On the other hand, transistors using oxide semiconductors can operate at high speed. The transistor can be an excellent substrate by applying the transistor exemplified in the above embodiment. It is possible to obtain threshold characteristics and make a fine transistor. The fast switching speed allows for high-speed operation, and the low off-state current reduces leakage current.

[0301] The transistor 2200 may be an n-channel transistor or a p-channel transistor. Either transistor or transistors may be used, and an appropriate transistor may be used depending on the circuit. In addition to using a transistor according to one embodiment of the present invention using a nitride semiconductor, other materials and structures are not required. For example, the specific configuration of the semiconductor device is not necessarily limited to that shown here.

[0302] In the configuration shown in FIGS. 51(A) and (B), an insulator 22 is provided on the top of the transistor 2200. 01, a transistor 2100 is provided through an insulator 2207 and an insulator 2208. In addition, a plurality of wirings 220 are provided between the transistor 2200 and the transistor 2100. 2. Also, a number of plugs 2203 embedded in various insulators are provided. The wiring and electrodes on the upper and lower layers are electrically connected. An insulator 2204 is provided to cover the capacitor 2100, and a wiring 2205 is provided on the insulator 2204. There are.

[0303] In this way, by stacking two types of transistors, the area occupied by the circuit is reduced, Multiple circuits can be arranged at higher density.

[0304] Here, when a silicon-based semiconductor material is used for the transistor 2200 provided in the lower layer, The hydrogen in the insulator provided near the semiconductor film of the transistor 2200 is a silicon dung. This has the effect of terminating the ring bond and improving the reliability of the transistor 2200. When an oxide semiconductor is used for the transistor 2100 provided in the upper layer, the transistor 21 Hydrogen in the insulator provided near the semiconductor film of 00 generates carriers in the oxide semiconductor. This may be one of the factors that reduces the reliability of the transistor 2100. Therefore, the upper layer of the transistor 2200 using a silicon-based semiconductor material is oxidized. When the transistor 2100 using a semiconductor is stacked, hydrogen diffusion between the transistors may occur. It is particularly effective to provide an insulator 2207 having a function of preventing the above-mentioned. 7, the reliability of the transistor 2200 is improved by confining hydrogen in the lower layer. In addition, the diffusion of hydrogen from the lower layer to the upper layer is suppressed, so that the transistor 2100 At the same time, reliability can be improved.

[0305] The insulator 2207 may be, for example, aluminum oxide, aluminum oxynitride, or gallium oxide. , gallium oxide nitride, yttrium oxide, yttrium oxide nitride, hafnium oxide, Hafnium nitride, yttria stabilized zirconia (YSZ), etc. can be used.

[0306] In addition, a transistor 2100 including an oxide semiconductor film is formed so as to cover the transistor 2100. It is preferable to form a blocking film having a function of preventing hydrogen diffusion on the substrate 2100. The blocking film can be made of the same material as the insulator 2207, and in particular, It is preferable to apply aluminum oxide, which dissolves the underlying insulating layer during its deposition. Excess oxygen can be added to the semiconductor substrate, and a thermal process can be used to convert the excess oxygen into the transistor 210. The oxygen ions migrate to the oxide semiconductor layer of 0, and have the effect of repairing defects in the oxide semiconductor layer. The aluminum oxide membrane is impermeable to both impurities such as hydrogen and moisture, and oxygen. Therefore, the blocking effect of the transistor 2100 is high. By using an aluminum oxide film as the backing film, the oxide film included in the transistor 2100 This prevents oxygen from being released from the oxide semiconductor film and prevents water and hydrogen from being mixed into the oxide semiconductor film. The blocking film can prevent the intrusion of the insulator 2204. 2204 , or may be provided underneath the insulator 2204 .

[0307] It should be noted that the transistor 2200 is not limited to a planar type transistor, but may be of various types. For example, FIN type, TRI-GATE type, In this case, the transistor may be a ligate type transistor. As shown in Figures 51(E) and (F), an insulator 2212 is provided on a semiconductor substrate 2211. The semiconductor substrate 2211 has a narrow protrusion (also called a fin). An insulator may be provided on the protrusion. When the protrusion is formed, the insulator is It acts as a mask to prevent the semiconductor substrate 2211 from being etched. The protrusion does not have to have a thin tip, and may be, for example, a substantially rectangular parallelepiped protrusion. The protrusion of the semiconductor substrate 2211 may have a gate insulator on the protrusion. 2214 is provided on the semiconductor substrate 2, and a gate electrode 2213 is provided thereon. A source region and a drain region 2215 are formed in the semiconductor substrate 211. In the above example, the semiconductor substrate 2211 has a protruding portion. For example, a semiconductor region having a protrusion is formed by processing an SOI substrate. It is acceptable to do so.

[0308] This embodiment may be appropriately combined with at least a part of other embodiments described in this specification. It can be implemented together.

[0309] (Embodiment 6) [CMOS Circuits] The circuit diagram shown in FIG. 51(C) includes a p-channel transistor 2200 and an n-channel transistor 2201. Transistor 2100 is connected in series and each gate is connected. The configuration of the S circuit is shown.

[0310] [Analog Switch] The circuit diagram shown in FIG. 51(D) is that of a transistor 2100 and a transistor 2200. The source and drain of each transistor are connected. This embodiment can function as a so-called analog switch. Part of the above may be implemented in appropriate combination with other embodiments described in this specification. .

[0311] (Embodiment 7) <cpu> The following describes a CPU including the above-mentioned transistor and the above-mentioned semiconductor device such as the memory device. I will explain this in more detail.

[0312] FIG. 52 is a block diagram showing the configuration of an example of a CPU that uses the above-mentioned transistor in part. be.

[0313] The CPU shown in FIG. 52 includes an ALU 1191 (ALU: Arithmetic Unit) on a board 1190. ic logic unit, arithmetic circuit), ALU controller 1192, instruction A timing decoder 1193, an interrupt controller 1194, and a timing controller 1195, register 1196, register controller 1197, bus interface 1 198, rewritable ROM 1199, and ROM interface 1189 The substrate 1190 may be a semiconductor substrate, an SOI substrate, a glass substrate, or the like. 199 and the ROM interface 1189 may be provided on a separate chip. The CPU shown in FIG. 52 is merely an example showing a simplified configuration. There are many different configurations depending on the application. For example, the CPU or arithmetic circuit shown in FIG. A configuration including the above is considered as one core, and multiple such cores are included, and each core operates in parallel. The number of bits that the CPU can handle in the internal arithmetic circuit and data bus is as follows: For example, it can be 8-bit, 16-bit, 32-bit, 64-bit, etc.

[0314] The instructions input to the CPU via the bus interface 1198 are The signal is input to the decoder 1193, decoded, and then passed to the ALU controller 1192, the interface Rupture Controller 1194, Register Controller 1197, Timing Controller Entered into 1195.

[0315] ALU controller 1192, interrupt controller 1194, register controller The controller 1197 and the timing controller 1195 control various Specifically, the ALU controller 1192 controls the operation of the ALU 1191. The interrupt controller 1194 also generates signals for the CPU program. During system execution, interrupt requests from external I / O devices and peripheral circuits are handled according to their priority and mask. The register controller 1197 determines the address of the register 1196 and processes it. It generates addresses and reads and writes to register 1196 depending on the state of the CPU.

[0316] In the CPU shown in FIG. 52, a memory cell is provided in a register 1196. The above-mentioned transistors and memory devices can be used as the memory cells of 1196. do.

[0317] In the CPU shown in FIG. 52, the register controller 1197 receives the According to the instruction, the holding operation is selected in the register 1196. In the memory cell of the Select whether to hold data by flip-flops. If the power supply voltage is set to 0, the power supply voltage is supplied to the memory cells in the register 1196. If data retention is selected for the capacitive element, data is rewritten to the capacitive element. This allows the supply of power supply voltage to the memory cells in the register 1196 to be stopped.

[0318] FIG. 53 is an example of a circuit diagram of a storage element that can be used as the register 1196. The memory element 1200 includes a circuit 1201 in which stored data is volatilized when the power is cut off, and a circuit 1202 in which stored data is volatilized when the power is cut off. A non-volatile circuit 1202, a switch 1203, a switch 1204, and a logic element The circuit includes a transistor 1206, a capacitor 1207, and a circuit 1220 having a selection function. 1202 includes a capacitor element 1208, a transistor 1209, and a transistor 1210. The memory element 1200 may include a diode, a resistor, an inductor, etc., as necessary. The semiconductor device may further include other elements such as a capacitor.

[0319] Here, the above-mentioned memory device can be used for the circuit 1202. When the supply of power supply voltage to the ND (0V) or a potential at which the transistor 1209 is turned off is continuously input. For example, the gate of the transistor 1209 is grounded via a load such as a resistor. .

[0320] The switch 1203 uses a transistor 1213 of one conductivity type (for example, an n-channel type). The switch 1204 is configured as a transistor of the opposite conductivity type (for example, a p-channel type). An example using a transistor 1214 is shown. Here, the first terminal of the switch 1203 The input corresponds to one of the source and drain of the transistor 1213, and the second input of the switch 1203. The terminal of corresponds to the other of the source and drain of the transistor 1213, and the switch 1203 A control signal RD input to the gate of the transistor 1213 switches the first terminal and the second terminal Conduction or non-conduction between the terminals (i.e., the conductive or non-conductive state of the transistor 1213) The first terminal of the switch 1204 is connected to the source and drain of a transistor 1214. The second terminal of the switch 1204 corresponds to one of the drains of the The switch 1204 is connected to the gate of the transistor 1214. A control signal RD is input to the first terminal and the second terminal to establish or break continuity (i.e., The conductive or non-conductive state of transistor 1214 is selected.

[0321] One of the source and drain of the transistor 1209 is connected to a pair of electrodes of the capacitor 1208. The connection part is electrically connected to one of the gate electrodes of the transistor 1210 and the gate of the transistor 1210. The node M2 ​​is connected to the source or drain of the transistor 1210. The other is electrically connected to a wiring (for example, a GND line) that can supply 1203 (one of the source and drain of the transistor 1213). The second terminal of the switch 1203 (the source and drain of the transistor 1213) is connected to the The other terminal of the switch 1204 (one of the source and drain terminals of the transistor 1214) The second terminal of the switch 1204 (the source terminal of the transistor 1214) is electrically connected to the The other of the source and drain terminals is electrically connected to a wiring that can supply the power supply potential VDD. The second terminal of the switch 1203 (the other of the source and drain of the transistor 1213) ) and a first terminal of the switch 1204 (one of the source and drain of the transistor 1214 ), an input terminal of a logic element 1206, and one of a pair of electrodes of a capacitor 1207; are electrically connected. Here, the connection point is referred to as node M1. The other of the electrodes may be configured to have a constant potential input thereto. It can be configured so that a power supply potential (GND, etc.) or a high power supply potential (VDD, etc.) is input. The other of the pair of electrodes of the capacitor 1207 is connected to a line that can supply a low power supply potential. The other of the pair of electrodes of the capacitor 1208 is electrically connected to a line (for example, a GND line). For example, a low power supply potential (such as GND) can be input. ) or a high power supply potential (such as VDD) can be input to the capacitance element 120. The other of the pair of electrodes 8 is connected to a wiring capable of supplying a low power supply potential (for example, GND The power supply is electrically connected to the power supply line.

[0322] The capacitors 1207 and 1208 are used to reduce parasitic capacitance of transistors and wirings. It is possible to omit it by making active use of it.

[0323] A control signal WE is input to a first gate (first gate electrode) of the transistor 1209. The switch 1203 and the switch 1204 are connected to a control signal RD, which is different from the control signal WE. A conductive state or a non-conductive state between the first terminal and the second terminal is selected by When the first terminal and the second terminal of one switch are in a conductive state, the first terminal and the There is no continuity between the two terminals.

[0324] The other of the source and drain of the transistor 1209 is connected to a data register 1204. In FIG. 53, the signal output from the circuit 1201 corresponds to the The example shown is input to the other of the source and drain of the switch 1203. The signal output from the second terminal (the other of the source and drain of the transistor 1213) is The logic value is inverted by the logic element 1206 to become an inverted signal, and the inverted signal is output via the circuit 1220. and input to the circuit 1201.

[0325] In FIG. 53, the second terminal of the switch 1203 (the source and drain of the transistor 1213) The signal output from the other of the two trains is routed through logic element 1206 and circuit 1220. The second terminal of the switch 1203 is connected to the first terminal of the switch 1203. The signal output from the other of the source and drain of the transistor 1213 is inverted. For example, the following may be included in the circuit 1201: When there is a node that holds a signal with the inverted logical value of the signal input from the input terminal The second terminal of the switch 1203 (the other of the source and drain of the transistor 1213) A signal output from the input terminal can be input to the node.

[0326] In addition, in FIG. 53, among the transistors used in the memory element 1200, The transistors other than the transistor 1209 are made of a film or a substrate 119 made of a semiconductor other than an oxide semiconductor. For example, a transistor having a channel formed at 0 can be used. The transistor may have a channel formed in a silicon substrate. All the transistors used in 1200 are transistors whose channels are formed of oxide semiconductors. Alternatively, the memory element 1200 may include other elements besides the transistor 1209. The other transistors may include a transistor in which the channel is formed of an oxide semiconductor. The transistor has a channel formed in a layer or substrate 1190 made of a semiconductor other than an oxide semiconductor. Alternatively, the transistor may be a transistor having a capacitance of 100 .mu.m.

[0327] For example, a flip-flop circuit can be used for the circuit 1201 in FIG. The logic element 1206 may be, for example, an inverter or a clocked inverter. It is possible.

[0328] In the semiconductor device according to one embodiment of the present invention, while a power supply voltage is not supplied to the memory element 1200, The data stored in the circuit 1201 is transferred to the capacitor 1208 in the circuit 1202. It can be held by

[0329] In addition, a transistor in which a channel is formed in an oxide semiconductor has an extremely small off-state current. For example, the off-state current of a transistor in which a channel is formed in an oxide semiconductor The off-current is significantly lower than that of transistors with a channel formed in silicon. By using this transistor as the transistor 1209, the memory element 120 The signal held in the capacitance element 1208 is maintained for a long period of time even while the power supply voltage is not supplied to the In this way, the memory element 1200 can retain its stored contents (data) even when the supply of power supply voltage is stopped. ) can be held.

[0330] In addition, by providing the switches 1203 and 1204, the precharge operation Since the circuit 1201 is a memory element that performs the above-mentioned operation after the power supply voltage is restarted, This shortens the time it takes to restore the original data.

[0331] In the circuit 1202, the signal held by the capacitor 1208 is The power supply voltage to the memory element 1200 is then restarted. After that, the signal held by the capacitance element 1208 is converted into the state of the transistor 1210 ( The state can be converted to a conductive state or a non-conductive state and read out from the circuit 1202. Therefore, even if the potential corresponding to the signal held in the capacitance element 1208 fluctuates slightly, the original signal It is possible to read out the number accurately.

[0332] Such a memory element 1200 may be a register or a cache memory of a processor. By using it in a storage device, it is possible to prevent data loss in the storage device due to a power supply interruption. In addition, after the supply of power voltage is resumed, the state before the power supply was stopped can be restored in a short time. Therefore, the entire processor, or one or more components of the processor, Since the power supply can be stopped for a short period of time in multiple logic circuits, power consumption can be reduced. It can be suppressed.

[0333] Although the memory element 1200 has been described as being used as a CPU, the memory element 1200 can also be used as a DSP ( Digital Signal Processor), Custom LSI, PLD (Pr LSIs such as rogrammable logic devices, RF tags (Rad It can also be applied to the IO Frequency Tag.

[0334] This embodiment may be appropriately combined with at least a part of other embodiments described in this specification. It can be implemented together.

[0335] (Embodiment 8) <Imaging device> FIG. 54(A) is a top view illustrating an example of an imaging device 200 according to one embodiment of the present invention. The device 200 includes a pixel section 210, a peripheral circuit 260 for driving the pixel section 210, and a peripheral circuit The pixel section 210 has p rows and q columns. (p and q are integers of 2 or more) have a plurality of pixels 211 arranged in a matrix. The peripheral circuits 260, 270, 280, and 290 each include a plurality of The pixel 211 is connected to the pixel 211 and has a function of supplying a signal for driving the pixel 211. In this specification, the peripheral circuits 260, 270, 280, and and peripheral circuit 290 may be referred to as a "peripheral circuit" or a "drive circuit." For example, peripheral circuit 260 may be considered a part of the peripheral circuit.

[0336] The imaging device 200 preferably also includes a light source 291. The light source 291 emits detection light P It can emit 1.

[0337] The peripheral circuits include at least a logic circuit, a switch, a buffer, an amplifier, or a converter. The peripheral circuits may be formed on the substrate on which the pixel portion 210 is formed. Also, a semiconductor device such as an IC chip may be used for part or all of the peripheral circuits. The peripheral circuits are a peripheral circuit 260, a peripheral circuit 270, a peripheral circuit 280, and a peripheral circuit 290. Any one or more of these may be omitted.

[0338] Also, as shown in FIG. 54B, in the pixel section 210 of the imaging device 200, By arranging the pixels 211 at an angle, the pixel size in the row direction and the pixel size in the pixel area can be increased. The pixel interval (pitch) in the column direction can be shortened. This can further improve the quality of the captured images.

[0339] <Pixel configuration example 1> The imaging device 200 has one pixel 211 that is composed of a plurality of sub-pixels 212. The pixel 212 is combined with a filter (color filter) that transmits light of a specific wavelength band. By this, it is possible to obtain information for realizing a color image display.

[0340] FIG. 55(A) is a top view showing an example of a pixel 211 for acquiring a color image. The pixel 211 shown in FIG. 55(A) is provided with a color filter that transmits light in the red (R) wavelength band. The subpixel 212 (hereinafter also referred to as "subpixel 212R") receives light in the green (G) wavelength band. A subpixel 212 (hereinafter, also referred to as “subpixel 212G”) is provided with a color filter that transmits A subpixel 212 is provided with a color filter that transmits light in the blue (B) and blue (C) wavelength bands. (hereinafter, also referred to as "subpixel 212B"). The subpixel 212 has a photo sensor. It can be made to function.

[0341] The subpixels 212 (subpixels 212R, 212G, and 212B) are connected to the wiring 23 1, electrically connected to wiring 247, wiring 248, wiring 249, and wiring 250. The pixel 212R, the sub-pixel 212G, and the sub-pixel 212B are each connected to an independent wiring 25 3. In this specification, for example, The wiring 248 and the wiring 249 are respectively represented as wiring 248[n] and wiring 249[n]. For example, the wiring 253 connected to the pixel 211 in the mth column is designated as wiring 253[m]. In FIG. 55A, the sub-pixel 212R of the pixel 211 in the m-th column is written as The wiring 253 connected to the subpixel 212G is disposed as wiring 253[m]R. The wiring 253 connected to the line 253[m]G and the subpixel 212B is referred to as a wiring 253[m]B. The subpixel 212 is electrically connected to the peripheral circuit via the wiring.

[0342] In addition, the imaging device 200 detects color filters of adjacent pixels 211 that transmit light of the same wavelength band. The sub-pixels 212 provided with filters are electrically connected to each other via switches. In Figure 55(B), there are n rows (n is an integer between 1 and p) and m columns (m is an integer between 1 and q). A sub-pixel 212 of the pixel 211 arranged in the pixel 211 and a sub-pixel 212 of the pixel 211 arranged in the pixel 211 arranged in the pixel 211 arranged in the pixel 211 arranged in the pixel 211 arranged in the pixel 212 ... 55B shows an example of a connection of the sub-pixels 212 of the arranged pixel 211. In FIG. The sub-pixel 212R arranged in row m and column m and the sub-pixel 212R arranged in row (n+1) and column m are switched. The sub-pixels 212A and 212B are connected to each other via a switch 201. The sub-pixel 212G arranged in the +1 row and the m column is connected via the switch 202. , the sub-pixel 212B arranged in the nth row and the mth column, and the sub-pixel 212B arranged in the n+1th row and the mth column They are connected via a switch 203 .

[0343] The color filters used for the subpixels 212 are not limited to red (R), green (G), and blue (B). The color filters transmit cyan (C), yellow (Y) and magenta (M) light respectively. A single pixel 211 may have three sub-pixels for detecting light of different wavelength bands. By providing 212, a full color image can be obtained.

[0344] Alternatively, color filters that transmit red (R), green (G) and blue (B) light are provided. In addition to the sub-pixel 212, a sub-pixel having a color filter that transmits yellow (Y) light is provided. Alternatively, pixel 211 may be used with pixel 212, or with cyan (C), yellow (Y In addition to the subpixel 212 provided with a color filter that transmits light of red (A) and magenta (M), The pixel 21 has a sub-pixel 212 provided with a color filter that transmits blue (B) light. A single pixel 211 may include sub-pixels 211 for detecting light of four different wavelength bands. By providing the second filter 12, the color reproducibility of the captured image can be further improved.

[0345] For example, in FIG. 55A, the sub-pixel 212 detects light in the red wavelength band, A subpixel 212 for detecting light in a wavelength band, and a subpixel 212 for detecting light in a blue wavelength band. The pixel ratio (or light receiving area ratio) does not have to be 1:1:1. For example, A Bayer array with a light receiving area ratio of red:green:blue=1:2:1 may be used. The pixel number ratio (light receiving area ratio) may be red:green:blue=1:6:1.

[0346] The number of sub-pixels 212 provided in the pixel 211 may be one, but it is preferable that the number is two or more. By providing two or more sub-pixels 212 that detect light in the same wavelength band, redundancy is increased and imaging is simplified. This can improve the reliability of the imaging device 200.

[0347] In addition, IR (IR: Infrared) filters absorb or reflect visible light and transmit infrared light. By using a filter, it is possible to realize an imaging device 200 that detects infrared light.

[0348] In addition, ND (Neutral Density) filters are used. This prevents output saturation that occurs when a large amount of light is incident on the photoelectric conversion element (light receiving element). By combining ND filters with different light reduction levels, This allows the dynamic range of the device to be increased.

[0349] In addition to the above-mentioned filter, a lens may be provided in the pixel 211. An example of the arrangement of the pixel 211, the filter 254, and the lens 255 will be described with reference to a cross-sectional view. By providing the lens 255, the photoelectric conversion element can efficiently receive incident light. Specifically, as shown in FIG. 56(A), a lens 255 and a filter 25 formed in a pixel 211 4 (filter 254R, filter 254G and filter 254B), and pixel circuit 2 30 or the like, light 256 can be made incident on the photoelectric conversion element 220.

[0350] However, as shown in the area surrounded by the dashed line, a part of the light 256 indicated by the arrow is Therefore, as shown in Figure 56(B), A lens 255 and a filter 254 are disposed on the conversion element 220 side. It is preferable that the light 256 is received efficiently from the photoelectric conversion element 220 side. By making the light incident on the photoelectric conversion element 220, the imaging device 200 with high detection sensitivity is provided. can be done.

[0351] As the photoelectric conversion element 220 shown in FIG. 56, a pn-type junction or a pin-type junction is formed. A photoelectric conversion element may also be used.

[0352] In addition, the photoelectric conversion element 220 is made of a material having a function of absorbing radiation and generating electric charges. The material having the function of absorbing radiation and generating electric charges may be a sintered material. Iron, lead iodide, mercury iodide, gallium arsenide, cadmium telluride, cadmium zinc alloy etc.

[0353] For example, if selenium is used for the photoelectric conversion element 220, in addition to visible light, ultraviolet light, and infrared light, Photoelectric conversion element 2 that has a light absorption coefficient over a wide wavelength range, including X-rays and gamma rays 20 can be achieved.

[0354] Here, one pixel 211 included in the imaging device 200 has a sub-pixel 212 shown in FIG. 2, may include a subpixel 212 having a first filter.

[0355] <Pixel configuration example 2> In the following, a transistor using silicon and a transistor using an oxide semiconductor according to the present invention will be described. An example of forming a pixel using a register will be described.

[0356] 57(A) and (B) are cross-sectional views of elements that constitute an imaging device.

[0357] The imaging device shown in FIG. 57(A) is a silicon-based transistor provided on a silicon substrate 300. A transistor 353 using an oxide semiconductor is stacked over the transistor 351. The transistor 354 and the anode 361 and the capacitor 362 are provided on the silicon substrate 300. The photodiode 360 ​​has a cathode 362. The electrodes 360 have electrical connections to various plugs 370 and wires 371. The anode 361 of the photodiode 360 ​​is connected to the plug 370 via the low resistance region 363. It has an electrical connection.

[0358] The imaging device includes a transistor 351 and a photodiode 352 disposed on a silicon substrate 300. A layer 305 having an electrode 360 ​​and a layer 371 having wiring 371 provided in contact with the layer 305. 20 and in contact with layer 320, and includes transistors 353 and 354. A layer 331 is provided in contact with the layer 331 and has wiring 372 and wiring 373. It has 40.

[0359] In the example of the cross-sectional view of FIG. 57(A), the transistor 3 is formed on the silicon substrate 300. The light receiving surface of the photodiode 360 ​​is disposed on the opposite side to the surface on which the photodiode 51 is formed. This configuration ensures an optical path without being affected by various transistors and wiring. Therefore, it is possible to form pixels with a high aperture ratio. Alternatively, the light receiving surface of the gate 360 ​​may be the same as the surface on which the transistor 351 is formed.

[0360] In the case where a pixel is formed using a transistor including an oxide semiconductor, the layer 305 Alternatively, the layer 305 may be omitted and an oxide semiconductor may be used. A pixel may be formed by only the transistor.

[0361] In the cross-sectional view of FIG. 57(A), a photodiode 360 ​​provided in the layer 305 and a The transistor 331 can be formed so as to overlap with the transistor 332. In other words, the resolution of the imaging device can be increased.

[0362] FIG. 57B shows an imaging device in which a photodiode 365 is provided on the layer 340 side as a transistor. In FIG. 57B, for example, the layer 305 has: The layer 320 includes a transistor 351 and a transistor 352 using silicon. The line 371 is a transistor 353 using an oxide semiconductor layer in the layer 331. The layer 340 has a photodiode 365, and the layer 340 has a photodiode 366. 65 is composed of semiconductor layers 366, 367, and 368, and wiring 373 and is electrically connected to wiring 374 via plug 370.

[0363] By using the element configuration shown in FIG. 57(B), the aperture ratio can be increased.

[0364] In addition, the photodiode 365 is made of an amorphous silicon film or a microcrystalline silicon film. A pin-type diode element or the like may be used. The photodiode 365 is an n-type semiconductor A layer 368, an i-type semiconductor layer 367, and a p-type semiconductor layer 366 are laminated in this order. It is preferable to use amorphous silicon for the i-type semiconductor layer 367. The p-type semiconductor layer 366 and the n-type semiconductor layer 368 are provided with dopants that impart their respective conductivity types. Amorphous silicon or microcrystalline silicon containing a dopant can be used. The photodiode 365, which uses silicon as a photoelectric conversion layer, has high sensitivity in the visible light wavelength range. It is highly sensitive to weak visible light.

[0365] Here, a layer 305 having a transistor 351 and a photodiode 360, An insulator 380 is provided between the layer 331 having the resistor 353 and the transistor 354. However, the position of the insulator 380 is not limited.

[0366] The hydrogen in the insulator provided near the channel forming region of the transistor 351 is converted into silicon diaphragm. This has the effect of terminating the ring bond and improving the reliability of the transistor 351. , hydrogen in an insulator provided near the transistor 353 and the transistor 354, etc. This is one of the factors that generate carriers in the oxide semiconductor. This may cause a decrease in reliability of the transistor 53 and the transistor 354. Therefore, a transistor using an oxide semiconductor is placed on top of a transistor using a silicon semiconductor. When the capacitors are stacked, an insulator 380 having a function of blocking hydrogen is provided between them. It is preferable to provide the insulator 380. By confining hydrogen below the insulator 380, the transistor The reliability of the insulator 351 can be improved. Since hydrogen diffusion to layers above 380 can be suppressed, the transistors 353 and The reliability of the transistors 353 and 354 can be improved. By providing the insulator 381 over the transistor 354, oxygen diffusion in the oxide semiconductor This is preferable because it can prevent scattering.

[0367] This embodiment may be appropriately combined with at least a part of other embodiments described in this specification. It can be implemented together.

[0368] (Embodiment 9) <RFタグ> In this embodiment, an RF device including a transistor or a memory device described in the previous embodiment is The tags will be described with reference to FIG.

[0369] The RF tag in this embodiment has a memory circuit therein and stores necessary information in the memory circuit. In addition, information is exchanged with the outside world using non-contact means, such as wireless communication. Due to these characteristics, RF tags are used as individual devices to identify items by reading their individual information. It can be used for biometric authentication systems, etc. Therefore, extremely high reliability is required.

[0370] The structure of an RF tag will be described with reference to FIG. 58. FIG. 58 is a block diagram showing an example of the structure of an RF tag. FIG.

[0371] As shown in FIG. 58, an RF tag 800 includes a communicator 801 (also called an interrogator, reader / writer, etc.). 8, which receives a radio signal 803 transmitted from an antenna 802 connected to the The RF tag 800 also includes a rectifier circuit 805, a constant voltage circuit 806, and a demodulator circuit 804. 07, a modulation circuit 808, a logic circuit 809, a memory circuit 810, and a ROM 811. In addition, the reverse current of the transistor having the rectification effect included in the demodulation circuit 807 is sufficiently suppressed. A material capable of being used for the insulating layer 11 may be, for example, an oxide semiconductor. This suppresses the deterioration of the rectification effect caused by the reverse current and prevents the output of the demodulation circuit from becoming saturated. In other words, the output of the demodulation circuit relative to the input of the demodulation circuit can be made closer to linear. The data transmission format is a pair of coils arranged facing each other and communication is carried out by mutual induction. The electromagnetic coupling method uses electromagnetic fields to communicate, the electromagnetic induction method uses radio waves to communicate, The RF tag 800 shown in this embodiment can be used with any of these methods. It is also possible to use it for.

[0372] Next, the configuration of each circuit will be described. The antenna 804 is an antenna connected to the communication device 801. The rectifier circuit 802 is used to transmit and receive a radio signal 803 to and from the antenna 802. 05 is a rectifier for an input AC signal generated by receiving a radio signal through an antenna 804. For example, half-wave double voltage rectification is performed, and the rectified signal is smoothed by a capacitive element provided in the latter stage. The rectifier circuit 805 is a circuit for generating an input potential by rectifying the input side of the rectifier circuit 805. A limiter circuit may be provided on the output side. When the internally generated voltage is large, it is necessary to prevent a certain amount of power from being input to the downstream circuit. This is a circuit for controlling the

[0373] The constant voltage circuit 806 generates a stable power supply voltage from the input potential and supplies it to each circuit. The constant voltage circuit 806 may include a reset signal generating circuit. The reset signal generating circuit uses the stable rise of the power supply voltage to reset the logic circuit 80. This is a circuit for generating the reset signal for 9.

[0374] The demodulation circuit 807 demodulates the input AC signal by envelope detection to generate a demodulated signal. The modulation circuit 808 is a circuit for modulating the data output from the antenna 804. This is a circuit for performing modulation based on the

[0375] The logic circuit 809 is a circuit for analyzing and processing the demodulated signal. This is a circuit that holds input information, and includes a row decoder, column decoder, memory area, etc. The ROM 811 also stores a unique number (ID) and outputs it according to the processing. This is a circuit for this purpose.

[0376] It should be noted that the above-mentioned circuits can be appropriately selected or omitted as necessary.

[0377] Here, the memory circuit described in the above embodiment can be used as the memory circuit 810. The memory circuit of one embodiment of the present invention can retain data even when power is cut off. The memory circuit of one embodiment of the present invention can be suitably used for an RF tag. The power (voltage) required to write data is significantly smaller than that of conventional non-volatile memory. It is also possible to eliminate the difference in maximum communication distance during reading and writing. To prevent malfunction or erroneous writing caused by a power shortage when writing data can be done.

[0378] In addition, the memory circuit of one embodiment of the present invention can be used as a nonvolatile memory. Therefore, it can be applied to ROM811. In that case, the producer must input the data to ROM811. A separate command is provided to write data, preventing users from freely rewriting it. It is preferable that the manufacturer writes the unique number on the product before shipping it. Therefore, instead of assigning a unique number to each RF tag that is produced, only good products that are shipped will be assigned a unique number. This means that the unique numbers of products will be discontinuous after shipment. This makes it easier to manage customers' accounts after products are shipped.

[0379] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification. .

[0380] (Embodiment 10) <Display device> A display device according to one embodiment of the present invention will be described below with reference to FIGS. 59 and 60. do.

[0381] Display elements used in display devices include liquid crystal elements (also called liquid crystal display elements), light-emitting elements, etc. The light-emitting element can be a light-emitting display element. Therefore, the category includes elements whose luminance can be controlled, specifically inorganic EL (Electroluminescent) The following is an example of a display device. Display devices using EL elements (EL display devices) and display devices using liquid crystal elements (liquid crystal display devices) This section explains the display device.

[0382] The display device described below is a panel in which a display element is sealed, and a control circuit is attached to the panel. This includes modules in which ICs including controllers are mounted.

[0383] The display device described below refers to an image display device or a light source (including a lighting device). Also, connectors, such as FPC, modules with TCP attached, and TCP with printers A module or display element with a printed wiring board has an IC (integrated circuit) mounted on it by the COG method. The display device also includes all modules mounted on the display device.

[0384] FIG. 59 shows an example of an EL display device according to one embodiment of the present invention. FIG. 59(B) is a top view showing the entire EL display device. FIG. 59(C) is a cross section of the MN corresponding to a part of the dashed line MN in FIG. 59(B). .

[0385] FIG. 59(A) is an example of a circuit diagram of a pixel used in an EL display device.

[0386] In this specification, the terms "active elements" and "passive elements" are used interchangeably. For all terminals of devices (capacitive elements, resistive elements, etc.), the connection destination is not specified. However, a person skilled in the art may be able to configure one aspect of the invention. Even if the destination is not specified, one aspect of the invention is clear. When the contents are described in this specification, etc., one aspect of the invention that does not specify a connection destination is the same as the embodiment of the present specification. In particular, if the terminal is connected to multiple When multiple locations are anticipated, it is not necessary to limit the connection destination of the terminal to a specific location. Therefore, active elements (transistors, diodes, etc.) and passive elements (capacitive elements, resistive elements) By specifying the connection destinations of only some of the terminals on It may be possible to configure a clear embodiment.

[0387] In this specification and the like, if at least the connection destination of a certain circuit is specified, it is understood by those skilled in the art that If you are a person who has experience in the field of electronics, you may be able to identify the invention. In some cases, a person skilled in the art can identify an invention by at least specifying the function. In other words, if the function is specified, one aspect of the invention is clear. It may be possible to determine that one aspect of the invention is described in the present specification. Therefore, even if the function of a circuit is not specified, if the connection destination is specified, it can be considered as an embodiment of the invention. and can constitute one embodiment of the invention. For a certain circuit, even if the connection destination is not specified, if the function is specified, it can be considered as one aspect of the invention. What is disclosed can constitute an embodiment of the invention.

[0388] The EL display device shown in FIG. 59(A) includes a switch element 743, a transistor 741, and a capacitor. The light emitting element 719 includes a capacitance element 742 and a light emitting element 719 .

[0389] Note that FIG. 59(A) is an example of a circuit configuration, and therefore, if a transistor is added, Conversely, at each node in FIG. 59(A), it is possible to It is also possible to avoid adding passive elements.

[0390] The gate of the transistor 741 is connected to one end of the switch element 743 and one end of the capacitance element 742. The source of the transistor 741 is electrically connected to the other electrode of the capacitor 742. and is electrically connected to one electrode of the light-emitting element 719. The drain of the switch element 741 is supplied with a power supply potential VDD. The other end of the switch element 743 is connected to the signal line 7 The other electrode of the light-emitting element 719 is electrically connected to the light-emitting element 44. A constant potential is applied to the other electrode of the light-emitting element 719. The constant potential is the ground potential GND or a potential lower than that.

[0391] It is preferable to use a transistor as the switch element 743. This allows the pixel area to be reduced, resulting in an EL display device with high resolution. The switch element 743 is a transistor manufactured through the same process as the transistor 741. By using the transistor 74, the productivity of the EL display device can be improved. 1 and / or the switch element 743, for example, a transistor shown in FIG. It is possible.

[0392] FIG. 59(B) is a top view of the EL display device. The EL display device is made up of a substrate 700 and a substrate 7 50, a sealant 734, a driving circuit 735, a driving circuit 736, a pixel 737, and an FP The sealing material 734 includes the pixel 737, the driving circuit 735, and the driving circuit The driving circuit 735 is disposed between the substrate 700 and the substrate 750 so as to surround the driving circuit 736. Alternatively / and the driving circuit 736 may be disposed outside the sealing material 734 .

[0393] FIG. 59(C) is a cross-sectional view of an EL display device corresponding to a part of the dashed line MN in FIG. 59(B). It is.

[0394] In FIG. 59C, a transistor 741 is shown having an insulator 712a on a substrate 700 and a conductive and a conductive body 704a, the conductive body 704a being disposed on the insulator 712a and the conductive body 704a. An insulator 706a having a partially overlapping region, a semiconductor 706b on the insulator 706a, and a semiconductor Conductors 716a1 and 716a2 in contact with the top surface of the conductor 706b, and conductor 716 a1 and the conductor 716a2, and the insulator 706c on the semiconductor 706b. and an insulator 718b on the insulator 706c, and a semiconductor 706b overlapping the insulator 718b. Note that the structure of the transistor 741 is only an example. It is possible for the structure to be different from that shown in FIG. 59(C).

[0395] In the transistor 741 shown in FIG. 59C, the conductor 704a serves as a gate electrode. The insulator 712a functions as a gate insulator, and the conductor 716a1 functions as a The conductor 716a1 functions as a source electrode, and the conductor 716a2 functions as a drain electrode. The insulator 718b functions as a gate insulator, and the conductor 714a functions as a gate electrode. The insulator 706a, the semiconductor 706b, and the insulator 706c have the following functions: Therefore, the electrical characteristics of the conductor 704a and the conductor 716 may change. It is preferable that at least one of the conductors 716a1, 716a2, and 714a has a light-shielding property. It is.

[0396] In FIG. 59C, a capacitor 742 is provided on the conductor 704b. an insulator 706d having an overlapping region; a semiconductor 706e on the insulator 706d; The conductor 716a3 and the conductor 716a4 are in contact with the upper surface of the body 706e, and the conductor 716a 3 and the conductor 716a4, and the insulator 706f on the semiconductor 706e. , an insulator 718b on the insulator 706f, and a semiconductor 706e on the insulator 718b. 7B, and a conductor 714b that is connected to the conductor 714.

[0397] In the capacitor 742, the conductor 704b serves as one electrode, and the conductor 714b serves as It serves as the other electrode.

[0398] The capacitor 742 can be formed using a film common to the transistor 741. In addition, it is preferable that the conductor 704a and the conductor 704b are made of the same type of conductor. In that case, The conductor 704a and the conductor 704b can be formed through the same process. It is preferable that the conductor 714a and the conductor 714b are made of the same type of conductor. The conductor 714a and the conductor 714b can be formed through the same process.

[0399] A capacitor 742 shown in FIG. 59C has a large capacitance per occupied area. Therefore, the EL display device in FIG. 59C has high display quality. The structure is merely an example, and a structure different from that shown in FIG. 59(C) may be used.

[0400] An insulator 728 is provided over the transistor 741 and the capacitor 742. An insulator 720 is disposed on the transistor 8. Here, the insulator 728 and the insulator 720 are The conductor 716a1 may have an opening that reaches the conductor 716a1 that functions as the source electrode of the transistor 741. A conductor 781 is disposed on the insulator 720. The conductor 781 is disposed on the insulator 728. And it may be electrically connected to the transistor 741 through an opening in the insulator 720 .

[0401] A partition 784 having an opening reaching the conductor 781 is disposed over the conductor 781. A light-emitting layer 782 is disposed on the wall 784 so as to be in contact with the conductor 781 at the opening of the partition wall 784. A conductor 783 is disposed over the light-emitting layer 782. The overlapping region of the conductor 783 becomes the light-emitting element 719 .

[0402] So far, an example of an EL display device has been described. Next, an example of a liquid crystal display device will be described. do.

[0403] FIG. 60(A) is a circuit diagram showing an example of the configuration of a pixel of a liquid crystal display device. The pixel is a pixel including a transistor 751, a capacitor element 752, and a pair of electrodes filled with liquid crystal. The liquid crystal element 753 is also included.

[0404] In the transistor 751, one of the source and the drain is electrically connected to a signal line 755. The gate is electrically connected to a scan line 754 .

[0405] In the capacitor 752, one electrode is electrically connected to the other of the source and drain of the transistor 751. The other electrode is electrically connected to a wiring that supplies a common potential.

[0406] In the liquid crystal element 753, one electrode is electrically connected to the other of the source and drain of the transistor 751. The other electrode is electrically connected to a wiring that supplies a common potential. A common potential applied to a wiring to which the other electrode of the capacitor 752 is electrically connected, The common potential applied to the other electrode of the liquid crystal element 753 may be different from the common potential applied to the other electrode of the liquid crystal element 753 .

[0407] The liquid crystal display device will be described assuming that the top view is the same as that of the EL display device. A cross-sectional view of the liquid crystal display device corresponding to the dotted chain line MN is shown in FIG. In this case, the FPC 732 is connected to the wiring 733a via the terminal 731. 3a is a conductor or a semiconductor of the same type as the conductor or semiconductor that constitutes the transistor 751. Alternatively, a semiconductor may be used.

[0408] For the transistor 751, refer to the description of the transistor 741. For 752, refer to the description of the capacitor 742. Although the structure of the capacitor 752 corresponding to the capacitor 742 in (C) is shown, the present invention is not limited to this. stomach.

[0409] Note that when an oxide semiconductor is used as the semiconductor of the transistor 751, the off-state current is extremely small. Therefore, the charge held in the capacitor 752 can be Therefore, the voltage applied to the liquid crystal element 753 can be maintained for a long period of time. Therefore, when displaying a moving image or a still image with little movement, the transistor 751 is turned off. This eliminates the need for power to operate the transistor 751, and the liquid crystal display has low power consumption. In addition, the area occupied by the capacitor 752 can be reduced; It is possible to provide a liquid crystal display device with a high aperture ratio or a high-definition liquid crystal display device.

[0410] An insulator 721 is provided over the transistor 751 and the capacitor 752. The insulator 721 has an opening that reaches the transistor 751. The conductor 791 is disposed on the insulator 721. The conductor 791 is connected to the transistor Electrically connect to 751.

[0411] An insulator 792 functioning as an alignment film is provided over the conductor 791. A liquid crystal layer 793 is disposed on the liquid crystal layer 793. An insulator 794 that functions as an alignment film is disposed on the liquid crystal layer 793. 94 is disposed on the insulator 794. A spacer 795 is disposed on the insulator 794. A conductor 796 is disposed on the insulator 794. The substrate 79 7 is placed.

[0412] By using the above-mentioned structure, it is possible to provide a display device having a capacitance element with a small occupancy area. Alternatively, a display device with high display quality can be provided. It is possible to provide a display device.

[0413] For example, in this specification and the like, a display element, a display device, a light-emitting element, or a light-emitting device is, for example, , EL elements (EL elements containing organic and inorganic materials, organic EL elements, inorganic EL elements), LED (white LED, red LED, green LED, blue LED, etc.), transistor (depending on current) transistors that emit light when exposed to light, electron emitters, liquid crystal elements, electronic ink, electrophoretic elements, grayscale Light bulbs (GLV), plasma displays (PDP), MEMS Display element using a chromium electro-mechanical system, digital micromirror Device (DMD), DMS (Digital Micro Shutter), IMOD (Interface Modulation Device) Fairness modulation element, shutter-type MEMS display element, optical interference method MEMS display elements, electrowetting elements, piezoelectric ceramic displays, The display element includes at least one of the following: However, due to electrical or magnetic effects, the contrast, brightness, reflectance, transmittance, etc., change. The display device may have a display medium.

[0414] An example of a display device using an EL element is an EL display. An example of a display device using this method is a field emission display (FED). is a flat panel display using the SED method (SED: Surface-conduction E LCD displays are used in the following applications: An example of the device is a liquid crystal display (transmissive liquid crystal display, semi-transmissive liquid crystal display, etc.). play, reflective LCD, direct-view LCD, projection LCD) An example of a display device using electronic ink or electrophoretic elements is an electronic page. In addition, there are also other LCDs that can realize semi-transmissive and reflective LCD displays. In this case, a part or the whole of the pixel electrode may be made to function as a reflective electrode. For example, a part or the whole of the pixel electrode may be made of aluminum, silver, etc. In this case, a memory circuit such as an SRAM may be provided under the reflective electrode. This makes it possible to further reduce power consumption.

[0415] When using an LED, graphene or graphene is placed under the LED electrode or nitride semiconductor. Graphene and graphite can be arranged in layers to form a multilayer film. In this way, by providing graphene or graphite, it is possible to form a nitride on the graphene or graphite. Semiconductors, such as n-type GaN semiconductors having crystals, can be easily formed into films. Furthermore, a p-type GaN semiconductor having crystals can be placed on top of it to form an LED. It is possible to fabricate a crystalline n-type GaN semiconductor using graphene or graphite. An AlN layer may be provided. The GaN semiconductor in the LED is formed by MOCVD. However, by providing graphene, the GaN semiconductor of the LED can be It is also possible to form the film by a tar deposition method.

[0416] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification. .

[0417] (Embodiment 11) In this embodiment, a display module to which a semiconductor device of one embodiment of the present invention is applied will be described with reference to FIG. The explanation will be given using 61.

[0418] <Display module> The display module 6000 shown in FIG. 61 is made up of an upper cover 6001 and a lower cover 6002. In between, touch panel 6004 connected to FPC 6003 and touch panel 6005 connected to FPC 6005 Display panel 6006, backlight unit 6007, frame 6009, printed circuit board 6010 and a battery 6011. In some cases, the read / write head 6011, the touch panel 6004, etc. may not be provided.

[0419] The semiconductor device of one embodiment of the present invention is, for example, a display panel 6006 or a printed circuit board. The present invention can be used in integrated circuits implemented in a semiconductor device.

[0420] The upper cover 6001 and the lower cover 6002 are connected to the touch panel 6004 and the display panel. The shape and dimensions can be changed appropriately to match the size of the cable 6006.

[0421] The touch panel 6004 is a resistive or capacitive touch panel. 6006. In addition, the opposing substrate (sealing substrate) of the display panel 6006 It is also possible to provide the display panel 6 with a touch panel function. It is also possible to add an optical sensor to each pixel of the 006 to add an optical touch panel function. Alternatively, a touch sensor electrode is provided in each pixel of the display panel 6006, and a capacitance method is used. It is also possible to add a touch panel function.

[0422] The backlight unit 6007 includes a light source 6008. It may be provided at the end of the unit 6007 and may be configured to use a light diffusion plate.

[0423] The frame 6009 has a function of protecting the display panel 6006 and also a function of preventing heat generation from the printed circuit board 6010. The frame 600 also functions as an electromagnetic shield to block electromagnetic waves generated by the 9 may also function as a heat sink.

[0424] The printed circuit board 6010 includes a power supply circuit, a signal circuit for outputting a video signal, and a clock signal. The power supply circuit is provided with a signal processing circuit. Alternatively, a separately provided battery 6011 may be used. In this case, the battery 6011 can be omitted.

[0425] In addition, the display module 6000 includes components such as a polarizing plate, a retardation plate, and a prism sheet. It may be added.

[0426] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification. .

[0427] (Embodiment 12) <Package using lead frame type interposer> Figure 62(A) shows the cross-sectional structure of a package using a lead frame type interposer. The package shown in FIG. 62(A) is a perspective view of a semiconductor device according to one embodiment of the present invention. The corresponding chip 551 is connected to the terminals on the interposer 550 by wire bonding. The terminal 552 is connected to the chip 551 of the interposer 550. The chip 551 is placed on the surface that is covered with the mold resin 553. Although it may be sealed, it is preferable that the sealing be performed while leaving a portion of each terminal 552 exposed.

[0428] The module configuration of an electronic device (mobile phone) in which a package is mounted on a circuit board is shown in Fig. The mobile phone module shown in FIG. 62(B) includes a printed wiring board 60 A package 602 and a battery 604 are mounted on the display device 1. A printed wiring board 601 is mounted on the panel 600 by an FPC 603. do.

[0429] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification. .

[0430] (Embodiment 13) In this embodiment, an electronic device and a lighting device according to one embodiment of the present invention will be described with reference to drawings. Reveal.

[0431] <Electronic equipment> Using the semiconductor device of one embodiment of the present invention, an electronic device or a lighting device can be manufactured. By using the semiconductor device of one embodiment of the present invention, highly reliable electronic devices and lighting devices can be manufactured. The semiconductor device according to one embodiment of the present invention is used in an electronic device or a lighting device in which the detection sensitivity of a touch sensor is improved. You can create devices.

[0432] The electronic device may be, for example, a television device (also called a television or television receiver). (c), computer monitors, digital cameras, digital video cameras, digital Photo frames, mobile phones (also called mobile phones or mobile phone devices), portable game machines, Examples include portable information terminals, audio playback devices, and large game machines such as pachinko machines.

[0433] In addition, when the electronic device or lighting device of one embodiment of the present invention is flexible, it can be attached to the inner wall of a house or a building. Or it can be installed along the curved surface of an exterior wall or the interior or exterior of a car. do.

[0434] Further, the electronic device of one embodiment of the present invention may include a secondary battery and may be configured to use non-contact power transmission. It is preferable to be able to charge the secondary battery.

[0435] As the secondary battery, for example, a lithium polymer battery (lithium ion battery) using a gel electrolyte is used. Lithium-ion secondary batteries such as lithium-ion polymer batteries, lithium-ion batteries, nickel-metal hydride batteries , nickel-cadmium battery, organic radical battery, lead acid battery, secondary air battery, nickel-zinc battery, silver-zinc battery Batteries and the like.

[0436] The electronic device according to one embodiment of the present invention may include an antenna. By doing so, it is possible to display images and information on the display unit. If present, the antenna may be used for contactless power transfer.

[0437] FIG. 63A shows a portable game machine. The portable game machine includes a housing 7101, a housing 7102, a display portion 7103, Display unit 7104, microphone 7105, speaker 7106, operation keys 7107, stylus The semiconductor device according to one embodiment of the present invention is built in the housing 7101. The display portion 7103 or the display portion 7104 can be used for an integrated circuit, a CPU, etc. By using the light-emitting device according to one embodiment of the present invention, the user experience is excellent and deterioration of quality is prevented. It is possible to provide a portable game machine in which the above-mentioned problems are unlikely to occur. The portable game machine has two display units 7103 and 7104. The number of display units that the device has is not limited to this.

[0438] FIG. 63B shows a smart watch. The smart watch includes a housing 7302, a display unit 7304, and operation buttons. 7311, 7312, a connection terminal 7313, a band 7321, a clasp 7322, etc. The semiconductor device according to one embodiment of the present invention is built in the display portion 7304 or the housing 7302. This can be used for memory, CPU, etc.

[0439] FIG. 63C shows a portable information terminal. In addition to a display portion 7502 incorporated in a housing 7501, , operation button 7503, external connection port 7504, speaker 7505, microphone 7506 The semiconductor device according to one embodiment of the present invention includes a housing 7501, a display portion 7502, and the like. It can be used for mobile memory and CPU built in the display unit 7. The 502 can achieve extremely high definition, so it can provide full HD despite its small to medium size. It can display a variety of resolutions, such as 4k, 5k, or 8k, and you can get very clear images. can.

[0440] FIG. 63D shows a video camera, which includes a first housing 7701, a second housing 7702, and a display unit 77 03, operation keys 7704, a lens 7705, a connection part 7706, etc. 4 and a lens 7705 are provided in a first housing 7701, and a display unit 7703 is provided in a second housing. The first housing 7701 and the second housing 7702 are connected to each other. The first housing 7701 and the second housing 7702 are connected by a connector 7706. The angle between the first housing 7701 and the second housing 7702 is The connection portion 7706 can change the image on the display portion 7703. 6, the switch is configured to switch according to the angle between the first housing 7701 and the second housing 7702. The imaging device according to one embodiment of the present invention may be provided at the focal position of the lens 7705. The semiconductor device according to one embodiment of the present invention is built in the first housing 7701. It can be used in integrated circuits, CPUs, etc.

[0441] FIG. 63E shows a digital signage. A display unit 7922 is installed on a utility pole 7921. The display device according to one embodiment of the present invention can be used as a control circuit for the display portion 7922. This can be done.

[0442] FIG. 64(A) shows a notebook personal computer, which includes a housing 8121 and a display unit 8122. , a keyboard 8123, a pointing device 8124, etc. Such a semiconductor device can be applied to a CPU or a memory built in the housing 8121. Since the display portion 8122 can have a very high resolution, it can be used in small and medium-sized devices. It is possible to display 8K images while using a smartphone, resulting in extremely clear images.

[0443] FIG. 64(B) shows the exterior of the automobile 9700. FIG. 64(C) shows the driver's seat of the automobile 9700. The automobile 9700 includes a body 9701, wheels 9702, a dashboard 9703, and a lighter. The semiconductor device of one embodiment of the present invention includes a display portion of the automobile 9700 and For example, the display unit 9710 shown in FIG. The semiconductor device of one embodiment of the present invention can be provided in the display portion 9715.

[0444] The display portion 9710 and the display portion 9711 are a display device provided on a windshield of an automobile, The display device or the input / output device according to one embodiment of the present invention is a display device or By forming the electrodes of the input / output device from a light-transmitting conductive material, The device is a so-called see-through display device or input / output device that allows the opposite side to be seen through. If it is a see-through display device or an input / output device, the operation of the car 9700 can be Therefore, the display device or input / output device according to one embodiment of the present invention can be used without obstructing the view even when the display device is turned on. The display device can be installed on the windshield of the automobile 9700. A display device or an input / output device is provided with transistors for driving the display device or the input / output device. In this case, organic transistors using organic semiconductor materials and transistors using oxide semiconductors are used. For example, a light-transmitting transistor such as a transistor having a light-transmitting property may be used.

[0445] The display unit 9712 is a display device provided on a pillar part. By displaying an image from the imaging means on the display unit 9712, the view blocked by the pillars can be compensated for. The display unit 9713 is a display device provided in the dashboard. For example, an image captured by an imaging means provided on the vehicle body is displayed on the display unit 9713. This can complement the view obstructed by the dashboard. By projecting images from the installed imaging means, blind spots can be filled and safety can be improved. In addition, by projecting an image that complements the invisible parts, it is possible to make the sense of discomfort more natural. Safety checks can be performed without any hassle.

[0446] FIG. 64(D) shows the interior of a car with bench seats for the driver and passenger. The display unit 9721 is a display device or an input / output device provided in the door section. For example, the driver can view the vehicle by displaying an image captured by an imaging means provided on the vehicle body on the display unit 9721. The display unit 9722 can complement the view blocked by the steering wheel. The display unit 9723 is a display device provided in the center of the seat surface of the bench seat. The display device is installed on the seat or backrest, and the display device is The heat generated by the display device can also be used as a seat heater.

[0447] The display unit 9714, the display unit 9715, or the display unit 9722 displays navigation information, odometer, tachometer, mileage, fuel level, gear status, air conditioning settings, etc. It is possible to provide various information. In addition, the display items and layout displayed on the display unit can be The above information can be displayed on the display unit 9. 710 to 9713, the display unit 9721, and the display unit 9723. In addition, the display units 9710 to 9715 and the display units 9721 to 9723 are illuminated. The display units 9710 to 9715 and the display unit The display portion 9721 to the display portion 9723 can also be used as a heating device.

[0448] FIG. 65A shows the external appearance of the camera 8000. The camera 8000 has a housing 8001. , a display unit 8002, an operation button 8003, a shutter button 8004, a connection unit 8005, etc. In addition, a lens 8006 can be attached to the camera 8000.

[0449] The coupling section 8005 has electrodes and is connected to the finder 8100 (to be described later) as well as a strobe device, etc. can be connected.

[0450] In this example, a camera 8000 is used, and a lens 8006 is removed from a housing 8001 and replaced. However, the lens 8006 and the housing may be integrated together.

[0451] An image can be captured by pressing the shutter button 8004. The display unit 8002 has a function as a touch panel, and an image is captured by touching the display unit 8002. It is also possible.

[0452] The display device or the input / output device according to one embodiment of the present invention can be applied to the display portion 8002. do.

[0453] FIG. 65(B) shows an example in which a finder 8100 is attached to a camera 8000. is.

[0454] The finder 8100 includes a housing 8101, a display portion 8102, a button 8103, and the like.

[0455] The housing 8101 has a joint portion that engages with the joint portion 8005 of the camera 8000. The finder 8100 can be attached to the camera 8000. The display unit 8102 displays images received from the camera 8000 via the electrodes. It can be done.

[0456] The button 8103 functions as a power button. The display of 102 can be switched on and off.

[0457] The semiconductor device of one embodiment of the present invention is applied to an integrated circuit and an image sensor in a housing 8101. It can be used.

[0458] In addition, in FIG. 65(A)(B), the camera 8000 and the finder 8100 are separate electronic devices. The camera 8000 is provided with a housing 8001 that is detachable. A finder having a display device or an input / output device according to an embodiment may be built in.

[0459] FIG. 65(C) shows the external appearance of the head mounted display 8200.

[0460] The head mounted display 8200 includes a mounting part 8201, a lens 8202, and a main body 820. 3, a display unit 8204, a cable 8205, etc. It has a built-in Terry 8206.

[0461] A cable 8205 supplies power from a battery 8206 to the main body 8203. 03 is equipped with a wireless receiver and the like, and image information such as image data received is displayed on a display unit 8204. In addition, the camera installed in the main body 8203 can record the movement of the user's eyeballs and eyelids. The system captures the user's gaze and calculates the coordinates of the user's gaze based on that information. It can be used as an input means.

[0462] Furthermore, the mounting unit 8201 may be provided with a plurality of electrodes at positions that come into contact with the user. The main body 8203 detects the current flowing through the electrodes in response to the movement of the user's eyeball, The device may have a function of recognizing the user's gaze. Also, the device may have a function of detecting the current flowing through the electrode. In this way, the mounting unit 8201 may have a function of monitoring the pulse of the user. The sensor may have various sensors such as a temperature sensor, a pressure sensor, and an acceleration sensor. The display unit 8204 may have a function of displaying the user's biological information. detect the movement or the like, and even if the video displayed on the display unit 8204 is changed according to the movement is acceptable.

[0463] The semiconductor device according to one aspect of the present invention can be applied to the integrated circuit inside the main body 8203. 。

[0464] This embodiment can be implemented in appropriate combination with at least a part of other embodiments described in this specification. It can be implemented in combination.

[0465] (Embodiment 14) In this embodiment, a usage example of an RF tag using the semiconductor device according to one aspect of the present invention will be described with reference to FIG. 66.

[0466] <Usage Example of RF Tag> The uses of RF tags are extensive. For example, banknotes, coins, securities, bearer bonds, certificates documents (driver's licenses, resident cards, etc., see FIG. 66(A)), vehicles (bicycles, etc., see FIG. 66(B) reference), packaging containers (wrapping paper, bottles, etc., see FIG. 66(C)), recording media (DVDs, video tapes, etc., see FIG. 66(D), personal belongings (bags, glasses, etc., see FIG. 66(E)), food products , plants, animals, human bodies, clothing, daily necessities, medical products including drugs and medicines, or electronic devices (liquid crystal display devices, EL display devices, television devices, or mobile phones) and other articles, or it can be used by being provided on a tag (see FIGS. 66(E) and 66(F)) attached to each article. It can be done.

[0467] The RF tag 4000 according to one aspect of the present invention is fixed to an article by being pasted or embedded on the surface. For example, if it is a book, it is embedded in paper, and if it is a package made of an organic resin it is For example, the RF tag is embedded in the organic resin and fixed to each article. The 4000 is small, thin, and lightweight, and even after it is attached to an object, it does not change the design of the object. In addition, the security of banknotes, coins, securities, bearer bonds, or certificates is not lost. By providing an RF tag 4000 according to one aspect of the present invention to a product or the like, an authentication function can be provided. This authentication function can be used to prevent counterfeiting. The present invention can be applied to a variety of items, including food, clothing, household goods, and electronic devices. By attaching RF tags related to the above, the efficiency of systems such as inspection systems can be improved. In addition, even in the case of vehicles, the RF tag according to one embodiment of the present invention can be attached. This can improve security against theft and the like.

[0468] As described above, an RF tag using a semiconductor device according to one embodiment of the present invention is By using these for each of the above applications, it is possible to reduce the power consumption during operation, including writing and reading information. Therefore, it is possible to extend the maximum communication distance. Since the data can be stored for an extremely long period of time, it is also suitable for applications where writing and reading are performed infrequently. It can be suitably used.

[0469] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification. . [Explanation of symbols]

[0470] 200 Imaging device 201 Switch 202 Switch 203 Switch 210 Pixel section 211 pixels 212 subpixels 212B subpixel 212G subpixel 212R subpixel 220 Photoelectric conversion element 230 Pixel Circuit 231 Wiring 247 Wiring 248 Wiring 249 Wiring 250 Wiring 253 Wiring 254 Filter 254B Filter 254G Filter 254R Filter 255 Lens 256 light 257 Wiring 260 Peripheral Circuits 270 Peripheral Circuits 280 Peripheral Circuits 290 Peripheral Circuits 291 Light source 300 Silicon substrate 301 Insulators 302 Insulators 303 Electron capture layer 305 layers 310a Conductor 310b conductor 310c conductor 320 layers 330 Transistor 331 layers 340 layers 351 Transistor 352 Transistor 353 Transistor 354 Transistor 360 Photodiode 361 Anode 362 Cathode 363 Low resistance region 365 Photodiode 366 Semiconductor Layer 367 Semiconductor Layer 368 Semiconductor Layer 370 Plug 371 Wiring 372 Wiring 373 Wiring 374 Wiring 380 Insulator 381 Insulators 400 Substrates 401 Insulators 402 Insulator 404 Conductors 406a Insulator 406a_1 Insulator 406b Semiconductors 406b_1 Semiconductor 406c Insulator 407 area 407a1 area 407a2 area 408 Insulator 410 Insulators 410a Insulator 411 Resist mask 412 Insulators 414 Conductors 415 Conductors 416a1 Conductor 416a2 Conductor 417 Conductors 417a Electric conductor 418 Insulator 419 Insulator 419a Insulator 420 Resist Mask 422 Conductors 422a Conductor 428 Insulator 429 Conductors 430 Conductors 431 Conductors 432 Conductors 433 Conductors 434 Conductors 437 Conductors 438 Conductors 440 Conductors 442 Conductors 444 Conductors 450 Semiconductor Substrate 454 Conductors 460 areas 462 Insulator 464 Insulator 465 Insulator 466 Insulators 467 Insulators 468 Insulator 469 Insulators 470 Insulator 472 Insulators 474a area 474b area 475 Insulator 476a Conductors 476b Conductors 476c Electrical conductors 477a Conductor 477b Conductors 477c Electrical conductor 478a Conductors 478b Conductor 478c Conductor 479a Conductors 479b Conductors 479c Electrical conductors 480a Conductor 480b Conductor 480c conductor 483a Conductor 483b Conductor 483c conductor 483d Conductor 483e Conductor 483f Conductors 484a Conductors 484b Conductors 484c Conductor 484d Conductor 485a Conductor 485b Conductor 485c Conductor 485d Conductor 487a Electric conductor 487b Conductor 487c Conductor 488a Conductors 488b Conductor 488c Electrical conductor 489a Conductors 489b Conductors 490a Conductors 490b Conductors 491a Conductors 491b Conductors 491c Electrical conductor 492a Conductors 492b Conductor 492c Electrical conductor 494 Conductors 496 Conductors 498 Insulator 550 Interposer 551 Chip 552 Terminal 553 Molding resin 600 Panels 601 Printed wiring board 602 Package 603 FPC 604 Battery 700 Substrates 704a Conductor 704b Conductor 706a Insulator 706b Semiconductors 706c Insulator 706d Insulator 706e Semiconductor 706f Insulator 710 Insulators 712a Insulator 714a Conductor 714b Conductor 716a1 Conductor 716a2 Conductor 716a3 Conductor 716a4 Conductor 718b Insulator 719 Light emitting element 720 Insulator 721 Insulators 728 Insulator 731 Terminal 732 FPC 733a Wiring 734 Sealing material 735 Drive Circuit 736 Drive Circuit 737 pixels 741 Transistor 742 Capacitive element 743 Switching element 744 Signal Line 750 Board 751 Transistor 752 Capacitive element 753 Liquid crystal element 754 scan lines 755 Signal Line 781 Conductors 782 Light-emitting layer 783 Conductors 784 Bulkhead 791 Conductors 792 Insulators 793 Liquid crystal layer 794 Insulators 795 Spacer 796 Conductors 797 Circuit Board 800 RF Tags 801 Communication Device 802 Antenna 803 radio signal 804 Antenna 805 Rectifier circuit 806 Constant voltage circuit 807 Demodulation Circuit 808 Modulation Circuit 809 Logic Circuit 810 Memory circuit 811 ROM 1189 ROM Interface 1190 Board 1191 ALU 1192 ALU Controller 1193 Instruction Decoder 1194 Interrupt Controller 1195 Timing Controller 1196 Registers 1197 Register Controller 1198 Bus Interface 1199 ROM 1200 memory elements 1201 Circuit 1202 Circuit 1203 Switch 1204 Switch 1206 Logic elements 1207 Capacitive element 1208 Capacitive element 1209 Transistor 1210 Transistor 1213 Transistor 1214 Transistor 1220 Circuit 2100 Transistor 2200 Transistor 2201 Insulators 2202 Wiring 2203 Plug 2204 Insulators 2205 Wiring 2207 Insulators 2208 Insulator 2211 Semiconductor substrate 2212 Insulators 2213 Gate electrode 2214 Gate insulator 2215 Source and drain regions 3001 Wiring 3002 Wiring 3003 Wiring 3004 Wiring 3005 Wiring 3200 Transistors 3300 Transistors 3400 Capacitive element 4000 RF tags 5100 pellets 5120 Circuit Board 5161 area 6000 Display Module 6001 Top cover 6002 Lower cover 6003 FPC 6004 Touch Panel 6005 FPC 6006 Display Panel 6007 Backlight unit 6008 Light source 6009 Frame 6010 Printed Circuit Board 6011 Battery 7101 Case 7102 Case 7103 Display section 7104 Display section 7105 Microphone 7106 Speaker 7107 Operation key 7108 Stylus 7302 Case 7304 Display section 7311 Operation button 7312 Operation button 7313 Connection terminal 7321 Band 7322 Clasp 7501 Case 7502 Display section 7503 Operation button 7504 External connection port 7505 Speaker 7506 Microphone 7701 Case 7702 Case 7703 Display section 7704 Operation key 7705 Lens 7706 Connection 7921 Electric pole 7922 Display section 8000 Camera 8001 Case 8002 Display section 8003 Operation button 8004 Shutter button 8005 Joint 8006 Lens 8100 Finder 8101 Case 8102 Display section 8103 Button 8121 Case 8122 Display section 8123 Keyboard 8124 Pointing Device 8200 Head Mounted Display 8201 Mounting part 8202 Lens 8203 Main unit 8204 Display section 8205 Cable 8206 Battery 9700 Automobiles 9701 Body 9702 wheels 9703 Dashboard 9704 Light 9710 Display section 9711 Display section 9712 Display section 9713 Display section 9714 Display section 9715 Display section 9721 Display section 9722 Display section 9723 Display section< / cpu>

Claims

1. A semiconductor device having a transistor, A first conductor; a first insulator having a region overlying the first conductor; an oxide semiconductor layer having a region located above the first insulator; a second insulator having a region located above the first insulator, a region located above the oxide semiconductor layer, and a region in contact with a side surface of the oxide semiconductor layer; a third insulator having a region located above the oxide semiconductor layer; a second conductor overlapping the oxide semiconductor layer with the third insulator interposed therebetween; a fourth insulator having a region in contact with an upper surface of the second insulator, a region in contact with an upper surface of the third insulator, and a region in contact with an upper surface of the second conductor; a fifth insulator having a region in contact with an upper surface of the fourth insulator; a sixth insulator having a region in contact with an upper surface of the fifth insulator; a third conductor having a region in contact with an upper surface of the sixth insulator; the third insulator and the second conductor have a region provided in a first opening provided in the second insulator; the third insulator has a region in contact with an inner wall of the first opening, the upper surface of the third insulator has a region whose upper surface is at the same height as the upper surface of the second insulator; the upper surface of the second conductor has a region where the height of the upper surface is the same as the height of the upper surface of the second insulator; a second opening provided in the fifth insulator and through which the third conductor is electrically connected to the first conductor has a diameter that is narrower than a third opening provided in the fourth insulator and through which the third conductor is electrically connected to the first conductor.

2. A semiconductor device having a transistor, A first conductor; a first insulator having a region overlying the first conductor; an oxide semiconductor layer having a region located above the first insulator; a second insulator having a region located above the first insulator, a region located above the oxide semiconductor layer, and a region in contact with a side surface of the oxide semiconductor layer; a third insulator having a region located above the oxide semiconductor layer; a second conductor overlapping the oxide semiconductor layer with the third insulator interposed therebetween; a fourth insulator having a region in contact with an upper surface of the second insulator, a region in contact with an upper surface of the third insulator, and a region in contact with an upper surface of the second conductor; a fifth insulator having a region in contact with an upper surface of the fourth insulator; a sixth insulator having a region in contact with an upper surface of the fifth insulator; a third conductor having a region in contact with an upper surface of the sixth insulator; the third insulator and the second conductor have a region provided in a first opening provided in the second insulator; the third insulator has a region in contact with an inner wall of the first opening, the upper surface of the third insulator has a region whose upper surface is at the same height as the upper surface of the second insulator; the upper surface of the second conductor has a region where the height of the upper surface is the same as the height of the upper surface of the second insulator; a second opening, which is provided in the fifth insulator and through which the third conductor is electrically connected to the first conductor, has a portion having a smaller diameter than a third opening, which is provided in the fourth insulator and through which the third conductor is electrically connected to the first conductor; the second conductor overlaps with the first conductor with the third insulator, the oxide semiconductor layer, and the first insulator interposed therebetween.

3. In claim 1 or 2, The oxide semiconductor layer contains In, Ga, and Zn.

4. In any one of claims 1 to 3, a diameter of the second opening, which is provided in the fifth insulator and through which the third conductor is electrically connected to the first conductor, has a portion that is narrower than a diameter of a fourth opening, which is provided in the sixth insulator and through which the third conductor is electrically connected to the first conductor.

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