Delay lines with process-voltage-temperature robustness, linearity and leakage current compensation

Abstract

One aspect includes a voltage regulator including: a ring oscillator coupled between a first node and a first voltage rail; a control circuit coupled to the first node; a delay line coupled between a second node and the first voltage rail; and an input coupled to the first node and an output coupled to the second node; The present invention relates to an apparatus comprising:

Description

[Technical field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS This patent application claims priority to pending U.S. non-provisional application Ser. No. 17 / 495,608, filed October 6, 2021, and assigned to the assignee of this patent application, which is expressly incorporated by reference herein as if fully set forth below and for all applicable purposes.

[0002] Aspects of the present disclosure relate generally to signal delay lines, and more particularly to signal delay circuits with process-voltage-temperature (PVT) robustness, linearity, and leakage current compensation. [Background technology]

[0003] Delay lines are used in many circuits to impart a delay to an input signal (e.g., an input clock) to generate an output signal (e.g., an output clock). For the imparted delay to be accurate and predictable, the delay must not vary substantially with process-voltage-temperature (PVT) variations. It may be further desirable that the variation of the delay with the delay control signal be substantially linear, so that an accurate and predictable delay may be achieved by appropriately setting the delay control signal. Additionally, it may be desirable to sense leakage currents in the delay line circuitry and compensate the delay line circuitry for the leakage currents. Otherwise, an accurate and predictable delay may not be achievable, especially for certain technology nodes that are sensitive to temperature variations. Summary of the Invention

[0004] SUMMARY OF THE DISCLOSURE The following presents a simplified summary of one or more implementations to provide a basic understanding of such implementations. This Summary is not an extensive overview of all contemplated implementations, and is not intended to identify key or critical elements of all implementations or to delineate the scope of any or all implementations. Its sole purpose is to present some concepts of one or more implementations in a simplified form as a prelude to the Detailed Description presented later.

[0005] One aspect of the present disclosure relates to an apparatus, comprising: a ring oscillator coupled between a first node and a first voltage rail, a control circuit coupled to the first node, a delay line coupled between a second node and the first voltage rail, and a voltage regulator including an input coupled to the first node and an output coupled to the second node; Includes.

[0006] Another aspect of the disclosure relates to a method, the method including: generating an oscillating signal based on a first voltage and a first current, controlling the first voltage and the first current such that a ratio of the first voltage to the first current is substantially constant, and delaying an input signal to generate an output signal based on a second voltage related to the first voltage; Includes.

[0007] Another aspect of the disclosure relates to an apparatus including: means for generating an oscillating signal based on a first voltage and a first current, means for controlling the first voltage and the first current such that a ratio of the first voltage to the first current is substantially constant, and means for delaying an input signal to generate an output signal based on a second voltage related to the first voltage; Includes.

[0008] Another aspect of the present disclosure relates to a wireless communication device, the wireless communication device including: one or more baseband signal processing modules, at least one antenna, a transceiver coupled to the at least one antenna and the one or more baseband signal processing modules, the transceiver including: a ring oscillator coupled between a first node and a first voltage rail, a control circuit coupled to the first node, a delay line coupled between a second node and the first voltage rail, and a voltage regulator including an input coupled to the first node and an output coupled to the second node; Includes.

[0009] To the accomplishment of the foregoing and related ends, the one or more implementations comprise the features hereinafter fully described and particularly pointed out in the claims. The following description and the annexed drawings set forth in detail certain illustrative aspects of the one or more implementations. These aspects are indicative, however, of but a few of the various ways in which the principles of the various implementations may be employed, and the described implementations are intended to include all such aspects and their equivalents. [Brief description of the drawings]

[0010] [Figure 1] FIG. 2 illustrates a block diagram of an exemplary signal delay circuit according to an aspect of the present disclosure. [Figure 2A] 1 shows a schematic diagram of another exemplary signal delay circuit according to another aspect of the present disclosure. [Figure 2B] 2B illustrates a graph of an example current / voltage response in an example control circuit and ring oscillator of the signal delay circuit of FIG. 2A according to another embodiment of the present disclosure. [Figure 2C] 2B illustrates another example current / voltage graph in an example control circuit and ring oscillator of the signal delay circuit of FIG. 2A according to another embodiment of the present disclosure. [Figure 2D] 2B shows a graph of an example current / voltage response for the example delay line of FIG. 2A according to another embodiment of the present disclosure. [Diagram 3]FIG. 1 illustrates a schematic diagram of an exemplary switched-capacitor resistor according to another aspect of the present disclosure. [Figure 4] 1 illustrates a schematic diagram of an exemplary ring oscillator according to another aspect of the present disclosure. [Diagram 5] 1 shows a block diagram of another exemplary signal delay circuit according to another aspect of the present disclosure. [Figure 6] 1 illustrates a schematic diagram of a portion of another exemplary signal delay circuit in accordance with another aspect of the present disclosure. [Figure 7] 1 illustrates a schematic diagram of a portion of another exemplary signal delay circuit in accordance with another aspect of the present disclosure. [Figure 8] 13 shows a schematic diagram of another portion of another exemplary signal delay circuit according to another aspect of the present disclosure. [Figure 9] 1 shows a schematic diagram of an exemplary leakage current sensor according to another aspect of the present disclosure. [Figure 10] 1 shows a schematic diagram of another exemplary leakage current sensor according to another aspect of the present disclosure. [Figure 11] 4 shows a flow diagram of an exemplary method for delaying a signal according to another aspect of the present disclosure. [Figure 12] 1 illustrates a block diagram of an example wireless communication device according to another aspect of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] The detailed description of the present invention described below in conjunction with the accompanying drawings is intended as an illustration of various configurations and is not intended to represent the only configurations in which the concepts described herein may be practiced. The detailed description of the present invention includes specific details intended to provide a thorough understanding of the various concepts. However, it will be apparent to one skilled in the art that these concepts may be practiced without these specific details. In some instances, well-known structures and components are shown in block diagram form to avoid obscuring such concepts.

[0012] Delay lines are used in many applications. For example, delay lines may be used in phase shifters, time-based analog-to-digital converters (ADCs), multi-phase clock generators, digital-to-time converters (DTCs), time-to-digital converters (TDCs), phase-locked loops (PLLs), delay-locked loop (DLL) systems, time measurement systems, and the like. In such applications, it is often important to control such delay lines to provide accurate and predictable delays. In this regard, delay lines and associated control circuits are designed to provide process-voltage-temperature (PVT) stable time delays, a substantially linear delay transfer response with an input delay control signal (e.g., an input code), and to compensate for leakage currents, which may affect the achievement of accurate and predictable delays.

[0013] 1 shows a block diagram of an exemplary signal delay circuit 100 according to one embodiment of the present disclosure. The signal delay circuit 100 receives an input signal S IN (e.g., a clock) and receives an input signal S IN The output signal S is a delayed version of OUT The delay line 150 is configured to generate an output signal S OUT An input signal S provided by a delay line 150 to generate IN The delay amount is determined by the reference voltage V REF2 The signal delay circuit 100 generates a reference voltage V REF2 The delay line 150 is coupled between the node n2 and a lower voltage rail (e.g., ground).

[0014] The signal delay circuit 100 further includes a delay control circuit 105 including a control circuit 110 (e.g., controlling an operating point (OP) of a ring oscillator (RO)), a ring oscillator 120, a delay controller 130, and a voltage regulator 140. The control circuit 110 and the ring oscillator 120 are coupled in series between an upper voltage rail VDD and a lower voltage rail (e.g., ground). In some implementations, the control circuit 110 controls the operating point (V REF1 / I1). As used herein, an operating point is defined as a target voltage V supplied to the ring oscillator 120. REF1 and current I1. As described further herein, the linear voltage / current response is transformed into a PVT stable delay for the input signal provided by delay line 150, and a substantially linear relationship between the delay control signal (DCS) and the resulting delay for the input signal provided by delay line 150.

[0015] The delay controller 130 is coupled to the ring oscillator 120 to provide a delay control signal (DCS) to the ring oscillator. As described further herein, the delay control signal (DCS) controls the number of inverters enabled in the ring oscillator 120, which affects the inherent current / voltage response of the ring oscillator 120. That is, the more inverters enabled, the higher the inherent current / voltage response of the ring oscillator 120, and the fewer inverters enabled, the lower the inherent current / voltage response of the ring oscillator 120.

[0016] The control circuit 110 has an inherent voltage-current / voltage response that is substantially linear. The control circuit 110 controls the current I1 supplied to the ring oscillator 120 such that the ring oscillator 120 exhibits the substantially linear current / voltage response of the control circuit 110. Thus, the control circuit 110 controls the reference voltage V in response to the delay controller 130, which controls the ring oscillator 120 as described above. REF1The reference voltage V is set to maintain the operating point along the linear current I1. REF1 and current I1. The voltage regulator 140 controls the reference voltage V REF1 Based on the reference voltage V REF2 (e.g., V REF2 is V REF1 (Essentially equal to .

[0017] As previously mentioned, the delay line 150 is connected to a reference voltage V REF2 Based on (for example, the reference voltage V REF2 (related to the output signal S OUT To generate the input signal S IN Therefore, the reference voltage V REF2 As increases, the current I drawn by the delay line 150 DLY is the reference voltage V REF2 The delay line 150 increases the input signal S IN The delay T given to DLY is the following relationship: T DLY ~C L ·V REF2 / I DLY , so that the delay line 150 reduces the input signal S IN The delay given to the reference voltage V REF2 Similarly, the reference voltage V REF2 decreases, the current I drawn by the delay line 150 DLY is the reference voltage V REF2 Therefore, the relationship T DLY ~C L ·V REF2 / I DLY According to the delay line 150, the input signal S IN The delay given to the reference voltage V REF2 increases with decreasing

[0018] The control of the delay line 150 by the delay control circuit 105 operates as follows. INIf a smaller delay is desired, the delay controller 130 decreases the reference voltage V by generating a delay control signal (DCS) to enable fewer inverters in the ring oscillator 120. REF1 As a result, the control circuit 110 adjusts (increases) the current I1 and the reference voltage V REF1 Increase the reference voltage V REF1 In response to this, the voltage regulator 140 generates a reference voltage V REF2 , thereby causing the delay line 150 to increase the input signal S IN By reducing the delay applied to the output signal S OUT Generate.

[0019] Conversely, the input signal S IN If a larger delay is desired, the delay controller 130 increases the reference voltage V by generating a delay control signal (DCS) to enable more inverters in the ring oscillator 120. REF1 This allows the control circuit 110 to adjust (reduce) the current I1 and the reference voltage V REF1 Lower the reference voltage V REF1 In response to the decrease in the reference voltage V REF2 , which causes the delay line 150 to reduce the input signal S IN By increasing the delay applied to the output signal S OUT Generate.

[0020] 2A shows a schematic diagram of another exemplary signal delay circuit 200 according to another embodiment of the present disclosure. The signal delay circuit 200 may be an exemplary more detailed implementation of the aforementioned signal delay circuit 100. The signal delay circuit 200 includes a delay line 250 and a delay control circuit including a control circuit 210, a ring oscillator 220, a delay controller 230 and a voltage regulator 240.

[0021] The delay line 250 is made up of M cascaded inverters M 13 / M 14 ~M M3 / M M4, where M is an integer. Cascaded inverters means that inverters are connected in series between the input and the output. For example, the output of an inverter is coupled to the input of the next inverter. Each of the set of cascaded inverters includes a p-channel metal oxide semiconductor field effect transistor (PMOS FET) coupled in series with an n-channel metal oxide semiconductor field effect transistor (NMOS FET) between node n2 and a lower voltage rail (e.g., ground). For example, the first inverters in the set of cascaded inverters are coupled together to couple the input signal S IN and a drain (inverter output) coupled together. 14 A PMOS FET M 13 Similarly, the second inverter includes the first inverter M 13 / M 14 An NMOS FET M including a gate (input) coupled to the output of 24 A PMOS FET M 23 and a drain (output) coupled together and coupled to the input of a subsequent inverter. This configuration includes an NMOS FET M M4 A PMOS FET M M3 and are coupled together to produce an output signal S OUT and a drain (inverter output) configured to generate a clock (eg, an output clock).

[0022] The delay line 250 is made up of cascaded inverters M 13 / M 14 ~M M3 / M M4 , and a lower voltage rail (e.g., ground). 12 ~C M2 The set of M capacitors C 12 ~C M2Each of the set of M capacitors C may be implemented as an individual capacitor, such as a metal-insulator-metal (MIM) capacitor, a metal-oxide-metal (MOM) capacitor, a metal-oxide-semiconductor (MOS) capacitor, or the like. 12 ~C M2 Each of the sets may be implemented as a designed parasite.

[0023] Ring oscillator 220 may be configured similarly to delay line 250, except that the number N of cascaded inverters is an odd integer, and the output of the "last" inverter is coupled to the input of the "first" inverter. More specifically, ring oscillator 220 is configured with N cascaded inverters M 11 / M 12 ~M N1 / M N2 Each of the rings of cascaded inverters includes a PMOS FET coupled in series with an NMOS FET between node n1 and a lower voltage rail (e.g., ground). For example, the "first" inverter in the ring of cascaded inverters is coupled together and the PMOS FET M of the "last" inverter is coupled N1 and NMOS FET M N2 The NMOS FET M 12 A PMOS FET M 11 Similarly, a "second" inverter in a ring of cascaded inverters includes an NMOS FET M1 with its gate (input) coupled to the output of the first inverter and its drain (inverter output) coupled together and to the input of the subsequent inverter. 22 A PMOS FET M 21 This arrangement includes the "last" inverter M N1 / M N2 Ring oscillator 220 may use FETs of the same technology (eg, complementary metal oxide semiconductor (CMOS)) and size as delay line 250.

[0024] The ring oscillator 220 is a cascaded inverter M 11 / M 12 ~M N1 / M N2 M capacitors C coupled between the output of the ring and a lower voltage rail (e.g., ground). 11 ~C N1 The set of M capacitors C 11 ~C N1 Each of the sets of M capacitors C may be implemented as individual capacitors, such as MIM, MOM, MOS, or other types of capacitors. 11 ~C N1 Each of the sets may be implemented as a designed parasite.

[0025] The control circuit 210 includes a first current source including a resistor R1 and a PMOS FET M1 coupled in series with a ring oscillator 220 between an upper voltage rail VDD and a lower voltage rail (e.g., ground). The control circuit 210 further includes a second current source including a resistor R2 and a PMOS FET M2 coupled in series with a resistive device R between the upper voltage rail VDD and a lower voltage rail (e.g., ground). The gates of the PMOS FETs M1 and M2 are coupled to each other to form a current mirror and may be sized to generate a current ratio I1 / I2 of X (e.g., the size of the PMOS FET M1 is X times larger than the size of the PMOS FET M2). Additionally, the control circuit 210 includes an operational amplifier 212 having a first (e.g., negative) input coupled to a node n1 between the first current source R1 / M1 and the ring oscillator 220, a second (e.g., positive) input coupled to a node n3 between the second current source R2 / M2 and the resistive device R, and an output coupled to a control input (e.g., gate) of the current source (e.g., PMOS FETs M1 and M2). The operational amplifier 212 converts the voltage V at node n3 into n3 and the reference voltage V at node n1 REF1 Based on the difference between the sensed voltage V SNS The method is configured to generate

[0026] The delay controller 230 is configured to generate a delay control signal (DCS). As described in more detail herein, the cascaded inverters M of the ring oscillator 220 11 / M 12 ~M N1 / M N2 Each of the sets of inverters M may include a set of parallel inverters. The delay control signal (DCS) may be 11 / M 12 ~M N1 / M N2 enable P (an integer greater than 0) of the set of parallel inverters in one or more first subsets of the set of cascaded inverters M 11 / M 12 ~M N1 / M N2 As described above with reference to the signal delay circuit 100, the current I1 drawn by the ring oscillator 220 is a function of the number A of all enabled inverters in the ring oscillator 220. * P+B * (P+1), where A is the number of cascaded inverters in the first subset and B is the number of cascaded inverters in the second subset. A+B is the stage number of ring oscillator 220. As previously mentioned and as described in further detail herein, the number of enabled inverters in ring oscillator 220, A, is the number of cascaded inverters in the first subset and B is the number of cascaded inverters in the second subset. A+B is the stage number of ring oscillator 220. * P+B * By controlling (P+1), the output signal S OUT The input signal S is generated by a delay line 250. IN The delay applied to can be linearly controlled.

[0027] The voltage regulator 240 may be configured as a low dropout (LDO) voltage regulator. In this regard, the voltage regulator 240 includes an operational amplifier 232 and a PMOS FET M3. The operational amplifier 232 includes a first (e.g., negative) input coupled to a node n1 (e.g., via a filter), a second (e.g., positive) input coupled to a node n2, and an output coupled to a gate of the PMOS FET M3. The PMOS FET M3 is coupled in series with a delay line 250 between an upper voltage rail VDD and a lower voltage rail (e.g., ground), and the node n2 is located between the PMOS FET M3 and the delay line 250.

[0028] The voltage regulator 240 may include filters for reducing supply voltage noise, such as a first low-pass filter (LPF) including a series resistor R3 coupled between node n1 and a first (negative) input of the operational amplifier 232 and a shunt capacitor C1 coupled between the negative input of the operational amplifier 232 and a lower voltage rail (e.g., ground), and a second LPF including a capacitor C2 and a resistor R4 coupled in parallel between node n2 and the lower voltage rail (e.g., ground).

[0029] 2B illustrates a graph of an example characteristic current vs. voltage response of the control circuit 210 and the ring oscillator 220 of the signal delay circuit 200 according to another embodiment of the present disclosure. The horizontal axis of the graph represents the reference voltage V REF1 (node ​​n1). The vertical axis represents the current versus intrinsic current / voltage response of control circuit 210 (labeled "X·I2") and the intrinsic current / voltage response of ring oscillator 220 (labeled "I1" and "I 1less ").

[0030] The inherent current / voltage response X·I2 of the control circuit 210 is expressed as the reference voltage V REF1is the response of current I1 with fluctuations. Similarly, the characteristic current / voltage responses I1 and I of the ring oscillator 220 1less are the responses of the current of the ring oscillator 220 with fluctuations in the reference voltage V in a state where the control circuit 210 is disconnected from node n1 REF1 .

[0031] As will be described in more detail herein, the control circuit 210 adjusts the operating point (e.g., V REF1 and I1) of the ring oscillator 220 to be on the linear X·I2 response. At this time, the following relationship holds

[0032] [Number] Here, R is the resistance of the resistance device R, and V n3 is the voltage at node n3. In this example, the ring oscillator 220 initially operates at point "A" on the X·I2 line. Also, the initial operating point "A" is on the non-linear response "I1" of the characteristic current versus the reference voltage V REF1 (since the ring oscillator 220 is drawing the I1 current).

[0033] And according to this example, the delay controller 230 adjusts (increases) the reference voltage V by generating a delay control signal (DCS) so that the number of inverters in the ring oscillator 220 can be reduced REF1 . As a result, the characteristic current versus the reference voltage V REF1 response changes to the non-linear response "I 1less ", where I 1less < I1. As shown in the figure, the characteristic current versus the reference voltage V REF1 response I 1less has a lower current than the characteristic current versus the reference voltage V REF1 response I1. Therefore, when fewer inverters are enabled in the ring oscillator 220 by the DCS, the operating point first changes to point "B", and the current drawn by the ring oscillator 220 is smaller than the current consumed when operating at point "A". However, the reference voltage VREF1 initially remains the same. As a result, the intrinsic conductivity of the ring oscillator 220 decreases.

[0034] In response to the intrinsic conductivity of the ring oscillator 220, a reference voltage V REF1 increases due to the control circuit 210 providing a current I1 to charge the node n1. Here, the voltage V n3 and the reference voltage V REF1 The operational amplifier 212 of the control circuit 210 senses the voltage difference between SNS This causes currents I1 and I2 to increase. In response, the voltage V n3 is the reference voltage V REF1 The voltage V n3 is the reference voltage V REF1 (e.g., equation 3 is satisfied), then ring oscillator 220 is operating at point "C" on the linear X·I2 response. Thus, control circuit 210 responds to changes in ring oscillator 220 to provide an operating point on the linear X·I2 response.

[0035] 2C illustrates an example characteristic current vs. voltage graph of the control circuit 210 and the ring oscillator 220 of the signal delay circuit 200 according to another embodiment of the present disclosure. The horizontal axis of the graph represents the reference voltage V REF1 (node ​​n1). The vertical axis represents the current versus intrinsic current / voltage response of control circuit 210 (labeled "X·I2") and the intrinsic current / voltage response of ring oscillator 220 (labeled "I1" and "I2") for two different configurations, as described further herein. 1more ").

[0036] Similarly, in this example, ring oscillator 220 is initially operating at point "A" on the X·I2 line. Also, the initial operating point "A" is the intrinsic current vs. reference voltage V (since ring oscillator 220 is drawing I1 current). REF1Next, according to this example, the delay controller 230 increases the reference voltage V by generating a delay control signal (DCS) to enable more inverters in the ring oscillator 220. REF1 As a result, the inherent current of the ring oscillator 220 versus the reference voltage V REF1 is the nonlinear response "I 1more " where I 1more As shown, the characteristic current vs. the reference voltage V REF1 Response I 1more is the characteristic current vs. reference voltage V REF1 The current drawn by the ring oscillator 220 is greater than that consumed when operating at point "A". However, the reference voltage V REF1 initially remains the same. As a result, the intrinsic conductivity of the ring oscillator 220 becomes high.

[0037] In response to an increase in the intrinsic conductivity of the ring oscillator 220, the control circuit 210 supplies a current I1 to the ring oscillator 220, causing the reference voltage V REF1 The voltage V n3 and the reference voltage V REF1 The operational amplifier 212 of the control circuit 210 senses the voltage difference between SNS This causes the currents I1 and I2 to decrease. In response, the voltage V n3 is the reference voltage V REF1 The voltage V n3 is the reference voltage V REF1, (e.g., Equation 3 is satisfied), the ring oscillator 220 is operating at point "E" on the linear X·I2 response. Thus, the control circuit 210 responds to changes in the ring oscillator 220 to provide an operating point on the linear X·I2 response. FIG. 2D illustrates a graph of an example inherent current / voltage response of the delay line 250 of the signal delay circuit 200 according to another aspect of the disclosure. The horizontal axis of the graph represents the reference voltage V applied to the delay line 250. REF2 (at node n2). The vertical axis represents the current drawn by delay line 250. The previous example described in relation to Figures 2B-2C will now be explained with the aid of an exemplary current / voltage response of delay line 250 in the graph shown in Figure 2D.

[0038] Control of the delay line 250 may be as follows: As previously described, the delay control signal (DCS) generated by the delay controller 230 sets the number of enabled inverters in the ring oscillator 220, which is related to the current I1 drawn by the ring oscillator 220. Referring to the example of Figures 2B-2C, the initial number of inverters enabled by the DCS sets the operating point of the ring oscillator to point "A". REF2 is V REF1 , so that a corresponding operating point “A” is plotted on the inherent current / voltage response of delay line 250.

[0039] As explained in the example of FIG. 2B, when the number of enabled inverters is reduced, the reference voltage V REF1 In response, the voltage regulator 240 increases the reference voltage V REF2 Thus, the delay line 250 now has its inherent current / voltage response I DLY The high reference voltage V REF2 As a result, the delay line 250 delays the input signal S IN Similarly, as illustrated in the example of FIG. 2C, increasing the number of enabled inverters reduces the delay applied to the reference voltage V REF1 In response, the voltage regulator 240 decreases the reference voltage VREF2 Thus, the delay line 250 now has its inherent current / voltage response I DLY The lower reference voltage V REF2 As a result, the delay line 250 delays the input signal S IN Increase the delay given to

[0040] Mathematically, the period T of the oscillating signal generated by the ring oscillator 220 is OSC can be determined by the following formula: T OSC =C R ·V REF1 / I1 formula 4 Here, C R is the capacitor C 11 ~C N1 However, according to Equation 1, V REF1 / I1 is equal to R / X. The resistance R of resistive device R and the current ratio X of current mirror M1 / M2 may be configured to be substantially constant over PVT variations. Thus, the period T OSC may be given by the following formula: T OSC =C R ·R / X formula 5 Therefore, C R , R, and X may be configured as substantially constant, the period T of the ring oscillator 220 OSC is also substantially constant. Therefore, this property OSC As will be described later, the delay line 250 improves the PVT robustness of the input signal S IN The delay T given to DLY is the period T of the ring oscillator 220. OSC Therefore, by extension, the delay T DLY also has higher PVT robustness.

[0041] Equation 5 expresses the period T of the oscillating signal generated by the ring oscillator 220. OSC R * C time constant, i.e. CR * The delay line 250 delays the input signal S IN The delay given to R * Period T related to C time constant OSC Since it is related to the resistor device R and the capacitor C 11 ~C N1 By appropriately designing the delay line 250, the PVT variation of the delay provided by the delay line 250 can be controlled. As an example, as discussed further herein, when a switched capacitor resistor is used as the resistive device R, the delay line 250 can be designed to have a PVT variation of 100 kHz. DLY is the capacitor ratio C R / C SW where C SW is the capacitor of the switched capacitor resistor. Resistance device R may also be configured as a thin film resistor that can be temperature compensated to reduce the delay dependence on PVT variations. IN The delay T given to DLY may be given by the following relationship: T DLY =C L ·V REF2 / I DLY formula 6 Here, C L is the capacitor C of the delay line 250 12 ~C M2 are the capacitances of each of the DLY is the current drawn by the delay line 250.

[0042] Due to the voltage regulator 240, the reference voltage V REF2 is the reference voltage V REF1 The current I drawn by the delay line 250 is substantially equal to DLY may be given by the following relationship:

[0043]

number

[0044]

number

[0045]

number

[0046]

number

[0047]

number

[0048]

number

[0049]

number

[0050]

number

[0051] 3 illustrates a schematic diagram of an example switched capacitor resistor 300 according to another embodiment of the present disclosure. As previously described, the resistive device R of the signal delay circuit 200 may be implemented as a switched capacitor resistor 300.

[0052] In particular, the switched capacitor resistor 300 includes a first switching device SW1, a capacitor C3, and a second switching device SW2. The first switching device SW1 and the capacitor C3 are coupled in series between a node n3 and a lower voltage rail (e.g., ground). The second switching device SW2 is coupled in parallel to the capacitor C3. The open / closed state of the first switching device SW1 is controlled by a first clock signal CLK1, and the open / closed state of the second switching device SW2 is controlled by a second clock signal CLK2. In an exemplary implementation, the first and second clock signals CLK1 and CLK2 are coupled to the input signal S to the delay line 250. IN It may be based on.

[0053] In operation, during a first phase of the switching operation of the first and second switching devices SW1 and SW2, the first switching device SW1 is closed and the second switching device SW2 is open. Thus, during this phase, a current I2 charges the capacitor C3. During a second phase of the switching operation of the first and second switching devices SW1 and SW2, the first switching device SW1 is open and the second switching device SW2 is closed. Thus, during this phase, the charge stored in the capacitor C3 during the first phase flows through the second switching device SW2 to the low-voltage rail (e.g., ground). By alternating the open and closed states of the first and second switching devices SW1 and SW2 at a frequency f, the switched capacitor resistor 300 is configured to have a current I2 that satisfies the following relationship: R=1 / (C SW * f) where C SW is the capacitance of capacitor C3.

[0054] 4 illustrates a schematic diagram of an example of a ring oscillator 400 according to another embodiment of the present disclosure. The ring oscillator 400 may be an example of a more detailed implementation of the ring oscillator 220 described above.

[0055] The ring oscillator 400 has a set of N inverter stages 410-1 to 410-N, each inverter stage having a set of parallel inverters. For example, the first inverter stage 410-1 includes a first set of parallel inverters I11 to IS1; the second inverter stage 410-2 includes a second set of parallel inverters I12 to IS2; the third inverter stage 410-3 includes a third set of parallel inverters I13 to IS3, and so on until the Nth inverter stage 410-N includes a set of Nth parallel inverters I1N to ISN, where N is an odd integer as previously described and S is an integer. Thus, in this example, there are SxN inverters. The inputs of the parallel inverters of each stage are coupled together and to the coupled outputs of the parallel inverters of the previous inverter stage (including the input of the first inverter stage 410-1 coupled to the output of the last inverter stage 410-N). Similarly, the outputs of the parallel inverters of each stage are coupled to each other and to the coupled inputs of the parallel inverters of the subsequent inverter stage (including the output of the last inverter stage 410-N coupled to the input of the first inverter stage 410-1).

[0056] In this example, some of the inverters may be always on or enabled. The always enabled inverters are inverters I11-I1N. That is, at least one string of inverters may include an inverter that is always enabled such that the ring oscillator 400 oscillates without the delay controller 450. The other inverters may be selectively enabled inverters. In this example, the selectively enabled inverters are inverters I21-ISN. Each of the selectively enabled inverters includes a first switching device coupled between node n1 and an inverter PMOS FET and a second switching device coupled between the inverter NMOS FET and a lower voltage rail (e.g., ground). The delay controller 450 is coupled to the control inputs of the first and second switching devices of each of the selectively enabled inverters to control the open / closed state of the switching devices via a delay control signal (DCS).

[0057] 5 illustrates a block diagram of another example of a signal delay circuit 500 according to another aspect of the disclosure. The signal delay circuit 500 is similar to the previously described signal delay circuit 100 and includes many similar elements identified with the same reference numbers, except that the most significant digit is a "5" in the signal delay circuit 100 compared to a "1" in the signal delay circuit 500.

[0058] The signal delay circuit 500 differs from the signal delay circuit 100 in that the signal delay circuit 500 has a compensation current I COMP A leakage current I configured to be injected into the ring oscillator 520 to compensate for current leakage in the ring oscillator 520. LKG 5, further including compensation circuit 560. In particular, at certain technology nodes (e.g., 7 nanometer (nm) FIN FETs and more or different advanced technology nodes) and relatively high temperatures, ring oscillator 520 may experience significant current leakage.

[0059] To compensate for the current leakage of the ring oscillator 520, a leakage current I LKGThe compensation circuit 560 reduces the leakage current I LKG The sensor 562 and the compensation current I COMP Including the injector 564. The leakage current I LKG The sensor 562 detects the leakage current I LKG (e.g., leakage current I LKG (proportional to the estimated value of SNS The compensation current I COMP The injector 564 detects the sensed current I SNS Based on the compensation current I COMP and injecting the compensation current I COMP is the leakage current I LKG should be substantially the same as or within a specified tolerance.

[0060] 6 illustrates a schematic diagram of a portion of another exemplary signal delay circuit 600 according to another embodiment of the present disclosure. The signal delay circuit 600 has a leakage current I LKG It may be an exemplary more detailed implementation of a portion of the aforementioned signal delay circuit 200 with the addition of a compensation circuit. Common to both signal delay circuits 600 and 200 is a ring oscillator 620 and a control circuit 610 including an operational amplifier 612. It should be understood that the signal delay circuit 600 may also include a delay controller, a voltage regulator, and a delay line, similar to the signal delay circuit 200.

[0061] As described above, the signal delay circuit 600 reduces the leakage current I LKG The compensation circuit 660 is included. The leakage current I LKG The compensation circuit 660 includes a leakage current sensor 662 and a compensation current I COMP and an injector 664. The leakage current I LKG The sensor 662 detects the estimated leakage current I LKG The sense current I is a scaled down (1 / K) version of SNS where 1 / K is a scaling factor.

[0062] Compensation current I COMP The injector 664 injects a leakage current I between the upper voltage rail VDD and a lower voltage rail (e.g., ground). LKG A PMOS FET M4 is coupled in series with the sensor 662. The compensation current I COMP The injector 664 includes a PMOS FET M5 coupled between the upper voltage rail VDD and node n1. The gates of the PMOS FETs M5 and M4 are coupled together and to the drain of the PMOS FET M4 to form a current mirror. The sizes of the PMOS FETs M5 and M4 are such that the sense current I SNS , may be configured to provide a current mirror ratio K to compensate for a scaled version of the estimated leakage current in . Thus, the compensation current I COMP The injector 664 detects the sensed current I SNS The compensation current I COMP The compensation current I COMP is supplied to the ring oscillator 620 via node n1.

[0063] 7 illustrates a schematic diagram of a portion of another exemplary signal delay circuit 700 according to another aspect of the present disclosure. The signal delay circuit 700 is a variation of the signal delay circuit 600, and has many of the same elements identified by the same reference numerals, except that the most significant digit in the case of the signal delay circuit 700 is a "7". The signal delay circuit 700 includes a compensation current I COMP The injector 764 differs from (i.e., is related to) the signal delay circuit 800 in that it further includes a current input error amplifier that forces the voltages at nodes n1 and n4 to be substantially the same or within a certain percentage difference (e.g., 20%). In other words, the current input error amplifier is configured to control a first voltage across the leakage current sensor 762 to be related to a second voltage at the first node n1. In a fast corner, the difference in the voltages at nodes n1 and n4 is a compensation current I COMPand the sensed leakage current occurring in the ring oscillator 720. The current input error amplifier also improves the power source rejection ratio (PSRR) so that power source variations can be reduced by the compensation current I COMP In this example, the current input error amplifier includes NMOS FETs M7 and M6 coupled between PMOS FETs M5 and M4 and nodes n1 and n4, respectively. The gates of NMOS FETs M7 and M6 are coupled to the drain of NMOS FET M7.

[0064] 8 illustrates a schematic diagram of a portion of another exemplary signal delay circuit 800 according to another embodiment of the present disclosure. The signal delay circuit 800 has a leakage current I LKG It may be an exemplary more detailed implementation of a portion of the aforementioned signal delay circuit 200 with the addition of a compensation circuit. Common to both the signal delay circuit 800 and the signal delay circuit 200 is a ring oscillator 820 and a control circuit 810 including an operational amplifier 812. It should be understood that the signal delay circuit 800 may also include a delay controller, a voltage regulator, and a delay line, similar to the signal delay circuit 200.

[0065] As previously mentioned, the signal delay circuit 800 includes a leakage current sensor (e.g., represented as a current source) coupled in parallel with a resistive device R of the control circuit 810 to measure the leakage current I LKG The compensation circuit 862 includes a leakage current sensor 862 that detects an estimated leakage current I LKG The sensed current I is essentially equal to 1 / X multiplied by SNS where X is the current ratio of the current mirror formed by the PMOS FETs M1 and M2 as previously described. Thus, the current mirror is configured to generate the sense current I SNS is amplified by the current ratio X to produce the compensation current I COMP and generates the compensation current I COMP is the leakage current I generated in the ring oscillator 820. LKG is substantially equal to the estimated value of (for example, within a defined tolerance of the estimate). COMPis the leakage current I LKG Therefore, in this embodiment, the compensation current I COMP is provided to the ring oscillator 820 via the control circuit 810.

[0066] 9 illustrates a schematic diagram of an example leakage current sensor 900 according to another embodiment of the present disclosure. The leakage current sensor 900 may be an example more detailed implementation of any one of the leakage current sensors 662, 762, and 862. The leakage current sensor 900 includes a dummy (non-operating) inverter M 15 / M 16 ~M T5 / M T6 The inverters are dummy or non-operational because their inputs (gates) are tied to either node n4, such as in signal delay circuits 600 and 700, or node n3, such as in signal delay circuit 800, or a lower voltage rail (e.g., ground). As an example, substantially half of the inverters may have their inputs associated with a lower voltage rail (e.g., ground) and substantially the other half may have their inputs associated with nodes n4 or n3.

[0067] The number of inverters in the leakage current sensor 900 should be near a scaled factor (e.g., 1 / K or 1 / X) of the number of enabled inverters in the corresponding ring oscillator. Because the number of enabled inverters in the corresponding ring oscillator may vary depending on the desired delay of the delay line, the number of inverters in the leakage current sensor 900 may be set to the average or median of the number of enabled inverters in the corresponding ring oscillator. The current drawn by the leakage current sensor 900 is the sensed current I as previously described. SNS It is.

[0068] 10 shows a schematic diagram of another exemplary leakage current sensor 1000 according to another aspect of the disclosure. The leakage current sensor 1000 may be an example of a more detailed implementation of any one of the leakage current sensors 662, 762, and 862. The leakage current sensor 1000 includes a dummy (non-operating) inverter M that is always enabled. 16 / M 17 ~M U6 / M U7 , and a selectively enabled dummy (non-operating) inverter M 18 / M 19 ~M V8 / M V9 and a set of selectively enabled dummy (non-operating) inverters M 18 / M 19 ~M V8 / M V9 The set of switching devices SW 18 / SW 19 ~SW V8 / SW V9 and a switching device SW 18 / SW 19 ~SW V8 / SW V9 may be controlled by a delay control signal (DCS) generated by a corresponding delay controller. That is, the delay controller can enable the number of selectively enabled inverters in the leakage current sensor 1000 to be a scaling factor (e.g., 1 / K or 1 / X) of the number of enabled inverters in the corresponding ring oscillator via the delay control signal (DCS). The current drawn by the leakage current sensor 1000 is the sensed current I SNS It is.

[0069] 11 illustrates a flow diagram of an example method 1100 of delaying a signal according to another aspect of the disclosure. The method 1100 includes generating an oscillating signal based on a first voltage and a first current (Block 1110). Examples of means for generating an oscillating signal based on the first voltage and the first current include any of the ring oscillators described herein.

[0070] The method 1100 further includes controlling the first voltage and the first current such that a ratio of the first voltage to the first current is substantially constant (block 1120). Examples of means for controlling the first voltage and the first current such that a ratio of the first voltage to the first current is substantially constant include any of the control circuits described herein.

[0071] Further, the method 1100 includes delaying the input signal to generate an output signal based on a second voltage relative to the first voltage (block 1130). Examples of means for delaying the input signal to generate an output signal based on a second voltage relative to the first voltage include any of the delay lines described herein.

[0072] Controlling the first voltage and the first current may include generating a second current related to the first current, routing the second current to a resistive device to generate a third voltage, and controlling the first and second currents based on a difference between the third voltage and the first voltage, where the first voltage is based on the first current. Means for generating the second current related to the first current may include, for example, any current mirror including PMOS FETs M1 and M2. An example of a means for routing the second current through a resistive device to generate the third voltage may include any coupling of a current mirror to a resistive device R. An example of a means for controlling the first and second currents based on a difference between the third voltage and the first voltage may include any of the operational amplifiers 212, 812, 912, 1012.

[0073] The method may further include regulating the first voltage including selectively enabling one or more parallel inverters of the ring of cascaded parallel inverters. An example of the means for enabling one or more parallel inverters of the ring of cascaded parallel inverters includes any of the delay controllers described herein. The method may further include sensing a leakage current in the ring oscillator and providing a compensation current to the ring oscillator based on the sensed leakage current. An example of the means for sensing a leakage current in the ring oscillator includes any of the leakage current sensors described herein. An example of the means for providing a compensation current to the ring oscillator based on the sensed leakage current includes any of the compensation current sensors described herein. COMP In one embodiment, the compensation current may include a compensation injector. Providing the compensation current to the ring oscillator may include providing the compensation current to the ring oscillator via a control circuit for controlling the first voltage. An example of a means for providing the compensation current to the ring oscillator via a control circuit may include coupling a leakage current sensor 862 to the control circuit described herein.

[0074] 12 illustrates a block diagram of an example of a wireless communication device 1200 according to another aspect of the present disclosure. The wireless communication device 1200 includes an integrated circuit (IC) 1210, which may be implemented as a system on a chip (SOC). The SOC 1210 includes one or more baseband signal processing modules 1220.

[0075] The wireless communication device 1200 further includes a transceiver (Tx / Rx) 1230 coupled to the one or more baseband signal processing modules 1220 to receive a baseband transmit signal BB_TX therefrom and to provide a baseband receive signal BB_RX thereto. The transceiver (Tx / Rx) 1230 may include a baseband amplifier 1232, an upconversion mixer 1234, a radio frequency (RF) filter 1236, and a power amplifier 1238. These devices 1232, 1234, 1236, and 1238 cascaded together with a mixer 1234 coupled to a local oscillator (LO) 1240 are configured to convert the baseband transmit signal BB_TX to an RF transmit signal RF_TX. The transceiver (Tx / Rx) 1230 further includes a low noise amplifier (LNA) 1242, a downconversion mixer 1244, a baseband filter 1246, and a baseband amplifier 1248. These devices 1242, 1244, 1246, and 1248, cascaded together along with a mixer 1244 coupled to a local oscillator (LO) 1240, are configured to convert the RF receive signal RF_RX to a baseband receive signal BB_RX.

[0076] The wireless communication device 1200 further includes an antenna interface 1250 and at least one antenna 1260. The transceiver 1230 is coupled to the at least one antenna 1260 via the antenna interface 1250. The antenna interface 1250 is configured to route an RF transmit signal RF_TX to the at least one antenna 1260 for over-the-air transmission thereof. The antenna interface 1250 is also configured to route an RF receive signal RF_RX received over-the-air via the at least one antenna 1260 to the transceiver 1230. The local oscillator (LO) 1240 may include a delay-locked loop (DLL) or a phase-locked loop (PLL) including any of the signal delay circuits described herein.

[0077] The following provides a summary of aspects of the disclosure. Aspect 1: A voltage regulator including: a ring oscillator coupled between a first node and a first voltage rail; a control circuit coupled to the first node; a delay line coupled between a second node and the first voltage rail; an input coupled to the first node; and an output coupled to the second node; 13. An apparatus comprising:

[0078] Aspect 2: A control circuit includes a resistor device, a first current source coupled in series with the resistor device between a second voltage rail and a first voltage rail, and a second current source coupled between the second voltage rail and a first node; an operational amplifier including a first input coupled to a third node between the first current source and the resistive device, a second input coupled to the first node, and outputs coupled to control inputs of the first current source and the second current source, respectively; 2. The apparatus of embodiment 1, comprising:

[0079] Example 3: The apparatus of example 2, wherein the resistive device comprises a switched capacitor resistor or a thin film resistor.

[0080] Example 4: The apparatus of any of Examples 2 or 3, further comprising a leakage current compensation circuit coupled between the third node and the first voltage rail.

[0081] Example 5: The apparatus of Example 4, wherein the leakage current compensation circuit includes a leakage current sensor.

[0082] Example 6: The apparatus of example 5, wherein the leakage current sensor includes a set of dummy inverters.

[0083] Example 7: The apparatus of example 5 or 6, further comprising a delay controller coupled to the ring oscillator and the leakage current sensor.

[0084] Example 8: The apparatus of any one of Examples 1 to 7, wherein the control circuit is configured to control an operating point of the ring oscillator.

[0085] Example 9: The apparatus of any one of examples 1 to 7, further comprising a delay controller coupled to the ring oscillator.

[0086] Example 10: The apparatus of any one of examples 1 to 9, wherein the ring oscillator includes a ring of cascaded inverters coupled between a first node and a first voltage rail, and a set of capacitors respectively coupled between outputs of the ring of cascaded inverters and the first voltage rail.

[0087] Example 11: The apparatus of example 10, wherein each of the cascaded inverters of the ring oscillator includes a set of selectable parallel inverters.

[0088] Example 12: The apparatus of example 11, further comprising a delay controller coupled to select an input of the set of selectable parallel inverters.

[0089] Example 13: The apparatus of any one of examples 1 to 12, wherein the delay line includes a set of cascaded inverters coupled between the second node and a first voltage rail, the set including an input configured to receive an input signal and an output configured to generate an output signal that is a delayed version of the input signal, and a set of capacitors respectively coupled between the outputs of the set of cascaded inverters and the first voltage rail.

[0090] Example 14: The apparatus of any one of examples 1 to 13, wherein the voltage regulator comprises a low dropout (LDO) regulator.

[0091] Example 15: The apparatus of any one of examples 1 to 13, wherein the voltage regulator includes a field effect transistor (FET) coupled between the second voltage rail and the second node, and an operational amplifier having a first input coupled to the first node, a second input coupled to the second node, and an output coupled to a gate of the FET.

[0092] Example 16: The apparatus of any one of Examples 1 to 15, further comprising a low pass filter (LPF) coupled to the first node or the second node.

[0093] Example 17: The apparatus of any one of Examples 1 to 4 and 9 to 16, further comprising a leakage current compensation circuit coupled to the first node.

[0094] Example 18: The apparatus of example 17, wherein the leakage current compensation circuit includes a leakage current sensor and a current mirror coupled to the leakage current sensor and the first node.

[0095] Example 19: The apparatus of Example 18, wherein the leakage current compensation circuit includes a current input error amplifier configured to control a first voltage across the leakage current sensor to be related to a second voltage at the first node.

[0096] Aspect 20: generating an oscillating signal based on a first voltage and a first current; controlling the first voltage and the first current such that a ratio of the first voltage to the first current is substantially constant; and delaying an input signal to generate an output signal based on a second voltage related to the first voltage; A method comprising:

[0097] Aspect 21: Controlling the first voltage and the first current includes generating a second current related to the first current, routing the second current through a resistive device to generate a third voltage, and controlling the first current and the second current based on a difference between the third voltage and the first voltage, where the first voltage is based on the first current; The method of embodiment 20, comprising:

[0098] Example 22: The method of example 20 or 21, further comprising regulating the first voltage comprising selectively enabling one or more parallel inverters of the ring of cascaded parallel inverters.

[0099] Example 23: The method of any one of Examples 20 to 22, further comprising: sensing a leakage current in the ring oscillator; and supplying a compensation current to the ring oscillator based on the sensed leakage current.

[0100] Example 24: The method of example 23, wherein providing the compensation current to the ring oscillator includes providing the compensation current to the ring oscillator via a control circuit for controlling the first voltage and the first current.

[0101] Aspect 25: A device comprising: a means for generating an oscillating signal based on a first voltage and a first current; a means for controlling the first voltage and the first current such that a ratio of the first voltage to the first current is substantially constant; and a means for delaying an input signal to generate an output signal based on a second voltage related to the first voltage. 13. An apparatus comprising:

[0102] Example 26: The apparatus of example 25, further comprising means for regulating the first voltage including means for selectively enabling one or more parallel inverters of the ring of cascaded parallel inverters.

[0103] Example 27: The apparatus of example 25 or 26, wherein the means for generating the vibration signal includes means for sensing a leakage current in the ring oscillator and means for supplying a compensating current to the ring oscillator based on the sensed leakage current.

[0104] Aspect 28: One or more baseband signal processing modules, at least one antenna, a transceiver coupled to the at least one antenna and the one or more baseband signal processing modules, comprising: a ring oscillator coupled between a first node and a first voltage rail; a control circuit coupled to the first node; a delay line coupled between a second node and the first voltage rail; and a voltage regulator including an input coupled to the first node and an output coupled to the second node; a transceiver; and a wireless communication device.

[0105] Aspect 29: The wireless communication device of aspect 28, wherein the ring oscillator includes a ring of cascaded inverters coupled between a first node and a first voltage rail, each of the cascaded inverters including a selectable set of parallel inverters, and the wireless communication device further includes a delay controller coupled to each of the selectable sets of parallel inverters of the cascaded inverters.

[0106] Example 30: The wireless communication device of example 28 or 29, further including a leakage current compensation circuit coupled to the first node or the control circuit.

[0107] The above description of the disclosure is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be readily apparent to those skilled in the art, and the general principles defined herein can be applied to other variations without departing from the spirit or scope of the disclosure. Thus, the disclosure is not intended to be limited to the embodiments described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A ring oscillator having a power supply terminal and a ground terminal, the ring oscillator being coupled between a first node and a first voltage rail via the power supply terminal to the first node and via the ground terminal to the first voltage rail; a control circuit coupled to the first node; a delay line coupled between a second node and the first voltage rail; A voltage regulator including an input coupled to the first node and an output coupled to the second node, a field effect transistor (FET) coupled between a second voltage rail and the second node; an operational amplifier including a first input coupled to the first node, a second input coupled to the second node, and an output coupled to a gate of the FET; a voltage regulator comprising: Equipped with The control circuit A resistive device; a first current source coupled in series with the resistive device between the second voltage rail and the first voltage rail; a second current source coupled between the second voltage rail and the first node; an operational amplifier including a first input coupled to a third node between the first current source and the resistive device, a second input coupled to the first node, and outputs coupled to control inputs of the first current source and the second current source, respectively; An apparatus comprising:

2. The apparatus of claim 1 , wherein the resistive device comprises a switched capacitor resistor or a thin film resistor.

3. 10. The apparatus of claim 1, further comprising a leakage current compensation circuit coupled between the third node and the first voltage rail.

4. The apparatus of claim 3 , wherein the leakage current compensation circuit comprises a leakage current sensor.

5. The apparatus of claim 4 , wherein the leakage current sensor comprises a set of dummy inverters.

6. The apparatus of claim 4 , further comprising a delay controller coupled to the ring oscillator and the leakage current sensor.

7. The apparatus of claim 1 , wherein the control circuit is configured to control an operating point of the ring oscillator.

8. The apparatus of claim 1 , further comprising a delay controller coupled to the ring oscillator.

9. The ring oscillator comprises: a ring of cascaded inverters coupled between the first node and the first voltage rail; a set of capacitors respectively coupled between the outputs of the ring of cascaded inverters and the first voltage rail; The apparatus of claim 1 , comprising:

10. 10. The apparatus of claim 9, wherein each of the cascaded inverters of the ring oscillator comprises a selectable set of parallel inverters.

11. The apparatus of claim 10 , further comprising a delay controller coupled to enable the input of the set of selectable parallel inverters.

12. The delay line: a set of cascaded inverters coupled between the second node and the first voltage rail, the set of cascaded inverters including an input configured to receive an input signal and an output configured to generate an output signal that is a delayed version of the input signal; a set of capacitors respectively coupled between the outputs of the set of cascaded inverters and the first voltage rail; The apparatus of claim 1 , comprising:

13. 2. The apparatus of claim 1, wherein the voltage regulator comprises a low dropout (LDO) regulator.

14. The apparatus of claim 1 , further comprising a low pass filter (LPF) coupled to at least one of the first node or the second node.

15. The apparatus of claim 1 , further comprising a leakage current compensation circuit coupled to the first node.

16. The leakage current compensation circuit includes: A leakage current sensor; a current mirror coupled to the leakage current sensor and the first node; 16. The apparatus of claim 15, comprising:

17. 17. The apparatus of claim 16, wherein the leakage current compensation circuit comprises a current input error amplifier configured to control a first voltage across the leakage current sensor to be related to a second voltage at the first node.

18. one or more baseband signal processing modules; At least one antenna; a transceiver coupled to the at least one antenna and to the one or more baseband signal processing modules, a ring oscillator having a power supply terminal and a ground terminal, the ring oscillator being coupled between a first node and a first voltage rail via the power supply terminal and coupled to the first voltage rail via the ground terminal; a control circuit coupled to the first node; a delay line coupled between a second node and the first voltage rail; A voltage regulator including an input coupled to the first node and an output coupled to the second node, a field effect transistor (FET) coupled between a second voltage rail and the second node; an operational amplifier having a first input coupled to the first node, a second input coupled to the second node, and an output coupled to a gate of the FET; a voltage regulator comprising: Equipped with The control circuit A resistive device; a first current source coupled in series with the resistive device between the second voltage rail and the first voltage rail; a second current source coupled between the second voltage rail and the first node; an operational amplifier including a first input coupled to a third node between the first current source and the resistive device, a second input coupled to the first node, and outputs coupled to control inputs of the first current source and the second current source, respectively; A wireless communication device comprising:

19. 20. The wireless communication device of claim 18, wherein the ring oscillator comprises a ring of cascaded inverters coupled between the first node and the first voltage rail, each of the cascaded inverters comprising a selectable set of parallel inverters, and the wireless communication device further comprises a delay controller coupled to each of the selectable sets of parallel inverters of the cascaded inverters.

20. 20. The wireless communication device of claim 18, further comprising a leakage current compensation circuit coupled to the first node or the control circuit.

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