Fast rise sample-and-hold switched-capacitor circuit

Abstract

A switched capacitor circuit for a capacitive sensor system includes an amplifier having a first input terminal, a second input terminal, and an output coupled to the second input terminal. The first input terminal is a non-inverting input terminal and the second input terminal is an inverting input terminal. The switched capacitor circuit further includes a first capacitor, a first switch configured to selectively couple the first capacitor to an input voltage to charge the first capacitor, a second switch configured to selectively couple the first capacitor to the first input terminal, a second capacitor, a third switch configured to selectively couple the second capacitor to the first input terminal, and a fourth switch configured to selectively couple the second capacitor to an output of the amplifier.

Description

[Technical field]

[0001] The present disclosure relates to capacitive sensors, and more particularly to switched-capacitor circuits configured as filters for capacitive sensors. [Background technology]

[0002] The background description provided herein is intended to provide a general background to the present disclosure. The work of the presently named inventors, to the extent described in this Background section, and aspects of the description that may not otherwise be regarded as prior art at the time of filing, are not admitted, either explicitly or implicitly, as prior art to the present disclosure.

[0003] The electronic device may implement a capacitive sensor configured to detect contact between an object (e.g., a finger) and a surface, e.g., a surface of the electronic device, and generate a detection signal indicative of the detection of the contact. For example, a reference signal generator (e.g., a waveform generator) is configured to generate and output a control signal to the capacitive sensor. In some examples, the control signal is a sinusoidal wave (i.e., the control signal is a sine wave). The detection signal corresponds to a change in amplitude and phase of the control signal based on whether an object is contacting the sensor. Thus, the presence or absence of an object contacting the sensor can be determined based on the amplitude and phase of the detection signal.

[0004] The sense signal may be provided to and sampled by an analog-to-digital circuit (ADC) via a sample-and-hold circuit configured to generate an output voltage according to a weighted average of input voltages corresponding to the sense signal. For example, the sample-and-hold may include a switched capacitor circuit. An example of a switched capacitor circuit is described in US Pat. No. 6,399,363. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] U.S. Patent No. 4,769,612 Summary of the Invention [Problem to be solved by the invention]

[0006] A technical problem associated with conventional switched capacitor circuits is that multiple switched capacitor sampling periods (and associated delays or rise times) are required for the output voltage to reach the average of the input voltage. The switched capacitor circuit of the present disclosure provides a solution to the above technical problem by presetting the capacitors of the switched capacitor circuit to initial sample values ​​and gradually increasing the values ​​to reduce the rise time and the number of sampling periods required for the output voltage (e.g., the output voltage average) to reach the input voltage average. [Means for solving the problem]

[0007] A switched capacitor circuit for a capacitive sensor system includes an amplifier having a first input terminal, a second input terminal, and an output coupled to the second input terminal. The first input terminal is a non-inverting input terminal and the second input terminal is an inverting input terminal. The switched capacitor circuit further includes a first capacitor, a first switch configured to selectively couple the first capacitor to an input voltage to charge the first capacitor, a second switch configured to selectively couple the first capacitor to the first input terminal, a second capacitor, a third switch configured to selectively couple the second capacitor to the first input terminal, and a fourth switch configured to selectively couple the second capacitor to an output of the amplifier.

[0008] In other features, the amplifier is an operational amplifier configured as a unity gain buffer. The first and second capacitors have approximately equal capacitance. The first and second capacitors have different capacitance. An output of the amplifier corresponds to an average of the charge on each of the first and second capacitors. A fourth switch is configured to couple the second capacitor to the output of the amplifier during a first sampling period, and a third switch is configured to couple the second capacitor to the first input terminal during a second sampling period.

[0009] In other features, the switched capacitor circuit further includes a third capacitor and a fifth switch. The third switch and the fourth switch are configured to selectively couple the third capacitor to the first input terminal. The fifth switch is configured to selectively couple the third capacitor to an output of the amplifier. The switched capacitor circuit further includes a fourth capacitor and a sixth switch. The third switch, the fourth switch, and the fifth switch are configured to selectively couple the fourth capacitor to the first input terminal, and the sixth switch is configured to selectively couple the fourth capacitor to the output of the amplifier. The switched capacitor circuit further includes a fifth capacitor and a seventh switch. The third switch, the fourth switch, the fifth switch, and the sixth switch are configured to selectively couple the fifth capacitor to the first input terminal, and the seventh switch is configured to selectively couple the fifth capacitor to the output of the amplifier.

[0010] In other features, the third switch, the fourth switch, the fifth switch, the sixth switch, and the seventh switch are configured to couple the second capacitor, the third capacitor, the fourth capacitor, and the fifth capacitor to the output of the amplifier during a first sampling period; couple the second capacitor to the first input terminal and the third capacitor, the fourth capacitor, and the fifth capacitor to the output of the amplifier during a second sampling period; couple the second capacitor and the third capacitor to the first input terminal and the fourth capacitor and the fifth capacitor to the output of the amplifier during a third sampling period; couple the second capacitor, the third capacitor, and the fourth capacitor to the first input terminal and the fifth capacitor to the output of the amplifier during a fourth sampling period; and couple the second capacitor, the third capacitor, the fourth capacitor, and the fifth capacitor to the first input terminal during a fifth sampling period.

[0011] In other features, the switched capacitor circuit further includes a sampling control module configured to control timing of opening and closing of the first switch, the second switch, the third switch, and the fourth switch. The switched capacitor circuit is included in a capacitive sensing system, the capacitive sensing system further includes an analog-to-digital converter coupled to an output of the amplifier. The capacitive sensing system further includes a sensor module configured to generate a sense signal indicative of at least one of contact with and proximity to an object. The input voltage corresponds to the sense signal.

[0012] A switched capacitor circuit for a capacitive sensor system includes an amplifier configured as a unity gain buffer having a first input terminal, a second input terminal, and an output coupled to the second input terminal, a first capacitor, a first switch configured to selectively couple the first capacitor to an input voltage to charge the first capacitor, a second switch configured to selectively couple the first capacitor to the first input terminal, a plurality of second capacitors, and a plurality of switches configured to selectively couple a second capacitor selected from the plurality of second capacitors to either the first input terminal or the output of the amplifier.

[0013] In other features, the first capacitor and each of the plurality of second capacitors have substantially equal capacitance. The first capacitor and one of the plurality of second capacitors have different capacitance. The first input terminal is a non-inverting input terminal and the second input terminal is an inverting input terminal. The switched capacitor circuit further includes a sampling control module configured to control timing of opening and closing of the first switch, the second switch, and the plurality of switches. The sampling control module is configured to selectively connect each of the plurality of second capacitors to an output of the amplifier and selectively connect each of the plurality of second capacitors to the first input terminal.

[0014] Further areas of applicability of the present application will become apparent from the detailed description, claims, and drawings. The detailed description and specific examples are for purposes of illustration only and are not intended to limit the scope of the disclosure. Effect of the Invention

[0015] In accordance with embodiments of the present disclosure, the rise time and number of sampling periods required for the output voltage to reach the input voltage average can be reduced. [Brief description of the drawings]

[0016] The present disclosure will become more fully understood from the detailed description and the accompanying drawings. [Figure 1] 1 is an example of an electronic device that includes a capacitive sensor. [Figure 2A] 1 is an example of a reference signal generator for a capacitive sensor. [Figure 2B] 1 is an example of a reference signal generator for a capacitive sensor. [Diagram 3] 1 is an example of a capacitive sensor system implementing a switched-capacitor circuit for a capacitive sensor in accordance with the present disclosure. [Figure 4A] 1 is an example of a switched capacitor circuit according to the prior art. [Figure 4B] 1 is an example of a switched capacitor circuit according to the prior art. [Diagram 5]4A or 4B show an example of sample-and-hold averaging using the circuitry of FIG. [Figure 6A] 1 is an example of a switched capacitor circuit according to the present disclosure. [Figure 6B] 1 is an example of a switched capacitor circuit according to the present disclosure.

[0017] Throughout the drawings, reference numbers may be reused to identify similar and / or identical elements. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0018] Changes in the signal (corresponding to the sensed signal) supplied to the capacitive sensor in response to contact with an object are usually small relative to the supplied signal (i.e. the control or drive signal) and can be difficult to detect. Various methods can therefore be implemented to improve detection of the changes. For example, a reference signal generator that supplies a signal to the sensor may also supply a replica of the signal, or a second reference signal generator can be provided to supply a replica of the signal. The replica signal is subtracted from the supplied signal and the result may be amplified to improve detection, corresponding to the sensed signal.

[0019] In some examples, the reference signal generator is a sine wave generator, such as a Wien bridge oscillator circuit. In other examples, the reference signal generator may be configured to provide a digital sine wave to a digital-to-analog converter (DAC), the output of which is filtered and / or amplified. In some examples, the offset control module is configured to generate an offset signal that is a replica of the sensed signal when there is no contact between the object and the capacitive sensor.

[0020] In some examples, an electronic device that includes a capacitive sensor may include a regulator circuit (e.g., a voltage-controlled current-mode regulator) coupled to an output of the capacitive sensor, the regulator circuit configured to regulate an output voltage of the capacitive sensor (corresponding to a sensed signal) and generate an output current indicative of the sensed signal.

[0021] In some examples, the sense signal (or an output signal indicative of the sense signal) is sampled by an analog-to-digital converter (ADC). The output signal may be provided to the ADC via a sample-and-hold circuit configured to generate an output according to a weighted average of the sense signal. For example, the sample-and-hold circuit may include a switched capacitor circuit, such as a switched capacitor, single-pole low-pass filter (LPF) circuit, etc.

[0022] A switched capacitor circuit is configured to receive (e.g., sample) an input voltage and generate an output voltage that corresponds to an average of sampled values ​​of the input voltage (i.e., the input voltage average). The output voltage may start from an initialized value (e.g., a reference voltage, ground, etc.) and gradually reach a value that corresponds to the input voltage average. Typically, multiple switched capacitor sampling periods (and associated delays or rise times) are required for the output voltage to reach the input voltage.

[0023] A switched capacitor circuit according to the present disclosure is configured to reduce the number of sampling periods required for an output voltage (e.g., an output voltage average) to reach an input voltage average. For example, a filter capacitor of a switched capacitor circuit may be preset to an initial sample value and gradually increased to the value of the input voltage to reduce rise time, as described in more detail below.

[0024] 1, an example electronic device 100 is shown including a sensor module 104 that supports a capacitive sensor. A reference signal generator (e.g., a waveform generator) 108 provides a reference or control signal (e.g., a square wave, a sine wave, etc.) 110 to the sensor module 104. The reference signal generator 108 may provide the control signal 110 to an offset control module 112, or an optional second reference signal generator 116 may provide a copy of the control signal 110 to the offset control module 112.

[0025] The sensor module 104 modifies the control signal to generate a sense signal 118 based on the control signal 110 and the proximity or closeness of a sensed object. In other words, the sense signal 118 corresponds to the control signal 110 modified according to the detection of an object (e.g., contact and / or closeness of an object). The sense signal 118 indicates whether an object (e.g., a finger) is in contact with the sensor module 104. In some examples, the sense signal 118 indicates the proximity of the object to the sensor module 104. The sense signal 118 may differ (e.g., in amplitude and / or phase) from the control signal 110 regardless of whether an object is in contact with the sensor module 104.

[0026] In one example, the offset control module 112 is configured to generate an offset signal 120 that is a replica of the sensed signal 118 in the absence of contact between the object and the sensor module 104. In other words, the offset control module 112 is configured to modify the control signal 110 in the same manner as the sensor module 104 would when there is no contact between the object and the sensor module 104 (and / or, in some examples, when the object is not close enough to the sensor module 104 to affect the sensed signal 118). As such, when there is no contact with an object, the sensed signal 118 and the offset signal 120 will be essentially equal (e.g., in amplitude, phase, and / or both amplitude and phase), and the difference between the sensed signal 118 and the offset signal 120 will approach zero. In another example, the offset signal 120 may be configured to have an opposite polarity relative to the control signal 110 and may simply be summed with the sensed signal 118.

[0027] In contrast, when there is contact between an object and the sensor module 104, the offset signal 120 and the sense signal 118 will be different. The regulator circuit 124 outputs and amplifies the difference between the offset signal 120 and the sense signal 118. The regulator circuit 124 is further configured to regulate the voltage provided to the sensor module (e.g., the voltage of the control signal 110). For example, the regulator circuit 124 may be a voltage-controlled current-mode regulator implemented as a current conveyor.

[0028] An output signal 128 (e.g., an output current) of the regulator circuit 124 indicative of the sense signal 118 may then be processed to detect contact between the sensor module 104 and an object. For example, contact may be determined based on whether the amplitude and / or phase of the output signal 128 exceed respective thresholds. In some examples, the sense signal 118 may indicate the proximity of an object to the sensor module 104, regardless of whether the object is in direct contact with the sensor module 104. In such examples, the sense signal 118 may further indicate the distance between the object and the sensor module 104.

[0029] The output signal 128 is provided to an output signal path (e.g., an output signal path of a capacitive sensor system of the electronic device 100) such as to an ADC via a switched capacitor sample and hold circuit in accordance with the principles of the present disclosure (described in further detail below).

[0030] In some examples, the reference signal generator 108 implements a sine wave generator such as a Wien bridge oscillator circuit, which may be difficult to adjust and / or modulate in amplitude. In other examples, the reference signal generator 108 may generate a digital sine wave that is then converted to an analog sine wave. For example, as shown in FIG. 2A and FIG. 2B, the reference signal generator 108 may include a digital sine wave generator 200. In FIG. 2A, an analog DAC 204 converts the digital sine wave to an analog signal, which is then filtered and amplified (or, in some examples, attenuated) using an LPF 208 with gain control capabilities. For example, an amplitude control signal is provided to the LPF 208 to control the gain. The LPF 208 may be a first order filter to reduce cost, or, in some examples, may be a second order, third order, or higher order filter. In other examples, a band pass filter may be used.

[0031] 2B, in contrast, a multiplier 212 is provided between the digital sine wave generator 200 and the analog DAC 204. An amplitude control signal is provided to the multiplier 212 to control the gain. The output of the multiplier 212 (corresponding to the amplified digital sine wave) is provided to the analog DAC 204. The analog signal output by the analog DAC 204 is filtered using a LPF 216 that does not have gain control.

[0032] 3, an example capacitive sensor system 300 (e.g., for electronic device 100) is shown including a sensor module 304 (e.g., a capacitive sensor) and a sample and hold circuit 308 implemented according to the present disclosure. A reference signal generator 312 outputs a reference or control signal 316 (e.g., a digital waveform such as a square wave, an analog sine wave, a digital sine wave converted to an analog sine wave, etc.). The control signal 316 is provided to the sensor module 304 via a regulator circuit 318 and, in some examples, to an offset control module 320. The offset control module 320 is configured to generate an offset signal 324 based on the control signal 316. The offset signal 324 is provided to the regulator circuit 318.

[0033] The sensor module 304 corresponds to a capacitive sensor (e.g., a capacitive touch circuit) that includes one or more parasitic capacitances (e.g., a parasitic capacitance Crg) that modify the amplitude and phase of a control signal 316 provided to the regulator circuit 318. In some examples, the control signal 316 is coupled to one or more sense electrodes through a capacitance Crs. When an object (e.g., a finger 332) approaches (i.e., comes within proximity of) and / or contacts one or more sense electrodes of the sensor module 304, the capacitance 336 of the finger 332 further modifies the amplitude and phase of a sense signal 340 that is based on the control signal 316. Thus, the sensor module 304 generates a sense signal 340 as an output voltage that indicates whether an object, such as a finger 332, is in contact with the sensor module 304 or, in some examples, the proximity of the finger 332 to the sensor module 304. More specifically, the sense signal 340 is modified according to the detected capacitance 336.

[0034] The regulator circuit 318 detects and outputs an indication of the sense signal 340. In some examples, the regulator circuit 318 detects and outputs a difference between the sense signal 340 and the offset signal 324. For example, the offset control module 320 is configured such that the sense signal 340 and the offset signal 324 (i.e., the amplitude and phase of each of the sense signal 340 and the offset signal 324) are the same when there is no contact between the sensor module 304 (e.g., one or more sensing electrodes) and an object, such as a finger 332. In some examples, the offset control module 320 is configured to adjust the phase and amplitude of the offset signal 324 such that the output of the regulator circuit 318 (e.g., the output signal 344 corresponding to the output current) is approximately zero when there is no contact between the sensor module 304 (e.g., one or more sensing electrodes) and an object.

[0035] In other words, the offset control module 320 is configured to adjust the phase and amplitude of the offset signal 324 so that the phase and amplitude of the offset signal 324 match the phase and amplitude of the sense signal 340, respectively, when the sense electrodes of the sensor module 304 do not sense the proximity of or contact with an object. For example, the parasitic capacitances Crs and Crg change the amplitude and phase of the control signal 316. The offset control module 320 adjusts the amplitude and phase of the offset signal 324 to compensate for the change in the control signal 316 caused by the parasitic capacitances Crs and Crg. The output of the regulator circuit 318 (i.e., the output signal 344) indicates whether there is contact between the sensor module 304 and the finger 332, or in some examples, the proximity of the finger 332 to the sensor module 304, based on the comparison between the sense signal 340 and the offset signal 324.

[0036] The regulator circuit 318 receives a control signal 316 from the reference signal generator 312 (e.g., as an input voltage of the regulator circuit 318). The regulator circuit 318 is configured to regulate a voltage (e.g., the voltage of the control signal 316) coupled to the sensor module 304. In some examples, the voltage coupled to the sensor module 304 corresponds to a voltage coupled to any sensor input / output (I / O) pad that is further coupled to an output of the sensor module 304. Thus, a sense signal 340 is generated based on the control signal 316 and corresponds to an output voltage of the regulator circuit 318 as further modified by the detected capacitance 336. The regulator circuit 318 generates an output signal 344 (e.g., an output current) indicative of the sense signal 340.

[0037] The sample and hold circuit 308 receives the output signal 344 as an input voltage. The control signal 316 (and therefore the output signal 344) is a periodic signal, such as a sine wave, a square wave, etc. As such, the input voltage of the sample and hold circuit 308 varies. The sample and hold circuit 308 is configured to sample the value of the input voltage and generate an output voltage 352 corresponding to the average of the sampled values ​​of the input voltage (i.e., the input voltage average). In this manner, the output voltage 352 is indicative of the output signal 344, and therefore the sense signal 340. The ADC 356 converts the samples of the output voltage 352 to digital values ​​for further processing by the capacitive sensor system 300. The sample and hold circuit 308 of the present disclosure implements a switched capacitor circuit, which is described in more detail below.

[0038] Exemplary conventional switched capacitor circuits 400 and 404 are shown in Figures 4A and 4B, respectively. The switched capacitor circuits 400 and 404 include an amplifier (e.g., an operational amplifier) ​​408 that is coupled to an input voltage Vin via one or more capacitors and switches. As shown in Figure 4A, the input voltage is coupled to a positive (non-inverting) input terminal of the amplifier 408, and capacitors C1 and C2 are selectively coupled between the input voltage and a reference voltage and between the reference voltage and the positive input terminal using switches S1 and S2. The output of the amplifier 408 is coupled to a negative (inverting) input terminal of the amplifier 408.

[0039] In contrast, as shown in Figure 4B, the input voltage is coupled to the negative input terminal of amplifier 408, and capacitor C3 is selectively coupled between the input voltage and the negative input terminal, between the input voltage and ground, and between ground and the negative input terminal using switches S3, S4, S5, and S6. The output of amplifier 408 is selectively coupled to the negative input terminal through capacitor C4 using switches S7 and S8, and capacitor C4 is selectively coupled to ground using switches S9 and S10. Capacitor C5 is coupled in parallel with capacitor C4 between the output and the negative input terminal of amplifier 408. The positive input terminal is coupled to ground.

[0040] In each of the switched capacitor circuits 400 and 404, each capacitor is selectively coupled to an input voltage to sample the input voltage during a sampling period. In other words, the capacitor accumulates charge according to the input voltage during the sampling period. The charged capacitor is decoupled from the input voltage and selectively coupled to the amplifier 408 to pass the charge (i.e., a voltage corresponding to the sampled input voltage) to the amplifier 408. Over time (e.g., multiple sampling periods), the accumulated charge reaches a value corresponding to the input voltage average.

[0041] 5 and with continued reference to FIGS. 4A and 4B, sample-and-hold averaging of input voltage signals (e.g., V1(t)) 500 and 504 using a conventional switched capacitor circuit such as switched capacitor circuit 400 or 404 is shown. Typically, input voltage signals 500 and 504 require multiple sampling periods (e.g., 1 ns, 2 ns, etc.) to reach a stable value. For example, as shown, input voltage signals 500 and 504 reach a stable value (approaching 1.0 volts or 1.5 volts, respectively) over multiple periods. However, because the initial sampled input values ​​are relatively low (e.g., approximately 0 volts, 0.5 volts, 0.75 volts, etc.), the input voltage average is weighted toward the initial, lower sample. Thus, the switched capacitor circuit requires approximately 20 periods (i.e., delay or rise time) for each output voltage 508 and 512 to settle to a value corresponding to the input voltage average.

[0042] 6A and 6B, exemplary switched capacitor circuits 600 and 604 according to the present disclosure are shown. The switched capacitor circuits 600 and 604 function as sample-and-hold circuits providing an LPF function. The switched capacitor circuits 600 and 604 include a first capacitor C1 and at least one second capacitor C2 configured to be selectively coupled to a first input terminal (e.g., a positive or non-inverting input terminal) of an amplifier 608. For example, the amplifier 608 is an operational amplifier configured as a unity gain buffer. A second input terminal (e.g., a negative or inverting input terminal) of the amplifier 608 is coupled to an output of the amplifier 608. An ADC (e.g., ADC356) may be coupled to the output of the amplifier 608.

[0043] The first capacitor C1 is selectively coupled between the input voltage and ground and between ground and the positive input terminal using the switches S1 and S2. In other words, the first switch S1 is configured to selectively couple the first capacitor C1 to the input voltage Vin to charge the first capacitor C1, and the second switch S2 is configured to selectively couple the first capacitor C1 to the positive input terminal.

[0044] The second capacitor C2 is selectively coupled to the output (i.e., output voltage) of the amplifier 608 and / or the positive input terminal of the amplifier 608 using the switches S3 and S4. In other words, the third switch S3 is configured to selectively couple the second capacitor C2 to the positive input terminal, and the fourth switch S4 is configured to selectively couple the second capacitor C2 to the output of the amplifier 608. For example, the fourth switch S4 is configured to selectively couple the second capacitor C2 to the output of the amplifier 608 during a first sampling period, and the third switch S3 is configured to selectively couple the second capacitor C2 to the positive input terminal during a second sampling period. The second capacitor C2 is coupled to the output of the amplifier 608 to preset the charge of the second capacitor C2 according to the output of the amplifier 608. In this way, the rise time (the time required for the output of the amplifier 608 to reach the input voltage average) is reduced, as described in more detail below.

[0045] The switches S1-S4 are selectively opened and closed to preset the charge on the second capacitor C2 and to acquire the input voltage. For example, a sampling control module (e.g., controller) 612 is configured to control the timing of opening and closing of the switches S1-S4 using one or more control signals 616. With reference to FIG. 6A, during acquisition of a first sample of the input voltage (e.g., a first sampling period or time period), the switch S1 is closed and the switch S2 is opened to store the first sample on the first capacitor C1. Furthermore, the switch S3 is opened and the switch S4 is closed to couple the second capacitor C2 to the output of the amplifier 608. Then, the switch S1 is opened and the switch S2 is closed to provide the first sample to the positive input terminal of the amplifier 608. Upon completion of the acquisition of the first sample, the output of the amplifier 608 is equal to the input voltage of the first sample. Since the output of the amplifier 608 corresponds to the input voltage of the first sample stored by the first capacitor C1, the voltage of the first capacitor C1 is also buffered (i.e., stored) on the second capacitor C2 via the output of the amplifier 608.

[0046] Following taking a first sample of the input voltage, switch S3 is closed and switch S4 is opened to disconnect the second capacitor C2 from the output of amplifier 608 and couple the second capacitor C2 to the positive input terminal of amplifier 608. Thus, during taking a subsequent second sample of the input voltage, both the first capacitor C1 and the second capacitor C2 are coupled to the positive input terminal of amplifier 608, and the output of amplifier 608 corresponds to the average of the previous sample held by the second capacitor C2 and the current sample provided by the first capacitor C1.

[0047] In some examples, the capacitances of the first capacitor C1 and the second capacitor C2 may be approximately equal. Increasing the capacitance (e.g., size) of the second capacitor C2 relative to the first capacitor C1 can shift the cutoff frequency of the LPF function. However, increasing the capacitance of the second capacitor C2 in this manner can increase the amount of time required for the output of the amplifier 608 to reach the input voltage average. As shown in FIG. 6B, rather than increasing the capacitance of the second capacitor C2, the switched capacitor circuit 604 includes multiple capacitors (i.e., two or more capacitors including the second capacitor C2 and at least a third capacitor C3, a fourth capacitor C4, a fifth capacitor C5, etc.) configured to be coupled to the output of the amplifier 608 using multiple switches S3, S4, S5, S6, and S7.

[0048] Each of the capacitors C2-C5 may have a capacitance that is approximately equal to the first capacitor C1. When the capacitances are approximately equal, the output of the amplifier 608 corresponds to an equally weighted average of the input samples. In other examples, the capacitance of one or more of the capacitors C2-C5 may be different from the capacitance of the first capacitor C1 (e.g., at least the capacitances of the first capacitor C1 and the second capacitor C2 are different). In this manner, the samples may be given different weights.

[0049] In the example shown in FIG. 6B, the plurality of switches S3-S7 are configured to selectively couple a selected one of the capacitors C2-C5 (the plurality of second capacitors) to either the positive input terminal or the output of the amplifier 608, as described in more detail below. For example, during acquisition of a first sample of the input voltage (e.g., a first sampling period or time), switch S1 is closed and switch S2 is open to store the first sample in the first capacitor C1. Furthermore, switch S3 is opened and switches S4-S7 are closed to couple each of the capacitors C2-C5 to the output of the amplifier 608. Switch S1 is then opened and switch S2 is closed to provide the first sample to the positive input terminal of the amplifier 608. Upon completion of acquisition of the first sample, the output of the amplifier 608 is equal to the input voltage of the first sample. Since the output of the amplifier 608 corresponds to the input voltage of the first sample stored by the first capacitor C1, the voltage of the first capacitor C1 is also buffered (i.e., stored) in each of the capacitors C2-C5 via the output of the amplifier 608.

[0050] During acquisition of a second sample of the input voltage (e.g., a second sampling period or time), switch S1 is closed and switch S2 is open to store the second sample on the first capacitor C1. Additionally, switches S3 and S4 are opened and switches S5-S7 are closed to couple each of the capacitors C3-C5 to the output of the amplifier 608. Switch S1 is then opened and switch S2 is closed to provide the second sample to the positive input terminal of the amplifier 608. Additionally, switch S3 is closed to couple the second capacitor C2 to the positive input terminal of the amplifier 608, switch S4 remains open, and switches S5-S7 remain closed.

[0051] Thus, during acquisition of a second sample of the input voltage, both the first capacitor C1 and the second capacitor C2 are coupled to the positive input terminal of amplifier 608, and the output at the positive input terminal of amplifier 608 corresponds to the average of the first sample stored on the second capacitor C2 and the second sample provided by the first capacitor C1. In other words, the output of amplifier 608 corresponds to the average of the charges on each of the first capacitor C1 and the second capacitor C2. Switches S5-S7 are closed and capacitors C3-C5 are coupled to the output of amplifier 608, such that the average of the first and second samples is stored on capacitors C3-C5, respectively.

[0052] During subsequent (e.g., third, fourth, and fifth) sampling periods, the switches that are open during acquisition of the samples move from switch S4 to switch S5, from switch S5 to switch S6, and from switch S6 to switch S7, respectively. For example, the third switch S3 and the fourth switch S4 are configured to selectively couple the third capacitor C3 to the positive input terminal, while the fifth switch S5 is configured to selectively couple the third capacitor C3 to the output of the amplifier 608. In other words, during acquisition of the third sample, the first capacitor C1, the second capacitor C2, and the third capacitor C3 are coupled to the positive input terminal of the amplifier 608, and the output of the amplifier 608 corresponds to the average of the first sample stored in the second capacitor C2, the second sample stored in the third capacitor C3, and the third sample provided by the first capacitor C1.

[0053] Similarly, the third switch S3, the fourth switch S4, and the fifth switch S5 are configured to selectively couple the fourth capacitor C4 to the positive input terminal, while the sixth switch S6 is configured to selectively couple the fourth capacitor C4 to the output of the amplifier 608. Thus, during acquisition of a fourth sample, the first capacitor C1, the second capacitor C2, the third capacitor C3, and the fourth capacitor C4 are coupled to the positive input terminal of the amplifier 608, and the output of the amplifier 608 corresponds to the average of the first sample stored in the second capacitor C2, the second sample stored in the third capacitor C3, the third sample stored in the fourth capacitor C4, and the fourth sample provided by the first capacitor C1.

[0054] The third switch S3, the fourth switch S4, the fifth switch S5, and the sixth switch S6 are configured to selectively couple the fifth capacitor C5 to the positive input terminal, while the seventh switch S7 is configured to selectively couple the fifth capacitor C5 to the output of the amplifier 608. Thus, during acquisition of the fifth sample, the first capacitor C1, the second capacitor C2, the third capacitor C3, the fourth capacitor C4, and the fifth capacitor C5 are coupled to the positive input terminal of the amplifier 608, and the output of the amplifier 608 corresponds to the average of the first sample stored in the second capacitor C2, the second sample stored in the third capacitor C3, the third sample stored in the fourth capacitor C4, the fourth sample stored in the fifth capacitor C5, and the fifth sample provided by the first capacitor C1. In this way, each of the first five samples is weighted equally, and the amount of time required for the output of the amplifier 608 to reach the input voltage average (i.e., the rise time) is significantly reduced.

[0055] In one example, as described above, the third switch S3, the fourth switch S4, the fifth switch S5, the sixth switch S6, and the seventh switch S7 are configured to couple the second capacitor C2, the third capacitor C3, the fourth capacitor C4, and the fifth capacitor C5 to the output of the amplifier 608 during a first sampling period; configured to couple the second capacitor C2 to the positive input terminal and couple the third capacitor C3, the fourth capacitor C4, and the fifth capacitor C5 to the output of the amplifier 608 during a second sampling period; configured to couple the second capacitor C2 and the third capacitor C3 to the positive input terminal and couple the fourth capacitor C4 and the fifth capacitor C5 to the output of the amplifier 608 during a third sampling period; configured to couple the second capacitor C2, the third capacitor C3, and the fourth capacitor C4 to the positive input terminal and couple the fifth capacitor C5 to the output of the amplifier 608 during a fourth sampling period; and configured to couple the second capacitor C2, the third capacitor C3, the fourth capacitor C4, and the fifth capacitor C5 to the positive input terminal during a fifth sampling period.

[0056] The foregoing description is merely exemplary in nature and is not intended to limit the disclosure, its application, or uses. The broad teachings of the disclosure can be embodied in various forms. Thus, while the disclosure includes specific examples, the true scope of the disclosure should not be so limited, since other variations will become apparent upon study of the drawings, specification, and claims. It should be understood that one or more steps in a method can be performed in different orders (or simultaneously) without altering the principles of the disclosure. Furthermore, although each embodiment is described above as having specific features, any one or more of these features described with respect to any embodiment of the disclosure may be implemented in any feature of any other embodiment and / or combined with the features of other embodiments (even if such combination is not explicitly described). In other words, the described embodiments are not mutually exclusive, and substitution of one or more embodiments for one another is also included within the scope of the disclosure.

[0057] Between elements (e.g. modules , semiconductor layerThe spatial and functional relationships between , "engaged" The terminology is described using various terms such as "coupled," "adjacent," "next to," "on top of," "above," "below," and "disposed." Unless expressly described as "direct," when a relationship between a first element and a second element is described in the above disclosure, the relationship can be a direct relationship where there are no other intervening elements between the first element and the second element, but can also be an indirect relationship where there are one or more intervening elements (spatial or functional) between the first element and the second element. As used herein, the phrase "at least one of A, B, and C" should be interpreted as meaning a logic using a non-exclusive OR (A OR B OR C), and not as meaning "at least one of A, at least one of B, and at least one of C."

[0058] In a diagram, the direction of the arrow, as indicated by the arrow head, generally indicates the flow of information (such as data or instructions) that is important to the diagram. For example, an arrow may point from element A to element B if element A and element B exchange various information, but the information sent from element A to element B is relevant to the diagram. This unidirectional arrow does not imply that other information is not sent from element B to element A. Additionally, for information sent from element A to element B, element B may send a request for the information or an acknowledgment of receipt to element A.

[0059] In this application, the term "circuitry" may be substituted for the terms "module" and "controller," including the definitions below. The term "module" may refer to, be a part of, or include an application specific integrated circuit (ASIC), digital, analog, or combined analog / digital discrete circuitry, digital, analog, or combined analog / digital integrated circuit, combinatorial logic circuitry, field programmable gate array (FPGA), processor circuitry (shared, dedicated, or group) that executes code, memory circuitry (shared, dedicated, or group) that stores code executed by the processor circuitry, other suitable hardware components that provide the described functionality, or a combination of some or all of the above, such as in a system-on-chip.

[0060] A module may include one or more interface circuits. In some examples, the interface circuits may include a wired or wireless interface that connects to a local area network (LAN), the Internet, a wide area network (WAN), or a combination thereof. The functionality of any given module of the present disclosure may be distributed among multiple modules that are connected via interface circuits. For example, multiple modules may enable load balancing. In a further example, a server (also known as remote or cloud) module may perform some functions on behalf of a client module.

[0061] The term code as used above includes software, firmware, and / or microcode, and may refer to programs, routines, functions, classes, data structures, and / or objects. The term shared processor circuit includes a single processor circuit that executes some or all code from multiple modules. The term group processor circuit includes a processor circuit that executes some or all code from one or more modules in combination with additional processor circuits. References to multiprocessor circuits include multiple processor circuits on separate dies, multiple processor circuits on a single die, multiple cores of a single processor circuit, multiple threads of a single processor circuit, or combinations of the above. The term shared memory circuit includes a single memory circuit that stores some or all code from multiple modules. The term group memory circuit includes a memory circuit that stores some or all code from one or more modules in combination with additional memory.

[0062] The term memory circuit is a subset of the term computer-readable medium. The term computer-readable medium as used herein does not encompass transitory electrical or electromagnetic signals propagating in a medium (such as a carrier wave). Thus, the term computer-readable medium may be considered to be tangible and non-transitory. Non-limiting examples of non-transitory tangible computer-readable media include non-volatile memory circuits (such as flash memory circuits, erasable programmable read-only memory circuits, or masked read-only memory circuits), volatile memory circuits (such as static random access memory circuits or dynamic random access memory circuits), magnetic storage media (such as analog or digital magnetic tape or hard disk drives), and optical storage media (such as CDs, DVDs, Blu-ray disks).

[0063] The apparatus and methods described herein may be implemented in part or in full by a special-purpose computer created by configuring a general-purpose computer to execute one or more specific functions embodied in a computer program. The functional blocks, flow chart components, and other elements described above function as software specifications and may be converted into a computer program by the routine work of a skilled technician or programmer.

[0064] A computer program includes processor-executable instructions stored on at least one non-transitory, tangible, computer-readable medium. A computer program may include or depend on stored data. A computer program may include a basic input / output system (BIOS) that interacts with the hardware of a special-purpose computer, device drivers that interact with specific devices of a special-purpose computer, one or more operating systems, user applications, background services, background applications, etc.

[0065] A computer program may include (i) explanatory text to be parsed, such as HTML (hypertext markup language), XML (extensible markup language), or JSON (JavaScript Object Notation); (ii) assembly code; (iii) object code generated from source code by a compiler; (iv) source code for execution by an interpreter; (v) source code for compilation and execution by a just-in-time compiler; etc. By way of example only, the source code may be written using syntax from languages ​​such as C, C++, C#, Objective-C, Swift, Haskell, Go, SQL, R, Lisp, Java, Fortran, Perl, Pascal, Curl, OCaml, Javascript, HTML5 (hypertext markup language 5th revision), Ada, ASP (Active Server Pages), PHP (PHP: hypertext Preprocessor), Scala, Eiffel, Smalltalk, Erlang, Ruby, Flash, Visual Basis, Lua, MATLAB, SIMULINK, and Python. [Explanation of symbols]

[0066] 100 Electronic Devices 104 Sensor Module 108 Reference Signal Generator 110 Control Signal 112 Offset Control Module 116 Optional Second Reference Signal Generator 118 Detection Signal 120 Offset Signal 124 Regulator circuit 128 output signals 200 Digital Sine Wave Generator 204 Analog DAC 208 LPF 212 Multiplier 216 LPF 300 Capacitive Sensor System 304 Sensor Module 312 Reference Signal Generator 316 Control Signals 318 Regulator circuit 320 Offset Control Module 324 Offset Signal 332 fingers 336 capacity 340 Detection Signal 344 Output Signal 308 Sample and Hold Circuit 352 Output voltage 356 ADC 400 Switched Capacitor Circuits 408 Amplifier 500 Input voltage signal 504 Input voltage signal 508 Output voltage 512 Output voltage 600 Switched Capacitor Circuits 604 Switched Capacitor Circuit 608 Amplifier 612 Sampling Control Module 616 Control Signals

Claims

1. 1. A switched capacitor circuit for a capacitive sensor system, comprising: an amplifier having a first input terminal, a second input terminal, and an output, the output being connected to the second input terminal, the first input terminal being a non-inverting input terminal, and the second input terminal being an inverting input terminal; A first capacitor; a first switch configured to selectively connect one end of the first capacitor to an input voltage so as to charge the first capacitor, the other end of which is grounded; a second switch configured to selectively connect the other end of the first capacitor to the first input terminal; A second capacitor; a third switch configured to selectively connect one end of the second capacitor, the other end of which is grounded, to the first input terminal; a fourth switch configured to selectively connect the other end of the second capacitor to the output of the amplifier; and having A switched-capacitor circuit, wherein the amplifier is an operational amplifier configured as a unity gain buffer with its output connected to its inverting input.

2. The first capacitor and the second capacitor have the same capacitance.

2. The switched capacitor circuit of claim 1.

3. The capacitances of the first capacitor and the second capacitor are different.

2. The switched capacitor circuit of claim 1.

4. the output of the amplifier corresponds to an average of the charges on each of the first and second capacitors.

2. The switched capacitor circuit of claim 1.

5. the fourth switch is configured to connect the other end of the second capacitor to the output of the amplifier during a first sampling period; the third switch is configured to connect the other end of the second capacitor to the first input terminal during a second sampling period; 2. The switched capacitor circuit of claim 1.

6. A third capacitor, one end of which is grounded; The fifth switch and the third switch and the fourth switch are configured to selectively connect the other end of the third capacitor to the first input terminal; the fifth switch is configured to selectively connect the other end of the third capacitor to the output of the amplifier.

2. The switched capacitor circuit of claim 1.

7. A fourth capacitor having one end grounded; The sixth switch and the third switch, the fourth switch, and the fifth switch are configured to selectively connect the other end of the fourth capacitor to the first input terminal; the sixth switch is configured to selectively connect the other end of the fourth capacitor to the output of the amplifier.

7. The switched capacitor circuit of claim 6.

8. A fifth capacitor, one end of which is grounded; The seventh switch and the third switch, the fourth switch, the fifth switch, and the sixth switch are configured to selectively connect the other end of the fifth capacitor to the first input terminal; the seventh switch is configured to selectively connect the other end of the fifth capacitor to the output of the amplifier.

8. The switched capacitor circuit of claim 7.

9. The third switch, the fourth switch, the fifth switch, the sixth switch, and the seventh switch are connecting the other ends of the second capacitor, the third capacitor, the fourth capacitor, and the fifth capacitor to the output of the amplifier during a first sampling period; during a second sampling period, connecting the other end of the second capacitor to the first input terminal and connecting the other ends of the third capacitor, the fourth capacitor, and the fifth capacitor to the output of the amplifier; during a third sampling period, connecting the other ends of the second capacitor and the third capacitor to the first input terminal and connecting the other ends of the fourth capacitor and the fifth capacitor to the output of the amplifier; during a fourth sampling period, connecting the other ends of the second capacitor, the third capacitor, and the fourth capacitor to the first input terminal and connecting the other end of the fifth capacitor to the output of the amplifier; During a fifth sampling period, the other ends of the second capacitor, the third capacitor, the fourth capacitor, and the fifth capacitor are connected to the first input terminal. It is configured as follows:

9. The switched capacitor circuit of claim 8.

10. a sampling control module configured to control timing of opening and closing of the first switch, the second switch, the third switch, and the fourth switch.

2. The switched capacitor circuit of claim 1.

11. 10. A capacitive sensing system comprising the switched capacitor circuit of claim 1, further comprising an analog-to-digital converter coupled to the output of the amplifier.

12. a sensor module configured to generate a detection signal indicative of at least one of contact with and proximity to an object; the input voltage corresponds to the sense signal; The capacitive sensing system of claim 11.

13. 1. A switched capacitor circuit for a capacitive sensor system, comprising: an amplifier configured as a unity gain buffer having a first input terminal, a second input terminal, and an output connected to the second input terminal; A first capacitor; a first switch configured to selectively connect one end of the first capacitor to an input voltage so as to charge the first capacitor, the other end of which is grounded; a second switch configured to selectively connect the other end of the first capacitor to the first input terminal; A plurality of second capacitors; a plurality of switches configured to selectively connect one end of a second capacitor selected from the plurality of second capacitors, the other end of which is grounded, to either the first input terminal or the output of the amplifier; A switched capacitor circuit having

14. the first input terminal is a non-inverting input terminal, and the second input terminal is an inverting input terminal; 14. The switched capacitor circuit of claim 13.

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