Power Amplifiers

Abstract

To stabilize phase and gain.SOLUTION: A power amplifier includes: a first amplifier, and a second amplifier electrically connected to the subsequent stage of the first amplifier; a third amplifier, and a fourth amplifier electrically connected to the subsequent stage of the third amplifier; a phase shifter for making different the phase of a high frequency signal flowing through a first path and the phase of a high frequency signal flowing through a second path; and a first bias circuit for supplying bias to the first amplifier and the third amplifier; a second bias circuit for supplying bias to the first amplifier and the second amplifier; and a third bias circuit for supplying bias to the third amplifier and the fourth amplifier. The second amplifier includes a second transistor, the fourth amplifier includes a fourth transistor, the second bias circuit includes a sixth transistor, and the third bias circuit includes a seventh transistor. The second transistor and the sixth transistor are connected in current mirror connection, and the fourth transistor and the seventh transistor are connected in current mirror connection.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present disclosure relates to power amplifiers. [Background technology]

[0002] The following Patent Document 1 discloses an amplifier that adjusts the phase and gain of a high-frequency output signal by inputting a high-frequency input signal to multiple amplification paths, making the phase of the high-frequency signal different in each amplification path, adjusting the gain of each amplification path, and vectorially combining the amplified signals. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] US Patent Application Publication No. 2022 / 0190790 Summary of the Invention [Problem to be solved by the invention]

[0004] However, the amplifier described in Patent Document 1 adjusts the gain of each amplification path only by the collector bias of the first-stage amplifier in each amplification path. Therefore, the amplifier described in Patent Document 1 has a problem in that the phase and gain of each amplification path as a whole are not stable because the phase of the high-frequency signal output from the first-stage amplifier changes depending on the collector bias.

[0005] The present disclosure has been made in consideration of the above, and has an object to stabilize the phase and gain. [Means for solving the problem]

[0006] A power amplifier according to one aspect of the present disclosure includes an input terminal to which a high frequency input signal is input, an output terminal to which a high frequency output signal is output, a first path and a second path electrically connected between the input terminal and the output terminal and connected in parallel with each other, a first amplifier included in the first path and a second amplifier electrically connected in a stage subsequent to the first amplifier, a third amplifier included in the second path and a fourth amplifier electrically connected in a stage subsequent to the third amplifier, and a phase difference between a high frequency signal flowing in the first path and a high frequency signal flowing in the second path. Transfer The phase shifter includes a first bias circuit electrically connected to the first amplifier and the third amplifier and supplying a bias to the first amplifier and the third amplifier, a second bias circuit electrically connected to the first amplifier and the second amplifier and supplying a bias to the first amplifier and the second amplifier, and a third bias circuit electrically connected to the third amplifier and the fourth amplifier and supplying a bias to the third amplifier and the fourth amplifier. The first amplifier includes a first transistor, the second amplifier includes a second transistor, the third amplifier includes a third transistor, the fourth amplifier includes a fourth transistor, the first bias circuit includes a fifth transistor, the second bias circuit includes a sixth transistor, and the third bias circuit includes a seventh transistor. The second transistor and the sixth transistor are current mirror connected, and the fourth transistor and the seventh transistor are current mirror connected. Effect of the Invention

[0007] According to the present disclosure, it is possible to stabilize the phase and gain. [Brief description of the drawings]

[0008] [Figure 1] FIG. 1 is a diagram illustrating a configuration of a power amplifier according to a first embodiment. [Diagram 2] FIG. 2 is a diagram showing configurations of a first amplifier, a second amplifier, a first bias circuit, and a second bias circuit of the power amplifier according to the first embodiment. [Diagram 3] FIG. 3 is a diagram illustrating a result of a circuit simulation of the power amplifier according to the first embodiment. [Figure 4] FIG. 4 is a diagram showing a result of a circuit simulation of the power amplifier according to the first embodiment. [Diagram 5] FIG. 5 is a diagram illustrating a configuration of a power amplifier according to the second embodiment. [Figure 6] FIG. 6 is a diagram showing configurations of a first amplifier, a second amplifier, a first bias circuit, and a second bias circuit of a power amplifier according to the second embodiment. [Figure 7] FIG. 7 is a diagram illustrating a configuration of a power amplifier according to the third embodiment. [Figure 8] FIG. 8 is a diagram showing configurations of a first amplifier, a second amplifier, a first bias circuit, and a second bias circuit of a power amplifier according to the third embodiment. [Figure 9] FIG. 9 is a diagram illustrating a configuration of a power amplifier according to the fourth embodiment. [Figure 10] FIG. 10 is a diagram showing configurations of a first amplifier, a second amplifier, a first bias circuit, and a second bias circuit of a power amplifier according to the fourth embodiment. [Figure 11] FIG. 11 is a diagram illustrating a configuration of a power amplifier according to the fifth embodiment. [Figure 12] FIG. 12 is a diagram illustrating a configuration of a power amplifier according to the sixth embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. Note that the present disclosure is not limited to these embodiments. It goes without saying that each embodiment is an example, and partial replacement or combination of the configurations shown in different embodiments is possible.

[0010] <First embodiment> 1 is a diagram showing the configuration of a power amplifier according to a first embodiment. The power amplifier 1 amplifies a radio frequency input signal RFin input to an input terminal 1a, and outputs a radio frequency output signal RFout from an output terminal 1b. A power supply voltage Vbatt is input to a terminal 1c of the power amplifier 1.

[0011] The power amplifier 1 includes a first path 11, a second path 12, a first bias circuit 13, a second bias circuit 14, and a third bias circuit 15.

[0012] The first path 11 and the second path 12 are connected in parallel to each other. The first path 11 and the second path 12 are electrically connected between the input terminal 1a and the output terminal 1b.

[0013] The first path 11 includes a first amplifier 21 and a first Transfer The phase shifter 22 and the second amplifier 23.

[0014] The first amplifier 21 has an input terminal 1a and a first Transfer The first amplifier 21 amplifies the high-frequency input signal RFin input to the input terminal 1a, and outputs the amplified high-frequency signal RF1 as a first Transfer The output is sent to the phase shifter 22.

[0015] No. 1 Transfer The phase shifter 22 is electrically connected between the first amplifier 21 and the second amplifier 23. Transfer The phase shifter 22 shifts the high frequency signal RF1 by a first phase ψ and outputs the shifted high frequency signal RF2 to the second amplifier 23. Transfer The phase shifter 22 may have an impedance matching function between the first amplifier 21 and the second amplifier 23 .

[0016] The second amplifier 23 is Transfer The second amplifier 23 is electrically connected between the phase shifter 22 and the output terminal 1b. The second amplifier 23 amplifies the high frequency signal RF2 and outputs the amplified high frequency signal RF3 to the output terminal 1b.

[0017] The second path 12 includes a third amplifier 31 and a second Transfer The phase shifter 32 and the fourth amplifier 33 .

[0018] The third amplifier 31 is connected to the input terminal 1a and the second TransferThe third amplifier 31 amplifies the high frequency input signal RFin input to the input terminal 1a, and outputs the amplified high frequency signal RF4 to the second amplifier 32. Transfer The output is sent to the phase shifter 32.

[0019] Second Transfer The phase shifter 32 is electrically connected between the third amplifier 31 and the fourth amplifier 33. Transfer The phase shifter 32 shifts the high frequency signal RF4 by a second phase φ different from the first phase ψ, and outputs the shifted high frequency signal RF5 to the fourth amplifier 33. Transfer The phase shifter 32 may have an impedance matching function between the third amplifier 31 and the fourth amplifier 33 .

[0020] The fourth amplifier 33 is Transfer The fourth amplifier 33 is electrically connected between the phase shifter 32 and the output terminal 1b. The fourth amplifier 33 amplifies the high frequency signal RF5 and outputs the amplified high frequency signal RF6 to the output terminal 1b.

[0021] The radio frequency signals RF3 and RF6 are vectorially added to each other to become the radio frequency output signal RFout. The radio frequency output signal RFout is output from the output terminal 1b. The second amplifier 23 and the fourth amplifier 33 are supplied with a power supply voltage Vbatt via a resistor Rc2.

[0022] In the first embodiment, Transfer Phase 22 and 2 Transfer The pair with the phaser 32 is the " Transfer This corresponds to an example of a "phase converter."

[0023] The first bias circuit 13 is electrically connected to the first amplifier 21 and the third amplifier 31. The first bias circuit 13 supplies a bias to the first amplifier 21 and the third amplifier 31 based on a control current Ctrl1.

[0024] The second bias circuit 14 is electrically connected to the first amplifier 21 via a resistor Rc11. The second bias circuit 14 is also electrically connected to the second amplifier 23. The second bias circuit 14 supplies a bias to the first amplifier 21 and the second amplifier 23 based on a control current Ctrl21.

[0025] The third bias circuit 15 is electrically connected to the third amplifier 31 via a resistor Rc12. The third bias circuit 15 is also electrically connected to the fourth amplifier 33. The third bias circuit 15 supplies a bias to the third amplifier 31 and the fourth amplifier 33 based on a control current Ctrl22.

[0026] FIG. 2 is a diagram showing configurations of a first amplifier, a second amplifier, a first bias circuit, and a second bias circuit of the power amplifier according to the first embodiment.

[0027] The configurations of the third amplifier 31, the fourth amplifier 33, and the third bias circuit 15 are similar to the configurations of the first amplifier 21, the second amplifier 23, and the second bias circuit 14, and therefore illustration and description thereof will be omitted.

[0028] The first amplifier 21 includes a transistor BJT11, a resistor Rb1, and a capacitor Cb1.

[0029] The transistor BJT11 corresponds to an example of the "first transistor" in the present disclosure. The transistor BJT11 of the third amplifier 31 (not shown) (having the same configuration as the first amplifier 21 in FIG. 2) corresponds to an example of the "third transistor" in the present disclosure.

[0030] In the present disclosure, each transistor is a bipolar transistor, but the present disclosure is not limited thereto. An example of a bipolar transistor is a heterojunction bipolar transistor (HBT), but the present disclosure is not limited thereto. The transistor may be, for example, a field effect transistor (FET). The transistor may be a multi-finger transistor in which a plurality of unit transistors are electrically connected in parallel. A unit transistor refers to the minimum configuration that constitutes a transistor.

[0031] The high frequency input signal RFin is input to one end of the capacitor Cb1. The capacitor Cb1 is a DC blocking capacitor that blocks the DC component of the high frequency input signal RFin. The other end of the capacitor Cb1 is electrically connected to the base of the transistor BJT11.

[0032] The emitter of the transistor BJT11 is electrically connected to a reference potential. The reference potential is exemplified by a ground potential, but the present disclosure is not limited thereto. The collector of the transistor BJT11 is electrically connected to one end of a resistor Rc11. The base of the transistor BJT11 is electrically connected to one end of a resistor Rb1.

[0033] The first bias circuit 13 includes a transistor BJT12 and a capacitor Cdc1.

[0034] The transistor BJT12 corresponds to an example of a "fifth transistor" of the present disclosure.

[0035] The emitter of the transistor BJT12 is electrically connected to a reference potential. The collector and base of the transistor BJT12 are electrically connected. That is, the transistor BJT12 is diode-connected. A control current Ctrl1 is input to the collector and base of the transistor BJT12. The transistor BJT12 generates a voltage according to the control current Ctrl1.

[0036] One end of the capacitor Cdc1 is electrically connected to the collector and base of the transistor BJT12. The other end of the capacitor Cdc1 is electrically connected to a reference potential. The capacitor Cdc1 AC grounds the collector and base of the transistor BJT12. This suppresses the output impedance (collector and base impedance) of the transistor BJT12, improving the output of the transistor BJT12.

[0037] The collector and base of the transistor BJT12 and one end of the capacitor Cdc1 are electrically connected to the other end of the resistor Rb1. That is, the transistors BJT12 and BJT11 are current-mirror connected via the resistor Rb1. As a result, a collector current corresponding to the control current Ctrl1 flows through the transistor BJT11.

[0038] The collector and base of the transistor BJT12 and one end of the capacitor Cdc1 are also electrically connected to the other end of the resistor Rb1 of a third amplifier 31 (not shown) (having the same configuration as the first amplifier 21 in FIG. 2).

[0039] The transistors BJT12 and BJT11 are connected in a current mirror configuration, which provides the following effects.

[0040] The transistor BJT11, which is a bipolar transistor, may change in temperature due to self-heating, and therefore its characteristics (for example, the base voltage threshold) may change. Therefore, if a fixed voltage is input to the base of the transistor BJT11, the characteristics of the transistor BJT11 will change even if the base voltage is fixed, and the collector current of the transistor BJT11 will change.

[0041] On the other hand, in the first embodiment, the transistors BJT11 and BJT12 are expected to have approximately the same temperature when they self-heat. In other words, the transistors BJT11 and BJT12 are expected to have approximately the same characteristics even when they self-heat.

[0042] A control current Ctrl1 flows from the collector and base of transistor BJT12 to the emitter, and a voltage corresponding to the control current Ctrl1 is generated at the collector and base of transistor BJT12. The collector and base voltages of transistor BJT12 change in response to temperature changes (characteristic changes). The collector and base voltages of transistor BJT12 are input to the base of transistor BJT11. Therefore, a current corresponding to the control current Ctrl1 flows through the collector of transistor BJT11 even if the temperature changes.

[0043] This suppresses changes in the gain of the transistor BJT11, making the gain stable.

[0044] The second amplifier 23 includes a transistor BJT21, a resistor Rb2, and a capacitor Cb2.

[0045] The transistor BJT21 corresponds to an example of a "second transistor" in the present disclosure. The transistor BJT21 of a fourth amplifier 33 (not shown) (having a configuration similar to that of the second amplifier 23 in FIG. 2) corresponds to an example of a "fourth transistor" in the present disclosure.

[0046] The high frequency signal RF2 is input to one end of the capacitor Cb2. The capacitor Cb2 is a DC blocking capacitor that blocks the DC component of the high frequency signal RF2. The other end of the capacitor Cb2 is electrically connected to the base of the transistor BJT21.

[0047] The emitter of the transistor BJT21 is electrically connected to a reference potential. The collector of the transistor BJT21 is electrically connected to one end of a resistor Rc2. The other end of the resistor Rc2 is supplied with a power supply voltage Vbatt. The collector of the transistor BJT21 is supplied with the power supply voltage Vbatt via the resistor Rc2. The base of the transistor BJT21 is electrically connected to one end of a resistor Rb2.

[0048] The second bias circuit 14 includes a transistor BJT13, a transistor BJT22, a capacitor Cdc2, a capacitor Cdc3, a capacitor Cfb, and a resistor Rc3.

[0049] The transistor BJT22 corresponds to an example of a "sixth transistor" in the present disclosure. The transistor BJT13 corresponds to an example of an "eighth transistor" in the present disclosure. The transistor BJT22 of a third bias circuit 15 (not shown) (having a configuration similar to that of the second bias circuit 14 in FIG. 2) corresponds to an example of a "seventh transistor" in the present disclosure. The transistor BJT13 of the third bias circuit 15 corresponds to an example of a "ninth transistor" in the present disclosure.

[0050] The emitter of the transistor BJT22 is electrically connected to a reference potential. The collector and emitter of the transistor BJT22 are electrically connected via a capacitor Cfb. That is, the transistor BJT22 is diode-connected. A control current Ctrl21 is input to the collector of the transistor BJT22. The collector and base of the transistor BJT22 generate a voltage according to the control current Ctrl21.

[0051] One end of the capacitor Cdc2 is electrically connected to the base of the transistor BJT22. The other end of the capacitor Cdc2 is electrically connected to the reference potential. In other words, the capacitor Cdc2 AC grounds the collector and base of the transistor BJT22. This suppresses the output impedance (collector and base impedance) of the transistor BJT22, improving the output of the transistor BJT22.

[0052] The base of the transistor BJT22 and one end of the capacitor Cdc2 are electrically connected to the other end of the resistor Rb2. That is, the transistor BJT22 and the transistor BJT21 are current-mirror connected via the resistor Rb2. As a result, a collector current corresponding to the control current Ctrl21 flows through the transistor BJT21.

[0053] The transistors BJT22 and BJT21 are connected in a current mirror configuration, which provides the following effects.

[0054] The temperature of the transistor BJT21, which is a bipolar transistor, can change due to self-heating, and therefore the characteristics (for example, the base voltage threshold) can change. Therefore, if a fixed voltage is input to the base of the transistor BJT21, the characteristics of the transistor BJT21 change even if the base voltage is fixed, and the collector current of the transistor BJT21 changes.

[0055] On the other hand, in the first embodiment, the transistors BJT21 and BJT22 are expected to have approximately the same temperature when they self-heat. In other words, the transistors BJT21 and BJT22 are expected to have approximately the same characteristics even when they self-heat.

[0056] A control current Ctrl21 flows from the collector to the emitter of the transistor BJT22, and a voltage corresponding to the control current Ctrl21 is generated in the collector and base of the transistor BJT22. The collector and base voltages of the transistor BJT22 change in response to temperature changes (characteristic changes). The collector and base voltages of the transistor BJT22 are input to the base of the transistor BJT21. Therefore, a current corresponding to the control current Ctrl21 flows in the collector of the transistor BJT21 even if the temperature changes.

[0057] This suppresses changes in the gain of the transistor BJT21, making the gain stable.

[0058] A power supply voltage Vbatt is input to the collector of the transistor BJT 13. A base of the transistor BJT 13 is electrically connected to the collector of the transistor BJT 22. A voltage equivalent to the voltage drop of the transistor BJT 22 is input to the base of the transistor BJT 13.

[0059] The emitter of the transistor BJT13 is electrically connected to the other end of the resistor Rc11. That is, the transistor BJT13 and the resistor Rc11 are connected in an emitter-follower configuration. The transistor BJT13 outputs a bias according to the control current Ctrl21 to the collector of the transistor BJT11.

[0060] One end of the capacitor Cdc3 is electrically connected to the base of the transistor BJT13. The other end of the capacitor Cdc3 is electrically connected to the reference potential. In other words, the capacitor Cdc3 AC-grounds the base of the transistor BJT13. This suppresses the output impedance (emitter impedance) of the transistor BJT13, improving the output of the transistor BJT13.

[0061] One end of the resistor Rc3 is electrically connected to the emitter of the transistor BJT13. That is, the transistor BJT13 and the resistor Rc3 are connected in an emitter-follower configuration. The other end of the resistor Rc3 is electrically connected to the base of the transistor BJT22.

[0062] This forms a feedback loop 100 extending from the base of the transistor BJT13 to the emitter of the transistor BJT13 to the resistor Rc3 to the capacitor Cfb to the base of the transistor BJT13.

[0063] Negative feedback is applied to the transistor BJT13 by the feedback loop 100. Therefore, when the temperature of the transistor BJT13 changes due to self-heating and the characteristics (for example, the base voltage threshold) change, the base bias changes in a direction that cancels the change in the characteristics. This allows the transistor BJT13 to keep the bias applied to the collector of the transistor BJT11 constant even if the temperature changes due to self-heating and the characteristics change.

[0064] This suppresses changes in the gain of the transistor BJT11, making the gain stable.

[0065] The capacitor Cfb limits the band of the feedback loop 100. As a result, the capacitor Cfb can suppress the amplification of noise in the feedback loop 100. The capacitor Cfb can also suppress the oscillation of high-frequency signals in the feedback loop 100.

[0066] (Circuit simulation results) 3 and 4 are diagrams showing the results of a circuit simulation of the power amplifier according to the first embodiment.

[0067] Fig. 3 is a diagram showing the gain (dB) of the first path 11 when the control current Ctrl21 and the power supply voltage Vbatt are changed. In Fig. 3, the horizontal axis represents the control current Ctrl21, and the vertical axis represents the power supply voltage Vbatt. The numerical values ​​on each line in Fig. 3 represent the gain (dB) of the first path 11.

[0068] Fig. 4 is a diagram showing the phase (deg) of the radio frequency signal RF3 when the control current Ctrl21 and the power supply voltage Vbatt are changed. In Fig. 4, the horizontal axis represents the control current Ctrl21, and the vertical axis represents the power supply voltage Vbatt. The numbers on each line in Fig. 4 represent the phase (deg) of the radio frequency signal RF3.

[0069] For example, if the first path 11 is operated in the region 110 in FIGS. 3 and 4, it is possible to change only the gain (see FIG. 3) with almost no change in the phase (see FIG. 4).

[0070] In this way, the first path 11 can operate as a phase-invariant variable gain amplifier.

[0071] (effect) The second bias circuit 14 can control the collector bias of the transistor BJT11 and the base bias of the transistor BJT21 based on one control current Ctrl21. The second bias circuit 14 can also cancel the characteristic changes due to temperature changes of the transistors BJT11 and BJT21. The third bias circuit 15 is similar to the second bias circuit 14.

[0072] This allows the power amplifier 1 to suppress fluctuations in gain and stabilize it.

[0073] Since the transistors BJT22 and BJT21 are connected in a current mirror configuration, the second bias circuit 14 can provide a bias to the base of the transistor BJT21 according to the control current Ctrl21 even if the transistor BJT21 generates heat by itself.

[0074] This allows the power amplifier 1 to suppress fluctuations in gain and stabilize it.

[0075] Since the transistors BJT12 and BJT11 are connected in a current mirror configuration, the first bias circuit 13 can provide a bias corresponding to the control current Ctrl1 to the base of the transistor BJT11 even if the transistor BJT11 generates heat by itself.

[0076] This allows the power amplifier 1 to suppress fluctuations in gain and stabilize it.

[0077] Since the feedback loop 100 is configured, the second bias circuit 14 can keep the bias applied to the collector of the transistor BJT11 constant even if the transistor BJT13 generates heat by itself.

[0078] This allows the power amplifier 1 to suppress fluctuations in gain and stabilize it.

[0079] <Second embodiment> Among the components of the second embodiment, the same components as those of the first embodiment are denoted by the same reference numerals and the description thereof will be omitted.

[0080] FIG. 5 is a diagram illustrating a configuration of a power amplifier according to the second embodiment.

[0081] Compared to power amplifier 1 (see FIG. 1) of the first embodiment, power amplifier 2 of the second embodiment includes, instead of second bias circuit 14 and third bias circuit 15, a second bias circuit 14A and a third bias circuit 15A.

[0082] FIG. 6 is a diagram showing configurations of a first amplifier, a second amplifier, a first bias circuit, and a second bias circuit of a power amplifier according to the second embodiment.

[0083] The configuration of the third bias circuit 15A is similar to that of the second bias circuit 14A, and therefore, illustration and description thereof will be omitted.

[0084] Compared to the second bias circuit 14 (see FIG. 2), the second bias circuit 14A further includes a transistor BJT 23. Also, compared to the second bias circuit 14, the second bias circuit 14A does not include a capacitor Cfb.

[0085] The collector and base of the transistor BJT23 are electrically connected. That is, the transistor BJT23 is diode-connected. A control current Ctrl21 is input to the collector and base of the transistor BJT23. The base of the transistor BJT23 is electrically connected to the base of the transistor BJT13. That is, the transistors BJT23 and BJT13 are current-mirror connected.

[0086] One end of the resistor Rc3 is electrically connected to the emitter of the transistor BJT23.

[0087] The collector and base of the transistor BJT22 are electrically connected to the other end of the resistor Rc3.

[0088] A voltage that is the sum of the voltage drop across the transistor BJT23, the voltage drop across the resistor Rc3, and the voltage drop across the transistor BJT22 is generated at the collector and base of the transistor BJT23. This voltage is input to the base of the transistor BJT13.

[0089] The second bias circuit 14A does not include the feedback loop 100 (see FIG. 2) of the second bias circuit 14. Therefore, the capacitor Cfb (see FIG. 2) that limits the band of the feedback loop 100 is not required.

[0090] (effect) Since the second bias circuit 14A does not have the feedback loop 100 of the second bias circuit 14, when noise is present, the noise is not amplified by the feedback loop 100, and high-frequency signals do not oscillate.

[0091] As a result, the power amplifier 2 can suppress noise while maintaining the effect of the power amplifier 1 (suppression of gain fluctuations).

[0092] <Third embodiment> Among the components of the third embodiment, the same components as those of the other embodiments are denoted by the same reference numerals and the description thereof will be omitted.

[0093] FIG. 7 is a diagram illustrating a configuration of a power amplifier according to the third embodiment.

[0094] Compared to the power amplifier 1 (see FIG. 1) of the first embodiment, the power amplifier 3 of the third embodiment includes a first path 11A and a second path 12A instead of the first path 11 and the second path 12. Also, compared to the power amplifier 1, the power amplifier 2 further includes an input branching circuit 16.

[0095] In the third embodiment, the input branch circuit 16 is Transfer This corresponds to an example of a "phase converter."

[0096] The input branch circuit 16 is electrically connected between the input terminal 1 a and the first amplifier 21 , and is also electrically connected between the input terminal 1 a and the third amplifier 31 .

[0097] The input branch circuit 16 has an impedance matching function between the input terminal 1a and the first amplifier 21. In addition, the input branch circuit 16 has an impedance matching function between the input terminal 1a and the third amplifier 31. Furthermore, the input branch circuit 16 has an isolation function between the first amplifier 21 and the third amplifier 31. Although a 90° hybrid coupler is exemplified as the input branch circuit 16, the present disclosure is not limited thereto.

[0098] The input branching circuit 16 delays the radio frequency input signal RFin by a first phase ψ, and outputs the delayed radio frequency signal RF11 to the first amplifier 21. In addition, the input branching circuit 16 delays the radio frequency input signal RFin by a second phase φ that is different from the first phase ψ, and outputs the delayed radio frequency signal RF12 to the third amplifier 31.

[0099] The first path 11A has a first Transfer A matching circuit 24 is included instead of the phase shifter 22. The matching circuit 24 performs impedance matching between the first amplifier 21 and the second amplifier 23.

[0100] The second path 12A has a second Transfer A matching circuit 34 is included instead of the phase shifter 32. The matching circuit 34 performs impedance matching between the third amplifier 31 and the fourth amplifier 33.

[0101] The matching circuit 24 and the matching circuit 34 may have the same circuit configuration. In other words, the matching circuit 24 and the matching circuit 34 may have the same amount of phase delay.

[0102] FIG. 8 is a diagram showing configurations of a first amplifier, a second amplifier, a first bias circuit, and a second bias circuit of a power amplifier according to the third embodiment.

[0103] The configuration of the second path 12A is similar to the configuration of the first path 11A, and therefore, illustration and description thereof will be omitted.

[0104] The matching circuit 24 is electrically connected between the first amplifier 21 and the second amplifier 23, and performs impedance matching between the first amplifier 21 and the second amplifier 23.

[0105] (effect) The power amplifier 3 can suppress and stabilize the gain fluctuation, similarly to the power amplifier 1 of the first embodiment.

[0106] The input branch circuit 16 can ensure isolation between the first amplifier 21 and the third amplifier 31. Therefore, a loop that follows the first path 11A and the second path 12A is not formed.

[0107] As a result, in the power amplifier 3, noise and high-frequency signals do not circulate through the first path 11A and the second path 12A, so that oscillation can be suppressed.

[0108] The input impedance of each of the first amplifier 21 and the third amplifier 31 may change due to a change in bias. However, isolation is ensured between the first amplifier 21 and the third amplifier 31. Therefore, even if the input impedance of one of the first amplifier 21 and the third amplifier 31 changes, it does not affect the other.

[0109] This allows the power amplifier 3 to suppress fluctuations in VSWR (Voltage Standing Wave Ratio) when the phase of the high frequency signal is varied.

[0110] <Fourth embodiment> Among the components of the fourth embodiment, the same components as those of the other embodiments are denoted by the same reference numerals and the description thereof will be omitted.

[0111] FIG. 9 is a diagram illustrating a configuration of a power amplifier according to the fourth embodiment.

[0112] Compared to the power amplifier 3 (see FIG. 7) of the third embodiment, the power amplifier 4 of the fourth embodiment includes a second bias circuit 14A and a third bias circuit 15A instead of the second bias circuit 14 and the third bias circuit 15.

[0113] FIG. 10 is a diagram showing configurations of a first amplifier, a second amplifier, a first bias circuit, and a second bias circuit of a power amplifier according to the fourth embodiment.

[0114] (effect) The power amplifier 4 can suppress and stabilize the gain fluctuation, similarly to the power amplifier 1 of the first embodiment.

[0115] Like the power amplifier 2 of the second embodiment, the power amplifier 4 does not include the feedback loop 100 (see FIG. 2), and therefore can suppress noise.

[0116] In the power amplifier 4, similarly to the power amplifier 3 of the third embodiment, noise and high-frequency signals do not circulate through the first path 11A and the second path 12A, so that oscillation can be suppressed.

[0117] As with the power amplifier 3 of the third embodiment, in the power amplifier 4, even if the input impedance of one of the first amplifier 21 and the third amplifier 31 changes, the other is not affected, and therefore, fluctuations in VSWR when the phase of the high-frequency signal is varied can be suppressed.

[0118] <Fifth embodiment> Among the components of the fifth embodiment, the same components as those of the other embodiments are denoted by the same reference numerals and the description thereof will be omitted.

[0119] FIG. 11 is a diagram illustrating a configuration of a power amplifier according to the fifth embodiment.

[0120] Compared to power amplifier 1 (see FIG. 1) of the first embodiment, power amplifier 5 of the fifth embodiment includes inductors Lc11, Lc12 and Lc2 instead of resistors Rc11, Rc12 and Rc2.

[0121] The inductor Lc11 is electrically connected between the second bias circuit 14 and the first amplifier 21. The inductor Lc12 is electrically connected between the third bias circuit 15 and the third amplifier 31. The inductor Lc2 is electrically connected between the terminal 1c and the second amplifier 23, and between the terminal 1c and the fourth amplifier 33.

[0122] (effect) The inductors Lc11, Lc12, and Lc2 have smaller voltage drops than the resistors Rc11, Rc12, and Rc2.

[0123] As a result, the power amplifier 5 can achieve a higher output than the power amplifier 1.

[0124] Sixth embodiment Among the components of the sixth embodiment, the same components as those of the other embodiments are denoted by the same reference numerals and the description thereof will be omitted.

[0125] FIG. 12 is a diagram illustrating a configuration of a power amplifier according to the sixth embodiment.

[0126] Compared to the power amplifier 5 of the fifth embodiment (see FIG. 11 ), the power amplifier 6 of the sixth embodiment includes a first path 11A and a second path 12A instead of the first path 11 and the second path 12. Moreover, compared to the power amplifier 5, the power amplifier 6 further includes an input branching circuit 16.

[0127] (effect) Like the power amplifier 5, the power amplifier 6 is capable of achieving higher output than the power amplifier 1.

[0128] <Configuration Example of the Present Disclosure> The present disclosure may also have the following configurations.

[0129] (1) an input terminal to which a high frequency input signal is input; an output terminal for outputting a high frequency output signal; a first path and a second path electrically connected between the input terminal and the output terminal, respectively, and connected in parallel with each other; a first amplifier and a second amplifier electrically connected to a downstream of the first amplifier, the second amplifier being included in the first path; a third amplifier and a fourth amplifier electrically connected to a downstream of the third amplifier, both included in the second path; The phase of the high frequency signal flowing through the first path is made different from the phase of the high frequency signal flowing through the second path. Transfer Phaser and a first bias circuit electrically connected to the first amplifier and the third amplifier and configured to provide a bias to the first amplifier and the third amplifier; a second bias circuit electrically connected to the first amplifier and the second amplifier and configured to provide a bias to the first amplifier and the second amplifier; a third bias circuit electrically connected to the third amplifier and the fourth amplifier and configured to provide a bias to the third amplifier and the fourth amplifier; Including, the first amplifier includes a first transistor; the second amplifier includes a second transistor; the third amplifier includes a third transistor; the fourth amplifier includes a fourth transistor; the first bias circuit includes a fifth transistor; the second bias circuit includes a sixth transistor; the third bias circuit includes a seventh transistor; the second transistor and the sixth transistor are connected in a current mirror configuration; the fourth transistor and the seventh transistor are connected in a current mirror configuration; Power amplifier.

[0130] (2) The power amplifier according to (1) above, The above Transfer The phaser is a first amplifier electrically connected between the first amplifier and the second amplifier, for shifting a high-frequency signal output by the first amplifier by a first phase; Transfer Phaser and a second amplifier electrically connected between the third amplifier and the fourth amplifier, for shifting a high frequency signal output from the second amplifier by a second phase different from the first phase; Transfer Phaser and Including, Power amplifier.

[0131] (3) The power amplifier according to (1) above, The above Transfer The phaser is an input branching circuit electrically connected between the input terminal and the first and third amplifiers, which shifts the high frequency input signal by a first phase and outputs it to the first amplifier, and which shifts the high frequency input signal by a second phase different from the first phase and outputs it to the third amplifier; Including, Power amplifier.

[0132] (4) A power amplifier according to any one of (1) to (3), The second bias circuit includes: an eighth transistor providing a bias to the first amplifier; The third bias circuit is a ninth transistor providing a bias to the third amplifier; Power amplifier.

[0133] (5) The power amplifier according to (4) above, the sixth transistor and the eighth transistor form a feedback loop, the seventh transistor and the ninth transistor form a feedback loop. Power amplifier.

[0134] (6) The power amplifier according to (4) above, the sixth transistor and the eighth transistor do not form a feedback loop; The seventh transistor and the ninth transistor do not form a feedback loop. Power amplifier.

[0135] (7) A power amplifier according to any one of (1) to (6), The fifth transistor is a current mirror connection with the first transistor; The fifth transistor is A current mirror connection is made with the third transistor. Power amplifier.

[0136] (8) A power amplifier according to any one of (1) to (7), The second bias circuit includes: providing a bias to the first amplifier via a first inductor; The third bias circuit is providing a bias to the third amplifier via a second inductor; The second amplifier and the fourth amplifier are The supply voltage is supplied via a third inductor. Power amplifier.

[0137] The above-described embodiment is for the purpose of facilitating understanding of the present invention, and is not intended to limit the present invention. The present invention may be modified or improved without departing from the spirit of the present invention, and equivalents thereof are also included in the present invention. [Explanation of symbols]

[0138] 1, 2, 3, 4, 5, 6 Power Amplifier 11, 11A Route 1 12, 12A Route 2 13 First bias circuit 14, 14A Second bias circuit 15, 15A 3rd bias circuit 16 Input branch circuit 21 First Amplifier 22 No. 1 Transfer companion 23 Second Amplifier 24, 34 matching circuit 31 Third Amplifier 32 No. 2 Transfer companion 33 4th Amplifier Rc11, Rc12, Rc2, Rc3, Rb1, Rb2 resistance BJT11, BJT12, BJT13, BJT21, BJT22, BJT23 transistors Cb1, Cb2, Cdc2, Cdc3, Cfb capacitors

Claims

1. an input terminal to which a high frequency input signal is input; an output terminal for outputting a high frequency output signal; a first path and a second path electrically connected between the input terminal and the output terminal, respectively, and connected in parallel with each other; a first amplifier and a second amplifier electrically connected to a downstream of the first amplifier, both included in the first path; a third amplifier and a fourth amplifier electrically connected to a downstream of the third amplifier, both included in the second path; a phase shifter that makes a phase of a high frequency signal flowing through the first path different from a phase of a high frequency signal flowing through the second path; a first bias circuit electrically connected to the first amplifier and the third amplifier and configured to provide a bias to the first amplifier and the third amplifier; a second bias circuit electrically connected to the first amplifier and the second amplifier and configured to provide a bias to the first amplifier and the second amplifier; a third bias circuit electrically connected to the third amplifier and the fourth amplifier and configured to provide a bias to the third amplifier and the fourth amplifier; Including, the first amplifier includes a first transistor; the second amplifier includes a second transistor; the third amplifier includes a third transistor; the fourth amplifier includes a fourth transistor; the first bias circuit includes a fifth transistor; the second bias circuit includes a sixth transistor; the third bias circuit includes a seventh transistor; the second transistor and the sixth transistor are connected in a current mirror configuration; the fourth transistor and the seventh transistor are connected in a current mirror configuration; Power amplifier.

2. 2. A power amplifier according to claim 1, The phase shifter comprises: a first phase shifter electrically connected between the first amplifier and the second amplifier, for shifting a high frequency signal output by the first amplifier by a first phase; a second phase shifter electrically connected between the third amplifier and the fourth amplifier, for shifting the high frequency signal output by the second amplifier by a second phase different from the first phase; Including, Power amplifier.

3. 2. A power amplifier according to claim 1, The phase shifter comprises: an input branching circuit electrically connected between the input terminal and the first and third amplifiers, for shifting the high frequency input signal by a first phase and outputting the signal to the first amplifier, and for shifting the high frequency input signal by a second phase different from the first phase and outputting the signal to the third amplifier; Including, Power amplifier.

4. 2. A power amplifier according to claim 1, The second bias circuit includes: an eighth transistor providing a bias to the first amplifier; The third bias circuit is a ninth transistor providing a bias to the third amplifier; Power amplifier.

5. 5. A power amplifier according to claim 4, the sixth transistor and the eighth transistor form a feedback loop, The seventh transistor and the ninth transistor form a feedback loop. Power amplifier.

6. 5. A power amplifier according to claim 4, the sixth transistor and the eighth transistor do not form a feedback loop; the seventh transistor and the ninth transistor do not constitute a feedback loop; Power amplifier.

7. 2. A power amplifier according to claim 1, The fifth transistor is a current mirror connection with the first transistor; The fifth transistor is A current mirror connection is made with the third transistor. Power amplifier.

8. 2. A power amplifier according to claim 1, The second bias circuit includes: providing a bias to the first amplifier via a first inductor; The third bias circuit is providing a bias to the third amplifier via a second inductor; The second amplifier and the fourth amplifier A power supply voltage is supplied via a third inductor. Power amplifier.

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