Multilayer ceramic capacitor and mounting structure thereof

Abstract

To provide a multilayer ceramic capacitor that suppresses occurrence of "squealing," without significantly impairing profile thinning (downsizing) and capacity heightening.SOLUTION: A multilayer ceramic capacitor includes a laminate in which a plurality of dielectric layers 20 and a plurality of internal electrode layers 30 are laminated. When it is assumed that, out of the plurality of internal electrode layers 30, an internal electrode layer that is located on a first surface TS1 side is defined as a first surface-side internal electrode layer 301 and an internal electrode layer that is located on a second surface TS2 side is defined as a second surface-side internal electrode layer 302, a first solid solution layer 301A where a second metal different from a first metal that is a main component is dissolved is formed at an interface, with the dielectric layer 20, of the first surface-side internal electrode layer 301, and a second solid solution layer 302A where the second metal is dissolved is formed at the interface, with the dielectric layer 20, of the second surface-side internal electrode layer 302. Concentration of the second metal in the second solid solution layer 302A is greater than concentration of the second metal in the first solid solution layer 301A.SELECTED DRAWING: Figure 4

Description

[Technical field]

[0001] The present invention relates to a multilayer ceramic capacitor and a mounting structure for the multilayer ceramic capacitor. [Background technology]

[0002] A multilayer ceramic capacitor is known that includes a laminate in which a plurality of dielectric layers and a plurality of internal electrode layers made of ceramic materials are laminated, and an external electrode disposed on an end face of the laminate. The laminate has an internal layer portion including some of the dielectric layers and a plurality of internal conductor layers, and a first external layer portion and a second external layer portion disposed so as to sandwich the internal layer portion and each including a portion other than the part of the dielectric layers, the first external layer portion disposed on the first main surface side, and the second external layer portion disposed on the second main surface side. In such multilayer ceramic capacitors, further miniaturization (thinning) and high capacity are required, and a ferroelectric material with a relatively high dielectric constant is sometimes used as the material for the dielectric layers.

[0003] However, because such dielectric layers have piezoelectricity and electrostriction, stress and mechanical distortion occur when an electric field is applied. Such stress and mechanical distortion are transmitted as vibrations to the board on which the multilayer ceramic capacitor is mounted. When this happens, the entire board becomes an acoustic reflection surface, generating a vibration noise known as "ringing."

[0004] In order to suppress the occurrence of this "squeak," there is known a multilayer ceramic capacitor in which the thickness of the lower outer layer is made thicker than the thickness of the upper outer layer, thereby suppressing the transmission of vibration from the multilayer ceramic capacitor to the substrate (see Patent Documents 1 to 3). [Prior art documents] [Patent documents]

[0005] [Patent Document 1] JP 2013-251522 A [Patent Document 2] JP 2015-65414 A [Patent Document 3] JP 2019-145684 A Summary of the Invention [Problem to be solved by the invention]

[0006] However, if the thickness of the lower outer layer portion is increased, either the thinning (miniaturization) or the increase in capacitance of the multilayer ceramic capacitor is significantly impaired.

[0007] An object of the present invention is to provide a multilayer ceramic capacitor and a mounting structure for the multilayer ceramic capacitor that suppresses the occurrence of "sound noise" without significantly impairing thinning (downsizing) and high capacitance. [Means for solving the problem]

[0008] As a result of extensive research, the inventor(s) of the present application have come to the new discovery that by adjusting the coverage of the main component metal of the lower internal electrode layer, it is possible to suppress the occurrence of "squeak" without significantly increasing the thickness of the lower outer layer.

[0009] Therefore, the multilayer ceramic capacitor according to the present invention is a laminate in which a plurality of dielectric layers and a plurality of internal electrode layers made of ceramic materials are laminated, the laminate having a first main surface and a second main surface facing each other in a lamination direction, two side surfaces facing each other in a width direction intersecting the lamination direction, and two end surfaces facing each other in a length direction intersecting the lamination direction and the width direction, and two external electrodes arranged on each of the two end surfaces of the laminate. Each of the plurality of internal electrode layers contains a first metal as a main component. If the internal electrode layer arranged on the first main surface side of the plurality of internal electrode layers is referred to as a first main surface side internal electrode layer and the internal electrode layer arranged on the second main surface side is referred to as a second main surface side internal electrode layer, a first solid-solution layer in which a second metal different from the first metal is solid-solved is formed at the interface with the dielectric layer in the first main surface side internal electrode layer, and a second solid-solution layer in which the second metal is solid-solved is formed at the interface with the dielectric layer in the second main surface side internal electrode layer. The concentration of the second metal in the second solid solution layer is higher than the concentration of the second metal in the first solid solution layer.

[0010] A mounting structure for a multilayer ceramic capacitor according to the present invention includes a circuit board and the multilayer ceramic capacitor described above. The multilayer ceramic capacitor is mounted on the circuit board such that the second main surface faces the circuit board. Effect of the Invention

[0011] According to the present invention, it is possible to suppress the occurrence of "squeak noise" without significantly impairing the thinning (miniaturization) and high capacitance of the multilayer ceramic capacitor. [Brief description of the drawings]

[0012] [Figure 1] 1 is a perspective view showing a multilayer ceramic capacitor and a mounting structure of the multilayer ceramic capacitor according to an embodiment of the present invention; [Diagram 2] 2 is a cross-sectional view (LT cross-section) of the multilayer ceramic capacitor and the mounting structure of the multilayer ceramic capacitor shown in FIG. 1. [Diagram 3] 3 is a cross-sectional view (WT cross section) taken along line III-III of the multilayer ceramic capacitor and the mounting structure of the multilayer ceramic capacitor shown in FIG. [Figure 4] 3 is an enlarged cross-sectional view of an internal electrode layer of a laminate in the multilayer ceramic capacitor shown in FIG. 2. [Diagram 5] 10 is a cross-sectional view (LT cross section) of a multilayer ceramic capacitor and a mounting structure of the multilayer ceramic capacitor according to a modified example of the present embodiment. [Figure 6] 10 is a cross-sectional view (WT cross section) of a multilayer ceramic capacitor and a mounting structure of the multilayer ceramic capacitor according to a modified example of the present embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0013] Hereinafter, an embodiment of the present invention will be described with reference to the accompanying drawings, in which the same or corresponding parts in each drawing are designated by the same reference numerals.

[0014] <Multilayer ceramic capacitors> Fig. 1 is a perspective view showing the multilayer ceramic capacitor according to this embodiment, Fig. 2 is a cross-sectional view taken along line II-II of the multilayer ceramic capacitor shown in Fig. 1, and Fig. 3 is a cross-sectional view taken along line III-III of the multilayer ceramic capacitor shown in Fig. 1. The multilayer ceramic capacitor 1 shown in Figs. 1 to 3 includes a laminate 10 and an external electrode 40. The external electrode 40 includes a first external electrode 41 and a second external electrode 42.

[0015] 1 to 3 show an XYZ orthogonal coordinate system. The X direction is the length direction L of the multilayer ceramic capacitor 1 and the laminate 10, the Y direction is the width direction W of the multilayer ceramic capacitor 1 and the laminate 10, and the Z direction is the lamination direction T of the multilayer ceramic capacitor 1 and the laminate 10. Thus, the cross section shown in Fig. 2 is also referred to as an LT cross section, and the cross section shown in Fig. 3 is also referred to as a WT cross section.

[0016] The length direction L, the width direction W, and the stacking direction T do not necessarily have to be perpendicular to each other, and may intersect each other.

[0017] The laminate 10 has a generally rectangular parallelepiped shape and has a first main surface TS1 and a second main surface TS2 facing each other in the stacking direction T, a first side surface WS1 and a second side surface WS2 facing each other in the width direction W, and a first end surface LS1 and a second end surface LS2 facing each other in the longitudinal direction L.

[0018] It is preferable that the corners and ridges of the laminate 10 are rounded. A corner is a portion where three faces of the laminate 10 intersect, and a ridge is a portion where two faces of the laminate 10 intersect.

[0019] 2 and 3, the laminate 10 has a plurality of dielectric layers 20 and a plurality of internal electrode layers 30 stacked in a stacking direction T. The laminate 10 also has, in the stacking direction T, an inner layer portion 100, and a first outer layer portion 101 and a second outer layer portion 102 arranged to sandwich the inner layer portion 100 therebetween.

[0020] The internal layer portion 100 includes some of the multiple dielectric layers 20 and multiple internal electrode layers 30. In the internal layer portion 100, the multiple internal electrode layers 30 are arranged facing each other via the dielectric layers 20. The internal layer portion 100 is a portion that generates capacitance and substantially functions as a capacitor.

[0021] The first outer layer portion 101 is disposed on the first main surface TS1 side of the laminate 10, and the second outer layer portion 102 is disposed on the second main surface TS2 side of the laminate 10. More specifically, the first outer layer portion 101 is disposed between the internal electrode layer 30 closest to the first main surface TS1 among the multiple internal electrode layers 30 and the first main surface TS1, and the second outer layer portion 102 is disposed between the internal electrode layer 30 closest to the second main surface TS2 among the multiple internal electrode layers 30 and the second main surface TS2. The first outer layer portion 101 and the second outer layer portion 102 do not include the internal electrode layer 30, and each of the multiple dielectric layers 20 includes a portion other than the portion for the internal layer portion 100. The first outer layer portion 101 and the second outer layer portion 102 are portions that function as protective layers for the internal layer portion 100.

[0022] The material of the dielectric layer 20 may be, for example, a dielectric ceramic containing BaTiO3, CaTiO3, SrTiO3, CaZrO3, or the like as a main component. The material of the dielectric layer 20 may also contain a Mn compound, an Fe compound, a Cr compound, a Co compound, a Ni compound, or the like as a secondary component.

[0023] The thickness of the dielectric layer 20 is not particularly limited, but is preferably 0.40 μm or more and 0.50 μm or less, and more preferably 0.40 μm or more and 0.45 μm or less. The number of the dielectric layers 20 is not particularly limited, but is preferably 100 sheets or more and 2000 sheets or less. The number of the dielectric layers 20 is the total number of the number of the dielectric layers in the inner layer portion and the number of the dielectric layers in the outer layer portion.

[0024] The multiple internal electrode layers 30 include multiple first internal electrode layers 31 and multiple second internal electrode layers 32. The multiple first internal electrode layers 31 and the multiple second internal electrode layers 32 are alternately arranged in the stacking direction T of the laminate 10.

[0025] The first internal electrode layer 31 includes a counter electrode portion 311 and a lead electrode portion 312 , and the second internal electrode layer 32 includes a counter electrode portion 321 and a lead electrode portion 322 .

[0026] The opposing electrode portion 311 and the opposing electrode portion 321 face each other via the dielectric layer 20 in the stacking direction T of the laminate 10. The shapes of the opposing electrode portion 311 and the opposing electrode portion 321 are not particularly limited and may be, for example, approximately rectangular. The opposing electrode portion 311 and the opposing electrode portion 321 are portions that generate electrostatic capacitance and substantially function as a capacitor.

[0027] The extracted electrode portion 312 extends from the counter electrode portion 311 toward a first end face LS1 of the laminate 10 and is exposed at the first end face LS1. The extracted electrode portion 322 extends from the counter electrode portion 321 toward a second end face LS2 of the laminate 10 and is exposed at the second end face LS2. The shapes of the extracted electrode portion 312 and the extracted electrode portion 322 are not particularly limited and may be, for example, a substantially rectangular shape.

[0028] As a result, the first internal electrode layer 31 is connected to the first external electrode 41, and a gap exists between the first internal electrode layer 31 and the second end face LS2 of the laminate 10, i.e., the second external electrode 42. In addition, the second internal electrode layer 32 is connected to the second external electrode 42, and a gap exists between the second internal electrode layer 32 and the first end face LS1 of the laminate 10, i.e., the first external electrode 41.

[0029] The first internal electrode layer 31 and the second internal electrode layer 32 contain metal Ni as a main component. The first internal electrode layer 31 and the second internal electrode layer 32 may contain at least one selected from metals such as Cu, Ag, Pd, or Au, or alloys containing at least one of these metals, such as an Ag-Pd alloy, as a main component or as a component other than the main component. Furthermore, the first internal electrode layer 31 and the second internal electrode layer 32 may contain particles of a dielectric material having the same composition as the ceramic contained in the dielectric layer 20 as a component other than the main component. In this specification, the metal of the main component is defined as the metal component with the highest weight percentage.

[0030] The thickness of the first internal electrode layer 31 and the second internal electrode layer 32 is not particularly limited, but is preferably, for example, 0.30 μm to 0.40 μm, and more preferably, 0.30 μm to 0.35 μm. The number of the first internal electrode layer 31 and the second internal electrode layer 32 is not particularly limited, but is preferably, for example, 10 to 1000.

[0031] As shown in FIG. 3, the laminate 10 has an electrode facing portion W30 between which the internal electrode layers 30 face, and a first side gap portion WG1 and a second side gap portion WG2 arranged to sandwich the electrode facing portion W30 in the width direction W. The first side gap portion WG1 is located between the electrode facing portion W30 and the first side surface WS1, and the second side gap portion WG2 is located between the electrode facing portion W30 and the second side surface WS2. More specifically, the first side gap portion WG1 is located between the end of the internal electrode layer 30 on the first side surface WS1 side and the first side surface WS1, and the second side gap portion WG2 is located between the end of the internal electrode layer 30 on the second side surface WS2 side and the second side surface WS2. The first side gap portion WG1 and the second side gap portion WG2 do not include the internal electrode layer 30, and only include the dielectric layer 20. The first side gap WG1 and the second side gap WG2 are portions that function as protective layers for the internal electrode layer 30. The first side gap WG1 and the second side gap WG2 are also called W gaps.

[0032] As shown in Fig. 2, the laminate 10 has an electrode facing portion L30 where the first internal electrode layer 31 and the second internal electrode layer 32 of the internal electrode layer 30 face each other, a first end gap portion LG1, and a second end gap portion LG2 in the length direction L. The first end gap portion LG1 is located between the electrode facing portion L30 and the first end face LS1, and the second end gap portion LG2 is located between the electrode facing portion L30 and the second end face LS2. More specifically, the first end gap portion LG1 is located between the end of the second internal electrode layer 32 on the first end face LS1 side and the first end face LS1, and the second end gap portion LG2 is located between the end of the first internal electrode layer 31 on the second end face LS2 side and the second end face LS2. The first end gap LG1 does not include the second internal electrode layer 32 but includes the first internal electrode layer 31 and the dielectric layer 20, and the second end gap LG2 does not include the first internal electrode layer 31 but includes the second internal electrode layer 32 and the dielectric layer 20. The first end gap LG1 is a portion that functions as a lead-out electrode portion to the first end face LS1 of the first internal electrode layer 31, and the second end gap LG2 is a portion that functions as a lead-out electrode portion to the second end face LS2 of the second internal electrode layer 32. The first end gap LG1 and the second end gap LG2 are also referred to as L gaps.

[0033] The electrode opposing portion L30 is provided with the opposing electrode portion 311 of the first internal electrode layer 31 and the opposing electrode portion 321 of the second internal electrode layer 32. The first end gap portion LG1 is provided with the lead-out electrode portion 312 of the first internal electrode layer 31, and the second end gap portion LG2 is provided with the lead-out electrode portion 322 of the second internal electrode layer 32.

[0034] The dimensions of the laminate 10 described above are not particularly limited, but it is preferable that, for example, the length in the longitudinal direction L is 0.05 mm or more and 1.00 mm or less, the width in the transverse direction W is 0.10 mm or more and 0.50 mm or less, and the thickness in the stacking direction T is 0.10 mm or more and 0.50 mm or less. In the laminate 10, if the dimension in the length direction L is L1, the dimension in the width direction W is W1, and the dimension in the lamination direction T is T1, then L1>T1>W1 may be satisfied. This makes it possible to obtain a tall multilayer ceramic capacitor with a large T1 while satisfying the prescribed L1 and W1, thereby realizing a compact size and high capacitance.

[0035] The thicknesses of the dielectric layers 20 and the internal electrode layers 30 can be measured, for example, by observing the LT cross section near the center in the width direction of the laminate exposed by polishing with a scanning electron microscope. Each value may be an average value of measurements taken at multiple locations in the length direction, or may be an average value of measurements taken at multiple locations in the stacking direction.

[0036] Similarly, the thickness of the laminate 10 may be measured by, for example, observing, with a scanning electron microscope, the LT cross section near the center in the width direction of the laminate exposed by polishing, or the WT cross section near the center in the length direction of the laminate exposed by polishing. Each value may be an average value of measurements taken at multiple points in the length direction or width direction. Similarly, the length of the laminate 10 can be measured by, for example, observing the LT cross section near the center in the width direction of the laminate exposed by polishing with a scanning electron microscope. Each value may be an average value of measurements at multiple points in the lamination direction. Similarly, the width of the laminate 10 can be measured, for example, by observing the WT cross section of the laminate exposed by polishing near the center in the longitudinal direction with a scanning electron microscope. Each value may be an average value of measurements taken at multiple points in the lamination direction.

[0037] The external electrodes 40 include a first external electrode 41 and a second external electrode 42 .

[0038] The first external electrode 41 is disposed on a first end face LS1 of the laminate 10, and is connected to the first internal electrode layer 31. The first external electrode 41 may extend from the first end face LS1 to a part of the first main face TS1 and a part of the second main face TS2. The first external electrode 41 may also extend from the first end face LS1 to a part of the first side face WS1 and a part of the second side face WS2.

[0039] The second external electrode 42 is disposed on the second end face LS2 of the laminate 10, and is connected to the second internal electrode layer 32. The second external electrode 42 may extend from the second end face LS2 to a part of the first main face TS1 and a part of the second main face TS2. The second external electrode 42 may also extend from the second end face LS2 to a part of the first side face WS1 and a part of the second side face WS2.

[0040] The first external electrode 41 has a first base electrode layer 415 and a first plating layer 416, and the second external electrode 42 has a second base electrode layer 425 and a second plating layer 426. The first external electrode 41 may be composed of only the first plating layer 416, and the second external electrode 42 may be composed of only the second plating layer 426.

[0041] The first base electrode layer 415 and the second base electrode layer 425 may be fired layers containing metal and glass. The glass may be a glass component containing at least one selected from B, Si, Ba, Mg, Al, Li, etc. As a specific example, borosilicate glass may be used. The metal may contain Cu as a main component. The metal may contain at least one selected from metals such as Ni, Ag, Pd, or Au, or alloys such as Ag-Pd alloy, as a main component or as a component other than the main component.

[0042] The fired layer is a layer formed by applying a conductive paste containing metal and glass to the laminate by a dipping method and firing the layer. The fired layer may be fired after firing the internal electrode layer, or may be fired simultaneously with the internal electrode layer. The fired layer may be a multi-layer structure.

[0043] Alternatively, the first base electrode layer 415 and the second base electrode layer 425 may be a resin layer containing conductive particles and a thermosetting resin. The resin layer may be formed on the above-mentioned fired layer, or may be formed directly on the laminate without forming a fired layer.

[0044] The resin layer is a layer formed by applying a conductive paste containing conductive particles and a thermosetting resin to the laminate by a coating method and then firing the conductive paste. The resin layer may be fired after firing the internal electrode layer, or may be fired simultaneously with the internal electrode layer. The resin layer may be a multi-layer structure.

[0045] The thickness of each of the first base electrode layer 415 and the second base electrode layer 425 as the fired layer or resin layer is not particularly limited, and may be 1 μm or more and 10 μm or less.

[0046] Alternatively, the first base electrode layer 415 and the second base electrode layer 425 may be a thin film layer of 1 μm or less formed by a thin film formation method such as sputtering or vapor deposition, on which metal particles are deposited.

[0047] First plating layer 416 covers at least a portion of first base electrode layer 415, and second plating layer 426 covers at least a portion of second base electrode layer 425. First plating layer 416 and second plating layer 426 each include at least one selected from, for example, metals such as Cu, Ni, Ag, Pd, or Au, or alloys such as Ag-Pd alloy.

[0048] Each of the first plating layer 416 and the second plating layer 426 may be formed of multiple layers. Preferably, it has a two-layer structure of Ni plating and Sn plating. The Ni plating layer can prevent the base electrode layer from being eroded by solder when mounting the ceramic electronic component, and the Sn plating layer improves the wettability of the solder when mounting the ceramic electronic component, making it easier to mount.

[0049] The thickness of each of first plating layer 416 and second plating layer 426 is not particularly limited, and may be 1 μm or more and 10 μm or less.

[0050] As shown in FIGS. 1 to 3, the laminated ceramic capacitor 1 is mounted on a circuit board CB such that the second main surface TS2 faces the circuit board CB.

[0051] <<Internal electrode layer>> Next, the internal electrode layers 30, i.e., the first internal electrode layers 31 and the second internal electrode layers 32, will be further described. Fig. 4 is an enlarged cross-sectional view of the internal electrode layers of the laminate in the multilayer ceramic capacitor shown in Fig. 2. As shown in Fig. 4, among the internal electrode layers 30, i.e., the first internal electrode layers 31 and the second internal electrode layers 32, the internal electrode layers arranged on the first main surface TS1 side from the center of the stacking direction T of the laminate 10 are referred to as the first main surface side internal electrode layers 301, and the internal electrode layers arranged on the second main surface TS2 side from the center of the stacking direction T of the laminate 10 are referred to as the second main surface side internal electrode layers 302.

[0052] A first solid solution layer 301A in which a main component metal, for example Ni, and a different subcomponent metal, for example Sn, are dissolved in solid solution is formed at the interface between the first main surface side internal electrode layer 301 and the dielectric layer 20. Meanwhile, a second solid solution layer 302A in which a subcomponent metal, for example Sn, is dissolved in solid solution is formed at the interface between the second main surface side internal electrode layer 302 and the dielectric layer 20. The metal dissolved in the first solid solution layer 301A and the second solid solution layer 302A may be at least one of Sn, In, Ga, Zn, Bi, Pb, Fe, V, Y, and Cu.

[0053] The concentration (content) of the secondary component metal, such as Sn, in the second solid solution layer 302A is higher than the concentration (content) of the secondary component metal, such as Sn, in the first solid solution layer 301A. In the internal electrode layer, a high concentration (content) of the secondary component metal, such as Sn, means that the concentration (content) of the main component metal, such as Ni, is low, that is, the coverage of the main component metal, such as Ni, is low.

[0054] The occurrence of "squeak" can be suppressed by mounting the multilayer ceramic capacitor 1 on the circuit board CB with the second main surface TS2 side, on which the internal electrode layers with low coverage of the main component metal such as Ni are arranged, facing the circuit board CB. Therefore, since there is no need to thicken the second outer layer portion 102, more internal electrode layers 30 can be arranged, and the multilayer ceramic capacitor 1 can be made thinner (smaller) and have a higher capacity.

[0055] The content (molar ratio) of the secondary component metal, for example, Sn, in the first solid-solution layer 301A is preferably 0.2 mol% or more and 0.8 mol% or less with respect to 100 mol of the main component metal, for example, Ni. On the other hand, the content (molar ratio) of the secondary component metal, for example, Sn, in the second solid-solution layer 302A may be higher than that of the first solid-solution layer 301A and may be 1.5 mol% or more and 2.5 mol% or less with respect to 100 mol of the main component metal, for example, Ni. The ratio of the first main surface side internal electrode layer 301 having the first solid-solution layer 301A to the total number of the internal electrode layers 30 is preferably 60% or more, while the ratio of the second main surface side internal electrode layer 302 having the second solid-solution layer 302A to the total number of the internal electrode layers 30 is preferably 40% or less.

[0056] Here, in order to make the multilayer ceramic capacitor 1 thinner (smaller) and to increase the capacitance, it is possible to reduce the thickness of the dielectric layers 20, for example. However, reducing the thickness of the dielectric layers 20 increases the electric field strength applied to each layer, which may reduce the life span, i.e., the reliability, of the multilayer ceramic capacitor 1.

[0057] In this regard, when the first solid solution layer 301A and the second solid solution layer 302A of a minor component metal such as Sn are formed at the interface of the internal electrode layer 30 with the dielectric layer 20, the insulation is improved at the interface with the dielectric layer 20 where the first solid solution layer 301A and the second solid solution layer 302A are formed, and an increase in the electric field strength in the dielectric layer 20 can be suppressed. Therefore, a decrease in the life span, i.e., the reliability, of the multilayer ceramic capacitor 1 can be suppressed.

[0058] If the content of the secondary component metal such as Sn in the second solid-solution layer 302A (and the first solid-solution layer 301A) is less than 1.5 mol%, the effect of the secondary component metal such as Sn described above is small. On the other hand, if the content of the secondary component metal such as Sn in the first solid-solution layer 301A (and the second solid-solution layer 302A) exceeds 2.5 mol%, the melting point of the internal electrode layer 30 decreases, and the main component metal of the internal electrode layer 30, such as Ni, may become beads. If the main component metal, such as Ni, becomes beads, the internal electrode layer 30 becomes locally thicker, the dielectric layer 20 becomes locally thinner, the electric field strength increases locally, and the effect of the secondary component metal such as Sn described above is canceled.

[0059] The content mol% (molar ratio) of the secondary component metal such as Sn in the first solid-solution layer 301A relative to the main component metal, for example, Ni, 100 mol, in the first main surface side internal electrode layer 301, and the content mol% (molar ratio) of the secondary component metal, such as Sn in the second solid-solution layer 302A relative to the main component metal, for example, Ni, 100 mol, in the second main surface side internal electrode layer 302, can be measured by TEM analysis, etc. The internal electrode layers arranged in the stacking direction are divided into three regions, and the internal electrode layers in the center of each region are measured at 10 points in the in-plane direction 10 nm inside from the interface by TEM analysis, and the average is determined as the molar ratio.

[0060] The thickness of the first solid solution layer 301A is preferably 1 nm or more and 20 nm or less, whereas the thickness of the second solid solution layer 302A is preferably 1 nm or more and 20 nm or less. The thickness of the first solid-solution layer 301A and the second solid-solution layer 302A can be measured by observing the LT cross section near the width direction center of the laminate exposed by polishing, similar to the thickness measurement method of the dielectric layer 20 and the internal electrode layer 30 described above. Measurement equipment can be, for example, wavelength dispersive X-ray analysis (WDX) or energy dispersive X-ray analysis (EDX), scanning electron microscope (SEM) or transmission electron microscope (TEM). In the case of the first solid-solution layer 301A, the content (molar ratio) of the secondary component metal, for example Sn, is set to a region of 0.2 mol% to 0.8 mol% relative to 100 mol of the main component metal, for example Ni, and in the case of the second solid-solution layer 302A, the content (molar ratio) of the secondary component metal, for example Sn, is set to a region of 1.5 mol% to 2.5 mol% relative to 100 mol of the main component metal, for example Ni.

[0061] <Manufacturing method> Next, a method for manufacturing the multilayer ceramic capacitor 1 described above will be described. First, a dielectric sheet for the dielectric layer 20 and a conductive paste for the internal electrode layer 30 are prepared. The dielectric sheet contains Sn. For example, an insulator sheet containing dielectric grain particles with a core-shell structure whose surface is coated with Sn is used. The Sn content of the dielectric sheet is made different between the dielectric sheet adjacent to the first main surface side internal electrode layer 301 and the dielectric sheet adjacent to the second main surface side internal electrode layer 302. In addition, the dielectric sheet and the conductive paste contain a binder and a solvent. Known materials can be used as the binder and the solvent.

[0062] Next, a conductive paste is printed on the dielectric sheet in a predetermined pattern, for example, to form an internal electrode pattern on the dielectric sheet. The internal electrode pattern can be formed by screen printing, gravure printing, or the like.

[0063] Next, a predetermined number of dielectric sheets for the second outer layer portion 102, on which no internal electrode pattern is printed, are laminated. On top of that, dielectric sheets for the inner layer portion 100, on which internal electrode patterns are printed, are laminated in sequence. On top of that, a predetermined number of dielectric sheets for the first outer layer portion 101, on which no internal electrode pattern is printed, are laminated. In this way, a laminate sheet is produced.

[0064] Next, the laminated sheet is pressed in the lamination direction by means of a hydrostatic press or the like to produce a laminated block. Next, the laminated block is cut to a predetermined size to cut out laminated chips. At this time, the corners and ridges of the laminated chips are rounded by barrel polishing or the like.

[0065] Next, the laminated chip is fired to produce the laminate 10. The firing temperature depends on the materials of the dielectric and the internal electrodes, but is preferably 900° C. or higher and 1400° C. or lower. At this time, a solid solution layer is formed at the interface between the internal electrode layer 30 and the dielectric layer 20, where Sn derived from the dielectric layer 20 is segregated and dissolved. For example, as described above, by making the Sn content different between the dielectric sheet adjacent to the first main surface side internal electrode layer 301 and the dielectric sheet adjacent to the second main surface side internal electrode layer 302, a first solid solution layer 301A is formed at the interface between the first main surface side internal electrode layer 301 and the dielectric layer 20, where Sn derived from the dielectric layer 20 is segregated and dissolved, and a second solid solution layer 302A is formed at the interface between the second main surface side internal electrode layer 302 and the dielectric layer 20, where Sn derived from the dielectric layer 20 is segregated and dissolved.

[0066] Next, the first end face LS1 of the laminate 10 is immersed in a conductive paste that is an electrode material for the base electrode layer by using a dipping method, thereby applying a conductive paste for the first base electrode layer 415 to the first end face LS1. Similarly, the second end face LS2 of the laminate 10 is immersed in a conductive paste that is an electrode material for the base electrode layer by using a dipping method, thereby applying a conductive paste for the second base electrode layer 425 to the second end face LS2. Then, these conductive pastes are fired to form the first base electrode layer 415 and the second base electrode layer 425, which are fired layers. The firing temperature is preferably 600°C or higher and 900°C or lower.

[0067] As described above, the first base electrode layer 415 and the second base electrode layer 425, which are resin layers, may be formed by applying a conductive paste containing conductive particles and a thermosetting resin by a coating method and baking it, or the first base electrode layer 415 and the second base electrode layer 425, which are thin films, may be formed by a thin film formation method such as a sputtering method or a vapor deposition method.

[0068] Thereafter, a first plating layer 416 is formed on the surface of the first base electrode layer 415 to form the first external electrode 41, and a second plating layer 426 is formed on the surface of the second base electrode layer 425 to form the second external electrode 42. Through the above steps, the multilayer ceramic capacitor 1 described above is obtained.

[0069] As described above, according to the multilayer ceramic capacitor 1 of this embodiment, the first solid solution layer 301A in which the main component metal, for example, Ni, and a secondary component metal, for example, Sn, different from the main component metal, is formed in the first main surface TS1 side of the first main surface side internal electrode layer 301, and the second solid solution layer 302A in which the main component metal, for example, Ni, and a secondary component metal, for example, Sn, different from the main component metal, is formed in the second solid solution layer 302A, and the concentration (content) of the secondary component metal, for example, Sn, in the second solid solution layer 302A is higher than the concentration (content) of the secondary component metal, for example, Sn, in the first solid solution layer 301A. In the internal electrode layer, a high concentration (content) of the secondary component metal, such as Sn, means that the concentration (content) of the main component metal, such as Ni, is low, that is, the coverage of the main component metal, such as Ni, is low.

[0070] By mounting the multilayer ceramic capacitor 1 on the circuit board CB with the second main surface TS2 side, on which the internal electrode layers with low coverage of the main component metal such as Ni are arranged, facing the circuit board CB, it is possible to suppress the occurrence of "squeak". As a result, it is not necessary to thicken the second outer layer portion 102, and more internal electrode layers 30 can be arranged, making it possible to make the multilayer ceramic capacitor 1 thinner (smaller) and with a higher capacity. Therefore, it is possible to suppress the occurrence of "squeak" without impairing the thinning (smaller) and high capacity of the multilayer ceramic capacitor 1.

[0071] Although the embodiment of the present invention has been described above, the present invention is not limited to the above-mentioned embodiment, and various changes and modifications are possible. For example, in the above-mentioned embodiment, a multilayer ceramic capacitor in which the boundary between the first main surface side internal electrode layer 301 and the second main surface side internal electrode layer 302 is near the center of the stacking direction T of the multilayer body 10 is exemplified. However, the present invention is not limited to this, and the boundary between the first main surface side internal electrode layer 301 and the second main surface side internal electrode layer 302 may be biased toward the first main surface TS1 side or toward the second main surface TS2 side. Alternatively, an internal electrode layer different from these internal electrode layers may be further disposed between the first main surface side internal electrode layer 301 and the second main surface side internal electrode layer 302. For example, the concentration (content) of a secondary component metal such as Sn in the intrinsic layer of the internal electrode layer may increase in two or more steps from the first main surface TS1 to the second main surface TS2, or a solid solution layer in which a secondary component metal such as Sn is dissolved may not be formed in the internal electrode layer between the first main surface side internal electrode layer 301 and the second main surface side internal electrode layer 302.

[0072] In the above-described embodiment, the multilayer ceramic capacitor is exemplified in which the thickness of the second outer layer portion 102 is approximately the same as the thickness of the first outer layer portion 101. However, the present invention is not limited to this, and as shown in FIG. 5 and FIG. 6, the thickness of the second outer layer portion 102 may be thicker than the thickness of the first outer layer portion 101. In other words, the distance between the internal electrode layer 30 closest to the second main surface TS2 and the second main surface TS2 may be larger than the distance between the internal electrode layer 30 closest to the first main surface TS1 and the first main surface TS1. In this modification, the effect of thinning (downsizing) and increasing the capacity is lower than in the above-described embodiment, but the effect of suppressing the occurrence of "squeak" is higher. Therefore, in this modification, the occurrence of "squeak" can be further suppressed without significantly impairing the thinning (downsizing) and increasing the capacity of the multilayer ceramic capacitor 1.

[0073] The method for measuring the thickness of the first outer layer portion 101 and the second outer layer portion 102 may be the same as the method for measuring the thickness of the dielectric layer 20 and the internal electrode layer 30 described above. For example, a method may be used in which the LT cross section near the widthwise center of the laminate exposed by polishing is observed with a scanning electron microscope. Each value may be an average value of measurements at multiple points in the length direction.

[0074] As a manufacturing method for the multilayer ceramic capacitor, a method of later providing a dielectric for the side gaps on the side surfaces WS1 and WS2 in the width direction W of the laminate 10 may be used. In this case, in the multilayer ceramic capacitor, the ends on both sides in the width direction W of the internal electrode layers are aligned (for example, aligned within an error of 5 μm). [Explanation of symbols]

[0075] 1. Multilayer ceramic capacitors 10 Laminate 20 Dielectric layer 30 Internal electrode layer 301 First main surface side internal electrode layer 302 Second main surface side internal electrode layer 301A First solid solution layer 302A Second solid solution layer 31 First internal electrode layer 311 First opposing electrode portion 312 First extraction electrode part 313 Diffusion Layer 32 Second internal electrode layer 321 Second opposing electrode part 322 Second extraction electrode part 323 Diffusion Layer 40 External electrode 41 First external electrode 415 First base electrode layer 416 First plating layer 42 Second external electrode 425 Second base electrode layer 426 Second plating layer 100 Inner layer 101 First Outer Layer 102 Second Outer Layer L30 Electrode facing part LG1 First end gap LG2 Second end gap section W30 Electrode facing part WG1 First side gap WG2 Second side gap L Length direction T Stacking direction W Width direction LS1 First end face LS2 Second end face TS1 First main surface TS2 Second main surface WS1 First Aspect WS2 The Second Side

Claims

1. a laminate including laminated dielectric layers and internal electrode layers, the laminate having a first surface and a second surface opposed to each other in a lamination direction, a third surface and a fourth surface opposed to each other in a width direction intersecting the lamination direction, and a fifth surface and a sixth surface opposed to each other in a length direction intersecting the lamination direction and the width direction; external electrodes provided on the fifth surface and the sixth surface of the laminate; Equipped with The internal electrode layer contains a first metal as a main component, Among the internal electrode layers, an internal electrode layer disposed on the first surface side is referred to as a first surface side internal electrode layer, and an internal electrode layer disposed on the second surface side is referred to as a second surface side internal electrode layer, the first surface side internal electrode layer includes a first solid solution layer in which a second metal different from the first metal is dissolved in a solid solution at an interface with the dielectric layer, the second surface side internal electrode layer includes a second solid solution layer in which the second metal is dissolved at an interface with the dielectric layer, a concentration of the second metal in the second solid solution layer is higher than a concentration of the second metal in the first solid solution layer; Multilayer ceramic capacitor.

2. a content of the second metal in the first solid solution layer is 0.2 mol % or more and 0.8 mol % or less with respect to 100 mol of the first metal, The content of the second metal in the second solid solution layer is 1.5 mol % or more and 2.5 mol % or less with respect to 100 mol of the first metal. The multilayer ceramic capacitor according to claim 1 .

3. 3. The multilayer ceramic capacitor according to claim 1, wherein, in the laminate, the dimension in the length direction is L1, the dimension in the width direction is W1, and the dimension in the lamination direction is T1, where L1>T1>W1.

4. the laminate has an inner layer portion including a portion of the dielectric layer and the internal electrode layer, and a first outer layer portion and a second outer layer portion arranged to sandwich the inner layer portion and each including a portion other than the portion of the dielectric layer, the first outer layer portion being arranged on the first surface side, and the second outer layer portion being arranged on the second surface side; 3. The multilayer ceramic capacitor according to claim 1, wherein the second outer layer portion is thicker than the first outer layer portion.

5. 3. The multilayer ceramic capacitor according to claim 1, wherein the first metal is Ni.

6. 3. The multilayer ceramic capacitor according to claim 1, wherein the second metal is Sn, In, Ga, Zn, Bi, Pb, Fe, V, Y, or Cu.

7. The thickness of the first solid solution layer is 1 nm or more and 20 nm or less, The thickness of the second solid solution layer is 1 nm or more and 20 nm or less.

3. The multilayer ceramic capacitor according to claim 1.

8. The ratio of the first surface side internal electrode layers to the internal electrode layers is 60% or more, The ratio of the second surface side internal electrode layers to the internal electrode layers is 40% or less.

3. The multilayer ceramic capacitor according to claim 1 or 2.

9. A circuit board; The multilayer ceramic capacitor according to claim 1 or 2, Equipped with the multilayer ceramic capacitor is mounted on the circuit board such that the second surface faces the circuit board; Mounting structure of a multilayer ceramic capacitor.

Images