Three-dimensional memory device and method for forming same - Patents.com

Abstract

A three-dimensional (3D) memory device and a method for forming the same are disclosed. In a particular embodiment, the 3D memory device includes a stack structure including alternating conductive and dielectric layers, a channel structure extending through the stack structure, and a doped semiconductor layer, the doped semiconductor layer including a plate and a plug extending from the plate into the channel structure. The channel structure includes a memory film and a semiconductor channel. The semiconductor channel includes a doped portion, and a portion of the doped portion of the semiconductor channel extends beyond the stack structure in a first direction. The doped portion of the semiconductor channel surrounds the plug of the doped semiconductor layer.

Description

[Technical field]

[0001] The present disclosure relates to three-dimensional (3D) memory devices and methods for fabricating the same. [Background technology]

[0002] Planar memory cells are scaled to smaller sizes by improving process technology, circuit design, programming algorithms, and fabrication processes. However, as memory cell feature sizes approach lower limits, planar processes and fabrication techniques become difficult and costly. As a result, memory density for planar memory cells approaches an upper limit.

[0003] 3D memory architectures can address density limitations of planar memory cells and include a memory array and peripheral devices for controlling signals to and from the memory array. Summary of the Invention [Means for solving the problem]

[0004] In one embodiment, a 3D memory device includes a stack structure including alternating conductive and dielectric layers, a channel structure extending through the stack structure, and a doped semiconductor layer, the doped semiconductor layer including a plate and a plug extending from the plate into the channel structure. The channel structure includes a memory film and a semiconductor channel. The semiconductor channel includes a doped portion, and a portion of the doped portion of the semiconductor channel extends beyond the stack structure in a first direction. The doped portion of the semiconductor channel surrounds the plug of the doped semiconductor layer.

[0005] In another embodiment, a 3D memory device includes a stack structure including interleaved conductive and dielectric layers, a doped semiconductor layer, and a channel structure extending through the stack structure. The channel structure includes a memory film and a semiconductor channel. The channel structure includes a memory film and a semiconductor channel. The semiconductor channel includes a doped portion. The channel structure extends beyond the stack structure in a first direction and is in contact with the doped semiconductor layer. The semiconductor channel includes a doped portion extending beyond one of the conductive layers in a second direction opposite the first direction.

[0006] In yet another aspect, a method for forming a 3D memory device is provided. A fill layer is formed above a substrate. A stack structure is formed above the fill layer. A channel structure is formed extending through the stack structure and the fill layer. The channel structure includes a memory film and a semiconductor channel. Portions of the channel structure extending beyond the substrate and the fill layer are sequentially removed to expose a portion of the semiconductor channel. A doped semiconductor layer is formed in contact with the exposed portion of the semiconductor channel. The doped semiconductor layer and the portion of the semiconductor channel in contact with the doped semiconductor layer are locally activated.

[0007] In yet another aspect, a system includes a 3D memory device configured to store data and a memory controller, the memory controller coupled to the 3D memory device and configured to control the 3D memory device. The 3D memory device includes a stack structure including alternating conductive and dielectric layers, a channel structure extending through the stack structure, and a doped semiconductor layer, the doped semiconductor layer including a plate and a plug extending from the plate into the channel structure. The channel structure includes a memory film and a semiconductor channel. The semiconductor channel includes a doped portion, and a portion of the doped portion of the semiconductor channel extends beyond the stack structure in a first direction. The doped portion of the semiconductor channel surrounds the plug of the doped semiconductor layer.

[0008] The accompanying drawings, which are incorporated in and form a part of the specification, illustrate aspects of the present disclosure and, together with the description, serve to explain the principles of the disclosure and to enable those skilled in the art to make and use the disclosure. [Brief description of the drawings]

[0009] [Figure 1A] 1 is a cross-sectional side view of an exemplary 3D memory device according to some aspects of the disclosure. [Figure 1B] 1 is a cross-sectional side view of another exemplary 3D memory device in accordance with some aspects of the present disclosure. [Diagram 2] 1B is a cross-sectional enlarged side view of an example channel structure in the 3D memory device of FIG. 1A according to some embodiments of the present disclosure. [Figure 3A] 1A-1D illustrate a fabrication process for forming an exemplary 3D memory device according to some aspects of the present disclosure. [Figure 3B] 1A-1D illustrate a fabrication process for forming an exemplary 3D memory device according to some aspects of the present disclosure. [Figure 3C]1A-1D illustrate a fabrication process for forming an exemplary 3D memory device according to some aspects of the present disclosure. [Figure 3D] 1A-1D illustrate a fabrication process for forming an exemplary 3D memory device according to some aspects of the present disclosure. [Figure 3E] 1A-1D illustrate a fabrication process for forming an exemplary 3D memory device according to some aspects of the present disclosure. [Figure 3F] 1A-1D illustrate a fabrication process for forming an exemplary 3D memory device according to some aspects of the present disclosure. [Figure 3G] 1A-1D illustrate a fabrication process for forming an exemplary 3D memory device according to some aspects of the present disclosure. [Figure 3H] 1A-1D illustrate a fabrication process for forming an exemplary 3D memory device according to some aspects of the present disclosure. [Figure 3I] 1A-1D illustrate a fabrication process for forming an exemplary 3D memory device according to some aspects of the present disclosure. [Figure 3J] 1A-1D illustrate a fabrication process for forming an exemplary 3D memory device according to some aspects of the present disclosure. [Figure 3K] 1A-1D illustrate a fabrication process for forming an exemplary 3D memory device according to some aspects of the present disclosure. [Figure 3L] 1A-1D illustrate a fabrication process for forming an exemplary 3D memory device according to some aspects of the present disclosure. [Figure 3M] 1A-1D illustrate a fabrication process for forming an exemplary 3D memory device according to some aspects of the present disclosure. [Figure 3N] 1A-1D illustrate a fabrication process for forming an exemplary 3D memory device according to some aspects of the present disclosure. [Figure 3O] 1A-1D illustrate a fabrication process for forming an exemplary 3D memory device according to some aspects of the present disclosure. [Figure 4A] 1A-1D illustrate a fabrication process for forming another exemplary 3D memory device in accordance with some aspects of the present disclosure. [Figure 4B] 1A-1D illustrate a fabrication process for forming another exemplary 3D memory device in accordance with some aspects of the present disclosure. [Figure 4C] 1A-1D illustrate a fabrication process for forming another exemplary 3D memory device in accordance with some aspects of the present disclosure. [Diagram 5] 1 is a flowchart of an exemplary method for forming a 3D memory device according to some aspects of the present disclosure. [Figure 6] 1 is a flowchart of another exemplary method for forming a 3D memory device according to some aspects of the present disclosure. [Figure 7] 1 is a block diagram of an example system having a 3D memory device in accordance with some aspects of the present disclosure. [Figure 8A] 1 is a diagram of an exemplary memory card having a 3D memory device according to some aspects of the disclosure. [Figure 8B] 1 is a diagram of an exemplary solid-state drive (SSD) having a 3D memory device according to some embodiments of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] The present disclosure will now be described with reference to the accompanying drawings.

[0011] While specific configurations and arrangements are discussed, it should be understood that this is done for illustrative purposes only. As such, other configurations and arrangements can be used without departing from the scope of the present disclosure. The present disclosure can also be used in a variety of other applications. The functional and structural features as described in the present disclosure can be combined, adjusted, and modified with each other and in ways not specifically shown in the drawings, such that these combinations, adjustments, and modifications are within the scope of the present disclosure.

[0012] Generally, terminology can be understood, at least in part, from usage in context. For example, the term "one or more" as used herein can be used in a singular sense to describe any feature, structure, or characteristic, or in a plural sense to describe a combination of features, structures, or characteristics, depending at least in part on the context. Similarly, terms such as "a," "an," or "the," etc., can be understood to convey singular usage or plural usage, again, depending at least in part on the context. In addition, the term "based on" can be understood not necessarily intended to convey an exclusive set of factors, but instead can allow for the existence of additional factors not necessarily explicitly recited, again, depending at least in part on the context.

[0013] It should be readily understood that the meanings of "on," "above," and "over" in this disclosure are to be interpreted in the broadest manner, such that "on" not only means "directly on" something, but also includes meaning "on" something with an intermediate feature or layer between them, and that "above" or "over" can not only mean "above" or "over" something, but also include meaning it is "above" or "over" something (i.e., directly on) with no intermediate features or layers between them.

[0014] Additionally, spatially relative terms such as "below," "below," "lower," "above," and "upper" may be used herein to describe the relationship of one element or feature to another element or feature as illustrated in the figures for ease of description. The spatially relative terms are intended to encompass different orientations of the device during use or operation in addition to the orientation shown in the figures. The device may be otherwise oriented (rotated 90 degrees or in other orientations) and the spatially relative descriptors used herein may be interpreted accordingly.

[0015] As used herein, the term "substrate" refers to a material onto which subsequent layers of material are added. The substrate itself can be patterned. The material added onto the substrate can be patterned or left unpatterned. Moreover, the substrate can include a variety of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, and the like. Alternatively, the substrate can be made of a non-conductive material, such as glass, plastic, or a sapphire wafer.

[0016] As used herein, the term "layer" refers to a material portion that includes a region having a predetermined thickness. A layer can extend throughout an underlying or overlying structure, or can have an extension that is less than the extension of the underlying or overlying structure. Furthermore, a layer can be a homogeneous or heterogeneous region of a continuous structure that has a thickness that is less than the thickness of the continuous structure. For example, a layer can be located between any pair of horizontal planes between (or at) the top and bottom surfaces of a continuous structure. A layer can extend horizontally, vertically, and / or along a tapered surface. A substrate can be a layer and can include one or more layers therein and / or have one or more layers on, above, and / or below it. A layer can include multiple layers. For example, an interconnect layer can include one or more conductor and contact layers (with interconnect lines and / or vertical interconnect access (via) contacts formed therein) and one or more dielectric layers.

[0017] In some 3D NAND memory devices, the semiconductor layer is selectively grown around the sidewalls of the channel structure (e.g., known as sidewall selective epitaxial growth (SEG)). Compared to another type of semiconductor layer that is epitaxially grown at the source end of the channel structure (e.g., bottom SEG), the formation of sidewall SEG avoids etching the memory film and semiconductor channel at the bottom surface of the channel hole (known as SONO punch), thereby increasing the process window, especially when fabricating 3D NAND memory devices with advanced technologies (e.g., with 90 or more levels with a multi-deck architecture).

[0018] However, because an intrinsic (pure, undoped) semiconductor material (such as intrinsic polysilicon) is used to form the semiconductor channel, a relatively high potential barrier exists between the semiconductor channel and the sidewall SEG or the conductive layer in contact with the semiconductor channel, thereby introducing a high contact resistance therebetween. The electrical performance of the 3D memory device may be affected by the high contact resistance.

[0019] To address the above-mentioned problems, the present disclosure introduces a solution in which the contact resistance between the semiconductor channel and the sidewall SEG or conductive layer can be reduced. In some implementations, the semiconductor channel is partially doped such that a portion of the semiconductor channel forming the source contact is highly doped to lower the potential barrier while leaving another portion of the semiconductor channel remaining undoped or forming a lightly doped memory cell. In some implementations, one end of each channel structure is opened from the backside to expose a doped portion of each semiconductor channel, and the 3D memory device further includes a doped semiconductor layer that electrically connects the exposed doped portion of the semiconductor channel to further reduce the contact resistance and sheet resistance. For example, the doped semiconductor layer can include a plug that extends the channel structure by replacing a portion of the capping layer of the channel structure to increase the contact area and further reduce the contact resistance. As a result, the electrical performance of the 3D memory device can be improved.

[0020] Consistent with the scope of the present disclosure, the doped portion of the semiconductor channel and the doped semiconductor layer can be locally activated (e.g., through local annealing) to activate the dopants therein without damaging other parts on the device chip that are heat sensitive (e.g., bonding interfaces and copper interconnects, etc.). For example, the heat to activate the dopants can be confined to an area that excludes heat sensitive components on the device chip. In some implementations, the local activation process also serves as an in situ doping process to dope the portion of the intrinsic semiconductor channel that is in contact with the doped semiconductor layer.

[0021] FIG. 1A illustrates a cross-sectional side view of an exemplary 3D memory device 100 according to some aspects of the disclosure. In some implementations, the 3D memory device 100 is a bonded chip including a first semiconductor structure 102 and a second semiconductor structure 104 stacked on the first semiconductor structure 102. According to some implementations, the first and second semiconductor structures 102 and 104 are bonded at a bonding interface 106 therebetween. As shown in FIG. 1A, the first semiconductor structure 102 can include a substrate 101, which can include silicon (e.g., single crystal silicon, c-Si), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), or any other suitable material.

[0022] The first semiconductor structure 102 of the 3D memory device 100 can include a peripheral circuit 108 on the substrate 101. It is noted that x-axis and y-axis are included in FIG. 1A to further illustrate the spatial relationships of components in the 3D memory device 100 with the substrate 101. The substrate 101 includes two lateral surfaces (e.g., a top surface and a bottom surface) that extend laterally in the x-direction (i.e., laterally). As used herein, whether one component (e.g., a layer or device) is "on," "above," or "below" another component (e.g., a layer or device) of a semiconductor device is determined in the y-direction (i.e., vertical direction) relative to the substrate of the semiconductor device (e.g., substrate 101) when the substrate is positioned in the lowest plane of the semiconductor device (e.g., 3D memory device 100) in the y-direction. The same concepts for describing spatial relationships are applied throughout this disclosure.

[0023] In some implementations, the peripheral circuits 108 are configured to control and sense the 3D memory device 100. The peripheral circuits 108 can be any suitable digital, analog, and / or mixed-signal control and sensing circuitry used to facilitate operation of the 3D memory device 100, including, but not limited to, page buffers, decoders (e.g., row and column decoders), sense amplifiers, drivers (e.g., word line drivers), charge pumps, current or voltage references, or any active or passive components of the circuitry (e.g., transistors, diodes, resistors, or capacitors). The peripheral circuits 108 can include transistors formed on the substrate 101, either wholly or partially formed in the substrate 101 (e.g., below the top surface of the substrate 101) and / or directly on the substrate 101. Isolation regions (e.g., shallow trench isolation (STI)) and doped regions (e.g., source and drain regions of the transistors) can be formed in the substrate 101 as well. According to some implementations, the transistors are fast due to advanced logic processes (e.g., technology nodes of 90 nm, 65 nm, 45 nm, 32 nm, 28 nm, 20 nm, 16 nm, 14 nm, 10 nm, 7 nm, 5 nm, 3 nm, 2 nm, etc.). It is understood that in some implementations, the peripheral circuits 108 can further include any other circuits compatible with advanced logic processes, including logic circuits (e.g., processors and programmable logic devices (PLDs)) or memory circuits (e.g., static random access memories (SRAMs) and dynamic RAMs (DRAMs)).

[0024] In some implementations, the first semiconductor structure 102 of the 3D memory device 100 further includes an interconnect layer (not shown) above the peripheral circuitry 108 to transfer electrical signals to and from the peripheral circuitry 108. The interconnect layer can include a plurality of interconnects (also referred to herein as contacts), including lateral interconnect lines and vertical interconnect access (VIA) contacts. As used herein, the term interconnect can broadly include any suitable type of interconnect, such as middle-end-of-line (MEOL) interconnects and back-end-of-line (BEOL) interconnects. The interconnect layer can further include one or more interlayer dielectric (ILD) layers (also known as intermetal dielectric (IMD) layers), and the interconnect lines and VIA contacts can be formed in the one or more interlayer dielectric (ILD) layers. That is, the interconnect layer may include interconnect lines and VIA contacts in multiple ILD layers. The interconnect lines and VIA contacts in the interconnect layer may include conductive materials including, but not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), silicide, or any combination thereof. The ILD layers in the interconnect layer may include dielectric materials including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, low dielectric constant (low k) dielectrics, or any combination thereof.

[0025] As shown in FIG. 1A, the first semiconductor structure 102 of the 3D memory device 100 can further include a bonding layer 110 at the bonding interface 106 and above the interconnect layer and peripheral circuitry 108. The bonding layer 110 can include a plurality of bonding contacts 111 and a dielectric that electrically isolates the bonding contacts 111. The bonding contacts 111 can include a conductive material, including but not limited to W, Co, Cu, Al, a silicide, or any combination thereof. The remaining areas of the bonding layer 110 can be formed by a dielectric, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, a low-k dielectric, or any combination thereof. The bonding contacts 111 and the surrounding dielectric in the bonding layer 110 can be used for hybrid bonding.

[0026] Similarly, as shown in FIG. 1A, the second semiconductor structure 104 of the 3D memory device 100 can also include a bonding layer 112 at the bonding interface 106 and above the bonding layer 110 of the first semiconductor structure 102. The bonding layer 112 can include a plurality of bonding contacts 113 and a dielectric that electrically isolates the bonding contacts 113. The bonding contacts 113 can include a conductive material, including but not limited to W, Co, Cu, Al, a silicide, or any combination thereof. The remaining areas of the bonding layer 112 can be formed by a dielectric, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, a low-k dielectric, or any combination thereof. The bonding contacts 113 and the surrounding dielectric in the bonding layer 112 can be used for hybrid bonding. According to some implementations, bonding contact 113 contacts bonding contact 111 at bonding interface 106 .

[0027] As described in detail below, the second semiconductor structure 104 can be bonded on the first semiconductor structure 102 in a face-to-face manner at the bonding interface 106. In some implementations, the bonding interface 106 is disposed between the bonding layer 110 and the bonding layer 112 as a result of hybrid bonding (also known as "metal / dielectric hybrid bonding"), which is a direct bonding technique (e.g., forming a bond between surfaces without using an intermediate layer (e.g., solder or adhesive, etc.)) that can simultaneously obtain metal-metal bonding and dielectric-dielectric bonding. In some implementations, the bonding interface 106 is where the bonding layers 112 and 110 meet and bond. In practice, the bonding interface 106 can be a layer having a certain thickness that includes the top surface of the bonding layer 110 of the first semiconductor structure 102 and the bottom surface of the bonding layer 112 of the second semiconductor structure 104.

[0028] In some implementations, the second semiconductor structure 104 of the 3D memory device 100 further includes an interconnect layer (not shown) above the bonding layer 112 to transfer electrical signals. The interconnect layer can include multiple interconnects (e.g., MEOL interconnects and BEOL interconnects, etc.). The interconnect layer can further include one or more ILD layers, and the interconnect lines and VIA contacts can be formed in the one or more ILD layers. The interconnect lines and VIA contacts in the interconnect layer can include conductive materials, including, but not limited to, W, Co, Cu, Al, silicide, or any combination thereof. The ILD layers in the interconnect layer can include dielectric materials, including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof.

[0029] In some implementations, the 3D memory device 100 is a NAND flash memory device, in which memory cells are provided in the form of an array of NAND memory strings. Each NAND memory string can include a respective channel structure 124. As shown in FIG. 1A, each channel structure 124 can extend vertically through multiple pairs each including a stacked conductive layer 116 and a stacked dielectric layer 118. The interleaved stacked conductive layers 116 and stacked dielectric layers 118 are part of the memory stack 114. The number of pairs of stacked conductive layers 116 and stacked dielectric layers 118 in the memory stack 114 determines the number of memory cells in the 3D memory device 100. In some implementations, the memory stack 114 can have a multi-deck architecture (not shown), which is understood to include multiple memory decks stacked on top of each other. The number of pairs of stacked conductive layers 116 and stacked dielectric layers 118 in each memory deck can be the same or different.

[0030] The memory stack 114 may include a plurality of interleaved stack conductive layers 116 and stack dielectric layers 118. The stack conductive layers 116 and stack dielectric layers 118 in the memory stack 114 may alternate vertically. In other words, each stack conductive layer 116, except for the one at the top or bottom of the memory stack 114, may be flanked by two stack dielectric layers 118 on both sides, and each stack dielectric layer 118 may be flanked by two stack conductive layers 116 on both sides. The stack conductive layers 116 may include conductive materials including, but not limited to, W, Co, Cu, Al, polysilicon, doped silicon, silicide, or any combination thereof. Each stack conductive layer 116 may include a gate electrode (gate line) surrounded by an adhesive layer and a gate dielectric layer. The gate electrode of the stack conductive layer 116 may extend laterally as a word line and terminate in one or more staircase structures of the memory stack 114. The stack dielectric layer 118 may include a dielectric material including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof.

[0031] As shown in FIG. 1A, the second semiconductor structure 104 of the 3D memory device 100 may also include a fill layer 120 above the memory stack 114. The fill layer 120 may include polysilicon, a high dielectric constant (high-k) dielectric, or a metal. For example, a high-k dielectric may include any dielectric material having a higher dielectric constant (e.g., k>3.7) than that of silicon oxide. Unlike some known solutions in which the fill layer 120 acts as a sidewall SEG surrounding the channel structure 124 and / or a conductive layer (e.g., a doped polysilicon layer, etc.) that electrically connects the channel structure 124, the fill layer 120 of the second semiconductor structure 104 of the 3D memory device 100 may not act as a sidewall SEG and / or a conductive layer, and thus may include a material other than doped polysilicon, such as a dielectric (e.g., a high-k dielectric), a metal (e.g., W, Co, Cu, or Al), a metal silicide, or undoped polysilicon. It is understood that in some instances, the fill layer 120 may also include doped polysilicon.

[0032] In some implementations, each channel structure 124 includes a channel hole filled by a semiconductor layer (e.g., as the semiconductor channel 128) and a composite dielectric layer (e.g., as the memory film 126). In some implementations, the semiconductor channel 128 includes silicon (e.g., amorphous silicon, polysilicon, or single crystal silicon). In some implementations, the memory film 126 is a composite layer including a tunneling layer, a storage layer (also known as a "charge trap layer"), and a blocking layer. As shown in FIG. 1A, the remaining space of the channel hole can be partially filled by a capping layer 127 including a dielectric material (e.g., silicon oxide) and / or an air gap (not shown). The channel structure 124 can have a cylindrical shape (e.g., a pillar shape). According to some implementations, the capping layer, the semiconductor channel 128, the tunneling layer, the storage layer, and the blocking layer of the memory film 126 are arranged in this order radially from the center to the outer surface of the pillar. The tunneling layer can include silicon oxide, silicon oxynitride, or any combination thereof. The storage layer can include silicon nitride, silicon oxynitride, silicon, or any combination thereof. The blocking layer can include silicon oxide, silicon oxynitride, high-k dielectric, or any combination thereof. In one example, the memory film 126 can include a composite layer of silicon oxide / silicon oxynitride / silicon oxide (ONO).

[0033] In some implementations, the channel structure 124 further includes a channel plug 129 at a bottom portion (e.g., at a lower end) of the channel structure 124. As used herein, an upper end of a component (e.g., the channel structure 124) is an end that is farther away from the substrate 101 in the y-direction, and a lower end of a component (e.g., the channel structure 124) is an end that is closer to the substrate 101 in the y-direction when the substrate 101 is positioned in the lowest plane of the 3D memory device 100. The channel plug 129 can include a semiconductor material (e.g., polysilicon). In some implementations, the channel plug 129 functions as a drain of the channel structure 124.

[0034] 1A, each channel structure 124 may extend vertically through the interleaved stack conductive layers 116 and stack dielectric layers 118 of the memory stack 114 and into the fill layer 120. That is, the channel structures 124 may extend beyond the memory stack 114 in the positive y-direction. According to some implementations, the upper end of the memory film 126 is coplanar with the upper end of the semiconductor channel 128, i.e., vertically aligned with one another. In some implementations, the upper ends of the memory film 126 and the semiconductor channel 128 are coplanar with the top surface of the fill layer 120.

[0035] Also, referring to the enlarged side view of the channel structure 124 in FIG. 2, the semiconductor channel 128 can include a doped portion 128a and an undoped portion 128b. In some implementations, at least a portion of the doped portion 128a of the semiconductor channel 128 extends beyond the memory stack 114 in a first direction (e.g., in the positive y direction in FIG. 2). That is, an upper end of the doped portion 128a can be above the interface between the fill layer 120 and the memory stack 114 (i.e., between the bottom surface of the fill layer 120 and the top surface of the memory stack 114). Similarly, an upper end of the memory film 126 can be above the interface between the fill layer 120 and the memory stack 114 as well. In some implementations, the doped portion 128a of the semiconductor channel 128 also extends beyond one of the stack conductive layers 116 in a second direction opposite the first direction (e.g., in the negative y direction in FIG. 2). It is understood that one or more of the stack conductive layers 116 near the fill layer 120 can be source select gate lines 201 (SSG lines; sometimes referred to as bottom select gate (BSG) lines), and the remaining portions of the stack conductive layers 116 can include word lines 203. Also, according to some implementations, the doped portion 128a of the semiconductor channel 128 extends beyond the source select gate line 201 that is closest to the fill layer 120. It is understood that, if the second semiconductor structure 104 of the 3D memory device 100 includes more than one source select gate line 201, the doped portion 128a can extend beyond all of the source select gate lines 201. On the other hand, the doped portion 128a may not extend further to face the word line 203. That is, the lower end of the doped portion 128a is between the source select gate line 201 and the word line 203 in the vertical direction according to some implementations.For example, as shown in FIG. 2, a portion of the doped portion 128a of the semiconductor channel 128 that extends beyond the memory stack 114 may face the fill layer 120, while a remaining portion of the doped portion 128a may face the source select gate line 201.

[0036] In some implementations, the doped portion 128a of the semiconductor channel 128 includes N-type doped polysilicon. The dopant can be any suitable N-type dopant (e.g., phosphorus (P), arsenic (Ar), or antimony (Sb), etc.), which contributes free electrons and increases the electrical conductivity of the intrinsic semiconductor. In some implementations, the doping concentration of the doped portion 128a is about 10 19 cm -3 About 10 21 cm -3 For example, 10 19 cm -3 From 10 21 cm -3 Between (for example, 10 19 cm -3 , 2×10 19 cm -3 , 3×10 19 cm -3 , 4×10 19 cm -3 , 5×10 19 cm -3 , 6×10 19 cm -3 , 7×10 19 cm -3 , 8×10 19 cm -3 , 9×10 19 cm -3 , 10 20 cm -3 , 2×10 20 cm -3 , 3×10 20 cm -3 , 4×10 20 cm -3 , 5×10 20 cm -3 , 6×10 20 cm -3, 7×10 20 cm -3 , 8×10 20 cm -3 , 9×10 20 cm -3 , 10 21 cm -3 , any range bounded by a lower end by any of these values, or any range defined by any two of these values), etc. The doping concentration of the doped portion 128a disclosed herein can significantly reduce the contact resistance between the semiconductor channel 128 and the doped semiconductor layer 122 as compared to an intrinsic semiconductor. It is understood that in some examples, the diffusion of dopants can be confined within the doped portion 128a of the semiconductor channel 128, such that the remaining portion of the semiconductor channel 128 (i.e., the portion facing the word line 203) is an undoped portion 128b that still includes an intrinsic semiconductor (e.g., intrinsic polysilicon, etc.) (i.e., the doping concentration is nominally zero). The doping concentration profile described above can reduce the potential barrier, contact resistance, and sheet resistance in the doped portion 128a of the semiconductor channel 128, which creates an electrical connection for the source of the corresponding NAND memory string, without changing the intrinsic properties of the undoped portion 128b of the semiconductor channel 128 that forms the memory cell of the NAND memory string.

[0037] In some implementations, the second semiconductor structure 104 of the 3D memory device 100 includes a doped semiconductor layer 122. Each channel structure 124 can extend beyond the memory stack 114 in a first direction and can be in contact with the doped semiconductor layer 122. In some embodiments, at least a portion of the doped portion 128a of each semiconductor channel 128 can extend beyond the memory stack 114 in a first direction and can be in contact with the doped semiconductor layer 122 such that the doped semiconductor layer 122 can electrically connect the multiple channel structures 124 through their doped portions 128a of the semiconductor channel 128. For example, the doped semiconductor layer 122 can provide electrical connection between sources (i.e., array common source (ACS)) of an array of NAND memory strings in the same block with or without the fill layer 120 (depending on whether the fill layer 120 is conductive). In other words, the fill layer 120 may not need to include a conductive material (such as, for example, a metal or doped polysilicon) because the doped semiconductor layer 122 alone can electrically connect the sources of multiple NAND memory strings. As a result, material and dimensional constraints on the fill layer 120 may be relaxed.

[0038] As shown in FIG. 1A, in some implementations, the doped semiconductor layer 122 includes two portions: a plate 121 in contact with the fill layer 120, and a plug 123 extending from the plate 121 into the channel structure 124. Also referring to FIG. 2, the doped portion 128a of the semiconductor channel 128 surrounds the plug 123 of the doped semiconductor layer 122 according to some embodiments. As described in detail below with respect to the fabrication of the 3D memory device 100, a portion of the channel hole in which the channel structure 124 is formed can be filled by the plug 123, which replaces a portion of the capping layer 127 in the channel hole, such that the doped portion 128a of the semiconductor channel 128 can surround and be in contact with the plug 123 in the lateral direction. Also, the plug 123 of the doped semiconductor layer 122 can be in contact with the capping layer 127 in the vertical direction. 2, in some implementations, the plug 123 protrudes into the channel structure 124 such that the lower end of the plug 123 (and the upper end of the capping layer 127) is below the interface between the fill layer 120 and the memory stack 114. That is, the capping layer 127 does not extend beyond the memory stack 114 due to the extension of the plug 123, according to some embodiments.

[0039] Similar to the doped portion 128a of the semiconductor channel 128, the plug 123 of the doped semiconductor layer 122 also extends beyond one of the stack conductive layers 116 in a second direction (e.g., the negative y direction in FIGS. 1A and 2). The plug 123 also extends beyond the source select gate line 201 that is closest to the fill layer 120 according to some implementations. It is understood that if the second semiconductor structure 104 of the 3D memory device 100 includes more than one source select gate line 201, the plug 123 can extend beyond all of the source select gate lines 201. In some embodiments, the plug 123 is aligned with the doped portion 128a of the semiconductor channel 128 in the vertical direction. That is, the upper end of the plug 123 and the upper end of the doped portion 128a of the semiconductor channel 128 can be coplanar with one another, and the lower end of the plug 123 and the lower end of the doped portion 128a of the semiconductor channel 128 can be coplanar with one another as well. As described in detail below with respect to the fabrication of the 3D memory device 100, the plug 123 can act as a doping source for forming the doped portion 128a of the semiconductor channel 128, such that only that portion of the semiconductor channel 128 in contact with the plug 123 is doped by the plug 123 to form the doped portion 128a of the semiconductor channel 128. It is understood that in some examples, a portion of the semiconductor channel 128 can be doped prior to the formation of the plug 123, such that the lower end of the plug 123 and the lower end of the doped portion 128a of the semiconductor channel 128 do not have to be coplanar with one another.

[0040] 1A, the plate 121 of the doped semiconductor layer 122 overlies and is in contact with the fill layer 120 and the memory film 126 of the channel structure 124, according to some embodiments. In other words, the memory film 126 can extend beyond the memory stack 114 in a first direction (e.g., the positive y-direction) and is in contact with the plate 121 of the doped semiconductor layer 122, and the fill layer 120 can be formed between the memory stack 114 and the plate 121 of the doped semiconductor layer 122. By extending laterally over the multiple channel structures 124, the plate 121 can connect multiple plugs 123, each of the multiple plugs 123 protruding into a respective channel structure 124.

[0041] As described in detail below, formation of the memory stack 114, as well as formation of the doped portion 128a of the semiconductor channel 128 and the doped semiconductor layer 122, can occur on the opposite side of the fill layer 120, thereby avoiding any deposition or etching processes through openings extending through the memory stack 114, thereby reducing fabrication complexity and cost and improving yield and vertical scalability.

[0042] Like the doped portion 128a of the semiconductor channel 128, in some implementations the doped semiconductor layer 122 (including the plate 121 and the plug 123) also comprises N-type doped polysilicon. The dopant can be any suitable N-type dopant (e.g., P, Ar, Sb, etc.), which contributes free electrons and increases the conductivity of the intrinsic semiconductor. Like the doped portion 128a of the semiconductor channel 128, in some implementations the doping concentration of the doped semiconductor layer 122 is about 10 19 cm -3 About 10 21 cm -3 For example, 10 19 cm -3 From 1021 cm -3 Between (for example, 10 19 cm -3 , 2×10 19 cm -3 , 3×10 19 cm -3 , 4×10 19 cm -3 , 5×10 19 cm -3 , 6×10 19 cm -3 , 7×10 19 cm -3 , 8×10 19 cm -3 , 9×10 19 cm -3 , 10 20 cm -3 , 2×10 20 cm -3 , 3×10 20 cm -3 , 4×10 20 cm -3 , 5×10 20 cm -3 , 6×10 20 cm -3 , 7×10 20 cm -3 , 8×10 20 cm -3 , 9×10 20 cm -3 , 10 21 cm -3, any range bounded by a lower end by any of these values, or any range defined by any two of these values), etc. The doping concentration of the doped semiconductor layer 122 disclosed herein can significantly reduce the contact resistance between the semiconductor channel 128 and the doped semiconductor channel 122 and the sheet resistance of the doped semiconductor layer 122 compared to an intrinsic semiconductor. As described in detail below, in some implementations, the doped portion 128a of the semiconductor channel 128 and the doped semiconductor layer 122 have the same material (e.g., N-type doped polysilicon) with the same dopant and have a continuous doping profile due to the same local activation process performed thereon. It is therefore understood that the interface and boundary between the doped portion 128a of the semiconductor channel 128 and the plug 123 of the doped semiconductor layer 122 can be indistinguishable and therefore cannot be discerned within the 3D memory device 100.

[0043] By doping and contacting the semiconductor channel 128 and the doped semiconductor layer 122, the contact resistance between the NAND memory strings (i.e., in the ACS of the NAND memory strings in the same block) can be reduced, thereby improving the electrical performance of the 3D memory device 100. As shown in FIG. 1A and FIG. 2, by extending the plug 123 into the channel structure 124, the doped portion 128a of the semiconductor channel 128 can surround the plug 123 of the doped semiconductor layer 122, thereby increasing the contact area between the semiconductor channel 128 and the doped semiconductor layer 122, which further reduces the contact resistance between them. The plug 123 of the N-type doped semiconductor layer 122 (which is surrounded by the doped portion 128a of the semiconductor channel 128) can enable gate-induced drain leakage (GIDL) assisted body biasing for erase operation for the 3D memory device 100. The GIDL around the source select gate line 201 can generate hole current (i.e., source leakage current) from the source of the corresponding NAND memory string into the semiconductor channel 128 to raise the body potential for the erase operation. That is, the plug 123 of the N-type doped semiconductor layer 122 is configured to generate GIDL-assisted body biasing when performing an erase operation, according to some implementations. In some implementations, the GIDL effect can be further enhanced by also doping a portion of the semiconductor channel 128 facing the source select gate line 201.

[0044] As shown in FIG. 1A, the second semiconductor structure 104 of the 3D memory device 100 can further include an insulating structure 130 that extends vertically through the interleaved stack conductive layers 116 and stack dielectric layers 118 of the memory stack 114. Unlike the channel structure 124 that extends further into the fill layer 120, the insulating structure 130 stops at the bottom surface of the fill layer 120 according to some implementations, i.e., does not extend vertically into the fill layer 120. That is, the top surface of the insulating structure 130 can be flush with the bottom surface of the fill layer 120. Also, each insulating structure 130 can extend laterally to separate the separate channel structures 124 into multiple blocks. That is, the memory stack 114 can be divided into multiple memory blocks by the insulating structure 130, such that the array of channel structures 124 can be separated into respective memory blocks. Unlike the slit structures in existing 3D NAND memory devices (which include front-side ACS contacts), the insulating structures 130, according to some implementations, do not include any contacts therein (i.e., do not function as source contacts) and therefore do not introduce parasitic capacitance and leakage current through the stack conductive layer 116. In some implementations, each insulating structure 130 includes an opening (e.g., a slit) filled with one or more dielectric materials, including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. In one example, each insulating structure 130 can be filled with silicon oxide. It is understood that in some examples (as shown in FIG. 1A ), the insulating structures 130 can be partially filled with a non-dielectric material (e.g., polysilicon, etc.) to adjust the mechanical properties (e.g., hardness and / or stress) of the insulating structures 130.

[0045] Moreover, as described in detail below, because the openings for forming the insulating structures 130 are not used to form the doped semiconductor layer 122 and the doped portions 128a of the semiconductor channel 128, an increase in the aspect ratio of the openings (e.g., greater than 50) as the number of interleaved stacked conductive layers 116 and stacked dielectric layers 118 increases does not affect the formation of the doped semiconductor layer 122 and the doped portions 128a of the semiconductor channel 128.

[0046] Instead of a front-side source contact, the 3D memory device 100 may include one or more back-side source contacts 132 above and in contact with the doped semiconductor layer 122, as shown in FIG. 1A. The source contacts 132 and the memory stack 114 (and the insulating structure 130 therethrough) may be disposed on opposite sides of the fill layer 120 and may thus be viewed as “back-side” source contacts. In some implementations, the source contacts 132 are electrically connected to the semiconductor channel 128 of the channel structure 124 through the doped semiconductor layer 122. The source contacts 132 may include any suitable type of contact. In some implementations, the source contacts 132 include VIA contacts. In some implementations, the source contacts 132 include laterally extending wall-shaped contacts. The source contact 132 may include one or more conductive layers, such as a metal layer (e.g., W, Co, Cu, or Al) or a silicide layer, surrounded by an adhesive layer (e.g., titanium nitride (TiN)).

[0047] As shown in FIG. 1A, the 3D memory device 100 can further include a BEOL interconnect layer 133 electrically connected to the source contact 132 above the source contact 132 for pad-out (e.g., to transfer electrical signals between the 3D memory device 100 and an external circuit). In some implementations, the interconnect layer 133 includes one or more ILD layers 134 over the doped semiconductor layer 122 and a redistribution layer 136 over the ILD layer 134. The upper end of the source contact 132 is flush with the top surface of the ILD layer 134 and the bottom surface of the redistribution layer 136, and the source contact 132 extends vertically through the ILD layer 134 to contact the doped semiconductor layer 122 according to some implementations. The ILD layer 134 in the interconnect layer 133 can include a dielectric material, including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof. The redistribution layer 136 in the interconnect layer 133 can include a conductive material, including, but not limited to, W, Co, Cu, Al, silicide, or any combination thereof. In some implementations, the interconnect layer 133 further includes a passivation layer 138 as an outermost layer for passivation and protection of the 3D memory device 100. A portion of the redistribution layer 136 can be exposed from the passivation layer 138 as a contact pad 140. That is, the interconnect layer 133 of the 3D memory device 100 can also include a contact pad 140 for wire bonding and / or bonding with an interposer. As described below with respect to the fabrication process, in some implementations, the source contact 132 and the redistribution layer 136 can be formed by the same process and have the same material (e.g., Al). Thus, the source contact 132 can be seen as part of the BEOL interconnect layer 133 in some examples as well.

[0048] In some implementations, the second semiconductor structure 104 of the 3D memory device 100 further includes contacts 142 and 144 through the doped semiconductor layer 122 and the fill layer 120. Since the doped semiconductor layer 122 can include polysilicon, the contacts 142 and 144 are through silicon contacts (TSCs) according to some implementations. In some implementations, the contact 142 extends through the doped semiconductor layer 122, the fill layer 120, and the ILD layer 134 and contacts the redistribution layer 136 such that the doped semiconductor layer 122 is electrically connected to the contact 142 through the source contact 132 and the redistribution layer 136 of the interconnect layer 133. In some implementations, the contact 144 extends through the doped semiconductor layer 122, the fill layer 120, and the ILD layer 134 and contacts the contact pad 140. Contacts 142 and 144 can each include one or more conductive layers, such as a metal layer (e.g., W, Co, Cu, or Al) or a silicide layer surrounded by an adhesive layer (e.g., tin). In some implementations, at least contact 144 further includes a spacer (e.g., a dielectric layer) to electrically isolate contact 144 from doped semiconductor layer 122 and fill layer 120.

[0049] In some implementations, the 3D memory device 100 further includes peripheral contacts 146 and 148 each extending vertically outside the memory stack 114. Each peripheral contact 146 or 148 can have a depth greater than the depth of the memory stack 114 and extend vertically from the bonding layer 112 to the fill layer 120 in a peripheral region outside the memory stack 114. In some implementations, the peripheral contact 146 is below and in contact with the contact 142 such that the doped semiconductor layer 122 is electrically connected to the peripheral circuitry 108 in the first semiconductor structure 102 through at least the source contact 132, the redistribution layer 136, the contact 142, and the peripheral contact 146. In some implementations, the peripheral contacts 148 underlie and are in contact with the contacts 144 such that the peripheral circuitry 108 in the first semiconductor structure 102 is electrically connected to the pad-out contact pads 140 through at least the contacts 144 and the peripheral contacts 148. The peripheral contacts 146 and 148 can each include one or more conductive layers, such as a metal layer (e.g., W, Co, Cu, or Al) or a silicide layer surrounded by an adhesive layer (e.g., TiN).

[0050] As shown in FIG. 1A, the 3D memory device 100 also includes various local contacts (also known as “C1”) as part of the interconnect structure, which directly contact structures in the memory stack 114. In some implementations, the local contacts include channel local contacts 150, each of which underlies and contacts a lower end of a respective channel structure 124. Each channel local contact 150 can be electrically connected to a bit line contact (not shown) for bit line fan-out. In some implementations, the local contacts further include word line local contacts 152, each of which underlies and contacts a respective stack conductive layer 116 (including word lines) in the staircase structure of the memory stack 114 for word line fan-out. The local contacts (e.g., channel local contact 150 and word line local contact 152, etc.) can be electrically connected to the peripheral circuitry 108 of the first semiconductor structure 102 through at least bonding layers 112 and 110. The local contacts (e.g., channel local contact 150 and word line local contact 152, etc.) can each include one or more conductive layers, such as a metal layer (e.g., W, Co, Cu, or Al) or a silicide layer, surrounded by an adhesive layer (e.g., TiN).

[0051] Although an exemplary 3D memory device 100 is shown in FIG. 1A , it is understood that by varying the relative positions of the first and second semiconductor structures 102 and 104, the use of backside source contacts 132 or known front-side source contacts (not shown), and / or pad-out locations (e.g., through the first semiconductor structure 102 and / or the second semiconductor structure 104), any other suitable architecture of a 3D memory device may be applicable in the present disclosure without further elaboration.

[0052] 1B illustrates a cross-sectional side view of another exemplary 3D memory device 160 according to some embodiments of the present disclosure. The 3D memory device 160 is similar to the 3D memory device 100, except for the different structure of the upper ends of the doped semiconductor layer 122 and the capping layer 127. It is understood that other identical structural details of both the 3D memory devices 160 and 100 are not repeated for ease of explanation.

[0053] 1B, the doped semiconductor layer 122 does not include any plugs (e.g., plugs 123 in FIG. 1A) that extend into the channel structure 124, according to some embodiments. That is, in some embodiments, the entire doped semiconductor layer 122 can be viewed as a plate 121. Without the plugs 123 that extend into the channel structure 124, the capping layer 127 of the channel structure 124 can completely fill the channel hole and thus extend beyond the memory stack 114 in a first direction (e.g., the positive y-direction in FIG. 1B) and contact the doped semiconductor layer 122. That is, the upper ends of the memory film 126, the semiconductor channel 128, and the capping layer 127 can be coplanar with each other and in contact with the doped semiconductor layer 122. As a result, in some embodiments, the channel structure 124 extends beyond the memory stack 114 in a first direction (e.g., the positive y-direction in FIG. 1B) and is in contact with the doped semiconductor layer 122.

[0054] FIG. 7 illustrates a block diagram of an example system 700 having a 3D memory device according to some aspects of the disclosure. The system 700 can be a mobile phone, a desktop computer, a laptop computer, a tablet, a vehicle computer, a gaming console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having storage therein. As shown in FIG. 7, the system 700 can include a host 708 and a memory system 702, the memory system 702 having one or more 3D memory devices 704 and a memory controller 706. The host 708 can be a processor (e.g., a central processing unit (CPU) or the like) of the electronic device, or a system-on-chip (SoC) (e.g., an application processor (AP) or the like). The host 708 can be configured to transmit data to or receive data from the 3D memory device 704.

[0055] The 3D memory devices 704 can be any 3D memory device disclosed herein (e.g., such as the 3D memory devices 100 and 160 shown in FIG. 1A and FIG. 1B). In some implementations, each 3D memory device 704 includes a NAND flash memory. Consistent with the scope of the present disclosure, the semiconductor channel of the 3D memory devices 704 can be partially doped, such that a portion of the semiconductor channel forming a source contact is highly doped to lower the potential barrier while leaving another portion of the semiconductor channel remaining undoped or forming a lightly doped memory cell. One end of each channel structure of the 3D memory devices 704 can be open from the backside to expose a doped portion of the respective semiconductor channel. The 3D memory devices 704 can further include a doped semiconductor layer electrically connecting the exposed doped portion of the semiconductor channel to further reduce contact resistance and sheet resistance. As a result, the electrical performance of the 3D memory device 704 can be improved, which in turn improves the performance of the memory system 702 and the system 700, for example achieving higher operating speeds.

[0056] The memory controller 706 is coupled to the 3D memory device 704 and the host 708 and, according to some implementations, is configured to control the 3D memory device 704. The memory controller 706 can manage data stored in the 3D memory device 704 and communicate with the host 708. In some implementations, the memory controller 706 is designed to operate in a low duty cycle environment, such as a Secure Digital (SD) card, a Compact Flash (CF) card, a Universal Serial Bus (USB) flash drive, or other media for use in electronic devices (e.g., personal computers, digital cameras, mobile phones, etc.). In some implementations, the memory controller 706 is designed to operate in a high duty cycle environment SSD or embedded multimedia card (eMMC) used as data storage and enterprise storage arrays for mobile devices (e.g., smartphones, tablets, laptop computers, etc.). The memory controller 706 can be configured to control the operations of the 3D memory device 704 (e.g., read operations, erase operations, and program operations, etc.). The memory controller 706 can also be configured to manage various functions related to data stored or to be stored in the 3D memory device 704 (including, but not limited to, bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc.). In some implementations, the memory controller 706 is further configured to process error correction codes (ECC) on data read from or written to the 3D memory device 704. Any other suitable functions can be similarly performed by the memory controller 706, for example, forming the 3D memory device 704. The memory controller 706 can communicate with an external device (e.g., a host 708) according to a particular communication protocol.For example, the memory controller 706 may communicate with external devices through at least one of a variety of interface protocols (e.g., a USB protocol, an MMC protocol, a Peripheral Component Interconnect (PCI) protocol, a PCI-express (PCI-E) protocol, an Advanced Technology Attachment (ATA) protocol, a Serial ATA protocol, a Parallel ATA protocol, a Small Computer Small Interface (SCSI) protocol, an Enhanced Small Disk Interface (ESDI) protocol, an Integrated Drive Electronics (IDE) protocol, a Firewire protocol, etc.).

[0057] The memory controller 706 and the one or more 3D memory devices 704 can be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Storage (UFS) package or an eMMC package, etc.). That is, the memory system 702 can be implemented and packaged into different types of end electronics products. In one example as shown in FIG. 8A, the memory controller 706 and the single 3D memory device 704 can be integrated into a memory card 802. The memory card 802 can include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 802 can further include a memory card connector 804 that electrically couples the memory card 802 with a host (e.g., the host 708 of FIG. 7). In another example, as shown in FIG. 8B, the memory controller 706 and the multiple 3D memory devices 704 can be integrated into an SSD 806. The SSD 806 can further include an SSD connector 808 that electrically couples the SSD 806 with a host (e.g., the host 708 of FIG. 7). In some implementations, the storage capacity and / or operating speed of the SSD 806 is greater than that of the memory card 802.

[0058] 3A-3O illustrate a fabrication process for forming an exemplary 3D memory device according to some implementations of the present disclosure. FIG. 5 illustrates a flowchart of a method 500 for forming an exemplary 3D memory device according to some implementations of the present disclosure. An example of a 3D memory device illustrated in FIGS. 3A-3O and 5 includes the 3D memory device 100 illustrated in FIG. 1A. FIGS. 3A-3O and 5 will be described together. It is understood that the operations illustrated in method 500 are not exhaustive, and that other operations can be performed before, after, or during any of the illustrated operations as well. Furthermore, some of the operations can be performed simultaneously or in a different order than that illustrated in FIG. 5.

[0059] Referring to FIG. 5, the method 500 begins at operation 502, where a peripheral circuit is formed on a first substrate. The first substrate can be a silicon substrate. As illustrated in FIG. 3G, a plurality of transistors are formed on a silicon substrate 350 using a plurality of processes, including, but not limited to, photolithography, etching, thin film deposition, thermal expansion, implantation, chemical mechanical polishing (CMP), and any other suitable processes. In some implementations, doped regions (not shown) are formed in the silicon substrate 350 by ion implantation and / or thermal diffusion, which function, for example, as source and / or drain regions of the transistors. In some implementations, isolation regions (e.g., STI) are also formed in the silicon substrate 350 by wet and / or dry etching and thin film deposition. The transistors can form a peripheral circuit 352 on the silicon substrate 350.

[0060] 3G, a bonding layer 348 is formed over the peripheral circuitry 352. The bonding layer 348 includes a bonding contact that is electrically connected to the peripheral circuitry 352. To form the bonding layer 348, an ILD layer is deposited using one or more thin film deposition processes, such as, for example, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof; a bonding contact through the ILD layer is formed using a wet etch and / or a dry etch (e.g., reactive ion etching (RIE)), followed by one or more thin film deposition processes, such as, for example, ALD, CVD, PVD, any other suitable process, or any combination thereof.

[0061] 5, the method 500 proceeds to operation 504 where a fill layer is formed over a second substrate and a stack structure is formed over the fill layer. The fill layer and stack structure may be formed on a front side of the second substrate on which semiconductor devices may be formed. The second substrate may be a silicon substrate. It is understood that because the second substrate will be removed from the final product, the second substrate can be a part of a dummy wafer (e.g., a carrier substrate) made of any suitable material (e.g., glass, sapphire, plastic, silicon, etc., to name a few) to reduce the cost of the second substrate. In some implementations, the substrate is a carrier substrate. In some implementations, the fill layer includes polysilicon, a high-k dielectric, or a metal, and the stack structure includes a dielectric stack having alternating stack dielectric layers and stack sacrificial layers. It is understood that in some examples, the stack structure can include a memory stack having alternating stack dielectric layers (e.g., silicon oxide layers) and stack conductive layers (e.g., polysilicon layers).

[0062] To better control the gauging and surface planarity of various structures to be formed on the second substrate, various stop layers can be formed between the second substrate and the fill layer. In some implementations, a first stop layer and a second stop layer are sequentially formed between the second substrate and the fill layer. The first stop layer can include silicon oxide or silicon nitride, and the second stop layer can include silicon oxide or polysilicon. In some implementations, a third stop layer (e.g., a silicon nitride layer or a polysilicon layer, etc.) is formed between the second stop layer and the fill layer. In some implementations, a single stop layer (e.g., a silicon oxide layer or a high-k dielectric layer, etc.) is formed between the second substrate and the fill layer.

[0063] As illustrated in FIG. 3A, a first stop layer 303 is formed above the carrier substrate 302, a second stop layer 304 is formed on the first stop layer 303, and a fill layer 306 is formed on the second stop layer 304. The fill layer 306 can include polysilicon, high-k dielectric, or metal. The second stop layer 304 can act as an etch stop layer when etching a channel hole from the front side, and thus can include any suitable material having high etch selectivity (e.g., greater than about 5) with respect to the material (e.g., silicon oxide or polysilicon, etc.) directly on the second stop layer 304. The first stop layer 303 can act as a CMP / etch stop layer when removing the carrier substrate 302 from the back side, and thus can include any suitable material (e.g., silicon nitride or silicon oxide, etc.) other than the material of the carrier substrate 302. It is understood that in some examples, a pad oxide layer (e.g., a silicon oxide layer) can be formed between the carrier substrate 302 and the first stop layer 303 to relieve stress between the different layers and avoid delamination.

[0064] As shown in FIG. 3A, a stack of a silicon oxide layer (pad oxide layer), a silicon nitride layer (first stop layer 303), and a silicon oxide layer (second stop layer 304) can be sequentially formed on a carrier substrate 302 using one or more thin film deposition processes, including but not limited to CVD, PVD, ALD, or any combination thereof. In some implementations, a fill layer 306 is formed by depositing polysilicon or any other suitable material (e.g., high-k dielectric or metal, etc.) on the second stop layer 304 using one or more thin film deposition processes, including but not limited to CVD, PVD, ALD, or any combination thereof. For ease of explanation, the combination of stop layers shown in FIG. 3A is used throughout this disclosure to describe the fabrication process. However, it is understood that any other suitable combination of stop layers can be used in other examples as well. In an example not shown, a single oxide layer or high-k dielectric layer (as first and second stop layers 303 and 304) can be formed on the carrier substrate 302 using one or more thin film deposition processes, including but not limited to CVD, PVD, ALD, or any combination thereof.

[0065] As illustrated in FIG. 3B , a dielectric stack 308 including a plurality of pairs of a first dielectric layer (referred to herein as “stack sacrificial layers” 312) and a second dielectric layer (referred to herein as “stack dielectric layers” 310; together referred to herein as “dielectric layer pairs”) is formed on the fill layer 306. The dielectric stack 308 includes alternating stack sacrificial layers 312 and stack dielectric layers 310 according to some implementations. The stack dielectric layers 310 and stack sacrificial layers 312 can be formed alternately on the fill layer 306 above the carrier substrate 302 to form the dielectric stack 308. In some implementations, each stack dielectric layer 310 includes a layer of silicon oxide and each stack sacrificial layer 312 includes a layer of silicon nitride. The dielectric stack 308 can be formed by one or more thin film deposition processes, including, but not limited to, CVD, PVD, ALD, or any combination thereof. As shown in FIG. 3B, a staircase structure can be formed on the edge of the dielectric stack 308. The staircase structure can be formed by performing multiple so-called "trim etch" cycles on the dielectric layer pairs of the dielectric stack 308 towards the carrier substrate 302. Due to the repeated trim etch cycles applied to the dielectric layer pairs of the dielectric stack 308, the dielectric stack 308 can have one or more sloping edges and a top dielectric layer pair that is shorter than a bottom one, as shown in FIG. 3B.

[0066] 5, the method 500 proceeds to operation 506, where a channel structure extending vertically through the dielectric stack and the fill layer is formed. The channel structure can include a memory film and a semiconductor channel. In some implementations, to form the channel structure, a channel hole extending vertically through the dielectric stack and the fill layer is formed, which stops at a second stop layer, and a memory film, a semiconductor channel, and a capping layer are sequentially formed in the channel hole.

[0067] As illustrated in FIG. 3B, each channel hole is an opening that extends vertically through the dielectric stack 308 and the fill layer 306, which stops at the second stop layer 304. In some implementations, multiple openings are formed, with each opening being a location for growing an individual channel structure 314 in a later process. In some implementations, the fabrication process for forming the channel holes of the channel structures 314 includes wet etching and / or dry etching (e.g., deep RIE (DRIE) etc.). The etching of the channel holes continues until it is stopped by the second stop layer 304 (e.g., silicon oxide or polysilicon etc.) according to some implementations. In some implementations, the etching conditions (e.g., etch rate and time etc.) can be controlled to ensure that each channel hole reaches and stops at the second stop layer 304 to minimize gouging variation between the channel holes and the channel structures 314 formed therein. It is understood that depending on the particular etch selectivity, one or more channel holes may extend into the second stop layer 304 only to a small extent and still be viewed in this disclosure as being stopped by the second stop layer 304.

[0068] As shown in FIG. 3B, a memory film including a blocking layer 317, a storage layer 316, and a tunneling layer 315, and a semiconductor channel 318 are sequentially formed in this order along the sidewall and bottom surface of the channel hole. In some implementations, the blocking layer 317, the storage layer 316, and the tunneling layer 315 are first deposited in this order along the sidewall and bottom surface of the channel hole using one or more thin film deposition processes (e.g., ALD, CVD, PVD, any other suitable process, or any combination thereof, etc.) to form a memory film. The semiconductor channel 318 can then be formed by depositing a semiconductor material (e.g., polysilicon (e.g., undoped polysilicon)) on the tunneling layer 315 using one or more thin film deposition processes (e.g., ALD, CVD, PVD, any other suitable process, or any combination thereof, etc.). In some implementations, a first silicon oxide layer, a silicon nitride layer, a second silicon oxide layer, and a polysilicon layer (a "SONO" structure) are deposited sequentially to form the blocking layer 317, the storage layer 316, and the tunneling layer 315, as well as the semiconductor channel 318 of the memory film.

[0069] As illustrated in FIG. 3B , a capping layer 319 is formed in the channel hole and over the semiconductor channel 318 to completely or partially fill the channel hole (e.g., with or without an air gap). The capping layer 319 can be formed by depositing a dielectric material (e.g., silicon oxide, etc.) using one or more thin film deposition processes (e.g., ALD, CVD, PVD, any other suitable process, or any combination thereof, etc.). A channel plug can then be formed in the upper portion of the channel hole. In some implementations, portions of the memory film, the semiconductor channel 318, and the capping layer 319 over the top surface of the dielectric stack 308 are removed and planarized by CMP, wet etching, and / or dry etching. A recess can then be formed in the upper portion of the channel hole by wet etching and / or dry etching the semiconductor channel 318 and the capping layer 319 in the upper portion of the channel hole. A channel plug can then be formed by depositing a semiconductor material (such as, for example, polysilicon) into the recess by one or more thin film deposition processes (such as, for example, CVD, PVD, ALD, or any combination thereof), such that a channel structure 314 is formed through the dielectric stack 308 and the fill layer 306, which stops at the second stop layer 304, according to some implementations.

[0070] As shown in FIG. 3C, the slits 320 are openings that extend vertically through the dielectric stack 308 and stop at the fill layer 306. In some implementations, the fabrication process for forming the slits 320 includes wet etching and / or dry etching (e.g., DRIE, etc.). A gate exchange can then be performed through the slits 320 to replace the dielectric stack 308 with a memory stack 330 (shown in FIG. 3E).

[0071] As illustrated in FIG. 3D , lateral recesses 322 are first formed by removing the stack sacrificial layers 312 (shown in FIG. 3C ) through the slits 320. In some implementations, the stack sacrificial layers 312 are removed by applying an etchant through the slits 320 to generate lateral recesses 322 interleaved between the stack dielectric layers 310. The etchant may include any suitable etchant that selectively etches the stack sacrificial layers 312 relative to the stack dielectric layers 310.

[0072] As shown in FIG. 3E, a stack conductive layer 328 (including a gate electrode and an adhesive layer) is deposited through the slit 320 into the lateral recess 322 (shown in FIG. 3D). In some implementations, a gate dielectric layer 332 is deposited into the lateral recess 322 before the stack conductive layer 328, such that the stack conductive layer 328 is deposited on the gate dielectric layer 332. The stack conductive layer 328 (e.g., a metal layer, etc.) can be deposited using one or more thin film deposition processes (e.g., ALD, CVD, PVD, any other suitable process, or any combination thereof, etc.). In some implementations, a gate dielectric layer 332 (e.g., a high-k dielectric layer, etc.) is similarly formed along the sidewalls and bottom of the slit 320. Thereby, a memory stack 330 including an interleaved stack conductive layer 328 and a stack dielectric layer 310 is formed, which according to some implementations replaces the dielectric stack 308 (shown in FIG. 3D).

[0073] As illustrated in FIG. 3E, an insulating structure 336 is formed that extends vertically through the memory stack 330 and stops at the top surface of the fill layer 306. The insulating structure 336 is formed by depositing one or more dielectric materials (e.g., silicon oxide, etc.) into the slits 320 and can fully or partially fill the slits 320 (e.g., with no air gap or with air gap) using one or more thin film deposition processes (e.g., ALD, CVD, PVD, any other suitable process, or any combination thereof, etc.). In some implementations, the insulating structure 336 includes a gate dielectric layer 332 (e.g., including a high-k dielectric) and a dielectric capping layer 334 (e.g., including silicon oxide). In some embodiments, the dielectric capping layer 334 can partially fill the slits 320, and the polysilicon core layer 335 can fill the remaining space of the slits 320 as part of the insulating structure 336 and adjust the mechanical properties (e.g., hardness or stress, etc.) of the insulating structure 336.

[0074] As shown in FIG. 3F, after the formation of the insulating structure 336, the local contacts (including the channel local contact 344 and the word line local contact 342, as well as the peripheral contacts 338 and 340) are formed. A local dielectric layer can be formed on the memory stack 330 by depositing a dielectric material (such as, for example, silicon oxide or silicon nitride) on the memory stack 330 using one or more thin film deposition processes (such as, for example, CVD, PVD, ALD, or any combination thereof). The channel local contact 344, the word line local contact 342, and the peripheral contacts 338 and 340 can be formed by etching contact openings through the local dielectric layer (and any other ILD layers) using wet and / or dry etching (such as, for example, RIE), followed by filling the contact openings with a conductive material using one or more thin film deposition processes (such as, for example, ALD, CVD, PVD, any other suitable process, or any combination thereof).

[0075] 3F, a bonding layer 346 is formed over the channel local contact 344, the word line local contact 342, and the peripheral contacts 338 and 340. The bonding layer 346 includes a bonding contact electrically connected to the channel local contact 344, the word line local contact 342, and the peripheral contacts 338 and 340. To form the bonding layer 346, an ILD layer is deposited using one or more thin film deposition processes (such as, for example, CVD, PVD, ALD, or any combination thereof), and a bonding contact is formed through the ILD layer using wet etching and / or dry etching (such as, for example, RIE), followed by one or more thin film deposition processes (such as, for example, ALD, CVD, PVD, any other suitable process, or any combination thereof).

[0076] The method 500 proceeds to operation 508, as illustrated in FIG. 5, where the first substrate and the second substrate are bonded in a face-to-face manner such that the memory stack is above the peripheral circuitry. The bonding can include hybrid bonding. As illustrated in FIG. 3G, the carrier substrate 302 and the components formed thereon (e.g., the memory stack 330 and the channel structure 314 formed therethrough) are flipped upside down. According to some implementations, the downward-facing bonding layer 346 is bonded with the upward-facing bonding layer 348, i.e., bonded in a face-to-face manner, thereby forming a bonding interface 354 between the carrier substrate 302 and the silicon substrate 350. In some implementations, a treatment process (e.g., plasma treatment, wet treatment, and / or thermal treatment) is applied to the bonding surface prior to bonding. After bonding, the bonding contacts in bonding layer 346 and the bonding contacts in bonding layer 348 are aligned and in contact with one another such that memory stack 330 and the channel structure 314 formed therethrough can be electrically connected to and is above peripheral circuitry 352.

[0077] The method 500 proceeds to operation 510, as illustrated in FIG. 5, where a portion of the channel structure extending beyond the second substrate and the fill layer is sequentially removed to expose a portion of the semiconductor channel. The removal can be performed from the backside of the second substrate. As illustrated in FIG. 6, in some implementations, at 602, the second substrate is removed, stopping at the first stop layer, to sequentially remove the second substrate and a portion of the channel structure; at 604, the first stop layer is removed, stopping at the second stop layer; and at 606, the second stop layer and a portion of the channel structure are removed, stopping at the fill layer. In some implementations, the removed portion of the channel structure extends into the second stop layer, and the second stop layer and the portion of the channel structure extending into the second stop layer are polished. As shown in FIG. 6, in some embodiments, at 608, a portion of the capping layer of the channel structure is etched back to form a recess surrounded by a portion of the semiconductor channel.

[0078] As illustrated in FIG. 3H, the carrier substrate 302 (and the pad oxide layer between the carrier substrate 302 and the first stop layer 303, illustrated in FIG. 3G) is completely removed from the backside until stopped by the first stop layer 303 (e.g., a silicon nitride layer). The carrier substrate 302 can be completely removed using CMP, grinding, dry etching, and / or wet etching. In some implementations, the carrier substrate 302 is peeled off. In some implementations where the carrier substrate 302 comprises silicon and the first stop layer 303 comprises silicon nitride, the carrier substrate 302 is removed using silicon CMP, which can be automatically stopped when the first stop layer 303 having a material other than silicon is reached (i.e., acting as a backside CMP stop layer). In some implementations, the carrier substrate 302 (silicon substrate) is removed using a wet etch with tetramethyl ammonium hydroxide (TMAH), which automatically stops when it reaches the first stop layer 303 having a material other than silicon (i.e., acts as a backside etch stop layer). The first stop layer 303 can ensure complete removal of the carrier substrate 302 without worrying about thickness uniformity after thinning.

[0079] As shown in FIG. 3I, the first and second stop layers 303 and 304 (shown in FIG. 3H) can then be similarly completely removed using a wet etch with a suitable etchant (e.g., phosphoric acid and hydrofluoric acid, etc.) until stopped by the fill layer 306 having a different material (e.g., polysilicon) than the second stop layer 304. As shown in FIG. 3I, the portion of the channel structure 314 that extends beyond the fill layer 306 is removed such that the upper end of the channel structure 314 is flush with the top surface of the fill layer 306. In some embodiments in which a portion of the channel structure 314 extends into the second stop layer 304, the second stop layer 304 and the portion of the channel structure 314 that extends into the second stop layer 304 are both removed by polishing (e.g., CMP, etc.) that stops at the fill layer 306. It is understood that if the channel structure 314 does not extend beyond the fill layer 306 into the second stop layer 304, removal of the upper end of the channel structure 314 may be skipped.

[0080] As illustrated in FIG. 3J, a portion of the capping layer 319 is removed to form a recess 321 surrounded by an upper portion of the semiconductor channel 318. For example, a portion of the capping layer 319 of the channel structure 314 can be etched back to form the recess 321, for example, using dry etching and / or wet etching. In some examples, when the upper end of the capping layer 319 is still covered by the semiconductor channel 318, a portion of the semiconductor channel 318 can be etched first to expose the capping layer 319. The etching of the capping layer 319 can be controlled by controlling the etching time and / or the etching rate such that the etching does not continue beyond the source select gate line (e.g., one or more stack conductive layers 328 closest to the fill layer 306). The formation of the recess 321 can expose a portion of the semiconductor channel 318 surrounding the recess 321. In some implementations, the upper portion of the semiconductor channel 318 exposed by the recess 321 is doped to increase its conductivity. For example, a tilted ion implantation process can be performed to dope the upper portion of the semiconductor channel 318 (e.g., comprising polysilicon) exposed by the recess 321 with any suitable dopant (e.g., an N-type dopant such as P, As, or Sb, etc.) to a desired doping concentration.

[0081] Removal of a portion of the channel structure 314 from the backside is much less difficult and has a higher production yield compared to known solutions using frontside wet etching via an opening (e.g., slit 320 in FIG. 3D) through a dielectric stack 308 / memory stack 330 with a high aspect ratio (e.g., greater than 50). By avoiding the problems introduced by the high aspect ratio of the slit 320, fabrication complexity and cost can be reduced and yield can be increased. Also, vertical scalability (e.g., increasing the level of the dielectric stack 308 / memory stack 330) can be improved as well.

[0082] The method 500 proceeds to operation 512, as illustrated in Figure 5, where a doped semiconductor layer is formed in contact with the exposed portion of the semiconductor channel. In some implementations, the dopant includes an N-type dopant. As illustrated in Figure 6, in some implementations, a layer of polysilicon is deposited into the recess and over the fill layer at 610; the deposited layer of polysilicon is doped at 612 to form the doped semiconductor layer.

[0083] As illustrated in FIG. 3K, a doped semiconductor layer 360 is formed in the recess 321 (shown in FIG. 3J) that is surrounded by and in contact with (is surrounded by) the exposed portion of the semiconductor channel 318 and the outside of the recess 321 above the fill layer 306. In some implementations, to form the doped semiconductor layer 360, a semiconductor layer (e.g., polysilicon) is deposited in the recess 321 in contact with the exposed portion of the semiconductor channel 318 and the capping layer 319, and outside of the recess 321 in contact with the fill layer 306, using one or more thin film deposition processes (e.g., ALD, CVD, PVD, any other suitable process, or any combination thereof, etc.). The deposited semiconductor layer can be doped with an N-type dopant (e.g., P, As, or Sb, etc.) using ion implantation and / or thermal diffusion. In some implementations, in-situ doping of an N-type dopant (such as, for example, P, As, or Sb) is performed as the semiconductor layer is deposited into the recess 321 and over the fill layer 306 to form a doped semiconductor layer 360. In some implementations, a CMP process can be performed to remove any excess doped semiconductor layer 360, if necessary.

[0084] The method 500 proceeds to operation 514, as illustrated in FIG. 5, where the doped semiconductor layer and the portion of the semiconductor channel in contact with the doped semiconductor layer are locally activated. In some implementations, heat is applied to a confined area having the doped semiconductor layer and the portion of the semiconductor channel to activate dopants in the doped semiconductor layer and the portion of the semiconductor channel for localized activation. The confined area can be between the stack structure and the doped semiconductor layer. In some implementations, the doping concentration of the doped semiconductor layer and the doping concentration of the portion of the semiconductor channel in contact with the doped semiconductor layer are each 10% or more after activation.19 cm -3 From 10 21 cm -3 It is between.

[0085] As illustrated in FIG. 3L, the doped semiconductor layer 360 and a portion of the semiconductor channel 318 in contact with the doped semiconductor layer 360 are locally activated. In some implementations, heat is applied to the confined area having the doped semiconductor layer 360 and a portion of the semiconductor channel 318 to activate the dopants therein (e.g., N-type dopants (e.g., P, As, or Sb, etc.). For example, the confined area can be between the memory stack 330 and the doped semiconductor layer 360 in the vertical direction. The heat can be applied and focused by any suitable technique (e.g., annealing, laser, ultrasound, or any other suitable thermal process, etc.). In some implementations, the confined area that may be affected by heat during the local activation process does not extend to and beyond the bonding interface 354 to avoid heating the Cu interconnects used to connect the bonding interface 354 and the peripheral circuitry 352. The local activation process can activate dopants into the doped semiconductor layer 360 (and the exposed portion of the semiconductor channel 318 if the semiconductor channel 318 is already doped). As a result, the doping concentration of the doped semiconductor layer 360 and the doping concentration of the exposed portion of the semiconductor channel 318 can each be increased by 10% or more after activation. 19 cm -3 From 10 21 cm -3In some implementations, the local activation process is controlled to allow dopants in the doped semiconductor layer 360 (and exposed portions of the semiconductor channel 318, if the semiconductor channel 318 is already doped) to diffuse from the source of the channel structure 314 toward the drain of the channel structure 314 until they cross the source select gate line (e.g., one or more stacked conductive layers 328 closest to the fill layer 306), but not facing the word line, as described above with respect to FIG. 2. If the portion of the semiconductor channel 318 is not yet doped, the doped semiconductor layer 360 acts as a doping source during the local activation process to allow dopants to diffuse from the doped semiconductor layer 360 into the semiconductor channel 318, such that the portion of the semiconductor channel 318 in contact with the doped semiconductor layer 360 can become a doped portion, and the doped semiconductor layer 360 and the doped portion of the semiconductor channel 318 can have the same dopant and doping concentration.

[0086] The local activation process can activate the dopants so that they occupy the silicon lattice, reducing the contact resistance between the doped semiconductor layer 360 and the semiconductor channel 318, and reducing the sheet resistance of the doped semiconductor layer 360. On the other hand, by confining the heat during the local activation process into areas that do not include heat-sensitive structures, any potential damage to the heat-sensitive structures (such as, for example, the bonding interface 354 and the Cu interconnects used to connect the peripheral circuitry 352) can be reduced or avoided.

[0087] The method 500 proceeds to operation 516, as illustrated in FIG. 5, where a source contact is formed in contact with the doped semiconductor layer. As illustrated in FIG. 3M, one or more ILD layers 356 are formed over the doped semiconductor layer 360. The ILD layer 356 can be formed by depositing a dielectric material over a top surface of the doped semiconductor layer 360 using one or more thin film deposition processes (e.g., ALD, CVD, PVD, any other suitable process, or any combination thereof, etc.). As illustrated in FIG. 3N, a source contact opening 358 can be formed through the ILD layer 356 to expose a portion of the doped semiconductor layer 360. In some implementations, the source contact opening 358 is formed using wet and / or dry etching (e.g., RIE, etc.).

[0088] As illustrated in FIG. 3O, source contacts (as part of a conductive layer 370) are formed in respective source contact openings 358 (shown in FIG. 3N) at the backside of the fill layer 306. According to some implementations, the source contacts are above and in contact with the doped semiconductor layer 360. In some implementations, a conductive layer 370 (e.g., Al, etc.) is deposited into the source contact openings 358 using one or more thin film deposition processes (e.g., ALD, CVD, PVD, any other suitable process, or any combination thereof, etc.) to fill the source contact openings 358. A planarization process (e.g., CMP, etc.) can then be performed to remove excess conductive layer 370.

[0089] 3O, in some implementations, the conductive layer 370 also includes a redistribution layer that is above and in contact with the source contacts, i.e., the conductive layer 370 is not only deposited into the source contact openings 358 as source contacts, but also deposited outside the source contact openings 358 on the ILD layer 356 as a redistribution layer that electrically connects multiple source contacts, according to some implementations.

[0090] As illustrated in FIG. 3O, in some implementations, the conductive layer 370 further includes a contact extending through the ILD layer 356, the doped semiconductor layer 360, and the fill layer 306. That is, the conductive layer 370 is not only deposited into the source contact opening 358 as a source contact, but also into the contact openings 363 and 361 (shown in FIG. 3N) as contacts electrically connected to the peripheral contacts 338 and 340. As illustrated in FIGS. 3M and 3N, the contact openings 363 and 361 extending through the spacer layer 371, the ILD layer 356, the doped semiconductor layer 360, and the fill layer 306, respectively, are formed using wet etching and / or dry etching (e.g., RIE, etc.). In some implementations, the contact openings 363 and 361 are patterned using lithography to be aligned with the peripheral contacts 338 and 340, respectively. Etching of contact openings 363 and 361 can be stopped at the upper edges of peripheral contacts 338 and 340 to expose peripheral contacts 338 and 340. As shown in FIG. 3N, spacers 362 are formed from spacer layer 371 along the sidewalls of contact openings 363 and 361 to electrically isolate doped semiconductor layer 360.

[0091] 4A-4C illustrate a fabrication process for forming another exemplary 3D memory device according to some embodiments of the present disclosure. An example of a 3D memory device depicted in FIG. 4A-4C includes the 3D memory device 160 depicted in FIG. 1B. As shown in FIG. 4A, unlike FIG. 3J in which the recess 321 is formed by etching back the capping layer 319, the upper portion of the semiconductor channel 318 is doped to increase its conductivity without first etching back the capping layer 319 to expose a portion of the semiconductor channel 318. For example, a tilted ion implantation process can be performed to dope the upper portion of the semiconductor channel 318 (e.g., including polysilicon) with any suitable dopant (e.g., an N-type dopant such as P, As, or Sb, etc.) to a desired doping concentration.

[0092] In some embodiments, a layer of polysilicon is deposited on the fill layer, and the deposited layer of polysilicon is doped to form a doped semiconductor layer. As shown in FIG. 4B, a doped semiconductor layer 360 is formed on the fill layer 306 and on the upper end of the channel structure 314. In some implementations, a semiconductor layer (e.g., polysilicon) is deposited on the fill layer 306 using one or more thin film deposition processes (e.g., ALD, CVD, PVD, any other suitable process, or any combination thereof, etc.) to form the doped semiconductor layer 360. The deposited semiconductor layer can be doped with an N-type dopant (e.g., P, As, Sb, etc.) using ion implantation and / or thermal diffusion. In some implementations, in-situ doping of an N-type dopant (e.g., P, As, Sb, etc.) is performed when the semiconductor layer is deposited on the fill layer 306 to form the doped semiconductor layer 360. In some implementations, a CMP process can be performed to remove any excess doped semiconductor layer 360, if desired.

[0093] 4C, the doped semiconductor layer 360 and the doped portion of the semiconductor channel 318 are locally activated. In some implementations, heat is applied to the confined area having the doped semiconductor layer 360 and the doped portion of the semiconductor channel 318 to activate the dopants therein (e.g., N-type dopants (e.g., P, As, or Sb)). The local activation process can activate the dopants doped into the doped semiconductor layer 360 and the doped portion of the semiconductor channel 318. As a result, the doping concentration of the doped semiconductor layer 360 and the doped portion of the semiconductor channel 318 are each 10 19 cm -3 From 10 21 cm -3 In some implementations, the local activation process is controlled to allow dopants in the doped semiconductor layer 360 and the doped portion of the semiconductor channel 318 to diffuse from the source of the channel structure 314 toward the drain of the channel structure 314, beyond the source select gate line (e.g., one or more stacked conductive layers 328 nearest the fill layer 306), but not facing the word line, as described above with respect to FIG.

[0094] According to one aspect of the disclosure, a 3D memory device includes a stack structure including alternating conductive and dielectric layers, a channel structure extending through the stack structure, and a doped semiconductor layer, the doped semiconductor layer including a plate and a plug extending from the plate into the channel structure. The channel structure includes a memory film and a semiconductor channel. The semiconductor channel includes a doped portion, and a portion of the doped portion of the semiconductor channel extends beyond the stack structure in a first direction. The doped portion of the semiconductor channel surrounds the plug of the doped semiconductor layer.

[0095] In some implementations, the doping concentration of the doped portion of the semiconductor channel and the doped semiconductor layer are each 10 19 cm -3 From 10 21 cm -3 It is between.

[0096] In some implementations, the doped portion of the semiconductor channel and the doped semiconductor layer each comprise N-type doped polysilicon.

[0097] In some implementations, the doped portion of the semiconductor channel and the plug of the doped semiconductor layer each extend beyond one of the conductive layers in a second direction opposite the first direction.

[0098] In some implementations, one of the conductive layers includes a source select gate line.

[0099] In some implementations, the 3D memory device further includes a filler layer between the stack structure and the plate of the doped semiconductor layer.

[0100] In some implementations, the fill layer includes polysilicon, a high-k dielectric, or a metal.

[0101] In some implementations, the 3D memory device further includes a source contact in contact with the doped semiconductor layer.

[0102] In some implementations, the memory film extends across the stack structure in a first direction and is in contact with a plate of the doped semiconductor layer.

[0103] In some implementations, the doped semiconductor layer plug is configured to generate a GIDL-assisted body bias when performing an erase operation.

[0104] According to another aspect of the disclosure, a 3D memory device includes a stack structure including interleaved conductive and dielectric layers, a doped semiconductor layer, and a channel structure extending through the stack structure. The channel structure includes a memory film and a semiconductor channel. The channel structure includes a memory film and a semiconductor channel. The semiconductor channel includes a doped portion. The channel structure extends beyond the stack structure in a first direction and is in contact with the doped semiconductor layer. The semiconductor channel includes a doped portion extending beyond one of the conductive layers in a second direction opposite the first direction.

[0105] In some implementations, the doping concentration of the doped portion of the semiconductor channel and the doped semiconductor layer are each 10 19 cm -3 From 10 21 cm -3 It is between.

[0106] In some implementations, the doped portion of the semiconductor channel and the doped semiconductor layer each comprise N-type doped polysilicon.

[0107] In some implementations, one of the conductive layers includes a source select gate line.

[0108] In some implementations, a portion of the doped portion of the semiconductor channel extends beyond the stack structure in the first direction and is in contact with the doped semiconductor layer.

[0109] In some implementations, the 3D memory device further includes a filler layer between the stack structure and the doped semiconductor layer.

[0110] In some implementations, the fill layer includes polysilicon, a high-k dielectric, or a metal.

[0111] In some implementations, the 3D memory device further includes a source contact in contact with the doped semiconductor layer.

[0112] In some implementations, the channel structure further includes a capping layer extending beyond the stack structure in the first direction and in contact with the doped semiconductor layer.

[0113] In some implementations, the doped semiconductor layer is configured to generate a GIDL-assisted body bias when performing an erase operation.

[0114] According to yet another aspect of the present disclosure, a method for forming a 3D memory device is provided. A fill layer is formed above a substrate. A stack structure is formed above the fill layer. A channel structure is formed extending through the stack structure and the fill layer. The channel structure includes a memory film and a semiconductor channel. Portions of the channel structure extending beyond the substrate and the fill layer are sequentially removed to expose a portion of the semiconductor channel. A doped semiconductor layer is formed in contact with the exposed portion of the semiconductor channel. The doped semiconductor layer and the portion of the semiconductor channel in contact with the doped semiconductor layer are locally activated.

[0115] In some implementations, to locally activate, heat is applied in a confined area having a portion of the doped semiconductor layer and the semiconductor channel to activate dopants in the doped semiconductor layer and the portion of the semiconductor channel.

[0116] In some implementations, the confined area is between the stack structure and the doped semiconductor layer.

[0117] In some implementations, the dopant comprises an N-type dopant, and after activation, the doping concentration of the doped semiconductor layer and the doping concentration of the portion of the semiconductor channel in contact with the doped semiconductor layer are each greater than or equal to 10 19 cm -3 From 10 21 cm -3 It is between.

[0118] In some implementations, the exposed portion of the semiconductor channel is doped prior to forming the doped semiconductor layer.

[0119] In some implementations, a first stop layer and a second stop layer are formed sequentially between the substrate and the fill layer.

[0120] In some implementations, the first stop layer comprises silicon oxide or silicon nitride, the second stop layer comprises silicon oxide or polysilicon, and the fill layer comprises polysilicon, a high-k dielectric, or a metal.

[0121] In some implementations, to form a channel structure, a channel hole is formed extending through the stack structure and the fill layer and stopping at a second stop layer, and a memory film, a semiconductor channel, and a capping layer are sequentially formed in the channel hole.

[0122] In some implementations, to sequentially remove the substrate and portions of the memory film, the substrate is removed, stopping at the first stop layer, the first stop layer is removed, stopping at the second stop layer, the second stop layer and portions of the channel structure are removed, and stopping at the fill layer.

[0123] In some implementations, the removed portion of the channel structure extends into the second stop layer. In some implementations, the second stop layer and the portion of the channel structure that extends into the second stop layer are polished to remove the second stop layer and the portion of the channel structure.

[0124] In some implementations, a portion of the capping layer of the channel structure is etched back to sequentially remove portions of the substrate and the channel structure, forming a recess surrounded by a portion of the semiconductor channel.

[0125] In some implementations, a layer of polysilicon is deposited into the recess and over the fill layer, and the deposited layer of polysilicon is doped to form a doped semiconductor layer.

[0126] In some implementations, a layer of polysilicon is deposited over the fill layer, and the deposited layer of polysilicon is doped to form a doped semiconductor layer.

[0127] In some implementations, after locally activating the doped semiconductor layer, a source contact is formed in contact with the doped semiconductor layer.

[0128] According to yet another aspect of the present disclosure, a system includes a 3D memory device configured to store data and a memory controller, the memory controller coupled to the 3D memory device and configured to control the 3D memory device. The 3D memory device includes a stack structure including alternating conductive and dielectric layers, a channel structure extending through the stack structure, and a doped semiconductor layer, the doped semiconductor layer including a plate and a plug extending from the plate into the channel structure. The channel structure includes a memory film and a semiconductor channel. The semiconductor channel includes a doped portion, and a portion of the doped portion of the semiconductor channel extends beyond the stack structure in a first direction. The doped portion of the semiconductor channel surrounds the plug of the doped semiconductor layer.

[0129] In some implementations, the system further includes a host, the host coupled to the memory controller and configured to transmit or receive data.

[0130] The foregoing description of specific implementations may be readily modified and / or adapted for a variety of applications. Therefore, such adaptations and modifications are intended to be within the meaning and range of equivalents of the disclosed implementations, based on the teaching and guidance presented herein.

[0131] The breadth and scope of the present disclosure should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents. [Explanation of symbols]

[0132] 100 3D Memory Devices 101 Substrate 102 First semiconductor structure 104 Second semiconductor structure 106 Bonding Interface 108 Peripheral Circuits 110 Bonding layer 111 Bonding contact 112 Bonding Layer 113 Bonding Contact 114 Memory Stack 116 stack conductive layer 118 Stacked Dielectric Layers 120 Filled bed 121 Plate 122 Doped Semiconductor Layer 123 Plug 124 Channel Structure 126 Memory Film 127 Capping Layer 128 Semiconductor Channels 128a doped part 128b Undoped part 129 Channel Plug 130 Insulating Structure 132 Source Contact 133 Interconnection Layer 134 ILD layer 136 Redistribution Layer 138 Passivation Layer 140 Contact Pad 142 Contact part 144 Contact Part 146 Peripheral contact area 148 Peripheral contact area 150 Channel Local Contact 152 Word Line Local Contact 160 3D Memory Devices 201 Source Select Gate Line 203 Word Line 302 Carrier Board 303 First stop layer 304 Second Stop Layer 306 Filled bed 308 Dielectric Stack 310 stack dielectric layers 312 stack sacrificial layer 314 Channel Structure 315 Tunneling Layer 316 Storage Tier 317 Blocking Layer 318 Semiconductor Channel 319 Capping Layer 320 Slit 321 Recess 322 Lateral recess 328 stack conductive layer 330 Memory Stack 332 Gate dielectric layer 334 Dielectric Capping Layer 335 Polysilicon core layer 336 Insulation Structure 338 Peripheral contact area 340 Peripheral contact area 342 Word Line Local Contact 344 Channel local contact 346 Bonding Layer 348 Bonding Layer 350 Silicon substrate 352 Peripheral Circuits 354 Bonding Interface 356 ILD layer 358 Source Contact Opening 360 Doped semiconductor layer 361 Contact opening 362 Spacer 363 Contact opening 370 Conductive Layer 371 Spacer layer 700 System 702 Memory System 704 3D Memory Device 706 Memory Controller 708 Host 802 Memory Card 804 memory card connector 806 SSD 808 SSD Connector

Claims

1. a stack structure including alternating conductive and dielectric layers; a channel structure extending through the stack structure, the channel structure including a memory film and a semiconductor channel, the semiconductor channel including a doped portion, a portion of the doped portion of the semiconductor channel extending beyond the stack structure in a first direction; a doped semiconductor layer including a plate and a plug extending from the plate into the channel structure, the doped portion of the semiconductor channel surrounding the plug of the doped semiconductor layer; Including, a doping concentration of the doped portion of the semiconductor channel that is higher than a doping concentration of other portions of the semiconductor channel; the doped portion of the semiconductor channel and the plug of the doped semiconductor layer each extend beyond one of the conductive layers in a second direction opposite the first direction.

2. The doping concentration of the doped portion of the semiconductor channel is 10 １９ cm －３ From 10 ２１ cm －３ 2. The 3D memory device of claim 1 , wherein:

3. The 3D memory device of claim 1, wherein the doping concentration of the doped semiconductor layer is between 10 19 cm −3 and 10 21 cm −3 .

4. 10. The 3D memory device of claim 1, wherein the doped portion of the semiconductor channel and the doped semiconductor layer each comprise N-type doped polysilicon.

5. 10. The 3D memory device of claim 1, wherein said one of said conductive layers comprises a source select gate line.

6. 10. The 3D memory device of claim 1, further comprising a fill layer between the stack structure and the plate of the doped semiconductor layer.

7. 7. The 3D memory device of claim 6, wherein the fill layer comprises polysilicon, a high dielectric constant (high-k) dielectric, or a metal.

8. 10. The 3D memory device of claim 1 further comprising a source contact in contact with the doped semiconductor layer.

9. 10. The 3D memory device of claim 1, wherein the memory film extends across the stack structure in the first direction and contacts the plate of the doped semiconductor layer.

10. a stack structure including alternating conductive and dielectric layers; a channel structure extending through the stack structure, the channel structure including a memory film and a semiconductor channel; a doped semiconductor layer; Including, the channel structure extends beyond the stack structure in a first direction and is in contact with the doped semiconductor layer; the semiconductor channel includes a doped portion that extends beyond one of the conductive layers in a second direction opposite the first direction; a doping concentration of the doped portion of the semiconductor channel that is higher than a doping concentration of other portions of the semiconductor channel; a portion of the doped semiconductor layer in contact with the doped portion of the semiconductor channel extends in the second direction beyond one of the conductive layers.

11. forming a fill layer above the substrate; forming a stack structure above the packing layer; forming a channel structure extending through the stack structure and the fill layer, the channel structure including a memory film and a semiconductor channel; sequentially removing the substrate and a portion of the channel structure extending beyond the fill layer to expose a portion of the semiconductor channel; forming a doped semiconductor layer in contact with the exposed portion of the semiconductor channel; locally activating dopants in the doped semiconductor layer and in the portion of the semiconductor channel in contact with the doped semiconductor layer; Including, A method for forming a three-dimensional (3D) memory device, wherein the doping concentration of the portion of the semiconductor channel is higher than a doping concentration of another portion of the semiconductor channel after the activation.

12. 12. The method of claim 11 , wherein locally activating comprises applying heat in a confined area having the doped semiconductor layer and the portion of the semiconductor channel to activate dopants in the doped semiconductor layer and the portion of the semiconductor channel.

13. The method of claim 11 , further comprising doping the exposed portion of the semiconductor channel prior to forming the doped semiconductor layer.

14. The method of claim 11 , further comprising sequentially forming a first stop layer and a second stop layer between the substrate and the fill layer.

15. The step of forming the channel structure comprises: forming a channel hole extending through the stack structure and the fill layer and terminating at the second stop layer; sequentially forming the memory film, the semiconductor channel, and a capping layer in the channel hole; 15. The method of claim 14, comprising:

16. The step of sequentially removing the substrate and the portion of the channel structure comprises: removing the substrate and stopping on the first stop layer; removing the first stop layer and stopping on the second stop layer; removing the second stop layer and the portion of the channel structure, stopping at the fill layer; 16. The method of claim 15, comprising:

17. 16. The method of claim 15, wherein sequentially removing the substrate and the portion of the channel structure further comprises etching back a portion of the capping layer of the channel structure to form a recess surrounded by the portion of the semiconductor channel.

18. The step of forming the doped semiconductor layer comprises: depositing a layer of polysilicon into the recess and over the fill layer; doping the deposited layer of polysilicon; 20. The method of claim 17, comprising:

19. The step of forming the doped semiconductor layer comprises: depositing a layer of polysilicon over the fill layer; doping the deposited layer of polysilicon; The method of claim 11 , comprising:

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