Inverter circuit, semiconductor device

Abstract

To provide a semiconductor device having a circuit with a shrunk area, and a semiconductor device having a circuit capable of reducing power supply voltage fluctuation.SOLUTION: A semiconductor device 500 includes a first transistor 491, a second transistor 490, a first power supply wiring 480, and a second power supply wiring 482, the second transistor and the first transistor are stacked, the second power supply wiring and the first power supply wiring are stacked, the second power supply wiring and the first power supply wiring mutually and at least partially overlap, the second power supply wiring and the first power supply wiring are arranged approximately in parallel, the source electrode of the first transistor is electrically connected to the first power supply wiring, the source electrode of the second transistor is electrically connected to the second power supply wiring, the second transistor is an n-channel type and its channel formation region is formed of an oxide semiconductor, and the first transistor is a p-channel type and its channel formation region is formed of silicon.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to an article, a method, or a manufacturing method. In particular, the term "composition of matter" refers to a process, manufacture, or composition of matter. The present invention relates to, for example, a semiconductor device, a display device, a light-emitting device, a lighting device, a power storage device, The present invention relates to a memory device or a processor, or a semiconductor device, a display device, or a light-emitting device. , a lighting device, a power storage device, a memory device, or a processor. DEVICE, DISPLAY DEVICE, LIGHT-EMITTING DEVICE, ILLUMINATION DEVICE, POWER STORAGE DEVICE, MEMORY DEVICE, OR PROCESSOR DRIVE METHOD - Patent application Regarding.

[0002] In this specification and the like, a semiconductor device is a device that can function by utilizing semiconductor characteristics. Refers to devices in general. Memory devices, display devices, light-emitting devices, lighting devices, electro-optical devices, semiconductor circuits Electronic devices and the like may include semiconductor devices. [Background technology]

[0003] A transistor in which the channel formation region is made of semiconductor silicon (Si) (hereinafter referred to as a Si transistor) These transistors are widely used in electronic devices such as integrated circuits and image display devices. The integrated circuit is configured with n-channel Si transistors and p-channel Si transistors. The cells (logic cells) are made up of wiring, such as inverter circuits, NAND circuits, and flip-flops. The building blocks of the LSI are the 3-D CMOS transistors, which are sometimes called standard cells (see Non-Patent Document 1). ).

[0004] On the other hand, when the channel formation region is made of oxide such as In-Ga-Zn oxide (In-Ga-Zn-O), Transistors made of oxide semiconductors (hereinafter referred to as OS transistors) are known. Since oxide semiconductors have a larger band gap than silicon, It is known that transistors have extremely low off-state current. For example, Patent Document 1 states: By using OS transistors in memory cells, it is possible to develop semiconductor devices that can retain data even after the power is cut off. A body device is described.

[0005] In recent years, miniaturized transistors have become more common as electronic devices become more powerful, smaller, and lighter. There is an increasing demand for circuits in which semiconductor elements such as transistors are integrated at high density. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] JP2011-187950A [Non-patent literature]

[0007] [Non-Patent Document 1] Neil HEWeste and David Money Harris, CMOS VLSI Design: A Circuits and Systems Perspective (4th Edition), Addison Wesley, p.27, 2011. Summary of the Invention [Problem to be solved by the invention]

[0008] One aspect of the present invention has at least one of the following objectives: To provide a semiconductor device (cell) having a circuit with a reduced area, the circuit being wired together, The transistors are arranged and wired to have a circuit capable of improving the operating speed. To provide a semiconductor device (cell), which is a consumption cell formed by arranging and wiring a plurality of transistors. To provide a semiconductor device (cell) having a circuit capable of reducing power consumption, A circuit capable of reducing fluctuations in power supply voltage, in which transistors are arranged and wired. To provide a semiconductor device (cell) in which a plurality of transistors are arranged and wired, To provide a semiconductor device having a high processing speed, in which a plurality of transistors are arranged and wired. To provide a semiconductor device capable of improving the performance of the semiconductor device, The present invention provides a semiconductor device capable of reducing power consumption, To provide a semiconductor device in which a stator is arranged and wired, and which can reduce costs. Or, to provide a novel semiconductor device.

[0009] The description of these problems does not preclude the existence of other problems. It is not necessary for one embodiment to solve all of these problems. The subject matter will be self-evident from the description, drawings, claims, etc. Other issues can be extracted from the drawings, claims, etc. [Means for solving the problem]

[0010] (1) One aspect of the present invention is a semiconductor device including a first transistor, a second transistor, a first conductor, and a second conductor. and a second conductor, the second transistor and the first transistor being stacked, and the first conductor The first conductor is supplied with a first power supply voltage, the second conductor is supplied with a second power supply voltage, and the first conductor is supplied with a first the first region and the second region are one or more layers. The source electrode or drain electrode of the first transistor overlaps the insulator of the first layer and extends parallel to the insulator. The drain electrode is electrically connected to the first conductor and serves as a source electrode or drain electrode of the second transistor. The drain electrode is electrically connected to the second conductor, and the second transistor is an n-channel type. A channel formation region of the second transistor is formed of an oxide semiconductor, and The first transistor is a p-channel type, and the channel forming region of the first transistor is made of silicon. It is a semiconductor device.

[0011] (2) Alternatively, one embodiment of the present invention is a semiconductor device having an input terminal and an output terminal, The width of each of the two conductors is wider than the width of the conductor connected to the input terminal and is connected to the output terminal. This is a semiconductor device according to aspect (1), which is wider than the width of the conductor to be connected.

[0012] (3) Alternatively, one aspect of the present invention is a semiconductor device comprising a first insulator having a first opening and a second opening. The first opening has a second insulator, a third conductor, and a fourth conductor. The source electrode or drain electrode of the transistor and the first conductor are directly connected via a third conductor. The second opening is connected to the source electrode or drain electrode of the second transistor. The conductor is either (1) or (2) directly connected via a fourth conductor. The present invention relates to a semiconductor device.

[0013] (4) Alternatively, one embodiment of the present invention is a semiconductor device comprising: a first conductor and a first transistor; Any of (1) to (3) having no transistor between the conductor and the second transistor. The present invention relates to a semiconductor device according to any one of the above aspects.

[0014] (5) Alternatively, in one embodiment of the present invention, there is no conductor between the first region and the second region. The semiconductor device according to any one of the above aspects (1) to (4).

[0015] (6) Alternatively, in one aspect of the present invention, the first conductor and the second conductor are formed by conductors of adjacent layers. The semiconductor device according to any one of (1) to (5) above is configured as follows.

[0016] (7) Alternatively, one embodiment of the present invention is a semiconductor device including a channel formation region of a first transistor, a first conductor, The second conductor and the channel forming region of the second transistor are stacked in this order (1) to (6). ) is a semiconductor device according to any one of the above aspects.

[0017] (8) Alternatively, one embodiment of the present invention is a semiconductor device including a channel formation region of a first transistor, a first conductor, The channel forming region of the second transistor and the second conductor are stacked in this order (1) to (6). ) is a semiconductor device according to any one of the above aspects.

[0018] (9) Alternatively, one embodiment of the present invention is a semiconductor device comprising: a source electrode, a gate electrode, and The direction in which the drain electrodes are arranged and the source electrode, gate electrode, and drain electrode of the second transistor are arranged in the same direction. The direction in which the electrodes of the first transistor are arranged is parallel or anti-parallel. The gate electrode of the second transistor is electrically connected to any one of (1) to (8). The present invention relates to a semiconductor device.

[0019] (10) Alternatively, according to one embodiment of the present invention, a direction of a current flow of a first transistor and a direction of a current flow of a second transistor are The direction of the current flow of the first transistor is parallel or antiparallel to the gate of the second transistor. The electrode and the gate electrode of the second transistor are electrically connected to any one of (1) to (9). The present invention relates to a semiconductor device according to any one of the above aspects.

[0020] (11) Alternatively, one embodiment of the present invention is a method for manufacturing a semiconductor device comprising the steps of: forming a channel formation region of a second transistor with an oxide; The nitride semiconductor has multiple crystal parts aligned along the c-axis, and the diffraction pattern shows the crystals aligned along the c-axis. Any of (1) to (10) in which the area in which the The present invention relates to a semiconductor device.

[0021] (12) Alternatively, one aspect of the present invention is a semiconductor device according to any one of the aspects (1) to (11). The present invention relates to a memory device having a memory cell array including a single memory device.

[0022] (13) Alternatively, one aspect of the present invention is a semiconductor device according to any one of the aspects (1) to (11). The RFID tag has a body device and an antenna.

[0023] (14) Alternatively, one aspect of the present invention is a semiconductor device according to any one of the aspects (1) to (11). An electronic device having a body device and a printed wiring board. Effect of the Invention

[0024] To provide a semiconductor device having a circuit with a reduced area in which transistors are arranged and wired. Alternatively, the transistors can be arranged and wired to improve the operating speed. It is possible to provide a semiconductor device having a circuit capable of performing the above-mentioned function. To provide a semiconductor device having a circuit that is arranged and wired to reduce power consumption. Alternatively, the transistors are arranged and wired to reduce fluctuations in the power supply voltage. It is possible to provide a semiconductor device having a circuit capable of performing the above-mentioned operations. The description of these effects does not preclude the existence of other effects. It is not necessary for one embodiment of the present invention to have all of these effects. Effects other than those mentioned above are obvious from the description, drawings, claims, etc. Other effects can be extracted from the description in the specification, drawings, claims, etc. It is possible. [Brief description of the drawings]

[0025] [Figure 1] 1 is a schematic diagram illustrating a semiconductor device according to one embodiment of the present invention. [Diagram 2] 1 is a schematic diagram illustrating a semiconductor device according to one embodiment of the present invention. [Diagram 3] FIG. 1 is a top view illustrating a semiconductor device according to one embodiment of the present invention. [Figure 4] FIG. 1 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. [Diagram 5] FIG. 1 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. [Figure 6] FIG. 1 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. [Figure 7] 1 is a schematic diagram illustrating a semiconductor device according to one embodiment of the present invention. [Figure 8] FIG. 1 is a top view illustrating a semiconductor device according to one embodiment of the present invention. [Figure 9] FIG. 1 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. [Figure 10] 1 is a schematic diagram illustrating a semiconductor device according to one embodiment of the present invention. [Figure 11] FIG. 1 is a top view illustrating a semiconductor device according to one embodiment of the present invention. [Figure 12] FIG. 1 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. [Figure 13] 1 is a schematic diagram illustrating a semiconductor device according to one embodiment of the present invention. [Figure 14] FIG. 1 is a top view illustrating a semiconductor device according to one embodiment of the present invention. [Figure 15]FIG. 1 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. [Figure 16] 1 is a schematic diagram illustrating a semiconductor device according to one embodiment of the present invention. [Figure 17] FIG. 1 is a top view illustrating a semiconductor device according to one embodiment of the present invention. [Figure 18] FIG. 1 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. [Figure 19] FIG. 1 is a circuit diagram illustrating a semiconductor device according to one embodiment of the present invention. [Figure 20] FIG. 1 is a circuit diagram illustrating a semiconductor device according to one embodiment of the present invention. [Figure 21] FIG. 2 is a block diagram showing a CPU according to an embodiment of the present invention. [Figure 22] FIG. 1 is a circuit diagram illustrating a semiconductor device according to one embodiment of the present invention. [Diagram 23] FIG. 1 is a circuit diagram illustrating a semiconductor device according to one embodiment of the present invention. [Figure 24] FIG. 1 illustrates a configuration of a chip and a module according to one embodiment of the present invention. [Diagram 25] FIG. 1 is a block diagram showing an RFID according to one embodiment of the present invention. [Figure 26] FIG. 1 is a block diagram illustrating a memory device according to one embodiment of the present invention. [Figure 27] FIG. 1 is a circuit diagram showing a memory cell. [Figure 28] FIG. 1 is a circuit diagram showing a memory cell. [Figure 29] FIG. 1 is a circuit diagram showing a memory cell. [Diagram 30] 1A to 1C are diagrams illustrating electronic devices according to one embodiment of the present invention. [Diagram 31] 1 is a schematic diagram illustrating a semiconductor device according to one embodiment of the present invention. [Diagram 32] 1 is a schematic diagram illustrating a semiconductor device according to one embodiment of the present invention. [Diagram 33] FIG. 1 is a cross-sectional view showing a transistor. [Diagram 34] FIG. 1 is a cross-sectional view showing a transistor. [Diagram 35] Cross-sectional TEM image and local Fourier transform image of an oxide semiconductor. [Diagram 36]1A and 1B are diagrams showing a nanobeam electron diffraction pattern of an oxide semiconductor and an example of a transmission electron diffraction measurement apparatus. [Figure 37] An example of structural analysis using transmission electron diffraction measurements, and a planar TEM image. [Figure 38] 1A and 1B are cross-sectional views showing stacked layers of semiconductors and diagrams showing band structures. [Figure 39] 1 is a schematic diagram illustrating a semiconductor device according to one embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0026] The present invention will be described in detail with reference to the drawings. The present invention is not limited to the description, and various modifications in form and details are possible. In addition, the present invention should not be construed as being limited to the description of the following embodiments. In explaining the configuration of the invention using the drawings, the same reference numerals are used It is used commonly across different drawings. Note that when referring to similar objects, the hatch pattern is used in the same way. In some cases, no particular symbol is given.

[0027] In the figures, the size, thickness of the film (layer), or area is exaggerated for clarity. There may be cases where this is the case.

[0028] Also, a voltage is a voltage between a certain potential and a reference potential (such as ground potential (GND) or source potential). Therefore, voltage can be replaced with electric potential. do.

[0029] The ordinal numbers 1 and 2 are used for convenience and do not indicate the order of processes or stacking. It does not indicate the layer order. For example, "first" should not be changed to "second" or "third" etc. In addition, the ordinal numbers described in this specification and the like can be replaced with the ordinal numbers. However, the ordinal numbers used to identify an aspect of the present invention may not be consistent.

[0030] Even if a material is described as a "semiconductor," it may be considered an "insulator" if, for example, its electrical conductivity is sufficiently low. In addition, the boundary between "semiconductors" and "insulators" is unclear and cannot be clearly defined. Therefore, the term "semiconductor" as used herein may not be clearly distinguishable from "insulator." Similarly, the term "insulator" as used herein may be interchangeable with "semiconductor." In other words,

[0031] In addition, even if a material is written as a "semiconductor," if the material has a sufficiently high electrical conductivity, it may be written as a "conductor." In addition, the boundary between "semiconductor" and "conductor" is unclear and not strictly defined. Therefore, the term "semiconductor" as used herein may not be used interchangeably with "conductor." Similarly, the term "conductor" as used herein may be interchangeable with "semiconductor." In other words,

[0032] The impurities in a semiconductor are, for example, substances other than the main components that make up the semiconductor. Elements present at less than 0.1 atomic percent are considered impurities. The formation of DOS (Density of State) in the conductor and carrier movement The degree of conductivity may decrease, and the crystallinity may decrease. In the case of a conductor, impurities that change the properties of the semiconductor include, for example, elements of Group 1, Group elements, Group 14 elements, Group 15 elements, transition metals other than the main component, etc., in particular, , hydrogen (also found in water), lithium, sodium, silicon, boron, phosphorus, carbon, nitrogen In the case of oxide semiconductors, for example, oxygen vacancies can be eliminated by the inclusion of impurities such as hydrogen. In addition, when the semiconductor is silicon, there are cases where a defect that changes the properties of the semiconductor is formed. The pure substances include, for example, oxygen, Group 1 elements excluding hydrogen, Group 2 elements, Group 13 elements, and Group 1 elements. Group 5 elements, etc.

[0033] In the following embodiments, unless otherwise specified, the insulator is, for example, boron. Element, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, Argon, Gallium, Germanium, Yttrium, Zirconium, Lanthanum, Neodymium Insulators containing one or more of hafnium and tantalum may be used in a single layer or a multilayer structure. Alternatively, resin may be used as the insulator. For example, polyimide, polyamide, Resin containing acrylic, silicone, etc. can be used. By using resin, the upper surface of the insulator In some cases, it may not be necessary to perform flattening treatment on the surface. Also, resin can form a thick film in a short time. As a result, productivity can be improved. The insulator is preferably aluminum oxide. , silicon oxide nitride, silicon nitride, gallium oxide, yttrium oxide, zirconium oxide Insulators containing tungsten oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or tantalum oxide may be used in a single layer or in a laminate.

[0034] In the following embodiments, unless otherwise specified, the conductor is, for example, boron. element, nitrogen, oxygen, fluorine, silicon, phosphorus, aluminum, titanium, chromium, manganese, Cobalt, nickel, copper, zinc, gallium, yttrium, zirconium, molybdenum, Conductors containing one or more of ruthenium, silver, indium, tin, tantalum, or tungsten For example, an alloy film or a compound film may be used. Conductors containing aluminum, conductors containing copper and titanium, conductors containing copper and manganese Conductors containing indium, tin and oxygen, and conductors containing titanium and nitrogen are used. This is also fine.

[0035] In this specification, when it is stated that A has a region of concentration B, for example, If the concentration in the entire depth direction of a certain area is B, the average concentration in the depth direction of the area of ​​A is If the average value is concentration B, then the median value in the depth direction in a region of A is concentration B, If the maximum value in the depth direction in a region of A is concentration B, then If the minimum value in the direction is concentration B, then the convergence value in the depth direction in a region of A is concentration B. This includes cases where the area where the most likely value of A is obtained is concentration B. .

[0036] In this specification, A represents an area of ​​size B, length B, thickness B, width B or distance B. When describing something as having a certain area, for example, the whole of A has size B, length B, thickness B, etc. If B, width B or distance B, the average value in a certain area of ​​A is size B, length B, thickness B If the length, width or distance of A is B, the median value of the area of ​​A is B, B If thickness B, width B, or distance B, the maximum value in a certain area of ​​A is size B, length B , thickness B, width B or distance B, the minimum value of an area of ​​A is the size B, length If A has a size B, thickness B, width B or distance B, then the convergence value in a region of A is size B, length B When the length B, thickness B, width B or distance B is measured, the most likely value of A itself can be obtained. This includes cases where the area has size B, length B, thickness B, width B or distance B.

[0037] Note that the channel length is, for example, the length of a semiconductor (or transistor) in a top view of a transistor. The area where the gate electrode overlaps with the semiconductor (the part through which current flows when the transistor is on). The source (source region or source electrode) in the region where the channel is formed This refers to the distance between the transistor and the drain (the drain region or the drain electrode). In a transistor, the channel length does not necessarily have the same value in all regions. The channel length of a transistor may not be determined to a single value. The channel length is any one of the values, maximum value, minimum value, and The value is the average value.

[0038] The channel width is the width of the semiconductor (or transistor) when it is in the on state. In the region where the gate electrode overlaps with the gate electrode (where the current flows) or in the region where the channel is formed, This refers to the length of the part where the source and drain face each other. In a transistor, the channel width does not necessarily have the same value in all regions. The channel width of a transistor may not be determined to a single value. The channel width is any one of the values, maximum value, minimum value, and maximum value in the region where the channel is formed. The value is the average value.

[0039] Depending on the structure of the transistor, the channel in the region where the channel is actually formed may be The effective channel width is shown in the top view of the transistor. The channel width that is actually used (hereinafter referred to as the apparent channel width) may differ from the actual channel width. For example, In a transistor having a three-dimensional structure, the effective channel width is The channel width becomes larger than the apparent width shown in the figure, and the effect becomes non-negligible. For example, in a transistor with a fine and three-dimensional structure, The percentage of the channel region formed on the side of the semiconductor compared to the percentage of the channel region formed on the inside of the semiconductor. In that case, the apparent channel width shown in the top view may be In this case, the effective channel width where the channel is actually formed is larger than the actual channel width.

[0040] In a transistor having a three-dimensional structure, the effective channel width is For example, it may be difficult to estimate the effective channel width from the design value. In order for the deposition to occur, it is necessary to assume that the shape of the semiconductor is known. If it is not known precisely, it is difficult to measure the effective channel width accurately.

[0041] The functions of the "source" and "drain" of a transistor are different for transistors of different polarities. When using a current source, or when the direction of the current changes during circuit operation, For this reason, in this specification, the terms "source" and "drain" are interchangeable. can be used instead.

[0042] In this specification, "parallel" means that two straight lines are at an angle of -10° or more and 10° or less. Therefore, it includes the case where the angle is between -5° and 5°. "Perpendicular" refers to two straight lines that form an angle between 80° and 100°. Therefore, cases between 85° and 95° are also included.

[0043] (Embodiment 1) In this embodiment, a semiconductor device according to one embodiment of the present invention will be described with reference to drawings.

[0044] A configuration example of a semiconductor device in which transistors are arranged and wired will be described with reference to FIG. do.

[0045] FIG. 1 shows a semiconductor device in which a transistor 490 and a transistor 491 are arranged and wired. The semiconductor device 500 includes a transistor 491 and a The semiconductor device includes a conductor 480 that functions as a transistor 490, and a conductor 482 that functions as a wiring. The semiconductor device 500 includes a transistor that is formed at the same time as the transistor 490. The transistor and the transistor 490 may be formed with the same semiconductor material. The semiconductor device 500 includes a transistor 491 formed at the same time. The transistor and the transistor 491 may be made of the same semiconductor material. The transistor 490 and the transistor 491 are stacked. The conductor 480 has a function of supplying a high power supply voltage (VDD) (hereinafter, referred to as a high power supply wiring The conductor 482 has a function of supplying a low power supply voltage (VSS) (hereinafter, referred to as a low (This is also called power wiring.) Conductor 482 and conductor 480 are stacked.

[0046] The transistor 491 is, for example, a p-channel transistor having a high switching speed. For example, the switching speed of transistor 491 is It is less than 10 ns, preferably less than 1 ns, and more preferably less than 0.1 ns. In addition, a p-channel Si transistor can be used as the transistor 491. The transistor 490 is, for example, an n-channel transistor with a high switching speed. For example, the switching speed of transistor 490 can be 10 It is less than ns, preferably less than 1 ns, more preferably less than 0.1 ns. The channel formation region includes an oxide semiconductor (preferably an oxide containing In, Ga, and Zn). The transistor including the above-mentioned oxide semiconductor is referred to as a transistor 490 (hereinafter, a transistor using an oxide semiconductor). (also called "multi-layered multi-layered") can be used.

[0047] The switching speed of a transistor is the speed at which a single transistor becomes non-conductive. This expresses the speed at which a transistor changes from a non-conducting state to a conducting state when the gate voltage is changed. The time it takes for a charge equivalent to an increment in the drain current of a transistor to accumulate in the gate capacitance is called the gate capacitance. The switching speed of a transistor can be interpreted as the speed at which the transistor When a transistor is used as an amplifier, the maximum frequency (cutoff frequency) at which the current gain is 1 or more is called the The speed corresponding to the wave number may be expressed as

[0048] The semiconductor device 500 includes a transistor 491 and / or a transistor 491 and and transistor 490, and / or transistor 490 By arranging and wiring the transistors that are formed at the same time, it functions as a circuit. The semiconductor device 500 is capable of supplying power to the transistor. The semiconductor device 500 is, for example, a semiconductor device that is connected to various electronic circuit components. Such a unit may be a standard cell, a logic cell, or simply a , called a cell.

[0049] The transistors and power supply wirings of the semiconductor device 500 are arranged closely together. It is preferable that the wiring is regularly arranged at the edge of the cell area. It can be made smaller.

[0050] The semiconductor device 500 (cell) includes an inverter circuit, a NAND circuit, an AND circuit, a NOR circuit, OR circuit, buffer, level shifter, XOR circuit, XNOR circuit, AND-NOR circuit, OR-NAND circuit, AND-OR-INV circuit, OR-AND-INV circuit, Analog switches, flip-flops, settable flip-flops, resettable flip-flops Flip-flops, settable and resettable flip-flops, adders, half adders, multi-adders Multiplexers, demultiplexers, registers, scan registers, retention registers , isolators, decoders, etc.

[0051] In particular, by arranging and wiring p-channel transistors and n-channel transistors, , Complementary Metal Oxide Semiconductor (CMOS) It is possible to construct a CMOS circuit. By forming such a circuit, the power consumption of the electronic circuit can be reduced.

[0052] The semiconductor device 500 (cell) is used as an electronic circuit, for example, a CPU, a GPU (Graph ics Processing Unit), DSP(Digital Signal Processor), MCU (Microcontroller Unit), RF- ID (Radio Frequency Identification), Custom L In these electronic circuits, multiple cells are arranged in multiple rows, and the electronic circuit is The input and output terminals of the cells are connected by wiring so that they function as a single unit.

[0053] The low power supply wiring (conductor 482) is connected to the source electrode (or source region) of transistor 490. Alternatively, the source electrode (or source region) of transistor 490 is connected to , through a transistor formed simultaneously with transistor 490, 82). The high power supply wiring (conductor 480) is connected to the source electrode of transistor 491. (or source region) of transistor 491. The transistor 491 is formed at the same time as the transistor 491. The low power supply wiring (conductor 482) and the high power supply wiring (conductor 483) are connected to each other. The electrodes 480 are arranged generally parallel to each other and overlap each other. The output signal OUT is , the drain electrode (or drain region) of transistor 490, transistor 490 and The drain electrode (or drain region) of the transistor is formed at the same time. The drain electrode (or drain region) of 491, or the transistor 491 is formed at the same time One or more of the drain electrodes (or drain regions) of the transistors to be fabricated The input signal IN is input to the gate electrode of transistor 490 or The gate electrode of the transistor formed at the same time as the transistor 490, the gate of the transistor 491 Electrode or one of the gate electrodes of a transistor formed at the same time as the transistor 491 One or more inputs are made.

[0054] The low power wiring (conductor 482) and the high power wiring (conductor 480) are overlapped with each other in a generally parallel manner. By being arranged in such a manner, the wiring has a large parasitic capacitance (also called wiring capacitance). As a result, by using this wiring as a power supply wiring, voltage fluctuations due to power supply noise can be reduced. The circuit is capable of suppressing the power supply voltage fluctuation and is resistant to power supply noise. In addition, in a semiconductor device to which the semiconductor device 500 (cell) is applied, In order to reduce fluctuations in the power supply voltage, a capacitive element may be intentionally provided in the power supply wiring. The low power supply wiring (conductor 482) and the high power supply wiring (conductor 480) have a large wiring capacitance. This allows the size of such a capacitance element to be reduced, which in turn allows the semiconductor device to be miniaturized. In addition, the low power supply wiring (conductor 482) and the high power supply wiring (conductor 480) By arranging the wirings so as to overlap each other, the area occupied by the wirings can be reduced, and The area of ​​the semiconductor device 500 (cell) can be reduced.

[0055] The low power supply wiring (conductor 482) and the high power supply wiring (conductor 480) are adjacent to each other in the vertical direction. It is preferable to use conductors for lines. It is preferable to use conductors for wiring adjacent to each other in the vertical direction. Therefore, the distance between the wires is small and the wires have a large capacitance. It is possible to realize a circuit that is resistant to noise and can reduce fluctuations in the power supply voltage. This makes it possible to miniaturize a semiconductor device to which the semiconductor device 500 (cell) is applied.

[0056] In addition, the wiring conductor A and the wiring conductor B are adjacent to each other in the vertical direction. When the conductor device has n layers of wiring conductors in order from the substrate side, wiring conductor A is the wiring conductor for the i-th layer, and wiring conductor B is the wiring conductor for the (i+1)-th layer. (i is an integer between 1 and (n-1) inclusive).

[0057] Alternatively, the low power wiring (conductor 482) and the high power wiring (conductor 480) are conductors of adjacent layers. Alternatively, in the semiconductor device 500 (cell), a low power supply wiring (conductive Between the high power supply wiring (conductor 482) and the high power supply wiring (conductor 480), there is no conductor overlapping them. It is preferable that there is no.

[0058] The transistors 490 and 491 are arranged on top of each other. As a result, This makes it possible to reduce the area of ​​the semiconductor device 500 (cell).

[0059] The transistor 490 and the transistor 491 overlap each other if, at least, The transistor 490 has a gate electrode, a drain electrode (or a drain region), or A part of the source electrode (or source region) of the transistor 491 is connected to the gate electrode, drain electrode (or drain region), or source electrode (or source region) ) of the transistor 490. A region including a drain electrode (or a drain region) and a source electrode (or a source region) A gate electrode and a drain electrode (or a drain region) of the transistor 491, and a region including a source electrode (or a source region) at least partially overlap with each other. Alternatively, a region including the components of the transistor 490 and a region including the components of the transistor 491 may be referred to as a region including the components of the transistor 490 and a region including the components of the transistor 491. This means that the region including the component overlaps at least partially with the region including the component.

[0060] The transistors 490 and 491 are arranged on top of each other. The direction of current flow in transistor 490 and the direction of current flow in transistor 491. The source electrode and gate electrode of the transistor 490 are generally parallel or antiparallel. The direction in which the source electrode, gate electrode, and drain electrode of the transistor 491 are arranged is shown in FIG. The direction in which the drain electrodes are aligned is generally parallel to the direction in which the drain electrodes are aligned. When the gate electrode of the transistor 490 is connected to the gate electrode of the transistor 491, The transistor 491 can be arranged in a small area including the connection part of the gate electrode. It is possible to reduce the area of ​​the device 500 (cell).

[0061] In addition, the transistor 491 or a transistor of the same type as the transistor 491 and the transistor By stacking a transistor 490 or a transistor of the same type as the transistor 490, a stack Compared to not using this, the area can be reduced, and the wiring length connecting the transistors can be shortened. As a result, it is possible to reduce the parasitic capacitance associated with the signal wiring. As a result, the operating speed of the semiconductor device 500 (cell) can be improved.

[0062] Transistor 490 is located above transistor 491. Conductor 482 is a conductive Conductor 482 is located above transistor 491.

[0063] In addition, part A being above part B means that part A is farther away from part B when viewed from the board side. Or, it means that part A is formed after part B. The term "position" includes regions, conductors, insulators, transistors, electrodes, etc. When the board has n layers of wiring conductors in order from the board side, part A is below conductor C. That is, part A is located between the wiring conductor of the i-th layer and the wiring conductor of the (i+1)-th layer. It is stated that the conductor C is a conductor for wiring from the (i+1)th layer or higher to the nth layer or lower. The part A is above the conductor C when the part A is above the conductor C and the conductor for the wiring of the i-th layer. 1) Between the conductors for wiring of the layer, and conductor C is for wiring of the first layer or higher and the i-th layer or lower This means that a conductor is used.

[0064] The transistors and power supply wirings of the semiconductor device 500 (cell) are arranged closely together. This allows the electronic circuit to be made smaller. The region (also called cell area) may be a rectangle with height Hcell and width Wcell. By the way, the wiring connecting the multiple cells includes wirings that extend in the height direction and are approximately perpendicular to each other. It is preferable to use at least a wire (conductor) extending in the width direction and a wiring (conductor) extending in the width direction. Let Px be the pitch of the wiring extending in the height direction, and Py be the pitch of the wiring extending in the width direction. Then, the cell height Hcell is an integer multiple of Py, and the cell width Wcell is an integer multiple of Px. In some cases, the cell area is twice as large as the conventional one. This makes it possible to efficiently connect cells. This can be done easily.

[0065] FIG. 39 is an example of a top view of an inverter circuit cell. A detailed explanation of the top view will be given later. Here, we will explain the cell area. In order to make it easier to understand, in Figure 39, The cell shown in FIG. 39 includes a transistor 490, a transistor The transistor 490 and the transistor 4 91. Conductor 480 and conductor 482 overlap. Its height is 6*Py and its width is 4*Px.

[0066] The above-mentioned semiconductor device 500 (cell) can reduce the cell area. For example, For inverter circuits, the cell height is preferably WW+WT+5*Py or less. More preferably, it can be set to WW+WT+4*Py or less, where WW is the power line width. WT is the maximum channel width of the multiple transistors in the semiconductor device 500 (cell). The channel width is 5*Px or less, and more preferably, 4*Px or less. In addition, for a small inverter, the cell height can be set to 6*Py or less. For example, in the case of a two-input NAND circuit, the cell height can be preferably set to should be WW+WT+7*Py or less, and more preferably WW+WT+5*Py or less. Also, the width of the cell is preferably 5*Px or less, more preferably 4*Px or less. It can be below.

[0067] It is also preferable that the heights of the cells are the same. By setting the height of a row as the height of the cell and arranging multiple cells in multiple rows, efficient placement and wiring can be achieved. can.

[0068] In order to densely arrange the transistors and power supply wirings of the semiconductor device 500 (cell), A source electrode or a drain electrode of the transistor 490 and a conductor functioning as a power supply wiring When (482) is electrically connected, the electrode and the conductor are provided on an insulator. It is preferable that the electrodes are directly connected to each other through a conductor (also called a via) provided in the opening. Alternatively, the connection is preferably made through a via and a conductor sandwiched between the vias. The source electrode or drain electrode of the transistor 491 and the conductor (48 0) is electrically connected to the electrode and the conductor through an opening provided in the insulator. It is preferable that the vias are directly connected to the vias through a conductor provided in the portion. It is preferable that the connection is made via a conductor sandwiched between the first and second electrodes.

[0069] In order to densely arrange the transistors and power supply wirings of the semiconductor device 500 (cell), The semiconductor device 500 (cell) includes a transistor 490 and a conductor ( 482), and a conductor (480) that functions as a transistor 491 and a power supply wiring It is preferable to have no transistor between the first and second gates.

[0070] The transistors and power supply wiring of the semiconductor device 500 (cell) are densely arranged, and In order to efficiently place a large number of cells, the power supply wiring is regularly placed at the edge of the cell area. In particular, the semiconductor device (cell) according to one embodiment of the present invention has one side of the cell area. The power supply wiring may be arranged only at the end of the cell area. In this case, the cell area can be made smaller than when a conventional 3D array is used.

[0071] A configuration example of a semiconductor device in which transistors are arranged and wired will be described with reference to FIG. The schematic diagram of the semiconductor device shown in FIG. 31 shows the semiconductor device 500 (cell) shown in FIG. A transistor 491, a high power supply wiring (conductor 480), a transistor 490, and a low 4 is a diagram showing a schematic representation of the positional relationship between the power supply wiring (conductor 482) and the.

[0072] In FIG. 31A, a semiconductor device 500 (cell) includes a transistor 491, a high power supply A line (conductor 480), a low power supply wiring (conductor 482), and a transistor 490 are stacked in this order. In other words, the high power supply wiring (conductor 480) is located above the transistor 491. A low power supply wiring (conductor 482) is disposed above the high power supply wiring (conductor 480). Also overlapping, transistor 490 is disposed above the low power supply wiring (conductor 482).

[0073] With this configuration, the low power supply wiring (conductor 482) and the high power supply wiring (conductor 48 0) is located close to the top and bottom, and therefore has a large wiring capacitance. It is possible to realize a circuit that is resistant to noise and can reduce fluctuations in the power supply voltage. It is possible to miniaturize a semiconductor device to which the semiconductor device 500 (cell) is applied.

[0074] In FIG. 31B, a semiconductor device 500 (cell) includes a transistor 491, a high power supply line A line (conductor 480), a transistor 490, and a low power wiring (conductor 482) are stacked in this order. In other words, the high power supply wiring (conductor 480) is located above the transistor 491. A transistor 490 is disposed above the high power supply wiring (conductor 480). A low power supply wiring (conductor 482) is disposed above resistor 490.

[0075] In the semiconductor device 500 (cell), the source electrode (or source The drain electrode (or drain region) is located above the transistor 490. In some cases, the semiconductor device has a structure in which the conductor is connected to only one of the conductors. The conductor is used for connection wiring between transistors in the device 500 (cell). However, it may be difficult to use the semiconductor device 500 as a connection wiring between multiple semiconductor devices 500 (cells). This is because the wiring positions are irregular in the connections between the multiple semiconductor devices 500 (cells). This is because the number of wirings that must be detoured increases if unusable areas are scattered. Even in such a case, the area is hardly increased, and the conductor can be used as a power supply wiring. This is because the power supply wiring is regularly arranged at the edge of the semiconductor device 500 (cell) region. In such a case, the power supply wiring (conductor 482) and the semiconductor device 5 The wiring between the transistors in the 00 (cell) can be made of the same conductor layer. This makes it possible to keep manufacturing costs low.

[0076] 2 to 4 and FIG. 19, the semiconductor device 500 (cell) of FIG. 1 will be described in more detail. The device structure will be described. The semiconductor device 501 (cell) shown in FIG. A transistor 490 and a transistor 491 are arranged corresponding to the device 500 (cell). It is a semiconductor device (cell) in which a semiconductor device is wired.

[0077] 2 is a schematic diagram showing an example of the configuration of a semiconductor device 501 (cell). In order to make it easier to understand, some of the insulators and other parts are omitted in Fig. 3. The conductors and other elements that are included in the circuit are marked with the same hatching pattern.

[0078] FIG. 3 is a top view showing an example of the configuration of a semiconductor device 501 (cell). FIG. 3(A) shows In the semiconductor device 501 (cell), a region including the transistor 491 and the conductor 480 FIG. 3B shows a top view of a semiconductor device 501 (cell), in which a transistor 490 4 shows a top view of an area including conductor 482 and conductor 484.

[0079] FIG. 4 is a cross-sectional view showing an example of the configuration of a semiconductor device 501 (cell). 3(A) and 3(B) are cross-sectional views taken along dashed line A1-A2 in FIG. 3(A) and FIG. 3(B), 3A and 3B show cross sections taken along dashed line B1-B2 in FIG.

[0080] The semiconductor device 501 (cell) has a transistor 491 and a transistor 490. 9. In the CMOS inverter circuit, the output signal O UT is the inverted signal of the input signal IN. In this embodiment, a p-channel transistor having a high speed can be used. The following description will be given assuming that a channel-type Si transistor is used. A fast n-channel transistor can be used as the transistor 490. In the embodiment, an oxide semiconductor (preferably an oxide containing In, Ga, and Zn) is used as a channel. The transistor included in the loop formation region will be described as the transistor 490.

[0081] The semiconductor device 501 (cell) includes a transistor 491, a conductor 480, and a transistor 490, a conductor 482, and conductors 424a and 424b. The transistor 90 and the transistor 491 are stacked. The conductor 482 and the conductor 480 are stacked. The transistor 491 includes a region 476a, a region 476b, and a conductor 454. The transistor 490 has a conductor 416 a , a conductor 416 b , and a conductor 404 .

[0082] The semiconductor device 501 (cell) includes a conductor 484. The transistor 490 includes a conductor It has 413.

[0083] The conductor 482 functions as a wiring (low power supply wiring) that supplies a low power supply voltage (VSS). The conductor 480 serves as a wiring (high power supply wiring) for supplying a high power supply voltage (VDD). The region 476a and the region 476b are the source electrode ( or source region) and drain electrode (or drain region) as one and the other The conductor 454 functions as a gate electrode of the transistor 491. The conductors 416a and 416b are connected to the source electrode (or source The gate electrode (or drain region) and the drain electrode (or drain region) function as one and the other. The conductor 404 functions as a gate electrode of the transistor 490.

[0084] The conductor 413 functions as a gate electrode of the transistor 490. A wiring 4 functions as a wiring for supplying a voltage to a gate electrode of a transistor 490.

[0085] Note that the conductor 413 and the conductor 404 are both gate electrodes of the transistor 490. Although they have the same function, the potentials applied to each may be different. By applying a negative or positive gate voltage to the capacitor 413, the threshold voltage of the transistor 490 is increased. You can adjust the pressure.

[0086] The high voltage wiring (conductor 480) is connected to the source region (region 476a) of transistor 491. The low power supply wiring (conductor 482) is electrically connected to the source electrode of transistor 490. (conductor 416a). The high power supply wiring (conductor 480) and the low power supply wiring ( The conductors 482 are arranged generally parallel to each other. The gate electrode (conductor 404) of the transistor 491 and the gate electrode (conductor 454) of the transistor 491 are electrically The drain electrode (conductor 416b) of transistor 490 and the The output signal OUT is electrically connected to the drain region (region 476b) of the transistor 491. The drain electrode (conductor 416b) of transistor 490 and the drain electrode (conductor 416c) of transistor 491 are connected to each other. Conductor 4 located above conductor 416b is connected to the drain region (region 476b). The input signal IN is input to the gate electrode (conducting A conductive body 404) and a gate electrode (conductor 454) of the transistor 491 are connected to the conductive body 404. The signal is input from the outside via the conductor 424b located above the body 404.

[0087] The gate electrode (conductor 413) of the transistor 490 is connected to a wiring (conductor The wiring (conductor 484) that supplies the gate voltage and the low-voltage The source wiring (conductor 482) is disposed generally parallel to and overlapping with each other.

[0088] The low power wiring (conductor 482) and the high power wiring (conductor 480) are overlapped with each other in a generally parallel manner. By being arranged in such a manner, the wiring has a large parasitic capacitance (also called wiring capacitance). As a result, by using this wiring as a power supply wiring, voltage fluctuations due to power supply noise can be reduced. The circuit is capable of suppressing the power supply voltage fluctuation and is resistant to power supply noise. In addition, in a semiconductor device to which the semiconductor device 501 (cell) is applied, In order to reduce fluctuations in the power supply voltage, a capacitive element may be intentionally provided in the power supply wiring. The low power supply wiring (conductor 482) and the high power supply wiring (conductor 480) have a large wiring capacitance. As a result, the semiconductor device 501 ( It is possible to miniaturize a semiconductor device using low power wiring (conductor 4). 82) and the high power supply wiring (conductor 480) are arranged to overlap each other, The occupied area can be reduced, and the surface area of ​​the semiconductor device to which the semiconductor device 501 (cell) is applied The product can be made smaller.

[0089] The high power supply wiring (conductor 480) and the low power supply wiring (conductor 482) are adjacent to each other in the vertical direction. By using conductors for wiring adjacent to each other in the vertical direction, As a result, the distance between the wirings is small and the wiring has a large wiring capacitance. It is possible to realize a circuit that is resistant to noise and can reduce fluctuations in the power supply voltage. In addition, it is possible to reduce the size of a semiconductor device to which the semiconductor device 501 (cell) is applied.

[0090] Alternatively, the low power wiring (conductor 482) and the high power wiring (conductor 480) are conductors of adjacent layers. Alternatively, a low power supply wiring (conductor 482) and a high power supply wiring (conductor It is preferable to have no conductors between the electrodes 480.

[0091] The transistors 490 and 491 are arranged on top of each other. As a result, This makes it possible to reduce the area of ​​the semiconductor device 501 (cell).

[0092] The transistors 490 and 491 are arranged on top of each other. The direction of current flow in transistor 490 and the direction of current flow in transistor 491. The source electrode and gate electrode of the transistor 490 are generally parallel or antiparallel. The direction in which the source electrode, gate electrode, and drain electrode of the transistor 491 are arranged is shown in FIG. The direction in which the drain electrodes are aligned is generally parallel to the direction in which the drain electrodes are aligned. The drain electrode of the transistor 491 can be arranged close to each other. The gate electrode of the transistor 490 and the gate electrode of the transistor 491 are connected to each other. In this way, the transistor 490 can be arranged in close proximity to the The drain electrode of the transistor 491 is connected to the drain electrode of the transistor 49 When the gate electrode of transistor 491 is connected to the gate electrode of transistor 492, the area of ​​the connection region is 5, and the area of ​​the semiconductor device 501 (cell) can be reduced.

[0093] The direction of current flow in transistor 490 (or the source of transistor 490) The direction in which the gate electrode, gate electrode, and drain electrode are aligned) and the low power supply wiring (conductor 482) The extension direction is generally parallel to the source electrode and the drain electrode of the transistor 490. Even if the electrodes are swapped, the source electrode and the low power supply wiring (conductor 482) are short. The direction of current flow in the transistor 491 is preferably the same as that in the transistor 491. (Alternatively, the source electrode, gate electrode, and drain electrode of the transistor 491 are arranged in the same manner. The direction of the high-voltage power supply wiring (conductor 480) is generally parallel to the direction of the high-voltage power supply wiring (conductor 480). The source electrode of the transistor 491 is connected to the high power supply wiring regardless of which side of the gate electrode the source electrode is located on. (conductor 480) can be connected by a short wire, which is preferable.

[0094] Note that the direction of current flow in the transistor 490 (or the direction of the The direction in which the source electrode, gate electrode, and drain electrode are aligned) and the low power supply wiring (conductor 48 The source electrode of the transistor 490 may be a low-voltage When connecting to the power supply wiring (conductor 482), the source electrode is arranged so as to overlap with the low power supply wiring. This is preferable because it is possible to reduce the area. The direction of current flow (or the source electrode, gate electrode, and drain electrode of transistor 491) The direction in which the power supply wiring (conductor 480) extends is generally perpendicular to the direction in which the power supply electrodes are arranged. When the source electrode of the transistor 491 is connected to the high power supply wiring (conductor 480), The source electrode can be arranged so as to overlap with the high power supply wiring, thereby reducing the area. Therefore, it is preferable.

[0095] In addition, when the input / output terminals are connected to adjacent cells or nearby cells, the output signal The output terminal OUT is connected to the drain electrode ( conductor 416b) or the drain region (region 476b) of transistor 491 directly adjacent The input terminal of the input signal IN may be connected to the input terminal of the cell that matches the input terminal of the input signal IN. The terminal is connected to the gate electrode of transistor 490 (conductor 404) without passing through conductor 424b. Alternatively, the gate electrode (conductor 454) of the transistor 491 may be directly connected to an adjacent cell or It may also be connected to the output terminal of the adjacent cell.

[0096] In FIG. 2, a semiconductor device 501 (cell) includes a transistor 491, a high-voltage power supply wiring (conductive A low power supply wiring (conductor 480), a conductor 482, and a transistor 490 are arranged in this order. In other words, the high power supply wiring (conductor 48) is stacked above the transistor 491. 0) is arranged, and a low power supply wiring (conductor 482) is arranged above the high power supply wiring (conductor 480). A conductor 484 is placed above and overlaps the low power supply wiring (conductor 482). A transistor 490 is disposed above the conductor 484 .

[0097] The source electrode (or source region) of transistor 491 is connected to the high power supply wiring (conductor 48 0), the source electrode (or source region) of transistor 491 is connected to When the power supply wiring (conductor 480) is connected to the low power supply wiring (conductor 482) arranged above the power supply wiring (conductor 480), The source electrode (or source region) of the transistor 490 is preferably Since the low power supply wiring (conductor 482) is connected to the low power supply wiring (conductor 483), the source voltage of transistor 490 is A high power line whose pole (or source region) is located below a low power line (conductor 482). This is easier and more preferable than connecting to (conductor 480).

[0098] In addition, in the semiconductor device 501 (cell), the high power supply wiring (conductor 480) and the low power supply wiring The width of each line (conductor 482) is equal to the width of the gate electrode (conductor 45 4) the gate electrode (conductor 404) of the transistor 490, or the gate electrode for transferring input / output signals It is preferable that the width of the wiring is wider than that of the signal wiring. The width of each low power supply wiring (conductor 482) is the same as that of the wiring (conductor) connected to the input terminal. It is preferable that the width of the power supply wiring is wider than the width of the wiring (conductor) connected to the output terminal. In general, a larger current flows through the wiring than through the signal wiring, and it is preferable to make the wiring resistance lower than that of the signal wiring. This is because it is desirable.

[0099] In addition, in the semiconductor device 501 (cell), the high power supply wiring (conductor 480) and the low power supply wiring The width of the overlapping area of ​​the line (conductor 482) is 4) the gate electrode (conductor 404) of the transistor 490, or the gate electrode for transferring input / output signals It is preferable that the width of the wiring is wider than that of the signal wiring. The width of the area where the low power supply wiring (conductor 482) overlaps is the width of the wiring (conductor) connected to the input terminal. It is preferable that the width of the wiring (conductor) connected to the output terminal is larger than that of the wiring (conductor).

[0100] A more detailed explanation will be given with reference to the cross-sectional view of the semiconductor device shown in FIG.

[0101] The semiconductor device 501 (cell) shown in FIG. 4 includes a transistor 491 and a transistor 491 The insulator 442 is disposed on the semiconductor device 100 and the transistor 490 is disposed on the insulator 442. 442 is preferably an insulator that has the function of blocking oxygen and hydrogen.

[0102] The transistor 491 is formed by an insulator 462 on a semiconductor substrate 400 and a conductive layer on the insulator 462. The conductive body 454, the insulator 470 in contact with the side of the conductive body 454, and the conductive body in the semiconductor substrate 400 454 and insulator 470 do not overlap with regions 476a and 476b, and insulator 4 and region 474 which is an overlapping region with 70.

[0103] The semiconductor substrate 400 may be, for example, a single semiconductor such as silicon, germanium, or a carbide. Silicon, silicon germanium, gallium arsenide, gallium nitride, indium phosphide, oxide A compound semiconductor such as zinc oxide or gallium oxide may be used for the semiconductor substrate 400. An amorphous semiconductor or a crystalline semiconductor may be used. As the crystalline semiconductor, a single crystal semiconductor , polycrystalline semiconductors, and microcrystalline semiconductors.

[0104] The insulator 462 functions as a gate insulator of the transistor 491. The insulator 454 functions as a gate electrode of the transistor 491. 70 functions as a sidewall insulator (also called a sidewall) of the conductor 454. Regions 476a and 476b are the source and drain regions of transistor 491. The region 474 also functions as an LDD (Light Diode) region of the transistor 491. The MTJ region functions as a truly doped drain region.

[0105] The region 474 can be formed by doping impurities using the conductor 454 as a mask. Then, the insulator 470 is formed, and the conductor 454 and the insulator 470 are mass-produced. Regions 476a and 476b can be formed by implanting impurities at the same time. When the region 474 and the regions 476a and 476b are formed by adding the same type of impurity, Therefore, region 474 has a lower impurity concentration than regions 476a and 476b.

[0106] Transistor 491 suppresses short channel effects by including region 474. Therefore, it is clear that this structure is suitable for miniaturization.

[0107] The transistor 491 is connected to the other transistors provided on the semiconductor substrate 400 and the insulator 4 60. In FIG. 4, the insulator 460 is an STI (sealing insulating film). This shows an example of a method called low trench isolation. For example, the insulator 460 may be replaced with a local oxide (LOCOS). The transistor was fabricated using an insulator formed by the ionization of silicon method. It is okay to separate the two.

[0108] The transistor 490 includes a conductor 413, an insulator 402 on the conductor 413, and an insulator 404. 02, a semiconductor 406a on the semiconductor 406a, and a semiconductor 406b on the semiconductor 406a. The conductor 416a and the conductor 416b contact the upper surface and the side surface of the semiconductor 406b. 16b, the side surface of the semiconductor 406a, the top surface and side surface of the semiconductor 406b, and the conductor 416a a semiconductor 406c in contact with the top and side surfaces of the conductor 416b and the top and side surfaces of the conductor 416b; The semiconductor 406c includes an insulator 412 on the semiconductor 406c and a conductor 404 on the insulator 412. Here, the conductor 413 is part of the transistor 490, but is not limited thereto. For example, the conductor 413 may be a separate component from the transistor 490. stomach.

[0109] The conductor 413 functions as a gate electrode of the transistor 490. Conductor 402 serves as a gate insulator for transistor 490. 16a and conductor 416b are connected to the source and drain electrodes of transistor 490. The insulator 412 also functions as a gate insulator for the transistor 490. The conductor 404 also functions as a gate electrode of the transistor 490. has.

[0110] As shown in FIG. 4, the conductor 416a and the conductor 416b are in contact with the side surface of the semiconductor 406b. The conductor 404 electrically surrounds the semiconductor 406b in the channel width direction. The structure is such that the semiconductor 406b is surrounded not only on the top surface but also on the sides. This type of transistor structure is called the surrounded channel (s-channel) This is called annular structure. It is preferable that the conductor 404 is structured so as to extend to below the semiconductor 406b. .

[0111] By making the transistor have an s-channel structure, In contrast, it becomes easier to control the channel formation region by the gate electric field. The structure extending below 406b provides even better control. The subthreshold swing value (also called S value) of the photodiode 490 can be reduced. The off-state current of transistor 490 can be reduced.

[0112] By using this structure, good electrical characteristics can be obtained even in miniaturized transistors. As transistors become smaller, semiconductor devices having such transistors can be highly integrated. In this way, a highly dense semiconductor device can be obtained. The amount of capacitance is reduced, resulting in better switching characteristics. For example, transistor 490 has The channel length is preferably 40 nm or less, more preferably 30 nm or less, and even more preferably The transistor 490 has a channel width of preferably 4 0 nm or less, more preferably 30 nm or less, and even more preferably 20 nm or less. do.

[0113] When the transistor 490 has an s-channel structure, the semiconductor 406b A channel may be formed throughout the bulk. Therefore, the thicker the semiconductor 406b, The channel forming region is large. For example, it is 20 nm or more, preferably 40 nm or more, and Preferably, the semiconductor has a region having a thickness of 60 nm or more, more preferably 100 nm or more. However, since the productivity of the semiconductor device may decrease, for example, , 300 nm or less, preferably 200 nm or less, more preferably 150 nm or less By using such a structure, the s-channel In the n-type transistor, a large current can flow between the source and drain of the transistor, and the The current (on-state current) can be increased.

[0114] In addition, at least a portion (or (all of which are referenced herein) may be used to describe the surface, side, top, and / or bottom of a semiconductor layer, such as semiconductor 406b. The semiconductor 406b is in contact with at least a part (or the entirety) of the surface. In n-type quartz, hydrogen can enter the oxygen vacancy site to form a donor level, The state in which hydrogen enters the oxygen vacancy site is called the V O H and table As a result, current flows through the n-channel conductive region, resulting in good on-state A current can be obtained.

[0115] In addition, as an oxide semiconductor, CAAC-OS (C Axis Aligned-Oxide Semiconductor) Crystalline Oxide Semiconductor) CAAC-OS is one of the oxide semiconductors having multiple crystal parts aligned along the c-axis. In particular, it is preferable to increase the CAAC ratio, which will be described later. The CAAC ratio is the ratio of the area in which the CAAC-OS diffraction pattern is observed in the range. Increasing the rate can result in fewer defects, for example. It is possible to reduce rear scattering. It also realizes CAAC-OS with few impurities. For example, it is possible to realize extremely low off-current characteristics. In the case of AAC-OS, the CAAC ratio is 50% or more, preferably 80% or more, and more preferably Preferably, the ratio is 90% or more, and more preferably, 95% or more and 100% or less.

[0116] In addition, the impurity concentration in the semiconductor 406b is reduced to make the oxide semiconductor intrinsic or substantially intrinsic. Here, the term "substantially intrinsic" means that the carrier density of the oxide semiconductor is , 1×10 17 / cm 3 Preferably less than 1 × 10 15 / cm 3 Less than and more preferably 1×10 13 / cm 3 In oxide semiconductors, Therefore, hydrogen, nitrogen, carbon, silicon, and metal elements other than the main components are considered impurities. For example, Hydrogen and nitrogen contribute to the formation of donor levels in oxide semiconductors and increase the carrier density. In addition, silicon forms an impurity level in the oxide semiconductor. .

[0117] A transistor using a substantially intrinsic oxide semiconductor has a capacitance in a channel formation region. Since the rear density is low, the threshold voltage is rarely negative. In addition, a transistor using the oxide semiconductor has fewer carrier traps in the oxide semiconductor. Therefore, the change in electrical characteristics is small, resulting in a highly reliable transistor. A transistor using a conductor can have a very low off-state current.

[0118] For example, the drain current of a transistor using an oxide semiconductor in an off state is (at about 25°C) 1×10 -18 A or less, preferably 1×10 -21 A or below, even better Preferably 1×10 -24 A or less, or 1 x 10 at 85°C -15 A or less, preferably 1 ×10 -18 A or less, more preferably 1×10 -21 A or less. In the case of an n-channel transistor, the transistor is in the off state when the gate voltage is at a threshold. Specifically, the gate voltage is 1V or more lower than the threshold voltage. If the voltage is more than 2 V or more than 3 V lower, the transistor is turned off.

[0119] In addition, when the transistor 490 is an accumulation type transistor in which electrons are the majority carriers, the semiconductor 40 The electric field extending from the region in contact with the source electrode and drain electrode of 6b to the channel is short. Because the transistor is shielded, carriers can be controlled by the gate electric field even if the channel is short. Cheap.

[0120] In addition, by forming a transistor on an insulating surface, the semiconductor substrate can be used as a channel Unlike when the gate electrode is used as a gate electrode, a parasitic capacitance is formed between the gate electrode and the semiconductor substrate. This makes it easier to control carriers using the gate electric field.

[0121] By using such a structure, good electrical properties can be obtained. It has excellent threshold characteristics, extremely small off-current, and good on-current. Switching characteristics are obtained.

[0122] The above three-layer structure is an example. For example, a two-layer structure without semiconductor 406a or semiconductor 406c Alternatively, the semiconductor 406 may be formed on or under the semiconductor 406a, or on or under the semiconductor 406. c, the semiconductor 406a, the semiconductor 406, and the semiconductor 406c are illustrated. Alternatively, the semiconductor 406 may be a four-layer structure having any one of the semiconductors. Either above the body 406a, below the semiconductor 406a, above the semiconductor 406c, or below the semiconductor 406c. At least two of the semiconductors 406a, 406b, and 406c are illustrated. It may have an n-layer structure (n is an integer of 5 or more) including any one of the semiconductors.

[0123] Note that the insulator 402 is preferably an insulator containing excess oxygen.

[0124] For example, an insulator containing excess oxygen can be used as an insulator that has the function of releasing oxygen by heat treatment. For example, silicon oxide containing excess oxygen releases oxygen when heated. Therefore, the insulator 402 is an insulating material through which oxygen can move. That is, the insulator 402 may be an insulator having oxygen permeability. For example, The insulator 402 may be an insulator having higher oxygen permeability than the semiconductor 406a.

[0125] The insulator containing excess oxygen may have a function of reducing oxygen vacancies in the semiconductor 406b. In the semiconductor 406b, oxygen vacancies form DOS, which become hole traps, etc. In addition, hydrogen can enter the oxygen vacancy site, generating electrons as carriers. Therefore, by reducing oxygen vacancies in the semiconductor 406b, the transistor 490 can be stably It is possible to impart the desired electrical properties.

[0126] The insulator 442 shown in FIG. 4 is between the transistor 491 and the transistor 490. The insulator 442 is, for example, an oxide containing aluminum, for example, oxide Aluminum is used. The insulator 442 is an insulator that blocks oxygen and hydrogen. , density 3.2g / cm 3 Aluminum oxide with less than 100% water is particularly effective at blocking hydrogen. Aluminum oxide with low crystallinity is particularly preferred because it has a function of blocking hydrogen. It is preferred because of its high efficiency.

[0127] For example, when the transistor 491 is a silicon transistor, hydrogen is introduced into the outside. By supplying the silicon from the The electrical characteristics of the transistor may be improved. Alternatively, for example, the insulator containing hydrogen may be The hydrogen is diffused by placing the hydrogen in the vicinity of the transistor 491 and performing a heat treatment. Specifically, the insulator 464 on the transistor 491 may supply hydrogen to the transistor 491. The insulator 464 may have a single-layer structure or a multi-layer structure. For example, silicon oxynitride or silicon oxide and silicon nitride oxide or nitride A stacked layer structure including silicon nitride and a silicon carbide may be used as the insulator 464.

[0128] For example, insulators containing hydrogen are heated to temperatures between 100°C and 700°C or 10 1×10 in the surface temperature range of 0℃ to 500℃ 18 atoms / cm 3 That's it, 1×1 0 19 atoms / cm 3 or more than 1×10 20 atoms / cm 3 More than hydrogen (hydrogen In some cases, the electrons emitted may be equivalent to the number of atoms.

[0129] By the way, hydrogen diffused from the insulator 464 is absorbed by the conductive material provided at the opening of the insulator 464. Through the body 471, the conductor 480 on the insulator 464, the conductor 482 on the conductor 480, etc. However, the insulator 442 blocks the hydrogen. Because of this function, only a small amount of hydrogen reaches the transistor 490. In the oxide semiconductor, it becomes a carrier trap or a carrier source, and the electrical characteristics of the transistor 490 Therefore, blocking hydrogen with the insulator 442 is not practical. This has important implications for improving the performance and reliability of semiconductor devices.

[0130] On the other hand, for example, when oxygen is supplied to the transistor 490 from the outside, Since oxygen vacancies can be reduced, the electrical characteristics of the transistor may be improved. The supply of oxygen may be performed, for example, by a heat treatment in an atmosphere containing oxygen. Alternatively, for example, an insulator containing excess oxygen (oxygen) is placed near the transistor 490 and heated. The oxygen may be diffused by heat treatment and supplied to the transistor 490 . Here, the insulator 402 of the transistor 490 is an insulator containing excess oxygen.

[0131] The diffused oxygen may reach the transistor 491 through each layer, but the insulator Since 442 has a function of blocking oxygen, the oxygen reaching the transistor 491 If the transistor 491 is a silicon transistor, The inclusion of oxygen in silicon reduces the crystallinity of silicon and inhibits the movement of carriers. Therefore, the insulator 442 is used to block oxygen. This is important for improving the performance and reliability of semiconductor devices.

[0132] In addition, in FIG. 4 and the like, the semiconductor device has an insulator 408 over a transistor 490. It is preferable that the insulator 408 has a function of blocking oxygen and hydrogen. For example, see the description of the insulator 442. Alternatively, the insulator 408 may be, for example, For example, the semiconductor 406a and / or the semiconductor 406c may have a higher blocking ability to block oxygen and hydrogen than the semiconductor 406a and / or the semiconductor 406c. It has high performance.

[0133] The semiconductor device includes an insulator 408, which prevents oxygen from diffusing out of the transistor 490. Therefore, the amount of excess oxygen (oxygen) contained in the insulator 402 can be suppressed. Therefore, oxygen can be effectively supplied to the transistor 490. Impurities including hydrogen from layers provided above the insulator 408 or from the outside of the semiconductor device In order to block the material, the electrical characteristics of the transistor 490 are degraded by the inclusion of impurities. This can be suppressed.

[0134] For convenience, the insulator 442 and / or the insulator 408 are distinguished from the transistor 490. However, it may be a part of the transistor 490.

[0135] In the cross-sectional view shown in FIG. 4, the semiconductor device 501 (cell) includes a transistor 49 0 and a multi-layer wiring conductor connected to transistor 491. The conductive body is located on an insulator 464 provided on a transistor 491, and is connected to a high power wiring (conductive The transistor 491 and the first layer conductor are provided in an insulator 464. The second layer may be connected through a conductor 471 (also called a via) provided in the opening. The conductor is located on an insulator 465 provided on the first layer conductor, and the low power wiring (conductive The first layer conductor and the second layer conductor are connected to an opening in an insulator 465. The third layer may be connected through a conductor 472 (also called a via) provided at the opening. The conductor is located on an insulator 466 that is disposed on the second layer of conductor and provides the gate voltage. The second layer conductor and the third layer conductor are provided in an insulator 466. The connection may be made through a conductor 473 (also called a via) provided in the opening. The insulator 442 is located on the insulator 467 provided on the third layer conductor. On top of this are conductor 413 and transistor 490. The insulator 408 is disposed on the conductor 490, and the conductor 424a is disposed on the insulator 468. The third and fourth layers of conductors are provided in the insulators 408 and 468. A conductor 475 (also called a via) is provided in the opening, and the drain of a transistor 490 is connected to the The fourth layer may be connected via the in-electrode (conductor 416b). An insulating layer may be provided on the insulating layer, on which one or more layers of conductors may be further provided. The conductors may be provided between the semiconductor devices (cells). In the configuration example shown in FIG. Three conductor layers are provided between the transistor 490 and the transistor 491. The structure of the semiconductor device (cell) is not limited to this. Between the resistors 491, one to ten layers of conductors may be provided.

[0136] The structure of the transistor 491 is not limited to the structure shown in FIG. As shown in FIG. 4, a transistor 491 has a protruding portion (also called a protrusion, a fin, or the like) on a semiconductor substrate 400. The structure of the transistor 491 shown in FIG. Compared with the structure of transistor 491 shown in FIG. 4, the effective channel for the same occupancy area is Therefore, the current of the transistor 491 when it is turned on can be increased. In addition, the conductor 454 can reduce the thickness of the protruding portion of the semiconductor substrate 400 in the channel width direction. This structure surrounds the gate, making it easier to control the channel formation region using the gate electric field. As a result, it has become possible to suppress the short channel effect, and it has been found that this structure is suitable for miniaturization. Light.

[0137] Alternatively, for example, a transistor 491 shown in FIG. 6 may be formed by forming an insulator on a semiconductor substrate 400. A structure in which the region 452 is provided may be used. This provides more reliable isolation between the individually operating transistors, reducing leakage currents. In addition, it is possible to suppress the parasitic capacitance formed between the substrate and the device and the leakage current to the substrate. As a result, the leakage current of the transistor 491 can be reduced. In addition, the transistor 491 can operate at high speed and with low power consumption.

[0138] The p-channel Si transistor described above provides good switching speed. For example, the switching speed of the transistor is less than 10 ns, preferably less than 1 ns. The time is preferably less than 0.1 ns. Transistors in the region have good switching speeds. The switching speed of the capacitor is less than 10 ns, preferably less than 1 ns, and more preferably less than 0.5 ns. The transistor 491 is a p-channel type Si transistor as described above. The transistor 490 is a transistor including the above-described oxide semiconductor in a channel formation region. By using the transistor, the operation speed of the semiconductor device (cell) according to one embodiment of the present invention can be improved. For example, an inverter which is a semiconductor device (cell) according to one embodiment of the present invention The delay time of the two-input NAND circuit is less than 10 ns, preferably less than 1 ns, and more preferably Most of the time it is less than 0.1 ns.

[0139] In addition, a transistor including an oxide semiconductor has an extremely small off-state current; therefore, It is possible to provide a semiconductor device with small leakage current (or DC leakage current). In particular, during the period when the input signal is low or the power supply voltage is low, the input signal Even if the gate electrode of a transistor using an oxide semiconductor is The transistor is turned off, and the leakage current through the transistor including an oxide semiconductor is extremely small. As a result, a semiconductor device capable of reducing power consumption can be provided. This becomes possible.

[0140] In addition, the transistor 491 or a transistor formed at the same time as the transistor 491 It is preferable to use only p-channel Si transistors. In the manufacturing process of the transistor, there is no need to manufacture n-channel Si transistors, It is possible to keep costs low. In particular, for miniaturized transistors, n-channel Si The manufacturing processes for p-channel Si transistors and p-channel Si transistors are optimized differently. Therefore, the manufacturing cost can be reduced by not manufacturing n-channel Si transistors. In addition, when manufacturing only p-channel Si transistors, the silicon substrate The surface orientation of the plate is suitable for p-channel transistors, e.g., to provide high mobility. For example, the surface orientation of a silicon substrate can be selected from Si It can be a (110) plane.

[0141] (Embodiment 2) The semiconductor device according to one embodiment of the present invention is not limited to the structures shown in FIGS. In the embodiment, an example of a semiconductor device according to one embodiment of the present invention will be described with reference to FIGS. The semiconductor device 502 (cell) shown in FIG. 7 corresponds to the semiconductor device 500 (cell) shown in FIG. A transistor 490 and a transistor 491 are arranged and wired cells.

[0142] 7 is a schematic diagram showing an example of the configuration of a semiconductor device 502 (cell). In order to facilitate understanding, some of the insulators and other parts are omitted in FIG. The conductors and other elements that are included in the circuit are marked with the same hatching pattern.

[0143] FIG. 8 is a top view showing an example of the configuration of a semiconductor device 502 (cell). FIG. 8(A) shows 5 is a top view of a region of a semiconductor device 502 including a transistor 491 and a conductor 480. 8B shows a semiconductor device 502 including a transistor 490 and a conductor 482. 1 shows a top view of an area including

[0144] FIG. 9 is a cross-sectional view showing an example of the configuration of a semiconductor device 502 (cell). 8(A) and 8(B) are cross-sectional views taken along dashed line A1-A2 in FIG. 8(A) and FIG. 8(B), 8 shows a cross section taken along dashed line B1-B2 in FIG. 8(A) and FIG. 8(B).

[0145] In FIG. 7, a semiconductor device 502 (cell) includes a transistor 491, a high-voltage power supply wiring (conductive A low power supply wiring (conductor 480), a low power supply wiring (conductor 482), and a transistor 490 are stacked in this order. In other words, the high power supply wiring (conductor 480) is disposed above the transistor 491. A low power supply wiring (conductor 482) is disposed above and overlaps a high power supply wiring (conductor 480). Thus, a transistor 490 is disposed above the low power supply wiring (conductor 482).

[0146] The source electrode (or source region) of transistor 491 is connected to the high power supply wiring (conductor 48 0), the source electrode (or source region) of transistor 491 is connected to When the power supply wiring (conductor 480) is connected to the low power supply wiring (conductor 482) arranged above the power supply wiring (conductor 480), The source electrode (or source region) of the transistor 490 is preferably Since the low power supply wiring (conductor 482) is connected to the low power supply wiring (conductor 483), the source voltage of transistor 490 is A high power line whose pole (or source region) is located below a low power line (conductor 482). This is easier and more preferable than connecting to (conductor 480).

[0147] In the semiconductor device 502 (cell), the high power supply wiring (conductor 480) and the low power supply wiring The width of each of the lines (conductors 482) is equal to the width of the gate electrode (conductors 45 4) the gate electrode (conductor 404) of the transistor 490, or the gate electrode for transferring input / output signals It is preferable that the width of the wiring is wider than that of the signal wiring. The width of each low power supply wiring (conductor 482) is the same as that of the wiring (conductor) connected to the input terminal. It is preferable that the width of the power supply wiring is wider than the width of the wiring (conductor) connected to the output terminal. In general, a larger current flows through the wiring than through the signal wiring, and it is preferable to make the wiring resistance lower than that of the signal wiring. This is because it is desirable.

[0148] In FIG. 2 to FIG. 6, the transistor 490 has a conductor 413 having a function of a gate electrode. However, the structure of the semiconductor device according to one embodiment of the present invention is not limited to this example. As shown in FIG. 9, the transistor 490 does not necessarily have to include the conductor 413. In addition, the semiconductor device 502 (cell) does not have a conductor 484 that supplies a voltage to the conductor 413. By adopting such a structure, the conductive layer for forming the conductor 484 may be is not necessary, which reduces the manufacturing cost.

[0149] 2 to 6, the gate electrode (conductor 404) of the transistor 490 and the transistor The gate electrode (conductor 454) of 491 and the conductor 424 located above the conductor 404 are However, the structure of the semiconductor device (cell) according to one embodiment of the present invention may be As shown in FIG. 7 to FIG. 9, the conductor 404 and the conductor 454 are The current is transferred only through the conductor located between the conductor 404 and the conductor 454, without passing through the conductor 424b. By using such a structure, the gate voltage of the transistor 490 The area connecting the electrode and the gate electrode of the transistor 491 can be made smaller. As a result, the semiconductor device 502 (cell) can be made smaller.

[0150] (Embodiment 3) The semiconductor device according to one embodiment of the present invention is not limited to the structures shown in FIGS. In the embodiment, an example of a semiconductor device according to one embodiment of the present invention will be described with reference to FIGS. The semiconductor device 503 (cell) shown in FIG. 10 is the same as the semiconductor device 500 (cell) shown in FIG. A transistor 490 and a transistor 491 are arranged and wired in the cell corresponding to the .

[0151] FIG. 10 is a schematic diagram showing an example of the configuration of a semiconductor device 503 (cell). In order to make it easier to understand, some of the insulators and other parts are omitted in Figures 1 and 11. The conductors etc. that are formed are given the same hatching pattern.

[0152] FIG. 11 is a top view showing an example of the configuration of a semiconductor device 503 (cell). In the semiconductor device 503, the upper surface of a region including the transistor 491 and the conductor 480 is FIG. 11B shows a semiconductor device 503 (cell) including a transistor 490 and a A top view of an area including conductor 482 is shown.

[0153] 12 is a cross-sectional view showing an example of the configuration of a semiconductor device 503 (cell). 11(A) and 11(B) are cross-sectional views taken along dashed line A1-A2. On the right side of the figure, a cross section taken along the dashed line B1-B2 in Figures 11(A) and 11(B) is shown. show.

[0154] In FIG. 10, a semiconductor device 503 (cell) includes a transistor 491, a high power supply wiring (conductor A low power supply wiring (conductor 480), a low power supply wiring (conductor 482), and a transistor 490 are stacked in this order. In other words, the high power supply wiring (conductor 480) is disposed above the transistor 491. The low power supply wiring (conductor 482) is disposed above and overlaps the high power supply wiring (conductor 480). A transistor 490 is disposed above the low power supply wiring (conductor 482).

[0155] The source electrode (or source region) of transistor 491 is connected to the high power supply wiring (conductor 48 0), the source electrode (or source region) of transistor 491 is connected to When the power supply wiring (conductor 480) is connected to the low power supply wiring (conductor 482) arranged above the power supply wiring (conductor 480), The source electrode (or source region) of the transistor 490 is preferably Since the low power supply wiring (conductor 482) is connected to the low power supply wiring (conductor 483), the source voltage of transistor 490 is A high power line whose pole (or source region) is located below a low power line (conductor 482). This is easier and more preferable than connecting to (conductor 480).

[0156] In addition, in the semiconductor device 503 (cell), the high power supply wiring (conductor 480) and the low power supply wiring The width of each of the lines (conductors 482) is equal to the width of the gate electrode (conductor 4 54), the gate electrode of transistor 490 (conductor 404), or It is preferable that the width of the signal wiring is wider than that of the high power supply wiring (conductor 480) and The width of each of the low power supply wiring (conductor 482) and the wiring connected to the input terminal (conductor It is preferable that the width of the power supply wiring is wider than the width of the wiring (conductor) connected to the output terminal. In many cases, the current flowing through the wiring is larger than that of the signal wiring, and the wiring resistance of the wiring can be made lower than that of the signal wiring. Because it is preferable.

[0157] In FIG. 2 to FIG. 6, the transistor 490 has a gate electrode (conductor 413) and a gate A gate voltage can be applied independently to the electrode (conductor 413) and the gate electrode (conductor 404). Although an example has been given, the structure of a semiconductor device (cell) according to one embodiment of the present invention is not limited to this. As shown in FIGS. 10 to 12, a gate electrode (conductor 413) and a gate electrode (conductor 40 4) may be electrically connected to apply the same potential. In this case, Since the channel width can be increased, the current when the transistor 490 is turned on can be increased. In addition, even in a region where the electric field from the gate electrode (conductor 404) is difficult to reach, Since the electric field of the gate electrode (conductor 413) reaches the sub-thread of the transistor 490, The shoulder swing value (also called S value) of the transistor 490 can be reduced. The off-state current can be reduced.

[0158] (Embodiment 4) The cross-sectional structure of the semiconductor device according to one embodiment of the present invention is not limited to the structures shown in FIGS. In this embodiment, an example of a cross-sectional structure of a semiconductor device according to one embodiment of the present invention is shown in FIG. The semiconductor device 504 (cell) shown in FIG. 13 is the same as the semiconductor device shown in FIG. A transistor 490 and a transistor 491 are arranged corresponding to the body device 500 (cell). It is a wired cell.

[0159] FIG. 13 is a schematic diagram showing an example of the configuration of a semiconductor device 504 (cell). In order to make it easier to understand, some parts such as the insulator are omitted in Figures 1 and 14. The conductors etc. that are formed are given the same hatching pattern.

[0160] FIG. 14 is a top view showing an example of the configuration of a semiconductor device 504 (cell). In the semiconductor device 504, the upper surface of a region including the transistor 491 and the conductor 480 is FIG. 14B shows a semiconductor device 504 including a transistor 490 and a conductor 491. A top view of the area including 82 and conductor 484 is shown.

[0161] 15 is a cross-sectional view showing an example of the configuration of a semiconductor device 504 (cell). 14(A) and 14(B) are cross-sectional views taken along dashed line A1-A2. On the right side of the figure, a cross section taken along the dashed line B1-B2 in Figures 14(A) and 14(B) is shown. show.

[0162] In FIG. 13, a semiconductor device 504 (cell) includes a transistor 491, a high power supply wiring (conductor A conductor 480, a conductor 484, a transistor 490, and a low power wiring (conductor 482) are In other words, the high power supply wiring (conductor 491) is stacked above the transistor 491. 80) is disposed, and a conductor 484 is disposed above and overlaps the high power supply wiring (conductor 480). A transistor 490 is disposed above the conductor 484. A low power supply wiring (conductor 482) is arranged.

[0163] The source electrode (or source region) of transistor 491 is connected to the high power supply wiring (conductor 48 0), the source electrode (or source region) of transistor 491 is connected to When the power supply wiring (conductor 480) is connected to the low power supply wiring (conductor 482) arranged above the power supply wiring (conductor 480), The source electrode (or source region) of the transistor 490 is preferably Since the low power supply wiring (conductor 482) is connected to the low power supply wiring (conductor 483), the source voltage of transistor 490 is A high power line whose pole (or source region) is located below a low power line (conductor 482). This is easier and more preferable than connecting to (conductor 480).

[0164] In the semiconductor device 504 (cell), the high power wiring (conductor 480) and the low power wiring The width of each of the lines (conductor 482) is equal to the width of the gate electrode (conductor 45 4) the gate electrode (conductor 404) of the transistor 490, or the gate electrode for transferring input / output signals It is preferable that the width of the wiring is wider than that of the signal wiring. The width of each low power supply wiring (conductor 482) is the same as that of the wiring (conductor) connected to the input terminal. It is preferable that the width of the power supply wiring is wider than the width of the wiring (conductor) connected to the output terminal. In general, a larger current flows through the wiring than through the signal wiring, and it is preferable to make the wiring resistance lower than that of the signal wiring. This is because it is desirable.

[0165] 2 to 6, the low power wiring (conductor 482) and the high power wiring (conductor 480) are Although an example in which adjacent conductors are used has been described, the structure of a semiconductor device (cell) according to one embodiment of the present invention As shown in FIG. 13 to FIG. 15, the low power supply wiring (conductor 482) Between the high power supply wiring (conductor 480), the low power supply wiring (conductor 482) is arranged so as to overlap each other. A conductor 484 may be provided in addition to the conductor 482. The wiring is arranged so that there is parasitic capacitance between the wirings. ) and the high power supply wiring (conductor 480), The conductor 480 and the conductor 484 may be provided in the same manner. These parasitic capacitances cause the following problems: It is possible to realize a circuit that is resistant to power supply noise and can reduce fluctuations in the power supply voltage. It is preferable that the electric potential of the conductor 484 does not change frequently. It is preferable that the wiring 4 functions as a power supply wiring. A phenomenon in which the potential of conductor 480 and conductor 482 fluctuates due to fluctuations in conductor 484. It can be reduced.

[0166] In the configuration examples shown in FIGS. 13 to 15, the conductor 484 serves as a wiring for applying a gate voltage. The gate voltage is used to control the threshold voltage of the transistor 490. The gate voltage may be constant, in which case the conductor 484 is The gate voltage is the voltage required for the semiconductor device 504 (cell) to operate. The value may be switched between active and inactive periods. This is not done frequently, and the conductor 484 is a wiring whose potential does not change frequently.

[0167] 2 to 6, the low power supply wiring (conductor 482) and the conductors 424a and 424b In the above embodiment, the conductors are provided in separate layers. As shown in FIGS. 13 to 15, the conductor 482 and the conductor 424 The conductors in the same layer as 424a and 424b may be used. As a result, the area can be reduced and the conductor Reducing the number of layers may reduce manufacturing costs.

[0168] The output signal OUT is supplied to the drain electrode (conductor 416b) of the transistor 490 and and the drain region (region 476b) of transistor 491. The signal is output to the outside from the conductor 425a located above. The input signal IN is connected to the gate voltage of the transistor 490. The electrode (conductor 404) of the transistor 491 and the gate electrode (conductor 454) of the transistor 492 are connected to each other. The signal is input from the outside through the conductor 425b located above the conductor 404. Conductor 425b is connected to conductor 424b via conductor 478. 8 is provided in an opening in the insulator 469 .

[0169] (Embodiment 5) An example of the configuration of a semiconductor device (cell) according to one embodiment of the present invention is shown in FIG. This will be explained with reference to FIG. 20 and FIG.

[0170] FIG. 32 shows transistors 490a, 490b, 491a, and 4 is a schematic diagram of a semiconductor device in which a transistor 491b is arranged and wired.

[0171] The semiconductor device 510 (cell) includes a transistor 491a, a transistor 491b, and a transistor A resistor 490a, a transistor 490b, and a conductor 480 functioning as wiring The conductor 482 functions as a CMOS two-input NAND circuit shown in FIG. In a two-input NAND circuit with a CMOS configuration, when two input signals A and B are both high, The output signal Z is low only if the transistor 490a and the transistor 490b are connected to each other. The transistor 491a and the transistor 491b are stacked. The conductor 480 serves to provide a high power supply voltage (VDD). The conductor 482 and the conductor 480 are stacked. The output signal Z is The drain electrode of transistor 490b, the drain electrode of transistor 491a, and the drain electrode of transistor 492a One of the input signals, A, is output from the drain electrode of transistor 490a. The other input signal B is input to the output electrode of the transistor 491a and the gate electrode of the transistor 491b. A signal input to the gate electrode of the transistor 490b and the gate electrode of the transistor 491b do.

[0172] The transistors 491a and 491b have, for example, a switching speed For example, a p-channel transistor with high switching speed can be used. The switching speed is less than 10 ns, preferably less than 1 ns, and more preferably less than 0.1 ns. For example, a p-channel Si transistor is used as the transistor 491a, The transistor 490a and the transistor 490b can be used as For example, n-channel transistors with high switching speed can be used. For example, the switching speed of the transistors is less than 10 ns, preferably less than 1 n For example, an oxide semiconductor (preferably In A transistor having a channel formation region made of a metal oxide containing Ga and Zn. 490a, and transistor 490b.

[0173] The low power supply line (conductor 482) is electrically connected to the source electrode of transistor 490a. The low power supply wiring (conductor 482) is connected to the source electrode of the transistor 490b. The high power supply wiring (conductor 480) is electrically connected to the transistor 490a. The source electrode of the transistor 491a and the source electrode of the transistor 491b are electrically connected to each other. The gate electrode of the transistor 490a and the gate electrode of the transistor 491a are electrically The gate electrode of the transistor 490b and the gate electrode of the transistor 491b are connected The drain electrode of the transistor 490b is electrically connected to the drain electrode of the transistor 491a. The drain electrode of the transistor 491b is electrically connected to the drain electrode of the transistor 491c. The drain electrode of transistor 490a and the source electrode of transistor 490b are electrically connected. The drain electrode of the transistor 491a and the drain electrode of the transistor 491b are electrically connected to each other. The low power supply wiring (conductor 482) and the high power supply wiring (conductor 480) are generally They are arranged in parallel and overlap each other.

[0174] The low power wiring (conductor 482) and the high power wiring (conductor 480) are generally parallel and overlap each other. By being arranged in such a manner, the wiring has a large parasitic capacitance (also called wiring capacitance). As a result, by using this wiring as a power supply wiring, voltage fluctuations due to power supply noise can be reduced. The circuit is capable of suppressing the power supply voltage fluctuation and is resistant to power supply noise. In addition, in a semiconductor device to which the semiconductor device 510 (cell) is applied, In order to reduce fluctuations in the power supply voltage, a capacitive element may be intentionally provided in the power supply wiring. The low power supply wiring (conductor 482) and the high power supply wiring (conductor 480) have a large wiring capacitance. As a result, the semiconductor device 510 ( It is possible to miniaturize a semiconductor device using low power wiring (conductor 4). 82) and the high power supply wiring (conductor 480) are arranged to overlap each other, The occupied area can be reduced, and the area of ​​the semiconductor device 510 (cell) can be reduced. can.

[0175] The low power supply wiring (conductor 482) and the high power supply wiring (conductor 480) are adjacent to each other in the vertical direction. It is preferable to use conductors for lines. It is preferable to use conductors for wiring adjacent to each other in the vertical direction. Therefore, the distance between the wires is small and the wires have a large capacitance. It is possible to realize a circuit that is resistant to noise and can reduce fluctuations in the power supply voltage. This makes it possible to miniaturize a semiconductor device to which the semiconductor device 510 (cell) is applied.

[0176] Alternatively, the low power wiring (conductor 482) and the high power wiring (conductor 480) are conductors of adjacent layers. Alternatively, a low power supply wiring (conductor 482) and a high power supply wiring (conductor It is preferable to have no conductors between the electrodes 480.

[0177] The transistor 490a and the transistor 491a are arranged so as to overlap each other. The transistor 490b and the transistor 491b are arranged so as to overlap each other. The area of ​​the semiconductor device 510 (cell) can be reduced.

[0178] The transistors 490a and 491a are arranged on top of each other. The direction of current flow in transistor 490a and the direction of current flow in transistor 491a The direction in which the source electrode of the transistor 490a is arranged is generally parallel or anti-parallel. , the direction in which the gate electrode and the drain electrode are arranged, and the source electrode of the transistor 491a, The gate electrode and the drain electrode are arranged generally parallel to each other. b and transistor 491b are arranged so as to overlap each other, and in transistor 490b The direction of current flow in the transistor 491b is approximately parallel to the direction of current flow in the transistor 491c. Alternatively, the source electrode, the gate electrode, and the The direction in which the drain electrodes are arranged and the source electrode, gate electrode, and drain electrode of the transistor 491b are arranged. The direction in which the drain electrodes are arranged is generally parallel to the direction in which the transistor 490a and the transistor The transistor 491a can be connected in a small area including the connection part of the gate electrode. The transistor 490b and the transistor 491b can be connected in a narrow area, including the connection part of the gate electrode. As a result, the (cell) area of ​​the semiconductor device 510 can be reduced.

[0179] In FIG. 32A, a semiconductor device 510 (cell) includes transistors 491a and 491b. b, the high power supply wiring (conductor 480), the low power supply wiring (conductor 482), and the transistor 49 In other words, transistors 491a and 491b are stacked in order. A high power supply wiring (conductor 480) is arranged above the The low power supply wiring (conductor 482) is arranged and overlaps the low power supply wiring (conductor 482). Transistors 490a and 490b are disposed in the same region.

[0180] With this configuration, the low power supply wiring (conductor 482) and the high power supply wiring (conductor 48 0) is located close to the top and bottom, and therefore has a large wiring capacitance. It is possible to realize a circuit that is resistant to noise and can reduce fluctuations in the power supply voltage. It is possible to miniaturize a semiconductor device to which the semiconductor device 510 (cell) is applied.

[0181] In FIG. 32B, a semiconductor device 510 (cell) is provided on a semiconductor substrate. On a semiconductor substrate, transistors 491a and 491b, a high power supply wiring (conductor 480), The transistors 490a and 490b and the low power supply wiring (conductor 482) are arranged in this order. In this case, a high power supply wiring (conductor 480) is disposed above transistors 491a and 491b. Transistors 490a and 490b are disposed above the high power supply wiring (conductor 480). A low power supply wiring (conductor 482) is disposed above transistors 490a and 490b.

[0182] In the semiconductor device 510 (cell), the source electrodes of the transistors 490a and 490b are Alternatively, the drain electrode may be connected to a semiconductor via a conductor above transistors 490a and 490b. In some cases, the conductor may be connected to other transistors in the device 510 (cell). When the conductor and the conductor used as the connection wiring between multiple cells are formed on the same layer, the required wiring can be reduced. This is because the area required for wiring between multiple cells may become large. The irregular layout of the wiring means that unusable areas are scattered, and the number of wiring routes that must be detoured increases. Even in such a case, the conductor and the conductor used as the power supply wiring are If they are formed on the same layer, there may be little increase in area. This is because the power supply wiring is This is because the conductive layers are regularly arranged at the edge of the region. As a result, the area can be reduced and the number of conductive layers can be reduced. This may result in further reduction in manufacturing costs.

[0183] The above-mentioned semiconductor device 510 (cell) can reduce the cell area. For example, For a two-input NAND circuit, the cell height should preferably be less than WW+WT+7*Py. More preferably, the width of the cell is equal to or less than WW+WT+5*Py. Preferably, it can be 5*Px or less, and more preferably, it can be 4*Px or less. , WW is the power supply line width, WT is the channel width of a plurality of transistors in the semiconductor device 510 (cell). This is the maximum channel width among all the channel widths.

[0184] It is also preferable that the heights of the cells are the same. By setting the height of a row as the height of the cell and arranging multiple cells in multiple rows, efficient placement and wiring can be achieved. can.

[0185] In order to densely arrange the transistors and power supply wirings of the semiconductor device 510 (cell), A source electrode of transistor 490a and / or a source electrode of transistor 490b When the conductor (482) that functions as a power supply wiring is electrically connected to the The electrodes and the conductors are connected through conductors (also called vias) provided in openings in the insulator. Alternatively, the source electrode of the transistor 490a and / or the source electrode of the transistor 490b and the conductor (482) functioning as the power supply wiring ) are preferably connected through vias and conductors sandwiched between the vias. A source electrode of the transistor 491a and / or a source electrode of the transistor 491b are connected to the When the conductor (480) that functions as the power supply wiring is electrically connected to the electrode, The conductor is directly connected through a conductor provided in an opening in the insulator. Alternatively, the source electrode of transistor 491a and / or the source electrode of transistor 4 The source electrode of 91b and the conductor (480) functioning as the power supply wiring are connected to the via and the via hole. It is preferable that the connection is made via a conductor sandwiched between the first and second electrodes.

[0186] In order to densely arrange the transistors and power supply wirings of the semiconductor device 510 (cell), The semiconductor device 510 (cell) includes a transistor 490a, a transistor 490b, and a power supply Between the conductor 480 functioning as wiring and the transistor 491a and the transistor No transistor is provided between the capacitor 491b and the conductor 482 functioning as the power supply wiring. It is preferable.

[0187] The transistors and power supply wiring of the semiconductor device 510 (cell) are densely arranged, and In order to efficiently place a large number of cells, the power supply wiring is regularly placed at the edge of the cell area. In particular, the semiconductor device (cell) according to one embodiment of the present invention has one side of the cell area. The power supply wiring may be arranged only at the end of the cell area. In this case, the cell area can be made smaller than when a conventional 3D array is used.

[0188] FIG. 16 is a schematic diagram showing an example of the configuration of a semiconductor device 511 (cell). The semiconductor device 511 (cell) corresponds to the semiconductor device 510 (cell) shown in FIG. A transistor 490a, a transistor 490b, a transistor 491a, and a transistor 491b is the placed and wired cell. Note that in FIG. 16 and FIG. 17, for ease of understanding, For this reason, some of the insulators and other parts are omitted, and conductors formed in the same layer are shown with the same hardware. The pattern is provided with a shaving pattern.

[0189] FIG. 17 is a top view showing an example of the configuration of a semiconductor device 511 (cell). The semiconductor device 511 includes the transistors 491a and 491b and the conductor 480. FIG. 17(B) shows a top view of a region including a transistor in a semiconductor device 511 (cell). A top view of the area including stanchions 490a and 490b and conductor 482 is shown.

[0190] 18 is a cross-sectional view showing an example of the configuration of a semiconductor device 511 (cell). 17(A) and 17(B) are cross-sectional views taken along dashed line A1-A2. On the right side of the figure, a cross section taken along the dashed line B1-B2 in Figures 17(A) and 17(B) is shown. show.

[0191] The semiconductor device 511 (cell) shown in FIG. 16 includes a transistor 491a and a transistor 49 1b, conductor 480, transistor 490a, transistor 490b, and conductor 482. The transistors 490a and 490b are the same as the transistors 491a and The transistor 491b is stacked. The conductor 482 and the conductor 480 are stacked. Transistor 491a has regions 476a and 476b and conductor 454a. Transistor 491b has regions 476b and 476c and a conductor 454b. 90a has conductors 416a, 416b, and 404a. Transistor 490b has It has conductors 416b, 416c, and 404b.

[0192] Regions 476a and 476b are the source electrode (or source region) and the drain electrode (or drain region). The conductor 454a functions as a gate electrode of the transistor 491a. 76b and 476c are the source electrode (or source region) of transistor 491b and It functions as one and the other of the drain electrodes (or drain regions). The conductor 454b functions as a gate electrode of the transistor 491b. and 416b are the source electrode (or source region) and drain of transistor 490a. The conductor 404 functions as one of the drain electrodes (or drain region). a serves as a gate electrode of the transistor 490a. 416c is the source electrode (or source region) and drain electrode of transistor 490b (or a drain region). It serves as the gate electrode of the transistor 490b.

[0193] The high power wiring (conductor 480) and the low power wiring (conductor 482) are generally parallel and overlap each other. The output signal is provided to the drain electrode of transistor 490b (conductor 416c ), the drain region of transistor 491a (region 476a), and the drain region of transistor 491b A conductor located above the conductor 416c that is connected to the drain region (region 476c) of the One of the input signals is input to the gate electrode of the transistor 490a. (conductor 404a) and the gate electrode (conductor 454a) of transistor 491a. The input is externally input through the conductor 424b located above the conductor 404a. The other signal is applied to the gate electrode (conductor 404b) of transistor 490b and the The gate electrode (conductor 454b) of the second gate electrode 491b is connected to the gate electrode (conductor 454b) of the second gate electrode 491b. The signal is input from the outside via the corresponding conductor 424c.

[0194] The low power wiring (conductor 482) and the high power wiring (conductor 480) are overlapped with each other in a generally parallel manner. By being arranged in such a manner, the wiring has a large parasitic capacitance (also called wiring capacitance). As a result, by using this wiring as a power supply wiring, voltage fluctuations due to power supply noise can be reduced. The circuit is capable of suppressing the power supply voltage fluctuation and is resistant to power supply noise. In addition, in a semiconductor device to which the semiconductor device 511 (cell) is applied, In order to reduce fluctuations in the power supply voltage, a capacitive element may be intentionally provided in the power supply wiring. The low power supply wiring (conductor 482) and the high power supply wiring (conductor 480) have a large wiring capacitance. As a result, the semiconductor device 511 ( It is possible to miniaturize a semiconductor device using low power wiring (conductor 4). 82) and the high power supply wiring (conductor 480) are arranged to overlap each other, The occupied area can be reduced, and the area of ​​the semiconductor device 511 (cell) can be reduced. can.

[0195] The low power supply wiring (conductor 482) and the high power supply wiring (conductor 480) are adjacent to each other in the vertical direction. By using conductors for wiring adjacent to each other in the vertical direction, As a result, the distance between the wirings becomes smaller and the wirings have a large wiring capacitance. It is possible to realize a circuit that is resistant to noise and can reduce fluctuations in the power supply voltage. It is possible to miniaturize a semiconductor device to which the semiconductor device 511 (cell) is applied.

[0196] Alternatively, the low power wiring (conductor 482) and the high power wiring (conductor 480) are conductors of adjacent layers. Alternatively, a low power supply wiring (conductor 482) and a high power supply wiring (conductor It is preferable to have no conductors between the electrodes 480.

[0197] The transistor 490a and the transistor 491a are arranged so as to overlap each other. The transistor 490b and the transistor 491b are arranged on top of each other. The area of ​​the body device 510 (cell) can be reduced.

[0198] The transistors 490a and 491a are arranged on top of each other. The direction of current flow in transistor 490a and the direction of current flow in transistor 491a The direction is generally parallel or anti-parallel. The direction in which the gate electrode and drain electrode of the transistor 491a are arranged and the direction in which the source electrode and The direction in which the source electrode and the drain electrode are arranged is generally parallel. and transistor 491b are arranged on top of each other, and a current is applied to transistor 490b. The direction of the current flow in the transistor 491b is generally parallel or substantially parallel to the direction of the current flow in the transistor 491b. Alternatively, the source electrode, gate electrode, and drain electrode of the transistor 490b are antiparallel. The direction in which the input electrodes are arranged and the source electrode, gate electrode, and drain electrode of the transistor 491b are aligned. The direction in which the gate electrodes are arranged is generally parallel to the direction in which the gate electrodes are arranged. The drain electrode of transistor 90a and the drain electrode of transistor 491a are disposed close to each other. The gate electrode of the transistor 490a and the gate electrode of the transistor 491a can be The drain electrode of the transistor 490b can be disposed close to each other. The drain electrode of the transistor 491b and the drain electrode of the transistor 491b can be disposed adjacent to each other, In addition, the gate electrode of the transistor 490b and the gate electrode of the transistor 491b are connected to each other. As a result, the gate electrode of transistor 490a and the gate The gate electrode of the transistor 491a is connected to the drain electrode of the transistor 490b. a drain electrode of the transistor 491b and a gate electrode of the transistor 490b and the gate electrode of the transistor 491b are connected to each other, the area of ​​the connection region is reduced. This allows the area of ​​the semiconductor device 510 (cell) to be reduced.

[0199] The direction of current flow in transistor 490a (or the The direction in which the source electrode, gate electrode, and drain electrode are aligned) and the low power supply wiring (conductor 482 In this case, the source electrode of the transistor 490a is Regardless of which side of the gate electrode is located, the low power supply wiring (conductor 482) and the short wiring The direction of current flow in the transistor 491a (or indicates the direction in which the source electrode, gate electrode, and drain electrode of the transistor 491a are arranged) The direction in which the high power supply wiring (conductor 480) extends is generally parallel to the transistor. The source electrode of the sta 491a is connected to the high power supply wiring ( The conductor 480 can be connected to the transistor 490b by a short wire, which is preferable. In the case of the transistor 490b, the direction of current flow (or the source electrode, gate electrode, and The direction in which the gate and drain electrodes are arranged and the extension direction of the low power supply wiring (conductor 482) are generally parallel to each other. In this case, the source electrode of transistor 490b is on either side of the gate electrode. Even if the power supply is located on the side of the power supply 481, the power supply 481 can be connected by a short wire to the low power supply wire (conductor 482). The direction in which the current flows in the transistor 491b (or the direction in which the current flows in the transistor 491b) The direction in which the source electrode, gate electrode, and drain electrode are aligned) and the high power supply wiring (conductor 4 80) are generally parallel to the source electrode of the transistor 491b. However, on either side of the gate electrode, the high power supply wiring (conductor 480) and the short wiring It is possible and preferable to connect by

[0200] The direction of current flow in transistor 490a (or the The direction in which the source electrode, gate electrode, and drain electrode are aligned) and the low power supply wiring (conductor 482 The source electrode of the transistor 490a may be a low-voltage When connecting to the power supply wiring (conductor 482), the source electrode is arranged so as to overlap with the low power supply wiring. This is preferable because it is possible to reduce the area. The direction of current flow (or the source electrode, gate electrode, and drain electrode of transistor 491a) The direction in which the drain electrodes are arranged and the direction in which the high power supply wiring (conductor 480) extends are approximately perpendicular to each other. The source electrode of the transistor 491a is connected to the high power supply wiring (conductor 480). In this case, the source electrode can be arranged to overlap with the high power supply wiring, reducing the area. This is preferable because the direction of current flow in transistor 490b (or the The direction in which the source electrode, gate electrode, and drain electrode of the transistor 490b are aligned, and The direction of extension of the power wiring (conductor 482) may be approximately perpendicular. When the source electrode of b is connected to the low power supply wiring (conductor 482), the source electrode is connected to the low power supply wiring This is preferable because it is possible to arrange the transistor so that it overlaps the transistor, thereby reducing the area. The direction in which current flows in the transistor 491b (or the source electrode of the transistor 491b, The direction in which the gate electrode and drain electrode are aligned) and the extension direction of the high power supply wiring (conductor 480) The direction may be substantially perpendicular to the source electrode of the transistor 491b. When connecting to a power supply line (480), the source electrode can be arranged so as to overlap with the power supply line. This is preferable because it is possible to reduce the area.

[0201] The direction of current flow in transistor 490a (or the The direction in which the source electrode, gate electrode, and drain electrode are aligned) and in the transistor 490b, The direction of current flow (or the source electrode, gate electrode, and The direction in which the gate electrodes and drain electrodes are arranged may be generally parallel or anti-parallel. By aligning the directions, it is possible to arrange the transistors in a regular pattern when wiring them to form a circuit. By performing regular arrangement, for example, the height of the semiconductor device (cell) can be This allows the cells to be arranged in the same direction, making it possible to efficiently place multiple cells. By aligning the direction of the transistors, the variation in the electrical characteristics of the transistors may be reduced. do.

[0202] In addition, when the input / output terminals are connected to adjacent cells or nearby cells, the output signal The output terminal OUT is connected to the drain of transistor 490b without passing through conductor 424a. Drain electrode (conductor 416c), the drain electrode or drain of transistor 491a Region (region 476a), or the drain electrode or drain region of transistor 491b Even if the region (region 476c) is directly connected to the input / output terminal of an adjacent cell or a nearby cell, One of the input terminals to which the input signal IN is input is connected to the transistor 424b without passing through the conductor 424b. The gate electrode of the transistor 490a (conductor 404a) or the gate electrode of the transistor 491a (Conductor 454a) can be directly connected to the input / output terminal of an adjacent cell or a nearby cell. The other input terminal to which the input signal IN is input is connected to a transistor without passing through the conductor 424c. The gate electrode of transistor 490b (conductor 404b) and the gate electrode of transistor 491b (Conductor 454b) can be directly connected to the input / output terminal of an adjacent cell or a nearby cell. good.

[0203] In FIG. 16, a semiconductor device 511 (cell) includes transistors 491a and 491b, A power supply wiring (conductor 480), a low power supply wiring (conductor 482), and a transistor 490a In other words, the transistors 491a and 491b are stacked on top of each other. A high-power wiring (conductor 480) is disposed above the high-power wiring (conductor 480). The wiring (conductor 482) is arranged and overlapped, and the trace is above the low power wiring (conductor 482). Transistors 490a and 490b are disposed.

[0204] The source electrodes (or source regions) of transistors 491a and 491b are connected to the high power supply wiring (conductor 480), the source electrodes (also or source region) is disposed above the high power supply wiring (conductor 480). This is easier and more preferable than connecting to the body 482 of the transistor 490a. The source electrode (or source region) is connected to the low power supply wiring (conductor 482), so The source electrode (or source region) of the transistor 490a is connected to the low power supply wiring (conductor 482). This makes it easier to connect than when it is connected to the high power supply wiring (conductor 480) arranged below the preferable.

[0205] In the semiconductor device 511 (cell), the high power supply wiring (conductor 480) and the low power supply wiring The width of each line (conductor 482) is equal to the width of the gate electrode (conductor 45 4) the gate electrode (conductor 404) of the transistor 490, or the gate electrode for transferring input / output signals It is preferable that the width of the wiring is wider than that of the signal wiring. The width of each low power supply wiring (conductor 482) is the same as that of the wiring (conductor) connected to the input terminal. It is preferable that the width of the power supply wiring is wider than the width of the wiring (conductor) connected to the output terminal. In general, a larger current flows through the wiring than through the signal wiring, and it is preferable to make the wiring resistance lower than that of the signal wiring. This is because it is desirable.

[0206] The semiconductor device shown in FIG. 18 has the same cross-sectional structure as the semiconductor device shown in FIG. Therefore, for the semiconductor device shown in FIG. 18, the description of the transistor shown in FIG. 5 should be referred to as appropriate. It can be lit up.

[0207] Note that this embodiment mode can be appropriately combined with other embodiment modes shown in this specification. do.

[0208] (Embodiment 6) The transistor 490 may have various structures. Therefore, only the transistor 490 and its surrounding area are extracted, and the results are shown in FIG. As shown in.

[0209] 33A is an example of a top view of a transistor 490. An example of a cross-sectional view taken along the lines E1-E2 and E3-E4 is shown in FIG. In FIG. 33(A), some insulators and the like are omitted for ease of understanding.

[0210] In FIG. 4 and the like, the conductor 416a and the conductor In the example shown, the body 416b is in contact with the upper and side surfaces of the semiconductor 406b and the upper surface of the insulator 402. However, the structure of the transistor according to one embodiment of the present invention is not limited to this. As shown in FIG. 3, the conductor 416a and the conductor 416b are in contact only with the top surface of the semiconductor 406b. It is acceptable for the structure to be such that

[0211] In the transistor illustrated in FIG. 33, the conductor 416a and the conductor 416b are the semiconductor 406 Therefore, the conductor 404 having a function as a gate electrode is not in contact with the semiconductor An electric field applied toward the side of 406b is generated by conductor 416a and conductor 416b. The conductor 416a and the conductor 416b are formed by insulating the insulator 4. Therefore, the excess oxygen (oxygen) released from the insulator 402 is not in contact with the upper surface of the insulator 402. 6a and conductor 416b are not consumed to oxidize the insulator 402. The released excess oxygen (oxygen) is efficiently utilized to reduce oxygen vacancies in the semiconductor 406b. That is, the transistor having the structure shown in FIG. current, high field effect mobility, low subthreshold swing, high reliability, etc. This is a transistor with excellent electrical characteristics.

[0212] 34A is an example of a top view of a transistor 490. An example of a cross-sectional view taken along the line G1-G2 and the dashed line G3-G4 is shown in FIG. In FIG. 34(A), some insulators and the like are omitted for ease of understanding.

[0213] The transistor 490 shown in FIG. 34(A) and FIG. 34(B) includes a conductive layer on an insulator 442. conductor 413, an insulator 402 having a protrusion on an insulator 442 and on a conductor 413, and an insulating The semiconductor 406a on the protruding portion of the body 402, the semiconductor 406b on the semiconductor 406a, and the semiconductor 406b on the semiconductor 406a are 406a, 406b, and 406c on the semiconductor 406a. A conductive material 416a and a conductive material 416b are in contact with each other and spaced apart from each other, and a semiconductor 406c is provided. On the top, the insulator 412 on the conductor 416a and the conductor 416b, and the conductor on the insulator 412 The body 404, the conductor 416a, the conductor 416b, the insulator 412, and the conductor 404 408 and an insulator 468 on the insulator 408 .

[0214] In addition, the insulator 412 is in contact with at least the side surface of the semiconductor 406b in the G3-G4 cross section. In addition, the conductor 404 is in contact with at least the insulator 412 in the G3-G4 cross section. The conductor 413 faces the top and side surfaces of the semiconductor 406b. The insulator 402 faces the lower surface of the semiconductor 406b through a protrusion. The semiconductor 406c may be omitted. The insulator 408 may be omitted. Also, the insulator 468 may be omitted.

[0215] The transistor 490 shown in FIG. 34 has a structure partially different from that of the transistor 490 shown in FIG. Specifically, the semiconductor 406a of the transistor 490 shown in FIG. The structure of conductor 406b and semiconductor 406c and the semiconductor of transistor 490 shown in FIG. The only difference is the structure of semiconductor 406a, semiconductor 406b, and semiconductor 406c. The transistor shown in FIG. 34 may be implemented by appropriately referring to the description of the transistor shown in FIG. This can be done.

[0216] In this embodiment, the transistor 490 has a channel, for example. However, in one embodiment of the present invention, an oxide semiconductor can be used. For example, transistor 490 has a channel and adjacent regions, a source region, a drain region, and a In some cases, or depending on the situation, Si (silicon), Ge ( Germanium), SiGe (Silicon Germanium), GaAs (Gallium Arsenide), etc. The insulating film may be formed of a material having the following properties:

[0217] For example, in this specification, transistors 490 and The type of substrate is limited to a specific one. An example of the substrate is a semiconductor substrate (e.g., a single crystal substrate or a silicon substrate), SOI (Silicon on insulator) substrate, glass substrate, stone English substrate, plastic substrate, metal substrate, stainless steel substrate, stainless steel Substrate with foil, Tungsten substrate, Substrate with tungsten foil, Flexible substrate Plates, laminated films, papers containing fibrous materials, or base films. Glass Examples of the substrate include barium borosilicate glass, aluminoborosilicate glass, or so Examples of flexible substrates, laminated films, and base films Examples of such materials include polyethylene terephthalate (PET), Representative examples include polyethylene naphthalate (PEN) and polyethersulfone (PES). Plastics are one example. Synthetic resins such as acrylic are another example. Examples of the material include polypropylene, polyester, polyvinyl fluoride, and polyvinyl chloride. Examples include polyamide, polyimide, aramid, epoxy, Inorganic deposition films, paper, etc. In particular, semiconductor substrates, single crystal substrates, or SOI substrates By manufacturing transistors using a plate or the like, the characteristics, size, shape, etc. can be varied. This allows the manufacture of small-sized transistors with low fluctuations and high current capability. When a circuit is constructed using such transistors, the power consumption of the circuit can be reduced or High integration can be achieved.

[0218] In addition, a flexible substrate is used as the substrate, and a transistor is formed directly on the flexible substrate. Alternatively, a release layer may be provided between the substrate and the transistor. After a semiconductor device is partially or completely completed, it is separated from the substrate and transferred to another substrate. In this case, the transistor can be transferred to a substrate with poor heat resistance or a flexible substrate. The above-mentioned peeling layer may be formed of an inorganic material such as a tungsten film and a silicon oxide film. The structure may be a laminated structure of films or a structure in which an organic resin film such as polyimide is formed on a substrate. It is possible.

[0219] That is, one substrate is used to form a transistor, and then another substrate is used to form the transistor. The transistor may be transposed and placed on another substrate. For example, in addition to the substrate on which the above-mentioned transistors can be formed, a paper substrate, a cellophane substrate, etc. Fan boards, aramid film boards, polyimide film boards, stone boards, wood boards, cloth Substrate (natural fibers (silk, cotton, linen), synthetic fibers (nylon, polyurethane, polyester) or recycled fibers (including acetate, cupra, rayon, recycled polyester, etc.), There are leather substrates, rubber substrates, etc. By using these substrates, Formation of transistors, formation of transistors with low power consumption, manufacturing of devices that are not easily damaged, heat resistance It is possible to provide a thinner, lighter, or thinner device.

[0220] (Embodiment 7) In the following, oxides applicable to the semiconductor 406a, the semiconductor 406b, the semiconductor 406c, etc. The structure of a semiconductor will be described. In this specification, the crystal is a trigonal or rhombohedral crystal. If it is, it is represented as a hexagonal crystal system.

[0221] Oxide semiconductors are roughly classified into non-single-crystal oxide semiconductors and single-crystal oxide semiconductors. The C Axis Aligned Crystalline Oxide Semiconductor (CAAC-OS) line oxide semiconductor), polycrystalline oxide semiconductor, microcrystalline oxide These include amorphous semiconductors, amorphous oxide semiconductors, etc.

[0222] First, let me explain about CAAC-OS.

[0223] The CAAC-OS is a type of oxide semiconductor that has multiple crystal parts aligned along the c-axis.

[0224] CAAC-OS was observed under a transmission electron microscope (TEM). When observed under a ferromagnetic microscope, clear boundaries between the crystals, i.e., crystal boundaries, were observed. It is not possible to confirm the grain boundary. It can be said that AC-OS is less susceptible to the decrease in electron mobility caused by grain boundaries.

[0225] The CAAC-OS was observed by TEM from a direction roughly parallel to the sample surface (cross-sectional TEM observation ) It can be confirmed that the metal atoms are arranged in layers in the crystal part. Each layer is formed by reflecting the unevenness of the surface on which the CAAC-OS is formed (also called the surface on which the CAAC-OS is formed) or the upper surface. The CAAC-OS has a shape similar to that of the pores, and is arranged parallel to the surface on which the CAAC-OS is formed or the upper surface.

[0226] On the other hand, the CAAC-OS was observed by TEM from a direction roughly perpendicular to the sample surface (planar TEM). When the metal atoms were observed, they were found to be arranged in triangular or hexagonal shapes in the crystals. However, the arrangement of metal atoms is not necessarily regular between different crystal regions. It is not necessarily an array.

[0227] FIG. 35(a) is a cross-sectional TEM image of the CAAC-OS. FIG. 35(b) is a cross-sectional TEM image of the CAAC-OS. This is a cross-sectional TEM image of 5(a) enlarged, with the atomic arrangement emphasized for ease of understanding. It is displayed.

[0228] Figure 35(c) shows the area surrounded by a circle (diameter approximately 4 mm) between AO and A' in Figure 35(a). From Fig. 35(c), it is clear that the c-axis orientation is In addition, the c-axis orientation is different between the A-O and O-A' sections, so the different graphs are formed. The c-axis angles between the AOs are 14.3° and 16. 6°, 26.4°, and so on. Similarly, OA Between these, the c-axis angle gradually changes to -18.3°, -17.6°, and -15.9°. It is clear that things are changing.

[0229] In addition, when electron diffraction is performed on CAAC-OS, spots (bright spots) indicating orientation are observed. For example, the top surface of the CAAC-OS is When electron diffraction using a line (also called nanobeam electron diffraction) is performed, spots are observed. (See Figure 36(A)).

[0230] Cross-sectional and planar TEM observations revealed that the crystals of CAAC-OS have an orientation. It is clear that there are

[0231] Most of the crystals in CAAC-OS are cubes with sides less than 100 nm. Therefore, the crystal part in the CAAC-OS has a side length of 10 nm. This also includes cases where the size fits within a cube of less than 5 nm or less than 3 nm. However, The multiple crystal parts in the CAAC-OS are connected to form a single large crystal domain. For example, in a planar TEM image, 2 More than 5μm 2 End or 1000μm 2 In some cases, crystal regions having more than this amount may be observed.

[0232] X-ray diffraction (XRD) was used for CAAC-OS. For example, the structure of CAAC-OS with InGaZnO4 crystals was analyzed using the In the out-of-plane analysis, a peak appears at a diffraction angle (2θ) of approximately 31°. This peak is often attributed to the (009) plane of the InGaZnO4 crystal. From this, it is considered that the CAAC-OS crystal has a c-axis orientation, and the c-axis is approximately perpendicular to the surface on which the CAAC-OS is formed or the upper surface. You can see that it is pointing in the right direction.

[0233] On the other hand, in-plane X-ray irradiation is performed on CAAC-OS in which X-rays are incident from a direction approximately perpendicular to the c-axis. In the analysis by the ane method, a peak may appear at 2θ around 56°. This peak is This is attributed to the (110) plane of the InGaZnO4 crystal. For a semiconductor, 2θ is fixed at around 56°, and the normal vector of the sample surface is set as the axis (φ axis). When the sample is rotated and analyzed (φ scan), the crystal plane equivalent to the (110) plane is obtained. In contrast, in the case of CAAC-OS, 2θ is set at 56°. Even when φ is fixed in the vicinity and scanned, no clear peak appears.

[0234] From the above, it is considered that the a-axis and b-axis orientations are inconsistent between different crystal regions in CAAC-OS. The crystal is regular, but has a c-axis orientation, and the c-axis is parallel to the normal vector of the surface on which the crystal is formed or the upper surface. Therefore, the layered arrangement confirmed by the cross-sectional TEM observation mentioned above is consistent with the above. Each layer of aligned metal atoms is a plane parallel to the ab plane of the crystal.

[0235] The crystals are formed when the CAAC-OS film is formed or when a crystallization process such as heat treatment is performed. As mentioned above, the c-axis of the crystal is aligned along the CAAC-OS surface or the The orientation is parallel to the normal vector of the upper surface. Therefore, for example, the shape of the CAAC-OS is When the crystal is changed by etching, the c-axis of the crystal is aligned with the CAAC-OS surface or It may not be parallel to the normal vector of the top surface.

[0236] Furthermore, in the CAAC-OS, the distribution of the c-axis oriented crystal parts does not need to be uniform. For example, the crystalline part of the CAAC-OS is formed by crystal growth from the top surface of the CAAC-OS. When a crystal is formed, the area near the top surface has a larger proportion of c-axis oriented crystals than the area near the surface on which the crystal is formed. In addition, the CAAC-OS containing impurities may have a high The crystallized area may be altered, forming areas with different proportions of c-axis oriented crystals. be.

[0237] In addition, the out-of-plane method of CAAC-OS with InGaZnO4 crystals In the analysis by , in addition to the peak at 2θ near 31°, a peak also appeared at 2θ near 36°. The peak at 2θ around 36° may be due to the c-axis orientation in some CAAC-OS. The CAAC-OS has a peak at 2θ of around 31°. It is preferable that the compound has a peak at 2θ of about 36°.

[0238] CAAC-OS is an oxide semiconductor with a low concentration of impurities. The impurities are hydrogen, carbon, silicon, etc. These are elements other than the main components of oxide semiconductors, such as silicon and transition metal elements. Any element that has a stronger bond with oxygen than the metal elements that make up an oxide semiconductor is an oxide semiconductor. By depriving the body of oxygen, the atomic arrangement of oxide semiconductors is disrupted, which leads to a decrease in crystallinity. In addition, heavy metals such as iron and nickel, argon, and carbon dioxide have atomic radii (or molecular weights). Since the molecular radius is large, when the oxide semiconductor is included in the oxide semiconductor, it disrupts the atomic arrangement of the oxide semiconductor. The impurities contained in the oxide semiconductor are carrier to carrier, which causes the crystallinity to decrease. It may be a source of rap or carrier.

[0239] In addition, the CAAC-OS is an oxide semiconductor having a low density of defect states. Oxygen vacancies in conductors can act as carrier traps or trap hydrogen, which can increase the carrier density. It can be a source of rear emissions.

[0240] The low impurity concentration and low defect level density (low oxygen vacancies) are called high purity intrinsic or The term "high-purity intrinsic" refers to a substantially high-purity intrinsic oxide semiconductor. Since the carrier generation source is small, the carrier density can be reduced. A transistor using an oxide semiconductor has electrical characteristics in which the threshold voltage is negative (normal Also called "leon". In addition, it is rare for the product to be high-purity genuine or substantially high-purity genuine. The oxide semiconductor has few carrier traps. Such a transistor has little fluctuation in electrical characteristics and is highly reliable. Charges trapped in carrier traps in oxide semiconductors take a long time to be released. Therefore, the impurity concentration is high and the defect level is low. A transistor using an oxide semiconductor with high potential density might have unstable electrical characteristics. .

[0241] In addition, transistors using CAAC-OS show improved electrical characteristics when irradiated with visible light or ultraviolet light. The fluctuation is small.

[0242] Next, a microcrystalline oxide semiconductor will be described.

[0243] In the TEM observation image of the microcrystalline oxide semiconductor, the crystal parts can be clearly seen. The crystal parts contained in the microcrystalline oxide semiconductor may have a size of 1 nm or more and 100 nm or less. Or, the size is often 1 nm to 10 nm. Nanocrystals (nc: nanocrystals) are microcrystals with a diameter of 1 nm or less but not exceeding 3 nm. The oxide semiconductor with nanocrystals is called nc-OS (nanocrystal). Also, nc-OS For example, in TEM observation images, crystal grain boundaries may not be clearly identified.

[0244] nc-OS is a material that is used in microscopic regions (e.g., regions between 1 nm and 10 nm, especially regions between 1 nm and The atomic arrangement has periodicity in the region of 3 nm or less. There is no regularity in the crystal orientation between the crystal parts. Therefore, no orientation is observed throughout the layer. Therefore, depending on the analysis method, nc-OS may be indistinguishable from amorphous oxide semiconductors. For example, an XRD device that uses X-rays with a diameter larger than the crystal part is used for nc-OS. When the structure was analyzed using the out-of-plane method, peaks indicating crystal planes were In addition, the probe diameter (e.g., 50 mm) is larger than the crystal area of ​​the nc-OS. When electron diffraction (also called selected area electron diffraction) is performed using an electron beam of 1 nm or more, a halo is The diffraction pattern is similar to that of the nc-OS. When nanobeam electron diffraction is performed using an electron beam with a probe diameter close to or smaller than the crystal part, In addition, when nanobeam electron diffraction was performed on the nc-OS, a circular pattern was observed. In some cases, a bright area (ring-shaped) may be observed. When performing beam electron diffraction, multiple spots may be observed within a ring-shaped region. (See Figure 36(B)).

[0245] The nc-OS is an oxide semiconductor with higher order than an amorphous oxide semiconductor. However, the density of defect states in the nc-OS is lower than that in the amorphous oxide semiconductor. In the case of S, there is no regularity in the crystal orientation between different crystal parts. Therefore, the nc-OS is The defect level density is higher than that of AC-OS.

[0246] Therefore, the carrier density of the nc-OS may be higher than that of the CAAC-OS. Oxide semiconductors with high carrier density can have high electron mobility. A transistor using an nc-OS can have high field-effect mobility. Compared with CAAC-OS, OS has a higher defect density and therefore more carrier traps. Therefore, the transistor using the nc-OS may be different from the transistor using the CAAC-OS. Compared to transistors, the fluctuation in electrical characteristics is large, making them less reliable. However, nc-OS can be formed even if it contains a relatively large amount of impurities, so CA It is easier to form than AC-OS, and may be suitable for some applications. Therefore, a semiconductor device having a transistor using the nc-OS can be manufactured with high productivity. It may be possible.

[0247] The oxide semiconductor may be, for example, an amorphous oxide semiconductor, a microcrystalline oxide semiconductor, or a CAAC The -OS may be a laminated film having two or more kinds.

[0248] As described above, CAAC-OS has a higher crystallinity due to the grain boundaries than polycrystalline and microcrystalline. The advantage is that the carrier scattering is small, so the carrier mobility is less likely to decrease. AAC-OS is an oxide semiconductor with a low density of defect states and has few carrier traps. In addition, transistors using CAAC-OS have excellent reliability and small fluctuations in electrical characteristics. This results in a transistor.

[0249] When an oxide semiconductor has multiple structures, the structure can be analyzed using nanobeam electron diffraction. may be possible.

[0250] FIG. 36C shows the electron gun chamber 10, the optical system 12 below the electron gun chamber 10, and the optical system 12 below the optical system 12. a sample chamber 14, an optical system 16 below the sample chamber 14, an observation chamber 20 below the optical system 16, and an observation A transillumination system having a camera 18 installed in a chamber 20 and a film chamber 22 below the observation chamber 20. The figure shows a device for measuring electron diffraction. The camera 18 is installed facing the inside of the observation chamber 20. The room chamber 22 may not be provided.

[0251] FIG. 36(D) shows the internal structure of the transmission electron diffraction measurement device shown in FIG. 36(C). Inside the transmission electron diffraction measurement device, electrons emitted from an electron gun installed in the electron gun chamber 10 The light 24 is irradiated onto a substance 28 placed in the sample chamber 14 via the optical system 12. The electrons that have passed through are incident on a fluorescent screen 32 installed inside the observation chamber 20 via the optical system 16. On the fluorescent screen 32, a pattern appears according to the intensity of the incident electrons, which is called a transmission electron diffraction pattern. Turns can be measured.

[0252] The camera 18 is installed facing the fluorescent screen 32 and captures the pattern appearing on the fluorescent screen 32. It is possible to capture an image of the object by a straight line passing through the center of the lens of the camera 18 and the center of the fluorescent screen 32. The angle between the line and the upper surface of the fluorescent screen 32 is, for example, 15° to 80°, or 30° to 40°. The smaller the angle, the more accurate the image captured by the camera 18. However, if the angle is known in advance, the resulting transmission electron diffraction pattern will be significantly distorted. If the TEM image is obtained, it is possible to correct the distortion of the transmission electron diffraction pattern. In some cases, the camera 18 may be placed in the film chamber 22. The fluorescent screen may be installed in the room chamber 22 so as to face the direction of incidence of the electrons 24. It is possible to capture a transmission electron diffraction pattern with little distortion from the back surface of the sample.

[0253] A holder for fixing a substance 28, which is a sample, is installed in the sample chamber 14. The holder is structured to be transparent to electrons passing through the material 28. The holder may have a function of moving the holder 28 in the X-axis, Y-axis, Z-axis, etc. For example, 1 nm or more and 10 nm or less, 5 nm or more and 50 nm or less, 10 nm or more and 100 nm or less m or less, 50 nm to 500 nm, 100 nm to 1 μm, etc. These ranges can be set optimally depending on the structure of the substance28. Good.

[0254] Next, the transmission electron diffraction pattern of the material is measured using the above-mentioned transmission electron diffraction measurement device. This article explains how to do this.

[0255] For example, as shown in FIG. 36(D), the irradiation position of the electron 24, which is a nanobeam, in the material By changing (scanning) the temperature, it is possible to observe how the structure of a substance changes. In this case, if the substance 28 is CAAC-OS, the cycle shown in FIG. 36(A) can be obtained. If the material 28 is an nc-OS, a fold pattern is observed. A ring-shaped diffraction pattern with bright spots like these is observed.

[0256] The diffraction pattern shown in FIG. 36(A) is a typical diffraction pattern of CAAC-OS, that is, the c-axis The diffraction pattern showing the orientation is called the diffraction pattern of the CAAC structure. In the CAAC-OS diffraction pattern, for example, spots at the vertices of a hexagon are clearly visible. CAAC-OS scans the irradiation position to determine the orientation of the hexagon. It appears that the rotation is not uniform, but rather rotates little by little. Also, the angle of rotation has a certain range. do.

[0257] Alternatively, in the diffraction pattern of CAAC-OS, by scanning the irradiation position, It can be seen that the object rotates little by little around the axis. For example, the a-axis and the b-axis form It can also be said that the surface is rotating.

[0258] By the way, even if substance 28 is a CAAC-OS, it may be partially the same as nc-OS, etc. Therefore, the quality of CAAC-OS is judged within a certain range. The ratio of the area in the range where the CAAC-OS diffraction pattern is observed (CAAC ratio, is also called the CAAC rate.) For example, a good CAAC- For OS, the CAAC ratio is 50% or more, preferably 80% or more, and more preferably 90% or more. 0% or more, and more preferably 95% or more and 100% or less. The ratio of the area where a diffraction pattern different from that of CAAC-OS is observed is called the non-CAAC ratio, or This is referred to as the non-CAAC rate.

[0259] The method for evaluating the CAAC ratio of CAAC-OS is described below. The diffraction pattern of the CAAC structure was calculated based on the total number of measurement points. The ratio of the number of measurement points at which the line is observed is calculated. Here, the number of measurement points is preferably 50 or more. A score of 100 or more is preferable.

[0260] As a method for randomly selecting measurement points, for example, the irradiation position is scanned linearly and the measurement points are selected at regular intervals. The diffraction pattern can be obtained at each time. This is preferable because it allows one to confirm the boundaries between regions having a structure and other regions.

[0261] As an example, a CAAC-OS film just after deposition (denoted as as-sputtered) The CAAC-OS samples were also heat-treated at 450°C in an oxygen-containing atmosphere. Samples were prepared, and the top surface of each sample was scanned to obtain a transmission electron diffraction pattern. Here, the diffraction pattern was observed while scanning at a speed of 5 nm / sec for 60 sec. The CAAC ratio was derived by converting the captured diffraction pattern into still images every 0.5 seconds. The electron beam used was a nano-beam electron beam with a probe diameter of 1 nm. The measurements were performed on six samples. The CAAC ratio was calculated by the average value of the six samples. was used.

[0262] The CAAC ratio in each sample is shown in Fig. 37(A). The AC ratio was 75.7% (non-CAAC ratio was 24.3%). The CAAC rate in CAAC-OS after surgery was 85.3% (non-CAAC rate was 14.7%). It can be seen that the CAAC ratio is higher after the 450°C heat treatment than immediately after the film formation. By heat treatment at high temperatures (e.g., 400°C or higher), the non-CAAC ratio is reduced. In addition, even in heat treatment at temperatures below 500°C, It can be seen that a CAAC-OS having a high CAAC ratio can be obtained.

[0263] Here, most of the diffraction patterns different from those of the CAAC-OS are similar to those of the nc-OS. Moreover, no amorphous oxide semiconductor was observed in the measurement area. Therefore, it is possible that the heat treatment resulted in the formation of a region with a structure similar to that of the nc-OS, adjacent to the This suggests that the rearrangement is influenced by the structure of the region, resulting in CAAC formation.

[0264] 37(B) and 37(C) show the CAAC- 37(B) and 37(C) are planar TEM images of OS. It can be seen that the CAAC-OS film after the 0°C heat treatment has a more homogeneous film quality. It can be seen that the film quality of the CAAC-OS is improved by heat treatment at 30°C.

[0265] Using this measurement method, it is possible to analyze the structure of oxide semiconductors that have multiple structures. This may be the case.

[0266] When nanobeam electron diffraction was performed, it was found that the CAAC-OS partially had a non-CAAC structure. For example, the diffraction pattern of the nc structure is observed, and the spinel type Consider a case where the diffraction pattern of the crystal structure of the following is observed in an area. In the region where the diffraction pattern of the CAAC structure is observed, the diffraction patterns of other structures are observed. At the boundary between the region where the carriers are dispersed, for example, scattering of carriers increases, and carrier mobility decreases. In addition, the boundary is thought to be a good place for impurities to move and to be a good place for impurities to be captured. Therefore, there is a concern that the impurity concentration of CAAC-OS may increase.

[0267] In particular, the region having a structure other than the CAAC structure is a region having a spinel type crystal structure. In this case, between the area with CAAC structure and the area with non-CAAC structure In addition, at the boundary, the carrier scattering occurs. In addition, when forming a conductive film on the CAAC-OS, The elements of the conductive film, such as metal elements, have a region with a CAAC structure and a region with a spinel crystal structure. In addition, the crystal structure of the spinel type may be diffused to the boundary of the region having the spinel type crystal structure. In a film that is subject to this, the impurity concentration in the film, for example the hydrogen concentration, may increase. It is possible that impurities such as hydrogen are trapped. In particular, it is more preferable that the crystal structure does not contain any or only a small amount of spinel type crystal structure.

[0268] Consider the case where the oxide semiconductor contains an indium oxide semiconductor, an element M, and zinc. Here, the element M is preferably aluminum, gallium, yttrium, tin, or the like. Other elements that can be used for element M include boron, silicon, titanium, iron, and nickel. Nickel, Germanium, Yttrium, Zirconium, Molybdenum, Lanthanum, Cerium , neodymium, hafnium, tantalum, tungsten, etc. However, as the element M, In some cases, a combination of two or more of the above elements may be used. A preferable range of the ratio of the number of atoms of element M and zinc, x:y:z, will be described below.

[0269] For oxides containing indium, element M and zinc, InMO3(ZnO) m (m is natural It is known that there exist homologous phases (homologous series) represented by the Here, the case where the element M is Ga will be considered as an example.

[0270] For example, compounds with a spinel-type crystal structure include ZnM2 such as ZnGa2O4. Compounds represented by the formula ZnGa2O4 are known. x Ga y O z where x, y, and z have values ​​close to (x, y, z) = (0, 1, 2). In this case, a spinel type crystal structure is likely to be formed or to be mixed. The CAAC-OS is preferably a CAAC-OS. In particular, the CAAC-OS is a spinel type crystal. It is preferable that the crystal structure is not included. In order to increase the carrier mobility, the inclusion of In is preferable. In the case of an oxide semiconductor containing indium, the element M, and zinc, The s orbital of the heavy metal contributes to carrier conduction. This allows more s orbitals to overlap. Therefore, oxides with a high indium content have The mobility is higher than that of oxides with a lower content of Zn. By using oxides with a high indium content, carrier mobility can be increased. .

[0271] For example, by increasing the atomic ratio of indium compared to other metal elements, the carrier For example, indium contained in an oxide semiconductor is preferable because the mobility can be increased. When the ratio of the number of atoms of element M and zinc is expressed as x:y:z, x is 1.75 times or more of y. This is preferable.

[0272] In addition, in order to increase the CAAC ratio of oxide semiconductors, it is necessary to use zinc in comparison with other metal elements. It is preferable to increase the atomic ratio of lead. For example, the atomic ratio of In-Ga-Zn oxide is fixed. By making the melting area a possible range, it may be possible to increase the CAAC ratio. Increasing the ratio of the number of zinc atoms to the sum of the number of indium and gallium atoms expands the solid solution region. The possible range tends to be wider. Therefore, for the sum of the number of indium and gallium atoms, By increasing the atomic ratio of zinc, it is possible to further increase the CAAC ratio of the oxide semiconductor. For example, the number of atoms of indium, element M, and zinc in the oxide semiconductor may be When the ratio is expressed as x:y:z, it is preferable that z is 0.5 times or more of x+y. In order to increase the atomic ratio of indium and to increase the carrier mobility, z is set to be less than twice the value of x+y. It is preferable to have one.

[0273] As a result, the rate at which spinel-type crystal structures are observed in nanobeam electron diffraction has been reduced. Therefore, it is possible to realize an excellent CAAC-OS. In addition, the carriers at the boundary between the CAAC structure and the spinel type crystal structure can be obtained. Since scattering and the like can be reduced, when an oxide semiconductor is used in a transistor, This makes it possible to realize a transistor with high field effect mobility. It is possible to realize the star.

[0274] As a result, an oxide semiconductor with a high CAAC ratio can be realized. In addition, a spinel-type crystal structure can be observed in the region. It is possible to realize CAAC-OS with no or very little margin. In the case of CAAC-OS, the CAAC ratio is 50% or more, preferably 80% or more, more preferably It is preferably 90% or more, and more preferably 95% or more and 100% or less.

[0275] In addition, when an oxide semiconductor is formed by sputtering, the atomic ratio of the target is different. In particular, zinc may form a film with a higher atomic ratio than that of the target. The atomic ratio of the film may become smaller. Specifically, the number of zinc atoms contained in the target The ratio may be between 40 atomic % and 90 atomic %.

[0276] Therefore, the atomic ratio of the target is higher than that of the oxide semiconductor obtained by sputtering. It is preferable that the atomic ratio of zinc is the highest.

[0277] Note that the oxide semiconductor may be a laminate of a plurality of films. The C ratio may be different. In addition, at least one of the laminated films may be, for example, For example, the CAAC ratio is preferably 90% or higher, more preferably 95% or higher. It is more preferable that the ratio is 7% or more and 100% or less.

[0278] The above is an oxide semiconductor that can be used for the semiconductor 406a, the semiconductor 406b, the semiconductor 406c, etc. The structure of the conductor.

[0279] Next, the semiconductors applicable to the semiconductor 406a, the semiconductor 406b, the semiconductor 406c, etc. Other elements will now be described.

[0280] An oxide semiconductor that can be used for the semiconductor 406b is, for example, an oxide semiconductor containing indium. For example, when the semiconductor 406b contains indium, the carrier mobility (electron mobility The semiconductor 406b preferably contains an element M. The element M is preferably is aluminum, gallium, yttrium, or tin. Other elements M Applicable elements include boron, silicon, titanium, iron, nickel, germanium, and indium. tritium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, Tantalum, tungsten, etc. However, the element M may be a combination of multiple of the above elements. The element M may be, for example, an element having a high bond energy with oxygen. For example, it is an element that has a higher bond energy with oxygen than indium. M is, for example, an element having a function of increasing the energy gap of the oxide semiconductor. The semiconductor 406b preferably contains zinc. When an oxide semiconductor contains zinc, it becomes crystalline. It may be easier to convert.

[0281] The semiconductor 406b is made of, for example, an oxide having a large energy gap. The energy gap of 6b is, for example, 2.5 eV or more and 4.2 eV or less, preferably 2. The potential is set to 8 eV or more and 3.8 eV or less, and more preferably 3 eV or more and 3.5 eV or less.

[0282] The semiconductor 406a, the semiconductor 406b, and the semiconductor 406c each contain at least indium. When the semiconductor 406a is an In-M-Zn oxide, the sum of In and M is When In is 100 atomic %, it is preferable that In is less than 50 atomic % and M is 5. 0 atomic % or more, more preferably In is less than 25 atomic % and M is 75 atomic % or more. When the semiconductor 406b is an In-M-Zn oxide, In and When the sum of In and M is 100 atomic %, In is preferably 25 atomic % or more. , M is less than 75 atomic %, more preferably In is 34 atomic % or more, and M is In addition, when the semiconductor 406c is an In-M-Zn oxide, When the sum of In and M is 100 atomic %, it is preferable that In is 50 atomic %. c%, M is 50 atomic % or more, and more preferably In is less than 25 atomic %. The semiconductor 406c is the same as the semiconductor 406a. A seed oxide may also be used.

[0283] The semiconductor 406b is an acid having a higher electron affinity than the semiconductor 406a and the semiconductor 406c. For example, the semiconductor 406b is a compound having a higher conductivity than the semiconductors 406a and 406c. The electron affinity is 0.07 eV or more and 1.3 eV or less, preferably 0.1 eV or more and 0.7 eV or less. V or less, more preferably, an oxide having a larger energy than the above by 0.15 eV to 0.4 eV is used. , electron affinity is the energy difference between the vacuum level and the bottom of the conduction band.

[0284] Indium gallium oxide has a small electron affinity and a high oxygen blocking property. Therefore, the semiconductor 406c preferably contains indium gallium oxide. The atomic ratio [Ga / (In+Ga)] is, for example, 70% or more, preferably 80% or more, and more preferably 100% or more. More preferably, it is 90% or more.

[0285] At this time, when an electric field is applied to the gate electrode, the semiconductor 406a, the semiconductor 406b, and the semiconductor A channel is formed in the semiconductor 406b having a large electron affinity among the semiconductors 406c. The field effect mobility of the transistor can be increased. Since the body 406c is made of common elements, there is almost no interface scattering.

[0286] Here, between the semiconductor 406a and the semiconductor 406b, In addition, between the semiconductor 406b and the semiconductor 406c, In some cases, the semiconductor 406b and the semiconductor 406c may have a mixed region. The level density is reduced. Therefore, the semiconductor 406a, the semiconductor 406b, and the semiconductor 406c In the laminate, the energy changes continuously near each interface (continuous junction). 38A shows a band structure of the semiconductor 406a and the semiconductor 406b. FIG. 38(B) is a cross-sectional view of a semiconductor 406c laminated in this order. The energy (Ec) of the conduction band edge corresponding to the dashed line P1-P2 in A is the energy of the semiconductor 4 FIG. 38C shows a case where the electron affinity of the semiconductor 406c is larger than that of the semiconductor 406a. This shows a case where the electron affinity of the semiconductor 406c is smaller than that of the conductor 406a.

[0287] At this time, the electrons are not in the semiconductor 406a and the semiconductor 406c but in the semiconductor 406 As described above, the electrons move mainly through the interface between the semiconductor 406a and the semiconductor 406b. , and the interface state density at the interface between the semiconductor 406b and the semiconductor 406c. By lowering the temperature, the movement of electrons in the semiconductor 406b is less hindered, and the The on-current of the transistor 490 can be increased.

[0288] For example, the semiconductor 406a and the semiconductor 406c contain oxygen other than that constituting the semiconductor 406b. The semiconductor 406b is an oxide semiconductor having one or more of the elements listed above. The semiconductor 406a and the semiconductor 406c are made of one or more elements other than oxygen. Therefore, the interface between the semiconductor 406a and the semiconductor 406b and the interface between the semiconductor 406b and the semiconductor At the interface with 406c, an interface state is unlikely to be formed.

[0289] The semiconductor 406a, the semiconductor 406b, and the semiconductor 406c each include a spinel type crystal structure. It is preferable that the semiconductor 406a, the semiconductor 406b, and the semiconductor Preferably, the body 406c is a CAAC-OS.

[0290] For example, a CAAC-OS having multiple c-axis oriented crystal parts is used as the semiconductor 406a. As a result, the semiconductor 406b laminated thereon has a high conductivity near the interface with the semiconductor 406a. Even in such a case, a region having a good c-axis orientation can be formed.

[0291] In addition, by increasing the CAAC ratio of CAAC-OS, for example, defects can be reduced. In addition, for example, the region having a spinel structure can be reduced. In addition, for example, the scattering of carriers can be reduced. Therefore, the semiconductor 406a and the semiconductor 406c can be formed as films having high blocking ability. By increasing the CAAC ratio, a good interface with the semiconductor 406b where the channel is formed is obtained. In addition, the impurity in the semiconductor 406b is reduced. Therefore, the impurity concentration of the semiconductor 406b can be reduced.

[0292] In addition, even if the density of defect states in the region where the channel is formed is high, the movement of electrons is hindered. will be done.

[0293] For example, if the semiconductor 406b has an oxygen vacancy (V O If the structure has oxygen vacancies, Hydrogen can enter the oxygen vacancy site, forming a donor level. The state in which hydrogen has entered is V O It may be written as H. V O H scatters electrons, This causes a decrease in the on-state current of the transistor 490. The inclusion of oxygen is more stable than the inclusion of silicon. Therefore, in order to reduce oxygen vacancies in the semiconductor 406b, By doing so, the on-state current of the transistor 490 can be increased in some cases.

[0294] In order to reduce oxygen vacancies in the semiconductor 406b, for example, excess oxygen in the insulator 402 is In this case, the element is transferred to the semiconductor 406b via the semiconductor 406a. The semiconductor 406a is an oxygen-permeable layer (a layer that allows oxygen to pass through or permeate). is preferred.

[0295] Oxygen is released from the insulator 402 by heat treatment or the like and is taken into the semiconductor 406a. In addition, oxygen may be present in a free state between atoms in the semiconductor 406a or in a state where oxygen is present in other atoms. The lower the density of the semiconductor 406a, the more the interatomic bonds. The more pores there are, the higher the oxygen permeability. For example, the semiconductor 406a has a layered crystal structure. If the semiconductor 406a has a sufficiently crystalline structure and oxygen migration across the layer is unlikely to occur, It is preferable that the layer has a low resistance.

[0296] In order to allow excess oxygen (oxygen) released from the insulator 402 to reach the semiconductor 406b In this case, the semiconductor 406a may have a crystallinity sufficient to transmit excess oxygen (oxygen). For example, In the case where the semiconductor 406a is a CAAC-OS, if the entire layer becomes CAAC, excess Since oxygen (oxygen) cannot pass through, it is preferable to have a structure with some gaps. For example, the CAAC ratio of the semiconductor 406a is set to less than 100%, preferably less than 98%, and more preferably less than 100%. More preferably, it is less than 95%, and even more preferably, it is less than 90%. In order to reduce the interface state density between the semiconductor 406a and the semiconductor 406b, the CA of the semiconductor 406a is The AC ratio is 10% or more, preferably 20% or more, more preferably 50% or more, and more preferably In most cases, it should be 70% or more.

[0297] In order to increase the on-current of the transistor 490, the thickness of the semiconductor 406c is small. For example, it is less than 10 nm, preferably 5 nm or less, and more preferably 3 The semiconductor 406c may have a region of 1 nm or less. The semiconductor 406b on which the insulator is formed is charged with elements other than oxygen (hydrogen, silicon) that constitute the adjacent insulator. Therefore, the semiconductor 406c It is preferable that the thickness of the film is 0.3 nm or more, preferably 1 nm or more. The semiconductor 406c may have a thickness of at least 100 nm, and more preferably at least 2 nm. In addition, the semiconductor 406c suppresses outward diffusion of oxygen released from the insulator 402, etc. Therefore, it is preferable that the material has an oxygen blocking property.

[0298] In order to increase reliability, the semiconductor 406a is thick and the semiconductor 406c is thin. For example, it is preferably 10 nm or more, more preferably 20 nm or more, and even more preferably 40 nm or more. The semiconductor 406a may have a thickness of at least 60 nm, more preferably at least 60 nm. By increasing the thickness of the semiconductor 406a, the interface between the adjacent insulator and the semiconductor 406a The distance from the semiconductor 406b where the channel is formed can be increased. For example, the thickness is set to 200 nm or less, preferably 120 nm or less, because the productivity of the device may decrease. If the semiconductor 406a has a region with a thickness of 80 nm or less, more preferably 80 nm or less, good.

[0299] For example, between the semiconductor 406b and the semiconductor 406a, for example, secondary ion mass spectrometry ( SIMS (Secondary Ion Mass Spectrometry) 1×10 19 atoms / cm 3 Less than 5 x 10 18 atoms / cm 3 less than 2×10 18 atoms / cm 3 The region where the silicon concentration is less than In addition, a 1×1 0 19 atoms / cm 3 Less than 5 x 10 18 atoms / cm 3 Less than, more Preferably 2 x 10 18 atoms / cm 3 The silicon concentration is less than 100 nm.

[0300] In order to reduce the hydrogen concentration in the semiconductor 406b, the semiconductor 406a and the semiconductor 406b are It is preferable to reduce the hydrogen concentration in the semiconductor 406a and the semiconductor 406c. At S, 2×10 20 atoms / cm 3 Less than or equal to 5×10 19 atoms / cm 3 Less than or equal to 1×10 19 atoms / cm 3 More preferably, 5×10 18 atoms / cm 3 The semiconductor 40 has a hydrogen concentration of 0.1 to 1.0 μm. In order to reduce the nitrogen concentration of the semiconductor 406b, the nitrogen concentration of the semiconductor 406a and the semiconductor 406c is reduced. The semiconductor 406a and the semiconductor 406c are preferably 5×1 0 19 atoms / cm 3 Less than 5 x 10 18 atoms / cm 3 More details below. Preferably 1 x 10 18 atoms / cm 3 Less than 5×10, more preferably 17 ato ms / cm 3 The nitrogen concentration ranges as follows:

[0301] The above is an oxide semiconductor that can be used for the semiconductor 406a, the semiconductor 406b, the semiconductor 406c, etc. The oxide semiconductor is a semiconductor 406a. By applying the conductor 406b, the semiconductor 406c, etc., the transistor 490 has good electrical properties. For example, good switching speed can be obtained. The switching speed of the transistor 490 is less than 10 ns, preferably less than 1 ns, more preferably In addition, the transistor 490 has good switching characteristics. By using a p-channel Si transistor having high speed, The operating speed of the semiconductor device (cell) can be improved. For example, the p-channel S The switching speed of the transistor is less than 10 ns, preferably less than 1 ns. Preferably, the delay time is less than 0.1 ns. The delay time of the inverter and NAND circuits, which are the transistors, is less than 10 ns, preferably less than 1 ns. More preferably, it is less than 0.1 ns.

[0302] (Embodiment 8) Regarding an example of a configuration of a semiconductor device using a semiconductor device (cell) according to one embodiment of the present invention, This will be explained with reference to FIG.

[0303] The semiconductor device 300 shown in FIG. The power management unit 321 includes a power The peripheral circuit 322 includes a controller 302 and a power switch 303. a cache 304 having a flash memory, a bus interface (BUS I / F) 305 and a debug interface (Debug I / F) 306. 01 includes a data bus 323, a control device 307, a PC (program counter) 308, A pipeline register 309, a pipeline register 310, an ALU (Arithmetic The CPU core 3 has a logic unit 311 and a register file 312. Data is exchanged between the DDR3101 and the peripheral circuits 322 such as the cache 304 via a data bus 322. This is done via 3.

[0304] The semiconductor device (cell) according to one aspect of the present invention includes a power controller 302, a control device 3 It can be applied to many logic circuits, including 07. In particular, it uses standard cells. The present invention can be applied to all logic circuits that can be constructed using small semiconductor devices. In addition, the present invention provides a semiconductor device 300 capable of reducing power consumption. It is also possible to provide a semiconductor device 300 that can improve the operating speed. As a result, it is possible to provide the semiconductor device 300 capable of reducing fluctuations in the power supply voltage.

[0305] The semiconductor device (cell) according to one embodiment of the present invention includes a p-channel Si transistor and the The oxide semiconductor described in the embodiment (preferably an oxide containing In, Ga, and Zn) is The semiconductor device (cell) is formed as a semiconductor device 300 using a transistor included in the channel forming region. By applying the present invention to the semiconductor device 300, a small semiconductor device 300 can be provided. In addition, the semiconductor device 300 can improve the operating speed. In particular, by using only p-channel type Si transistors, This allows the manufacturing costs to be kept low.

[0306] The control unit 307 includes a PC 308, a pipeline register 309, and a pipeline register 310, ALU 311, register file 312, cache 304, bus interface The operation of the interface 305, the debug interface 306, and the power controller 302 is controlled by the By controlling the entire system, the commands contained in the input application programs can be The device has the function of decoding and executing the above.

[0307] The ALU 311 has a function of performing various arithmetic operations such as arithmetic operations and logical operations.

[0308] The cache 304 has a function of temporarily storing frequently used data. C308 is a register that has the function of storing the address of the next instruction to be executed. Although not shown in FIG. 21, the cache 304 includes a cache memory control unit. A cache controller is provided.

[0309] The pipeline register 309 is a register that has a function of temporarily storing instruction data. It is.

[0310] The register file 312 has a number of registers including general-purpose registers. Data read from memory or data obtained as a result of ALU311 arithmetic processing, etc. can be stored.

[0311] The pipeline register 310 stores data to be used for the arithmetic processing of the ALU 311, or A register that temporarily stores data obtained as a result of LU311's calculations. It is.

[0312] The bus interface 305 is a bus interface between the semiconductor device 300 and each external device. Debug interface 3 functions as a data path between the device and the 06 is a signal path for inputting a command for controlling debugging to the semiconductor device 300. It functions as a road.

[0313] The power switch 303 is a power supply that is provided in the semiconductor device 300 other than the power controller 302. The above circuits have the function of controlling the supply of power supply voltage to various circuits. Each circuit belongs to a power domain. The switch 303 controls whether the power supply voltage is supplied. 302 has a function of controlling the operation of a power switch 303 .

[0314] The semiconductor device 300 having the above configuration is capable of performing power gating. The flow of the power gating operation will be described with an example.

[0315] First, the CPU core 301 determines the timing to stop the supply of the power supply voltage by the power controller. Then, the CPU core 301 transmits the command to the power controller 302. 02 to start power gating. The various registers and caches 304 included in the memory 302 start to evacuate data. The power supply voltage to various circuits other than the power controller 302 of the device 300 is The power switch 303 then stops the power supply. Then, an interrupt signal is sent to the power controller 302. When the signal is input to the semiconductor device 300, the supply of the power supply voltage to the various circuits of the semiconductor device 300 begins. A counter is provided in the power controller 302 so that the power supply voltage is supplied The timing at which the interrupt is generated is determined by using the counter, regardless of the input of the interrupt signal. The various registers and caches 304 then begin to restore the data. Then, execution of instructions in the controller 307 resumes.

[0316] Such power gating can be applied to the entire processor or to a part of the processor. It can be done in one or more logic circuits. This allows for fine-grained spatial and temporal analysis of power consumption. Reductions can be made.

[0317] When power gating is performed, the information held by the CPU core 301 and the peripheral circuit 322 is It is preferable to be able to evacuate in a short time. This allows the power to be turned on and off in a short time. This results in a large power saving effect.

[0318] In order to save the information held by the CPU core 301 and the peripheral circuit 322 in a short time, It is preferable that the flip-flop circuit can save data within the circuit (backup possible (This is called a flip-flop circuit.) In addition, the SRAM cell can store data within the cell. It is preferable to use a backup-capable SRAM cell. The chip circuit and the SRAM cell are made of an oxide semiconductor (preferably an oxide containing In, Ga, and Zn). It is preferable to have a transistor having a channel formation region including a The low off-state current of the transistors makes them ideal for use in backup flip-flop circuits and SR AM cells can retain information for long periods without power. The fast switching speed allows for backup flip-flop circuits and SR The AM cell may be capable of short-term data evacuation and restoration.

[0319] Examples of backup-capable flip-flop circuits and backup-capable SRAM cells are given below. This will be described with reference to FIG. 22 and FIG. 23.

[0320] The semiconductor device 200 shown in FIG. 22 is an example of a flip-flop circuit capable of backing up. The semiconductor device 200 includes a first memory circuit 201, a second memory circuit 202, and a third memory circuit 203. The semiconductor device 200 includes a memory circuit 203 and a read circuit 204. The potential difference between potential V1 and potential V2 is supplied as the power supply voltage. The potential V1 is at the low level, and the other is at the high level. A configuration example of the semiconductor device 200 will be described using the case of a bell as an example.

[0321] The first memory circuit 201 stores the following data during a period in which the power supply voltage is supplied to the semiconductor device 200: When a signal D containing data is input, the semiconductor memory device has a function of holding the data. During the period when the power supply voltage is supplied to the semiconductor device 200, the first memory circuit 201 On the other hand, the first memory circuit 201 outputs a signal Q including the stored data. During the period when the power supply voltage is not supplied to the semiconductor device 200, data can be held. In other words, the first memory circuit 201 can be called a volatile memory circuit.

[0322] The second memory circuit 202 reads the data stored in the first memory circuit 201 and stores the data. The third memory circuit 203 has a function of storing (or saving) data. The data held in the memory 202 can be read and stored (or saved). The read circuit 204 reads the data stored in the second memory circuit 202 or the third memory circuit 203. The first memory circuit 201 has a function of reading out the data and storing (or restoring) the data in the first memory circuit 201 .

[0323] In particular, the third memory circuit 203 stores the In this case, the data held in the second memory circuit 202 is read and stored (or It has the function of avoiding accidents.

[0324] As shown in FIG. 22, the second memory circuit 202 includes a transistor 212 and a capacitor 219. The third memory circuit 203 includes a transistor 213, a transistor 215, and a capacitor. The read circuit 204 includes a transistor 210 and a transistor 211. 8, transistor 209, and transistor 217.

[0325] The transistor 212 stores a charge according to the data stored in the first memory circuit 201. The transistor 212 has a function of charging and discharging the capacitor 219. The charge corresponding to the data held in the memory cell 01 can be quickly charged and discharged to and from the capacitance element 219. Specifically, the transistor 212 is preferably made of crystalline silicon (preferably Preferably, the channel forming region contains silicon (preferably polycrystalline silicon, more preferably single crystal silicon). desirable.

[0326] The transistor 213 is turned on or off depending on the charge stored in the capacitor 219. The non-conducting state is selected. The transistor 215 is in the conductive state when the transistor 213 is in the conductive state. At this time, the capacitor 220 has a function of charging and discharging electric charge according to the potential of the wiring 244. It is desirable for the transistor 215 to have a significantly small off-state current. The transistor 215 is made of an oxide semiconductor (preferably an oxide containing In, Ga, and Zn) as a channel. It is desirable to include it in the formation region.

[0327] To explain the connection relationship of each element in detail, the source and drain of the transistor 212 are One end of the transistor 212 is connected to the first memory circuit 201. The other input is connected to one electrode of the capacitor 219, the gate of the transistor 213, and the The other electrode of the capacitor 219 is connected to the gate of the transistor 218. One of the source and drain of the transistor 213 is connected to the wiring 244. The other of the source and drain of the transistor 213 is connected to the The source and drain of the transistor 215 are connected to one of the source and drain. The other terminal of the transistor 210 is connected to one electrode of the capacitor 220 and the gate of the transistor 210. The other electrode of the capacitor 220 is connected to a wiring 243. One of the source and drain of the transistor 210 is connected to the wiring 241. The other of the source and drain is connected to one of the source and drain of a transistor 218. The other of the source and drain of the transistor 218 is connected to the source of the transistor 209. The source and drain of the transistor 209 are connected to one of the The other is a transistor 217 connected to one of the source and drain of the first memory circuit 201. The other of the source and the drain of the transistor 217 is connected to a wiring 240. In FIG. 22, the gate of the transistor 209 is 17, the gate of transistor 209 is not necessarily connected to the gate of transistor It is not necessary that the gate of the input terminal 217 is connected to the input terminal 217 .

[0328] The transistor 215 can be any of the transistors described in the above embodiments. Since the off-state current of the transistor 215 is small, the semiconductor device 200 can be supplied with power for a long period of time. The transistor 215 has good switching characteristics, so that information can be retained without any loss. Therefore, the semiconductor device 200 can perform high-speed backup and recovery.

[0329] The semiconductor device 100 shown in FIG. 23 is an example of a backup SRAM cell. The semiconductor device 100 includes transistors M101, M102, Mos1, and Mos2, an inverter The semiconductor device includes INV101, INV102 and capacitors C101, C102. 100 is connected to wirings WL, BL, BLB, and BRL. A low power supply voltage (VSS) or the like is supplied to as a power supply voltage.

[0330] The inverters INV101 and INV102 have input and output nodes that are The gate of the transistor M101 and the gate of the transistor M102 form an inverter loop circuit. The gate of the transistor M102 is connected to the wiring WL. , which functions as a switch connecting the wiring BL and the input node of the inverter INV101, The transistor M102 connects the wiring BLB and the input node of the inverter INV102. It functions as a switch.

[0331] The wiring WL functions as a write / read word line and transmits a memory cell selection signal ( WLE) is input from the word line driver circuit. The wirings BL and BLB are data signals D, The data signal DB functions as a bit line that transmits the data signal D with its logical value inverted. The data signals D and DB are supplied from a bit line driver circuit. The wirings BL and BLB are also wirings for transmitting data read from the semiconductor device 100 to an output circuit. be.

[0332] The semiconductor device 100 includes an inverter INV101, an inverter INV102, a transistor A pair of memory circuits is provided in a volatile memory circuit having a transistor M101 and a transistor M102. The pair of memory circuits corresponds to a transistor Mos1 and a capacitor C1. A memory circuit having a transistor (hereinafter referred to as a memory circuit (Mos1, C101)) A memory circuit having a memory element Mos2 and a capacitor C102 (hereinafter, the memory circuit (Mos2, C1 02). It is composed of a memory circuit (Mos1, C101), a memory circuit (Mos2 , C102) respectively record the potentials held at the nodes NET1 and NET2. These circuits back up the data in the volatile memory circuits by storing data. The memory circuit of the capacitor C 101, C102 can be charged or discharged to write data and turn it off. By retaining the charge stored in the capacitor, data is retained without a power supply. That is why.

[0333] Data recovery is also performed by turning on transistors Mos1 and Mos2. With the power supply to the inverters INV101 and INV102 stopped, Turn on the Mos1 and Mos2 switches to connect the nodes FN1 and NET1. The charge is shared between node FN1 and node NET1, and node FN2 and node NET2 are connected. Then, the charge is shared between the node FN2 and the node NET2. Then, the inverter INV10 1. By supplying power to INV102, the potential of nodes NET1 and NET2 changes. Then, the data is restored to the inverter loop circuit. Turn off Mos2.

[0334] The gates of the transistors Mos1 and Mos2 are connected to the wiring BRL. A signal OSG is input to the input terminal L. The signal OSG activates a pair of memory circuits (memory circuits (Mos 1, C101), and the memory circuit (Mos2C102)) are driven and used for backup or reset. Coverage is carried out.

[0335] The configurations of the memory circuits (Mos1, C101) and (Mos2, C102) are as follows: The operation will now be described.

[0336] The memory circuits (Mos1, C101) and (Mos2, C102) include a capacitor C101, By storing charge in C102, the potentials of nodes FN1 and FN2 are maintained. By turning on the nodes Mos1 and Mos2, the nodes NET1 and FN1 are connected. The potential held at the node NET1 is applied to the node FN1, and the transistor By turning on Mos2, node NET2 and node FN2 are connected, and node F The potential held at node NET2 is applied to transistor Mos1. By turning off Mos2, the nodes FN1 and FN2 are electrically floating. The charge stored in the capacitors C101 and C102 is held, and the memory circuit is in a data holding state. It becomes a posture.

[0337] For example, when node FN1 is at the H level, charge leaks from C101 and gradually The transistors Mos1 and Mos2 are oxide semiconductors. It is preferable that the channel forming region contains an oxide (preferably an oxide containing In, Ga, and Zn). As a result, the leakage current (off-state current) flowing between the source and drain in the off state is Since the voltage at the node FN1 is extremely small, the voltage fluctuation at the node FN1 is suppressed. 1, C101) is a non-volatile memory circuit, or a circuit that retains data for a long period of time without power supply. It is possible to operate the memory circuit as a memory circuit that can store data. The same is true for the inverter INV101 and the inverter INV102. A volatile memory circuit having a transistor M101, a transistor M102, It can be used as a backup memory circuit.

[0338] The transistors illustrated in the previous embodiment are applied to the transistors Mos1 and Mos2. Since the off-current of the transistors Mos1 and Mos2 is small, The transistor Mos1, 100, can retain information for a long period without power supply. Because of the good switching characteristics of Mos2, the semiconductor device 100 has a high speed backup. It can perform backup and recovery.

[0339] A semiconductor device (cell) according to one embodiment of the present invention and an oxide semiconductor A flip-flop capable of backing up a transistor having a channel forming region including It is possible to apply a circuit and an SRAM cell to the semiconductor device 300. This makes it possible to turn the power on and off during a certain period of time, and thus makes it possible to provide a semiconductor device with lower power consumption. Cut.

[0340] In addition, the semiconductor device (cell) according to one embodiment of the present invention and the oxide A flip-flop with a back-up function using a transistor including a semiconductor in a channel forming region A drop circuit and an SRAM cell can be applied to the semiconductor device 300. It is possible to reduce manufacturing costs. In particular, it is used for flip-flop circuits and SRAM cells. The n-channel transistors in the above embodiment are all made of the oxide semiconductor. The Si transistor may be replaced with a transistor included in the semiconductor device forming region. By using the same material, the manufacturing cost can be kept low.

[0341] The semiconductor device (cell) according to one embodiment of the present invention can be used not only for a CPU but also for a GPU (Graphics Processing Unit). aphics Processing Unit), PLD (Programmable Logic Devices), DSPs (Digital Signal Processes) sor), MCU (Microcontroller Unit), RF-ID (Rad io Frequency Identification), custom LSI, etc. It is applicable.

[0342] (Embodiment 9) In this embodiment, a usage example of a semiconductor device (cell) according to one embodiment of the present invention will be described. do.

[0343] Figure 24(A) shows a part of the inside of a package using a lead frame type interposer. 24A is a perspective view illustrating a package according to one embodiment of the present invention. The chip 751 to which the cell is applied is attached to the interposer by wire bonding. The terminal 752 is connected to the chip 750 of the interposer 750. The chip 751 is mounted on the surface. The chip 751 is then molded with resin. 753, each terminal 752 may be sealed in a state where a part of the terminals 752 is exposed. Make sure that.

[0344] The module configuration of an electronic device (mobile phone) in which a package is mounted on a circuit board is The mobile phone module shown in FIG. 24(B) includes a printed wiring board 7 A package 762 and a battery 764 are mounted on the display device 61. A printed wiring board 761 is mounted on the provided panel 760 by an FPC 763. There are.

[0345] (Embodiment 10) Regarding an example of a configuration of a semiconductor device using a semiconductor device (cell) according to one embodiment of the present invention, The following description will be given with reference to FIGS.

[0346] An example of the configuration of a semiconductor device is shown in Fig. 26. The semiconductor device 600 shown in Fig. 26 is a memory device. The semiconductor device 600 is an example of a semiconductor device that can function as a memory cell. Array 610, row decoder 621, word line driver circuit 622, bit line driver circuit 630, an output circuit 640, and a control logic circuit 660.

[0347] The bit line driver circuit 630 includes a column decoder 631, a precharge circuit 632, The precharge circuit 632 includes a sense amplifier 633 and a write circuit 634. The function to precharge the lines BL and BLB, and the voltage of the lines BL and BLB in the same column The sense amplifier 633 has a function of equalizing the data read from the wirings BL and BLB. The amplified data signals D and DB are output to the output circuit 640. The digital data signal RDATA is outputted to the outside of the semiconductor device 600 via the GND terminal 614.

[0348] The semiconductor device 600 also receives a low power supply voltage VSS as an external power supply voltage, A high power supply voltage VDD for the circuit section 601 other than the array, a high power supply voltage VDD for the memory cell array 610 A pressure VIL is supplied.

[0349] The semiconductor device 600 also includes control signals CE, WE, and RE, an address signal ADDR, The data signal WDATA is input from the outside. The WDATA is input to a write circuit 634.

[0350] The control logic circuit 660 receives control signals (CE, WE, RE ) to generate control signals for the row decoder 621 and the column decoder 631. The signal CE is a chip enable signal, and the control signal WE is a write enable signal. The control signal RE is a read enable signal. The signals processed by 0 are not limited to these, and other control signals can be input as necessary. Just put in the effort.

[0351] It should be noted that the above-mentioned circuits and signals can be appropriately selected or omitted as necessary.

[0352] The semiconductor device (cell) according to one embodiment of the present invention includes a row decoder 621, a word line driver circuit 622, bit line driver circuit 630, output circuit 640, control logic circuit 660. In particular, it can be constructed using standard cells. This can be applied to all logic circuits. As a result, a compact semiconductor device 600 can be provided. In addition, it is possible to provide a semiconductor device 600 that can reduce power consumption. Therefore, it is possible to provide a semiconductor device 600 capable of improving the efficiency.

[0353] The semiconductor device (cell) according to one embodiment of the present invention includes a p-channel Si transistor and the above-mentioned The oxide semiconductor described in the embodiment (preferably an oxide containing In, Ga, and Zn) is used. By using a transistor included in the channel forming region and applying it to the semiconductor device 600, It is possible to provide a semiconductor device 600. In addition, the semiconductor device 600 can reduce power consumption. In addition, it is possible to provide a semiconductor device 600 that can improve the operating speed. In particular, by using only p-channel type Si transistors, manufacturing costs can be kept low. can be done.

[0354] The memory cell array 610 includes the oxide semiconductor (preferably A transistor containing an oxide containing In, Ga, and Zn in the channel formation region is used. An example of such a memory cell will be described below with reference to FIGS.

[0355] FIG. 27 is a circuit diagram showing an example of the configuration of a memory cell. The node FN3 is a data storage unit. , and the terminal of the capacitor C103 is connected. The transistor Mos3 is connected to the node FN3 The gate of the switch is connected to the wiring WL. A signal OSG is input to WL as a memory cell selection signal.

[0356] FIG. 28 is a circuit diagram showing an example of the configuration of a memory cell. A node FN 4 is a data storage unit, and the transistor Mos4 is a switch that connects the node FN4 and the wiring BL. The gate of the switch is connected to the line WL. The signal OSG is input to the line WL. The capacitor C104 connects the wiring WLC and the node FN4. is used to supply a constant voltage to the C104 terminal during write and read operations. The transistor M104 is a p-channel transistor, and the gate The node FN4 has a source connected to the wiring SL and a drain connected to the wiring BL.

[0357] With a constant voltage applied to the wiring WLC and SL, the transistor Mos4 is turned on. , data is written by connecting node FN4 to the wiring BL. A constant voltage is applied to the wirings BL, WLC, and SL. The transistor The current value flowing between the source and drain of the transistor M104 fluctuates. The line BL is charged or discharged by the source-drain current, so the voltage of the line BL is By detecting this, the data value stored in the memory cell 104 can be read.

[0358] The transistor M104 may be an n-channel transistor. The voltage applied to the wiring (BL, SL, WLC) is determined according to the conductivity type of the transistor M104. It is determined.

[0359] FIG. 29 is a circuit diagram showing an example of the configuration of a memory cell. A resistor Mos5, a transistor M105, a transistor M106 and a capacitor C10 The node FN5 is a data storage section, and the transistor Mos5 is The gate of the switch is connected to the wiring WL. A signal OSG is input to the transistor WL. The gate of the transistor M105 is connected to the The gate of the transistor M106 is connected to the line RWL, and the gate of the transistor M107 is connected to a node FN5. The other terminal of the capacitor C105 is connected to a node FN5.

[0360] To write data, the transistor Mos5 is turned on and the node FN4 is connected to the wiring B L. Data is read by turning on transistor M105. The source voltage of the transistor M106 is set to 0 V in response to the voltage of the node FN5. The current flowing between the drains of the transistor M106 varies. The line BL is charged or discharged, so the memory can be The data value held in cell 105 can be read.

[0361] The transistors M105 and M106 can be p-channel transistors. The voltage applied to the wiring RWL is set according to the conductivity type of the transistors M105 and M106. Then, the voltage to be applied to the capacitor C105 can be determined.

[0362] In the configuration examples of the memory cell shown in FIGS. 27 to 29, the transistors Mos3 and Mo s4 and Mos5 are oxide semiconductors (preferably oxides containing In, Ga, and Zn). As a result, the source and drain of the transistor in the off state are Since the leakage current (off-state current) flowing between the drains is extremely small, the nodes FN3, FN4, The voltage fluctuation of FN5 is suppressed. In other words, the circuit including Mos3 and C103, Mos4 and The circuit including C104 and the circuit including Mos3 and C103 are non-volatile memory circuits. It operates as a memory circuit that can retain data for a long period without a power supply. It is possible to do this.

[0363] A semiconductor device (cell) according to one embodiment of the present invention and an oxide semiconductor A memory cell using a transistor including the above in a channel formation region is applied to the semiconductor device 600. By using this technology, data can be stored for a long period of time without a non-volatile memory circuit or power supply. It is possible to provide a semiconductor device 600 having a memory circuit capable of performing the above-mentioned steps. A semiconductor that can operate at high speed with low power consumption or reduce fluctuations in the power supply voltage An apparatus 600 can be provided.

[0364] In addition, the semiconductor device (cell) according to one embodiment of the present invention and the oxide A semiconductor device 60 is provided with a memory cell using a transistor including a semiconductor in a channel formation region. Therefore, it is possible to reduce manufacturing costs. The n-type transistors used in the memory cells are all made of the oxide semiconductor The transistor may be formed by using a transistor having a channel formation region of p By using only the channel type, the manufacturing cost can be kept low.

[0365] Note that this embodiment mode can be appropriately combined with other embodiment modes shown in this specification. do.

[0366] (Embodiment 11) FIG. 25 shows an example of the configuration of a device using a semiconductor device (cell) according to one embodiment of the present invention. I will explain using the following.

[0367] The semiconductor device 800 shown in FIG. 25 is an example of the configuration of an RFID tag. The RFID tag in the RFID tag has a memory circuit inside, which stores the necessary information and transmits it in a non-contact manner. It transmits and receives information to and from the outside using a means such as wireless communication. RFID tags are used for individual authentication to identify items by reading their individual information. It can be used in systems, etc.

[0368] The semiconductor device 800 shown in FIG. 25 includes an antenna 804, a rectifier circuit 805, a constant voltage circuit 80 6, demodulation circuit 807, modulation circuit 808, logic circuit 809, memory circuit 810, ROM 811 It has.

[0369] The antenna 804 transmits a radio signal 803 to and from the antenna 802 connected to the communication device 801. The rectifier circuit 805 generates an input potential. Generally, the input AC signal is generated by receiving a radio signal at an antenna 804. A capacitive element provided after the rectifier circuit 805 that rectifies the input signal, for example, performs half-wave double voltage rectification. The rectified signal is smoothed by the rectifier circuit 805. Alternatively, a limiter circuit may be provided on the output side. When the width is large and the internally generated voltage is large, a certain amount of power or more must not be input to the subsequent circuit. This is a circuit for controlling the

[0370] The constant voltage circuit 806 generates a stable power supply voltage from the input potential and supplies it to each circuit. The constant voltage circuit 806 may have a reset signal generating circuit therein. The signal generation circuit uses the stable rise of the power supply voltage to generate a reset signal for the logic circuit 809. Generate a number.

[0371] The demodulation circuit 807 demodulates the input AC signal by envelope detection to generate a demodulated signal. In addition, the modulation circuit 808 performs modulation according to the data output from the antenna 804. .

[0372] The logic circuit 809 decodes and processes the demodulated signal. The ROM 811 also has a row decoder, a column decoder, a memory area, etc. It stores unique numbers (IDs) and other information and outputs them according to processing.

[0373] The data transmission format is a pair of coils arranged opposite each other and communication is carried out by mutual induction. Electromagnetic coupling method, electromagnetic induction method that communicates by induced electromagnetic fields, radio wave method that communicates using radio waves The semiconductor device 800 described in this embodiment can be used for any of the methods. It is possible.

[0374] It should be noted that the above-mentioned circuits can be appropriately selected or omitted as necessary.

[0375] The semiconductor device (cell) according to one embodiment of the present invention includes a logic circuit 809, a memory circuit 810, a RO In particular, it can be configured using standard cells. As a result, a small-sized semiconductor device 800 can be provided. In addition, it is possible to provide a semiconductor device 800 that can reduce power consumption. It is possible to provide a semiconductor device 800 capable of improving the operating speed.

[0376] A p-channel Si transistor and an oxide semiconductor (preferably The transistor used had a channel formation region made of In, Ga, and Zn. By applying a semiconductor device (cell) according to one embodiment of the present invention to the semiconductor device 800, In addition, the semiconductor device 800 can reduce power consumption. 0 can be provided. Also, a semiconductor device 800 capable of improving the operating speed can be provided. In particular, by using only p-channel Si transistors, manufacturing costs can be kept low. This can be done.

[0377] Note that the memory circuit 810 can be any of the memory circuits described in the above embodiments. In addition, the element exhibiting the rectification action included in the demodulation circuit 807 may be the oxide semiconductor layer described in the previous embodiment. The channel forming region includes an oxide semiconductor (preferably an oxide containing In, Ga, and Zn). A transistor may be used. Since the transistor has a low off-state current, the rectification function This makes it possible to suppress the reverse current of the element that exhibits high rectification efficiency. It can be achieved.

[0378] Note that this embodiment mode can be appropriately combined with other embodiment modes shown in this specification. do.

[0379] (Embodiment 12) The semiconductor device (cell) according to one aspect of the present invention is applicable to display devices, personal computers, recording devices, and the like. Image playback devices equipped with recording media (typically DVD: Digital Versatile A device with a display that can play back recording media such as discs and display the images. In addition, the semiconductor device (cell) according to one embodiment of the present invention can be used in Examples of electronic devices that can be used include mobile phones, portable game consoles, portable data terminals, electronic books, etc. Registered terminals, cameras such as video cameras and digital still cameras, goggle-type displays ( Head-mounted displays), navigation systems, audio playback devices (car audio) digital audio players, copiers, fax machines, printers, These include multifunction machines, automated teller machines (ATMs), and vending machines. A specific example of the device is shown in FIG.

[0380] FIG. 30A shows a portable game machine, which includes a housing 901, a housing 902, a display unit 903, and a display 904, microphone 905, speaker 906, operation keys 907, stylus 90 8. The portable game machine shown in FIG. 30(A) has two display units 903 and Although the portable game machine has a display unit 904, the number of display units that the portable game machine has is not limited to this. do not have.

[0381] FIG. 30B shows a portable data terminal, which includes a first housing 911, a second housing 912, and a first display unit. The first display unit 913, the second display unit 914, the connection unit 915, the operation keys 916, etc. 13 is provided in the first housing 911, and the second display unit 914 is provided in the second housing 912. The first housing 911 and the second housing 912 are connected by a connection part 915. The angle between the first housing 911 and the second housing 912 can be changed by the connection part 915. The image on the first display unit 913 is transmitted between the first housing 911 and the second housing 912 at the connection unit 915. The display may be switched according to the angle between the first display unit 912 and the body 912. At least one of the first display unit 913 and the second display unit 914 is provided with a function as a position input device. The function of the position input device may be implemented by a display device. This can be added by providing a touch panel. Or, it can function as a position input device. The display device can also be equipped with a photoelectric conversion element, also called a photosensor, in the pixel portion of the display device. It can be added.

[0382] FIG. 30C shows a notebook personal computer, which includes a housing 921, a display unit 922, It has a keyboard 923, a pointing device 924, and the like.

[0383] FIG. 30(D) shows an electric refrigerator-freezer, which includes a housing 931, a refrigerator compartment door 932, and a freezer compartment door 933. 33, etc.

[0384] FIG. 30E shows a video camera, which includes a first housing 941, a second housing 942, and a display unit 943. The operation key 944, the lens 945, the connection part 946, etc. The lens 945 is provided in the first housing 941, and the display unit 943 is provided in the second housing 942. The first housing 941 and the second housing 942 are connected by a connection portion 946. The angle between the first housing 941 and the second housing 942 can be changed by the connection part 946. The image on the display unit 943 is transmitted between the first housing 941 and the second housing 942 at the connection unit 946. 942.

[0385] FIG. 30(F) shows a standard automobile, which includes a body 951, wheels 952, a dashboard 953, Light 954 and others.

[0386] By using a semiconductor device (cell) according to one embodiment of the present invention in these electronic devices, The trend towards smaller devices, faster operation speeds, lower power consumption, and / or less fluctuation in power supply voltages In particular, by using only p-channel Si transistors, As a result, it is possible to reduce manufacturing costs and provide a compact electronic device. In addition, power consumption is reduced by using a semiconductor device (cell) according to one embodiment of the present invention. It is possible to provide an electronic device that can operate at high speed. It is also possible to provide an electronic device that can operate more stably. It is possible to provide electronic devices that operate smoothly.

[0387] Note that this embodiment mode can be appropriately combined with other embodiment modes shown in this specification. do.

[0388] In addition, the contents (or even a part of the contents) described in one embodiment may be used in the embodiment. Another content (or a part of the content) described in the form, and / or one or more other implementations The contents (or a part of the contents) described in the embodiments may be applied, combined, or replaced. It is possible to do things like drawing.

[0389] The contents described in the embodiments are explained in detail with reference to various figures in each embodiment. The content is described in the specification or using sentences in the description.

[0390] In addition, a figure (or a part of it) described in one embodiment may be replaced with another part of the figure. , another figure (or a part thereof) described in the embodiment, and / or one or more By combining the figures (or a part of them) described in the other embodiments of the present invention, This allows even more diagrams to be constructed. [Explanation of symbols]

[0391] 10 Electron Gun Room 11 Memory circuit 12 Optical system 14 Sample Room 16 Optical system 18 Camera 20 Observation Room 22 Film Room 24 electronic 28 Substance 32 Fluorescent Screen 100 Semiconductor device 101 INV 102 INV 103 Memory Cells 104 memory cells 105 memory cells 200 Semiconductor device 201 Memory circuit 202 Memory circuit 203 Memory circuit 204 Circuit 209 Transistor 210 Transistor 212 Transistor 213 Transistor 215 Transistor 217 Transistor 218 Transistor 219 Capacitive element 220 Capacitive element 240 Wiring 241 Wiring 242 Wiring 243 Wiring 244 Wiring 300 Semiconductor device 301 CPU cores 302 Power Controller 303 Power Switch 304 Cache 305 Bus Interface 306 Debug Interface 307 Control Device 308 PC 309 Pipeline Registers 310 Pipeline Registers 311 ALU 312 Register File 321 Power Management Unit 322 Peripheral Circuits 323 Data Bus 400 Semiconductor Substrates 402 Insulator 404 Conductors 404a Conductor 404b Conductor 406 Semiconductors 406a Semiconductors 406b Semiconductors 406c Semiconductors 408 Insulator 412 Insulators 413 Conductors 416a Conductor 416b Electric conductor 416c Conductor 424a Conductor 424b Conductor 424c conductor 425a Conductors 425b Conductor 442 Insulator 452 Insulator Region 454 Conductors 454a Conductors 454b Conductors 460 Insulator 462 Insulator 464 Insulator 465 Insulator 466 Insulators 467 Insulators 468 Insulator 470 Insulator 471 Conductors 472 Conductors 473 Conductors 474 area 476a area 476b area 476c area 480 Conductors 482 Conductors 484 Conductors 490 Transistors 490a Transistor 490b transistor 491 Transistor 491a Transistor 491b Transistor 492 Transistors 500 Semiconductor device 501 Semiconductor device 502 Semiconductor devices 503 Semiconductor Devices 504 Semiconductor devices 510 Semiconductor device 511 Semiconductor devices 600 Semiconductor device 601 Circuit section 610 Memory Cell Array 621 Low Decoder 622 Word Line Driver Circuit 630 Bit Line Driver Circuit 631 Column Decoder 632 Precharge Circuit 633 Sense Amplifier 634 Circuit 640 Output Circuit 660 Control Logic Circuit 750 Interposer 751 Chips 752 Terminal 753 Molding resin 760 Panel 761 Printed Wiring Board 762 packages 763 FPC 764 Battery 800 Semiconductor Devices 801 Communication Device 802 Antenna 803 radio signal 804 Antenna 805 Rectifier circuit 806 Constant voltage circuit 807 Demodulation Circuit 808 Modulation Circuit 809 Logic Circuit 810 Memory circuit 811 ROM 901 Case 902 Case 903 Display section 904 Display section 905 Microphone 906 Speaker 907 Operation Key 908 Stylus 911 Case 912 Case 913 Display section 914 Display section 915 Connection 916 Operation Key 921 Case 922 Display section 923 Keyboard 924 Pointing Device 931 Case 932 Refrigerator door 933 Freezer door 941 Case 942 Case 943 Display section 944 Operation Key 945 Lens 946 Connection 951 Body 952 wheels 953 Dashboard 954 Light

Claims

1. An inverter circuit having a first transistor and a second transistor, the first transistor has a first channel formation region having silicon and a first gate electrode located above the first channel formation region; the second transistor includes a second channel formation region including an oxide semiconductor, a second gate electrode located above the second channel formation region, and a third gate electrode located below the second channel formation region; a first insulator is provided on the first gate electrode; the second channel formation region is provided on the first insulator, One of the source and the drain of the first transistor is electrically connected to a high power supply line; one of the source and the drain of the second transistor is electrically connected to a low power supply line; the first gate electrode is electrically connected to the second gate electrode via a first conductor; the second gate electrode is electrically connected to the third gate electrode via the first conductor; a second insulator is provided on the second gate electrode; the first conductor is provided on the second insulator; the other of the source and the drain of the first transistor is electrically connected to the other of the source and the drain of the second transistor via a second conductor and a third conductor; the second conductor has a region in contact with the silicon, the third conductor has a region in contact with the oxide semiconductor, In a plan view, the high power supply wiring has a region extending in a first direction, In a plan view, the low power supply wiring has a region extending in the first direction.

2. In claim 1, When seen in a plan view, the first transistor has a region through which carriers flow in a direction along the first direction, an inverter circuit, wherein, in a plan view, the second transistor has a region through which carriers flow in a direction along the first direction.

3. A semiconductor device comprising the inverter circuit according to claim 1 or 2.

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