Semiconductor structure having shared epitaxial layer - Patents.com

Abstract

The semiconductor structure comprises two or more vertical fins, a lower epitaxial layer surrounding a lower portion of a given vertical fin of the two or more vertical fins, an upper epitaxial layer surrounding an upper portion of the given vertical fin of the two or more vertical fins, a shared epitaxial layer surrounding a middle portion of the given vertical fin of the two or more vertical fins, and a connecting layer in contact with the lower epitaxial layer and the upper epitaxial layer, the connecting layer being disposed on a lateral side of the two or more vertical fins.

Description

[Technical field]

[0001] This application relates to semiconductors and, more particularly, to techniques for forming semiconductor structures. Semiconductors and integrated circuit chips are ubiquitous in many products, especially as their cost and size continue to shrink. There is a continuing desire to reduce the size of structural features and / or provide more structural features for a given chip size. Miniaturization generally allows for improved performance at lower power levels and lower costs. Current technology is at or approaching atomic level scaling of certain microdevices such as logic gates, field-effect transistors (FETs), and capacitors. Summary of the Invention

[0002] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention provide techniques for forming stacked vertical transport field-effect transistor (VTFET) logic gate structures having a shared epitaxial layer.

[0003] In one embodiment, a semiconductor structure comprises two or more vertical fins, a lower epitaxial layer surrounding a lower portion of a given vertical fin of the two or more vertical fins, an upper epitaxial layer surrounding an upper portion of the given vertical fin of the two or more vertical fins, a shared epitaxial layer surrounding a middle portion of the given vertical fin of the two or more vertical fins, and a connection layer in contact with the lower epitaxial layer and the upper epitaxial layer, the connection layer being disposed on a lateral side of the two or more vertical fins.

[0004] In another embodiment, a method of forming a semiconductor structure includes forming two or more vertical fins, forming a lower epitaxial layer surrounding a lower portion of a given vertical fin of the two or more vertical fins, forming an upper epitaxial layer surrounding an upper portion of the given vertical fin of the two or more vertical fins, forming a shared epitaxial layer surrounding a middle portion of the given vertical fin of the two or more vertical fins, and forming a connecting layer in contact with the lower epitaxial layer and the upper epitaxial layer, wherein the connecting layer is disposed on a lateral side of the two or more vertical fins.

[0005] In another embodiment, the inverter logic gate comprises a four-channel n-type field effect transistor and a four-channel p-type field effect transistor. The four-channel n-type field effect transistor comprises two vertical fins, each of which comprises a lower epitaxial layer surrounding the lower portion of the two vertical fins, an upper epitaxial layer surrounding the upper portion of the two vertical fins, and a shared epitaxial layer surrounding the middle portion of the two vertical fins. The four-channel p-type field effect transistor comprises two vertical fins, each of which comprises a lower epitaxial layer surrounding the lower portion of the two vertical fins, an upper epitaxial layer surrounding the upper portion of the two vertical fins, and a shared epitaxial layer surrounding the middle portion of the two vertical fins. The inverter logic gate also comprises a connection layer contacting the lower epitaxial layer and the upper epitaxial layer of the four-channel n-type field effect transistor and the four-channel p-type field effect transistor.

[0006] In another embodiment, the two-input logic gate comprises two two-channel n-type field effect transistors and two two-channel p-type field effect transistors. The two two-channel n-type field effect transistors comprise two vertical fins, each of which comprises a lower epitaxial layer surrounding the lower portion of the two vertical fins, an upper epitaxial layer surrounding the upper portion of the two vertical fins, and a shared epitaxial layer surrounding the middle portion of the two vertical fins. The two two-channel p-type field effect transistors comprise two vertical fins, each of which comprises a lower epitaxial layer surrounding the lower portion of the two vertical fins, an upper epitaxial layer surrounding the upper portion of the two vertical fins, and a shared epitaxial layer surrounding the middle portion of the two vertical fins. The two-input logic gate also comprises (i) the two two-channel n-type field effect transistors and (ii) a connection layer contacting the lower epitaxial layer and the upper epitaxial layer of one of the two two-channel p-type field effect transistors.

[0007] In another embodiment, a three-input logic gate comprises three n-type field effect transistors and three p-type field effect transistors, the three n-type field effect transistors comprising a first set of one or more vertical fins, at least one vertical fin in the first set of one or more vertical fins comprising a lower epitaxial layer surrounding a lower portion of at least one vertical fin in the first set of one or more vertical fins, an upper epitaxial layer surrounding an upper portion of at least one vertical fin in the first set of one or more vertical fins, and a shared epitaxial layer surrounding a middle portion of at least one vertical fin in the first set of one or more vertical fins. The three p-type field effect transistors comprise a second set of one or more vertical fins, where at least one vertical fin in the second set of one or more vertical fins comprises a lower epitaxial layer surrounding a lower portion of at least one vertical fin in the second set of one or more vertical fins, an upper epitaxial layer surrounding an upper portion of at least one vertical fin in the second set of one or more vertical fins, and a shared epitaxial layer surrounding a middle portion of at least one vertical fin in the second set of one or more vertical fins. The three-input logic gate also comprises a connection layer contacting the lower epitaxial layer and the upper epitaxial layer of one of the one or more vertical fins in the first set and the at least one vertical fin in one of the one or more vertical fins in the second set. [Brief description of the drawings]

[0008] [Figure 1A] FIG. 2 is a top view of a stacked vertical transport field effect transistor inverter structure using two two-channel n-type field effect transistors and two two-channel p-type field effect transistors according to one embodiment of the present invention. [Figure 1B] FIG. 2 is a circuit diagram for an inverter, according to one embodiment of the present invention. [Figure 1C]FIG. 1 is a circuit diagram for a stacked vertical transport field effect transistor using a shared source / drain structure to connect the upper fin channel and the lower fin channel, in accordance with one embodiment of the present invention. [Figure 1D] 1B is a first cross-sectional view of the stacked vertical transport field effect transistor inverter structure of FIG. 1A in accordance with one embodiment of the present invention. [Figure 1E] 1B is a second cross-sectional view of the stacked vertical transport field effect transistor inverter structure of FIG. 1A in accordance with one embodiment of the present invention. [Figure 2A] FIG. 2 is a top view of a vertical transport field effect transistor inverter structure using two two-channel n-type field effect transistors and two two-channel p-type field effect transistors according to one embodiment of the present invention. [Figure 2B] 2B is a cross-sectional view of the vertical transport field effect transistor inverter structure of FIG. 2A according to one embodiment of the present invention. [Diagram 3] FIG. 2 illustrates a cross-sectional view of a semiconductor structure after forming an upper portion of a vertical fin in accordance with one embodiment of the present invention. [Figure 4] FIG. 4 is a cross-sectional view of the structure of FIG. 3 after forming a lower portion of a vertical fin, in accordance with one embodiment of the present invention. [Diagram 5] 5 is a cross-sectional view of the structure of FIG. 4 after forming a lower epitaxial layer, according to one embodiment of the present invention. [Figure 6] FIG. 6 is a cross-sectional view of the structure of FIG. 5 after forming a gate stack for a lower vertical transport field effect transistor in accordance with one embodiment of the present invention. [Figure 7A] FIG. 7 is a cross-sectional view of the structure of FIG. 6 after forming a shared epitaxial layer and spacers for the lower and upper vertical transport field effect transistors, according to one embodiment of the present invention. [Figure 7B] FIG. 7B is a top view of the structure of FIG. 7A, in accordance with one embodiment of the present invention. [Figure 8]FIG. 7B is a cross-sectional view of the structure of FIG. 7A after forming a gate stack and a top epitaxial layer for an upper vertical transport field effect transistor according to one embodiment of the present invention. [Figure 9] 9 is a cross-sectional view of the structure of FIG. 8 after removing the sacrificial layer surrounding the shared epitaxial layer, in accordance with one embodiment of the present invention. [Figure 10A] 10 is a cross-sectional view of the structure of FIG. 9 after forming a connecting layer surrounding the shared epitaxial layer, according to one embodiment of the present invention. [Figure 10B] FIG. 10B is a top view of the structure of FIG. 10A, in accordance with one embodiment of the present invention. [Figure 11A] FIG. 10B is a cross-sectional view of the structure of FIG. 10A after forming shared contacts to the lower and upper epitaxial layers and a shared contact to the gate stack, in accordance with one embodiment of the present invention. [Figure 11B] FIG. 11B is a top view of the structure of FIG. 11A, in accordance with one embodiment of the present invention. [Figure 11C] FIG. 10B is another cross-sectional view along the length of the fin of the structure of FIG. 10A after forming shared contacts to the lower and upper epitaxial layers and a shared contact to the gate stack in accordance with one embodiment of the present invention. [Figure 12] FIG. 1 illustrates a process flow diagram for forming a stacked vertical transport field effect transistor structure having a shared epitaxial layer between an upper vertical transport field effect transistor and a lower vertical transport field effect transistor in a vertical fin of the stacked vertical transport field effect transistor structure according to one embodiment of the present invention. [Figure 13A] FIG. 2 is a top view of a stacked vertical transport field effect transistor NAND2 structure using two two-channel n-type field effect transistors and two two-channel p-type field effect transistors according to one embodiment of the present invention. [Figure 13B] 4 is a circuit diagram and logic table for a NAND2 gate, according to one embodiment of the present invention. [Figure 13C]FIG. 13B is a cross-sectional view taken along a first one of the fins of the stacked vertical transport field effect transistor NAND2 structure of FIG. 13A in accordance with one embodiment of the present invention. [Figure 13D] FIG. 13B is a cross-sectional view taken across a fin of the stacked vertical transport field effect transistor NAND2 structure of FIG. 13A in accordance with one embodiment of the present invention. [Figure 13E] FIG. 13B is a cross-sectional view taken along a second one of the fins of the stacked vertical transport field effect transistor NAND2 structure of FIG. 13A in accordance with one embodiment of the present invention. [Figure 13F] FIG. 13B is another cross-sectional view taken across the fin of the stacked vertical transport field effect transistor NAND2 structure of FIG. 13A in accordance with one embodiment of the present invention. [Figure 14A] FIG. 2 is a top view of a vertical transport field effect transistor NAND2 structure using two two-channel n-type field effect transistors and two two-channel p-type field effect transistors according to one embodiment of the present invention. [Figure 14B] FIG. 14B is a cross-sectional view of the vertical transport field effect transistor NAND2 structure of FIG. 14A according to one embodiment of the present invention. [Figure 15A] FIG. 2 is a top view of a stacked vertical transport field effect transistor NOR2 structure using two two-channel n-type field effect transistors and two two-channel p-type field effect transistors according to one embodiment of the present invention. [Figure 15B] 2 is a circuit diagram and logic table for a NOR2 gate, according to one embodiment of the present invention. [Figure 15C] FIG. 15B is a cross-sectional view taken along a first one of the fins of the stacked vertical transport field effect transistor NOR2 structure of FIG. 15A in accordance with one embodiment of the present invention. [Figure 15D] FIG. 15B is a cross-sectional view taken across the fin of the stacked vertical transport field effect transistor NOR2 structure of FIG. 15A in accordance with one embodiment of the present invention. [Figure 15E]FIG. 15B is a cross-sectional view taken along a second one of the fins of the stacked vertical transport field effect transistor NOR2 structure of FIG. 15A in accordance with one embodiment of the present invention. [Figure 15F] FIG. 15B is another cross-sectional view taken across the fin of the stacked vertical transport field effect transistor NOR2 structure of FIG. 15A in accordance with one embodiment of the present invention. [Figure 15G] FIG. 15B is a cross-sectional view taken along the output of the stacked vertical transport field effect transistor NOR2 structure of FIG. 15A in accordance with one embodiment of the present invention. [Figure 16A] FIG. 2 is a top view of a vertical transport field effect transistor NOR2 structure using two two-channel n-type field effect transistors and two two-channel p-type field effect transistors according to one embodiment of the present invention. [Figure 16B] FIG. 16B is a cross-sectional view of the vertical transport field effect transistor NOR2 structure of FIG. 16A according to one embodiment of the present invention. [Figure 17] 6 is a cross-sectional view of the structure of FIG. 5 after forming a lower epitaxial layer and shallow trench isolation regions, in accordance with one embodiment of the present invention. [Figure 18A] FIG. 18 is a cross-sectional view of the structure of FIG. 17 after forming a gate stack for a lower vertical transport field effect transistor in accordance with one embodiment of the present invention. [Figure 18B] FIG. 18B is a top cross-sectional view of the structure of FIG. 18A, in accordance with one embodiment of the present invention. [Figure 19] FIG. 18B is a cross-sectional view of the structure of FIG. 18A after forming a shared epitaxial layer, according to one embodiment of the present invention. [Figure 20A] FIG. 20 is a cross-sectional view of the structure of FIG. 19 after forming a sacrificial layer around the shared epitaxial layer in accordance with one embodiment of the present invention. [Figure 20B] FIG. 20 is another cross-sectional view of the structure of FIG. 19 after forming a sacrificial layer around the shared epitaxial layer in accordance with one embodiment of the present invention. [Figure 20C]FIG. 2C is a top cross-sectional view of the structure of FIGS. 20A and 20B for a stacked vertical transport field effect transistor NAND2 structure according to one embodiment of the present invention. [Figure 20D] FIG. 2C is a top cross-sectional view of the structure of FIGS. 20A and 20B for a stacked vertical transport field effect transistor NOR2 structure, according to one embodiment of the present invention. [Figure 21A] FIG. 20B is a cross-sectional view of the structure of FIG. 20A after forming a gate stack for an upper vertical transport field effect transistor in accordance with one embodiment of the present invention. [Figure 21B] FIG. 21B is a top cross-sectional view of the structure of FIG. 21A, in accordance with one embodiment of the present invention. [Figure 22A] FIG. 21B is a cross-sectional view of the structure of FIG. 21A after forming an upper epitaxial layer, according to one embodiment of the present invention. [Figure 22B] FIG. 22B is a top cross-sectional view of the structure of FIG. 22A, in accordance with one embodiment of the present invention. [Figure 23A] FIG. 22B is a cross-sectional view of the structure of FIG. 22A after forming contacts, according to one embodiment of the present invention. [Figure 23B] FIG. 22B is another cross-sectional view of the structure of FIG. 22A after forming contacts for the stacked vertical transport field effect transistor NAND2 structure according to one embodiment of the present invention. [Figure 23C] FIG. 22B is another cross-sectional view of the structure of FIG. 22A after forming contacts for the stacked vertical transport field effect transistor NAND2 structure according to one embodiment of the present invention. [Figure 23D] FIG. 22B is another cross-sectional view of the structure of FIG. 22A after forming contacts for the stacked vertical transport field effect transistor NOR2 structure, according to one embodiment of the present invention. [Figure 23E] FIG. 22B is another cross-sectional view of the structure of FIG. 22A after forming contacts for the stacked vertical transport field effect transistor NOR2 structure, according to one embodiment of the present invention. [Figure 24A] FIG. 2 is a top view of a stacked vertical transport field effect transistor NAND3 structure using three 1-channel n-type field effect transistors and three 1-channel p-type field effect transistors according to one embodiment of the present invention. [Figure 24B] FIG. 24B is a cross-sectional view of the stacked vertical transport field effect transistor NAND3 structure of FIG. 24A according to one embodiment of the present invention. [Figure 24C] FIG. 24B is another cross-sectional view of the stacked vertical transport field effect transistor NAND3 structure of FIG. 24A according to one embodiment of the present invention. [Figure 24D] 2 is a circuit diagram and logic table for a NAND3 logic gate, according to one embodiment of the present invention. [Diagram 25] FIG. 2 is a top view of a vertical transport field effect transistor NAND3 structure using three 1-channel n-type field effect transistors and three 1-channel p-type field effect transistors according to one embodiment of the present invention. [Figure 26A] FIG. 2 is a top view of a stacked vertical transport field effect transistor NOR3 structure using three 1-channel n-type field effect transistors and three 1-channel p-type field effect transistors according to one embodiment of the present invention. [Figure 26B] FIG. 26B is a cross-sectional view of the stacked vertical transport field effect transistor NOR3 structure of FIG. 26A according to one embodiment of the present invention. [Figure 26C] FIG. 26B is another cross-sectional view of the stacked vertical transport field effect transistor NOR3 structure of FIG. 26A according to one embodiment of the present invention. [Figure 26D] 2 is a circuit diagram and logic table for a NOR3 logic gate, according to one embodiment of the present invention. [Figure 27] FIG. 2 is a top view of a vertical transport field effect transistor NOR3 structure using three 1-channel n-type field effect transistors and three 1-channel p-type field effect transistors according to one embodiment of the present invention. [Figure 28] FIG. 2 illustrates a top view of a substrate after forming fins, according to one embodiment of the present invention. [Figure 29] FIG. 29 is a top view of the structure of FIG. 28 after forming the lower epitaxial layer, a lower spacer for the lower vertical transport field effect transistor, and patterning the gate stack for the lower vertical transport field effect transistor, in accordance with one embodiment of the present invention. [Diagram 30] FIG. 30 is a top view of the structure of FIG. 29 after forming an interlevel dielectric layer, according to one embodiment of the present invention. [Figure 31A] FIG. 31 is a top view of the structure of FIG. 30 after forming a shared intermediate epitaxial layer and a sacrificial material for patterning contacts to the shared intermediate epitaxial layer for a stacked vertical transport field effect transistor NAND3 structure according to one embodiment of the present invention. [Figure 31B] FIG. 31 is a top view of the structure of FIG. 30 after forming a shared intermediate epitaxial layer and a sacrificial material for patterning contacts to the shared intermediate epitaxial layer for a stacked vertical transport field effect transistor NOR3 structure according to one embodiment of the present invention. [Diagram 32] FIG. 31C is a top view of the structure of FIG. 31A or FIG. 31B after forming a bottom spacer for the upper vertical transport field effect transistor and patterning a gate stack for the upper vertical transport field effect transistor, according to one embodiment of the present invention. [Diagram 33] FIG. 33 is a top view of the structure of FIG. 32 after forming an upper spacer for the upper vertical transport field effect transistor and forming an upper epitaxial layer, according to one embodiment of the present invention. [Diagram 34] FIG. 34 is a top view of the structure of FIG. 33 after forming contacts, according to one embodiment of the present invention. [Figure 35A] FIG. 2 is a top view of a stacked vertical transport field effect transistor NAND3 structure using three two-channel n-type field effect transistors and three two-channel p-type field effect transistors according to one embodiment of the present invention. [Figure 35B] FIG. 35B is a cross-sectional view of the stacked vertical transport field effect transistor NAND3 structure of FIG. 35A according to one embodiment of the present invention. [Figure 35C] FIG. 35B is another cross-sectional view of the stacked vertical transport field effect transistor NAND3 structure of FIG. 35A according to one embodiment of the present invention. [Diagram 36]FIG. 2 is a top view of a vertical transport field effect transistor NAND3 structure using three two-channel n-type field effect transistors and three two-channel p-type field effect transistors according to one embodiment of the present invention. [Figure 37A] FIG. 2 is a top view of a stacked vertical transport field effect transistor NOR3 structure using three two-channel n-type field effect transistors and three two-channel p-type field effect transistors according to one embodiment of the present invention. [Figure 37B] FIG. 37B is a cross-sectional view of the stacked vertical transport field effect transistor NOR3 structure of FIG. 37A according to one embodiment of the present invention. [Figure 37C] FIG. 37B is another cross-sectional view of the stacked vertical transport field effect transistor NOR3 structure of FIG. 37A according to one embodiment of the present invention. [Figure 38] FIG. 2 is a top view of a vertical transport field effect transistor NOR3 structure using three two-channel n-type field effect transistors and three two-channel p-type field effect transistors according to one embodiment of the present invention. [Figure 39] FIG. 2 illustrates a top view of a substrate after forming fins, according to one embodiment of the present invention. [Diagram 40] FIG. 40 is a top view of the structure of FIG. 39 after forming the lower epitaxial layer, a lower spacer for the lower vertical transport field effect transistor, and patterning the gate stack for the lower vertical transport field effect transistor, in accordance with one embodiment of the present invention. [Diagram 41] FIG. 30 is a top view of the structure of FIG. 29 after forming an interlevel dielectric layer, according to one embodiment of the present invention. [Figure 42A] FIG. 42 is a top view of the structure of FIG. 41 after forming a shared intermediate epitaxial layer and a sacrificial material for patterning contacts to the shared intermediate epitaxial layer for a stacked vertical transport field effect transistor NAND3 structure according to one embodiment of the present invention. [Figure 42B]FIG. 42 is a top view of the structure of FIG. 41 after forming a shared intermediate epitaxial layer and a sacrificial material for patterning contacts to the shared intermediate epitaxial layer for a stacked vertical transport field effect transistor NOR3 structure according to one embodiment of the present invention. [Diagram 43] FIG. 42C is a top view of the structure of FIG. 42A or FIG. 42B after forming a bottom spacer for the upper vertical transport field effect transistor and patterning a gate stack for the upper vertical transport field effect transistor, according to one embodiment of the present invention. [Diagram 44] FIG. 33 is a top view of the structure of FIG. 32 after forming an upper spacer for the upper vertical transport field effect transistor and forming an upper epitaxial layer, according to one embodiment of the present invention. [Figure 45A] FIG. 45 is a top view of the structure of FIG. 44 after forming contacts for a stacked vertical transport field effect transistor NAND3 structure according to one embodiment of the present invention. [Figure 45B] FIG. 45 is a top view of the structure of FIG. 44 after forming contacts for a stacked vertical transport field effect transistor NOR3 structure according to one embodiment of the present invention. [Figure 46] FIG. 1 illustrates a process flow diagram for forming a stacked vertical transport field effect transistor structure having a shared epitaxial layer between an upper vertical transport field effect transistor and a lower vertical transport field effect transistor in a vertical fin of the stacked vertical transport field effect transistor structure according to one embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] Exemplary embodiments of the invention may be described herein in the context of exemplary methods for forming stacked vertical transport field effect transistor and logic gate structures having a shared epitaxial layer, as well as exemplary apparatus, systems, and devices formed using such methods. However, it should be understood that embodiments of the invention are not limited to the exemplary methods, apparatus, systems, and devices, but may be more broadly applicable to other suitable methods, apparatus, systems, and devices.

[0010] A field effect transistor (FET) is a transistor that has a source, a gate, and a drain, and whose operation depends on the flow of carriers (electrons or holes) along a channel running between the source and drain. The current through the channel between the source and drain can be controlled by a lateral electric field under the gate.

[0011] FETs are widely used for switching, amplifying, filtering, and other tasks. FETs include metal-oxide-semiconductor (MOS) FETs (MOSFETs). Complementary MOS (CMOS) devices are widely used, using both n-type and p-type transistors (NFETs and PFETs) to fabricate logic and other circuits. The source and drain regions of a FET are typically formed by adding dopants to target regions of a semiconductor body on either side of the channel, and a gate is formed above the channel. The gate includes a gate dielectric over the channel and a gate conductor over the gate dielectric. The gate dielectric is an insulating material that prevents large leakage currents from flowing into the channel when a voltage is applied to the gate conductor, while allowing the applied gate voltage to create a transverse electric field in the channel.

[0012] Increasing demands for higher density and performance in integrated circuit devices have necessitated the development of new structural and design features, including shorter gate lengths and other reductions in device size or scaling. However, continued scaling is reaching the limits of conventional manufacturing techniques.

[0013] Vertical stacking of FETs provides an additional dimension to CMOS area scaling. However, stacking planar FETs is difficult. Vertical transport FETs (VTFETs) are being pursued as a viable CMOS architecture for scaling beyond 7 nanometers (nm). VTFETs offer the opportunity to further scale devices compared to other device architectures. VTFETs have various potential advantages over other conventional structures such as fin field effect transistors (FinFETs). Such advantages may include improvements in density, performance, power consumption, and integration. VTFETs can provide additional advantages when stacking FETs.

[0014] Exemplary embodiments provide techniques for forming stacked VTFET structures, including stacked VTFET structures for various types of logic gates, including inverters, NAND gates, NOR gates, etc. In some embodiments, the stacked VTFET structures utilize a shared source / drain between an "upper" VTFET and a "lower" VTFET in the stacked VTFET structure.

[0015] For current VTFETs, one way to increase the drive current is to increase the contact area between the epitaxial layers that provide the source / drain to the channel. However, this approach compromises the area scaling of the VTFET, as the area of ​​this architecture depends on the size of the active area. Some embodiments provide techniques for inverter logic gate designs where the inverter uses 4-channel FETs, improving the effective width (Weff) by 33% compared to a 3-channel VTFET with the same top-down area. As the number of FET channels increases, the advantage over conventional VTFETs increases. The inverter design also utilizes a C-shaped connection between the drain region on the top fin channel and the drain region on the bottom fin channel, further realizing area scaling and track height reduction without sacrificing Weff.

[0016] In some embodiments, the inverter structure uses stacked fin VTFETs that share source / drain between the same device types (e.g., NFETs, PFETs). This structure does not require isolation between the top and bottom fin channels because the top and bottom fin channels share the same source / drain. In a stacked VTFET structure, the same device types (e.g., NFETs, PFETs) are stacked on top of each other (e.g., for a given fin, the top and bottom VTFETs are both NFETs or both PFETs). There are three epitaxial regions along the stacked fin. Depending on the configuration, the regions can be as follows: (i) two epitaxial layers provide the drain regions and one epitaxial layer provides a shared source region; (ii) two epitaxial layers provide the source regions and one epitaxial layer provides a shared drain region; or (iii) a shared epitaxial layer is the drain (or source) for the lower VTFET while being the source (or drain) for the upper VTFET.

[0017] For each fin, the structure may include a lower epitaxial layer for the fin channel of the lower VTFET, a lower spacer for the lower VTFET, a gate stack for the lower VTFET, an upper spacer for the lower VTFET, an epitaxial layer shared between the fin channel of the lower VTFET and the fin channel of the upper VTFET, a lower spacer for the upper VTFET, a gate stack for the upper VTFET, an upper spacer for the upper VTFET, and an upper epitaxial layer for the upper VTFET. The primary carriers (e.g., electrons and holes) of the NFET and PFET devices may or may not flow in opposite directions between the fin channel for the upper VTFET and the fin channel for the lower VTFET. Advantageously, such a structure reduces the top surface area by 33% compared to a non-stacked VTFET at the same Weff. For each fin, there are VTFETs of the same device type stacked on top of each other (e.g., for one fin the upper and lower VTFETs are both NFETs, and for another fin the upper and lower VTFETs are both PFETs.) In other words, the fin channel on top of another n-type channel for a fin providing an NFET is n-type, and the fin channel on top of another p-type channel for a fin providing a PFET is p-type.

[0018] The stacked VTFET inverter design utilizes a C-shaped middle-of-line (MOL) connection between two drain terminals on the same fin. Additional connections are included between this C-shaped MOL connection to the inverter output for the two drain terminals on the same fin, and between the two C-shaped MOL connections for the fins providing the NFET and PFET. The stacked VTFET inverter design allows for the use of two channels per fin without the use of a silicon-on-insulator (SOI) wafer. The stacked VTFET inverter design utilizes three epitaxial processes for the two-channel fin structure for each device type (e.g., three epitaxial processes for the fins providing the two p-type channels for the stacked PFET, and three epitaxial processes for the fins providing the two n-type channels for the stacked NFET).

[0019] 1A shows a top view of a stacked VTFET inverter structure 100. FIG 1A shows a set of two 2-channel PFETs 101, a set of two 2-channel NFETs 103, a high power rail 105, a low power rail 107, an input 109, and an output 111.

[0020] FIG. 1B shows a circuit diagram 125 illustrating the circuit connections to form an inverter having PFET 101, NFET 103, high power rail 105, low power rail 107, input 109, and output 111. Input 109 is coupled to the gate of PFET 101 and the gate of NFET 103. The source region of PFET 101 is connected to high power rail 105 and the source region of NFET 103 is connected to low power rail 107. The drain region of PFET 101 and the drain region of NFET 103 are connected to output 111. When input 109 is low, PFET 101 is on and NFET 103 is off. Thus, output 111 is high via PFET 101 connection to high power rail 105. When input 109 is high, PFET 101 is off and NFET 103 is on. Therefore, the output 111 goes low through the NFET 103 connection to the low power rail 107.

[0021] 1C shows a schematic 130 illustrating the connections between stacked VTFETs in one of the fins. As illustrated, the upper and lower FETs have a common gate and shared source / drain connections, allowing carrier flow to be flexible in or out of the upper or lower fin channel depending on the design.

[0022] FIG 1D illustrates a cross-sectional view 150 taken along line DD shown in top view 100 of FIG 1A across two fins providing NFET 103, which includes two two-channel NFETs. FIG 1D illustrates a lower drain region 102-1 for NFET 103, four NFET fin channels 104-1, 104-2, 104-3, and 104-4 for NFET 103, shared source regions 106-1 and 106-2 (e.g., one for each fin) for NFET 103, upper drain regions 108-1 and 108-2 (e.g., one for each fin) for NFET 103, and a gate stack 110 for NFET 103 (which may include, e.g., a gate dielectric and a gate conductor, such as a work function metal (WFM)). As illustrated, there is a C-shaped connection 112-1 connecting the lower drain region 102-1 for NFET 103 to the upper drain regions 108-1 and 108-2.

[0023] 1E shows a cross-sectional view 175 taken along line EE shown in top view 100 of FIG. 1A along one of the fins that provides two channels for PFET 101 and two channels for NFET 103. FIG. 1E shows a lower drain region 102-1 for NFET 103, a lower drain region 102-2 for PFET 101, two of the fin channels 104-1 and 104-2 for NFET 103, two of the fin channels 104-5 and 104-6 for PFET 101, an upper drain region 108-1 for NFET 103, one of the shared source regions 106-1 for NFET 103, one of the shared source regions 106-3 for PFET 101, an upper drain region 108-2 for PFET 101, and gate stacks 110 for PFET 101 and NFET 103. FIG. 1E shows a C-shaped connection 112-1 connecting the lower drain region 102-1 with the upper drain region 108-1 (and upper drain region 108-2, not shown) for NFET 103, and a C-shaped connection 112-2 connecting the lower drain region 102-2 with the upper drain region 108-3 (and another upper drain region, not shown) for PFET 101. The gate stack 110 is coupled to the input 109 of the inverter. FIG. 1E further shows a contact 114 from the high power rail 105 to the shared source region 106-3 for PFET 101, and a contact 116 from the low power rail 107 to the shared source region 106-1 for NFET 103. Although not shown, contacts 114 and 116 also connect to other shared source regions for PFET 101 and NFET 103.

[0024] The stacked VTFET inverter structure shown in Figures 1A-1E offers various advantages over non-stacked VTFETs and other approaches. For example, the stacked VTFET inverter structure shown in Figures 1A-1E utilizes parallel channels for PFET 101 and NFET 103, with the parallel channels having a length in the "X" direction of two contact poly pitches (CPPs) and a length in the "Z" direction of approximately 160 nanometers (nm). Figure 2A shows a top view 200 of a non-stacked VTFET structure having PFET 201 and NFET 203, where PFET 201 includes two two-channel PFETs and NFET 203 includes two two-channel NFETs. Figure 2B shows a cross-sectional view 250 taken along line B1-B1 for PFET 201 or line B2-B2 for NFET 203. Cross-section 250 shows four channels 204-1, 204-2, 204-3, and 204-4 (p-type channels for PFET 201 and n-type channels for NFET 203). The non-stacked VTFET structure of Figures 2A and 2B has a length in the "X" direction of 3 CPP and a length in the "Z" direction of approximately 160 nm, resulting in an area scaling of 1 compared to an area scaling of 0.7 for the stacked VTFET inverter structure of Figures 1A-1E. Tables 1 and 2 below illustrate the area scaling, cell height, fin length (Lfin), Weff, and Weff / sqrt(area) for the stacked VTFET inverters of FIGS. 1A-1E and the non-stacked VTFET inverters of FIGS. 2A and 2B, respectively, and Table 3 below illustrates the improvement in Weff / sqrt(area) for the stacked VTFET inverters of FIGS. 1A-1E compared to the non-stacked VTFET inverters of FIGS. 2A and 2B.

[0025] [Table 1]

[0026] [Table 2]

[0027] [Table 3]

[0028] In summary, for the same Weff, the stacked VTFET inverter structure of Figures 1A-1E occupies 33% less area compared to the non-stacked VTFET inverter structure of Figures 2A and 2B. For the same Y-length of 160 nm, the non-stacked VTFET inverter structure of Figures 2A-2B has an X-length of 3 CPP, with an area scaling of 1, while the stacked VTFET inverter structure of Figures 1A-1E has an X-length of 2 CPP, with an area scaling of 0.7. Note that this takes into account the space occupied by the C-shaped connections, which occupy 1 CPP.

[0029] An exemplary process for forming a stacked VTFET inverter structure will now be described with reference to FIGS.

[0030] 3 illustrates a cross-sectional view 300 of a substrate or wafer 302 after self-aligned double patterning (SADP) and fin etching to form upper fin portions 306-1 and 306-2 below a patterned hard mask layer 304. As described in more detail below, upper fin portion 306-1 provides a fin channel for an upper VTFET in a first fin, and upper fin portion 306-2 provides a fin channel for an upper VTFET in a second fin. FIG. 3 also illustrates the formation of a liner spacer layer 308 covering the top surface of substrate 302 and surrounding upper fin portions 306-1 and 306-2 and hard mask layer 304.

[0031] The bulk substrate 302 may be formed from any suitable semiconductor structure, including various silicon-containing materials, including but not limited to silicon (Si), silicon germanium (SiGe), silicon germanium carbide (SiGeC), silicon carbide (SiC), and multilayers thereof. Although silicon is the semiconductor material primarily used in wafer fabrication, alternative semiconductor materials may be employed for additional layers, such as but not limited to germanium (Ge), gallium arsenide (GaAs), gallium nitride (GaN), SiGe, cadmium telluride (CdTe), zinc selenide (ZnSe), and the like.

[0032] The horizontal thickness or width (in the X-X' direction) of substrate 302 may vary based on the number of fins formed, the spacing required for contacting the VTFETs formed from the structure, etc. The vertical thickness or height (in the Y-Y' direction) of substrate 302 may be in the range of 200 micrometers (μm) to 300 μm.

[0033] The hard mask layer 304 may be formed from a nitride, such as silicon nitride (SiN), although other suitable materials may be used. The hard mask layer 304 may be formed as a multilayer, such as a two-layer multilayer including a nitride and an oxide (e.g., SiN and silicon dioxide (SiO2)), a three-layer multilayer including one or more nitride layers and one or more oxide layers (e.g., SiN / SiO2 / SiN, SiO2 / SiN / SiO2), in some embodiments. The height or vertical thickness (in the Y-Y' direction) of the hard mask layer 304 may be in the range of 10 nm to 100 nm.

[0034] The upper fin portions 306-1 and 306-2 may be formed using other suitable techniques, such as sidewall image transfer (SIT) or lithography and etching, including reactive-ion etching (RIE). The width or horizontal thickness (in the X-X' direction) of each of the upper fin portions 306-1 and 306-2 may be in the range of 6 nm to 10 nm.

[0035] Although FIG. 3 illustrates the formation of an upper fin portion of two vertical fins, it should be understood that more or fewer vertical fins may be formed depending on the desired number of stacked VTFET structures.

[0036] The liner layer 308 protects the upper vertical fin portions 306-1 and 306-2 during downstream processing, which will be described in more detail below. The liner layer 308 may be formed from a very hard material, such as a high-k dielectric material, such as hafnium oxide (HfO2), a high-k / SiN multilayer, etc. The liner layer 308 may be formed by atomic layer deposition (ALD). The thickness (in the X-X' direction) of the liner layer 308 may be in the range of 3 nm to 6 nm.

[0037] FIG. 4 shows a cross-sectional view 400 of the structure of FIG. 3 after extending the vertical fin by additional fin etching (e.g., using RIE or other suitable etching process) to form lower fin portions 306-3 and 306-4. An additional liner layer 310 is then formed to cover the structure on the sidewalls of the upper and lower fin portions 306-1, 306-2, 306-3, and 306-4 and the hard mask layer 304. The lower fin portions 306-3 and 306-4 provide fin channels for the lower VTFET devices formed in the resulting structure. The height or vertical thickness (in the Y-Y' direction) of the lower fin portions 306-3 and 306-4 of the vertical fin may be in the range of 5 nm to 8 nm.

[0038] The additional liner layer 310 is a protective liner and may be formed of silicon boron carbide nitride (SiBCN). The additional liner layer 310 may be formed using selective ALD. The thickness (in the X-X' direction) of the additional liner layer 310 may be in the range of 2 nm to 4 nm.

[0039] FIG. 6 shows a cross-sectional view 600 of the structure of FIG. 5 after forming the lower epitaxial layer 312 and shallow trench isolation (STI) regions 314. This may be achieved by recessing the substrate 302 and epitaxially growing the lower epitaxial layer 312. The lower epitaxial layer 312 may provide a lower drain region when forming a stacked VTFET inverter. The lower epitaxial layer 312 is also referred to herein as the lower drain region 312, and its height or vertical thickness (in the Y-Y' direction) may be in the range of 15-30 nm. The lower drain region 312 surrounds both fins and provides two channels (e.g., either the two n-type channels of the NFET 103 or the two p-type channels of the PFET 101 in the stacked VTFET inverter structure of FIGS. 1A-1E).

[0040] The lower drain region 312 may be formed by implantation of a suitable dopant, for example, using ion implantation, gas phase doping, plasma doping, plasma immersion ion implantation, cluster doping, implantation doping, liquid phase doping, solid phase doping, etc. The n-type dopant may be selected from the group of phosphorus (P), arsenic (As), and antimony (Sb), and the p-type dopant may be selected from the group of boron (B), boron fluoride (BF2), gallium (Ga), indium (In), and thallium (Tl). The lower drain region 312 may also be formed by an epitaxial growth process. In some embodiments, the epitaxy process includes in-situ doping (dopants are incorporated into the epitaxy material during epitaxy). The epitaxial material may be grown from gaseous or liquid precursors. Epitaxial materials may be grown using vapor-phase epitaxy (VPE), molecular-beam epitaxy (MBE), liquid-phase epitaxy (LPE), rapid thermal chemical vapor deposition (RTCVD), metal organic chemical vapor deposition (MOCVD), ultra-high vacuum chemical vapor deposition (UHVCVD), low-pressure chemical vapor deposition (LPCVD), limited reaction processing CVD (LRPCVD), or other suitable processes. Epitaxial silicon, silicon-germanium (SiGe), germanium (Ge), or carbon-doped silicon (Si:C) silicon, or combinations thereof, can be doped during deposition (in-situ doping) by adding dopants such as n-type dopants (e.g., phosphorus or arsenic) or p-type dopants (e.g., boron or gallium), depending on the type of transistor.The dopant concentration is 1 × 10. 19 cm -3 From 3×10 21 cm -3 or preferably 2×10 20 cm -3 From 3×10 21 cm -3 The range may be between .

[0041] An STI region 314 is formed surrounding the lower drain region 312 to provide device isolation. The height or vertical thickness (in the Y-Y' direction) of the STI region 314 may be in the range of 50 to 400 nm. The STI region 314 may be formed from any suitable isolation material.

[0042] FIG. 7A illustrates a cross-sectional view 700 of the structure of FIG. 6 after forming a gate stack for the lower VTFET and forming an epitaxial layer shared between the upper and lower VTFETs. FIG. 7A illustrates a lower spacer layer 316 for the lower VTFET formed to surround a portion of the lower portions 306-3 and 306-4 of the vertical fins above the lower drain region 312 and the STI region 314. The lower spacer layer 316 may be formed using a variety of processes, such as non-conformal deposition and etch-back processes (e.g., physical vapor deposition (PVD), high density plasma (HDP) deposition, etc.). The lower spacer layer 316 may be formed of a dielectric material, such as SiO2, SiN, silicon carbide oxide (SiCO), SiBCN, etc. The height or vertical thickness (in the Y-Y' direction) of the lower spacer layer 316 may be in the range of 3 to 10 nm.

[0043] After the formation of the lower spacer layer 316, the gate stack material is deposited, including a gate dielectric layer 318 and a gate conductor layer 320. The gate dielectric layer 318 may be formed of a high-k dielectric material. Examples of high-k materials include, but are not limited to, metal oxides such as HfO2, hafnium silicon oxide (Hf-Si-O), hafnium silicon oxynitride (HfSiON), lanthanum oxide (La2O3), lanthanum aluminum oxide (LaAlO3), zirconium oxide (ZrO2), zirconium silicon oxide, zirconium silicon oxynitride, tantalum oxide (Ta2O5), titanium oxide (TiO2), barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide (Y2O3), aluminum oxide (Al2O3), lead scandium tantalum oxide, and lead zinc niobate. High-k materials may further include dopants such as lanthanum (La), aluminum (Al), and magnesium (Mg).The uniform thickness of the gate dielectric layer 120 may be in the range of 1 nm to 3 nm.

[0044] The gate conductor layer 320 may include a metal gate or a work function metal (WFM). In some embodiments, the gate conductor layer 320 is formed using ALD or another suitable process. For NFET devices, the WFM of the gate conductor may be titanium (Ti), aluminum (Al), titanium aluminum (TiAl), titanium aluminum carbon (TiAlC), a combination of Ti alloy and Al alloy, a stack including a barrier layer (e.g., of titanium nitride (TiN) or another suitable material) followed by one or more of the aforementioned WFM materials, and the like. For PFET devices, the WFM of the gate conductor may be TiN, tantalum nitride (TaN), or another suitable material. In some embodiments, the PFET WFM may include a metal stack in which a thicker barrier layer (e.g., TiN, TaN, etc.) is formed followed by a WFM such as Ti, Al, TiAl, TiAlC, or any combination of Ti alloy and Al alloy. It should be understood that various other materials may be used for the gate conductor layer 320 as desired. The thickness of the gate conductor layer 320 may be in the range of 5 to 20 nm.

[0045] An interlayer dielectric (ILD) layer 322 is formed and then the gate stack material is recessed to the level illustrated in FIG. 7A. The ILD layer 322 material is first formed to fill the structure (e.g., by first forming a liner, which may be SiN), followed by chemical mechanical planarization (CMP) and etchback. Alternatively, the ILD layer 322 material may be first formed using HDP and etchback processes to result in the ILD layer 322 as shown in FIG. 7A. The ILD layer 322 may be formed of any suitable isolation material, including, but not limited to, SiO2, SiOC, SiON, etc.

[0046] After formation of the ILD layer 322, the gate stack material (e.g., gate dielectric layer 318 and gate conductor layer 320) is recessed such that the height of the gate stack material matches the height of the ILD layer 322. The height or vertical thickness (in the Y-Y' direction) of the ILD layer 322 may be in the range of 10-30 nm. The recessed gate stack material provides the gate for the lower VTFET.

[0047] An upper spacer layer 324 for the lower VTFET is formed surrounding a portion of the lower portions 306-3 and 306-4 of the vertical fins on the ILD layer 322. The upper spacer layer 324 may be formed from similar materials and with similar sizing as described above with respect to the lower spacer layer 316.

[0048] A shared epitaxial layer 326 is formed over the upper spacer layer 324 surrounding a portion of the lower portions 306-3 and 306-4 of the vertical fins. The epitaxial layer 326 is shared between the upper and lower VTFETs. The shared epitaxial layer 326 may be formed from similar materials and by similar processes as described above with respect to the epitaxial layer 312. For stacked VTFET inverter structures, the shared epitaxial layer 326 provides a shared source for the upper and lower VTFETs and may also be referred to as a shared source region 326. The height or vertical thickness (in the Y-Y' direction) of the shared source region 326 may be in the range of 10-30 nm, and the width or horizontal thickness (in the X-X' direction) may be in the range of 5-15 nm.

[0049] A sacrificial layer 328 is formed to surround the shared source region 326. The sacrificial layer 328 is a silicon oxide (SiO x) or other suitable material. As described in more detail below, the sacrificial layer 328 is later removed and replaced with a metal material to form contacts to the power rails (e.g., high power rail for PFETs, low power rail for NFETs). The height or vertical thickness (in the Y-Y' direction) of the sacrificial layer 328 may match the height or vertical thickness of the shared source region 326, and the width or horizontal thickness (in the X-X' direction) may vary based on the type of connection required for the intermediate epitaxial layer.

[0050] FIG. 7B shows a top cross-sectional view 750 taken along line BB in cross-sectional view 700 of FIG. 7A, illustrating a shared source region 326 surrounding a portion of the lower portions 306-3 and 306-4 of the vertical fins, as well as a sacrificial layer 328 extending along the Z-Z' direction to provide a connection to a power rail 701.

[0051] 8 shows a cross-sectional view 800 of the structure of FIG. 7 after forming the gate stack and top epitaxial layers for the top VTFET. An ILD layer 330 is formed surrounding the sacrificial layer 328. The ILD layer 330 may be formed using materials and processes similar to those described above with respect to the ILD layer 322. A bottom spacer layer 332 for the top VTFET is formed above the ILD layer 330. The bottom spacer layer 332 may be formed using materials, processes, and sizing similar to those described above with respect to the bottom spacer layer 316.

[0052] The gate stack of the upper VTFET is then formed after removal of the liner 308. The gate stack for the upper VTFET includes a gate dielectric layer 334 and a gate conductor layer 336. The gate dielectric layer 334 and the gate conductor layer 336 may be formed using similar materials, processing, and sizing as described above with respect to the gate dielectric layer 318 and the gate conductor layer 320 of the gate stack for the lower VTFET. Although not shown, an interface layer may be formed between the gate stacks of the upper and lower VTFETs and the sidewalls of the lower and upper portions 306-3 and 306-4 and 306-1 and 306-2 of the vertical fin on which the gate stacks are formed. The interface layer may be formed of SiO2 or silicon oxynitride (SiO x N y The width or horizontal thickness (in the X-X' direction) of the interface layer may be in the range of 0.5 nm to 1.5 nm.

[0053] An ILD layer 338 is deposited surrounding the gate stack for the upper VTFET, the ILD layer 338 being formed using materials and processes similar to those described with respect to the ILD layer 322. An upper spacer layer 340 for the upper VTFET is formed over the ILD layer 338, the upper spacer layer 340 may be formed using materials, processes, and sizing similar to those described above with respect to the lower spacer layer 316.

[0054] The HM layer 304 is then removed using a selective wet etch or other suitable process to expose a portion of the top portions 306-1 and 306-2 of the vertical fins. An upper epitaxial layer 342 is then formed to surround a portion of the top portions 306-1 and 306-2 of the vertical fins. The height or vertical thickness (in the Y-Y' direction) of the upper epitaxial layer 342 may be in the range of 10-30 nm, and the width or horizontal thickness (in the X-X' direction) may be in the range of 10-30 nm. For stacked VTFET inverters, the upper epitaxial layer 342 provides the upper drain, and is therefore also referred to as the upper drain region 342. Another ILD layer 344 is then formed on top of the upper spacer layer 340 to surround the remaining portions of the top portions 306-1 and 306-2 of the fins and the upper drain region 342. ILD layer 344 may be formed using materials and processes similar to those described above with respect to ILD layer 322 .

[0055] Figure 9 shows the cross-sectional view 900 of Figure 8 after removing the sacrificial layer 328 surrounding the shared source region 326. The sacrificial layer 328 may be removed using any suitable process, such as a hydrofluoric (HF) etch.

[0056] FIG. 10A illustrates a cross-sectional view 1000 of the structure of FIG. 9 after forming a metal connection layer 346 in the space formed by the removal of the sacrificial layer 328. The metal connection layer 346 may be formed using ALD or other suitable processes. The metal connection layer 346 may include silicon (Si), TiN, or another suitable material. FIG. 10B illustrates a top cross-sectional view 1050 taken along line BB in the cross-sectional view 1000 of FIG. 10A. The top cross-sectional view 1050 illustrates the fin portions 306-3 and 306-4, the shared source region 326, and the metal connection layer 346 contacting the power rail 701 as described above.

[0057] FIG. 11A shows a cross-sectional view 1100 of the structure of FIG. 10A after forming a C-shaped contact 348 connecting the lower drain region 312 and the upper drain region 342. The C-shaped contact 348 will ultimately connect to the output of the stacked VTFET inverter structure. As discussed above, the C-shaped contact 348 for the four-channel FET shown in cross-sectional view 1100 is also connected to another C-shaped contact for another four-channel FET. For example, cross-sectional view 1100 may illustrate the NFET 103 of the stacked VTFET inverter structure of FIGS. 1A-1E, and another similar structure formed using a process similar to that described above with respect to FIGS. 3-11 is used to form the PFET 101 of the stacked VTFET inverter structure of FIGS. 1A-1E having another C-shaped contact connecting to the C-shaped contact 348.

[0058] A mask may be patterned over the ILD layer 344 to open a via 1101 on one side of the vertical fin down to the lower drain region 312 to form a C-shaped contact 348. Cross section 1100 is taken "across" the two vertical fins, similar to cross sections 300, 400, 500, 600, 700, 800, 900, and 1000 in Figures 3, 4, 5, 6, 7A, 8, 9, and 10A. Figure 11B is a top view 1150 of the structure shown in Figure 11A, showing the upper drain region 342, the metal connection layer 346 from the shared source region 326 to the power rail 701, and the top of the C-shaped contact 348 along the via 1101 down to the lower drain region 312. FIG. 11C shows another cross-section 1175 taken along the “length” (in the Z-Z′ direction) of one of the vertical fins. Cross-section 1175 shows contacts 350 to the gate stacks of the upper and lower VTFETs. Contacts 350 may be formed by patterning a mask layer on the ILD layer 344 down to the gate conductor layer 320 between two vertical fins providing two two-channel FETs (e.g., two two-channel NFETs 103 in the stacked VTFET inverter structure of FIGS. 1A-1E) and another set of two vertical fins providing two two-channel FETs (e.g., two two-channel PFETs 101 in the stacked VTFET inverter structure of FIGS. 1A-1E).

[0059] FIG. 12 illustrates a process flow 1200 for forming a stacked VTFET inverter. Process flow 1200 begins by starting a wafer or substrate (e.g., substrate 302) in step 1201. In step 1203, a hard mask layer (e.g., hard mask layer 304) is deposited, followed by SADP in step 1205. In step 1207, fin RIE is performed to form upper and lower portions of vertical fins (e.g., upper portions 306-1 and 306-2, lower portions 306-3 and 306-4) that provide fin channels for the upper and lower VTFETs in the stacked VTFET inverter. Liner layers (e.g., liner layers 308 and 310) may be formed to protect portions of the vertical fins during additional processing.

[0060] In step 1209, the substrate (e.g., substrate 302) is recessed, followed by the formation of a lower drain region (e.g., lower epitaxial layer 312) and an STI region (e.g., STI region 314). In step 1211, a lower spacer (e.g., lower spacer 316) for the lower VTFET is formed, followed by the formation of a gate stack (e.g., gate dielectric layer 318 and gate conductor layer 320) for the lower VTFET in step 1213.

[0061] In step 1215, litho-etch litho-etch (LELE) gate patterning is performed for the lower VTFET. Then, in step 1217, a top spacer (e.g., top spacer layer 324) for the lower VTFET is formed. In step 1219, a shared source (e.g., shared epitaxial layer 326) is formed, followed by a shared source contact cavity (e.g., sacrificial layer 328) and ILD (e.g., ILD layer 330) filling. Next, in step 1223, a bottom spacer (e.g., bottom spacer layer 332) for the upper VTFET is formed, followed by a gate stack (e.g., gate dielectric layer 334 and gate conductor layer 336) for the upper VTFET is formed in step 1225.

[0062] In step 1227, LELE gate patterning is performed for the upper VTFET. In step 1229, a top spacer (e.g., top spacer layer 340) for the upper VTFET is formed. In step 1231, a top drain (e.g., top epitaxial layer 342) is formed. In step 1233, the drain and gate contacts (e.g., drain contact 348, gate contact 350) are patterned. Then, in step 1235, the power rail contact to the shared source is patterned. For the NFET 103 in the stacked VTFET inverter structure of Figures 1A-1E, the shared source contacts the low power rail. For the PFET 101 in the stacked VTFET inverter structure of Figures 1A-1E, the shared source contacts the high power rail.

[0063] The stacked VTFET inverters described above with respect to Figures 1A-1E and 3-12 are one example of logic gates formed using stacked VTFETs using the techniques described herein. NAND and NOR logic gates may also be formed using the techniques described herein. Various embodiments are now described with respect to structures for forming two-input NAND and three-input NAND (NAND2 and NAND3) and two-input NOR and three-input NOR logic gates (e.g., NOR2, NOR3).

[0064] A NAND2 logic gate may be formed using two-channel PFETs and two-channel NFETs (e.g., two two-channel NFETs and two two-channel PFETs for a total of four two-channel FETs), and is therefore referred to as a NAND2 logic gate structure. The two-channel PFETs and two-channel NFETs are formed using a stacked VTFET structure, and for the two-channel NFETs, the upper fin channel and the lower fin channel of each fin are connected in series, and there is a shared epitaxial layer between the upper fin channel and the lower fin channel. The shared epitaxial layer is the drain region for the upper fin channel and the source region for the lower fin channel of the two-channel NFET. The shared epitaxial layer is also connected between the two fins such that the upper fin channels of each of the two fins are in parallel, forming one of two two-channel NFETs. Similarly, the lower fin channels of each of the two fins are connected in parallel, forming the other of two two-channel NFETs. The two-channel NFET formed by the upper fin-channel of the two fins is connected in series with the two-channel NFET formed by the lower fin-channel of the two fins.

[0065] As described above, the NAND2 logic gate structure includes a shared source / drain and a shared source-source for the top and bottom fin channels of the stacked VTFET. One fin includes the top and bottom fin channels for the NFET, and the shared source / drain includes the drain for the top fin channel and the source for the bottom fin channel. The other fin includes the top and bottom fin channels for the PFET, and there is a shared source for the top and bottom fin channels. For each NFET stacked fin, the top epitaxial layer is connected to the ground or low power rail and the bottom epitaxial layer is connected to the output, and vice versa. To form two inputs for the NAND circuit, gate contacts are formed at different depths to control separate gates for the stacked VTFET. Advantageously, the stacked VTFET NAND2 structure has a 33% reduction in top surface area compared to the non-stacked VTFET NAND2 structure at the same Weff. Furthermore, since the upper and lower fin channels share an epitaxial layer (e.g., a shared source / drain for NFETs or a shared source for PFETs), no insulation is needed between the upper and lower fin channels.

[0066] The stacked VTFET NAND2 structure utilizes an interconnect structure with vertical and horizontal trenches patterned at the same lithography level by single-step metallization. This is achieved using a buried sacrificial dielectric material surrounding a shared epitaxial layer. A top spacer or fin liner maintains the surface quality of the upper fin channel prior to gate dielectric deposition for the gate stack of the upper fin channel.

[0067] 13A-13F illustrate a stacked VTFET NAND2 structure including two two-channel PFETs 1301 and two two-channel NFETs 1303 formed using stacked VTFETs in two fins. FIG. 13A shows a top view 1300 of the stacked VTFET NAND2 structure, showing the two-channel PFETs 1301, the two-channel NFETs 1303, the high power rail 1305, the low power rail 1307, the first input 1309-1 and the second input 1309-2, and the output 1311.

[0068] FIG. 13B shows a circuit diagram 1325 for a NAND2 logic gate along with a logic table 1330 for the NAND2 logic gate. As illustrated in the circuit diagram 1325, the PFETs 1301 are connected in parallel with their sources connected to a high power rail 1305 and their drains connected to an output 1311. The NFETs 1303 are connected in series with a first one of the NFETs 1303 having a source connected to ground or a low power rail 1307 and a drain connected to a source of a second one of the NFETs 1303. The drain of the second one of the NFETs 1303 is connected to the output 1311. The gates of the PFETs 1301 and the NFETs 1303 are connected to a first input 1309-1 and a second input 1309-2. If both inputs 1309-1 and 1309-2 are high or 1, then both NFETs 1303 are on and output 1311 is 0 (e.g., output 1311 is pulled to low power rail 1307). If at least one of inputs 1309-1 and 1309-2 is low or 0, then at least one of NFETs 1303 is off and output 1311 is not pulled to low power rail 1307. Instead, if at least one of inputs 1309-1 and 1309-2 is low, then at least one of PFETs 1301 is on and output 1311 is 1 (e.g., output 1311 is pulled to high power rail 1305).

[0069] FIG. 13C shows a cross-sectional view 1350 taken along line CC shown in the top view 1300 of FIG. 13A, FIG. 13D shows a cross-sectional view 1375 taken along line DD shown in the top view 1300 of FIG. 13A, FIG. 13E shows a cross-sectional view 1385 taken along line EE in the top view 1300 of FIG. 13A, and FIG. 13F shows a cross-sectional view 1390 taken along line FF in the top view 1300 of FIG. 13A. Cross-sectional views 1350 and 1385 are taken along the length of the first and second fins in the Z-Z' direction, respectively. Cross-sectional views 1375 and 1390 are taken across the first and second fins, respectively, showing PFET fin channels 1304-5 through 1304-8 and NFET fin channels 1304-1 through 1304-4. NFET lower fin channel 1304-1 and NFET lower fin channel 1304-3 provide the lower NFET of the two-channel NFET 1303. NFET upper fin channel 1304-2 and NFET upper fin channel 1304-4 provide the upper NFET of the two-channel NFET 1303. PFET lower fin channel 1304-5 and PFET upper fin channel 1304-6 provide one side of the two-channel PFET 1301, and PFET lower fin channel 1304-7 and PFET upper fin channel 1304-8 provide the other side of the two-channel PFET 1301.

[0070] We now describe the epitaxial layers that provide the source and drain regions for two-channel PFET 1301 and two-channel NFET 1303. The top epitaxial layer for the upper fin channels 1304-2 and 1304-4 of the first of the two two-channel NFETs 1303 provides a source region 1306-1 that is coupled to low power rail 1307 via contact 1312-2. An intermediate epitaxial layer shared between (i) upper fin channels 1304-2 and 1304-4 providing a first one of two two-channel NFETs 1303 and (ii) lower fin channels 1304-1 and 1304-3 providing a second one of two two-channel NFETs 1303 provides a drain region 1302-1 for the first two-channel NFET (e.g., for the upper VTFET) and a source region 1306-2 for the second two-channel NFET (e.g., for the lower VTFET). A lower epitaxial layer for the lower fin channels 1304-1 and 1304-3 for the second one of two two-channel NFETs 1303 provides a drain region 1302-2 that is coupled to an output 1311 via a contact 1312-5. An intermediate epitaxial layer shared between the PFET lower fin channels 1304-5 and 1304-7 and the PFET upper fin channels 1304-6 and 1304-8 provides the respective shared source regions 1306-3 and 1306-4. The PFET lower fin channels 1304-5 and 1304-7 have a shared drain region 1302-3, and the PFET upper fin channels 1304-6 and 1304-8 have respective drain regions 1302-4 and 1302-5. Gate stacks 1310-1 through 1310-8 are formed for the fin channels 1304-1 through 1304-8, respectively.

[0071] We now describe the contacts for the stacked VTFET NAND2 structure of Figures 13A-13F. Contact 1312-1 connects source regions 1306-3 and 1306-4 of the first and second two-channel PFETs 1301 to the high power rail 1305. Contact 1312-2 connects source 1306-1 of the upper one of the two-channel NFETs 1303 to the low power rail 1307. Contact 1312-3 connects gate stacks 1310-3 and 1310-7 to the first input 1309-1. Contact 1312-4 connects gate stacks 1310-2 and 1310-6 to the second input 1309-2. Contact 1312-5 connects drains 1302-3, 1302-4, and 1302-5 of two-channel PFET 1301 and drain 1302-2 of the lower one of two-channel NFETs 1303 to output 1311.

[0072] The current flow in the stacked VTFET NAND2 structure of Figures 13A-13F will now be described. Current flows from the high power rail 1305 to the source regions 1306-3 and 1306-4 of the two two-channel PFETs 1301, then to the drain region 1302-3 (1313-1), and to the drain regions 1302-4 and 1302-5 (1313-2). The current then flows from the drain regions 1302-3, 1302-4, and 1302-5 to the drain region 1302-2 of the lower two-channel NFET of the two two-channel NFETs 1303. From there, the current flows to the intermediate epitaxial layer, which is the source region 1306-1 for the lower two-channel NFET of the two two-channel NFETs 1303 and the drain region 1302-1 of the upper two-channel NFET of the two two-channel NFETs 1303. The current flow continues (1313-4) to the source region 1306-1 of the upper channel NFET of the two two-channel NFETs 1303, which is coupled to the low power rail 1307 via contact 1312-2.

[0073] The stacked VTFET NAND2 structure shown in Figures 13A-13F offers various advantages over non-stacked VTFET NAND2 structures and other approaches. For example, the stacked VTFET NAND2 structure shown in Figures 13A-13F has a length in the "X" direction of 2 CPP and a length in the "Z" direction of approximately 230 nm.

[0074] Figure 14A shows a top view 1400 of a non-stacked VTFET NAND2 structure having four PFET channels 1401 and four NFET channels 1403. Figure 14B shows a cross-sectional view 1450 taken along line BB (e.g., along the length of one of the fins) in the top view 1400 of Figure 14A. Figure 14B shows NFET drain region 1402-1, NFET channel 1404-1, NFET source region 1406-1, NFET gate stack 1410-1, PFET drain 1402-2, PFET channel 1404-2, PFET source region 1406-2, and PFET gate region 1410-2. Contact 1412-1 connects PFET source region 1406-2 to high power rail 1405, contact 1412-2 connects NFET source region 1406-1 to low power rail 1407, contact 1412-3 connects gate stacks 1410-1 and 1410-2 to input 1409, and contact 1412-4 connects PFET drain region 1402-2 to output 1411. The non-stacked VTFET NAND2 structure of Figures 14A and 14B has a length in the "X" direction of 3 CPP and a length in the "Z" direction of 230 nm, resulting in an area scaling of 1 compared to an area scaling of 0.67 for the stacked VTFET NAND2 structure of Figures 13A-13F.

[0075] A NOR2 logic gate may also be formed using two-channel PFETs and two-channel NFETs (e.g., two two-channel NFETs and two two-channel PFETs for a total of four two-channel FETs), and is therefore referred to as a NOR2 logic gate structure. The two-channel PFETs and two-channel NFETs are formed using a stacked VTFET structure, where for the two-channel NFETs, the upper and lower fin channels of each fin are connected in parallel, and the connections between the first and second fins are also parallel. There is a shared epitaxial layer at the bottom of the lower NFET fin channels of the first and second fins. The two-channel PFET is composed of an upper fin channel and a lower fin channel along the same fin. There is a shared epitaxial layer at the bottom of the lower PFET fin channels of the first and second fins, where for the first fin, the shared epitaxial layer acts as the source region, and for the second fin, the shared epitaxial layer acts as the drain region.

[0076] The NOR2 logic gate structure includes a shared epitaxial layer between the upper and lower fin channels of the first and second fins. In the case of the NFET upper fin channel and the NFET lower fin channel, the shared epitaxial layer of the first and second fins provides the source region for the NFET upper fin channel and the NFET lower fin channel. In the case of the PFET upper fin channel and the PFET lower fin channel, the shared epitaxial layer of the first fin provides the source region and the shared epitaxial layer of the second fin provides the drain region. Each fin provides one two-channel NFET and one two-channel PFET for a total of four two-channel FETs (two two-channel NFETs and two two-channel PFETs). The epitaxial layer between the upper and lower fin channels is shared by the stacked VTFETs, and thus advantageously no insulation between the upper and lower fin channels is required. For the two-channel PFET, the shared epitaxial layer serves as the source region for the first fin and as the drain region for the second fin. For the first fin, the top and bottom epitaxial layers serve as the source region for the two-channel PFET. For the second fin, the top and bottom epitaxial layers serve as the drain region for the two-channel PFET. For the two-channel PFET, the shared epitaxial layer of one fin connects to the high power rail and the shared epitaxial layer of the other fin connects to the output of the stacked VTFET NOR2 structure. For the two-channel NFET, both the first and second fins use the shared epitaxial layer as a source region that connects to ground or the low power rail. The output of the stacked VTFET NOR2 structure connects to both the top and bottom epitaxial layers of the first and second fins for the two-channel NFET. The output connection from the drain terminal of one of the two-channel PFETs is at the same level as its shared epitaxial layer, while for the two-channel NFET the output connection is at the same level as the bottom epitaxial layer for the lower fin channel.The gate contacts for the stacked VTFET NOR2 structure can, but need not, be at different depths to control separate gates for the stacked VTFETs to form the two inputs for the NOR circuit. The stacked VTFET NOR2 structure, as an example, provides a 33% increase in Weff / area compared to the non-stacked VTFET NOR2 structure.

[0077] The stacked VTFET NOR2 structure utilizes an interconnect structure with vertical and horizontal trenches patterned at the same lithographic level by a single-step metallization process. This is achieved using a buried sacrificial dielectric material surrounding a shared epitaxial layer. A top spacer or fin liner maintains the surface quality of the upper fin channel prior to gate dielectric deposition for the gate stack of the upper fin channel.

[0078] 15A-15G illustrate a stacked VTFET NOR2 structure including two two-channel PFETs 1501 and two two-channel NFETs 1503 formed using stacked VTFETs in two fins. FIG. 15A shows a top view 1500 of the stacked VTFET NOR2 structure, showing the two-channel PFETs 1501, the two-channel NFETs 1503, the high power rail 1505, the low power rail 1507, the first and second inputs 1509-1 and 1509-2, the output 1511, and vias 1519 providing interconnection between the upper epitaxial layer providing the drain region 1502-5 and source region 1506-5 and the lower epitaxial layer providing the source region 1506-3 and drain region 1502-4, as described in more detail below.

[0079] FIG. 15B shows a circuit diagram 1525 for a NOR2 logic gate along with a logic table 1530 for the NOR2 logic gate. As illustrated in the circuit diagram 1525, the PFETs 1501 are connected in series with the source of a first one of the PFETs 1501 connected to a high power rail 1505 and the drain of a first one of the PFETs 1501 connected to the source of a second one of the PFETs 1501. The NFETs 1503 are connected in parallel with their sources connected to a low power rail 1507 and their drains connected to an output 1511. The drain of the second one of the PFETs 1501 also connects to the output 1511. The gates of the PFETs 1501 and the NFETs 1503 are connected to a first input 1509-1 and a second input 1509-2. If both inputs 1509-1 and 1509-2 are low or 0, then both PFETs 1501 are on and output 1511 is a 1 (e.g., output 1511 is pulled to high power rail 1505). If at least one of inputs 1509-1 and 1509-2 is high or 1, then at least one of NFETs 1503 is on and output 1511 is pulled to low power rail 1507, thus a 0.

[0080] Figure 15C shows a cross-sectional view 1550 taken along line CC shown in the top view 1500 of Figure 15A, Figure 15D shows a cross-sectional view 1575 taken along line DD shown in the top view 1500 of Figure 15A, Figure 15E shows a cross-sectional view 1585 taken along line EE in the top view 1500 of Figure 15A, Figure 15F shows a cross-sectional view 1590 taken along line FF in the top view 1500 of Figure 15A, and Figure 15G shows a cross-sectional view 1595 taken along line GG in the top view 1500 of Figure 15A. The cross-sectional views 1550 and 1585 are taken along the length of the first and second fins, respectively, in the Z-Z' direction. Cross section 1575 and cross section 1590 are taken across the first and second fins and show PFET fin channels 1504-5 through 1504-8 and NFET fin channels 1504-1 through 1504-4, respectively. Cross section 1595 is taken along the output in the Z-Z' direction. NFET lower fin channel 1504-1 and NFET upper fin channel 1504-2 of the first one of the fins provide one of the two two-channel NFETs 1503, and NFET lower fin channel 1504-3 and NFET upper fin channel 1504-4 of the second one of the fins provide the other of the two two-channel NFETs 1503. The PFET lower fin channel 1504-5 and the PFET upper fin channel 1504-6 of the first fin provide one of the two two-channel PFETs 1501, and the PFET lower fin channel 1504-7 and the PFET upper fin channel 1504-8 of the second fin provide the other of the two two-channel PFETs 1501.

[0081] We now describe the epitaxial layers providing the source and drain regions for two-channel PFET 1501 and two-channel NFET 1503. An intermediate epitaxial layer shared between NFET lower fin channel 1504-1 and NFET upper fin channel 1504-2 provides a shared source region 1506-1, and an intermediate epitaxial layer shared between NFET lower fin channel 1504-3 and NFET upper fin channel 1504-4 provides a shared source region 1506-2. The lower epitaxial layers of the first and second fins provide the drain region 1502-1 for NFET lower fin channels 1504-1 and 1504-3. The upper epitaxial layers of the first and second fins provide the drain regions 1502-2 and 1502-3 for NFET upper fin channels 1504-2 and 1504-4, respectively. The NFET lower fin channel 1504-1 and the NFET upper fin channel 1504-2 provide one of the two two-channel NFETs 1503, and the NFET lower fin channel 1504-3 and the NFET upper fin channel 1504-4 provide the other of the two two-channel NFETs 1503. An intermediate epitaxial layer shared between the PFET lower fin channel 1504-5 and the PFET upper fin channel 1504-6 provides a shared source region 1506-4, and an intermediate epitaxial layer shared between the PFET lower fin channel 1504-7 and the PFET upper fin channel 1504-8 provides a shared drain region 1502-6. The lower epitaxial layers of the first and second fins provide source region 1506-3 for PFET lower fin channel 1504-7 and drain region 1502-4 for PFET lower fin channel 1504-5. The upper epitaxial layer for PFET upper fin channel 1504-6 provides drain region 1502-5 and the upper epitaxial layer for PFET upper fin channel 1504-8 provides source region 1506-5. Gate stacks 1510-1 through 1510-8 are formed for fin channels 1504-1 through 1504-8, respectively.

[0082] We now describe the contacts for the stacked VTFET NOR2 structure of Figures 15A-15G. Contact 1512-1 connects the shared source region 1506-4 to the high power rail 1505. Contact 1512-2 connects the shared source regions 1506-1 and 1506-2 to the low power rail 1507. Contact 1512-3 connects the gate stacks 1510-2 and 1510-6 to the first input 1509-1. Contact 1512-4 connects the gate stacks 1510-3 and 1510-7 to the second input 1509-2. Contact 1512-5 connects the drain regions 1502-1, 1502-2, 1502-3, and 1502-6 together to the output 1511. Contact 1512-6 connects source region 1506-5 and drain region 1502-5.

[0083] We now describe the current flow in the stacked VTFET NOR2 structure of Figures 15A-15G. For PFET 1501, current flows from high power rail 1505 to source region 1506-4 (1513-1 and 1513-2), then from source region 1506-4 to drain regions 1502-4 and 1502-5 (1513-3 and 1513-4). Current then flows from drain region 1502-5 to source region 1506-5, and from drain region 1502-4 to source region 1506-3. From there, current flows from drain region 1502-4 to source region 1506-3 (which is a shared epitaxial layer) (1513-5), and from drain region 1502-5 to source region 1506-5 (1513-6). The current flow continues from source region 1506-3 to drain region 1502-6 (1513-7), and from source region 1506-5 to drain region 1502-6 (1513-8). The current then continues to flow (1513-9 and 1513-10) to the output 1511. For NFET 1503, the current flows from drain region 1502-2 to shared source 1506-1 (1513-11), from shared drain region 1502-1 to shared source region 1506-1 (1513-12), from drain region 1502-3 to shared source region 1506-2 (1513-13), and from shared drain region 1502-1 to shared source region 1506-2 (1513-14). The current flow continues from the shared source regions 1506-1 and 1506-2 to the low power rail 1507 (1513-15 and 1513-16).

[0084] The stacked VTFET NOR2 structure shown in Figures 15A-15G offers various advantages over non-stacked VTFET NOR2 structures and other approaches. For example, the stacked VTFET NOR2 structure shown in Figures 15A-15G has a length in the "X" direction of 2 CPP and a length in the "Z" direction of approximately 230 nm.

[0085] Figure 16A shows a top view 1600 of a non-stacked VTFET NOR2 structure having four PFET channels 1601 and four NFET channels 1603. Figure 16B shows a cross-sectional view 1650 taken along line BB (e.g., along the length of one of the fins) in the top view 1600 of Figure 16A. Figure 16B shows NFET drain region 1602-1, NFET channel 1604-1, NFET source region 1606-1, NFET gate stack 1610-1, PFET drain 1602-2, PFET channel 1604-2, PFET source region 1606-2, and PFET gate region 1610-2. Contact 1612-1 connects PFET source region 1606-2 to high power rail 1605, contact 1612-2 connects NFET source region 1606-1 to low power rail 1607, contact 1612-3 connects gate stacks 1610-1 and 1610-2 to input 1609, and contact 1612-4 connects NFET drain region 1602-2 to output 1611. The non-stacked VTFET NOR2 structure of Figures 16A and 16B has a length in the "X" direction of 3 CPP and a length in the "Z" direction of 230 nm, resulting in an area scaling of 1 compared to an area scaling of 0.67 for the stacked VTFET NOR2 structure of Figures 15A-15G.

[0086] An exemplary process for forming the stacked VTFET NAND2 and NOR2 structures will now be described with reference to Figures 3-5 and 17-23C. Figures 3-5 detail the formation of the upper and lower fin channels 306-1-306-4 and the formation of the liner layers 308 and 310, as described above.

[0087] Figure 17 shows a cross-sectional view 1700 of the structure of Figure 5 after forming a lower epitaxial layer 1712 and STI regions 1714. The lower epitaxial layer 1712 and STI regions 1714 may be formed from similar materials, and with similar sizing and processing, as described above with respect to the lower epitaxial layer 312 and STI regions 314.

[0088] Figure 18A shows a cross-sectional view 1800 of the structure of Figure 17 after removing the liner 310 and forming the gate stack for the lower VTFET. Figure 18A shows a lower spacer layer 1716 for the lower VTFET formed to surround the lower epitaxial layer 1712 and a portion of the lower portions 306-3 and 306-4 of the vertical fins over the STI regions 1714. The lower spacer layer 1716 may be formed from similar materials and with similar sizing and processing as described above for the lower spacer layer 316.

[0089] After formation of the lower spacer layer 1716, the gate stack material includes a gate dielectric layer 1718 and a gate conductor layer 1720, surrounded by an ILD layer 1722. The gate dielectric layer 1718, the gate conductor layer 1720, and the ILD layer 1722 may be formed from similar materials, and with similar sizing and processing, as described above with respect to the gate dielectric layer 318, the gate conductor layer 320, and the ILD layer 322.

[0090] FIG. 18B shows a top cross-sectional view 1850 taken along line BB in the cross-sectional view 1800 of FIG. 18A. The top cross-sectional view 1850 illustrates that the gate conductor 1720 surrounding the lower fin channel 306-2 (for one of the two-channel NFETs) also surrounds the lower fin channel 306-6 (for one of the two-channel PFETs). For a stacked VTFET NAND2 structure, the gate conductor 1720 surrounding the lower fin channels 306-2 and 306-6 connects to the first input 1309-1. For a stacked VTFET NOR2 structure, the gate conductor 1720 surrounding the lower fin channels 306-2 and 306-6 connects to the second input 1509-2.

[0091] Figure 19 shows a cross-sectional view 1900 of the structure of Figure 18A after forming the upper spacer layer 1724 for the lower VTFET and forming the shared epitaxial layer 1726. The upper spacer layer 1724 and the shared epitaxial layer 1726 may be formed from similar materials, and with similar sizing and processing, as described above with respect to the upper spacer layer 324 and the shared epitaxial layer 326.

[0092] Figure 20A shows a cross-sectional view 2000 of the structure of Figure 19 after forming a sacrificial layer 1728 that surrounds the shared epitaxial layer 1726. Figure 20A shows that the sacrificial layer 1728 does not connect the shared epitaxial layer 1726 for the lower fin channel.

[0093] Figure 20B shows another cross-sectional view 2050 after forming a sacrificial layer 1728 surrounding the shared epitaxial layer 1726. Figure 20B shows that the sacrificial layer 1728 connects the shared epitaxial layer 1726 for the lower fin channel.

[0094] For a stacked VTFET NAND2 structure (e.g., of Figures 13A-13F), Figure 20A illustrates that the sacrificial layer 1728 does not connect the shared epitaxial layer 1726 for the PFET (e.g., 1301), and Figure 20B illustrates that the sacrificial layer 1728 connects the shared epitaxial layer 1726 for the NFET (e.g., 1303). For a stacked VTFET NOR2 structure (e.g., of Figures 15A-15G), Figure 20A illustrates that the sacrificial layer 1728 does not connect the shared epitaxial layer 1726 for both the NFET (e.g., 1503) and the PFET (e.g., 1501). The sacrificial layer 1728 may include a FCVD oxide that is deposited and then etched back.

[0095] Figure 20C shows a top cross-sectional view 2075 illustrating how sacrificial layer 1728 connects shared epitaxial layer 1726 to power rail 2001 for the PFET of the stacked VTFET NAND2 structure of Figures 13A-13F. In the stacked VTFET NAND2 structure of Figures 13A-13F, power rail 2001 is high power rail 1305 that connects to shared epitaxial layer 1726, which is shared source regions 1306-3 and 1306-4.

[0096] Figure 20D shows a top cross-sectional view 2085 illustrating how the sacrificial layer 1728 connects the shared epitaxial layer 1726 to the power rail 2001 and output 2003 for the PFET of the stacked VTFET NOR2 structure of Figures 15A-15G. In the stacked VTFET NOR2 structure of Figures 15A-15G, the power rail 2001 is the high power rail 1505 that connects to the shared epitaxial layer 1726 that is the shared source region 1506-4. The output 2003 is the output 1511 that connects to the shared epitaxial layer 1726 that is the shared drain region 1502-6.

[0097] Figure 21A shows a cross-sectional view 2100 of the structure of Figure 20A after forming an ILD layer 1730, a lower spacer layer 1732, a gate stack for an upper VTFET including a gate dielectric layer 1734 and a gate conductor layer 1736, and an ILD layer 1738. The ILD layer 1730, the lower spacer layer 1732, the gate dielectric layer 1734, the gate conductor layer 1736, and the ILD layer 1738 may be formed from similar materials, and with similar sizing and processing, as described above with respect to the ILD layer 330, the lower spacer layer 332, the gate dielectric layer 334, the gate conductor layer 336, and the ILD layer 338.

[0098] FIG. 21B shows a top cross-sectional view 2150 taken along line BB in the cross-sectional view 2100 of FIG. 21A. The top cross-sectional view 2150 illustrates that the gate conductor layer 1736 surrounding the upper fin channel 306-1 (for one of the two-channel NFETs) also surrounds the upper fin channel 306-5 (for one of the two-channel PFETs). For a stacked VTFET NAND2 structure, the gate conductor 1736 surrounding the upper fin channels 306-1 and 306-5 connects to the second input 1309-2. For a stacked VTFET NOR2 structure, the gate conductor 1736 surrounding the upper fin channels 306-1 and 306-5 connects to the first input 1509-1.

[0099] FIG 22A shows a cross-sectional view 2200 of the structure of FIG 21A after forming the top spacer layer 1740, the top epitaxial layer 1742, and the ILD layer 1744. The top spacer layer, the top epitaxial layer 1742, and the ILD layer 1744 may be formed from similar materials and with similar sizing and processing as described above for the top spacer layer 340, the top epitaxial layer 342, and the ILD layer 344. FIG 22A also shows the formation of a sacrificial layer 1745 connecting the top epitaxial layer 1742. The sacrificial layer 1745 may be formed using similar materials and processing as described above for the sacrificial layer 328.

[0100] FIG. 22B shows a top cross-section 2250 taken along line BB in cross-section 2200 of FIG. 22A, illustrating how sacrificial layer 1745 connects upper epitaxial layer 1742 to vias 2201 down to lower epitaxial layer 1712. For a stacked VTFET NAND2 structure, sacrificial layer 1745 uses vias 2201 to connect PFET drain region 1302-4 to PFET drain regions 1302-5 and 1302-6, which then connect to output 1311. For a stacked VTFET NOR2 structure, sacrificial layer 1745 uses vias 2201 to connect NFET drain region 1502-1 to NFET drain regions 1502-2 and 1502-3, which then connect to output 1511.

[0101] Figure 23A shows a cross-section 2300 of the structure of Figure 22A after replacing the sacrificial layer 1745 with a contact 1748 to the output 1311 for a stacked VTFET NAND2 structure or to the output 1511 for a stacked VTFET NOR2 structure. For a stacked VTFET NAND2 structure, the cross-section 2300 is taken along line DD (e.g., across PFET 1301) in the top view 1300 of Figure 13A. For a stacked VTFET NOR2 structure, the cross-section 2300 is taken along line FF (e.g., across NFET 1503) in the top view 1500 of Figure 15A.

[0102] Figure 23B shows a cross-section 2350 of the structure of Figure 23A taken along the first fin along line CC in the top view 1300 of Figure 13A for a stacked VTFET NAND2 structure. Figure 23C shows a cross-section 2375 of the structure of Figure 23A taken along the second fin along line EE in the top view 1300 of Figure 13A for a stacked VTFET NAND2 structure. In Figures 23B and 23C, connections to the intermediate epitaxial layers 1726-1 through 1726-4 are not shown for clarity. In FIG. 23B, the lower epitaxial layer 1712-1 is the drain region 1302-2, the shared intermediate epitaxial layer 1726-1 is the drain region 1302-1 / source region 1306-2, the upper epitaxial layer 1742-1 is the source region 1306-1, the lower epitaxial layer 1712-2 is the drain region 1302-3, the shared intermediate epitaxial layer 1726-2 is the source region 1306-3, and the upper epitaxial layer 1742-2 is the drain region 1302-4. In FIG. 23C, the lower epitaxial layer 1712-3 is the drain region 1302-2, the shared intermediate epitaxial layer 1726-3 is the drain region 1302-1 / source region 1306-2, the upper epitaxial layer 1742-1 is the source region 1306-1, the lower epitaxial layer 1712-2 is the drain region 1302-3, the shared intermediate epitaxial layer 1726-2 is the source region 1306-4, and the upper epitaxial layer 1742-2 is the drain region 1302-5.

[0103] Figure 23D shows a cross-section 2385 of the structure of Figure 23A taken along the first fin along line CC in the top view 1500 of Figure 15A for a stacked VTFET NOR2 structure. Figure 23E shows a cross-section 2390 of the structure of Figure 23A taken along the second fin along line EE in the top view 1500 of Figure 15A for a stacked VTFET NOR2 structure. In Figures 23D and 23E, connections to the intermediate epitaxial layers 1726-1 through 1726-4 are not shown for clarity. In FIG. 23D, lower epitaxial layer 1712-1 is drain region 1502-1, shared intermediate epitaxial layer 1726-1 is source region 1506-1, upper epitaxial layer 1742-1 is drain region 1502-2, lower epitaxial layer 1712-2 is drain region 1502-4 and source region 1506-3, shared intermediate epitaxial layer 1726-2 is source region 1506-4, and upper epitaxial layer 1742-2 is drain region 1502-5. In FIG. 23E, the lower epitaxial layer 1712-3 is drain region 1502-1, the shared intermediate epitaxial layer 1526-3 is source region 1506-2, the upper epitaxial layer 1742-3 is drain region 1502-3, the lower epitaxial layer 1712-4 is drain region 1502-4 and source region 1506-3, the shared intermediate epitaxial layer 1726-4 is drain region 1502-6, and the upper epitaxial layer 1742-4 is source region 1506-5.

[0104] 23A-23E further illustrate contacts 1748, 1750, 1752, 1754, and 1756. Contact 1748 connects to output 1311 for the stacked VTFET NAND2 structure of FIGS. 13A-13F and output 1511 for the stacked VTFET NOR2 structure of FIGS. 15A-15G. Contact 1750 connects to low power rail 1307 for the stacked VTFET NAND2 structure of FIGS. 13A-13F. Contact 1752 connects to first input 1309-1 for the stacked VTFET NAND2 structure of FIGS. 13A-13F and first input 1509-1 for the stacked VTFET NOR2 structure of FIGS. 15A-15G. Contact 1754 connects to second input 1309-2 for the stacked VTFET NAND2 structure of Figures 13A-13F and to second input 1509-2 for the stacked VTFET NOR2 structure of Figures 15A-15G. Contact 1756 connects the top epitaxial layer of PFET 1501 of the VTFET NOR2 structure of Figures 15A-15G.

[0105] Contacts 1748, 1750, 1752, 1754, and 1756 may be formed of any suitable metal connection, similar to the materials of metal connection layer 346 described above. Some of the contacts are formed at least partially in areas where sacrificial layers 1728 and 1745 were previously formed. Sacrificial layers 1728 and 1745 may be removed using any suitable process, such as an HF etch.

[0106] NAND3 and NOR3 logic gates may also be formed using stacked VTFETs. Stacked VTFET NAND3 and NOR3 structures may include three 1-channel NFETs and three 1-channel PFETs, or three 2-channel NFETs and three 2-channel PFETs, using a shared intermediate epitaxial layer. For stacked VTFET NAND3 or NOR3 structures with three 1-channel NFETs and three 1-channel PFETs, a dummy fin channel is formed on top of the active fin channel. Three-dimensional (3D) parallel connections for pull-down utilize a shared epitaxial layer connection, and pull-up connections use a shared epitaxial layer and epitaxial interconnect for series connections. For pull-down, some embodiments utilize a "pearl chain" concept, in which the drain regions of the PFETs are in parallel and their connections are fused to form a series connection with the source of one of the NFETs, then split and fused again for the parallel fin connection. The dummy fin area is used to form the super via connection between the NFET and PFET.

[0107] Figure 24A shows a top view 2400 of a stacked VTFET NAND3 structure using three 1-channel PFETs 2401 and three 1-channel NFETs 2403. Figure 24B shows a cross section 2450 taken across the fins for the NFETs 2403, and Figure 24C shows a cross section 2475 taken across the fins for the PFETs 2401.

[0108] The stacked VTFET NAND3 structure of Figures 24A-C includes fin channels 2404-1 through 2404-8. Fin channel 2404-1 provides an NFET fin channel for a first one of NFETs 2403, fin channel 2404-2 is a dummy fin that is removed, fin channel 2404-3 provides an NFET fin channel for a second one of NFETs 2403, and fin channel 2404-4 provides an NFET fin channel for a third one of NFETs 2403. NFET fin channels 2404-3 and 2404-4 are stacked as illustrated. Fin channel 2404-5 provides a PFET fin channel for a first one of PFETs 2401, fin channel 2404-6 is a dummy fin that is removed, fin channel 2404-7 provides a PFET fin channel for a second one of PFETs 2401, and fin channel 2404-8 provides a PFET fin channel for a third one of PFETs 2401. PFET fin channels 2404-7 and 2404-8 are stacked as illustrated. Dummy fins 2415-1 and 2415-2 are also formed.

[0109] We now describe the epitaxial layers providing the source and drain regions for PFET 2401 and NFET 2403. The middle epitaxial layer for the first fin provides source region 2406-1 for a first one of NFETs 2403, the bottom epitaxial layer provides drain region 2402-1 for a first one of NFETs 2403 and drain region 2406-2 for a second one of NFETs 2403, the middle epitaxial layer for the second fin provides drain region 2402-2 for a second one of NFETs 2403 and source region 2406-3 for a third one of NFETs 2403, and the top epitaxial layer for the second fin provides drain region 2402-3 for a third one of NFETs 2403. Another intermediate epitaxial layer for the first fin provides source region 2406-6 for a first one of the PFETs 2401, another bottom epitaxial layer provides drain region 2402-2 for a first and second one of the PFETs 2401, another intermediate epitaxial layer for the second fin provides source region 2406-5 for a second and third one of the PFETs 2401, and another top epitaxial layer for the second fin provides drain region 2402-5 for a third one of the PFETs 2401. Gate stacks 2410-1 through 2410-6 are formed for fin channels 2404-1, 2404-3, 2404-4, 2404-5, 2404-7, and 2404-8, respectively. The NFETs 2403 are connected in series and the PFETs 2401 are connected in parallel.

[0110] The contacts for the stacked VTFET NAND3 structure of Figures 24A-C will now be described. Contact 2412-1 connects drain region 2402-3 for the third one of NFETs 2403 to output 2411, and contact 2412-2 connects drain regions 2402-4 and 2402-5 for PFET 2401 to output 2411. High power rail 2405 connects source regions 2406-4 and 2406-5 for PFET 2401. Low power rail 2507 connects source region 2406-1 for the first one of NFETs 2403. Input 2409-1 connects to gate stack 2410-1 for a first NFET of NFETs 2403 and gate stack 2410-4 for a first PFET of PFETs 2401, input 2409-2 connects to gate stack 2410-2 for a second NFET of NFETs 2403 and gate stack 2410-5 for a second PFET of PFETs 2401, and input 2409-3 connects to gate stack 2410-3 for a third NFET of NFETs 2403 and gate stack 2410-6 for a third PFET of PFETs 2401. Input 2409-3 may be connected within the area of ​​dummy fin 2415-1. Vias 2414-1 and 2414-2 connect contacts 2412-1 and 2412-2 to output 2411.

[0111] FIG. 24D shows a circuit diagram 2485 for a NAND3 logic gate along with a logic table 2490 for the NAND3 logic gate. As illustrated in the circuit diagram 2485, the PFETs 2401 are connected in parallel with their sources connected to the high power rail 2405 and their drains connected to the output 2411. The NFETs 2403 are connected in series with a first one of the NFETs 2403 having a source connected to ground or the low power rail 2407 and a drain connected to the source of the second one of the NFETs 2403. The drain of the second one of the NFETs 2403 is connected to the source of the third one of the NFETs 2403, and the drain of the third one of the NFETs 2403 is connected to the output 2411. The gates of the PFETs 2401 and the NFETs 2403 are connected to a first input 2409-1, a second input 2409-2, and a third input 2409-3. If inputs 2409-1, 2409-2, and 2409-3 are all high or 1, then all of the NFETs 2403 are on and output 2411 is 0 (e.g., output 2411 is pulled to low power rail 2407). If at least one of the inputs 2409-1, 2409-2, and 2409-3 is low or 0, then at least one of the NFETs 2403 is off and output 2411 is not pulled to low power rail 2407. Instead, if at least one of the inputs 2409-1, 2409-2, and 2409-3 is low, then at least one of the PFETs 2401 is on and output 2411 is 1 (e.g., output 2411 is pulled to high power rail 2405).

[0112] FIG. 25 shows a top view 2500 of a non-stacked VTFET NAND3 structure formed using three 1-channel PFETs 2501 and three 1-channel NFETs 2503. The non-stacked VTFET NAND3 structure of FIG. 25 includes NFET fin channels 2504-1, 2504-2, and 2504-3, and PFET fin channels 2504-4, 2504-5, and 2504-6. The bottom epitaxial layer provides source region 2506-1 for a first one of the NFETs 2503, which connects to low power rail 2507. The top epitaxial layer connects NFET fin channels 2504-1 and 2504-2, and provides drain region 2502-1 for NFET fin channel 2504-1 and source region 2506-2 for NFET fin channel 2504-2. The bottom epitaxial layer connects NFET fin channels 2504-2 and 2504-3 and provides drain region 2502-2 for NFET fin channel 2504-2 and source region 2506-3 for NFET fin channel 2504-3. The top epitaxial layer for NFET fin channel 2504-3 provides drain region 2502-3 that connects to output 2511. The bottom epitaxial layer provides drain region 2506-4 for PFET 2501 that connects to high power rail 2505. The top epitaxial layer for PFET fin channels 2504-4, 2504-5, and 2504-6 provides drain region 2502-4 that connects to output 2511. Input 2509-1 connects to the gate stacks of NFET fin channel 2504-1 and PFET fin channel 2504-4, input 2509-2 connects to the gate stacks of NFET fin channel 2504-2 and PFET fin channel 2504-5, and input 2509-3 connects to the gate stacks of NFET fin channel 2504-3 and PFET fin channel 2504-6.

[0113] The stacked VTFET NAND3 structure shown in Figures 24A-24C has a length in the "X" direction of 3 CPP, a height in the "Y" direction of 191 nm, and an area scaling of 1. Similarly, the non-stacked VTFET NAND3 structure shown in Figure 25 has a length in the "X" direction of 3 CPP, a height in the "Y" direction of 191 nm, and an area scaling of 1.

[0114] Figure 26A shows a top view 2600 of a stacked VTFET NOR3 structure using three 1-channel PFETs 2601 and three 1-channel NFETs 2603. Figure 26B shows a cross section 2650 taken across the fins for the NFETs 2603, and Figure 26C shows a cross section 2675 taken across the fins for the PFETs 2601.

[0115] The stacked VTFET NOR3 structure of Figures 26A-C includes fin channels 2604-1 through 2604-8. Fin channel 2604-1 provides an NFET fin channel for a first one of NFETs 2603, fin channel 2604-2 is a dummy fin that is removed, fin channel 2604-3 provides an NFET fin channel for a second one of NFETs 2603, and fin channel 2604-4 provides an NFET fin channel for a third one of NFETs 2603. NFET fin channels 2604-3 and 2604-4 are stacked as illustrated. Fin channel 2604-5 provides a PFET fin channel for a first one of the PFETs 2601, fin channel 2604-6 is a dummy fin that is removed, fin channel 2604-7 provides a PFET fin channel for a second one of the PFETs 2601, and fin channel 2604-8 provides a PFET fin channel for a third one of the PFETs 2601. PFET fin channels 2604-7 and 2604-8 are stacked as illustrated. Dummy fins 2615-1 and 2615-2 are also formed.

[0116] We now describe the epitaxial layers providing the source and drain regions for PFET 2601 and NFET 2603. The middle epitaxial layer for the first fin provides source region 2606-1 for a first one of NFETs 2603, the bottom epitaxial layer provides drain region 2602-1 for a first and second one of NFETs 2603, the middle epitaxial layer for the second fin provides source region 2606-2 for a second and third one of NFETs 2603, and the top epitaxial layer for the second fin provides drain region 2602-2 for a third one of NFETs 2603. Another intermediate epitaxial layer for the first fin provides a source region 2606-3 for a first PFET of PFETs 2601, another lower epitaxial layer provides a drain region 2602-3 for a first PFET of PFETs 2601 and a source region 2606-4 for a second PFET of PFETs 2601, the intermediate epitaxial layer for the second fin provides a drain region 2602-4 for a second PFET of PFETs 2601 and a source region 2606-5 for a third PFET of PFETs 2601, and the upper epitaxial layer for the second fin provides a drain region 2602-5 for the third PFET of PFETs 2601. Gate stacks 2610-1 through 2610-6 are formed for fin channels 2604-1, 2604-3, 2604-4, 2604-5, 2604-7, and 2604-8, respectively. The PFETs 2601 are connected in series and the NFETs 2603 are connected in parallel.

[0117] We now describe the contacts for the stacked VTFET NOR3 structure of Figures 26A-C. Contact 2612-1 connects drain region 2602-2 for the third one of NFETs 2603 to output 2611, and contact 2612-2 connects drain region 2602-5 for the third one of PFETs 2601 to output 2611. High power rail 2605 connects source region 2606-3 for the first one of PFETs 2601. Low power rail 2607 connects source regions 2606-1 and 2606-2 for NFET 2603. Input 2609-1 connects to gate stack 2610-1 for a first NFET of NFETs 2603 and gate stack 2610-4 for a first PFET of PFETs 2601, input 2609-2 connects to gate stack 2610-2 for a second NFET of NFETs 2603 and gate stack 2610-5 for a second PFET of PFETs 2601, and input 2609-3 connects to gate stack 2610-3 for a third NFET of NFETs 2603 and gate stack 2610-6 for a third PFET of PFETs 2601. Input 2609-3 may be connected within the area of ​​dummy fin 2615-1. Via 2614 connects contact 2612-1 to output 2611.

[0118] FIG. 26D shows a circuit diagram 2685 for a NOR3 logic gate along with a logic table 2690 for the NOR3 logic gate. As illustrated in the circuit diagram 2685, the NFETs 2603 are connected in parallel with their sources connected to the low power rail 2607 and their drains connected to the output 2611. The PFETs 2601 are connected in series with a first one of the PFETs 2601 having a source connected to the high power rail 2605 and a drain connected to a source of a second one of the PFETs 2601. The drain of the second one of the PFETs 2601 is connected to a source of a third one of the PFETs 2601, and the drain of the third one of the PFETs 2601 is connected to the output 2611. The gates of the PFETs 2601 and the NFETs 2603 are connected to a first input 2609-1, a second input 2609-2, and a third input 2609-3. If inputs 2609-1, 2609-2, and 2609-3 are all low or 0, then all of the PFETs 2601 are on and outputs 2611 are 1 (e.g., output 2611 is pulled to high power rail 2605). If at least one of inputs 2609-1, 2609-2, and 2609-3 is high or 1, then at least one of the PFETs 2601 is off and output 2611 is not pulled to high power rail 2605. Instead, if at least one of inputs 2609-1, 2609-2, and 2609-3 is high, then at least one of the NFETs 2603 is on and output 2611 is 0 (e.g., output 2611 is pulled to low power rail 2607).

[0119] FIG. 27 shows a top view 2700 of a non-stacked VTFET NOR3 structure formed using three 1-channel PFETs 2701 and three 1-channel NFETs 2703. The non-stacked VTFET NOR3 structure of FIG. 27 includes NFET fin channels 2704-1, 2704-2, and 2704-3, and PFET fin channels 2704-4, 2704-5, and 2704-6. The bottom epitaxial layer provides a source region 2706-1 for NFET 2703, which connects to low power rail 2707. The top epitaxial layer connects NFET fin channels 2704-1, 2704-2, 2704-3 to a drain region that connects to output 2711 via contact 2712-1. The bottom epitaxial layer provides the source region for PFET fin channel 2704-4 which connects to high power rail 2705. The top epitaxial layer for PFET fin channel 2704-4 connects to the top epitaxial layer for PFET fin channel 2704-5 and provides the drain region. The bottom epitaxial layer for PFET fin channels 2705-5 and 2704-6 provide the source region and the top epitaxial layer for PFET fin channel 2704-6 provides the drain region which connects to output 2711 via contact 2712-2. Input 2709-1 connects to the gate stacks of NFET fin channel 2704-1 and PFET fin channel 2704-4, input 2709-2 connects to the gate stacks of NFET fin channel 2704-2 and PFET fin channel 2704-5, and input 2709-3 connects to the gate stacks of NFET fin channel 2704-3 and PFET fin channel 2704-6.

[0120] The stacked VTFET NOR3 structure shown in Figures 26A-26C has a length in the "X" direction of 3 CPP and a height in the "Y" direction of 191 nm, with an area scaling of 1. Similarly, the non-stacked VTFET NOR3 structure shown in Figure 27 has a length in the "X" direction of 3 CPP and a height in the "Y" direction of 191 nm, with an area scaling of 1.

[0121] Here, a process for forming the stacked VTFET NAND3 structure of FIGS. 24A to 24C and the stacked VTFET NOR3 structure of FIGS. 26A to 26C will be described with reference to FIGS. 28 to 34.

[0122] FIG. 28 shows a top view 2800 illustrating a substrate 2802 on which a set of fins are formed using a patterned hard mask layer 2804. The fin formation may utilize SADP or other suitable processes. The substrate 2802 and hard mask layer 2804 may be formed from similar materials and with similar sizing and processing as described above with respect to the substrate 302 and hard mask layer 304. Although FIG. 28 shows eight fins being formed, some of the fins are "dummy" fins that will be removed using a fin sawing process.

[0123] FIG. 29 illustrates a top view 2900 of the structure of FIG. 28 after forming a lower epitaxial layer (not shown) and STI regions (not shown), forming a lower spacer layer 2816 for the lower VTFET, and patterning a gate stack for the lower VTFET. Patterning the gate stack includes forming a gate dielectric layer 2818 and a gate conductor layer 2820. As illustrated, the gate conductor layer 2820 connects a pair of fins to form contacts for the first 2409-1 and second 2409-2 inputs of the stacked VTFET NAND3 structure of FIGS. 24A-C or the first 2609-1 and second 2609-2 inputs of the stacked VTFET NOR3 structure of FIGS. 26A-C. The lower epitaxial layer, the STI region, the lower spacer layer 2816, the gate dielectric layer 2818, and the gate conductor layer 2820 may be formed from similar materials and with similar sizing and processing as described above with respect to the lower epitaxial layer 312, the STI region 314, the lower spacer layer 316, the gate dielectric layer 318, and the gate conductor layer 320.

[0124] Figure 30 shows a top view 3000 of the structure of Figure 29 after forming ILD layer 2822. ILD layer 2822 may be formed from similar materials, and with similar sizing and processing, as described above for ILD layer 322.

[0125] FIG. 31A shows a top view 3100 of the structure of FIG. 30 after forming the upper spacer layer 2824, the shared intermediate epitaxial layer 2826, and the sacrificial material 2828 for the lower VTFET. The sacrificial material 2828 in FIG. 31A is used to pattern contacts to the shared intermediate epitaxial layer 2826 of the different fin channels for the stacked VTFET NAND3 structure of FIGS. 24A-24C. More specifically, the sacrificial materials 2828-1 and 2828-2 are used to pattern contacts between the intermediate epitaxial layer 2826 (e.g., providing source regions 2406-4 and 2406-5 for PFET 2401) and the high power rail 2405. Sacrificial material 2828-3 is used to pattern a contact between intermediate epitaxial layer 2826 (eg, providing source region 2406-1 for a first one of NFETs 2403) and low power rail 2407.

[0126] FIG. 31B shows a top view 3150 of the structure of FIG. 30 after forming the upper spacer layer 2824, the shared intermediate epitaxial layer 2826, and the sacrificial material 2828 for the lower VTFET. The sacrificial material 2828 in FIG. 31B is used to pattern contacts to the shared intermediate epitaxial layer 2826 of the different fin channels for the stacked VTFET NOR3 structure of FIGS. 26A-C. More specifically, the sacrificial material 2828-1 is used to pattern contacts between the intermediate epitaxial layer 2826 (e.g., providing the source region 2606-3 for the first one of the PFETs 2601) and the high power rail 2605. Sacrificial materials 2828-2 and 2828-3 are used to pattern contacts between intermediate epitaxial layer 2826 (eg, providing source regions 2606-1 and 2606-2 for NFET 2603) and low power rail 2607.

[0127] The top spacer layer 2824, the shared intermediate epitaxial layer 2826, and the sacrificial material 2828 may be formed from similar materials and with similar sizing and processing as described above with respect to the top spacer layer 324, the shared intermediate epitaxial layer 326, and the sacrificial material 328.

[0128] FIG 32 shows a top view 3200 of the structure of FIG 31A or 31B after forming another ILD layer (not shown), a bottom spacer layer 2832 for the upper VTFET, and a gate stack including a gate dielectric layer 2834 and a gate conductor layer 2836 for the upper VTFET. As illustrated, the gate conductor layer 2836 connects the second fin to an area (e.g., 2414-1, 2514-1) within the region of one of the dummy fins where a via 3201 will be formed for contact to a third input (e.g., input 2409-3 for the stacked VTFET NAND3 structure of FIGS. 24A-C, input 2609-3 for the stacked VTFET NOR3 structure of FIGS. 26A-C). The ILD layer, lower spacer layer 2832, gate dielectric layer 2834, and gate conductor layer 2836 may be formed from similar materials and with similar sizing and processing as described above for the ILD layer 330, lower spacer layer 332, gate dielectric layer 334, and gate conductor layer 336.

[0129] Figure 33 shows a top view 3300 of the structure of Figure 32 after forming another ILD layer (not shown), an upper spacer layer 2840 for the upper VTFET, and an upper epitaxial layer 2842. The ILD layer, upper spacer layer 2840, and upper epitaxial layer 2842 may be formed from similar materials, and with similar sizing and processing, as described above with respect to the ILD layer 338, upper spacer layer 340, and upper epitaxial layer 342.

[0130] Figure 34 shows a top view 3400 of the structure of Figure 33 after forming an ILD layer 2844 for the upper VTFET. The ILD layer 2844 may be formed from similar materials, and with similar sizing and processing, as described above for the ILD layer 344. FIG. 34 also illustrates high power rails (e.g., 2405 for the stacked VTFET NAND3 structures of FIGS. 24A-24C, 2605 for the stacked VTFET NOR3 structures of FIGS. 26A-26C), low power rails (e.g., 2407 for the stacked VTFET NAND3 structures of FIGS. 24A-24C, 2607 for the stacked VTFET NOR3 structures of FIGS. 26A-26C), inputs (e.g., 2409-1, 2409-2, and 2409-3 for the stacked VTFET NAND3 structures of FIGS. 24A-24C, 2609-1, 2609-2, and 2609-3 for the stacked VTFET NOR3 structures of FIGS. 26A-26C), and outputs (e.g., 2409-1, 2409-2, and 2409-3 for the stacked VTFET NOR3 structures of FIGS. 26A-26C). FIG 34 illustrates the patterning of contacts for stacked VTFET NAND3 structures (e.g., 2411 for the NAND3 structure, 2611 for the stacked VTFET NOR3 structure of FIGS. 26A-C). FIG 34 also illustrates contacts (e.g., 2412-1 and 2412-2 for the stacked VTFET NOR3 structure of FIGS. 24A-C, 2612-1 and 2612-2 for the stacked VTFET NOR3 structure of FIGS. 26A-C) and vias (e.g., 2414-1 and 2414-2 for the stacked VTFET NAND3 structure of FIGS. 24A-C, 2614 for the stacked VTFET NOR3 structure of FIGS. 26A-C).

[0131] Figure 35A shows a top view 3500 of a stacked VTFET NAND3 structure using three two-channel PFETs 3501 and three two-channel NFETs 3503. Figure 35B shows a cross section 3550 taken across the fins for the NFETs 3503, and Figure 35C shows a cross section 3575 taken across the fins for the PFETs 3501.

[0132] The stacked VTFET NAND3 structure of Figures 35A-35C includes fin channels 3504-1 through 3504-12. Fin channels 3504-1 and 3504-2 provide a lower NFET fin channel and an upper NFET fin channel for a first one of the two-channel NFETs 3503, fin channels 3504-3 and 3504-4 provide a lower NFET fin channel and an upper NFET fin channel for a second one of the two-channel NFETs 3503, fin channels 3504-5 and 3504-6 provide a lower NFET fin channel and an upper NFET fin channel for a third one of the two-channel NFETs 3503, and fin channels 3504-8 and 3504-9 provide a lower NFET fin channel and an upper NFET fin channel for a third one of the two-channel NFETs 3503. Fin channels 3504-7 and 3504-8 provide a lower PFET fin channel and an upper PFET fin channel for a first one of the two-channel PFETs 3501, fin channels 3504-9 and 3504-10 provide a lower PFET fin channel and an upper PFET fin channel for a second one of the two-channel PFETs 3501, and fin channels 3504-11 and 3504-12 provide a lower PFET fin channel and an upper PFET fin channel for a third one of the two-channel PFETs 3501. Fin channels 3504-1 through 3504-12 are stacked as illustrated.

[0133] The epitaxial layers providing the source and drain regions for PFET 3501 and NFET 3503 will now be described. For NFET 3503, the middle epitaxial layer for the first fin provides source region 3506-1 for the first one of the two-channel NFETs 3503, the top epitaxial layer for the first fin provides drain region 3502-1 for the first one of the two-channel NFETs 3503, the bottom epitaxial layers of the first and second fins provide drain region 3502-1 for the first one of the two-channel NFETs 3503 and source region 3506-2 for the second one of the two-channel NFETs 3503, and the middle epitaxial layer for the second fin provides drain region 3502-1 for the first one of the two-channel NFETs 3503 and source region 3506-2 for the second one of the two-channel NFETs 3503. The epitaxial layer for the second fin provides drain region 3502-3 for a second one of the two-channel NFETs 3503, the top epitaxial layer for the second fin provides source region 3506-3 for the second one of the two-channel NFETs 3503, the middle epitaxial layer for the third fin provides source region 3504-6 for a third one of the two-channel NFETs 3503, and the lower and upper epitaxial layers of the third fin provide drain regions 3502-4 and 3502-5 for the third one of the two-channel NFETs 3503. For PFET 3501, the middle epitaxial layers of the first fin, second fin, and third fin provide source regions 3506-5, 3506-6, and 3506-7 for the first, second, and third two-channel PFETs of the two-channel PFET 3501. The bottom and top epitaxial layers provide drain regions 3502-6, 3502-7, 3502-8, and 3502-9 for the two-channel PFET 3501. Gate stacks 3510-1 through 3510-12 are formed for fin channels 3504-1 through 3504-12, respectively. NFETs 3503 are connected in series and PFETs 3501 are connected in parallel.

[0134] The contacts for the stacked VTFET NAND3 structure of Figures 35A-35C will now be described. Contact 3512-1 connects drain region 3502-5 for the third one of the two-channel NFETs 3503 to output 3511, and contact 3512-2 connects drain regions 3502-6, 3502-7, 3502-8, and 3502-9 of PFET 3501 to output 3511. High power rail 3505 connects to source regions 3506-5, 3506-6, and 3506-7 of PFET 3501. Low power rail 3507 connects to source region 3506-1 for the first one of the two-channel NFETs 3503. Input 3509-1 connects to gate stacks 3510-1 and 3510-2 for a first one of two-channel NFETs 3503 and gate stacks 3510-7 and 3510-8 for a first one of two-channel PFETs 3501. Input 3509-2 connects to gate stacks 3510-3 and 3510-4 for a second one of two-channel NFETs 3503 and gate stacks 3510-9 and 3510-10 for a second one of two-channel PFETs 3501. Input 3509-3 connects to gate stacks 3510-5 and 3510-6 for a third one of two-channel NFETs 3503 and gate stacks 3510-11 and 3510-12 for a first one of two-channel PFETs 3501. Vias 3514-1 and 3514-2 connect contacts 3512-1 and 3512-2 to output 3511. Contact 3512-3 connects the upper epitaxial layers of the first and second fins for NFET 3503 (e.g., drain region 3502-1 and source region 3506-3). Contact 3512-3 can be located in the area between the first and second fins or between the fin and a power rail (e.g., low power rail 3507). The top view 3500 of FIG. 35A also shows via 3519 connecting the upper and lower epitaxial layers.

[0135] Figure 36 shows a top view 3600 of a non-stacked VTFET NAND3 structure formed using three two-channel PFETs 3601 and three two-channel NFETs 3603. The non-stacked VTFET NAND3 structure of Figure 36 includes NFET fin channels 3604-1 through 3604-6 and PFET fin channels 3604-7 through 3604-12.

[0136] NFET fin channels 3604-1 and 3604-2 provide a first one of two channel NFETs 3603 and have a bottom epitaxial layer that connects to low power rail 3607. The top epitaxial layer of NFET fin channels 3604-1 and 3604-2 provides a drain region that connects to the top epitaxial layer of NFET fin channels 3604-3 and 3604-4 that provides a second one of two channel NFETs 3603. The top epitaxial layer of NFET fin channels 3604-3 and 3604-4 provides a source region for the second one of two channel NFETs 3603 and the bottom epitaxial layer of NFET fin channels 3604-3 and 3604-4 provides a drain region for the second one of two channel NFETs 3603. The lower epitaxial layer of NFET fin channels 3604-3 and 3604-4 connects with the lower epitaxial layer of NFET fin channels 3604-5 and 3604-6 which provides a third one of the two-channel NFETs 3603. The lower epitaxial layer of NFET fin channels 3604-5 and 3604-6 provides a source region for the third one of the two-channel NFETs 3603, and the upper epitaxial layer of NFET fin channels 3604-5 and 3604-6 provides a drain region for the third one of the two-channel NFETs 3603, which connects to output 3611 via contact 3612-2.

[0137] The bottom epitaxial layer of PFET fin channels 3604-7 through 3604-12 provides a source region for PFET 3501 which connects to high power rail 3605, and the top epitaxial layer of PFET fin channels 3604-7 through 3604-12 provides a drain region for PFET 3501 which connects to output 3611 via contact 3612-1. PFET fin channels 3604-7 and 3604-8 provide a first two-channel PFET of two-channel PFET 3601, PFET fin channels 3604-9 and 3604-10 provide a second two-channel PFET of two-channel PFET 3601, and PFET fin channels 3604-11 and 3604-12 provide a third two-channel PFET of two-channel PFET 3601.

[0138] Input 3609-1 connects to the gate stacks of NFET fin channels 3604-1 and 3604-2 and the gate stacks of PFET fin channels 3604-7 and 3604-8, input 3609-2 connects to the gate stacks of NFET fin channels 3604-3 and 3604-4 and the gate stacks of PFET fin channels 3604-9 and 3604-10, and input 3609-3 connects to the gate stacks of NFET fin channels 3604-5 and 3604-6 and the gate stacks of PFET fin channels 3604-11 and 3604-12.

[0139] The stacked VTFET NAND3 structure shown in Figures 35A-35C has a length in the "X" direction of 3 CPP and a height in the "Y" direction of 191 nm, with an area scaling of 0.6. The non-stacked VTFET NAND3 structure shown in Figure 36 has a length in the "X" direction of 5 CPP and a height in the "Y" direction of 191 nm, with an area scaling of 1. Thus, the stacked VTFET NAND3 structure shown in Figures 35A-35C provides significant space savings over the non-stacked VTFET NAND3 structure of Figure 36.

[0140] Figure 37A shows a top view 3700 of a stacked VTFET NOR3 structure using three two-channel PFETs 3701 and three two-channel NFETs 3703. Figure 37B shows a cross section 3750 taken across the fins for the NFETs 3703, and Figure 37C shows a cross section 3775 taken across the fins for the PFETs 3701.

[0141] The stacked VTFET NOR3 structure of Figures 37A-37C includes fin channels 3704-1 through 3704-12. Fin channels 3704-1 and 3704-2 provide a lower NFET fin channel and an upper NFET fin channel for a first one of the two-channel NFETs 3703, fin channels 3704-3 and 3704-4 provide a lower NFET fin channel and an upper NFET fin channel for a second one of the two-channel NFETs 3703, fin channels 3704-5 and 3704-6 provide a lower NFET fin channel and an upper NFET fin channel for a third one of the two-channel NFETs 3703, and fin channels 3704-6 and 3704-7 provide a lower NFET fin channel and an upper NFET fin channel for a third one of the two-channel NFETs 3703. Fin channels 3704-7 and 3704-8 provide a lower PFET fin channel and an upper PFET fin channel for a first one of the two-channel PFETs 3701, fin channels 3704-9 and 3704-10 provide a lower PFET fin channel and an upper PFET fin channel for a second one of the two-channel PFETs 3701, and fin channels 3704-11 and 3704-12 provide a lower PFET fin channel and an upper PFET fin channel for a third one of the two-channel PFETs 3701. Fin channels 3704-1 through 3704-12 are stacked as illustrated.

[0142] We now describe the epitaxial layers that provide the source and drain regions for PFET 3701 and NFET 3703. For NFET 3703, the middle epitaxial layers of the first fin, second fin, and third fin provide source regions 3706-1, 3706-2, and 3706-3 for the first, second, and third two-channel NFETs of two-channel NFET 3703. The bottom and top epitaxial layers provide drain regions 3702-1, 3702-2, 3702-3, and 3702-4 for two-channel NFET 3703. For PFET 3501, the intermediate epitaxial layer for the first fin provides a source region 3706-4 for a first one of the two-channel PFETs 3701, the top epitaxial layer of the first fin provides a drain region 3702-5 for the first one of the two-channel PFETs 3701, the bottom epitaxial layers of the first fin and second fin provide a drain region 3702-6 for the first one of the two-channel PFETs 3701 and a source region 3706-5 for the second one of the two-channel PFETs 3701, and the intermediate epitaxial layer for the second fin provides a drain region 3702-7 for the first one of the two-channel PFETs 3701 and a source region 3706-8 for the second one of the two-channel PFETs 3701. The epitaxial layer for the second fin provides drain region 3702-7 for the second one of the two-channel PFETs 3701, the top epitaxial layer for the second fin provides source region 3706-6 for the second one of the two-channel PFETs 3701, the middle epitaxial layer for the third fin provides source region 3706-7 for the third one of the two-channel PFETs 3701, and the bottom and top epitaxial layers for the third fin provide drain regions 3702-8 and 3702-9 for the third one of the two-channel PFETs 3701. Gate stacks 3710-1 through 3710-12 are formed for the fin channels 3704-1 through 3704-12, respectively. The PFETs 3701 are connected in series and the NFETs 3703 are connected in parallel.

[0143] We now describe the contacts for the stacked VTFET NOR3 structure of Figures 37A-37C. Contact 3712-1 connects drain regions 3702-1 through 3702-4 of NFET 3703 to output 3711, and contact 3712-2 connects drain regions 3702-8 and 3702-9 for the third one of the two-channel PFETs 3701 to output 3711. High power rail 3705 connects to source region 3706-4 of the first one of the two-channel PFETs 3701. Low power rail 3707 connects to source regions 3706-1, 3706-2, and 3706-3 of NFET 3703.

[0144] Input 3709-1 connects to gate stacks 3710-1 and 3710-2 for a first two-channel NFET of two-channel NFET 3703, and gate stacks 3710-7 and 3710-8 for a first two-channel PFET of two-channel PFET 3701. Input 3709-2 connects to gate stacks 3710-3 and 3710-4 for a second two-channel NFET of two-channel NFET 3703, and gate stacks 3710-9 and 3710-10 for a second two-channel PFET of two-channel PFET 3701. Input 3709-3 connects to gate stacks 3710-5 and 3710-6 for a third two-channel NFET of two-channel NFET 3703, and gate stacks 3710-11 and 3710-12 for a first two-channel PFET of two-channel PFET 3701. Vias 3714-1 and 3714-2 connect contacts 3712-1 and 3712-2 to output 3711. Contact 3712-3 connects the upper epitaxial layers (e.g., drain region 3702-5 and source region 3706-6) of the first and second fins for PFET 3701. Via 3719 provides interconnection between the upper epitaxial layer providing drain region 3702-5 and source region 3706-5 and the lower epitaxial layer providing source region 3706-5 and drain region 3702-6.

[0145] Figure 38 shows a top view 3800 of a non-stacked VTFET NOR3 structure formed using three two-channel PFETs 3801 and three two-channel NFETs 3803. The non-stacked VTFET NOR3 structure of Figure 38 includes NFET fin channels 3804-1 through 3804-6, and PFET fin channels 3804-7 through 3804-12.

[0146] The lower epitaxial layer of NFET fin channels 3804-1 through 3804-6 provides a source region for NFET 3803 which connects to low power rail 3807, and the upper epitaxial layer of NFET fin channels 3804-1 through 3804-6 provides a drain region for NFET 3803 which connects to output 3811 via contact 3812-1. NFET fin channels 3804-1 and 3804-2 provide a first two-channel NFET of two-channel NFET 3803, NFET fin channels 3804-3 and 3804-4 provide a second two-channel NFET of two-channel NFET 3803, and NFET fin channels 3804-5 and 3804-6 provide a third two-channel NFET of two-channel NFET 3803.

[0147] PFET fin channels 3804-7 and 3804-8 provide a first one of two channel PFETs 3801 and have a bottom epitaxial layer that connects to high power rail 3805. The top epitaxial layer of PFET fin channels 3804-7 and 3804-8 provides a drain region that is connected via contact 3812-2 to the top epitaxial layer of PFET fin channels 3804-9 and 3804-10 that provides a second one of two channel PFETs 3801. The top epitaxial layer of PFET fin channels 3804-9 and 3804-10 provides a source region for the second one of two channel PFETs 3801 and the bottom epitaxial layer of PFET fin channels 3804-9 and 3804-10 provides a drain region for the second one of two channel PFETs 3801. The lower epitaxial layer of PFET fin channels 3804-9 and 3804-10 connects with the lower epitaxial layer of PFET fin channels 3804-11 and 3804-12 which provide a third two-channel PFET of two-channel PFET 3801. The lower epitaxial layer of PFET fin channels 3804-11 and 3804-12 provides a source region for the third two-channel PFET of two-channel PFET 3801, and the upper epitaxial layer of PFET fin channels 3804-11 and 3804-12 provides a drain region for the third two-channel PFET of two-channel PFET 3801, which drain region connects to output 3811.

[0148] Input 3809-1 connects to the gate stacks of NFET fin channels 3804-1 and 3804-2 and the gate stacks of PFET fin channels 3804-7 and 3804-8, input 3809-2 connects to the gate stacks of NFET fin channels 3804-3 and 3804-4 and the gate stacks of PFET fin channels 3804-9 and 3804-10, and input 3809-3 connects to the gate stacks of NFET fin channels 3804-5 and 3804-6 and the gate stacks of PFET fin channels 3804-11 and 3804-12.

[0149] The stacked VTFET NOR3 structure shown in Figures 37A-37C has a length in the "X" direction of 3 CPP and a height in the "Y" direction of 191 nm, with an area scaling of 0.6. The non-stacked VTFET NOR3 structure shown in Figure 38 has a length in the "X" direction of 5 CPP and a height in the "Y" direction of 191 nm, with an area scaling of 1. Thus, the stacked VTFET NOR3 structure shown in Figures 37A-37C provides significant space savings over the non-stacked VTFET NOR3 structure of Figure 38.

[0150] Now, a process for forming the stacked VTFET NAND3 structure of FIGS. 35A to 35C and the stacked VTFET NOR3 structure of FIGS. 37A to 37C will be described with reference to FIGS. 39 to 44.

[0151] FIG. 39 shows a top view 3900 illustrating a substrate 3902 on which a set of fins are formed using a patterned hard mask layer 3904. The fin formation may utilize SADP or other suitable processes. The substrate 3902 and hard mask layer 3904 may be formed from similar materials and with similar sizing and processing as described above with respect to the substrate 302 and hard mask layer 304. Although FIG. 39 shows eight fins being formed, some of the fins are "dummy" fins that will be removed using a fin sawing process.

[0152] FIG. 40 illustrates a top view 4000 of the structure of FIG. 39 after forming a lower epitaxial layer (not shown) and STI regions (not shown), forming a lower spacer layer 3916 for the lower VTFET, and patterning the gate stack for the lower VTFET. Patterning the gate stack includes forming a gate dielectric layer 3918 and a gate conductor layer 3920. As illustrated, the gate conductor layer 3920 connects a set of fins to form contacts for the first input 3509-1, the second input 3509-2, and the third input 3509-3 of the stacked VTFET NAND3 structure of FIGS. 35A-35C, or the first input 3709-1, the second input 3709-2, and the third input 3709-3 of the stacked VTFET NOR3 structure of FIGS. 37A-37C. The lower epitaxial layer, the STI region, the lower spacer layer 3916, the gate dielectric layer 3918, and the gate conductor layer 3920 may be formed from similar materials and with similar sizing and processing as described above with respect to the lower epitaxial layer 312, the STI region 314, the lower spacer layer 316, the gate dielectric layer 318, and the gate conductor layer 320.

[0153] Figure 41 shows a top view 4100 of the structure of Figure 40 after forming an ILD layer 3922. The ILD layer 3922 may be formed from similar materials and with similar sizing and processing as described above with respect to the ILD layer 322.

[0154] FIG. 42A shows a top view 4200 of the structure of FIG. 41 after forming an upper spacer layer 3924, a shared intermediate epitaxial layer 3926, and sacrificial material 3928 for the lower VTFET. The sacrificial material 3928 in FIG. 42A is used to pattern contacts to the shared intermediate epitaxial layer 3926 of the different fin channels for the stacked VTFET NAND3 structure of FIGS. 35A-35C. More specifically, sacrificial materials 3928-1, 3928-2, and 3928-3 are used to pattern contacts between the intermediate epitaxial layer 3926 (e.g., providing source regions 3506-5, 3506-6, and 3506-7 for PFET 3501) and the high power rail 3505. Sacrificial material 3928-4 is used to pattern contacts between intermediate epitaxial layer 3926 (e.g., providing source region 3506-1 for a first one of two-channel NFETs 3503) and low power rail 3507. Sacrificial material 3928-5 is used to connect the intermediate epitaxial layers of the second and third fins (e.g., providing drain region 3502-3 for a second one of two-channel NFETs 3503 and source region 3506-4 for a third one of two-channel NFETs 3503).

[0155] FIG. 42B shows a top view 4250 of the structure of FIG. 41 after forming the upper spacer layer 3924, the shared intermediate epitaxial layer 3926, and the sacrificial material 3928 for the lower VTFET. The sacrificial material 3928 in FIG. 42B is used to pattern contacts to the shared intermediate epitaxial layer 3926 of the different fin channels for the stacked VTFET NOR3 structure of FIGS. 37A-37C. More specifically, the sacrificial material 3928-1 is used to pattern contacts between the intermediate epitaxial layer 3926 (e.g., providing the source region 3706-4 for the first one of the two-channel PFETs 3701) and the high power rail 3705. Sacrificial materials 3928-2, 3928-3, and 3928-4 are used to pattern contacts between intermediate epitaxial layer 3926 (e.g., providing source regions 3706-1, 3706-2, and 3706-3 for NFET 3703) and low power rail 3707. Sacrificial material 3928-5 is used to connect the intermediate epitaxial layers of the second and third fins (e.g., providing drain region 3702-7 for a second one of two-channel PFETs 3701 and source region 3706-7 for a third one of two-channel PFETs 3701).

[0156] The top spacer layer 3924, the shared intermediate epitaxial layer 3926, and the sacrificial material 3928 may be formed from similar materials and with similar sizing and processing as described above with respect to the top spacer layer 324, the shared intermediate epitaxial layer 326, and the sacrificial material 328.

[0157] Figure 43 shows a top view 4300 of the structure of Figure 42A or 42B after forming a gate stack including another ILD layer (not shown), a lower spacer layer 3932 for the upper VTFET, and a gate dielectric layer 3934 and a gate conductor layer 3936 for the upper VTFET. The ILD layer, lower spacer layer 3932, gate dielectric layer 3934, and gate conductor layer 3936 may be formed from similar materials, and with similar sizing and processing, as described above with respect to the ILD layer 330, lower spacer layer 332, gate dielectric layer 334, and gate conductor layer 336.

[0158] Figure 44 shows a top view 4400 of the structure of Figure 43 after forming another ILD layer (not shown), an upper spacer layer 3940 for the upper VTFET, and an upper epitaxial layer 3942. The ILD layer, upper spacer layer 3940, and upper epitaxial layer 3942 may be formed from similar materials, and with similar sizing and processing, as described above with respect to the ILD layer 338, upper spacer layer 340, and upper epitaxial layer 342.

[0159] Figures 45A and 45B show top views 4500 and 4550, respectively, of the structure of Figure 44 after forming an ILD layer 3944 for the upper VTFET. The ILD layer 3944 may be formed from similar materials and with similar sizing and processing as described above with respect to the ILD layer 344.

[0160] FIG. 45A also illustrates the contact patterning for the stacked VTFET NAND3 structure of FIGS. 35A-35C, and FIG. 45B also illustrates the contact patterning for the stacked VTFET NOR3 structure of FIGS. 37A-37C. Such contact patterning may include high power rails (e.g., 3505 for the stacked VTFET NAND3 structures of FIGS. 35A-35C, 3705 for the stacked VTFET NOR3 structures of FIGS. 37A-37C), low power rails (e.g., 3507 for the stacked VTFET NAND3 structures of FIGS. 35A-35C, 3707 for the stacked VTFET NOR3 structures of FIGS. 37A-37C), inputs (e.g., 3509-1, 3509-2, and 3509-3 for the stacked VTFET NAND3 structures of FIGS. 35A-35C, 3709-1, 3709-2, and 3709-3 for the stacked VTFET NOR3 structures of FIGS. 37A-37C), and outputs (e.g., 3509-2, 3509-3 for the stacked VTFET NOR3 structures of FIGS. 37A-37C). 3511 for the stacked VTFET NAND3 structure, 3711 for the stacked VTFET NOR3 structure of Figures 37A-37C. Figures 45A and 45B also illustrate contacts (e.g., 3512-1 and 3512-2 for the stacked VTFET NAND3 structure of Figures 35A-35C, 3712-1 and 3712-2 for the stacked VTFET NOR3 structure of Figures 37A-37C) and vias (e.g., 3514-1 and 3514-2 for the stacked VTFET NAND3 structure of Figures 35A-35C, 3714 for the stacked VTFET NOR3 structure of Figures 37A-37C).

[0161] FIG. 46 illustrates a process flow 4600 for forming a stacked VTFET inverter, NAND2, NOR2, NAND3, or NOR3 structure. Process flow 4600 is similar to process flow 1200 described above. Process flow 4600 begins by initiating a wafer or substrate (e.g., substrate 302, 2802, 3902) in step 4601. In step 4603, a hard mask layer (e.g., hard mask layer 304, 2804, 3904) is deposited, followed by SADP in step 4605. In step 4607, fin RIE is performed to form the top and bottom portions of the vertical fins (e.g., top fin channel and bottom fin channel for top and bottom VTFETs). Step 4607 also includes an optional fin sawing process used when forming the NAND3 and NOR3 structures as described above. Liner layers (eg, liner layers 308 and 310) may be formed to protect portions of the vertical fins during further processing.

[0162] In step 4609, the substrate (e.g., substrate 302, 2802, 3902) is recessed, followed by formation of the lower epitaxial layer (e.g., lower epitaxial layer 312, 1712) and STI regions (e.g., STI region 314, 1714). In step 4611, a lower spacer (e.g., lower spacer 316, 1716, 2816, 3916) for the lower VTFET is formed, followed by formation of the gate stack (e.g., gate dielectric layer 318, 1718, 2818, 3918, gate conductor layer 320, 2820, 3920) for the lower VTFET in step 4613.

[0163] In step 4615, lithography-etch-lithography-etch (LELE) gate patterning is performed for the lower VTFET. Then, in step 4617, a top spacer (e.g., top spacer layer 324, 1724, 2824, 3924) for the lower VTFET is formed. In step 4619, an intermediate epitaxial layer (e.g., shared epitaxial layer 326, 1726, 2826, 3926) is formed, followed by patterning a sacrificial material (e.g., sacrificial material 328, 1728, 2828, 3928) for the intermediate epitaxial layer connection, and filling an ILD (e.g., ILD layer 330, 1730). Next, in step 4623, a lower spacer (e.g., lower spacer layer 332, 1732, 2832, 3932) for the upper VTFET is formed, followed by formation of a gate stack (e.g., gate dielectric layer 334, 1734, 2834, 3934 and gate conductor layer 336, 1736, 2836, 3936) for the upper VTFET in step 4625.

[0164] In step 4627, LELE gate patterning is performed for the upper VTFET. In step 4629, a top spacer (e.g., top spacer layer 340, 1740, 2840, 3940) for the upper VTFET is formed. In step 4631, a top epitaxial layer (e.g., top epitaxial layer 342, 1742, 2842, 3942) is formed. Then, in step 4633, the sacrificial material patterned in step 4621 is removed and replaced with contact material. Then, in step 4635, contact patterning is performed, including contacts to the lower, middle, and upper epitaxial layers (e.g., for connections to high power rails, low power rails, and outputs, as described elsewhere herein) and contacts to the gate stacks (e.g., for inputs, as described elsewhere herein), and connections between different ones of the upper, middle, and lower epitaxial layers, as needed.

[0165] In some embodiments, a semiconductor structure comprises two or more vertical fins, a lower epitaxial layer surrounding a lower portion of a given vertical fin of the two or more vertical fins, an upper epitaxial layer surrounding an upper portion of the given vertical fin of the two or more vertical fins, a shared epitaxial layer surrounding a middle portion of the given vertical fin of the two or more vertical fins, and a connection layer (e.g., a metal layer or a MOL connection) in contact with the lower epitaxial layer and the upper epitaxial layer, the connection layer being disposed on a lateral side of the two or more vertical fins.

[0166] A first region between the lower epitaxial layer and the shared epitaxial layer of a given vertical fin of the two or more vertical fins may include a first fin channel for the four-channel VTFET, a second region between the shared epitaxial layer and the upper epitaxial layer of a given vertical fin of the two or more vertical fins may include a second fin channel for the four-channel VTFET, the shared epitaxial layer may include a shared source region for the first fin channel and the second fin channel of the four-channel VTFET, and the lower epitaxial layer and the upper epitaxial layer may include a drain region for the first fin channel and a drain region for the second fin channel of the four-channel VTFET. The connection layer contacts the drain region for the first fin channel and the drain region for the second fin channel to an output of the inverter logic gate.

[0167] A first region between the lower epitaxial layer and the shared epitaxial layer of a given vertical fin of the two or more vertical fins may include a first fin channel for a two-channel VTFET, a second region between the shared epitaxial layer and the upper epitaxial layer of a given vertical fin of the two or more vertical fins may include a second fin channel for the two-channel VTFET, the shared epitaxial layer may include a shared source region for the first fin channel and the second fin channel of the two-channel VTFET, the lower epitaxial layer and the upper epitaxial layer may include a drain region for the first fin channel and a drain region for the second fin channel of the two-channel VTFET. The two-channel VTFET may include a PFET, and the connecting layer may connect the drain region for the first fin channel and the drain region for the second fin channel to an output of a two-input NAND logic gate. The two-channel VTFET may include an NFET, and the connecting layer may connect the drain region for the first fin channel and the drain region for the second fin channel to an output of the two-input NOR logic gate.

[0168] A first region between the lower epitaxial layer and the shared epitaxial layer of a given vertical fin of the two or more vertical fins may include a fin channel for a first one-channel VTFET, a second region between the shared epitaxial layer and the upper epitaxial layer of a given vertical fin of the two or more vertical fins may include a fin channel for a second one-channel VTFET, the shared epitaxial layer may include a shared source region for the first one-channel VTFET and the second one-channel VTFET, the lower epitaxial layer may include a drain region of the first one-channel VTFET, and the upper epitaxial layer may include a drain region of the second one-channel VTFET. The first one-channel VTFET and the second one-channel VTFET may include PFETs, and the connecting layer may connect the drain region of the first one-channel VTFET and the drain region of the second one-channel VTFET to an output of a three-input NAND logic gate. The first one-channel VTFET and the second one-channel VTFET may include NFETs, and the connecting layer may connect the drain region of the first one-channel VTFET and the drain region of the second one-channel VTFET to an output of a three-input NOR logic gate.

[0169] A first region between the lower epitaxial layer and the shared epitaxial layer of a given vertical fin of the two or more vertical fins may include a first fin channel for a two-channel VTFET, a second region between the shared epitaxial layer and the upper epitaxial layer of a given vertical fin of the two or more vertical fins may include a second fin channel for the two-channel VTFET, the shared epitaxial layer may include a shared source region for the two-channel VTFET, and the lower epitaxial layer and the upper epitaxial layer may include a drain region of the two-channel VTFET. The two-channel VTFET may include a PFET, and the connecting layer may connect the drain region of the two-channel VTFET to an output of a three-input NAND logic gate. The two-channel VTFET may include an NFET, and the connecting layer may connect the drain region of the two-channel VTFET to an output of a three-input NOR logic gate.

[0170] In some embodiments, a method of forming a semiconductor structure includes forming two or more vertical fins, forming a lower epitaxial layer surrounding a lower portion of a given vertical fin of the two or more vertical fins, forming an upper epitaxial layer surrounding an upper portion of the given vertical fin of the two or more vertical fins, forming a shared epitaxial layer surrounding a middle portion of the given vertical fin of the two or more vertical fins, and forming a connecting layer in contact with the lower epitaxial layer and the upper epitaxial layer, where the connecting layer is disposed on a lateral side of the two or more vertical fins.

[0171] The lower epitaxial layer and the upper epitaxial layer may include a drain region of at least one VTFET of the logic gate. The connecting layer may connect the drain region of the at least one VTFET to an output of the logic gate.

[0172] In some embodiments, the inverter logic gate comprises a four-channel NFET and a four-channel PFET. The four-channel NFET comprises two vertical fins, each of which comprises a lower epitaxial layer surrounding the lower portion of the two vertical fins, an upper epitaxial layer surrounding the upper portion of the two vertical fins, and a shared epitaxial layer surrounding the middle portion of the two vertical fins. The four-channel PFET comprises two vertical fins, each of which comprises a lower epitaxial layer surrounding the lower portion of the two vertical fins, an upper epitaxial layer surrounding the upper portion of the two vertical fins, and a shared epitaxial layer surrounding the middle portion of the two vertical fins. The inverter logic gate also comprises a connection layer (e.g., MOL connection) contacting the lower epitaxial layer and the upper epitaxial layer of the four-channel NFET and the four-channel PFET.

[0173] The inverter logic gate may further comprise an input of the inverter logic gate connected to a gate stack of the four-channel NFET and the four-channel PFET surrounding a portion between the lower epitaxial layer and the shared epitaxial layer and a portion between the shared epitaxial layer and the upper epitaxial layer of the two vertical fins, an output of the inverter logic gate connected to the lower epitaxial layer and the upper epitaxial layer of the four-channel NFET and the four-channel PFET, a first contact connected to the shared epitaxial layer of the four-channel PFET (e.g., connecting the shared epitaxial layer of the four-channel PFET to a high power rail), and a second contact connected to the shared epitaxial layer of the four-channel NFET (e.g., connecting the shared epitaxial layer of the four-channel NFET to a low power rail).

[0174] In some embodiments, the two-input logic gate comprises two two-channel NFETs and two two-channel PFETs. The two two-channel NFETs comprise two vertical fins, each of which comprises a lower epitaxial layer surrounding the lower portion of the two vertical fins, an upper epitaxial layer surrounding the upper portion of the two vertical fins, and a shared epitaxial layer surrounding the middle portion of the two vertical fins. The two two-channel PFETs comprise two vertical fins, each of which comprises a lower epitaxial layer surrounding the lower portion of the two vertical fins, an upper epitaxial layer surrounding the upper portion of the two vertical fins, and a shared epitaxial layer surrounding the middle portion of the two vertical fins. The two-input logic gate also comprises (i) the two two-channel NFETs and (ii) a connection layer (e.g., a MOL connection) contacting the lower epitaxial layer and the upper epitaxial layer of one of the two two-channel PFETs.

[0175] The two-input logic gate comprises a two-input NAND logic gate, a first input of the two-input NAND logic gate connected to a gate stack of a first two-channel NFET of the two two-channel NFETs and a gate stack of a first two-channel p-type field effect transistor of the two two-channel p-type field effect transistors, a second input of the two-input NAND logic gate connected to a gate stack of a second two-channel NFET of the two two-channel NFETs and a gate stack of a second two-channel PFET of the two two-channel PFETs, and a second input of the two-input NAND logic gate connected to a lower epitaxial layer and an upper epitaxial layer of the two two-channel PFETs via a MOL connection. and an output of a two-input NAND logic gate connected to a lower epitaxial layer of the two vertical fins of a first of the two two-channel NFETs; a first contact connected to a shared epitaxial layer of the two two-channel PFETs (e.g., connecting the shared epitaxial layer of the two two-channel PFETs to a high power rail); and a second contact connected to an upper epitaxial layer of the two vertical fins of a second of the two two-channel NFETs (e.g., connecting the upper epitaxial layer of the two vertical fins of the second of the two two-channel NFETs to a low power rail).

[0176] The two-input logic gate may comprise a two-input NOR logic gate, a first input of the two-input NOR logic gate connected to the gate stack of a first two-channel NFET of the two two-channel NFETs and the gate stack of a first two-channel PFET of the two two-channel PFETs, a second input of the two-input NOR logic gate connected to the gate stack of a second two-channel NFET of the two two-channel NFETs and the gate stack of a second two-channel PFET of the two two-channel PFETs, and a second input of the two-input NOR logic gate connected to the gate stack of a second two-channel NFET of the two two-channel NFETs and the gate stack of a second two-channel PFET of the two two-channel PFETs via a MOL connection to the bottom epitaxial layer and the top epitaxial layer of the two two-channel NFETs and the shared epitaxy of the first vertical fin of the two vertical fins of the first two-channel PFET. the output of the two-input NOR logic gate connected to a first shared epitaxial layer of the vertical fins of the second of the two two-channel PFETs; a first contact connected to a second shared epitaxial layer of a second vertical fin of the two vertical fins of the second of the two two-channel PFETs (e.g., connecting the second shared epitaxial layer of the second vertical fin of the two vertical fins of the second of the two two-channel PFETs to a high power rail); and a second contact connected to the shared epitaxial layer of the two vertical fins of the two two-channel NFETs (e.g., connecting the shared epitaxial layer of the two vertical fins of the two two-channel NFETs to a low power rail).

[0177] In some embodiments, the three-input logic gate comprises three NFETs and three PFETs, the three NFETs comprising a first set of one or more vertical fins, at least one vertical fin in the first set of one or more vertical fins comprising a lower epitaxial layer surrounding a lower portion of the at least one vertical fin in the first set of one or more vertical fins, an upper epitaxial layer surrounding an upper portion of the at least one vertical fin in the first set of one or more vertical fins, and a shared epitaxial layer surrounding a middle portion of the at least one vertical fin in the first set of one or more vertical fins. The three PFETs comprise a second set of one or more vertical fins, where at least one vertical fin in the second set of one or more vertical fins comprises a lower epitaxial layer surrounding a lower portion of at least one vertical fin in the second set of one or more vertical fins, an upper epitaxial layer surrounding an upper portion of at least one vertical fin in the first set of one or more vertical fins, and a shared epitaxial layer surrounding a middle portion of at least one vertical fin in the second set of one or more vertical fins. The three-input logic gate also comprises a connection layer (e.g., a MOL connection) contacting the lower epitaxial layer and the upper epitaxial layer of one of the first set of one or more vertical fins and the at least one vertical fin in one of the second set of one or more vertical fins.

[0178] The three-input logic gate may comprise a three-input NAND logic gate, the three NFETs may comprise three one-channel NFETs, and the three PFETs may comprise three one-channel PFETs, the three-input logic gate having a first input of the three-input NAND logic gate connected to a gate stack of a first one-channel NFET of the three one-channel NFETs and a gate stack of a first two-channel PFET of the three one-channel PFETs, a second input of the three-input NAND logic gate connected to a gate stack of a second one-channel NFET of the three one-channel NFETs and a gate stack of a second one-channel PFET of the three one-channel PFETs, a third input of the three-input NAND logic gate connected to a gate stack of a third one-channel NFET of the three one-channel NFETs and a gate stack of a third one-channel PFET of the three one-channel PFETs, and a third input of the three-input NAND logic gate connected to a gate stack of a third one-channel NFET of the three one-channel NFETs and a gate stack of a third one-channel PFET of the three one-channel PFETs. The semiconductor device may further include an output of a three-input NAND logic gate connected to the lower epitaxial layer and the upper epitaxial layer and connected to the upper epitaxial layer of at least one vertical fin in the first set of one or more vertical fins; a first contact connected to the shared epitaxial layer of at least one vertical fin in the second set of one or more vertical fins and the shared epitaxial layer of another vertical fin in the second set of one or more vertical fins (e.g., connecting the shared epitaxial layer of at least one vertical fin in the second set of one or more vertical fins and the shared epitaxial layer of another vertical fin in the second set of one or more vertical fins to a high power rail); and a second contact connected to the shared epitaxial layer of another vertical fin in the first set of one or more vertical fins (e.g., connecting the shared epitaxial layer of the other vertical fin in the first set of one or more vertical fins to a low power rail).

[0179] The three-input logic gate may comprise a three-input NOR logic gate, the three NFETs may comprise three one-channel NFETs, and the three PFETs may comprise three one-channel PFETs, the three-input logic gate having a first input of the three-input NOR logic gate connected to a gate stack of a first one-channel NFET of the three one-channel NFETs and a gate stack of a first two-channel PFET of the three one-channel PFETs, a second input of the three-input NOR logic gate connected to a gate stack of a second one-channel NFET of the three one-channel NFETs and a gate stack of a second one-channel PFET of the three one-channel PFETs, a third input of the three-input NOR logic gate connected to a gate stack of a third one-channel NFET of the three one-channel NFETs and a gate stack of a third one-channel PFET of the three one-channel PFETs, and a lower portion of at least one vertical fin in the first set of one or more vertical fins via a MOL connection. The semiconductor device may further include an output of a three-input NOR logic gate connected to the epitaxial layer and the top epitaxial layer and connected to the top epitaxial layer of at least one vertical fin in the second set of one or more vertical fins; a first contact connected to a shared epitaxial layer in another vertical fin in the second set of one or more vertical fins (e.g., connecting the shared epitaxial layer in the other vertical fin in the second set of one or more vertical fins to a high power rail); and a second contact connected to the shared epitaxial layer of at least one vertical fin in the first set of one or more vertical fins and the shared epitaxial layer in another vertical fin in the first set of one or more vertical fins (e.g., connecting the shared epitaxial layer of at least one vertical fin in the first set of one or more vertical fins and the shared epitaxial layer in another vertical fin in the first set of one or more vertical fins to a low power rail).

[0180] The three-input logic gate may comprise a three-input NAND logic gate, the three NFETs may comprise three two-channel NFETs, and the three PFETs may comprise three two-channel PFETs, and the three-input logic gate may comprise a first input of the three-input NAND logic gate connected to a gate stack of a first two-channel NFET of the three two-channel NFETs and a gate stack of a first two-channel PFET of the three two-channel PFETs, a second input of the three-input NAND logic gate connected to a gate stack of a second two-channel NFET of the three two-channel NFETs and a gate stack of a second two-channel PFET of the three two-channel PFETs, and a third input of the three-input NAND logic gate connected to a gate stack of a third two-channel NFET of the three two-channel NFETs and a gate stack of a third two-channel PFET of the three two-channel PFETs. an input of a 3-input NAND logic gate connected to the lower and upper epitaxial layers of a vertical fin in the second set of one or more vertical fins via a MOL connection and connected to the upper and lower epitaxial layers of one of the vertical fins in the first set of one or more vertical fins via another MOL connection; a first contact connected to the shared epitaxial layer in the second set of one or more vertical fins (e.g., connecting the shared epitaxial layer in the second set of one or more vertical fins to a high power rail); and a second contact connected to the shared epitaxial layer of one of the vertical fins in the first set of one or more vertical fins (e.g., connecting the shared epitaxial layer of one of the vertical fins in the first set of one or more vertical fins to a low power rail).

[0181] The three-input logic gate may comprise a three-input NOR logic gate, the three NFETs may comprise three two-channel NFETs, the three PFETs may comprise three two-channel PFETs, and the three-input logic gate may comprise a first input of the three-input NOR logic gate connected to a gate stack of a first two-channel NFET of the three two-channel NFETs and a gate stack of a first two-channel PFET of the three two-channel PFETs, a second input of the three-input NOR logic gate connected to a gate stack of a second two-channel NFET of the three two-channel NFETs and a gate stack of a second two-channel PFET of the three two-channel PFETs, a third input of the three-input NOR logic gate connected to a gate stack of a third two-channel NFET of the three two-channel NFETs and a gate stack of a third two-channel PFET of the three two-channel PFETs, and The semiconductor device may further include an output of a 3-input NOR logic gate connected to the lower and upper epitaxial layers of a vertical fin in the first set of one or more vertical fins via an OL connection and connected to the upper and lower epitaxial layers of one vertical fin in the second set of one or more vertical fins via another MOL connection, a first contact connected to a shared epitaxial layer in a vertical fin of the first set of one or more vertical fins (e.g., connecting the shared epitaxial layer in a vertical fin of the first set of one or more vertical fins to a high power rail), and a second contact connected to the shared epitaxial layer of one of the vertical fins in the second set of one or more vertical fins (e.g., connecting the shared epitaxial layer of one of the vertical fins in the second set of one or more vertical fins to a low power rail).

[0182] It should be understood that the various materials, processing methods (e.g., etch types, deposition types, etc.) and dimensions provided in the above description are presented by way of example only, and various other suitable materials, processing methods and dimensions may be used, as desired.

[0183] The semiconductor devices and methods for forming semiconductor devices according to the above techniques may be employed in a variety of applications, hardware, or electronic systems or combinations thereof. Suitable hardware and systems for implementing embodiments of the present invention include, but are not limited to, sensors and sensing devices, personal computers, communication networks, electronic commerce systems, portable communication devices (e.g., mobile phones and smart phones), solid-state media storage devices, functional circuits, and the like. Systems and hardware incorporating semiconductor devices are contemplated embodiments of the present invention. Given the teachings provided herein, one skilled in the art will be able to contemplate other implementations and applications of embodiments of the present invention.

[0184] The various structures described above may be implemented in an integrated circuit. The resulting integrated circuit chips may be distributed by the manufacturer in raw wafer form (i.e., a single wafer with multiple unpackaged chips) as bare die, or in packaged form. In the latter case, the chips are mounted in a single-chip package (such as a plastic carrier with leads fixed to a motherboard, or other higher level carrier) or in a multi-chip package (such as a ceramic carrier with either surface interconnects or embedded interconnects, or both). In either case, the chips are then integrated with other chips, discrete circuit elements, or other signal processing devices, or a combination thereof, as part of either (a) an intermediate product, such as a motherboard, or (b) a final product. The final product may be any product that contains the integrated circuit chip, ranging from toys and other low performance applications to advanced computer products with displays, keyboards or other input devices, and central processing units.

[0185] The description of various embodiments of the present invention is presented for illustrative purposes and is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope of the described embodiments. The terms used in this specification are selected to best explain the principles of the embodiments, practical applications or technical improvements over the art found in the market, or to enable those skilled in the art to understand the embodiments disclosed herein.

Claims

1. 1. A semiconductor structure comprising: Two or more vertical fins; a lower epitaxial layer surrounding a lower portion of at least a first vertical fin of the two or more vertical fins; a first upper epitaxial layer surrounding an upper portion of a first vertical fin of the two or more vertical fins; a second upper epitaxial layer surrounding an upper portion of a second vertical fin of the two or more vertical fins; a first shared epitaxial layer surrounding a middle portion of the first vertical fin of the two or more vertical fins; a second shared epitaxial layer surrounding a middle portion of the second vertical fin of the two or more vertical fins; a first metal layer surrounding the first shared epitaxial layer; a second metal layer surrounding the second shared epitaxial layer; an interlevel dielectric layer between the first metal layer and the second metal layer; a connection layer contacting the lower epitaxial layer and at least one of the first upper epitaxial layer and the second upper epitaxial layer, the connection layer being disposed on a lateral side of the two or more vertical fins; 1. A semiconductor structure comprising:

2. a first region between the lower epitaxial layer and the first shared epitaxial layer of the first vertical fin of the two or more vertical fins includes a first fin channel for a four-channel vertical transport field effect transistor; a second region between the first shared epitaxial layer and the first upper epitaxial layer of the first vertical fin of the two or more vertical fins includes a second fin channel for the four-channel vertical transport field effect transistor; the first shared epitaxial layer includes a shared source region for the first fin channel and the second fin channel of the four-channel vertical transport field effect transistor; 2. The semiconductor structure of claim 1 , wherein said lower epitaxial layer and said first upper epitaxial layer comprise a drain region for said first fin channel and a drain region for said second fin channel of said four-channel vertical transport field effect transistor.

3. A semiconductor structure comprising: Two or more vertical fins; a lower epitaxial layer surrounding a lower portion of a given vertical fin of the two or more vertical fins; an upper epitaxial layer surrounding an upper portion of the given vertical fin of the two or more vertical fins; a shared epitaxial layer surrounding a middle portion of the given vertical fin of the two or more vertical fins; a connection layer in contact with the lower epitaxial layer and the upper epitaxial layer, the connection layer being disposed on a lateral side of the two or more vertical fins; Equipped with a first region between the lower epitaxial layer and the shared epitaxial layer of the given vertical fin of the two or more vertical fins includes a first fin channel for a four-channel vertical transport field effect transistor; a second region between the shared epitaxial layer and the top epitaxial layer of the given vertical fin of the two or more vertical fins includes a second fin channel for the four-channel vertical transport field effect transistor; the shared epitaxial layer includes a shared source region for the first fin channel and the second fin channel of the four-channel vertical transport field effect transistor; the lower epitaxial layer and the upper epitaxial layer include a drain region for the first fin channel and a drain region for the second fin channel of the four-channel vertical transport field effect transistor; A semiconductor structure, wherein the connecting layer connects the drain region for the first fin channel and the drain region for the second fin channel to an output of an inverter logic gate.

4. a first region between the lower epitaxial layer and the first shared epitaxial layer of the first vertical fin of the two or more vertical fins includes a first fin channel for a two-channel vertical transport field effect transistor; a second region between the first shared epitaxial layer and the first upper epitaxial layer of the first vertical fin of the two or more vertical fins includes a second fin channel for the two-channel vertical transport field effect transistor; the first shared epitaxial layer includes a shared source region for the first fin channel and the second fin channel of the two-channel vertical transport field effect transistor; 2. The semiconductor structure of claim 1 , wherein said lower epitaxial layer and said first upper epitaxial layer comprise a drain region for said first fin channel and a drain region for said second fin channel of said two-channel vertical transport field effect transistor.

5. 5. The semiconductor structure of claim 4 wherein said two-channel vertical transport field effect transistor comprises a p-type field effect transistor, and said connecting layer connects said drain region for said first fin channel and said drain region for said second fin channel to an output of a two-input NAND logic gate.

6. 5. The semiconductor structure of claim 4 wherein said two-channel vertical transport field effect transistor comprises an n-type field effect transistor, and said connecting layer connects said drain region for said first fin channel and said drain region for said second fin channel to an output of a two-input NOR logic gate.

7. a first region between the lower epitaxial layer and the first shared epitaxial layer of the first vertical fin of the two or more vertical fins includes a fin channel for a first one-channel vertical transport field effect transistor; a second region between the first shared epitaxial layer and the first upper epitaxial layer of the first vertical fin of the two or more vertical fins includes a fin channel for a second one-channel vertical transport field effect transistor; the first shared epitaxial layer includes a shared source region for the first one-channel vertical transport field effect transistor and the second one-channel vertical transport field effect transistor; the lower epitaxial layer includes a drain region of the first one-channel vertical transport field effect transistor; 2. The semiconductor structure of claim 1 wherein said first upper epitaxial layer comprises a drain region for said second one-channel vertical transport field effect transistor.

8. 8. The semiconductor structure of claim 7, wherein said first one-channel vertical transport field effect transistor and said second one-channel vertical transport field effect transistor comprise p-type field effect transistors, and said connecting layer connects said drain region of said first one-channel vertical transport field effect transistor and said drain region of said second one-channel vertical transport field effect transistor to an output of a three-input NAND logic gate.

9. 8. The semiconductor structure of claim 7, wherein said first one-channel vertical transport field effect transistor and said second one-channel vertical transport field effect transistor comprise n-type field effect transistors, and said connecting layer connects said drain region of said first one-channel vertical transport field effect transistor and said drain region of said second one-channel vertical transport field effect transistor to an output of a three-input NOR logic gate.

10. a first region between the lower epitaxial layer and the first shared epitaxial layer of the first vertical fin of the two or more vertical fins includes a first fin channel for a two-channel vertical transport field effect transistor; a second region between the first shared epitaxial layer and the first upper epitaxial layer of the first vertical fin of the two or more vertical fins includes a second fin channel for the two-channel vertical transport field effect transistor; the first shared epitaxial layer includes a shared source region for the two-channel vertical transport field effect transistor; 2. The semiconductor structure of claim 1 wherein said lower epitaxial layer and said first upper epitaxial layer comprise a drain region of said two-channel vertical transport field effect transistor.

11. 11. The semiconductor structure of claim 10 wherein said two-channel vertical transport field effect transistor comprises a p-type field effect transistor, and said connecting layer connects said drain region of said two-channel vertical transport field effect transistor to an output of a three-input NAND logic gate.

12. 11. The semiconductor structure of claim 10 wherein said two-channel vertical transport field effect transistor comprises an n-type field effect transistor, and said connecting layer connects said drain region of said two-channel vertical transport field effect transistor to an output of a three-input NOR logic gate.

13. 1. A method of forming a semiconductor structure, comprising: forming two or more vertical fins; forming a lower epitaxial layer surrounding a lower portion of at least a first vertical fin of the two or more vertical fins; forming a first upper epitaxial layer surrounding an upper portion of a first vertical fin of the two or more vertical fins; forming a second upper epitaxial layer surrounding an upper portion of a second vertical fin of the two or more vertical fins; forming a first shared epitaxial layer surrounding a middle portion of the first vertical fin of the two or more vertical fins; forming a second shared epitaxial layer surrounding a middle portion of the second vertical fin of the two or more vertical fins; forming a first metal layer surrounding the first shared epitaxial layer; forming a second metal layer surrounding the second shared epitaxial layer; forming an interlevel dielectric layer between the first metal layer and the second metal layer; forming a connection layer contacting the lower epitaxial layer and at least one of the first upper epitaxial layer and the second upper epitaxial layer, the connection layer being disposed on a lateral side of the two or more vertical fins; A method comprising:

14. 14. The method of claim 13, wherein the lower epitaxial layer, the first upper epitaxial layer and the second upper epitaxial layer comprise a drain region of at least one vertical transport field effect transistor of a logic gate.

15. The method of claim 14 , wherein the connecting layer connects the drain region of the at least one vertical transport field effect transistor to an output of the logic gate.

16. 1. An inverter logic gate, comprising: a four-channel n-type field effect transistor, the four-channel n-type field effect transistor comprising two vertical fins, each of the two vertical fins comprising a lower epitaxial layer surrounding a lower portion of the two vertical fins, an upper epitaxial layer surrounding an upper portion of the two vertical fins, and a shared epitaxial layer surrounding a middle portion of the two vertical fins; a four-channel p-type field effect transistor, the four-channel p-type field effect transistor comprising two vertical fins, each of the two vertical fins comprising a lower epitaxial layer surrounding a lower portion of the two vertical fins, an upper epitaxial layer surrounding an upper portion of the two vertical fins, and a shared epitaxial layer surrounding a middle portion of the two vertical fins; an inverter logic gate comprising: said four-channel n-type field effect transistor; and a connection layer contacting said lower epitaxial layer and said upper epitaxial layer of said four-channel p-type field effect transistor.

17. an input of the inverter logic gate connected to a gate stack of the four-channel n-type field effect transistor and the four-channel p-type field effect transistor surrounding a portion of the two vertical fins between the lower epitaxial layer and the shared epitaxial layer and a portion of the two vertical fins between the shared epitaxial layer and the upper epitaxial layer; an output of the inverter logic gate connected to the lower epitaxial layer and the upper epitaxial layer of the four-channel n-type field effect transistor and the four-channel p-type field effect transistor; a first contact connected to a shared epitaxial layer of the four-channel p-type field effect transistor; a second contact connected to the shared epitaxial layer of the four-channel n-type field effect transistor; 20. The inverter logic gate of claim 16 further comprising:

18. A two-input logic gate, two two-channel n-type field effect transistors, the two two-channel n-type field effect transistors comprising two vertical fins, each of the two vertical fins comprising a lower epitaxial layer surrounding a lower portion of the two vertical fins, an upper epitaxial layer surrounding an upper portion of the two vertical fins, and a shared epitaxial layer surrounding a middle portion of the two vertical fins, a metal layer surrounding the shared epitaxial layer, and an interlayer dielectric layer between the metal layers; two two-channel p-type field effect transistors each having two vertical fins, each of the two vertical fins comprising a lower epitaxial layer surrounding a lower portion of the two vertical fins, an upper epitaxial layer surrounding an upper portion of the two vertical fins, and a shared epitaxial layer surrounding a middle portion of the two vertical fins, a metal layer surrounding the shared epitaxial layer, and an interlayer dielectric layer between the metal layers; (i) the two two-channel n-type field effect transistors; and (ii) a connection layer contacting the lower epitaxial layer and the upper epitaxial layer of one of the two two-channel p-type field effect transistors. A two-input logic gate comprising:

19. the two-input logic gate comprises a two-input NAND logic gate; a first input of the two-input NAND logic gate connected to a gate stack of a first two-channel n-type field effect transistor of the two two-channel n-type field effect transistors and a gate stack of a first two-channel p-type field effect transistor of the two two-channel p-type field effect transistors; a second input of the two-input NAND logic gate connected to a gate stack of a second two-channel n-type field effect transistor of the two two-channel n-type field effect transistors and a gate stack of a second two-channel p-type field effect transistor of the two two-channel p-type field effect transistors; an output of the two-input NAND logic gate connected to the lower epitaxial layer and the upper epitaxial layer of the two two-channel p-type field effect transistors through the connection layer and connected to a lower epitaxial layer of the two vertical fins of a first two-channel n-type field effect transistor of the two two-channel n-type field effect transistors; a first contact connected to a shared epitaxial layer of the two dual-channel p-type field effect transistors; a second two-channel n-type field effect transistor connected to the upper epitaxial layer of the two vertical fins of a second two-channel n-type field effect transistor of the two two-channel n-type field effect transistors; Contact area and 20. The two-input logic gate of claim 18 further comprising:

20. the two-input logic gate comprises a two-input NOR logic gate; a first input of the two-input NOR logic gate connected to a gate stack of a first two-channel n-type field effect transistor of the two two-channel n-type field effect transistors and a gate stack of a first two-channel p-type field effect transistor of the two two-channel p-type field effect transistors; a second input of the two-input NOR logic gate connected to a gate stack of a second two-channel n-type field effect transistor of the two two-channel n-type field effect transistors and a gate stack of a second two-channel p-type field effect transistor of the two two-channel p-type field effect transistors; an output of the two-input NOR logic gate connected to the lower epitaxial layer and the upper epitaxial layer of the two two-channel n-type field effect transistors through the connection layer and connected to a first shared epitaxial layer of the shared epitaxial layers of a first vertical fin of the two vertical fins of a first two-channel p-type field effect transistor of the two two-channel p-type field effect transistors; a first contact connected to a second shared epitaxial layer of the shared epitaxial layers of a second vertical fin of the two vertical fins of a second two-channel p-type field effect transistor of the two two-channel p-type field effect transistors; a second contact connected to the shared epitaxial layer of the two vertical fins of the two dual-channel n-type field effect transistors; 20. The two-input logic gate of claim 18 further comprising:

21. 1. A three-input logic gate comprising: three n-type field effect transistors, the three n-type field effect transistors comprising a first set of vertical fins, the first set of vertical fins comprising a lower epitaxial layer surrounding a lower portion of at least one vertical fin in the first set of vertical fins, an upper epitaxial layer surrounding an upper portion of the first set of vertical fins, a shared epitaxial layer surrounding a middle portion of the first set of vertical fins, a metal layer surrounding the shared epitaxial layer of the first set of vertical fins, and an interlayer dielectric layer between the metal layers; three p-type field effect transistors, the three p-type field effect transistors comprising a second set of vertical fins, the second set of vertical fins comprising a lower epitaxial layer surrounding a lower portion of at least one vertical fin in the second set of vertical fins, an upper epitaxial layer surrounding an upper portion of the second set of vertical fins, a shared epitaxial layer surrounding a middle portion of the second set of vertical fins, a metal layer surrounding the shared epitaxial layer of the second set of vertical fins, and an interlayer dielectric layer between the metal layers; a connection layer contacting the lower epitaxial layer and the upper epitaxial layer of one of the at least one vertical fin in one of the first set of multiple vertical fins and the second set of multiple vertical fins; 1. A three-input logic gate comprising:

22. the three-input logic gate comprises a three-input NAND logic gate, the three n-type field effect transistors comprise three one-channel n-type field effect transistors, the three p-type field effect transistors comprise three one-channel p-type field effect transistors, and the three-input logic gate comprises: a first input of the three-input NAND logic gate connected to a gate stack of a first one-channel n-type field effect transistor of the three one-channel n-type field effect transistors and a gate stack of a first one-channel p-type field effect transistor of the three one-channel p-type field effect transistors; a second input of the three-input NAND logic gate connected to a gate stack of a second one-channel n-type field effect transistor of the three one-channel n-type field effect transistors and a gate stack of a second one-channel p-type field effect transistor of the three one-channel p-type field effect transistors; a third input of the three-input NAND logic gate connected to a gate stack of a third one-channel n-type field effect transistor of the three one-channel n-type field effect transistors and to a gate stack of a third one-channel p-type field effect transistor of the three one-channel p-type field effect transistors; an output of the three-input NAND logic gate connected to the lower epitaxial layer and the upper epitaxial layer of the at least one vertical fin in the second set of multiple vertical fins through the connecting layer and connected to the upper epitaxial layer of the at least one vertical fin in the first set of multiple vertical fins; a first contact connected to the shared epitaxial layer of at least one vertical fin in the second set of multiple vertical fins and to a shared epitaxial layer of another vertical fin in the second set of multiple vertical fins; a second contact connected to a shared epitaxial layer in another vertical fin in the first set of multiple vertical fins; and 22. The three-input logic gate of claim 21 further comprising:

23. the three-input logic gate comprises a three-input NOR logic gate, the three n-type field effect transistors comprise three one-channel n-type field effect transistors, the three p-type field effect transistors comprise three one-channel p-type field effect transistors, and the three-input logic gate comprises: a first input of the three-input NOR logic gate connected to a gate stack of a first one-channel n-type field effect transistor of the three one-channel n-type field effect transistors and a gate stack of a first one-channel p-type field effect transistor of the three one-channel p-type field effect transistors; a second input of the three-input NOR logic gate connected to a gate stack of a second one-channel n-type field effect transistor of the three one-channel n-type field effect transistors and to a gate stack of a second one-channel p-type field effect transistor of the three one-channel p-type field effect transistors; a third input of the three-input NOR logic gate connected to a gate stack of a third one-channel n-type field effect transistor of the three one-channel n-type field effect transistors and to a gate stack of a third one-channel p-type field effect transistor of the three one-channel p-type field effect transistors; an output of the three-input NOR logic gate connected to the lower epitaxial layer and the upper epitaxial layer of the at least one vertical fin in the first set of multiple vertical fins through the connecting layer and connected to the upper epitaxial layer of the at least one vertical fin in the second set of multiple vertical fins; a first contact connected to a shared epitaxial layer in another vertical fin in the second set of multiple vertical fins; a second contact connected to the shared epitaxial layer of at least one vertical fin in the first set of multiple vertical fins and to a shared epitaxial layer of another vertical fin in the first set of multiple vertical fins; 22. The three-input logic gate of claim 21 further comprising:

24. the three-input logic gate comprises a three-input NAND logic gate, the three n-type field effect transistors comprise three two-channel n-type field effect transistors, the three p-type field effect transistors comprise three two-channel p-type field effect transistors, and the three-input logic gate comprises: a first input of the three-input NAND logic gate connected to a gate stack of a first two-channel n-type field effect transistor of the three two-channel n-type field effect transistors and a gate stack of a first two-channel p-type field effect transistor of the three two-channel p-type field effect transistors; a second input of the three-input NAND logic gate connected to a gate stack of a second two-channel n-type field effect transistor of the three two-channel n-type field effect transistors and a gate stack of a second two-channel p-type field effect transistor of the three two-channel p-type field effect transistors; a third input of the three-input NAND logic gate connected to a gate stack of a third two-channel n-type field effect transistor of the three two-channel n-type field effect transistors and to a gate stack of a third two-channel p-type field effect transistor of the three two-channel p-type field effect transistors; an output of the three-input NAND logic gate connected to a lower epitaxial layer and an upper epitaxial layer of a vertical fin in the second set of vertical fins through the connection layer and connected to the upper epitaxial layer and the lower epitaxial layer of one of the vertical fins in the first set of vertical fins through another connection layer; a first contact connected to the shared epitaxial layer of the second set of vertical fins; a second contact connected to the shared epitaxial layer of one of the vertical fins in the first set of vertical fins; 22. The three-input logic gate of claim 21 further comprising:

25. the three-input logic gate comprises a three-input NOR logic gate, the three n-type field effect transistors comprise three two-channel n-type field effect transistors, the three p-type field effect transistors comprise three two-channel p-type field effect transistors, and the three-input logic gate comprises: a first input of the three-input NOR logic gate connected to a gate stack of a first two-channel n-type field effect transistor of the three two-channel n-type field effect transistors and a gate stack of a first two-channel p-type field effect transistor of the three two-channel p-type field effect transistors; a second input of the three-input NOR logic gate connected to a gate stack of a second two-channel n-type field effect transistor of the three two-channel n-type field effect transistors and a gate stack of a second two-channel p-type field effect transistor of the three two-channel p-type field effect transistors; a third input of the three-input NOR logic gate connected to a gate stack of a third two-channel n-type field effect transistor of the three two-channel n-type field effect transistors and to a gate stack of a third two-channel p-type field effect transistor of the three two-channel p-type field effect transistors; an output of the three-input NOR logic gate connected to a lower epitaxial layer and an upper epitaxial layer of a vertical fin in the first set of vertical fins through the connection layer and connected to the upper epitaxial layer and the lower epitaxial layer of a vertical fin in the second set of vertical fins through another connection layer; a first contact connected to a shared epitaxial layer in the vertical fins of the first set of vertical fins; a second contact connected to the shared epitaxial layer of one of the vertical fins in the second set of vertical fins; 22. The three-input logic gate of claim 21 further comprising:

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