Imaging device and electronic device

Abstract

[Problem] To provide an imaging device capable of operating at higher speed and with lower power consumption with respect to a column signal processing system that includes a successive approximation analog-digital converter. [Solution] This imaging device is provided with: a pixel array unit formed by arranging pixels that include photoelectric conversion elements; a column amp unit for acquiring a difference between a reset component and a signal component inputted through a signal line from each pixel of the pixel array unit, and outputting the difference as a pixel signal; a capacitance unit for holding the pixel signal inputted from the column amp unit; and a successive approximation analog-digital conversion unit for converting the analog signal inputted from the capacitance unit into a digital signal.

Description

[Technical field]

[0001] The present disclosure relates to an imaging device and an electronic device. [Background technology]

[0002] The imaging device is equipped with an analog-to-digital converter that converts an analog signal (pixel signal) output from a pixel into a digital signal, and a successive approximation resistor (SAR) type analog-to-digital converter is used as the analog-to-digital converter (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2019-092143 A Summary of the Invention [Problem to be solved by the invention]

[0004] Successive approximation type analog-digital converters are superior to so-called single-slope type analog-digital converters in that they can operate at high speeds and with low power consumption. For column signal processing systems that include successive approximation type analog-digital converters, operation at higher speeds and with lower power consumption is desirable.

[0005] In view of the above, an object of the present disclosure is to provide an imaging device capable of operating at higher speed and with lower power consumption in a column signal processing system including a successive approximation type analog-to-digital converter, and an electronic device having the imaging device. [Means for solving the problem]

[0006] *** Claim-01 In order to achieve the above object, the imaging device of the present disclosure comprises: a pixel array section in which pixels each including a photoelectric conversion element are arranged; a column amplifier section that calculates a difference between a reset component and a signal component input from each pixel of the pixel array section through a signal line, and outputs the difference as a pixel signal; A capacitance unit that holds a pixel signal input from the column amplifier unit; and a successive approximation type analog-to-digital conversion unit that converts an analog signal input from the capacitance unit into a digital signal; Equipped with.

[0007] *** Claim-12 In order to achieve the above object, an electronic device according to the present disclosure includes an imaging device having the above configuration. [Brief description of the drawings]

[0008] [Figure 1] FIG. 1 is a block diagram showing an outline of the basic configuration of a CMOS image sensor, which is an example of an imaging device to which the technology according to the present disclosure is applied. [Diagram 2] FIG. 2 is a circuit diagram showing an example of a circuit configuration of a pixel. [Diagram 3] FIG. 3 is a plan view that diagrammatically illustrates an outline of a flat-type semiconductor chip structure of a CMOS image sensor. [Figure 4] FIG. 4 is an exploded perspective view showing a schematic outline of a stacked semiconductor chip structure of a CMOS image sensor. [Diagram 5] FIG. 5 is a block diagram showing an outline of the configuration of a CMOS image sensor which is an example of an imaging device according to the first embodiment of the present disclosure. [Figure 6] FIG. 6 is a circuit diagram showing an outline of the configuration of a column signal processing system according to the first embodiment. [Figure 7] FIG. 7 is a timing chart illustrating the circuit operation of the column signal processing system according to the first embodiment. [Figure 8] FIG. 8 is a circuit diagram showing an outline of the configuration of a column signal processing system according to the second embodiment. [Figure 9]FIG. 9 is a circuit diagram showing an outline of the configuration of a column signal processing system according to the third embodiment. [Figure 10] FIG. 10 is a timing chart illustrating the circuit operation of the column signal processing system according to the third embodiment. [Figure 11] FIG. 11 is a circuit diagram showing an outline of the configuration of a column signal processing system according to the fourth embodiment. [Figure 12] FIG. 12 is a diagram for explaining a level diagram. [Figure 13] FIG. 13 is a circuit diagram showing an example of the configuration of a current reuse column amplifier. [Figure 14] FIG. 14 is a detailed circuit diagram of a successive approximation type analog-to-digital converter. [Figure 15] FIG. 15 is a block diagram showing an example of a system configuration of an indirect TOF range image sensor according to the second embodiment of the present disclosure. [Figure 16] FIG. 16 is a circuit diagram showing an example of a circuit configuration of a pixel in the indirect TOF range image sensor according to the second embodiment. [Figure 17] FIG. 17 is a diagram illustrating an application example of the technology according to the present disclosure. [Figure 18] FIG. 18 is a block diagram showing an outline of an example configuration of an imaging system that is an example of an electronic device according to the present disclosure. [Figure 19] FIG. 19 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a moving object control system to which the technology according to the present disclosure can be applied. [Figure 20] FIG. 20 is a diagram showing an example of the installation position of the imaging unit in the mobile object control system. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] Hereinafter, a form for carrying out the technology according to the present disclosure (hereinafter, referred to as "embodiment") will be described in detail with reference to the drawings. The technology according to the present disclosure is not limited to the embodiment, and various numerical values ​​in the embodiment are merely examples. In the following description, the same reference numerals will be used for the same elements or elements having the same functions, and duplicated description will be omitted. The description will be given in the following order. 1. General Description of the Imaging Device and Electronic Device of the Present Disclosure 2. Imaging device to which the technology disclosed herein is applied 2-1.Example of CMOS image sensor configuration 2-2. Example of pixel circuit configuration 2-3.Semiconductor chip structure 2-3-1.Flat-type semiconductor chip structure 2-3-2.Stacked semiconductor chip structure 2-4. Single-slope analog-to-digital converter 3. First embodiment of the present disclosure (example of CMOS image sensor) 3-1. First embodiment (an example of intermittent operation in which a successive approximation type analog-digital converter performs conversion processing only during the P phase and waits during the D phase) 3-1-1. Column amplifier configuration example 3-1-2. Example of capacitance multiplexer configuration 3-1-3. Example of a successive approximation type analog-to-digital converter 3-1-4. Column signal processing circuit operation 3-2. Second embodiment (modification of the first embodiment: an example of non-intermittent operation in which the successive approximation type analog-digital converter performs conversion processing not only during the P phase but also during the D phase) 3-3. Third embodiment (modification of the second embodiment: an example in which three capacitance elements are used equally for the potential VSL of two signal lines) 3-3-1. Column signal processing system configuration example 3-3-2. Column signal processing circuit operation 3-4. Fourth embodiment (example of differential circuit configuration after the capacitive multiplexer) 3-4-1. Power supply voltage and transistors used 3-4-2.About the level diagram 3-4-3. Column amplifier configuration example 3-4-4. Example of a successive approximation type analog-to-digital converter 4. Second embodiment of the present disclosure (example of indirect TOF range image sensor) 4-1. System configuration example 4-2. Example of pixel circuit configuration 5. Variations 6. Application Examples 7. Application Examples of the Technology Disclosed Herein 7-1. Electronic Device of the Present Disclosure (Example of Imaging Device) 7-2. Application examples for mobile devices 8. Configurations that the present disclosure can take

[0010] *** Claim-02 <General Description of Imaging Device and Electronic Device of the Present Disclosure> In the imaging device and electronic device disclosed herein, the column amplifier section may be configured to include an amplifier having a non-inverting input terminal to which the potential of the signal line is input, a first switch having one end connected to the output terminal of the amplifier and the other end connected to the inverting input terminal of the amplifier, a second switch having one end connected to the output terminal of the amplifier, a first capacitive element having one end connected to the other end of the second switch and the other end connected to the other end of the first switch and the inverting input terminal of the amplifier, a second capacitive element connected between the other end of the first capacitive element and the inverting input terminal of the amplifier and a reference potential node, and a third switch having one end connected to the other end of the second switch and one end of the first capacitive element and having a reference voltage applied to its other end.

[0011] *** Claim-03 In the imaging device and electronic device of the present disclosure including the preferred configuration described above, in the column amplifier section, when a reset component is input, the first switch is closed to charge the reset component to the first capacitive element and the second capacitive element, and the third switch is closed to capture a local reference voltage, and then the first switch and the third switch are opened and the second switch is closed to form a non-inverting amplifier circuit by the first capacitive element, the second capacitive element and the amplifier, and feedback is applied so that when a signal component is input, the voltage of the common connection node of the first capacitive element and the second capacitive element becomes the same voltage as the signal component.

[0012] *** Claim-04, Claim-05, Claim-06 In addition, in the imaging device and electronic device of the present disclosure including the above-mentioned preferred configuration, for one successive approximation type analog-digital converter of the successive approximation type analog-digital conversion section, the potentials of the multiple signal lines can be multiplexed and processed through multiple column amplifiers and capacitance sections corresponding to the multiple signal lines. Furthermore, the successive approximation type analog-digital converter can be configured to perform conversion processing only when a reset component is input and to wait when a signal component is input, or to perform conversion processing not only when a reset component is input but also when a signal component is input.

[0013] *** Claim-07 In addition, in the imaging device and electronic device disclosed herein including the above-mentioned preferred configuration, the potentials of the multiple signal lines can be divided into two systems of signal lines, and the capacitance section can have three capacitance elements. The three capacitance elements of the capacitance section can be evenly used for the potentials of the two systems of signal lines.

[0014] *** Claim-08, Claim-09 In the imaging device and electronic device of the present disclosure including the above-mentioned preferred configuration, in a column signal processing system including a column amplifier section, a capacitance section, and a successive approximation type analog-digital conversion section, the capacitance section and subsequent sections can be configured as differential circuits. Also, the column amplifier of the column amplifier section can be configured as a current reuse column amplifier that performs voltage amplification by utilizing a bias current of a signal line.

[0015] *** Claim-10, Claim-11 In the imaging device and electronic device according to the present disclosure including the above-described preferred configuration, the capacitance unit may be configured to include a capacitance multiplexer, and the capacitance unit may be configured to hold pixel signals by sampling using a switched capacitor.

[0016] <Imaging device to which the technology according to the present disclosure is applied> First, the basic configuration of an imaging device to which the technology according to the present disclosure is applied will be described. Here, a CMOS (Complementary Metal Oxide Semiconductor) image sensor, which is a type of XY address type imaging device, will be taken as an example of the imaging device. A CMOS image sensor is an image sensor that is manufactured by applying or partially using a CMOS process.

[0017] [Example of CMOS image sensor configuration] FIG. 1 is a block diagram showing an outline of the basic configuration of a CMOS image sensor, which is an example of an imaging device to which the technology according to the present disclosure is applied.

[0018] The CMOS image sensor 10 according to this example has a configuration including a pixel array section 11 and a peripheral circuit section of the pixel array section 11. The pixel array section 11 is configured by pixels (pixel circuits) 20 including photoelectric conversion elements being arranged two-dimensionally in row and column directions, that is, in a matrix. Here, the row direction refers to the arrangement direction of the pixels 20 in a pixel row, and the column direction refers to the arrangement direction of the pixels 20 in a pixel column. The pixels 20 generate and accumulate photoelectric charges according to the amount of light received by performing photoelectric conversion.

[0019] The peripheral circuit section of the pixel array section 11 is composed of, for example, a row selection section 12, a constant current source section 13, a column amplifier section 14, an analog-to-digital conversion section 15, a horizontal transfer scanning section 16, a signal processing section 17, and a timing control section 18.

[0020] In the pixel array section 11, pixel control lines 31 (311 to 31 m ) are wired in the row direction. Also, signal lines 32 (321 to 322) are wired for each pixel column. n ) are wired in the column direction. The pixel control line 31 transmits a drive signal for driving the pixel 20 when reading out a signal. In FIG. 1, the pixel control line 31 is illustrated as a single wire, but the number of wires is not limited to one. One end of the pixel control line 31 is connected to an output terminal of the row selection section 12 corresponding to each row.

[0021] Below, we will explain each component of the peripheral circuit section of the pixel array section 11, namely, the row selection section 12, the constant current source section 13, the column amplifier section 14, the analog-to-digital conversion section 15, the horizontal transfer scanning section 16, the signal processing section 17, and the timing control section 18.

[0022] The row selection unit 12 is composed of a shift register, an address decoder, etc., and controls scanning of pixel rows and addresses of pixel rows when selecting each pixel 20 in the pixel array unit 11. Although the specific configuration of the row selection unit 12 is not shown in the figure, the row selection unit 12 is generally configured to have two scanning systems, a read scanning system and a sweep scanning system.

[0023] The readout scanning system sequentially selects and scans the pixels 20 in the pixel array unit 11 row by row to read out pixel signals from the pixels 20. The pixel signals read out from the pixels 20 are analog signals. The sweep scanning system performs sweep scanning on the readout row to be read out scanned by the readout scanning system, prior to the readout scanning by the shutter speed.

[0024] The sweep-out scanning by this sweep-out scanning system sweeps out unnecessary charges from the photoelectric conversion elements of the pixels 20 in the readout row, thereby resetting the photoelectric conversion elements. Then, by sweeping out (resetting) the unnecessary charges by this sweep-out scanning system, a so-called electronic shutter operation is performed. Here, the electronic shutter operation refers to the operation of discarding the photoelectric charge in the photoelectric conversion element and starting a new exposure (starting the accumulation of photoelectric charge).

[0025] The constant current source unit 13 connects the signal lines 321 to 322 for each pixel column. n 2, each of which is connected to a load current source I, e.g., a MOS transistor. n A bias current is provided through each of the

[0026] The column amplifier unit 14 has signal lines 321 to 32 n Each column amplifier of the column amplifier section 14 is provided corresponding to each pixel 20 of the pixel array section 11. n The pixel signal supplied through the amplifier 14 is amplified and supplied to the analog-to-digital converter 15 .

[0027] The analog-digital conversion unit 15 is a column-parallel type analog-digital conversion unit that is made up of a set of multiple analog-digital converters that are provided corresponding to the pixel columns of the pixel array unit 11 (for example, provided for each pixel column). The analog-digital conversion unit 15 is connected to signal lines 321 to 32 for each pixel column. nThe analog pixel signals are output through the column amplifier 14 and amplified by the column amplifier unit 14, and converted into digital pixel signals.

[0028] The horizontal transfer scanning unit 16 is composed of a shift register, an address decoder, etc., and controls the scanning of pixel columns and the addresses of pixel columns when reading out signals from each pixel 20 in the pixel array unit 11. Under the control of this horizontal transfer scanning unit 16, the pixel signals converted into digital signals by the analog-to-digital conversion unit 15 are read out to the horizontal transfer line L on a pixel column basis.

[0029] The signal processing unit 17 performs predetermined signal processing on the digital pixel signals supplied through the horizontal transfer line L to generate two-dimensional image data. For example, the signal processing unit 17 performs digital signal processing such as correction of vertical line defects and point defects, parallel-serial conversion, compression, encoding, addition, averaging, and intermittent operation. The signal processing unit 17 outputs the generated image data to a downstream device as an output signal of the CMOS image sensor 10.

[0030] The timing control unit 18 generates various timing signals, clock signals, control signals, etc., and based on these generated signals, controls the driving of the row selection unit 12, the constant current source unit 13, the column amplifier unit 14, the analog-to-digital conversion unit 15, the horizontal transfer scanning unit 16, and the signal processing unit 17, etc.

[0031] [Pixel circuit configuration example] 2 is a circuit diagram showing an example of the configuration of a pixel (pixel circuit) 20. The pixel 20 has, for example, a photodiode 21 as a photoelectric conversion element. In addition to the photodiode 21, the pixel 20 has a transfer transistor 22, a reset transistor 23, an amplification transistor 24, and a selection transistor 25.

[0032] For example, N-channel MOS type field effect transistors (FETs) are used as the four transistors, namely the transfer transistor 22, the reset transistor 23, the amplification transistor 24, and the selection transistor 25. However, the combinations of the conductivity types of the four transistors 22 to 25 illustrated here are merely examples, and are not limited to these combinations.

[0033] For these pixels 20, a plurality of pixel control lines are commonly wired to each pixel 20 in the same pixel row as the above-mentioned pixel control line 31. These pixel control lines are connected on a pixel row basis to output terminals of the row selection unit 12 corresponding to each pixel row. The row selection unit 12 appropriately outputs a transfer signal TRG, a reset signal RST, and a selection signal SEL to the plurality of pixel control lines.

[0034] The photodiode 21 has an anode electrode connected to a low potential power supply (for example, ground), and photoelectrically converts received light into photocharges (here, photoelectrons) with an amount of charge corresponding to the amount of light, and accumulates the photocharges. The cathode electrode of the photodiode 21 is electrically connected to the gate of the amplification transistor 24 via the transfer transistor 22. Here, the region electrically connected to the gate of the amplification transistor 24 is a floating diffusion (floating diffusion region / impurity diffusion region) FD. The floating diffusion FD is a charge-voltage converter that converts charge into voltage.

[0035] A high level (e.g., V DD A transfer signal TRG in which a signal level (signal level) becomes active is provided from the row selection unit 12. The transfer transistor 22 becomes conductive in response to the transfer signal TRG, and transfers the photoelectric charge that is photoelectrically converted by the photodiode 21 and accumulated in the photodiode 21 to the floating diffusion FD.

[0036] The reset transistor 23 is connected to the high-potential power supply voltage V DDA reset signal RST, which is active at a high level, is provided to the gate of the reset transistor 23 from the row selection unit 12. In response to the reset signal RST, the reset transistor 23 becomes conductive and transfers the charge of the floating diffusion FD to a voltage V DD Reset the floating diffusion FD by dumping it into the node.

[0037] The amplifier transistor 24 has a gate connected to the floating diffusion FD and a drain connected to the high-potential power supply voltage V DD The amplification transistor 24 serves as an input section of a source follower that reads out a signal obtained by photoelectric conversion in the photodiode 21. That is, the source of the amplification transistor 24 is connected to a signal line 32 via a selection transistor 25. The amplification transistor 24 and a load current source I connected to one end of the signal line 32 constitute a source follower that converts the voltage of the floating diffusion FD into the potential of the signal line 32.

[0038] The selection transistor 25 has a drain connected to the source of the amplification transistor 24 and a source connected to a signal line 32. A selection signal SEL that becomes active at a high level is provided to the gate of the selection transistor 25 from the row selection unit 12. The selection transistor 25 becomes conductive in response to the selection signal SEL, thereby placing the pixel 20 in a selected state and transmitting a signal output from the amplification transistor 24 to the signal line 32.

[0039] In the above circuit example, the circuit configuration of the pixel 20 is a 4Tr configuration consisting of four transistors (Tr), that is, the transfer transistor 22, the reset transistor 23, the amplification transistor 24, and the selection transistor 25, but the present invention is not limited to this. For example, the selection transistor 25 can be omitted and a 3Tr configuration can be used in which the amplification transistor 24 has the function of the selection transistor 25, or a circuit configuration of 5Tr or more can be used by increasing the number of transistors as necessary.

[0040] [Semiconductor chip structure] Examples of the semiconductor chip structure of the CMOS image sensor 10 having the above-mentioned configuration include a flat-type semiconductor chip structure and a stacked-type semiconductor chip structure. In both the flat-type and stacked-type CMOS image sensors 10, when the substrate surface on which the wiring layer is arranged is defined as the front surface (front), the pixel 20 can have a back-illuminated pixel structure that captures light irradiated from the back surface side on the opposite side, or a front-illuminated pixel structure that captures light irradiated from the front surface side. The flat-type semiconductor chip structure and stacked-type semiconductor chip structure will be described below.

[0041] (Flat-type semiconductor chip structure) Fig. 3 is a plan view showing a schematic outline of a flat-type semiconductor chip structure of a CMOS image sensor 10. As shown in Fig. 3, the flat-type semiconductor chip structure is a structure in which a peripheral circuit portion of a pixel array section 11 is formed on the same semiconductor chip (semiconductor substrate) 41 as the pixel array section 11, in which pixels 20 are arranged in a matrix. Specifically, a row selection section 12, a constant current source section 13, a column amplifier section 14, an analog-digital conversion section 15, a horizontal transfer scanning section 16, a signal processing section 17, a timing control section 18, and the like are formed on the same semiconductor chip 41 as the pixel array section 11.

[0042] (Stacked semiconductor chip structure) FIG. 4 is an exploded perspective view showing a schematic outline of the stacked chip structure of the CMOS image sensor 10. As shown in FIG. 4, the stacked semiconductor chip structure is a structure in which at least two semiconductor chips (semiconductor substrates), a first-layer semiconductor chip 42 and a second-layer semiconductor chip 43, are stacked. In this stacked structure, the pixel array section 11 is formed in the first-layer semiconductor chip 42. Circuit parts such as the row selection section 12, the constant current source section 13, the column amplifier section 14, the analog-digital conversion section 15, the horizontal transfer scanning section 16, the signal processing section 17, and the timing control section 18 are formed in the second-layer semiconductor chip 43. The first-layer semiconductor chip 42 and the second-layer semiconductor chip 43 are electrically connected through connection sections (VIA) 44A and 44B such as Cu-Cu connections.

[0043] According to the CMOS image sensor 10 having this stacked structure, the first-layer semiconductor chip 42 only needs to be large enough (area) to form the pixel array section 11, so that the size (area) of the first-layer semiconductor chip 42 and, ultimately, the size of the entire chip can be reduced. Furthermore, since a process suitable for fabricating the pixels 20 can be applied to the first-layer semiconductor chip 42 and a process suitable for fabricating the circuit section can be applied to the second-layer semiconductor chip 43, there is also the advantage that the process can be optimized when manufacturing the CMOS image sensor 10. In particular, advanced processes can be applied when fabricating the circuit section.

[0044] Although a two-layered structure in which the first-layer semiconductor chip 42 and the second-layer semiconductor chip 43 are stacked has been exemplified here, the stacked structure is not limited to a two-layered structure, and may be a three-layered or more structure. In the case of a three-layered or more stacked structure, circuit parts such as the row selection unit 12, the constant current source unit 13, the column amplifier unit 14, the analog-digital conversion unit 15, the horizontal transfer scanning unit 16, the signal processing unit 17, and the timing control unit 18 may be formed in a distributed manner in the semiconductor chips in the second layer and thereafter.

[0045] [Single-slope analog-to-digital converter] In the CMOS image sensor 10 configured as above, for example, a single-slope analog-digital converter has generally been used as the analog-digital converter in the analog-digital conversion unit 15. Here, the single-slope analog-digital converter will be described.

[0046] In a single-slope analog-digital converter, a signal with a ramp waveform (ramp wave) that changes linearly with a certain slope is used as a reference signal. The single-slope analog-digital converter compares the analog pixel signal read from the pixel 20 with a ramp wave reference signal, amplifies and clips the difference, modulates it into a phase signal, and then samples it to convert it into a digital signal. This single-slope analog-digital converter has the following problems.

[0047] ·Problem 1 The delay in modulating the phase signal introduces an offset, so digital Correlated Double Sampling (CDS) is essential to remove the fixed pattern noise of the pixel 20, requiring two analog-to-digital conversions and additional time for auto-zeroing. ·Problem 2 When the pixel signal and the ramp reference signal cross, a shoot-through current or kickback occurs. The time at which the pixel signal crosses depends on the pixel signal level, and this causes interference with the analog-to-digital converters of other pixel columns. ·Problem 3 Since the amplification transistor 24 of the pixel 20 is used to hold the voltage during analog-to-digital conversion, the conversion time limits the readout speed of the pixel signal.

[0048] Regarding problem 1, in single-slope analog-to-digital converters, auto-zeroing of the input amplifier (offset cancellation by shorting the input and output) is performed to prevent offsets. This makes it possible to remove DC offsets. However, because the ramp wave reference signal changes over time, it is not possible to remove AC offsets due to delays. While the delay can be reduced by widening the bandwidth, this increases the output phase noise.

[0049] Problem 2 is known as the mechanism of interference (streaking) from bright areas to dark areas. In a single-slope analog-to-digital converter, when multiple pixel rows have the same brightness, switching occurs simultaneously, which increases the effect of interference.

[0050] Problem 3 is a problem that occurs when sampling of the potential of the signal line 32 is not performed. The amplifying transistor 24 of the pixel 20 consumes a relatively large amount of power to drive the signal line 32, which has a large load capacitance. Therefore, it is not advisable to use the amplifying transistor 24 only to hold the voltage during analog-to-digital conversion.

[0051] *** Claim-01 First Embodiment of the Present Disclosure In the imaging device (a CMOS image sensor as an example) according to the first embodiment of the present disclosure, a successive approximation (SAR) type analog-digital converter is used as each analog-digital converter in the analog-digital conversion unit 15. The successive approximation type analog-digital converter is capable of operating at a higher speed with lower power consumption than the single-slope type analog-digital converter having the various problems described above. In this embodiment, the column signal processing system including the successive approximation type analog-digital converter is capable of operating at a higher speed with lower power consumption.

[0052] FIG. 5 is a block diagram showing an outline of the configuration of a CMOS image sensor which is an example of an imaging device according to the first embodiment of the present disclosure.

[0053] In the CMOS image sensor 10 according to this embodiment, the column amplifier unit 14 performs a process (CDS process) of finding the difference between a signal component (so-called D phase) and a reset component (so-called P phase) input from each pixel 20 of the pixel array unit 11 through a signal line 32, and outputs the difference as a pixel signal. A capacitance unit 19 is provided in the subsequent stage of the column amplifier unit 14.

[0054] *** Claims-10 The capacitance unit 19 holds the pixel signal input from the column amplifier unit 14, for example, by sampling using a switched capacitor. A successive approximation type analog-digital conversion unit 15A is provided in the subsequent stage of the capacitance unit 19. The successive approximation type analog-digital conversion unit 15A is made up of a plurality of successive approximation (SAR) type analog-digital converters that can operate at higher speed and with lower power consumption than a single-slope type analog-digital converter, and converts the analog pixel signal input from the capacitance unit 19 into a digital pixel signal.

[0055] *** Claims-10 According to the CMOS image sensor 10 of this embodiment, each successive approximation type analog-digital converter in the successive approximation type analog-digital conversion unit 15A performs a binary search, and therefore, in principle, when viewed individually, is more efficient than a single-slope type analog-digital converter that performs a sweep. Also, the CDS process, which was conventionally performed in two analog-digital conversions in an analog-digital converter, can be performed in the column amplifier unit 14 of the analog circuit system, thereby reducing the number of analog-digital conversions by half. Furthermore, by introducing sampling using a switched capacitor, the potential VSL of the signal line does not need to wait for analog-digital conversion, and sampling is always performed simultaneously regardless of the potential VSL of the signal line 32, so that the influence of interference due to switching is also small.

[0056] Below, we will explain a specific example of a column signal processing system in the CMOS image sensor 10 of the first embodiment, specifically, a column signal processing system including a column amplifier section 14, a capacitance section 19, and an analog-to-digital conversion section 15.

[0057] *** Claim-05, Claim-10 [First embodiment] The first embodiment is an example of intermittent operation in which a successive approximation type analog-digital converter performs conversion processing only during the P phase when a reset component is input, and waits during the D phase when a signal component is input. Fig. 6 is a circuit diagram showing an outline of the configuration of a column signal processing system according to the first embodiment. The column amplifier unit 14 is composed of column amplifiers 140 provided in the same number as the number of pixel columns, and the capacitance unit 19 is also composed of capacitance multiplexers 190 in the same number as the number of pixel columns.

[0058] *** Claim-04 Here, for one successive approximation type analog-digital converter 150 of the successive approximation type analog-digital conversion unit 15A, a configuration will be described as an example in which the potentials VSL0 to VSL7 of multiple signal lines 32, for example, eight signal lines 32, are multiplexed and processed through eight column amplifiers 140 and a capacitive multiplexer 190 corresponding to the eight signal lines 32.

[0059] *** Claim-02 (Column amplifier configuration example) The column amplifier 140 includes an amplifier 141, a first switch 142, a second switch 143, a third switch 144, a first capacitance element 145, and a second capacitance element 146. The first capacitance element 145 (hereinafter simply referred to as the "capacitance element 145") has a capacitance value C F The second capacitance element 146 (hereinafter simply referred to as the “capacitance element 146”) has a capacitance value C S It has.

[0060] *** Claim-02 The amplifier 141 receives the potential VSL (VSL0 to VSL7) of the signal line 32 as an input to a non-inverting (+) input terminal. A first switch 142 (hereinafter simply referred to as "switch 142") has one end connected to the output terminal of the amplifier 141 and the other end connected to the inverting (-) input terminal of the amplifier 141. A switch control signal S p Depending on the polarity (high level / low level) of the signal, the switch turns on (closed) or off (open).

[0061] *** Claim-02 One end of the second switch 143 (hereinafter simply referred to as "switch 143") is connected to the output terminal of the amplifier 141. One end of the capacitance element 145 is connected to the other end of the switch 143, and the other end is connected to the other end of the switch 142 and the inverting input terminal of the amplifier 141. The capacitance element 146 is connected to the other end of the capacitance element 145 and between the output terminal of the amplifier 141 and a node of a reference potential (for example, ground). The switch 143 is controlled by a switch control signal S D The on / off operation is performed according to the polarity of the

[0062] *** Claim-02 That is, the switch 143, the capacitance element 145, and the capacitance element 146 are connected in series in that order between the output terminal of the amplifier 141 and a node of a reference potential (for example, ground). In addition, a common connection node N1 of the capacitance elements 145 and 146 and the other end of the switch 142 are electrically connected.

[0063] *** Claim-02 The third switch 144 (hereinafter simply referred to as "switch 144") has one end connected to a common connection node N2 between the switch 143 and the capacitance element 145, and receives a switch control signal S VR The switch 144 performs an on / off operation according to the polarity of the switch 143. A local reference voltage VR that defines the zero voltage of the output of the column amplifier 140 is applied to the other end of the switch 144. That is, the switch 144 selectively applies the local reference voltage VR to a common connection node N2 between the switch 143 and the capacitance element 145.

[0064] *** Claim-10, Claim-11 (Example of a capacitance multiplexer configuration) The capacitance multiplexer 190 constituting the capacitance unit 19 has four switches 191 to 194 and one capacitance element 195, and is configured to perform sampling using a switched capacitor. The capacitance element 195 has a capacitance value C IN It has.

[0065] The switch 191 has one end connected to the output end of the column amplifier 140, i.e., the output terminal of the amplifier 141, and is connected to a switch control signal S IN The switch 192 is connected at one end to the other end of the switch 191 and is turned on / off according to the polarity of the switch control signal S VMI0 The switch 192 performs an on / off operation depending on the polarity of the switch 192. A specific reference voltage VX is applied to the other end of the switch 192. A local reference voltage VR may be used as the specific reference voltage VX.

[0066] One end of the capacitance element 195 is connected to the other end of the switch 191. One end of the switch 193 is connected to the other end of the capacitance element 195, and a switch control signal S VM The other end of the switch 193 is connected to a capacitance array unit (C DAC ) 155 is applied with an intermediate voltage VM.

[0067] The switch 194 has one end connected to the other end of the capacitive element 195 and one end of the switch 193, and is connected to a switch control signal S SUM0 The other end of the switch 194 is commonly connected to the eight capacitance multiplexers 190 corresponding to the potentials VSL0 to VSL7 of the signal line 32, and serves as the output end of the capacitance multiplexer 190.

[0068] (Example of the configuration of a successive approximation type analog-to-digital converter) The successive approximation type analog-to-digital converter 150 includes a preamplifier 151, a comparator 152, a SAR logic unit 153, a digital-to-analog converter (DAC) 154, and a capacitance array unit (C DAC )155.

[0069] The preamplifier 151 is composed of an amplifier 1511 and a switch 1512. The amplifier 1511 receives an analog voltage supplied from the capacitance multiplexer 190 at its inverting (-) input terminal and outputs a common-mode reference voltage V CM is input to the non-inverting (+) input terminal. The switch 1512 is an auto-zero (offset cancellation by input / output short) switch, and is connected between the inverting (-) input terminal and the output terminal of the preamplifier 151. The switch control signal S AZ The on / off operation is performed according to the polarity of the

[0070] The comparator 152 compares the analog voltage supplied through the preamplifier 151 with a comparison reference voltage in synchronization with the comparator clock CKI, and supplies the comparison result to the SAR logic unit 153 .

[0071] The SAR logic unit 153 is, for example, an N-bit successive approximation register, and stores the comparison result of the comparator 152 for each bit in synchronization with the clock CK, and outputs an N-bit digital value D OUT The output is as follows:

[0072] The digital-analog converter 154 and the capacitance array unit 155 constitute an N-bit capacitive digital-analog converter. In this capacitive digital-analog converter, the N-bit digital value D OUT is converted to an analog voltage and applied to the inverting (-) input terminal of amplifier 1511 as its input.

[0073] (Circuit operation of column signal processing system) Next, the circuit operation of the column signal processing system according to the first embodiment, which is composed of the column amplifier 140, the capacitive multiplexer 190, and the successive approximation type analog-to-digital converter 150, will be described with reference to the timing chart of FIG.

[0074] In the timing chart of FIG. 7, the potential VSL of the signal line 32, the switch control signal S P ,S VR , switch control signal S D ,S IN , S VM , switch control signal S VMI0 ,S SUM0 ~S VMI7 ,S SUM7 , clock CK, switch control signal S AZ , and the timing relationship of the comparator clock CKI.

[0075] *** Claim-03 First, the potentials VSL0 to VSL7 of the eight signal lines 32 are input to the corresponding dedicated column amplifiers 140. When the potentials VSL0 to VSL7 of the eight signal lines 32 are in a state of a reset component (P-phase voltage), the switch control signal S P and switch control signal S VR becomes high level, the switches 142 and 144 are turned on (closed). As a result, the reset component (P-phase voltage) is charged to the capacitive elements 145 and 146. At this time, the voltage of the common connection node N2 between the switch 143 and the capacitive element 145 is a reset component (P-phase voltage) that varies greatly depending on the pixel 20 (low accuracy), but the local reference voltage VR varies little (high accuracy) because it is generated on the column amplifier 140 side.

[0076] *** Claim-03 Next, the switch control signal S P and switch control signal S VR When the switch 142 and the switch 144 are turned off (open), the switch control signal S DWhen the voltage V 1 goes high, the switch 143 is turned on (closed). At this time, a non-inverting amplifier circuit is formed by the capacitive elements 145 and 146 and the amplifier 141, and the output voltage V out is approximately the same voltage as the local reference voltage VR.

[0077] *** Claim-03 Thereafter, when the potentials VSL0 to VSL7 of the eight signal lines 32 change (specifically, drop) to the signal components (D-phase voltages) that are luminance components, feedback is applied so that the voltage of the common connection node N1 between the capacitance elements 145 and 146 becomes the same voltage as the signal components (D-phase voltages). This series of operations performs CDS processing to find the difference between the reset components (P-phase voltages) and the signal components (D-phase voltages), and the output voltage V out is the potential VSL of the signal line 32 (C F +C S ) / C F The voltage drops by a factor of 1.

[0078] *** Claim-03 The signal components amplified by the column amplifier 140 are input to a capacitive multiplexer 190 that is composed of the same number of capacitive elements 195 as the column amplifiers 140. In the capacitive multiplexer 190, in the D phase, the switch control signal S IN and switch control signal S VM becomes high level, and in response to this, the switches 191 and 193 are turned on, so that the intermediate voltage VM is applied to the capacitive element 195. IN and switch control signal S VM becomes low level, and in response to this, the switches 191 and 193 are turned off, so that the capacitance value C IN A charge is held in the capacitance element 195.

[0079] *** Claim-03 Next, during the P phase, the switch control signal S VMIx (x=0 to 7) and switch control signal S SUMx(x=0 to 7) go to high level in sequence, and the switches 192 and 194 are turned on, so that the charge held in the capacitance element 191 is transferred to the successive approximation type analog-digital converter 150. The charge transfer is performed by dividing the P phase time into eight parts. As the D phase is used for sampling, the charge transfer can only be performed during the P phase.

[0080] *** Claim-03 When the capacitive element 191 is connected to the input terminal of the successive approximation type analog-digital converter 150 through the switch 194, a comparator clock CKI is input to the comparator 152 to start comparison. The comparison result of the comparator 152 is fed back to the digital-analog converter 154 through the SAR logic unit 153, and a binary search is performed so that the input of the preamplifier 151 becomes 0V. Eventually, almost all of the charge accumulated in the capacitive element 195 of the capacitive multiplexer 190 is transferred to the capacitive array unit (C DAC ) 155, and the input of the digital-to-analog converter 154 at that time is obtained as the output code.

[0081] Next, before the capacitance element 195 is connected, the switch control signal S AZ By setting the level of the preamplifier 151 to a high level, the switch 1512 of the preamplifier 151 is turned on (closed), and the capacitance array unit (C DAC )155 charge needs to be reset.

[0082] As described above, in the circuit operation of the column signal processing system according to the first embodiment, the successive approximation type analog-digital converter 150 operates only in the P phase, and is in an intermittent operation of waiting without doing anything in the D phase. During standby, the circuit current is stopped so as not to consume power, but since parts that cannot respond quickly cannot be stopped, waste occurs. In addition, since the power supply current differs greatly between the P phase and the D phase, it takes time for the power supply voltage to settle immediately after recovery.

[0083] In addition, in the configuration of the column signal processing system according to the first embodiment, in the capacitive multiplexer 190, the capacitive element 195 needs to sample the output of the column amplifier 140 during the D phase, and therefore cannot continue to hold the charge.

[0084] *** Claim-06 [Second embodiment] The second embodiment is a modification of the first embodiment, and is an example of a non-intermittent operation in which the successive approximation type analog-digital converter performs conversion processing not only in the P phase in which the reset component is input, but also in the D phase in which the signal component is input. Fig. 8 is a circuit diagram showing an outline of the configuration of a column signal processing system according to the second embodiment.

[0085] If the P-phase period and the D-phase period are roughly the same and analog-to-digital conversion is performed in half each, then when the potentials VSL0 to VSL7 of the eight signal lines 32 are multiplexed and processed, analog-to-digital conversion will be performed four times each.

[0086] In the column signal processing system according to the second embodiment, as shown in FIG. 8, the potentials VSL0 to VSL7 of the eight signal lines 32 are divided into potentials VSL0 to VSL3 of the first four signal lines 32 and potentials VSL4 to VSL7 of the last four signal lines 32.

[0087] The potentials VSL0 to VSL3 of the first four signal lines 32 are configured in the same manner as in the intermittent operation of the column signal processing system according to the first embodiment, since analog-to-digital conversion is performed during the P phase. The potentials VSL4 to VSL7 of the latter four signal lines 32 are configured in the same manner as in the intermittent operation of the column signal processing system according to the first embodiment, since sampling and analog-to-digital conversion are performed simultaneously during the D phase, and twice as many capacitive elements are prepared and used alternately for each sampling.

[0088] Specifically, three systems of circuits for performing sampling using switched capacitors are provided. The first system is a switch 191 _A , Switch 192 _A , Switch 193 _A , Switch 194_A , and the capacitance element 195 _A This is a circuit consisting of switch 191 _A , Switch 192 _A , Switch 193 _A is the switch control signal S IN0A ,S VMIA0 ,S VMA ,S SUMA0 The on / off operation is performed according to the polarity of the

[0089] The second system is switch 191 _B , Switch 192 _B , Switch 193 _B , Switch 194 _B , and the capacitance element 195 _B This is a circuit consisting of switch 191 _B , Switch 192 _B , Switch 193 _B is the switch control signal S IN1B ,S VMIB0 ,S VMB ,S SUMB0 The on / off operation is performed according to the polarity of the

[0090] The third system is switch 191 _C , Switch 192 _C , Switch 193 _C , Switch 194 _C , and the capacitance element 195 _C This is a circuit consisting of switch 191 _C , Switch 192 _C , Switch 193 _C , Switch 194 _C is the switch control signal S IN1C ,S VMIC ,S VMC ,S SUMC0 The on / off operation is performed according to the polarity of the

[0091] In the capacitive multiplexer 190 of the column signal processing system according to the second embodiment having the above configuration, during the P phase, the switch 191 _A , Switch 192 _A, Switch 193 _A , Switch 194 _A , and the capacitance element 195 _A During the D phase, the switch 191 is connected to the potentials VSL4 to VSL7 of the latter four signal lines 32. _B , Switch 192 _B , Switch 193 _B , Switch 194 _B , and the capacitance element 195 _B A circuit comprising: _C , Switch 192 _C , Switch 193 _C , Switch 194 _C , and the capacitance element 195 _C The circuit consisting of the above will operate.

[0092] *** Claim-07 [Third embodiment] The third embodiment is a modification of the second embodiment, and three capacitance elements (195) of the capacitance unit 19 (capacitance multiplexer 190) are connected to the potentials VSL0 to VSL3 of the two signal lines 32 and the potentials VSL4 to VSL7 of the signal lines 32. _A ,195 _B ,195 _C 9 is a circuit diagram showing an outline of the configuration of a column signal processing system according to the third embodiment.

[0093] (Example of column signal processing system configuration) In the capacitive multiplexer 190 of the column signal processing system according to the third embodiment, a switch 191 _A , Switch 191 _B , and switch 191 _C There are two systems each. And the switch 191 of one system _0A , Switch 191 _0B , and switch 191 _0C Each of the first four signal lines 32 has one end commonly connected to the output end of the column amplifier 140 for potentials VSL0 to VSL3, and the switch control signal S IN0A ,S IN0B ,S IN0CThe on / off operation is performed according to the polarity of the

[0094] Also, the switch 191 of the other system _1A , Switch 191 _1B , and switch 191 _1C The respective ends of the signal lines 32 are connected in common to the output ends of the column amplifiers 140 for the potentials VSL4 to VSL7 of the latter four signal lines 32, and the switch control signal S IN1A ,S IN1B ,S IN1C The on / off operation is performed according to the polarity of the

[0095] Switch 191 _0A and switch 191 _1A The other end of each of the switches 192 _A together with the other end of the capacitance element 195 _A The input terminals of the switch 191 are connected in common. _0B and switch 191 _1B The other end of each of the switches 192 _B together with the other end of the capacitance element 195 _B The input terminals of the switch 191 are connected in common. _0C and switch 191 _1C The other end of each of the switches 192 _C together with the other end of the capacitance element 195 _C are commonly connected to the input terminals of the

[0096] (Circuit operation of column signal processing system) FIG. 10 shows a timing chart for explaining the circuit operation of the column signal processing system according to the third embodiment.

[0097] In the timing chart of FIG. 10, the potential VSL of the signal line 32, the switch control signal S P ,S VR , switch control signal S D ,S IN , S VM , switch control signal S IN0A ,S IN1B , switch control signal S IN0B ,S IN1C , switch control signal S IN0C,S IN1A , and the switch control signal S VMA ,S VMB , S VMC The timing chart of FIG. 10 further shows the timing relationship between the switch control signal S VMIA0 ,S SUMA0 ~S VMIA3 ,S SUMA3 , switch control signal S VMIB0 ,S SUMB0 ~S VMIB3 ,S SUMB3 , switch control signal S VMIC0 ,S SUMC0 ~S VMIC3 ,S SUMC3 , clock CK, switch control signal S AZ , and the timing relationship of the comparator clock CKI.

[0098] The column amplifier 140 outputs a signal in the D phase. _A ,195 _B ,195 _C ) is performed only in the D phase, while the comparison in the comparator 152 is performed continuously in both the P phase and the D phase. In the example of the timing chart of FIG. 10, the capacitance element 195 _A The potentials VSL0 to VSL3 of the signal line 32 are sampled, and the capacitance element 195 _B The potentials VSL4 to VSL7 of the signal lines 32 are sampled.

[0099] The potentials VSL0 to VSL3 of the signal lines 32 are analog-digital converted in the immediately following P phase, and the potentials VSL4 to VSL7 of the signal lines 32 are analog-digital converted in the second D phase. _B is used for analog-to-digital conversion, the available capacitance is 195 _C and a capacitance element 195 _A At this time, the output of the column amplifier 140 is sampled. _AEach time, a potential VSL4 to VSL7 of the signal line 32 different from the previous time is sampled. By repeating this operation, the same capacitive element is not always used for the potential VSL of a specific signal line 32.

[0100] In the successive approximation type analog-digital converter 150, before each analog-digital conversion, the switch 1512 of the preamplifier 151 is turned on (closed) to activate the capacitance array unit (C DAC An auto-zero is performed to determine the initial value of capacitance multiplexer 190. At this time, switch 194 of capacitance multiplexer 190 is in the OFF (open) state.

[0101] During auto-zero, the capacitance array section (C DAC ) 155 is set to an arbitrary reset code, and this reset code becomes the output code when the input voltage is 0V.

[0102] Auto-zero has the effect of canceling the offset of the preamplifier 151, but it should be noted that in this analog-to-digital conversion, the input capacitance is separated at the time of sampling, so offset cancellation cannot be performed completely.

[0103] After a certain period of time has elapsed, the switch 1512 of the preamplifier 151 is turned off (open), and the switches 192 and 194 of the capacitance multiplexer 190 are turned on (closed) to transfer the charges. At the same time, an intermediate voltage VM is applied to the entire capacitance array unit 155 (see FIG. 11).

[0104] After settling, the first pulse of the clock ICK is input to start the comparison operation. The clock ICK is input multiple times, the analog-to-digital conversion result is determined, and the next analog-to-digital conversion is started. Auto-zero takes more time than the settling of the capacitance array unit 155, so it is set to a predetermined length. In addition, the time from auto-zero to the first clock ICK is set to a predetermined period.

[0105] In the configuration of the column signal processing system according to the second embodiment shown in FIG. 8, the capacitance element 195 is always used for sampling the potentials VSL0 to VSL3 of the signal line 32. _A On the other hand, the potentials VSL4 to VSL7 of the signal line 32 are sampled using the capacitance element 195 _B and Capacitive element 195 _C This may result in systematic errors being introduced.

[0106] In contrast, in the configuration of the column signal processing system according to the third embodiment, as is clear from the above-mentioned circuit operation, three capacitance elements (195 _A ,195 _B ,195 _C ) are used evenly, which helps to avoid systematic errors.

[0107] *** Claim-08 [Fourth embodiment] The fourth embodiment is an implementation example of a column signal processing system, and is an example of a configuration of a differential circuit after the capacitive unit 19 (capacitive multiplexer 190). Fig. 11 is a circuit diagram showing an outline of the configuration of the column signal processing system according to the fourth embodiment.

[0108] 11 illustrates the column amplifier 140, the capacitive multiplexer 190, and a reference voltage generation unit 160 that generates a reference voltage used in the successive approximation type analog-to-digital converter 150. The reference voltage generation unit 160 is composed of a first amplifier unit 161, a second amplifier unit 162, and a third amplifier unit 163.

[0109] The first amplifier section 161 generates a local reference voltage VR that defines the zero voltage of the output of the column amplifier 140. The local reference voltage VR is supplied to the column amplifier 140 through a voltage line L1. The second amplifier section 162 generates a common-mode reference voltage V CM is supplied to the capacitive multiplexer 190 through the voltage line L2. The output common-mode reference voltage V CMis also supplied to the successive approximation type analog-to-digital converter 150 through the voltage line L3. DAC The high voltage VH, the medium voltage VM, and the low voltage VL are supplied to the capacitance array unit (C) 155 through voltage lines L4, L5, and L6. DAC )155.

[0110] During the P phase, the capacitive element 145 of the column amplifier 140 is charged by the local reference voltage VR, and during the D phase, the local reference voltage VR is used as the negative signal input of the capacitive multiplexer (CMUX) 190. The capacitive multiplexer 190 is configured differentially. The input side switch 192 _A , Switch 192 _B , and switch 192 _C When the comparator 152 makes a comparison, the differential is shorted and is not connected to the common node. In this way, the input side of the capacitive multiplexer 190 is completely isolated when the comparator 152 makes a comparison, so that the capacitance array section (C DAC )155 can settle faster.

[0111] A switch 193 on the output side of the capacitance multiplexer 190 _AP ,193 _AM , Switch 193 _BP ,193 _BM , and switch 193 _CP ,193 _CM is the output common-mode reference voltage V CM It is connected to the voltage line L2 that transmits the output common-mode reference voltage V CM becomes the same voltage as the input operating potential of the preamplifier 151.

[0112] The high voltage VH, the medium voltage VM, and the low voltage VL generated by the third amplifier unit 163 are supplied to the capacitor array unit (C DAC ) 155 is the reference voltage of the capacitance array section (C DACSince comparator 152 operates at high speed during comparison, high voltage VH and low voltage VL are required to be capable of high-speed response and have low impedance.

[0113] (Power supply voltage and transistors used) Here, the power supply voltage specification is, for example, 2.8V (V DD _H) and 0.8V(V DD _L) is assumed. 2.8V is the same as the voltage used in the pixel 20, and is used for circuits of high-voltage transistors. 0.8V is assumed to be the voltage used in logic circuits. The potential VSL of the signal line 32 is a maximum of 2V or more, and therefore cannot be handled by low-voltage transistors. Therefore, the column amplifier 140 must be configured with high-voltage transistors. The successive approximation type analog-digital converter 150 is desirably configured with low-voltage transistors, since it requires high-speed comparison operations. However, care must be taken to avoid large leakage currents in low-voltage transistors.

[0114] In addition, when multiple power supplies are involved in the loop of the successive approximation type analog-digital converter 150, an operating margin is required to absorb the variations between the different power supplies, so it is important to configure it with a single power supply. DAC ) 155, we want to apply sufficient gate voltage to the switches that make up the DD Since the output of the column amplifier 140 is a high voltage, the switches constituting the capacitive multiplexer 190 are all made of high-voltage transistors.

[0115] (About the level diagram) A level diagram is shown in Fig. 12. The voltage range of the potential VSL of the signal line 32 varies depending on the sensor specifications, but here, the voltage is set to 2V as a reference and drops according to the brightness, with a maximum voltage drop of 450mV. The potential VSL of this signal line 32 is amplified by the column amplifier 140, and since the higher the gain, the more the noise of the successive approximation type analog-digital converter 150 in the subsequent stage is suppressed and the noise of the column amplifier 140 itself is also reduced, it is desirable to have as large a gain as possible. However, since the power supply voltage is 2.8V, it is necessary to suppress the output of the column amplifier 140 within a range that includes the operating range and margin of the circuit.

[0116] Here, the gain is set to 4 times, and the range is 1.8V to 2.8V. The input to the successive approximation type analog-digital converter 150 is a differential voltage, with the negative input fixed to the reference voltage. When the pixel 20 has zero brightness, a differential of 0V is input to the successive approximation type analog-digital converter 150, and as the pixel 20 becomes brighter (i.e., the potential VSL of the signal line 32 decreases), a negative differential voltage is added. The relationship with the output code of the successive approximation type analog-digital converter 150 is such that a differential of 1.8V corresponds to 3 / 4 full scale, and 7 / 8 full scale is output when 0V is input.

[0117] For small input signals, the input-referred noise can be reduced by increasing the gain. As shown in Figure 12, when the gain is increased by 8 times (x8), the input range is halved. The gain can be increased further, but since the contribution of the column amplifier 140 is dominant in the input-referred noise, there is little benefit to increasing the gain beyond 8 times.

[0118] A specific example of the configuration of the column amplifier 140 and the successive approximation type analog-digital converter 150 will be described below.

[0119] *** Claim-09 (Column amplifier configuration example) Here, a current reuse column amplifier (CRCA) is illustrated as an example of a specific configuration of the column amplifier 140. The current reuse column amplifier performs voltage amplification by utilizing the bias current of the signal line 32, and therefore can realize a low-power non-inverting column amplifier. A circuit diagram of an example of the configuration of the current reuse column amplifier is shown in FIG.

[0120] The current reuse column amplifier 1400 includes a current amplifying transistor 1401 , current source transistors 1402 and 1403 , cascode transistors 1404 and 1405 , switches 1406 , 1407 , and 1408 , a reference side capacitance element 1409 , and a feedback capacitance element 1410 .

[0121] Here, for example, P-channel MOS field effect transistors are used as the current amplification transistor 1401, the current source transistor 1403, and the cascode transistor 1404. Also, for example, N-channel MOS field effect transistors are used as the current source transistor 1402 and the cascode transistor 1405.

[0122] The current amplifying transistor 1401 and the current source transistor 1402 are connected in series in that order between the signal line 32 and a node of a reference potential (for example, ground). That is, the source electrode of the current amplifying transistor 1401 is connected to the signal line 32. A predetermined bias voltage nbias is applied to the gate electrode of the current source transistor 1402. As a result, the current source transistor 1402 passes a constant bias current corresponding to the predetermined bias voltage nbias through the signal line 32.

[0123] The current source transistor 1403, the cascode transistor 1404, and the cascode transistor 1405 are connected to a power supply voltage V DDand the drain electrode of the current source transistor 1402. A predetermined bias voltage pbias is applied to the gate electrode of the current source transistor 1403, a predetermined bias voltage pcas is applied to the gate electrode of the cascode transistor 1404, and a predetermined bias voltage ncas is applied to the gate electrode of the cascode transistor 1405.

[0124] The switch 1406 is connected between the gate electrode of the current amplifying transistor 1401 and the drain electrode of the cascode transistor 1404 (the drain electrode of the cascode transistor 1405), and is connected to a switch control signal S P Depending on the polarity, it performs on (close) / off (open) operation.

[0125] The reference-side capacitance element 1409 is connected between the gate electrode of the current amplification transistor 1401 and a node of a reference potential (for example, ground). One end of the feedback capacitance element 1410 is connected to the gate electrode of the current amplification transistor 1401.

[0126] The switch 1047 is connected between the other end of the feedback capacitance element 1410 and the drain electrode of the cascode transistor 1404 (the drain electrode of the cascode transistor 1405), and is connected to a switch control signal S D The on / off operation is performed according to the polarity of the

[0127] The switch 1408 has one end connected to a common connection node N 11 and the switch control signal S VR The switch 1408 is turned on / off according to the polarity of the switch control signal S. The other end of the switch 1408 is applied with a local reference voltage VR. VR Under the control of the common connection node N 11 A local reference voltage VR is selectively provided for each of the inputs.

[0128] With the above configuration, the source electrode of the current amplifying transistor 1401 serves as the (+) input terminal, the gate electrode serves as the (-) input terminal, and the common connection node N 12 The current amplifying transistor 1401 utilizes the bias current of the signal line 32, and therefore can efficiently amplify the voltage.

[0129] In the current reuse column amplifier 1400 having the above configuration, in terms of the correspondence with the column amplifier 140 shown in FIG. 6, the switch 1406 corresponds to the switch 142 in FIG. 6, the switch 1407 corresponds to the switch 143 in FIG. 6, and the switch 1408 corresponds to the switch 144 in FIG. 6. Also, the reference side capacitance element 1409 has a capacitance value C S The feedback capacitance element 1410 corresponds to the capacitance element 146 having a capacitance value of C F This corresponds to the capacitance element 145.

[0130] (Example of the configuration of a successive approximation type analog-to-digital converter) The successive approximation type analog-to-digital converter 150 is highly power efficient. A detailed circuit diagram of the successive approximation type analog-to-digital converter 150 is shown in FIG.

[0131] The circuit of the successive approximation type analog-to-digital converter 150 is configured as a fully differential circuit. A typical successive approximation type analog-to-digital converter has an input capacitance for sampling an input voltage and a DAC capacitance (C DAC ) are often integrated together, but here they are separated for multiplexing purposes.

[0132] 14 also illustrates an input capacitance section (hereinafter, for convenience, referred to as "capacitance multiplexer 190") that also serves as the capacitance multiplexer 190. For simplicity, only one of multiple input capacitance sections (190) is illustrated here.

[0133] In the capacitance multiplexer 190, during sampling, the switch 191_P ,191 _M and switch 193 _P ,193 _M is turned on (closed) and the capacitance element 195 _P ,195 _M During analog-to-digital conversion, the switches 192 and 194 _P ,194 _M When this signal is turned on (closed), the capacitive multiplexer 190 is connected to the successive approximation type analog-to-digital converter 150.

[0134] The switch 192 is not connected to a specific reference potential, but only shorts the differential. This is to prevent the common-mode potential on the preamplifier 151 side from fluctuating due to the common-mode potential of the input. The output common-mode potential of the preamplifier 151 and the output common-mode reference voltage V CM By combining these, the input common-mode potential of the preamplifier 151 is always equal to the output common-mode reference voltage V CM It becomes the same as:

[0135] Since the output of the column amplifier 140 is single-ended, the common-mode potential of the input varies depending on the signal, but the input common-mode potential of the preamplifier 151 does not change, improving linearity. The input side is the output of the column amplifier 140 (2.4V to 0.6V) and the local reference voltage VR (2.4V), but the output common-mode reference voltage V CM Since the voltage is fixed at about 0.5V, DD _L) preamplifier 151 can be used.

[0136] Although the input differential voltage is high at 1.8V, the DAC capacitance (C DAC ), the input voltage of the preamplifier 151 is sufficiently attenuated. By managing the common-mode and differential voltages in this way, the switches other than the capacitive multiplexer 190 can be constructed using low-voltage transistors with relatively thin film thicknesses. Incidentally, all the switches of the capacitive multiplexer 190 are constructed using high-voltage transistors with relatively thick film thicknesses.

[0137] A preamplifier 151, a comparator 152, a SAR logic unit 153, and a DAC capacitance (C DAC ) all use the same power supply voltage and transistors of the same thickness, enabling high-speed operation.

[0138] It is also important that the SAR logic unit 153 is completely isolated from the column amplifier 140 and reference nodes other than the high voltage VH / low voltage VL during operation. These nodes are not very fast or low impedance, so the DAC capacitance (C DAC ) settling must not be affected.

[0139] As shown in Figure 14, the DAC capacitance (C DAC The capacitor array of the 3141 consists of 14 capacitors grouped in a 6-4-4 configuration. The first 6-bit group is the MSB, the middle 4-bit group is the LSB1, and the last 4-bit group is the LSB0. Each group is separated by a bridge capacitor element, and the weight of each capacitor element varies. If the weight of the MSB is 1, then LSB1 is 1 / 8 and LSB0 is 1 / 32.

[0140] The most significant bit in LSB1 and the least significant bit in MSB have the same weight, providing redundancy. Similarly, the most significant bit in LSB0 is duplicated. Since there is a total of 2 bits of redundancy, the final bit precision of the successive approximation type analog-to-digital converter 150 is 12 bits. The redundancy is provided to compensate for insufficient settling of the upper bits and to correct nonlinearity caused by variations in the bridge capacitance elements.

[0141] To expand the range of redundancy, the redundant bits should be inserted as far up as possible, but there is a trade-off in that the number of capacitance elements increases and noise also increases. Also, to correct the variation in the bridge capacitance elements, the redundant bits need to be inserted within each group.

[0142] The capacitance value of the bridge capacitance element, C BThe ratio of the weights to the lower groups is α (<1), and the total capacity of the lower groups (including the actual capacity of the lower groups) is C TL Then, it can be expressed by the following equation. C B =C TL / {(1 / α)-1}

[0143] Since the bridge capacitance element determines the weight of the entire lower bits, deviation in the ratio with the unit capacitance element will cause nonlinearity. Therefore, it is necessary to implement it so that deviation is avoided as much as possible, but since it is not an integer multiple and there is no continuity in the layout, it is difficult to match the ratio between the bridge capacitance element and the unit capacitance element. Therefore, it seems necessary to perform digital correction by multiplying each group by a non-integer correction coefficient.

[0144] <Second embodiment of the present disclosure> The second embodiment of the present disclosure is an example in which the technology according to the present disclosure is applied to an indirect-TOF (Indirect-Time of Flight) type range image sensor. The indirect TOF type range image sensor is a sensor that measures the distance to a measurement object (subject) by measuring the time of flight of light emitted from a light source and reflected by the measurement object based on detection of the arrival phase difference of the reflected light.

[0145] [System configuration example] FIG. 15 is a block diagram showing an example of a system configuration of an indirect TOF range image sensor according to the second embodiment of the present disclosure.

[0146] In the indirect TOF type range image sensor 50, light emitted from a light source 60 is reflected by a measurement target (subject), and the reflected light is incident. The indirect TOF type range image sensor 50 has a stacked structure including a sensor chip 51 and a circuit chip 52 stacked on the sensor chip 51. In this stacked structure, the sensor chip 51 and the circuit chip 52 are electrically connected through a connection part (not shown) such as a via (VIA) or a Cu-Cu connection. Note that FIG. 15 illustrates a state in which the wiring of the sensor chip 51 and the wiring of the circuit chip 52 are electrically connected through the above-mentioned connection part.

[0147] A pixel array section 53 is formed on the sensor chip 51. The pixel array section 53 includes a plurality of pixels 54 arranged in a matrix (array) in a two-dimensional grid pattern on the sensor chip 51. In the pixel array section 53, each of the plurality of pixels 54 receives incident light (for example, near-infrared light), performs photoelectric conversion, and outputs an analog pixel signal. Two signal lines VSL1 and VSL2 are wired to the pixel array section 53 for each pixel column. If the number of pixel columns in the pixel array section 53 is M (M is an integer), a total of (2×M) signal lines VSL are wired to the pixel array section 53.

[0148] Each of the pixels 54 has a first tap A and a second tap B (details of which will be described later). Of the two signal lines VSL1 and VSL2, the signal line VSL1 carries an analog pixel signal AIN P1 Also, an analog pixel signal AIN P2 Analog pixel signal AIN P1 ,AIN P2 More on this later.

[0149] A row selection unit 55, a column signal processing unit 56, an output circuit unit 57, and a timing control unit 58 are arranged on the circuit chip 52. The row selection unit 55 drives each pixel 54 of the pixel array unit 53 in units of pixel rows, and outputs a pixel signal AIN P1 ,AIN P2 Under the driving of the row selection unit 55, the analog pixel signal AIN P1 ,AIN P2 are supplied to the column signal processing unit 56 through two signal lines VSL1 and VSL2.

[0150] The column signal processing unit 56 has a configuration including a plurality of analog-to-digital converters (ADCs) 59 provided corresponding to (for example, for each pixel column) the pixel columns of the pixel array unit 53. The analog-to-digital converters 59 convert analog pixel signals AIN P1 ,AIN P2 The output circuit unit 57 converts the digitized pixel signal A.I.N output from the column signal processor 56 into digital data. P1 ,AIN P2 The signal is subjected to a predetermined signal processing and output to the outside of the circuit chip 52.

[0151] The timing control unit 58 generates various timing signals, clock signals, control signals, etc., and controls the driving of the row selection unit 55, the column signal processing unit 56, the output circuit unit 57, etc. based on these signals.

[0152] [Pixel circuit configuration example] FIG. 16 is a circuit diagram showing an example of a circuit configuration of a pixel 54 in an indirect TOF range image sensor 50 according to the second embodiment.

[0153] The pixel 54 according to this example has, as a photoelectric conversion element, for example, a photodiode 541. In addition to the photodiode 541, the pixel 54 has an overflow transistor 542, two transfer transistors 543, 544, two reset transistors 545, 546, two floating diffusion layers 547, 548, two amplification transistors 549, 550, and two selection transistors 551, 552. The two floating diffusion layers 547, 548 correspond to first and second taps A, B (hereinafter, may be simply referred to as "taps A, B") shown in FIG. 15.

[0154] The photodiode 541 photoelectrically converts the received light to generate an electric charge. The photodiode 541 may have, for example, a back-illuminated pixel structure. However, the structure is not limited to the back-illuminated type, and the photodiode 541 may have a front-illuminated type structure that captures light irradiated from the front surface side of the substrate.

[0155] The overflow transistor 542 is connected to the cathode electrode of the photodiode 541 and the power supply voltage V DD and has a function of resetting the photodiode 541. Specifically, the overflow transistor 542 becomes conductive in response to an overflow gate signal TRG supplied from the row selection unit 55, thereby sequentially transferring the charge generated in the photodiode 541 to the floating diffusion layers 547 and 548, respectively.

[0156] The floating diffusion layers 547 and 548 corresponding to the first and second taps A and B accumulate the charge transferred from the photodiode 541, convert the charge into a voltage signal having a voltage value according to the amount of charge, and generate a pixel signal AIN P1 ,AIN P2 Generate.

[0157] The two reset transistors 545 and 546 are connected to the two floating diffusion layers 547 and 548, respectively, and the power supply voltage V DD The reset transistors 545 and 546 are connected between the power supply line of the row selector 55 and the floating diffusion layers 347 and 348. When the reset transistors 545 and 546 are turned on in response to a reset signal RST supplied from the row selector 55, the reset transistors 545 and 546 pull out electric charges from the floating diffusion layers 347 and 348, respectively, to initialize the amounts of electric charges.

[0158] The two amplifying transistors 549 and 550 are connected to a power supply voltage V DD and two selection transistors 551 and 552, respectively, and amplify the voltage signals converted from charges to voltages in the floating diffusion layers 547 and 548, respectively.

[0159] The two selection transistors 551 and 552 are connected between the two amplification transistors 549 and 550 and the signal lines VSL1 and VSL2, respectively. The selection transistors 551 and 552 are turned on in response to a selection signal SEL supplied from the row selection unit 55, and thereby convert the voltage signals amplified by the amplification transistors 549 and 550 into analog pixel signals AIN P1 ,AIN P2 and outputs the signal to two signal lines VSL1 and VSL2.

[0160] The two signal lines VSL1 and VSL2 are connected to the input terminal of one analog-to-digital converter 59 in the column signal processing unit 56 for each pixel column, and the analog pixel signal AIN P1 ,AIN P2 is transmitted to an analog-to-digital converter 59.

[0161] The circuit configuration of the pixel 54 is such that an analog pixel signal AIN P1 ,AIN P2 As long as the circuit configuration can generate the above, the present invention is not limited to the circuit configuration illustrated in FIG.

[0162] In the indirect TOF range image sensor 50 having the above configuration, the technology according to the present disclosure can be applied to the column signal processing unit 56 including the analog-digital converter 59. More specifically, as in the first embodiment, the column signal processing system according to the first, second, third, or fourth embodiment including the column amplifier unit 14, the capacitance unit 19, and the successive approximation type analog-digital conversion unit 15A can be used as the column signal processing unit 56 including the analog-digital converter 59.

[0163] <Modification> Although the technology according to the present disclosure has been described above based on preferred embodiments, the technology according to the present disclosure is not limited to these embodiments. The configurations and structures of the CMOS image sensor and the indirect TOF range image sensor described in the above embodiments are merely examples and can be modified as appropriate.

[0164] <Application Examples> The imaging device (CMOS image sensor) according to the first embodiment can be used in various devices for sensing light such as visible light, infrared light, ultraviolet light, and X-rays, as shown in Fig. 17. Specific examples of various devices are listed below.

[0165] ·Digital cameras, mobile devices with camera functions, and other devices that take images for viewing purposes - Devices used for traffic purposes, such as on-board sensors that take pictures of the front, rear, surroundings, and interior of a vehicle for safe driving (such as automatic stopping) and for recognition of the driver's condition, surveillance cameras that monitor moving vehicles and roads, and distance measuring sensors that measure distances between vehicles, etc. A device used in home appliances such as TVs, refrigerators, and air conditioners to capture user gestures and operate the appliances according to those gestures. -Medical and healthcare equipment, such as endoscopes and devices that take blood vessel images using infrared light - Equipment used for security purposes, such as surveillance cameras for crime prevention and cameras for person authentication - Devices used for beauty purposes, such as skin measuring devices that take pictures of the skin and microscopes that take pictures of the scalp - Devices used for sports, such as action cameras and wearable cameras for sports use Agricultural equipment such as cameras for monitoring fields and crop conditions

[0166] <Application examples of the technology disclosed herein> The technology according to the present disclosure can be applied to various products. More specific application examples will be described below.

[0167] *** Claim-12 [Electronic device of the present disclosure] Here, the present invention will be described as being applied to imaging systems such as digital still cameras and video cameras, portable terminal devices having an imaging function such as mobile phones, and electronic devices such as copiers that use an imaging device in an image reading section.

[0168] (Example of imaging system) FIG. 18 is a block diagram showing an example of the configuration of an imaging system that is an example of the electronic device of the present disclosure.

[0169] 18, an imaging system 100 according to this example includes an imaging optical system 101 including a lens group and the like, an imaging unit 102, a DSP (Digital Signal Processor) circuit 103, a frame memory 104, a display device 105, a recording device 106, an operation system 107, and a power supply system 108. The DSP circuit 103, the frame memory 104, the display device 105, the recording device 106, the operation system 107, and the power supply system 108 are connected to each other via a bus line 109.

[0170] The imaging optical system 101 captures incident light (image light) from a subject and forms an image on the imaging surface of the imaging unit 102. The imaging unit 102 converts the amount of incident light imaged on the imaging surface by the optical system 101 into an electrical signal on a pixel-by-pixel basis and outputs the signal as a pixel signal. The DSP circuit 103 performs general camera signal processing, such as white balance processing, demosaic processing, and gamma correction processing.

[0171] The frame memory 104 is used to store data as appropriate during signal processing in the DSP circuit 103. The display device 105 is made up of a panel-type display device such as a liquid crystal display device or an organic EL (electro luminescence) display device, and displays moving images or still images captured by the imaging unit 102. The recording device 106 records the moving images or still images captured by the imaging unit 102 on a recording medium such as a portable semiconductor memory, an optical disc, or an HDD (Hard Disk Drive).

[0172] An operation system 107, under the operation of a user, issues operation commands for various functions of the imaging device 100. A power supply system 108 appropriately supplies various types of power to the DSP circuit 103, frame memory 104, display device 105, recording device 106, and operation system 107 as operating power sources to these devices.

[0173] In the imaging system 100 having the above configuration, the imaging device according to the first embodiment described above can be used as the imaging unit 102. In the imaging device according to the first embodiment, the successive approximation type analog-digital converter in particular has excellent power efficiency, so that using the imaging device as the imaging unit 102 can contribute to reducing the power consumption of the imaging system 100.

[0174] [Application to moving objects] The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure may be realized as an imaging device mounted on any type of moving object such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, a personal mobility device, an airplane, a drone, a ship, a robot, a construction machine, or an agricultural machine (tractor).

[0175] FIG. 19 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a moving object control system to which the technology according to the present disclosure can be applied.

[0176] The vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001. In the example shown in Fig. 19, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside-vehicle information detection unit 12030, an inside-vehicle information detection unit 12040, and an integrated control unit 12050. Also, as functional configurations of the integrated control unit 12050, a microcomputer 12051, an audio / video output unit 12052, and an in-vehicle network I / F (interface) 12053 are illustrated.

[0177] The drivetrain control unit 12010 controls the operation of devices related to the drivetrain of the vehicle in accordance with various programs. For example, the drivetrain control unit 12010 functions as a control device for a drive force generating device for generating a drive force of the vehicle, such as an internal combustion engine or a drive motor, a drive force transmission mechanism for transmitting the drive force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, and a braking device for generating a braking force of the vehicle.

[0178] The body system control unit 12020 controls the operation of various devices mounted on the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window device, or various lamps such as head lamps, back lamps, brake lamps, turn signals, and fog lamps. In this case, radio waves or signals of various switches transmitted from a portable device that replaces a key may be input to the body system control unit 12020. The body system control unit 12020 receives the input of these radio waves or signals and controls the door lock device, power window device, lamps, and the like of the vehicle.

[0179] The outside-vehicle information detection unit 12030 detects information outside the vehicle equipped with the vehicle control system 12000. For example, an imaging unit 12031 is connected to the outside-vehicle information detection unit 12030. The outside-vehicle information detection unit 12030 causes the imaging unit 12031 to capture an image outside the vehicle and receives the captured image. The outside-vehicle information detection unit 12030 may perform object detection processing or distance detection processing for a person, a car, an obstacle, a sign, or characters on a road surface, based on the received image.

[0180] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal according to the amount of light received. The imaging unit 12031 can output the electrical signal as an image, or as distance measurement information. The light received by the imaging unit 12031 may be visible light or invisible light such as infrared light.

[0181] The in-vehicle information detection unit 12040 detects information inside the vehicle. For example, a driver state detection unit 12041 that detects the state of the driver is connected to the in-vehicle information detection unit 12040. The driver state detection unit 12041 includes, for example, a camera that captures an image of the driver, and the in-vehicle information detection unit 12040 may calculate the degree of fatigue or concentration of the driver based on the detection information input from the driver state detection unit 12041, or may determine whether the driver is dozing.

[0182] The microcomputer 12051 can calculate control target values ​​for the driving force generating device, the steering mechanism, or the braking device based on the information inside and outside the vehicle acquired by the outside-of-vehicle information detection unit 12030 or the inside-vehicle information detection unit 12040, and output a control command to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing the functions of an ADAS (Advanced Driver Assistance System), including vehicle collision avoidance or impact mitigation, following driving based on the inter-vehicle distance, vehicle speed maintenance driving, vehicle collision warning, vehicle lane departure warning, etc.

[0183] In addition, the microcomputer 12051 can perform cooperative control for the purpose of autonomous driving, which allows the vehicle to travel autonomously without relying on the driver's operation, by controlling the driving force generating device, steering mechanism, braking device, etc. based on information about the surroundings of the vehicle acquired by the outside vehicle information detection unit 12030 or the inside vehicle information detection unit 12040.

[0184] Furthermore, the microcomputer 12051 can output a control command to the body system control unit 12020 based on the information outside the vehicle acquired by the outside-vehicle information detection unit 12030. For example, the microcomputer 12051 can control the headlamps according to the position of a preceding vehicle or an oncoming vehicle detected by the outside-vehicle information detection unit 12030, and perform cooperative control for the purpose of preventing glare, such as switching from high beams to low beams.

[0185] The audio / image output unit 12052 transmits at least one output signal of audio and image to an output device capable of visually or audibly notifying information to passengers in the vehicle or the outside of the vehicle. In the example of Fig. 19, an audio speaker 12061, a display unit 12062, and an instrument panel 12063 are exemplified as the output device. The display unit 12062 may include at least one of an on-board display and a head-up display, for example.

[0186] FIG. 20 is a diagram showing an example of the installation position of the imaging unit 12031.

[0187] In FIG. 20, a vehicle 12100 has imaging units 12101, 12102, 12103, 12104, and 12105 as an imaging unit 12031.

[0188] The imaging units 12101, 12102, 12103, 12104, and 12105 are provided at positions such as the front nose, side mirrors, rear bumper, back door, and the upper part of the windshield inside the vehicle cabin of the vehicle 12100. The imaging unit 12101 provided at the front nose and the imaging unit 12105 provided at the upper part of the windshield inside the vehicle cabin mainly acquire images of the front of the vehicle 12100. The imaging units 12102 and 12103 provided at the side mirrors mainly acquire images of the sides of the vehicle 12100. The imaging unit 12104 provided at the rear bumper or back door mainly acquires images of the rear of the vehicle 12100. The images of the front acquired by the imaging units 12101 and 12105 are mainly used to detect a preceding vehicle, a pedestrian, an obstacle, a traffic light, a traffic sign, a lane, or the like.

[0189] 20 shows an example of the imaging ranges of the imaging units 12101 to 12104. An imaging range 12111 indicates the imaging range of the imaging unit 12101 provided on the front nose, imaging ranges 12112 and 12113 indicate the imaging ranges of the imaging units 12102 and 12103 provided on the side mirrors, respectively, and an imaging range 12114 indicates the imaging range of the imaging unit 12104 provided on the rear bumper or back door. For example, an overhead image of the vehicle 12100 viewed from above is obtained by superimposing the image data captured by the imaging units 12101 to 12104.

[0190] At least one of the imaging units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera made up of a plurality of imaging devices, or may be an imaging device having pixels for detecting a phase difference.

[0191] For example, the microcomputer 12051 can extract, as a preceding vehicle, a three-dimensional object that is the closest three-dimensional object on the travel path of the vehicle 12100 and travels at a predetermined speed (for example, 0 km / h or more) in approximately the same direction as the vehicle 12100, by calculating the distance to each three-dimensional object in the imaging ranges 12111 to 12114 and the change over time of this distance (relative speed with respect to the vehicle 12100) based on the distance information obtained from the imaging units 12101 to 12104. Furthermore, the microcomputer 12051 can set a vehicle distance to be secured in advance in front of the preceding vehicle, and perform automatic brake control (including follow-up stop control) and automatic acceleration control (including follow-up start control). In this way, cooperative control can be performed for the purpose of automatic driving that travels autonomously without relying on the driver's operation.

[0192] For example, the microcomputer 12051 classifies and extracts three-dimensional object data on three-dimensional objects into two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects based on distance information obtained from the imaging units 12101 to 12104, and can use the data for automatic obstacle avoidance. For example, the microcomputer 12051 distinguishes obstacles around the vehicle 12100 into obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see. Then, the microcomputer 12051 determines a collision risk indicating the risk of collision with each obstacle, and when the collision risk is equal to or greater than a set value and a collision is possible, the microcomputer 12051 can provide driving assistance for collision avoidance by outputting an alarm to the driver via the audio speaker 12061 or the display unit 12062, or by performing forced deceleration or avoidance steering via the drive system control unit 12010.

[0193] At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 can recognize a pedestrian by determining whether or not a pedestrian is present in the captured images of the imaging units 12101 to 12104. The recognition of such a pedestrian is performed, for example, by a procedure of extracting feature points in the captured images of the imaging units 12101 to 12104 as infrared cameras, and a procedure of performing pattern matching processing on a series of feature points that indicate the contour of an object to determine whether or not the object is a pedestrian. When the microcomputer 12051 determines that a pedestrian is present in the captured images of the imaging units 12101 to 12104 and recognizes the pedestrian, the audio / image output unit 12052 controls the display unit 12062 to superimpose a rectangular contour line for emphasis on the recognized pedestrian. The audio / image output unit 12052 may also control the display unit 12062 to display an icon or the like indicating a pedestrian at a desired position.

[0194] An example of a vehicle control system to which the technology according to the present disclosure can be applied has been described above. The technology according to the present disclosure can be applied to, for example, the imaging units 7910, 7912, 7914, 7916, and 7918 and the outside vehicle information detection units 7920, 7922, 7924, 7926, 7928, and 7930 among the configurations described above. In particular, since the successive approximation type analog-digital converter has excellent power efficiency, applying the technology according to the present disclosure can contribute to reducing power consumption of the vehicle control system.

[0195] <Configurations that the present disclosure can take> The present disclosure may also be configured as follows.

[0196] A. Imaging device [A-01] A pixel array section in which pixels each including a photoelectric conversion element are arranged; a column amplifier section that calculates a difference between a reset component and a signal component input from each pixel of the pixel array section through a signal line, and outputs the difference as a pixel signal; A capacitance unit that holds a pixel signal input from the column amplifier unit; and a successive approximation type analog-to-digital conversion unit that converts an analog signal input from the capacitance unit into a digital signal; An imaging device comprising: [A-02] The column amplifier section is an amplifier having a non-inverting input terminal to which the potential of a signal line is input; a first switch having one end connected to the output terminal of the amplifier and the other end connected to the inverting input terminal of the amplifier; a second switch having one end connected to the output terminal of the amplifier; a first capacitance element having one end connected to the other end of the second switch and the other end connected to the other end of the first switch and the inverting input terminal of the amplifier; a second capacitance element connected between the other end of the first capacitance element and the inverting input terminal of the amplifier and a reference potential node; and a third switch, one end of which is connected to the other end of the second switch and one end of the first capacitive element, and the other end of which is connected to a local reference voltage; having The imaging device described in [A-01] above. [A-03] In the column amplifier section, When a reset component is input, the first switch is closed to charge the reset component to the first capacitance element and the second capacitance element, and the third switch is closed to retrieve a local reference voltage; Next, the first switch and the third switch are opened and the second switch is closed to form a non-inverting amplifier circuit using the first capacitance element, the second capacitance element, and the amplifier; When a signal component is input, feedback is applied so that the voltage of a common connection node between the first capacitance element and the second capacitance element becomes the same voltage as the signal component. The imaging device described in [A-02] above. [A-04] For one successive approximation type analog-to-digital converter of the successive approximation type analog-to-digital conversion unit, the potentials of the multiple signal lines are multiplexed and processed through multiple column amplifiers and capacitance units corresponding to the multiple signal lines. The imaging device according to any one of [A-01] to [A-03] above. [A-05] The successive approximation type analog-to-digital converter performs conversion processing only when a reset component is input, and waits for a signal component to be input. The imaging device described in [A-04] above. [A-06] The successive approximation type analog-to-digital converter performs conversion processing not only when a reset component is input, but also when a signal component is input. The imaging device described in [A-04] above. [A-07] The potential of multiple signal lines is divided into two systems of signal line potentials, The capacitance section has three capacitance elements, The three capacitive elements in the capacitance section are used equally for the potential of the two signal lines. The imaging device described in [A-06] above. [A-08] In a column signal processing system including a column amplifier section, a capacitance section, and a successive approximation type analog-to-digital conversion section, the capacitance section and subsequent sections are configured as differential circuits. The imaging device described in [A-06] above. [A-09] The column amplifier of the column amplifier section is composed of a current reuse column amplifier that uses the bias current of the signal line to amplify the voltage. The imaging device described in [A-08] above. [A-10] The capacitive section comprises a capacitive multiplexer; The imaging device according to any one of [A-01] to [A-09] above. [A-11] The capacitance unit holds the pixel signal by sampling using a switched capacitor. The imaging device according to [A-10] above.

[0197] ≪B.Electronic equipment≫ [B-01] A pixel array section in which pixels each including a photoelectric conversion element are arranged; a column amplifier section that calculates a difference between a reset component and a signal component input from each pixel of the pixel array section through a signal line, and outputs the difference as a pixel signal; A capacitance unit that holds a pixel signal input from the column amplifier unit; and a successive approximation type analog-to-digital conversion unit that converts an analog signal input from the capacitance unit into a digital signal; An electronic device having an imaging device comprising: [B-02] The column amplifier section is an amplifier having a non-inverting input terminal to which the potential of a signal line is input; a first switch having one end connected to the output terminal of the amplifier and the other end connected to the inverting input terminal of the amplifier; a second switch having one end connected to the output terminal of the amplifier; a first capacitance element having one end connected to the other end of the second switch and the other end connected to the other end of the first switch and the inverting input terminal of the amplifier; a second capacitance element connected between the other end of the first capacitance element and the inverting input terminal of the amplifier and a reference potential node; and a third switch, one end of which is connected to the other end of the second switch and one end of the first capacitive element, and the other end of which is connected to a local reference voltage; having The electronic device described in [B-01] above. [B-03] In the column amplifier section, When a reset component is input, the first switch is closed to charge the reset component to the first capacitance element and the second capacitance element, and the third switch is closed to retrieve a local reference voltage; Next, the first switch and the third switch are opened and the second switch is closed to form a non-inverting amplifier circuit using the first capacitance element, the second capacitance element, and the amplifier; When a signal component is input, feedback is applied so that the voltage of a common connection node between the first capacitance element and the second capacitance element becomes the same voltage as the signal component. The electronic device described in [B-02] above. [B-04] For one successive approximation type analog-to-digital converter of the successive approximation type analog-to-digital conversion unit, the potentials of the multiple signal lines are multiplexed and processed through multiple column amplifiers and capacitance units corresponding to the multiple signal lines. The electronic device according to any one of [B-01] to [B-03] above. [B-05] The successive approximation type analog-to-digital converter performs conversion processing only when a reset component is input, and waits for a signal component to be input. The electronic device described in [B-04] above. [B-06] The successive approximation type analog-to-digital converter performs conversion processing not only when a reset component is input, but also when a signal component is input. The electronic device described in [B-04] above. [B-07] The potential of multiple signal lines is divided into two systems of signal lines, The capacitance section has three capacitance elements, The three capacitive elements in the capacitance section are used equally for the potential of the two signal lines. The electronic device described in [B-06] above. [B-08] In a column signal processing system including a column amplifier section, a capacitance section, and a successive approximation type analog-to-digital conversion section, the capacitance section and subsequent sections are configured as differential circuits. The electronic device described in [B-06] above. [B-09] The column amplifier of the column amplifier section is composed of a current reuse column amplifier that uses the bias current of the signal line to amplify the voltage. The electronic device described in [B-08] above. [B-10] The capacitive section comprises a capacitive multiplexer; The electronic device according to any one of [B-01] to [B-09] above. [B-11] The capacitance unit holds the pixel signal by sampling using a switched capacitor. The electronic device described in [B-10] above. [Explanation of symbols]

[0198] 10 CMOS image sensor, 11 pixel array section, 12 row selection section, 13 constant current source section, 14 column amplifier section, 15 analog-digital conversion section, 15A successive approximation type analog-digital conversion section, 16 horizontal transfer scanning section, 17 signal processing section, 18 timing control section, 19 capacitance section, 20 pixel (pixel circuit), 21 photodiode (photoelectric conversion element), 22 transfer transistor, 23 reset transistor, 24 amplifying transistor, 25 selection transistor, 31 (311 to 31 m )···Pixel control line, 32 (321~32 n )···signal line, 50···indirect TOF range image sensor, 60···light source, 100···imaging system, 140···column amplifier, 150···successive approximation type analog-to-digital converter, 160···reference voltage generator, 190···capacitive multiplexer, 1400···current reuse column amplifier (CRCA), VR···local reference voltage, V CM Output common mode reference voltage

Claims

1. a pixel array section in which pixels each including a photoelectric conversion element are arranged; a column amplifier section that calculates a difference between a reset component and a signal component input from each pixel of the pixel array section through a signal line, and outputs the difference as a pixel signal; a capacitance unit for holding a pixel signal input from the column amplifier unit; and a successive approximation type analog-to-digital conversion unit that converts the analog signal input from the capacitance unit into a digital signal; Equipped with The column amplifier unit includes: an amplifier having a non-inverting input terminal to which the potential of the signal line is input; a first switch having one end connected to the output terminal of the amplifier and the other end connected to the inverting input terminal of the amplifier; a second switch having one end connected to the output terminal of the amplifier; a first capacitance element having one end connected to the other end of the second switch and the other end connected to the other end of the first switch and the inverting input terminal of the amplifier; a second capacitance element connected between the other end of the first capacitance element and the inverting input terminal of the amplifier and a reference potential node; and an imaging device comprising: a third switch having one end connected to the other end of the second switch and one end of the first capacitive element, and having the other end to which a local reference voltage is applied;

2. In the column amplifier section, When a reset component is input, the first switch is closed to charge the reset component to the first capacitance element and the second capacitance element, and the third switch is closed to receive a local reference voltage. Next, the first switch and the third switch are opened and the second switch is closed to form a non-inverting amplifier circuit using the first capacitance element, the second capacitance element, and the amplifier; When a signal component is input, feedback is applied so that the voltage of a common connection node between the first capacitance element and the second capacitance element becomes the same voltage as the signal component. The imaging device according to claim 1 .

3. The column amplifier unit has a plurality of column amplifiers, the successive approximation type analog-to-digital conversion unit multiplexes and processes the potentials of the plurality of signal lines through the plurality of column amplifiers and the capacitance unit corresponding to the plurality of signal lines; The imaging device according to claim 1 .

4. The successive approximation type analog-to-digital conversion unit performs conversion processing only when a reset component is input, and waits for a signal component to be input. The imaging device according to claim 3 .

5. The successive approximation type analog-to-digital conversion unit performs conversion processing not only when a reset component is input but also when a signal component is input. The imaging device according to claim 3 .

6. The potentials of the plurality of signal lines are divided into two systems of potentials of the signal lines, The capacitance section has three capacitance elements, The three capacitance elements of the capacitance unit are used equally for the potentials of the two signal lines. The imaging device according to claim 5 .

7. In a column signal processing system including the column amplifier unit, the capacitance unit, and the successive approximation type analog-to-digital conversion unit, the capacitance unit and subsequent units are configured as differential circuits. The imaging device according to claim 5 .

8. The column amplifier is a current reuse column amplifier that performs voltage amplification by utilizing a bias current of the signal line. The imaging device according to claim 7.

9. The capacitive section comprises a capacitive multiplexer. The imaging device according to claim 1 .

10. The capacitance unit holds pixel signals by sampling using a switched capacitor. The imaging device according to claim 9.

11. a pixel array section in which pixels each including a photoelectric conversion element are arranged; a column amplifier section that calculates a difference between a reset component and a signal component input from each pixel of the pixel array section through a signal line, and outputs the difference as a pixel signal; a capacitance unit for holding a pixel signal input from the column amplifier unit; and a successive approximation type analog-to-digital conversion unit that converts the analog signal input from the capacitance unit into a digital signal; Equipped with The column amplifier unit includes: an amplifier having a non-inverting input terminal to which the potential of the signal line is input; a first switch having one end connected to the output terminal of the amplifier and the other end connected to the inverting input terminal of the amplifier; a second switch having one end connected to the output terminal of the amplifier; a first capacitance element having one end connected to the other end of the second switch and the other end connected to the other end of the first switch and the inverting input terminal of the amplifier; a second capacitance element connected between the other end of the first capacitance element and the inverting input terminal of the amplifier and a reference potential node; and a third switch having one end connected to the other end of the second switch and one end of the first capacitive element and having the other end to which a local reference voltage is applied; An electronic device having

Images