Semiconductor device and its manufacturing method

Abstract

To provide a semiconductor device capable of improving a total performance, and provide a manufacturing method of them.SOLUTION: A semiconductor device contains: a substrate 110 containing a first region 1 and a second region 2; a shallow trench isolation structure 150 that is provided into the first region 1 and the second region 2, and becomes lower from a front surface of the substrate, and forms an open; a dielectric layer 180 that is provided into the open and on the substrate, and in which the height in the second region is larger than that in the first region; a gate 22 provided onto the dielectric layer; and a drain 23 that is provided onto the substrate, and is provided to a source 21 and the substrate positioned at one side of the gate, and is positioned on the other side of the gate.SELECTED DRAWING: Figure 18

Description

[Technical field]

[0001] The present invention relates to the field of semiconductor technology, and more particularly to semiconductor devices and methods for manufacturing the same. [Background technology]

[0002] With the continuous increase in the integration degree of semiconductor devices, miniaturization of semiconductor devices has become a general trend of semiconductor devices. In addition, multiple types of devices must be integrated and manufactured, for example, different types of transistors are fabricated on the same substrate and the different transistors are isolated by shallow trench isolation structures. However, as the size of the transistor becomes smaller, the transistor is more susceptible to many problems, such as gate leakage current, boron penetration effect, and depressions appearing in the shallow trench isolation structures at the edge of the transistor, which leads to the degradation of the electrical performance of the transistor and the reduction of the effectiveness of the semiconductor device.

[0003] Therefore, how to obtain high performance semiconductor devices has become an issue that needs to be solved immediately. Summary of the Invention [Problem to be solved by the invention]

[0004] An object of the present invention is to provide a semiconductor device and a method for manufacturing the same, which can improve the overall performance of the semiconductor device. [Means for solving the problem]

[0005] In order to solve the above technical problems, the present invention is realized by the following technical solutions.

[0006] The present invention provides a semiconductor device including at least a substrate including a first region and a second region, a shallow trench isolation structure provided in the first region and the second region and lower than a surface of the substrate to form an opening, a dielectric layer provided in the opening and on the substrate and having a height in the second region greater than its height in the first region, a gate provided on the dielectric layer, a source provided on the substrate and located on one side of the gate, and a drain provided on the substrate and located on the other side of the gate.

[0007] In one embodiment of the present invention, the shallow trench isolation structure is 10 to 30 nm lower than the surface of the substrate.

[0008] In one embodiment of the present invention, the semiconductor device includes sidewall structures located on both sides of the gate and on the dielectric layer.

[0009] In one embodiment of the present invention, the sidewall structure is a single insulating layer or a laminated structure of an insulating layer and a stress layer.

[0010] In one embodiment of the present invention, the semiconductor device includes a passivation layer, and the passivation layer is disposed on the gate, the sidewall structure and the dielectric layer.

[0011] In one embodiment of the present invention, the gate comprises a first metal gate, and stress regions are provided in the substrate on either side of the first metal gate.

[0012] In one embodiment of the present invention, the stress region extends toward a bottom of the first metal gate and extends to a connection between the sidewall structure and the first metal gate.

[0013] In one embodiment of the present invention, the gate comprises a second metal gate, and lightly doped regions are provided in the substrate on both sides of the second metal gate.

[0014] In one embodiment of the present invention, the thickness of the dielectric layer in the first region is 2 to 5 nm, and the thickness of the dielectric layer in the second region is 4 to 8 nm.

[0015] In one embodiment of the present invention, the gate is a single-layer metal, a multi-layer metal, or a laminated structure of metal and metal compound.

[0016] The present invention provides a method for manufacturing a semiconductor device, comprising: providing a substrate, the substrate including a first region and a second region; forming a plurality of shallow trench isolation structures on the first region and the second region; removing a pad oxide layer on the substrate by extending an etching time to remove a portion of the shallow trench isolation structures, forming an opening on the shallow trench isolation structures that is lower than a surface of the substrate; forming a dielectric layer in the opening and on the substrate, the dielectric layer having a height in the second region greater than a height in the first region; forming a gate on the dielectric layer; forming a source on the substrate, the source being located on one side of the gate; and forming a drain on the substrate, the drain being located on the other side of the gate. Effect of the Invention

[0017] The semiconductor device and the manufacturing method thereof provided by the present invention can reduce the recess phenomenon at the edge of the shallow trench isolation structure, thereby improving the electrical performance of the semiconductor device. In addition, the number of photomasks is not added during the manufacturing process, which simplifies the manufacturing flow and reduces costs. In addition, the effective channel width of the semiconductor device can be increased, thereby enhancing the performance of the semiconductor device. As described above, the semiconductor device and the manufacturing method thereof provided by the present invention can improve the performance of the semiconductor device.

[0018] Of course, any product embodying the present invention need not necessarily achieve all of the advantages discussed above simultaneously.

[0019] In order to more clearly describe the technical solutions of the embodiments of the present invention, the drawings that need to be used in the description of the embodiments are briefly described below. It should be noted that the drawings described below are only some of the embodiments of the present invention, and those skilled in the art can obtain other drawings from these drawings without requiring creative labor. [Brief description of the drawings]

[0020] [Figure 1] FIG. 1 is a schematic diagram of the distribution of a substrate in one embodiment. [Diagram 2] FIG. 2 is a schematic diagram of a shallow trench isolation structure in one embodiment. [Diagram 3] FIG. 3 is a schematic diagram of well distribution in one embodiment. [Figure 4] FIG. 4 is a schematic diagram of an aperture in one embodiment. [Diagram 5] FIG. 5 is a schematic diagram of a dielectric layer in one embodiment. [Figure 6] FIG. 6 is a schematic diagram of a dummy gate in one embodiment. [Figure 7] FIG. 7 is a schematic diagram of a sidewall structure in one embodiment. [Figure 8] FIG. 8 is a schematic structural diagram of a low concentration impurity region in one embodiment. [Figure 9] FIG. 9 is a schematic diagram of the formation of stress regions in one embodiment. [Figure 10] FIG. 10 is a schematic diagram of the formation of stress regions in one embodiment. [Figure 11] FIG. 11 is a schematic diagram of the formation of stressed regions in one embodiment. [Figure 12] FIG. 12 is a schematic diagram of a self-aligned silicide barrier layer in one embodiment. [Figure 13]FIG. 13 is a schematic diagram of polysilicon layer removal in one embodiment. [Figure 14] FIG. 14 is a schematic diagram of a metal gate in one embodiment. [Figure 15] FIG. 15 is a schematic structural diagram of a first metal gate on a substrate in one embodiment. [Figure 16] FIG. 16 is a schematic structural diagram of a second metal gate on a substrate in one embodiment. [Figure 17] FIG. 17 is a schematic diagram of a passivation layer in one embodiment. [Figure 18] FIG. 18 is a schematic diagram of a semiconductor device having PMOS and NMOS transistors in one embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0021] Hereinafter, the embodiments of the present invention will be described with reference to specific examples. Those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. Furthermore, the present invention can be implemented or applied in other different specific embodiments. In addition, each detail in this specification may be supplemented or modified in various ways based on different perspectives and applications without departing from the spirit of the present invention.

[0022] It should be noted that the drawings provided in this embodiment are only for the purpose of roughly explaining the basic idea of ​​the present invention. The drawings only show assemblies related to the present invention, and are not based on the number, shape and size of the assemblies in actual implementation. The form, quantity and ratio of each assembly in actual implementation may be arbitrarily changed, and the layout and shape of the assemblies may be more complicated.

[0023] In the present invention, when terms such as "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", and "outer" are used as points to be explained, the directions or positional relationships shown are based on the drawings, and are merely for the convenience and simplification of the description of this application, and do not expressly or imply that the target device or member has a specific direction and must be constructed and operated in a specific direction. Therefore, they should not be construed as limiting the present application. In addition, when terms such as "first" and "second" are used, they are merely for the purpose of description and distinction, and should not be construed as expressing or implying relative importance.

[0024] The present invention provides a semiconductor device and a method for manufacturing the same, which allows semiconductor devices with different functions to be fabricated in different regions of the same substrate, and each semiconductor device has excellent performance. The method for manufacturing the semiconductor device provided by the present invention can be widely applied to the manufacturing processes of various fine semiconductor devices.

[0025] Referring to FIG. 1, in one embodiment of the present invention, a substrate 110 includes, for example, a first region 1 and a second region 2. In addition, a plurality of metal-oxide-semiconductor field-effect transistors (Metal-Oxide-Semiconductor Field-Effect Transistors, MOS), including, for example, a P-type metal-oxide-semiconductor field-effect transistor (Positive Channel Metal Oxide Semiconductor, PMOS) and an N-type metal-oxide-semiconductor field-effect transistor (Negative Channel Metal Oxide Semiconductor, NMOS), can be disposed in the first region 1 and the second region 2. In addition, the PMOS transistors and the NMOS transistors are arranged alternately. By fabricating semiconductor devices in different regions of the same substrate, production efficiency is improved and production costs are reduced.

[0026] Referring to FIG. 1, in one embodiment of the present invention, a substrate 110 is provided first. The substrate 110 can be any material suitable for formation (for example, silicon wafer, germanium substrate, silicon germanium, SOI (Silicon on Insulator) or SSOI (Stacked Silicon on Insulator), etc.). The present invention does not particularly limit the type and thickness of the substrate 110. In this embodiment, for example, a silicon wafer is selected as the substrate 110 for detailed description. For example, the substrate 110 is a P-type silicon wafer. The substrate 110 includes, for example, a first region 1 and a second region 2. For example, a Core MOS, which is used inside the device and generally has a low operating voltage, is provided in the first region 1. For example, a peripheral metal oxide semiconductor field effect transistor (i.e., an IO MOS transistor) corresponding to the Core MOS transistor is provided in the second region 2. The IO MOS transistor is generally used for interaction between the chip and the external interface, and has a higher operating voltage than the operating voltage of the Core MOS transistor. In this embodiment, the first region 1 includes one PMOS transistor and one NMOS transistor, and the second region 2 includes one PMOS transistor and one NMOS transistor. The PMOS transistors and the NMOS transistors are alternately distributed. The PMOS transistor and the NMOS transistor are separated from each other by a shallow trench isolation structure.

[0027] Referring to FIG. 1, in one embodiment of the present invention, a plurality of shallow trench isolation structures are formed on a substrate 110. Specifically, a pad oxide layer 120 is formed on the substrate 110. The pad oxide layer 120 is made of a material such as dense silicon oxide. The pad oxide layer 120 can be formed by a method such as thermal oxidation, in-situ steam generation, or chemical vapor deposition (CVD). A pad nitride layer 130 is formed on the pad oxide layer 120. The pad nitride layer 130 is made of a material such as silicon nitride or a mixture of silicon nitride and silicon oxide. The pad nitride layer 130 can be formed by a method such as chemical vapor deposition. In the process of forming the shallow trench isolation structure, the pad oxide layer 120 can improve the stress between the substrate 110 and the pad oxide layer 120, and can also protect the substrate 110 when forming a well by ion implantation, thereby preventing damage to the substrate 110 caused by high-energy ions. In addition, a patterned photoresist layer 140 is formed on the pad nitride layer 130, and a number of first recesses 141 are provided on the patterned photoresist layer 140. The first recesses 141 are used to define the positions of the shallow trench isolation structures, and the first recesses 141 expose the pad nitride layer 130.

[0028] 1 and 2, in one embodiment of the present invention, after forming a patterned photoresist layer 140, etching is performed in the direction of the substrate 110 by, for example, dry etching using the patterned photoresist layer 140 as a mask to form a shallow trench. The etching gas may be, for example, one or a mixture of chlorine (Cl2), fluoroform (CHF3), difluoromethane (CH2F2), nitrogen trifluoride (NF3), sulfur hexafluoride (SF6), hydrogen bromide (HBr), and the like. A lining oxide layer (not shown) is formed in the shallow trench by, for example, a thermal oxidation method. This repairs etching damage caused during the formation of the shallow trench, and reduces leakage current of the semiconductor device. An isolation dielectric is deposited in the shallow trench by, for example, a method such as high density plasma CVD (HDP-CVD) or high aspect ratio chemical vapor deposition (HARP-CVD). After the deposition of the isolation dielectric is completed, the isolation dielectric and the pad nitride layer 130 are planarized by, for example, a chemical mechanical polishing (CMP) process to form the shallow trench isolation structure 150. The shallow trench isolation structure 150 and the pad oxide layers 120 on both sides are flush with each other.

[0029] Referring to FIG. 3, in one embodiment of the present invention, after the shallow trench isolation structure 150 is fabricated, different wells are formed by ion implantation into the substrate 110. First, doping ions with a higher concentration than that of the substrate 110 are implanted with high implantation energy. That is, a first well 160 is formed in the substrate 110. Also, a second well 170 is formed in a region for forming an NMOS transistor by implanting doping ions with a higher concentration than that of the first well 160 with high implantation energy. Also, the second well 170 is located on a part of the first well 160. In this embodiment, the first well 160 and the second well 170 are of different types. For example, the first well 160 is an N-type deep well, and the doping ions are phosphorus (P), arsenic (As), aluminum (Al), or the like. Also, for example, the second well 170 is a P-type deep well, and the doping ions are boron (B), gallium (Ga), or the like. After the first well 160 and the second well 170 are formed, a rapid thermal annealing process (RTA) is performed on the first well 160 and the second well 170. In this embodiment, the annealing temperature is, for example, 1000 to 1400°C, and the annealing time is, for example, 1 to 3 hours. The annealing process is performed in a stable gas atmosphere, for example, in a nitrogen gas atmosphere. The annealing process implants ions into the first well 160 and the second well 170 to an appropriate depth and improves the avalanche breakdown resistance of the semiconductor device.

[0030] 3-4, in one embodiment of the present invention, after the first well 160 and the second well 170 are formed, the pad oxide layer 120 is removed. In this embodiment, the pad oxide layer 120 is removed by, for example, wet etching. For example, hydrofluoric acid is selected as the wet etching solution, and etching is performed at room temperature. In other embodiments, other etching methods may be adopted and may be selected according to specific manufacturing requirements. When removing the pad oxide layer 120, the etching time is extended to remove the isolation dielectric in a part of the shallow trench isolation structure 150, and the opening 11 is formed. For example, the depth of the opening 11 is 10-30 nm. That is, the lower surface of the opening 11 after etching is lower than the surface of the substrate 110 on both sides, and the height difference is, for example, 10-30 nm. By providing the opening 11, it is possible to avoid a situation in which a recess is formed at the edge of the shallow trench isolation structure 150 when the pad oxide layer 120 is removed, so that the occurrence of leakage current is reduced and the electrical performance of the semiconductor device is improved. Moreover, by removing the pad oxide layer 120 and forming the opening 11 in the same process, the number of photomasks remains the same and the photoresist and etching steps are not increased, thus reducing costs.

[0031] 5 and 15, in one embodiment of the present invention, after the opening 11 is formed, a material with a high dielectric constant is deposited in the opening 11 and on the substrate 110 to form a dielectric layer 180 as a gate dielectric layer of a semiconductor device. In this embodiment, the dielectric layer 180 can be formed by a method such as atomic layer deposition (ALD), metal-organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), chemical vapor deposition, or physical vapor deposition (PVD). The dielectric layer 180 is made of one or a mixture of several materials selected from hafnium oxide (HfO2), hafnium oxynitride (HfON), zirconia (ZrO2), zirconium oxynitride (ZrON), zirconium oxynitride silicate (ZrSiON), hafnium silicate (HfSiO), hafnium nitride silicate (HfSiON), hafnium lanthanum oxynitride (HfLaON), and hafnium aluminate (HfAlO). Since a dielectric material with a high dielectric constant is selected for the dielectric layer 180, the interface quality with the substrate 110 is poor. Therefore, before depositing the dielectric layer 180, an interface layer 111 is formed on the substrate 110 and on the sidewall of the opening 11 by, for example, in-situ steam generation (ISSG). In addition, in order to improve the interface quality between the dielectric layer 180 and the substrate 110, the thickness of the interface layer 111 is, for example, 0.5 to 1.5 nm. After the deposition of the dielectric layer 180 is completed, a planarization process is performed on the dielectric layer 180. Since the operating voltage of the transistor in the second region 2 is high, the residual thickness of the dielectric layer 180 is different in the first region 1 and the second region 2. In this embodiment, the thickness of the dielectric layer 180 on the well in the first region 1 is, for example, 2 to 5 nm, and the thickness of the dielectric layer 180 on the well in the second region 2 is, for example, 4 to 8 nm. This can improve the voltage resistance of the transistor in the second region 2. By providing the opening 11 and the dielectric layer 180, the effective channel width of the transistor in the subsequent process is increased, improving the performance of the device and reducing the leakage current phenomenon.

[0032] Referring to FIG. 6, in one embodiment of the present invention, after forming the dielectric layer 180, a dummy gate 190 is formed on the dielectric layer 180. Specifically, a protective layer 191, a polysilicon layer 192, a shielding layer 193, and an anti-reflection layer 194 are sequentially formed on the dielectric layer 180. In this embodiment, for example, the protective layer 191 is titanium nitride or the like. And, for example, the protective layer 191 is formed by atomic layer deposition (ALD). By providing the protective layer 191, it is possible to prevent contamination or damage of the dielectric layer 180 in the subsequent manufacturing process, so that the performance of the metal gate to be fabricated later can be improved. The polysilicon layer 192 is, for example, an N-type doped polysilicon layer. This allows the removal rate of the polysilicon layer 192 to be improved in the subsequent manufacturing process. The shielding layer 193 is, for example, one or more types of silicon nitride, titanium nitride, silicon carbonitride, or the like. Also, for example, the anti-reflective layer 194 is a reflective material such as silicon oxynitride. In this way, the structural integrity of the dummy gate 190 can be reliably guaranteed during the formation of the dummy gate 190. After forming a patterned photoresist layer (not shown) on the anti-reflective layer 194, the anti-reflective layer 194, the shielding layer 193, the polysilicon layer 192 and the protective layer 191 are etched. The dielectric layer 180 is used as an etching stop layer. A stacked columnar structure is formed on the dielectric layer 180, and the shielding layer 193 and the anti-reflective layer 194 are removed to form the dummy gate 190 on the dielectric layer 180. The dummy gate 190 is located on the first well 160 and the second well 170.

[0033] Referring to FIG. 7, in one embodiment of the present invention, after forming the dummy gate 190, the sidewall structure 200 is formed on both sides of the dummy gate 190. That is, the sidewall structure 200 is formed on the side of the dummy gate 190. And the sidewall structure 200 is located on the dielectric layer 180. The edge of the sidewall structure 200 overlaps with the edge of the dielectric layer 180 located below the dummy gate 190. In this embodiment, the sidewall structure 200 has a stacked structure. The sidewall structure 200 includes, for example, a first insulating layer 201, a first stress layer 202, a second insulating layer 203, and a second stress layer 204. The insulating layer is, for example, silicon oxide, and the stress layer is, for example, silicon nitride. That is, the sidewall structure 200 is a stacked structure of a silicon oxide layer / silicon nitride layer. The stress layer can ensure the stability of the sidewall structure during the removal of the dummy gate 190 and reduce unevenness in the gate deposition in the subsequent process caused by the inward tilt of the sidewall structure. This improves the uniformity of the gate structure, thereby improving the stability of the threshold voltage of the semiconductor structure. In other embodiments, the sidewall structure 200 can be a single insulating layer or other structure. It is noted that the loss of the sidewall structure in the subsequent manufacturing process is reduced by making the sidewall structure a multi-layer structure.

[0034] 8 and 9, in one embodiment of the present invention, after forming the sidewall structure 200, a low-concentration impurity region 210 is formed in the second well 170. The low-concentration impurity region 210 is located between the sidewall structure 200 and the shallow trench isolation structure 150 and is adjacent to the sidewall structure 200 and the shallow trench isolation structure 150. This improves the short channel effect of the transistor to be formed. Specifically, doping ions are implanted with low implantation energy. Thus, the low-concentration impurity region 210 is located on the side of the second well 170 close to the dielectric layer 180. The implanted doping ions are, for example, N-type ions such as phosphorus, arsenic, or aluminum. The low-concentration impurity region 210 can be a source or drain region of an NMOS transistor. After forming the low-concentration impurity region 210, the dielectric layer 180 on the shallow trench isolation structure 150, the first well 160, and the second well 170 is removed, and the dielectric layer 180 in the region covered by the dummy gate 190 and the sidewall structure 200 is left. In addition, the dielectric layer 180 in the opening 11 is left, and the dielectric layer 180 in the opening 11 and the substrate 110 are made flush with each other. In this embodiment, the dielectric layer 180 can be removed by dry etching, wet etching, or a combination of dry etching and wet etching. By removing the dielectric layer 180 after forming the low-concentration impurity region 210, damage to the second well 170 during the formation of the low-concentration impurity region 210 can be prevented. This improves the performance of the semiconductor device.

[0035] 10-11, in one embodiment of the present invention, after removing the dielectric layer 180, a groove 12 is formed on the first well 160. The groove 12 is located between the sidewall structure 200 and the shallow trench isolation structure 150, and is adjacent to the sidewall structure 200 and the shallow trench isolation structure 150. Specifically, a patterned photoresist layer (not shown) is formed on the substrate 110, and the substrate 110 on both sides of the sidewall structure 200 on the first well 160 is dry-etched or wet-etched to form the groove 12. In this embodiment, the sidewall of the groove 12 is formed to form an open polygon, so that the contact area between the stress region 220 to be deposited later and the channel region of the transistor can be enlarged. This improves the effect of the stress on the channel region, thereby improving the mobility in the channel region. A semiconductor material is deposited in the groove 12 to form the stress region 220. The stress region 220 can be a source region or a drain region of a PMOS transistor. In this embodiment, for example, the stress region 220 is silicon germanium (SiGe). The SiGe is SiGe doped with P-type impurities. The shape of the stress region 220 is the same as that of the groove 12, and is, for example, polygonal. One side of the polygon is adjacent to the shallow trench isolation structure 150. The stress region 220 extends toward the bottom of the dummy gate 190 and also extends to the connection between the sidewall structure 200 and the dummy gate 190. By providing the stress region 220 to extend to the connection between the sidewall structure 200 and the dummy gate 190, it is possible to avoid the leakage current phenomenon that occurs when the stress region 220 extends to the bottom of the dummy gate 190. If the stress region 220 does not extend to the connection between the sidewall structure 200 and the dummy gate 190, the width of the channel region between the stress regions 220 increases, and the carrier mobility decreases, which affects the performance of the semiconductor device. Therefore, the electrical performance of the semiconductor device can be optimized by extending the stress region 220 to the connection between the sidewall structure 200 and the dummy gate 190. In this embodiment, the stress region 220 is fabricated by, for example, depositing using a low temperature epitaxial process.In addition, the externally supplied gases used in the low-temperature epitaxial process include germanium source gas, silicon source gas, hydrogen chloride gas, and hydrogen gas. The ratio of germanium in the stress region 220 is adjusted by adjusting the ratio of the germanium source gas and the silicon source gas. The ratio of germanium in the stress region 220 is, for example, 20 to 40%. By controlling the germanium content, the lattice constant difference between the stress region 220 and the inner wall of the groove 12 can be reduced, so that defects in the stress region 220 are reduced. After the stress region 220 is formed, the low-concentration impurity region 210 and the stress region 220 are activated. For example, rapid thermal annealing is performed on the substrate 110. The rapid thermal annealing optimizes the repair of lattice defects generated during the manufacturing process, the activation of doping ions, and the minimization of doping ion diffusion, thereby activating the stress layer and the low-concentration impurity region. The rapid thermal annealing also reduces transient enhanced diffusion.

[0036] Referring to FIG. 12, in one embodiment of the present invention, a self-aligned silicide barrier layer (Self-Aligned Block, SAB) 230 is formed on the dummy gate 190, the low concentration impurity region 210, and the stress region 220. Specifically, a metal layer (not shown) is formed on the dielectric layer 180, the dummy gate 190, the low concentration impurity region 210, and the stress region 220. The metal layer is, for example, a titanium layer (Ti), a cobalt layer (Co), or a nickel layer (Ni). Then, a primary annealing is performed on the substrate 110. For example, the temperature of the primary annealing is 300 to 350° C. As a result, the metal atoms react with the silicon atoms in the dummy gate 190, the low concentration impurity region 210, or the stress region 220 to form an intermediate silicide layer. Then, the unreacted metal layer is selectively removed by a chemical solution, and the intermediate silicide layer is subjected to a secondary annealing. The temperature of the secondary annealing is higher than the temperature of the primary annealing. For example, the temperature of the secondary annealing is 400-500° C. After annealing, the intermediate silicide layer is transformed into a silicide layer, i.e., a self-aligned silicide barrier layer 230. The self-aligned silicide barrier layer 230 has good thermal stability and can reduce the electrical resistance of the device, thereby ensuring good contact with the metal electrodes to be fabricated later.

[0037] 6 and 13, in one embodiment of the present invention, after forming the self-aligned silicide barrier layer 230, the self-aligned silicide barrier layer 230 on the ceiling of the dummy gate 190 and the polysilicon layer 192 in the dummy gate 190 are removed, and the protective layer 191 in the dummy gate 190 is left to form the groove 13. That is, the protective layer 191 is exposed in the groove 13. When removing the polysilicon layer 192, dry etching, wet etching, or a combination of dry etching and wet etching can be adopted. When adopting dry etching, chlorine gas, bromine gas, helium gas, hydrogen bromide, or a mixed gas of at least one of these gases and oxygen gas can be selected. Dry etching has excellent anisotropy and selectivity, and has high etching efficiency. When adopting wet etching, the polysilicon layer 192 can be removed by selecting a tetramethylammonium hydroxide solution or a potassium hydroxide solution. When adopting wet etching, there are advantages in that the operation is easy, the requirements for equipment are low, and mass production is easy. During the etching process, the sidewall structure 200 is left behind to be used for positioning the metal gate and to serve as the sidewall structure of the metal gate to be fabricated later.

[0038] 14 to 16, in one embodiment of the present invention, after forming the groove 13, a metal is deposited in the groove 13 to form a metal gate 260. The metal gate 260 has a structure such as a single-layer metal, a multi-layer metal, or a laminate of metal compounds. The metal gate 260 includes a first metal gate 240 and a second metal gate 250. The first metal gate 240 is a metal gate of a PMOS transistor, and the second metal gate 250 is a metal gate of an NMOS transistor.

[0039] Please refer to FIG. 14 to FIG. 15. In one embodiment of the present invention, FIG. 15 is a schematic structural diagram of a first metal gate 240 on a substrate 110. The first metal gate 240 includes a dielectric layer 180, a protection layer 191, a first barrier layer 241, a first work function metal layer 242, and a first metal conductive layer 243. The dielectric layer 180 is a dielectric layer with a high dielectric constant. The protection layer 191 is formed in the process of forming the dummy gate to reduce damage to the dielectric layer 180. The first barrier layer 241 is formed on the protection layer 191. The material of the first barrier layer 241 can be a metal compound such as titanium nitride (TiN) or tantalum nitride (TaN) or a laminate thereof. In this embodiment, the first barrier layer 241 includes a titanium nitride layer or a tantalum nitride layer. The tantalum nitride layer is provided on the protection layer 191, and the titanium nitride layer is provided on the tantalum nitride layer. The first barrier layer 241 can be formed by atomic layer deposition, physical vapor deposition, or chemical vapor deposition. The first work function metal layer 242 is provided on the first barrier layer 241. For example, the first work function metal layer 242 is a P-type work function metal layer, and the material can be one or a stack of tantalum nitride, titanium nitride, titanium aluminide (TiAl), titanium aluminum nitride (TiAlN), or tungsten nitride (WN). In this embodiment, for example, the first work function metal layer 242 is a stack of a titanium aluminide layer and a titanium nitride layer. The titanium aluminide layer is provided on the first barrier layer 241, and the titanium nitride is provided on the titanium aluminide layer. The first work function metal layer 242 is formed by plasma enhanced chemical vapor deposition (PECVD), atomic layer deposition, or physical vapor deposition. In addition, a first conductive metal layer 243 is formed on the first work function metal layer 242. The first conductive metal layer 243 is made of a metal having good conductivity, such as metal tungsten, copper, or silver, to improve the electrical performance of the transistor. The first conductive metal layer 243 is formed by a method such as magnetron sputtering or deposition. After the first conductive metal layer 243 is formed, a planarization process is performed to improve the planarity of the first conductive metal layer 243.

[0040] Please refer to FIG. 14 and FIG. 16. In one embodiment of the present invention, FIG. 16 is a schematic structural diagram of a second metal gate 250 on a substrate 110. The second metal gate 250 includes a dielectric layer 180, a protection layer 191, a second barrier layer 251, a second work function metal layer 252 and a second metal conductive layer 253. The dielectric layer 180 is a dielectric layer with a high dielectric constant. The protection layer 191 is formed during the formation of the dummy gate to reduce damage to the dielectric layer 180. The second barrier layer 251 is formed on the protection layer 191. The material of the second barrier layer 251 can be a metal compound such as titanium nitride or tantalum nitride or a laminate thereof. In this embodiment, for example, the second barrier layer 251 is a tantalum nitride layer. And the second barrier layer 251 can be formed by a method such as atomic layer deposition, physical vapor deposition or chemical vapor deposition. The second work function metal layer 252 is provided on the second barrier layer 251. For example, the second work function metal layer 252 is an N-type work function metal layer, and the material can be one or a stack of tantalum nitride, titanium nitride, titanium aluminide, titanium aluminum nitride, tungsten nitride, etc. In this embodiment, for example, the second work function metal layer 252 is a stack of a titanium aluminide layer and a titanium nitride layer. The titanium aluminide layer is disposed on the second barrier layer 251, and the titanium nitride is disposed on the titanium aluminide layer. The second work function metal layer 252 is formed by a method such as plasma enhanced chemical vapor deposition, atomic layer deposition, or physical vapor deposition. A second metal conductive layer 253 is formed on the second work function metal layer 252. The second metal conductive layer 253 is a metal with good conductivity, such as metal tungsten, copper, or silver, which improves the electrical performance of the transistor. The second metal conductive layer 253 is formed by a method such as magnetron sputtering or evaporation. After forming the second metal conductive layer 253, a planarization process is performed to improve the planarity of the second metal conductive layer 253. In this embodiment, the metal conductive layers in the metal gates of the NMOS transistor and the PMOS transistor can be connected or separated from each other, which can be adjusted according to the actual production. In addition, when the metal conductive layers are connected, the height of the metal conductive layer above the shallow trench isolation structure 150 is smaller than the height of the metal conductive layer above the substrate 110.The height of the metal conductive layer on the shallow trench isolation structure 150 is lower than the height on the substrate 110, and the height difference is, for example, 5 nm or more.

[0041] 17, in one embodiment of the present invention, after forming the metal gate 260, a passivation layer 270 is formed on the side of the substrate 110 adjacent to the metal gate 260. That is, the passivation layer 270 covers the metal gate 260, the dielectric layer 180, the self-aligned silicide barrier layer 230, and the sidewall structure 200. The passivation layer 270 has a second recess 14 on the position of the metal gate 260 and the self-aligned silicide barrier layer 230, which exposes the metal gate 260 and the self-aligned silicide barrier layer 230 for positioning and connecting the metal electrode. In this embodiment, the passivation layer 270 is an insulating material such as silicon oxide or titanium oxide, which protects the device and improves the voltage resistance of the device. By providing the passivation layer 270, the service life of the device and the performance of the device can be improved.

[0042] 17-18, in one embodiment of the present invention, an insulating layer 280 is formed on the substrate 110. The insulating layer covers the entire surface of the substrate 110. For example, the insulating layer 280 is a silicon oxide layer. After the insulating layer 280 is formed, a planarization process is performed and a plurality of passages are formed on the insulating layer 280. The passages are located on the second recess 14. The passages expose the metal gate 260 and the self-aligned silicide barrier layer 230. Metal connection lines made of a metal such as tungsten, copper or silver are provided in the passages to form electrodes. The electrodes include a source 21, a gate 22 and a drain 23. The source 21 is located on one side of the metal gate 260 and is connected to the self-aligned silicide barrier layer 230. The gate 22 is provided on the metal gate 260 and is connected to the metal conductive layer of the metal gate 260. The drain 23 is provided on the other side of the metal gate 260 and is connected to the self-aligned silicide barrier layer 230.

[0043] As described above, the present invention provides a semiconductor device and a method for manufacturing the same, in which a dielectric layer is formed before forming a dummy gate, thereby improving the electrical performance of the semiconductor device, and increasing the effective channel width of the semiconductor device, thereby enhancing the performance of the semiconductor device, and improving the performance of semiconductor devices with different functions on the same substrate, thereby obtaining a high quality semiconductor device.

[0044] The above disclosed examples of the present invention are merely to assist in the detailed description of the present invention. The examples do not describe all the details, and do not limit the present invention to only the specific embodiments described above. Needless to say, many modifications and variations can be made based on the contents of this specification. The above examples are selected and specifically described in this specification in order to more clearly explain the principles and practical applications of the present invention, so that those skilled in the art can better understand and use the present invention. The present invention is limited only by the claims and their full scope and equivalents. [Explanation of symbols]

[0045] 110 Substrate 120 Pad Oxide Layer 130 Pad nitride layer 140 Patterning photoresist layer 141 First recess 150 Shallow trench isolation structure 160 First well 170 Second Well 180 Dielectric layer 190 Dummy Gate 191 Protective layer 192 Polysilicon layer 193 Shielding layer 194 Anti-reflection layer 200 side wall structure 201 First insulating layer 202 First stress layer 203 Second insulating layer 204 Second Stress Layer 210 Low concentration impurity region 220 Stress Area 230 Self-Aligned Silicide Barrier Layer 240 1st Metal Gate 241 First Barrier Layer 242 First work function metal layer 243 First metal conductive layer 250 Second Metal Gate 251 Second Barrier Layer 252 Second work function metal layer 253 Second metal conductive layer 260 Metal Gate 270 Passivation Layer 280 Insulating Layer 11 Aperture 12 Groove 13 Groove 14 Second recess 21 Source 22 Gate 23 Drain

Claims

1. A substrate including a first region and a second region; a shallow trench isolation structure provided in the first region and the second region and lowered below a surface of the substrate to form an opening; a dielectric layer disposed in the opening and on the substrate, the dielectric layer having a height in the second region greater than a height in the first region; a gate disposed on the dielectric layer; a source disposed on the substrate and located on one side of the gate; and a drain disposed on the substrate and on the other side of the gate, the semiconductor device includes a sidewall structure; The sidewall structures are located on both sides of the gate and on the dielectric layer, and are a repeating stack structure consisting of an insulating layer and a stress layer.

2. 2. The semiconductor device of claim 1, wherein the shallow trench isolation structure is 10-30 nm below the surface of the substrate.

3. 10. The semiconductor device of claim 1, wherein the semiconductor device includes a passivation layer, the passivation layer being disposed over the gate, the sidewall structure and the dielectric layer.

4. 2. The semiconductor device of claim 1, wherein the gate comprises a first metal gate, and stress regions are provided in the substrate on either side of the first metal gate.

5. 5. The semiconductor device of claim 4, wherein the stress region extends toward a bottom of the first metal gate and extends to a connection between the sidewall structure and the first metal gate.

6. 2. The semiconductor device of claim 1, wherein the gate comprises a second metal gate, and lightly doped regions are provided in the substrate on either side of the second metal gate.

7. 2. The semiconductor device of claim 1, wherein the thickness of the dielectric layer in the first region is 2-5 nm, and the thickness of the dielectric layer in the second region is 4-8 nm.

8. 2. The semiconductor device according to claim 1, wherein the gate is a single-layer metal, a multi-layer metal, or a laminated structure of a metal and a metal compound.

9. providing a substrate, the substrate including a first region and a second region; forming a plurality of shallow trench isolation structures on the first region and the second region; removing a portion of the shallow trench isolation structure by extending an etching time during the removal of the pad oxide layer on the substrate; forming an opening in the shallow trench isolation structure that is lower than a surface of the substrate; forming a dielectric layer in the opening and on the substrate, the dielectric layer having a height in the second region greater than a height in the first region; forming a gate on the dielectric layer; forming a source on the substrate, the source being located on one side of the gate; 1. A method for manufacturing a semiconductor device, comprising forming a drain on the substrate, the drain being located on the other side of the gate, the method comprising the steps of: the semiconductor device includes a sidewall structure; A method for manufacturing a semiconductor device, characterized in that the sidewall structure is located on both sides of the gate and on the dielectric layer, and has a laminated structure consisting of an insulating layer and a stress layer repeated.

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