Semiconductor Device

Abstract

To solve a problem which becomes obvious with the increased memory capacity and with progression of scaling of a transistor that a DRAM in the past requires refresh at intervals of a few tens of seconds for retaining data to cause increase in power consumption, and that a state of a transistor is switched between an ON-state and an OFF-state frequently to cause deterioration of the transistor.SOLUTION: In a semiconductor device, by using a transistor having a wide-gap semiconductor, a trench transistor having a trench for a gate electrode and a trench for element isolation is provided. Even when a distance between a source electrode and a drain electrode is decreased, by setting a depth of the trench for the gate electrode appropriately, onset of a short channel effect can be inhibited.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a technology for miniaturizing semiconductor integrated circuits. In addition to silicon semiconductors, compound semiconductors are also used as elements of semiconductor integrated circuits. The present invention discloses an element using a wide-gap semiconductor as an example. [Background technology]

[0002] Dynamic RAM (DRAM) is a well-known semiconductor memory device. DRAM is also used in various electronic devices. The memory cells that make up the core of DRAM are It is composed of write and read transistors and capacitors.

[0003] DRAM, like other semiconductor integrated circuits, is subject to scaling rules, and circuit patterns are becoming finer. However, it was thought that it would be difficult to reduce the design rule to 100 nm or less. One of the reasons for this is that the channel length of transistors is less than 100 nm. In this case, punch-through current is more likely to flow due to the short channel effect, and the transistor becomes slow. The problem was that the device would no longer function as a switching element. To prevent current flow, it would be possible to dope the silicon substrate with a high concentration of impurities, but this would Junction leakage current easily flows between the source and the substrate or between the drain and the substrate, eventually causing the This will cause a decrease in retention characteristics and is not an appropriate solution to this problem. It was.

[0004] To address this issue, the transistors that make up the memory cells are formed in three dimensions, The area occupied by the memory cell is reduced while the effective channel length of the transistor is shortened. Methods have been devised to keep the effect to a level that does not occur. For example, A U-shaped vertically long groove is formed in the region where the gate electrode is to be formed, and a gate insulating film is formed along the wall surface of the groove. Further, a gate electrode is embedded in the trench (see Non-Patent Document 1).

[0005] A transistor having such a structure in the channel portion has a source region and a drain region. The current flows around the groove, making the effective channel length longer. This reduces the area occupied by the transistor in the memory cell while suppressing the short channel effect. This had the advantage of being able to control [Prior art documents] [Non-patent literature]

[0006] [Non-Patent Document 1] Kinam Kim, "Technology for sub-50nm DRAM and NAND Flash Manufacturing," International Electron Devices Meeting, 2005. IEDM Technical Digest, December 2005, p. 333 - 336 Summary of the Invention [Problem to be solved by the invention]

[0007] However, conventional DRAM requires refreshing every few tens of milliseconds to retain data. This resulted in an increase in power consumption. The problem was that the transistors would degrade because they switched between on and off states. This has become more prominent as memory capacity has increased and transistors have become more miniaturized.

[0008] Therefore, the present invention provides a technique for improving the data retention characteristics of a semiconductor memory device. Another object of the present invention is to provide a semiconductor memory device having improved data retention characteristics. It is an object of the present invention to provide a technology that can reduce power consumption while achieving high reliability. [Means for solving the problem]

[0009] In order to solve the above problems, a transistor having a wide gap semiconductor, particularly a wide Using an insulated gate transistor having a gap semiconductor, a circuit, specifically a semiconductor memory Configure the storage device.

[0010] By using transistors with wide-gap semiconductors, This allows the refresh to be performed at longer intervals, reducing power consumption. The number of times the transistor switches between on and off per unit time is reduced, This allows the transistors to have a longer life than conventional DRAM.

[0011] In addition, transistors using wide-gap semiconductor layers are also becoming smaller. If the temperature rises, there is a risk of the short channel effect appearing. We propose a new transistor structure that uses

[0012] One aspect of the embodiments disclosed herein is to provide a first trench and a second trench in an insulating layer. a wide gap semiconductor layer in contact with the bottom surface and the inner wall surface of the first trench; A gate insulating layer is formed on the semiconductor layer, a gate electrode is formed on the gate insulating layer, and a second trench is filled with and an insulating layer for insulating the gate insulating layer on the bottom surface and the inner wall surface of the second trench. The semiconductor device is characterized in that the first trench is filled with the gate electrode. The trench is a trench for a gate electrode, and the second trench is a trench for element isolation. The top surface of the first trench is stripe-shaped or rod-shaped, and the top surface of the second trench is The upper surface of the chuck has a lattice, stripe or bar shape.

[0013] In the above-mentioned configuration, a source electrode or a drain electrode is further provided in contact with the wide gap semiconductor layer. It is characterized by having a pole.

[0014] As a wide-gap semiconductor, it has a band gap at least larger than that of silicon (1.1 eV). For example, In-Ga-Zn-O oxide semiconductors have a 3.15 eV Indium-tin-zinc oxide semiconductors have an energy density of 2.6 eV to 2.8 eV or more, while indium oxide has an energy density of about 3.0 eV, indium tin oxide is about 3.0 eV, indium gallium oxide is about 3.3 eV, Indium zinc oxide is about 2.7 eV, tin oxide is about 3.3 eV, and zinc oxide is about 3.37 eV V) and GaN (about 3.4 eV).

[0015] The cross-sectional shape of the wide gap semiconductor layer in the channel length direction is the same as that of the first trench. The shape is curved along the surface, i.e., U-shaped, and the first trench is deep. The higher the structure, the longer the channel length of the transistor.

[0016] In addition, the trench-structure transistor disclosed in this specification has a source electrode, a drain electrode, and Even if the distance between the first and second trenches is narrowed, the short channel effect can be prevented by appropriately setting the depth of the first trench. can be suppressed. Effect of the Invention

[0017] It is possible to improve the data retention characteristics of the semiconductor memory device. This makes it possible to improve data retention characteristics while reducing power consumption. [Brief description of the drawings]

[0018] [Figure 1] 1A and 1B are a cross-sectional view and a top view illustrating one embodiment of the present invention. [Diagram 2] 1A and 1B are cross-sectional views and a circuit diagram illustrating one embodiment of the present invention. [Diagram 3] FIG. 1 is a cross-sectional view showing one embodiment of the present invention. [Figure 4] 1A and 1B are a circuit diagram and a conceptual diagram illustrating one embodiment of the present invention. [Diagram 5] FIG. 1 is a cross-sectional view showing one embodiment of the present invention. [Figure 6] This shows a cross-sectional view of the structure used in the calculations and the calculation results. [Figure 7] This shows a cross-sectional view of the structure used in the calculations and the calculation results. [Figure 8] This shows a cross-sectional view of the structure used in the calculations and the calculation results. [Figure 9] FIG. 1 is a circuit diagram illustrating one embodiment of the present invention. [Figure 10] FIG. 1 is a block diagram of a mobile device illustrating one embodiment of the present invention. [Figure 11] FIG. 1 is a block diagram of a semiconductor device illustrating one embodiment of the present invention. [Figure 12] FIG. 1 is a block diagram of an electronic book illustrating one embodiment of the present invention. [Figure 13] 1A to 1C are diagrams illustrating a structure of an oxide material according to one embodiment of the present invention. [Figure 14] 1A to 1C are diagrams illustrating a structure of an oxide material according to one embodiment of the present invention. [Figure 15] 1A to 1C are diagrams illustrating a structure of an oxide material according to one embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0019] Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings. The present invention is not limited to the following description, and various modifications in form and details are possible by those skilled in the art. The present invention is not limited to the description of the following embodiments. It is not something that can be done.

[0020] (Embodiment 1) In this embodiment, a structure and a manufacturing method of a transistor according to one embodiment of the present invention will be described. The description will be given with reference to FIG. 1. FIG. 1A is a cross-sectional view of a transistor 162 in the channel length direction. FIG. 1B shows an example of an element structure of a transistor 162 and a transistor 163. FIG. 1C shows an example of a cross-sectional view of the isolation region 165. 1B is a top view of the transistor 162. 1(C) is a part of a cross-sectional view in the channel width direction, taken along the dashed line D1-D2 in FIG. FIG. 1(A) corresponds to a cross section taken along the dashed line A1-A2 in FIG. 1(C). do.

[0021] First, an insulating layer 130 made of an oxide film is formed on a semiconductor substrate. Then, a wide gap semiconductor is formed to cover the trenches. A conductor layer 144 is formed. A known technique may be used to form a trench. In this embodiment, a trench having a depth of about 0.4 μm is formed. The trenches for the FETs are formed by a single etch or multiple etches.

[0022] The semiconductor substrate is an SOI substrate, and the drive circuit includes a MOSFET transistor. A semiconductor substrate on which a semiconductor device is formed, a semiconductor substrate on which a capacitor is formed, or the like is used.

[0023] The insulating layer 130 may be a silicon oxide film, a gallium oxide film, an aluminum oxide film, or a silicon nitride film. A silicon oxynitride film, an aluminum oxynitride film, or a silicon nitride oxide film is used. It can be formed.

[0024] The film thickness of the wide gap semiconductor layer 144 is set to 1 nm or more and 100 nm or less. method, MBE (Molecular Beam Epitaxy) method, CVD method, pulse Laser deposition method, ALD (Atomic Layer Deposition) method, coating method In addition, the wide gap semiconductor layer 144 may be formed by a sputtering method. The deposition is performed with multiple substrate surfaces set approximately perpendicular to the deposition target surface. The sputtering equipment that performs this process is called the CP sputtering equipment (Columnar Plasma Sputtering). The film may be formed using a tering system.

[0025] The material for the wide-gap semiconductor layer 144 should have a forbidden band larger than that of silicon. The wide oxide semiconductor, gallium nitride, gallium oxide nitride, and zinc gallium oxide nitride are used. At least indium is an oxide semiconductor with a larger band gap than silicon. It is preferable that the alloy contains aluminum (In) or zinc (Zn). It is particularly preferable that the alloy contains In and Zn. In order to reduce variation in electrical characteristics of a transistor using the oxide semiconductor, It is preferable to have gallium (Ga) in addition to the above as a stabilizer. It is also preferable to have tin (Sn) as a stabilizer. It is preferable that the stabilizer contains hafnium (Hf). It is preferable that the metal oxide contains niobium (Al).

[0026] Other stabilizers include the lanthanides lanthanum (La) and cerium ( Ce), praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), hol Ho, Erbium, Thulium, Ytterbium, Ru The element may contain one or more of the elements tetraethynyl (Te) and tetraethynyl (Lu).

[0027] For example, oxide semiconductors include indium oxide, tin oxide, zinc oxide, and oxides of binary metals. In-Zn oxide, Sn-Zn oxide, Al-Zn oxide, Zn-Mg oxide, etc. Oxides, Sn-Mg oxides, In-Mg oxides, In-Ga oxides, ternary metal oxides In-Ga-Zn oxide (also written as IGZO), In-Al-Zn oxide Oxide, In-Sn-Zn oxide, Sn-Ga-Zn oxide, Al-Ga-Zn oxide oxides, Sn-Al-Zn oxides, In-Hf-Zn oxides, In-La-Zn oxides In-Ce-Zn oxides, In-Pr-Zn oxides, In-Nd-Zn oxides , In-Sm-Zn oxide, In-Eu-Zn oxide, In-Gd-Zn oxide, In-Tb-Zn oxide, In-Dy-Zn oxide, In-Ho-Zn oxide, I n-Er-Zn oxide, In-Tm-Zn oxide, In-Yb-Zn oxide, In -Lu-Zn ​​oxides, In-Sn-Ga-Zn oxides, which are oxides of quaternary metals, I n-Hf-Ga-Zn oxide, In-Al-Ga-Zn oxide, In-Sn-Al- Zn-based oxide, In-Sn-Hf-Zn-based oxide, In-Hf-Al-Zn-based oxide are used. There can be.

[0028] In this case, for example, In-Ga-Zn oxide is a material containing In, Ga, and Zn as main components. The ratio of In, Ga, and Zn does not matter. Metal elements other than a and Zn may be present.

[0029] In addition, as an oxide semiconductor, InMO3(ZnO) m (m>0 and m is not an integer) In addition, M may be selected from Ga, Fe, Mn, and Co. It indicates one or more metal elements. In addition, as an oxide semiconductor, In3SnO5 (ZnO) n A material expressed as (n>0, and n is an integer) may be used.

[0030] For example, In:Ga:Zn=1:1:1 (=1 / 3:1 / 3:1 / 3) or In:G In-Ga-Zn system oxide with an atomic ratio of a:Zn=2:2:1 (=2 / 5:2 / 5:1 / 5) Alternatively, In:Sn:Zn=1 :1:1(=1 / 3:1 / 3:1 / 3), In:Sn:Zn=2:1:3(=1 / 3:1 / 6:1 / 2) or In:Sn:Zn=2:1:5(=1 / 4:1 / 8:5 / 8) It is advisable to use an In--Sn--Zn-based oxide having an atomic ratio or an oxide having a composition close to that.

[0031] In addition, the In-Sn-Zn oxide can be called ITZO (registered trademark), and the The target composition ratio is In:Sn:Zn, with the atomic ratio being 1:2:2, 2:1:3, and 1:1. Use an oxide target with a ratio of 20:1, or 20:45:35, etc.

[0032] However, the present invention is not limited to these, and can be applied to any semiconductor characteristics (mobility, threshold, variation, etc.) required. In order to obtain the required semiconductor characteristics, the appropriate composition should be used. Carrier density, impurity concentration, defect density, atomic ratio of metal elements to oxygen, interatomic bond length, density It is preferable to make the above appropriate.

[0033] For example, high mobility can be obtained relatively easily with In-Sn-Zn oxides. Therefore, in the case of In-Ga-Zn oxides, the mobility can be increased by reducing the defect density in the bulk. It can be done.

[0034] For example, the atomic ratio of In, Ga, and Zn is In:Ga:Zn=a:b:c(a+b+ The composition of the oxide with the atomic ratio of In:Ga:Zn=A:B:C (A+B+C = 1), a, b, and c are in the vicinity of the oxide composition (a-A). 2 +(b-B) 2 + (c-C) 2 ≦r 2 The above condition is satisfied, and r can be set to, for example, 0.05. The same is true for compounds.

[0035] The oxide semiconductor may be single-crystalline or non-single-crystalline. In the latter case, it may be amorphous or polycrystalline. In addition, the structure may include a portion having crystallinity in the amorphous state, or a non-amorphous structure. That's fine too.

[0036] Since it is relatively easy to obtain a flat surface for an amorphous oxide semiconductor, This can reduce interface scattering when fabricating a transistor, and can be achieved relatively easily and with relatively high quality. Therefore, high mobility can be obtained.

[0037] In this embodiment, the c-axis is oriented and has a triangular or triangular shape when viewed from the ab plane, surface, or interface direction. The atomic arrangement is hexagonal or hexagonal, and the metal atoms are arranged in layers or in a combination of metal atoms and oxygen atoms along the c axis. The molecules are arranged in layers, and the a-axis and b-axis directions are different in the ab plane (the c-axis is the center). C-Axis Aligned Crystal (CAAC) This article will explain oxides containing .

[0038] In a broad sense, oxides containing CAAC are non-single crystals that are not crystalline when viewed from a direction perpendicular to the ab plane. The atomic arrangement is a triangle, a hexagon, an equilateral triangle, or an equilateral hexagon, and is perpendicular to the c-axis direction. From the viewpoint of the direction, it is an acid containing a phase in which metal atoms are arranged in layers, or metal atoms and oxygen atoms are arranged in layers. It refers to a monster.

[0039] CAAC is not a single crystal, but it is not composed of only amorphous matter. AC contains crystallized parts (crystalline parts), but the boundary between one crystalline part and another crystalline part is not clearly defined. Sometimes it is not possible to determine with certainty.

[0040] When oxygen is contained in CAAC, a part of the oxygen may be replaced with nitrogen. The c-axes of the individual crystals that make up the CAAC are aligned in a certain direction (e.g., the substrate surface supporting the CAAC, C The CAAC may be aligned in a direction perpendicular to the surface of the AAC. The normal to the ab plane of the crystal part of the CAAC is in a certain direction (for example, the substrate plane supporting the CAAC, The direction may be perpendicular to the surface of the substrate.

[0041] CAAC can be a conductor, a semiconductor, or an insulator depending on its composition. Also, depending on the composition, it may be transparent or opaque to visible light. To do.

[0042] An example of such a CAAC is a film-like CAAC that is perpendicular to the film surface or the supporting substrate surface. When observed from the direction, a triangular or hexagonal atomic arrangement is observed, and when the cross section of the film is observed, When the metal atoms are mixed, a layered arrangement of metal atoms or metal atoms and oxygen atoms (or nitrogen atoms) is observed. Crystals may also be mentioned.

[0043] An example of a crystal structure contained in CAAC will be described in detail with reference to FIGS. 13 to 15, the upward direction is the c-axis direction, and the The plane that is the boundary between the two is called the ab plane. In Figure 13, the circled O represents a 4-coordinate O, and the The circled O indicates a three-coordinate O.

[0044] In Fig. 13(A), one hexacoordinate In atom and six tetracoordinate oxygen atoms (hereafter referred to as 4) adjacent to the In atom are shown. The structure shown here has one metal atom and one nearby oxygen atom. The structure shown in Fig. 13(A) is an octahedral structure, but it is easy to For simplicity, the structure is shown in a plan view. There are three O atoms in each group that are 4-coordinated. The small group shown in Figure 13(A) has a zero charge.

[0045] In Figure 13(B), one pentagonal Ga atom and three trigonal oxygen atoms (hereafter referred to as 3 The structure shows a 3-coordinate O and two adjacent 4-coordinate O. There is also one 4-coordinate valence atom in the upper and lower halves of Figure 13(B). O. In addition, since In also has a 5-coordinate, it can have the structure shown in Figure 13(B). The small group shown in (B) has a zero charge.

[0046] FIG. 13(C) shows a structure having one tetracoordinate Zn and four tetracoordinate O atoms adjacent to the Zn. The upper half of Figure 13(C) has one tetracoordinate O atom, and the lower half has three tetracoordinate O atoms. Or, in the upper half of Fig. 13(C), there are three 4-coordinate Os, and in the lower half, there is one There may be 4-coordinated O. The small group shown in Figure 13(C) has a zero charge.

[0047] FIG. 13(D) shows a structure having one hexacoordinate Sn atom and six tetracoordinate O atoms adjacent to the Sn atom. The upper half of Figure 13(D) has three tetracoordinate O atoms, and the lower half has three tetracoordinate O atoms. The small group shown in Figure 13(D) has a charge of +1.

[0048] Figure 13(E) shows a small group containing two Zn atoms. The upper half of Figure 13(E) shows one Zn atom. The small group shown in Figure 13(E) has four-coordinated O atoms, and one four-coordinated O atom in the lower half. has a charge of -1.

[0049] Here, a collection of multiple small groups is called a medium group, and a collection of multiple medium groups is called a These are called large groups (also called unit cells).

[0050] Here, we will explain the rules for combining these small groups. The upper three O's of the 6-coordinate In have three adjacent In's downward, and the lower three Each O has three adjacent In atoms in the upward direction. Each O in the upper half has one adjacent Ga in the downward direction, and each O in the lower half has one adjacent Ga in the upward direction. The upper half of the Zn with 4-coordinates shown in Figure 13(C) has one O atom downward. The three O's in the lower half each have three adjacent Zn's in the upward direction. Similarly, the number of 4-coordinated O atoms above a metal atom and the number of adjacent metal atoms below that O are Similarly, the number of 4-coordinated O atoms below the metal atom and the number of adjacent metal atoms above the O atom are The number of atoms is equal. Since O is 4-coordinated, the number of neighboring metal atoms below is equal to the number of neighboring metal atoms above. The sum of the number of contact metal atoms is 4. Therefore, the number of 4-coordinated O atoms above the metal atom and the number of other When the sum of the number of tetracoordinated O atoms below the metal atom is 4, two types of metal atoms are Small groups can bond together. For example, a 6-coordinate metal When an atom (In or Sn) is bonded through a tetrahedral O in the lower half, there are three tetrahedral O atoms. Therefore, the 5-coordinate metal atom (Ga or In) or the 4-coordinate metal atom (Zn) It will combine with either one.

[0051] Metal atoms with these coordination numbers are bonded in the c-axis direction via four-coordinate oxygen atoms. In addition, multiple small groups are bonded together so that the total charge of the layer structure is zero. Forms a medium group.

[0052] Figure 14(A) shows a model diagram of the middle group that constitutes the In-Sn-Zn-O system layer structure. Figure 14(B) shows a large group consisting of three medium groups. FIG. 14C shows the atomic arrangement when the layer structure of FIG. 14B is observed from the c-axis direction.

[0053] In FIG. 14(A), for simplicity, the tricoordinate O is omitted, and only the number of the tetracoordinate O is shown. For example, the upper and lower halves of Sn each contain three 4-coordinate O atoms, as shown in the circle. Similarly, in FIG. 14(A), the upper and lower halves of In are Each has one 4-coordinate O atom, which is indicated by the circle 1. Similarly, in Figure 14 In (A), there is one tetracoordinate O in the lower half and three tetracoordinate O in the upper half. Zn with one tetrahedral O atom in the upper half and three tetrahedral O atoms in the lower half. This shows that:

[0054] In FIG. 14(A), the middle group, which is composed of an In-Sn-Zn-O system layer structure, is Sn has three tetracoordinate O atoms in the upper half and three in the lower half, and one tetracoordinate O atom in the upper half. The In is bonded to the In in the upper and lower halves of the Z atom, which has three tetracoordinate O atoms in the upper half. n, and three tetracoordinate O atoms are bonded to the upper half of the Zn via one tetracoordinate O atom in the lower half of the Zn. and In in the lower half, which is bonded to Zn2 with one 4-coordinated O in the upper half. It bonds to a small group of 4-coordinate O atoms in the lower half of this small group. The structure has three O atoms bonded to Sn atoms in the upper and lower halves. Multiple loops are combined to form large groups.

[0055] Here, the charge per bond for the three-coordinated O and four-coordinated O is -0.6, respectively. 67, -0.5. For example, In (6 or 5 coordinates), Zn (4 The charges of Sn (5 or 6 coordinated) are +3, +2, and +4, respectively. Therefore, the small group containing Sn has a charge of +1. Therefore, a layer structure containing Sn is formed. To do this, a charge of -1 is required to cancel out the charge of +1. The structure shown in Figure 1 shows a structure that can take a charge of -1. As shown in Figure 3(E), a small group containing two Zn atoms is included. For example, Sn-containing If there is one small group with two Zn atoms per small group, the charges are cancelled out. Therefore, the total charge of the layer structure can be set to zero.

[0056] Specifically, the large group shown in FIG. 14(B) is repeated to form the In-Sn-Zn In-Sn-ZnO crystals (In2SnZn3O8) can be obtained. -The layered structure of the Zn-O system is In2SnZn2O7(ZnO) m (m is 0 or a natural number.) This can be expressed by the composition formula:

[0057] In addition, there are oxides of four-component metals, such as In-Sn-Ga-Zn oxides and trimetallic oxides. In-Ga-Zn oxide (also written as IGZO), which is an oxide of the elemental metal, In- Al-Zn oxide, Sn-Ga-Zn oxide, Al-Ga-Zn oxide, Sn-A l-Zn oxide, In-Hf-Zn oxide, In-La-Zn oxide, In-C e-Zn oxide, In-Pr-Zn oxide, In-Nd-Zn oxide, In-Sm -Zn oxide, In-Eu-Zn oxide, In-Gd-Zn oxide, In-Tb- Zn-based oxide, In-Dy-Zn-based oxide, In-Ho-Zn-based oxide, In-Er-Z n-type oxides, In-Tm-Zn-type oxides, In-Yb-Zn-type oxides, In-Lu-Zn In-Zn oxides, Sn-Zn oxides, and Al oxides are binary metal oxides. -Zn-based oxides, Zn-Mg-based oxides, Sn-Mg-based oxides, In-Mg-based oxides, and I The same applies when n-Ga-based oxides are used.

[0058] For example, Figure 15(A) shows a model of the middle group consisting of an In-Ga-Zn-O layer structure. A diagram of the rule is shown.

[0059] In FIG. 15(A), the middle group, which is made up of an In-Ga-Zn-O-based layer structure, is In the upper half and lower half, there are three tetracoordinate O atoms, and in the lower half, there is one tetracoordinate O atom. It bonds to Zn at the bottom of the Zn atom, and one tetracoordinate O atom is bonded to the Zn atom via the three tetracoordinate O atoms in the bottom half of the Zn atom. It bonds to Ga in the upper and lower halves, respectively, and is bonded to one tetracoordinate O in the lower half of the Ga. The structure is such that three 4-coordinate O atoms are bonded to In atoms in the upper and lower halves. These medium groups combine to form large groups.

[0060] Figure 15(B) shows a large group consisting of three medium groups. 15B is viewed from the c-axis direction.

[0061] Here, the charges of In (6 or 5 coordinates), Zn (4 coordinates), and Ga (5 coordinates) are Since the valence numbers are +3, +2, and +3, respectively, the small group containing either In, Zn, or Ga is , the charge is 0. Therefore, if these small groups are combined, the combination of the medium groups The total charge will always be zero.

[0062] The middle group, which is made up of an In-Ga-Zn-O-based layer structure, is shown in FIG. Not limited to the middle group, large-scale combination of middle groups with different arrangements of In, Ga, and Zn Groups are also possible.

[0063] Next, a source electrode or a drain electrode is formed on the wide gap semiconductor layer 144. The electrodes 142a and 142b are formed by using molybdenum. Titanium, Tantalum, Tungsten, Aluminum, Copper, Chromium, Neodymium, Scandium The insulating layer 11 can be formed using a metal material such as aluminum or an alloy material containing this as a main component.

[0064] In addition, when GaN is used as the wide gap semiconductor layer 144, The electrodes 142a and 142b functioning as the inner electrodes are made of titanium or the like. Between 2a, 142b and the wide gap semiconductor layer 144, a two-dimensional electron gas is formed. Aluminum gallium nitride (AlGaN) is used as a buffer layer for this purpose.

[0065] Furthermore, in order to protect the electrodes 142a and 142b, insulating layers 143a and 143b are formed. Next, a planarization process is performed using CMP (chemical mechanical polishing) or the like. At this time, the insulating layers 143a and 143b serve as buffer layers to prevent the electrodes 142a and 142b from being scraped. It functions as:

[0066] Next, a trench for isolating the device in the channel length direction and a trench for isolating the device in the channel width direction are formed. These isolation trenches form a continuous top surface pattern. In this embodiment, the trench is formed by Therefore, in order to separate the wide-gap semiconductor layer, these trends are The channel pattern is a connected top surface pattern shape (lattice shape). When forming the trench for isolating the electrodes, the electrodes 142a and 142b can also be separated. The timing of forming the trenches for isolating the elements is not particularly limited. The depth of the isolation trench is set to be equal to the trench for the gate electrode if the device isolation is sufficient. The depth is not limited to the same horizontal position of the bottom surface as the trench for the gate electrode. By deepening the horizontal position of the bottom surface of the trench for use, element isolation can be performed reliably.

[0067] Next, a part of the wide gap semiconductor layer 144, which functions as a source electrode or a drain electrode, The gate insulating layer 14 covers the electrodes 142a, 142b and the insulating layers 143a, 143b. 6 is formed. Also, the inner wall and bottom of the trench for element isolation in the channel length direction and the channel A gate insulating layer 146 is also formed on the inner wall and bottom surface of the trench in the width direction.

[0068] The thickness of the gate insulating layer 146 is set to 1 nm or more and 100 nm or less. The E method, CVD method, pulsed laser deposition method, ALD method, coating method, printing method, etc. can be used appropriately. Also, the gate insulating layer 146 is formed approximately perpendicular to the surface of the sputtering target. A sputtering device that deposits films on multiple substrate surfaces set in a chamber, known as a CP sputtering device. Alternatively, the film may be formed using

[0069] The material of the gate insulating layer 146 is a silicon oxide film, a gallium oxide film, an aluminum oxide film, or the like. a silicon nitride film, a silicon oxynitride film, an aluminum oxynitride film, or a nitride oxide film. The gate insulating layer 146 can be formed using a silicon film. It is preferable to form the gate insulating layer 146 taking into consideration the size of the transistor and the step coverage of the gate insulating layer 146. In this embodiment, the gate insulating layer 146 is made of SiO 2+α (where α>0) This silicon oxide film is used as the gate insulating layer 146. This allows oxygen to be supplied to the In-Ga-Zn-O oxide semiconductor, improving its characteristics. It is possible.

[0070] The material of the gate insulating layer 146 is hafnium oxide, yttrium oxide, hafnium Silicate (HfSi x O y x>0, y>0), nitrogen-doped hafnium silicate (HfSi x O y N z (x>0, y>0, z>0)), hafnium aluminate (Hf Al x O y (x>0, y>0)) and other high-k materials are used to reduce gate leakage. In addition, the gate insulating layer 146 may have a single layer structure or a stacked layer structure. It is also possible to say this.

[0071] Then, the gate electrode 148a is filled in the trench for the gate electrode with a gate insulating film. The gate electrode 148a is formed on the edge layer 146. The material of the gate electrode 148a is selected from the group consisting of molybdenum, titanium, and tantalum. Metallic materials such as tungsten, aluminum, copper, chromium, neodymium, and scandium, The gate electrode 148a can be formed by using an alloy material containing these as main components. It may have a single layer structure or a laminated structure.

[0072] A layer of the gate electrode 148a in contact with the gate insulating layer 146 is a metal oxide containing nitrogen. Specifically, nitrogen-containing In-Ga-Zn-O films, nitrogen-containing In-Sn-O films, and nitrogen-containing In-Ga-O films containing nitrogen, In-Zn-O films containing nitrogen, Sn-O films containing nitrogen, In the case of the ferroelectric material, nitrogen-containing In-O films and metal nitride films (InN, SnN, etc.) are used. 5 electron volts, preferably 5.5 electron volts or more, and used as a gate electrode. In this case, the threshold voltage of the transistor can be made positive, which is called a normally-off state. It is possible to realize a switching element having the above structure.

[0073] At the stage where the gate electrode 148a is formed in the trench for the gate electrode, the transistor of the trench structure is A transistor 162 is formed.

[0074] Next, an insulating layer 149 is formed to cover the gate electrodes 148a and 148b. It is preferable to use an insulating film with good step coverage. Silicon film, gallium oxide film, aluminum oxide film, silicon nitride film, silicon oxynitride film The insulating film can be formed using an aluminum oxynitride film or a silicon nitride oxide film. In this embodiment, an aluminum oxide film is used as the material of the insulating layer 149. In FIG. 1B, a gate insulating layer is provided in contact with the side surface of the wide gap semiconductor layer 144. 146 is formed, and then an insulating layer 149 is formed. Therefore, in this embodiment, Si O 2+α (where α>0) is a silicon oxide film on the side of the wide-gap semiconductor layer 144. The aluminum oxide film covers the silicon oxide film, and the aluminum oxide film covers the silicon oxide film. Oxygen diffuses and is blocked from passing through the insulating layer 149 .

[0075] After the insulating layer 149 is formed, an insulating layer 150 for filling the trenches for element isolation is formed by CV. The insulating layer 150 is filled in the trench for element isolation by the D method or the like. The element isolation regions 161 and 165 are formed. Note that, before the insulating layer 150 is formed, In the trench, a gate insulating layer 146 and an insulating layer 149 are laminated, so that the insulating layer 15 This makes it possible to reduce the area filled with 0 and smoothly fill the insulating layer 150. After that, a planarization process is performed using CMP or the like to obtain the structure shown in FIG. 1(A) and FIG. 1(B). It is possible.

[0076] As shown in FIG. 1B, the gate electrode 148a of the transistor 162 and the adjacent An insulating layer 150 is also filled between the gate electrode 148b of the transistor 163, and the gate As shown in FIG. 1A, the transistor 162 The electrodes functioning as source and drain electrodes of the transistors are adjacent to each other in the channel length direction. An insulating layer 150 is also provided between the electrodes that function as the source and drain electrodes of the transistor. It is also possible to prevent a short circuit of the source electrode or the drain electrode.

[0077] In this embodiment, the wide gap semiconductor layer 144 is in contact with the inner wall of the trench having a thickness of 0.4 μm. In order to form the wide gap semiconductor layer 144, the channel length is about 0.8 μm or more. In contrast, when using an In-Ga-Zn-O oxide semiconductor, the channel length is 0.8 μm or more. This makes it possible to make a normally-off transistor, which reduces the short channel effect. In addition, by adopting a trench structure, This allows the planar area of ​​the capacitor to be reduced, making high integration possible.

[0078] (Embodiment 2) The transistor 162 shown in FIG. 1 is used to retain memory contents even when power is not supplied. FIG. 2 shows an example of a semiconductor device that is capable of performing write operations without limiting the number of times the data can be written.

[0079] Since the off-state current of the transistor 162 is small, the use of the transistor 162 enables long-term recording. In other words, the frequency of refresh operations can be reduced significantly. This makes it possible to sufficiently reduce power consumption.

[0080] FIG. 2A shows an example of a cross section of a semiconductor device.

[0081] The semiconductor device shown in FIG. 2A includes a transistor 160 using a first semiconductor material in a lower portion. The transistor 162 is made of a second semiconductor material. Since the resistor 162 is the same as that in the first embodiment, the resistor 162 in FIG. ) The same parts as those in the above description will be explained using the same reference numerals.

[0082] Here, the first semiconductor material and the second semiconductor material may be materials having different forbidden band widths. For example, the first semiconductor material may be a semiconductor material other than an oxide semiconductor (such as silicon). The second semiconductor material can be an oxide semiconductor. The transistors used in this study can easily operate at high speed. The characteristics of the charge storage capacitor enable it to retain electric charge for a long period of time.

[0083] It should be noted that the above transistors are all n-channel transistors. However, it goes without saying that a p-channel transistor can be used. The technical essence of the invention is to use wide-gap semiconductors as transistors to hold information. 162, the materials used in the semiconductor device and the structure of the semiconductor device, etc. The specific configuration of the conductor device need not be limited to those shown here.

[0084] The transistor 160 in FIG. 2A includes a semiconductor material (e.g., silicon). A channel forming region 116 is provided on the substrate 100, and a an impurity region 120 provided in the semiconductor substrate 10 and a metal compound region 124 in contact with the impurity region 120; A gate insulating layer 108 is provided on the channel forming region 116. and a gate electrode 110 provided thereon.

[0085] An electrode 126 is connected to a portion of the metal compound region 124 of the transistor 160 . Here, the electrode 126 functions as a source electrode or a drain electrode of the transistor 160. In addition, an element isolation insulating layer is provided on the substrate 100 so as to surround the transistor 160. An insulating layer 130 is provided to cover the transistor 160. In order to achieve this, the transistor 160 has a sidewall insulation as shown in FIG. On the other hand, in order to prioritize the characteristics of the transistor 160, In this case, a sidewall insulating layer is provided on the side of the gate electrode 110, and the impurity concentration is different. An impurity region 120 including a region may be provided.

[0086] As shown in FIG. 2A, the transistor 162 has a wide-gap semiconductor layer 144. This is a trench structure transistor.

[0087] Here, it is desirable that the wide gap semiconductor layer 144 is highly purified. By using highly purified wide-gap semiconductors, transistors with extremely excellent electrical characteristics can be manufactured. You can get star 162.

[0088] In the transistor 162 in FIG. 2A, leakage current occurring between elements due to miniaturization is prevented. In order to suppress this, an element isolation region 161 is provided. The wide-gap semiconductor layer 144 is processed into an island shape smaller than the region to be covered. As shown in the first embodiment, the semiconductor device is not processed into an island shape until the trench for element isolation is formed. In the case where the wide gap semiconductor layer is not processed into an island shape, This can prevent contamination of the wide gap semiconductor layer 144 caused by etching during the etching process. When the gap semiconductor layer is not processed into an island shape, the number of steps can be reduced. The wide-gap semiconductor is processed into an island shape smaller than the area surrounded by the element isolation region 161. When a semiconductor layer is used, the wide-gap semiconductor layer is divided by forming a trench for element isolation. Therefore, the horizontal position of the bottom surface of the trench for element isolation is the same as that of the trench for gate electrode. It is possible to make the trench depth shallower than that of the conventional method, or to reduce the total area of ​​the trench for element isolation. do.

[0089] An insulating layer 151 is provided on the transistor 162, and a gate An electrode 153 is provided which is electrically connected to the electrode 148a. The insulating layer 152 is provided on the gate insulating layer 146, the insulating layer 150, and the insulating layer An electrode 154 is provided in an opening formed in the insulating layer 151, the insulating layer 152, etc. A wiring 156 that is connected to the electrode 154 is formed on the electrode 126. and the electrode 154, the metal compound region 124, the electrode 142b, and the wiring 156. However, the disclosed invention is not limited to this. Alternatively, the wiring 156 may be directly connected to the electrode 142b. You can touch it.

[0090] Next, an example of a circuit configuration corresponding to FIG. 2(A) is shown in FIG. 2(B).

[0091] In FIG. 2B, the first wiring (1st Line) and the source voltage of the transistor 160 The electrodes are electrically connected to the second wiring (2nd Line) and the drain of the transistor 160. The third line and the drain electrode are electrically connected. The fourth transistor 162 is electrically connected to one of the source electrode and the drain electrode. The wiring (4th Line) and the gate electrode of the transistor 162 are electrically connected. The gate electrode of the transistor 160 and the source voltage of the transistor 162 are The other of the electrodes or the drain electrode is electrically connected to one of the electrodes of the capacitor 164. The fifth line and the other electrode of the capacitor 164 are electrically connected. There are.

[0092] The capacitor 164 is manufactured in the same process as the transistor 160 and the transistor 162. In this way, the device can be formed with a pair of electrodes and an insulating layer that acts as a dielectric material and is sandwiched between the electrodes. The transistors 160 and 162 are formed in the same process. Without being limited thereto, a separate layer of the capacitor 164 may be provided above the transistor 162 . For example, a trench capacitor or a stack capacitor can be used separately for the 16 2 or below the transistor 160, and then stacked three-dimensionally to form a high Integration may also be attempted.

[0093] In the semiconductor device shown in FIG. 2B, the potential of the gate electrode of the transistor 160 can be held. By taking advantage of this feature, it is possible to write, retain, and read information as follows.

[0094] The writing and holding of data will be described. First, the potential of the fourth wiring is set to The transistor 162 is turned on by applying a potential to the transistor 162. The potential of the third wiring is applied to the gate electrode of the transistor 160 and the capacitor 164. That is, a predetermined charge is applied to the gate electrode of the transistor 160 ( Write). Here, charges that give two different potential levels (hereinafter, low-level charges, Then, either the high level charge or the low level charge is applied to the fourth wiring. The potential is set to a potential at which the transistor 162 is turned off, so that the transistor 162 is turned off. By setting the transistor 160 in this state, the charge applied to the gate electrode of the transistor 160 is held ( retention).

[0095] A back gate electrode may be provided, and a voltage is applied to the back gate electrode. It is preferable to ensure that transistor 162 is normally off.

[0096] This embodiment mode can be freely combined with the first embodiment mode.

[0097] (Embodiment 3) In this embodiment, the transistor 162 shown in FIG. 1 is used, and the transistor 162 is not supplied with power. A semiconductor device that can retain memory contents even in a variety of situations and has no limit on the number of times it can be written to. Next, the configuration different from that shown in the second embodiment will be described with reference to FIG.

[0098] The semiconductor device shown in FIG. 3 has a transistor 350 using a first semiconductor material in a lower portion. The upper portion has a transistor 162 using a second semiconductor material. A plurality of transistors are formed in the semiconductor material below and typically includes a transistor The following describes the transistor 350 and the transistor 162. FIG. 3 corresponds to a cross-sectional view perpendicular to the channel length direction of the transistor.

[0099] Here, the first semiconductor material and the second semiconductor material may be materials having different forbidden band widths. For example, the first semiconductor material may be a semiconductor material other than an oxide semiconductor (such as silicon). The second semiconductor material can be an oxide semiconductor. The transistors used in this study can easily operate at high speed. The characteristics of the charge storage capacitor enable it to retain electric charge for a long period of time.

[0100] The transistor 162 using the second semiconductor material in the upper portion is the same as that in the first embodiment and 1(A) and the transistor 162 described in the second embodiment. ) the same parts are designated by the same reference numerals, and detailed explanations thereof will be omitted.

[0101] Here, the transistor 350 using the first semiconductor material in the lower portion will be described below. cormorant.

[0102] The transistor 350 includes a semiconductor substrate 310, a gate insulating layer 314, a semiconductor layer 316, and a conductive layer 318, a protective insulating layer 320, a sidewall insulating layer 322, an impurity region 324, and an insulating The semiconductor layer 316 and the conductive layer 318 are connected to the gate electrode 322. The impurity region 324 functions as a source region or a drain region.

[0103] The transistor 350 is adjacent to a shallow trench isolator (STI). olation region 312.

[0104] As the STI region 312, first, a protective insulating film is formed in a desired region on the semiconductor substrate 310. By forming a trench and then etching it, a trench is formed. After that, an insulating dielectric film is filled into the trench to form the STI region 312. The insulating dielectric film may be a silicon oxide film, a silicon nitride film, or the like. .

[0105] Next, a detailed description of the transistor 350 will be given. The gate insulating layer 31 of the transistor 350 4, after forming an insulating film on a semiconductor substrate 310 in which an STI region 312 is formed, Patterning and etching are performed at desired positions to form STI regions 312 and Then, a heat treatment is performed in an oxygen atmosphere to form trenches of different depths. The semiconductor substrate 310 in the trench may be oxidized to form a gate insulating layer 314. .

[0106] After the gate insulating layer 314 is formed, a silicon film is formed by using the LPCVD method or the like. , the silicon film + , p + Doping or heat treatment is then performed to produce the so-called polysilicon. A highly conductive semiconductor layer is then formed on the semiconductor layer by sputtering. The metal film is formed by a method such as the deposition of tungsten, titanium, cobalt, Nickel or alloy films containing tungsten, titanium, cobalt, nickel, metal nitride A patterning film, a silicide film, or the like can be appropriately used. The conductive layer 318 is formed by masking and etching. The semiconductor layer 316 can be formed by etching the semiconductor layer as a mask. The conductive layer 318 and the semiconductor layer 316 function as a gate electrode of the transistor 350. .

[0107] Next, a protective insulating layer 320 is formed on the conductive layer 318. The protective insulating layer 320 may include: Using a plasma CVD method or the like, a silicon oxide film, a silicon nitride film, etc. are formed, and the desired area is The insulating layer can be formed by performing patterning and etching processes on the insulating layer.

[0108] Next, a plasma CVD method or the like is used to cover the semiconductor substrate 310 and the protective insulating layer 320. A silicon nitride film is formed and etched back to form a sidewall insulating layer 32. 2 can be formed.

[0109] Next, the protective insulating layer 320 and the sidewall insulating layer 322 are used as a mask to perform doping. By carrying out the process, an impurity region 324 is formed. Note that the dopant is boron or The dopant used for the impurity region 324 may be phosphorus or the like. + area, p + The impurity region 324 may be formed as appropriate. The source and drain regions of the transistors are connected to the source and drain electrodes of the transistors.

[0110] Next, a SiO 2 film is formed on the impurity region 324, the protective insulating layer 320, and the sidewall insulating layer 322 so as to cover the impurity region 324, the protective insulating layer 320, and the sidewall insulating layer 322. The insulating layer 326 is formed as shown in FIG. It can be formed using a silicon film or the like.

[0111] Next, an opening is provided in a desired region of the insulating layer 326, and the opening is electrically connected to the impurity region 324. A connection electrode 325 and a connection electrode 331 are formed. After the formation of 331, the surfaces of the insulating layer 326, the connection electrode 325, and the connection electrode 331 are planarized. For example, a CMP process may be performed to increase the surface roughness.

[0112] Next, a layer is formed on the insulating layer 326, the connection electrode 325, and the connection electrode 331 by a sputtering method or the like. A conductive film is formed using a material such as a silicon nitride film, which is then patterned in the desired area and etched. Form the electrodes 328 and 332. Materials that can be used for the electrodes 328 and 332 As the material, tungsten, copper, titanium, etc. can be appropriately used.

[0113] Next, the insulating layer 329 is formed over the insulating layer 326, the electrode 328, and the electrode 332. The insulating layer 329 can be formed using a material and method similar to those of the insulating layer 326 .

[0114] Through the above steps, a semiconductor substrate on which a transistor 350 using the first semiconductor material is formed is obtained. A plate 310 can be formed.

[0115] Here, a transistor 350 using a first semiconductor material in the lower part and a transistor 350 using a second semiconductor material in the upper part are The connections of the transistor 162 using the material will be described below.

[0116] The transistor 350 includes an impurity region 324, a connection electrode 325, an electrode 328, and a connection On the other hand, the transistor 162 is electrically connected to the non-transistor 330. A pure region 324, a connection electrode 331, an electrode 332, a connection electrode 334, and an electrode 336. , and is electrically connected to the wiring 156 via a connection electrode 338 .

[0117] Also, the gate electrode of the transistor 350 (i.e., the semiconductor layer 316 and the conductive layer 318 ) is electrically connected to the source electrode of the transistor 162. The connection between the gate electrode of transistor 350 and the source electrode of transistor 162 is not shown. The connection is not made in a straight line, but in three dimensions.

[0118] As described above, the memory cells formed in the upper portion are one type of wide gap semiconductor. The transistor using an oxide semiconductor is formed. Since the off-current of a transistor is small, the memory contents can be maintained for a long period of time by using the transistor. In other words, the frequency of refresh operations can be reduced significantly. Therefore, power consumption can be reduced sufficiently. Semiconductor materials other than oxide semiconductors are used. For example, silicon, germanium, silicon germanium, silicon carbide, or gallium. It is preferable to use a single crystal semiconductor. A transistor using this material can operate at a sufficiently high speed. By using transistors made of materials other than silicon, various circuits that require high speed operation (logic circuits, drive circuits, etc.) It is possible to realize suitable circuits such as a driving circuit.

[0119] In this way, transistors using materials other than oxide semiconductors (in other words, transistors that operate at sufficiently high speed) The peripheral circuits are made of transistors that can be operated with a semiconductor oxide. In a broader sense, the off-state current of the transistor is sufficiently small. This makes it possible to realize a semiconductor device having unprecedented features. By forming the gate and the memory circuit in a stacked structure, the integration of the semiconductor device can be promoted.

[0120] This embodiment mode can be implemented in appropriate combination with the configurations described in other embodiments. It is.

[0121] (Embodiment 4) In this embodiment, the transistor 162 shown in FIG. 1 is used, and the transistor 162 is not supplied with power. A semiconductor device that can retain memory contents even in a variety of situations and has no limit on the number of times it can be written to. Regarding the configuration different from the configurations shown in the second and third embodiments, FIG. 5 will be used for explanation.

[0122] FIG. 4A shows an example of a circuit configuration of a semiconductor device, and FIG. 4B shows an example of the semiconductor device. First, the semiconductor device shown in FIG. 4(A) will be explained, followed by the semiconductor device shown in FIG. The semiconductor device shown in FIG.

[0123] In the semiconductor device shown in FIG. 4A, the bit line BL and the source electrode of the transistor 162 The word line WL and the gate electrode of the transistor 162 are electrically connected. The source electrode or drain electrode of the transistor 162 and the capacitor The first terminal of the capacitor 254 is electrically connected to the first terminal of the capacitor 254 .

[0124] The transistor 162 using an oxide semiconductor for a wide-gap semiconductor layer has an off-state current Therefore, the transistor 162 is turned off. As a result, the potential of the first terminal of the capacitor 254 (or the potential stored in the capacitor 254) It is possible to hold the charge (or charge) for an extremely long period of time. In the transistor 162 using an oxide semiconductor for a conductor layer, the short channel effect is unlikely to occur. There is also the advantage that

[0125] Next, information is written and held in the semiconductor device (memory cell 250) shown in FIG. The following describes such a case.

[0126] First, the potential of the word line WL is set to a potential at which the transistor 162 is turned on. This causes the potential of the bit line BL to rise to the potential of the capacitor 254. Then, the potential of the word line WL is applied to the first terminal of the transistor The transistor 162 is turned off by setting the potential at which the transistor 162 is turned off. The potential of the first terminal of the capacitor 254 is held (held).

[0127] Since the off-state current of the transistor 162 is extremely small, the voltage of the first terminal of the capacitor 254 The potential (or charge stored in the capacitor) can be held for a long period of time.

[0128] Next, the reading of information will be described. When the transistor 162 is turned on, The bit line BL and the capacitor 254 are electrically connected to each other. The charge is redistributed between bit line BL and bit line BL. As a result, the potential of bit line BL changes. The change in potential is proportional to the potential of the first terminal of the capacitor 254 (or the potential of the capacitor 254). It takes on different values ​​depending on the amount of charge stored.

[0129] For example, the potential of the first terminal of the capacitor 254 is V, the capacitance of the capacitor 254 is C, and the bit The capacitance component of the bit line BL (hereinafter also referred to as the bit line capacitance) is CB. If the previous potential of the bit line BL is VB0, then the potential of the bit line BL after the charge is redistributed is Therefore, the state of memory cell 250 is The potential of the first terminal of the capacitor 254 has two states, V1 and V0 (V1>V0). Then, the potential of the bit line BL when the potential V1 is held is (=CB*VB0+C* V1) / (CB+C)) is the potential of the bit line BL when the potential V0 is maintained (=CB *VB0+C*V0) / (CB+C)).

[0130] Then, by comparing the potential of the bit line BL with a predetermined potential, information can be read out. do.

[0131] As described above, in the semiconductor device illustrated in FIG. 4A, the off-state current of the transistor 162 is extremely small. Due to its small size, the charge stored in the capacitor 254 can be maintained for a long period of time. In other words, refresh operations are not required or the frequency of refresh operations can be reduced. Since it is possible to reduce the power consumption to an extremely low level, the power consumption can be reduced sufficiently. In addition, even if there is no power supply, the memory contents can be retained for a long period of time. be.

[0132] Next, the semiconductor device shown in FIG. 4B will be described.

[0133] The semiconductor device shown in FIG. 4B has the memory cell 2 shown in FIG. 4A as a memory element in the upper portion. 4A, a memory cell array 251 having a plurality of 50, and A memory cell array 252 having a plurality of memory cells is provided at the bottom. The peripheral circuit 253 required for operating the rechargeable cell array 252 is also included. In this embodiment, the memory cell array 252 is a memory cell array 251 and a peripheral circuit 253. However, since it is located above the peripheral circuit 253, the memory cell Assume that the array 251 and the memory cell array 252 are located at the top.

[0134] By using the configuration shown in FIG. 4B, the peripheral circuit 253 is connected to the memory cell array 251, In addition, the memory cell array 252 can be provided directly below the memory cell array 252. The semiconductor device can be made smaller by forming the memory cell array 252 and the memory cell array 251 into a stacked structure. It is possible.

[0135] Next, a specific structure of the semiconductor device shown in FIG. 4B will be described with reference to FIG.

[0136] The semiconductor device shown in FIG. 5 has a plurality of memory cells (memory cells 452) formed in a multi-layer structure on the upper portion. The lower peripheral circuit 400 is a memory cell 452b. 400 includes a transistor 450 made of a first semiconductor material, which is formed in a multilayer on top of The plurality of memory cells (memory cell 452a and memory cell 452b) are The transistor 162 is made of the material. FIG. 5 corresponds to a cross-sectional view perpendicular to the channel length direction of the transistor.

[0137] Here, the first semiconductor material and the second semiconductor material may be materials having different forbidden band widths. For example, the first semiconductor material may be a semiconductor material other than an oxide semiconductor (such as silicon). The second semiconductor material can be an oxide semiconductor. The transistors used in this study can easily operate at high speed. The characteristics of the charge storage capacitor enable it to retain electric charge for a long period of time.

[0138] In addition, the transistor 162 having the second semiconductor material in the upper portion is the same as that in the first to third embodiments. Since the transistor 162 is the same as that described in the third embodiment, the transistor 162 in FIG. The same parts are designated by the same reference numerals, and detailed explanations are omitted. A transistor 450 using a conductive material will be described below.

[0139] The transistor 450 in FIG. 5 is formed on a substrate 4 comprising a semiconductor material (e.g., silicon). 02 and a channel forming region 404 provided between the The impurity region 406 and the high-concentration impurity region 408 (collectively referred to as the impurity region) A metal compound region 410 in contact with the high concentration impurity region 408, and a channel-shaped A gate insulating layer 411 is provided on the gate insulating region 404. A gate electrode layer 412 electrically connected to the impurity region and a source electrode or a drain electrode It has an electrode 418a and a source or drain electrode 418b.

[0140] Here, a sidewall insulating layer 414 is provided on the side surface of the gate electrode layer 412 . In addition, an element isolation insulating layer 403 is provided on the substrate 402 so as to surround the transistor 450. The transistor 450 is covered with an interlayer insulating layer 420 and an interlayer insulating layer 422. A source or drain electrode 418a and a source or drain electrode 418b are provided. The rain electrode 418b is formed through an opening formed in the interlayer insulating layer 420 and the interlayer insulating layer 422. In other words, the source electrode or the drain electrode is electrically connected to the metal compound region 410. The source or drain electrode 418a and the source or drain electrode 418b are formed in the metal compound region 4 10 is electrically connected to the high concentration impurity region 408 and the impurity region 406 Note that a sidewall insulating layer 414 is formed for integration of the transistor 450. In addition, the source electrode of the transistor 450 may not be formed on the interlayer insulating layer 422. and a source or drain electrode 418b. The interlayer insulating layer 422 includes an electrode 424a, an electrode 424b, and an electrode 424c. The electrodes 424a, 424b, and 424c are covered with an insulating layer 425, which is planarized. There are.

[0141] The electrode 424c is electrically connected to the electrode 428 via a connection electrode 426. The electrode 428 is formed in the same layer as the source and drain electrode layers of the transistor 162. It has been made.

[0142] Moreover, the wiring 432 is electrically connected to the electrode 428 via a connection electrode 430. The connection electrode 434 is connected to the source and drain electrode layers of the transistor 162. The electrode 436 is electrically connected to the connection electrode 4 38 is electrically connected to wiring 440 .

[0143] The electrode 424c, the wiring 432, and the wiring 440 provide electrical connection between the memory cells and It is possible to electrically connect the side circuit 400 to the memory cells.

[0144] In the semiconductor device shown in FIG. 5, two memory cells (memory cell 452a and memory Although a configuration in which the cells 452b) are stacked has been illustrated, the number of stacked memory cells is not limited to this. A configuration in which three or more memory cells are stacked may also be used.

[0145] In the semiconductor device shown in FIG. 5, the memory cell 452a, the memory cell 452b, and the peripheral For connection to the side circuit 400, an electrode 424c, an electrode 428, a wiring 432, an electrode 436, and Although the configuration in which the connection is made by the wiring 440 has been illustrated, the present invention is not limited to this. Between the memory cell 452a, the memory cell 452b, and the peripheral circuit 400, two or more wiring layers and The insulating film may be provided with an electrode.

[0146] As described above, the memory cells formed in the upper multilayer structure are a wide gap semiconductor layer and The wide band gap semiconductor layer is formed of a transistor using an oxide semiconductor. Since a transistor using an oxide semiconductor as a gate insulating film has a low off-state current, This makes it possible to retain the stored contents for a long period of time. Since the frequency can be made extremely low, power consumption can be reduced sufficiently. On the other hand, semiconductor materials other than oxide semiconductors are used in peripheral circuits. Examples of semiconductor materials other than conductors include silicon, germanium, and silicon germanium. Silicon, silicon carbide, gallium arsenide, or the like can be used, and a single crystal semiconductor can be used. It is preferable to use an organic semiconductor material. Therefore, a transistor made of a material other than an oxide semiconductor can be used. By using transistors that have high speed operation, various circuits (logic circuits, driver circuits, etc.) ) can be suitably realized.

[0147] In this way, transistors using materials other than oxide semiconductors (in other words, transistors that operate at sufficiently high speed) The peripheral circuits are made of transistors that can be operated with a semiconductor oxide. In a broader sense, the off-state current of the transistor is sufficiently small. This makes it possible to realize a semiconductor device having unprecedented features. By forming the gate and the memory circuit in a stacked structure, the integration of the semiconductor device can be promoted.

[0148] This embodiment mode can be implemented in appropriate combination with the configurations described in other embodiments. It is.

[0149] (Embodiment 5) In this embodiment, the semiconductor device described in the above embodiment is applied to a mobile phone, a smartphone, An example of application to a portable device such as an electronic book will be described with reference to FIGS.

[0150] In mobile devices such as mobile phones, smartphones, and e-books, image data is temporarily stored. SRAM or DRAM is used in the following. SRAM or DRAM is used The reason is that flash memory has a slow response time and is not suitable for image processing. On the other hand, when SRAM or DRAM is used for temporary storage of image data, the following characteristics are observed: .

[0151] In a normal SRAM, as shown in FIG. 9A, one memory cell is made up of transistors 801 to 808. It is composed of six transistors, X decoder 807 and Y decoder 807. The transistor 803, the transistor 805, and the transistor 808 are driven by the 4 and transistor 806 form an inverter, enabling high-speed operation. The memory cell is composed of six transistors, so the cell area is large. When the minimum dimension of the design rule is F, the area of ​​the SRAM memory cell is usually 100 ~150F 2 For this reason, SRAM has the highest cost per bit among all types of memory. stomach.

[0152] On the other hand, in a DRAM, the memory cell is made up of a transistor 811, a storage The signal is driven by an X decoder 813 and a Y decoder 814. Each cell is composed of one transistor and one capacitance, and has a small area. The memory cell area of ​​a RAM is usually 10F 2 However, DRAM is always refreshed. It requires a write operation and consumes power even if the data is not being rewritten.

[0153] However, the memory cell area of ​​the semiconductor device described in the above embodiment is 10F 2 Before and after and frequent refresh is not required. Therefore, the memory cell area is reduced, and Power consumption can be reduced.

[0154] Next, FIG. 10 is a block diagram of a portable device. The portable device shown in FIG. 10 includes an RF circuit 901, Analog baseband circuit 902, digital baseband circuit 903, battery 904 , a power supply circuit 905, an application processor 906, a flash memory 910, A spray controller 911, a memory circuit 912, a display 913, a touch sensor 9 19, a voice circuit 917, a keyboard 918, etc. is composed of a display unit 914, a source driver 915, and a gate driver 916. The application processor 906 includes a CPU 907, a DSP 908, and an interface The memory circuit 912 is generally an SRAM or a DRAM. By adopting the semiconductor device described in the previous embodiment for this portion, This allows for high speed writing and reading of information, long-term storage, and low power consumption. The forces can be significantly reduced.

[0155] Next, FIG. 11 shows a semiconductor device according to the above embodiment that is incorporated in a memory circuit 950 of a display. The memory circuit 950 shown in FIG. It is composed of a switch 954, a switch 955 and a memory controller 951. The memory circuit 950 stores image data (input image data) input from a signal line, The data (stored image data) stored in the memory 952 and the memory 953 is read out, and A display controller 956 controls the display. A display 957 that displays the signal is connected.

[0156] First, certain image data is generated by an application processor (not shown). The input image data A is input to the memory 952 via the switch 954. The image data stored in the memory 952 (stored image data A) is then The image is sent to a display 957 via a switch 955 and a display controller 956. , will be displayed.

[0157] When there is no change in the input image data A, the stored image data A usually has a frequency of about 30 to 60 Hz. In the first period, the display controller 956 reads the data from the memory 952 via the switch 955. is read out.

[0158] Next, for example, when the user rewrites the screen (i.e., input image data A If there is a change in the input image data, the application processor The input image data B is stored in the memory 953 via the switch 954. During this time, the stored image data A is periodically read out from the memory 952 via the switch 955. When the new image data (stored image data B) has been stored in the memory 953, From the next frame of the display 957, the stored image data B is read out, and the switch 95 5, and the stored image data is displayed on the display 957 via the display controller 956. Data B is sent and displayed. This readout is followed by the next new image data being stored in the memory. This continues until the data is stored in the memory 952.

[0159] In this way, the memory 952 and the memory 953 alternately write image data and receive image data. The display 957 displays the data by reading the data. The memory 952 and the memory 953 are not limited to being separate memories, but may be divided from one memory. The semiconductor device described in the above embodiment may be used as the memory 952 and the memory 9 By adopting 53, it is possible to write and read information at high speed and to store data for a long period of time. It is possible to maintain the operation time and reduce power consumption sufficiently.

[0160] Next, FIG. 12 is a block diagram of an electronic book. FIG. 12 shows a battery 1001 and a power supply circuit 1002. 002, microprocessor 1003, flash memory 1004, audio circuit 1005, Keyboard 1006, memory circuit 1007, touch panel 1008, display 100 9, and a display controller 1010.

[0161] Here, the semiconductor device described in the previous embodiment is used for the memory circuit 1007 in FIG. The role of the memory circuit 1007 is to temporarily store the contents of the book. An example of a feature is when a user uses the highlight feature. When reading an e-book, you may want to mark a specific part. The highlighting function is called the highlight function, and it can be used to change the display color, underline, make text bold, etc. The aim is to differentiate the device from its surroundings by making it brighter or changing the font of the text. This is a function that memorizes and retains information at specified locations. If you want to store this information for a long period of time, It may be copied to the flash memory 1004. In this case, the same as in the previous embodiment is also possible. By adopting the semiconductor device described in the above embodiment, writing and reading of information can be improved. It is possible to store data quickly and for a long period of time, and the power consumption can be sufficiently reduced.

[0162] As described above, the portable device shown in this embodiment mode is equipped with the semiconductor device according to the above embodiment. This allows for high-speed readout, long-term memory retention, and low power consumption. Thus, a portable device with reduced noise is realized.

[0163] The structures, methods, and the like described in this embodiment may be combined as appropriate with the structures, methods, and the like described in other embodiments. They can be used in combination. EXAMPLES

[0164] In this embodiment, the short channel effect occurs in the transistor having the trench structure shown in the first embodiment. I did some calculations to see if that would work.

[0165] The calculations were performed using Synopsys' device simulation software Sentaurus. Device was used.

[0166] The structure and individual sizes used in the calculation are shown in Figure 6(A). The thickness of the gate insulating layer is 5 nm. The thickness of the wide-gap semiconductor layer is 5 nm, and the depth of the trench for the gate electrode is 0.4 In FIG. 6(A), the length of the bottom of the trench (length in the channel length direction) is set to 90 μm. nm, and the distance between the source and drain electrodes (length in the channel length direction) is 110 nm. This is a transistor with a trench structure. The material of the wide-gap semiconductor layer is In-Ga-Zn -O-based oxide semiconductor (band gap 3.15 eV, electron affinity 4.6 eV, electron mobility 10cm 2 / Vs, electrodes (source and drain electrodes) in contact with the wide-gap semiconductor layer The work function of the gate electrode is set to 5.5 eV. Calculated Vg-Id characteristics (Vds=1V, temperature 27℃) of a 1.5-inch transistor This is shown in Figure 6(B).

[0167] In addition, in FIG. 7(A), the length of the bottom of the trench (length in the channel length direction) is 60 nm, The distance between the source electrode and the drain electrode (length in the channel length direction) is 80 nm. The transistor is the same as in the figure except for the length of the bottom of the trench and the distance between the source electrode and the drain electrode. Figure 7(B) shows the results of calculations performed under the same conditions as in 6(B).

[0168] In addition, in FIG. 8(A), the length of the bottom of the trench (length in the channel length direction) is 30 nm, The distance between the source electrode and the drain electrode (length in the channel length direction) is 50 nm. The transistor is the same as in the figure except for the length of the bottom of the trench and the distance between the source electrode and the drain electrode. Figure 8(B) shows the results of calculations performed under the same conditions as in 6(B).

[0169] As a result of the calculation, the transistor characteristics of all the structures in Fig. 6(A), Fig. 7(A), and Fig. 8(A) are The results were almost the same. The threshold voltage (Vth) of each transistor was 0.8V, and the S value was A good value of 60mV / dec was observed.

[0170] From these calculation results, the distance between the source electrode and the drain electrode (length in the channel length direction) is set to 5 Even if the gate width is narrowed to 0 nm, short channel effects such as negative shift in threshold voltage and increase in S value do not occur. No visible light was observed, and good transistor characteristics were observed.

[0171] For comparison, a similar experiment was performed using a planar transistor structure instead of a trench structure. When the calculation was performed, it was found that narrowing the distance between the source electrode and the drain electrode (length in the channel length direction) As a result, the channel length becomes narrower, and short channel problems such as a negative shift in threshold voltage and an increase in S value occur. The effect is manifested, and the leakage current (off-state current) when a negative bias is applied to the gate An increase in was also confirmed.

[0172] Compared with the calculation results for this comparison, the calculation results of Figs. 6(B), 7(B), and 8(B) In addition, by using the transistor structure shown in Embodiment 1, Even if the spacing between the gate electrodes (length in the channel length direction) is narrowed, the effective channel length does not change much. Therefore, the short channel effect does not occur and the off-current can be suppressed to a low level. Therefore, it is possible to fabricate memory cells with excellent performance. [Explanation of symbols]

[0173] 100 Substrates 108 Gate Insulation Layer 110 Gate electrode 116 Channel formation region 120 Impurity region 124 Metal compound area 126 electrode 130 Insulating layer 142a, 142b electrode 143a, 143b Insulating layer 144 Wide-gap semiconductor layer 146 Gate Insulation Layer 148a, 148b gate electrode 149 Insulating Layer 150 Insulating layer 151 Insulating layer 152 Insulating layer 153 Electrode 154 Electrode 156 Wiring 160 Transistors 161 Element isolation region 162 Transistor 163 Transistor 164 Capacitor 165 Element isolation area 250 memory cells 251 Memory Cell Array 253 Peripheral Circuits 254 Capacitor 310 Semiconductor Substrate 312 STI area 314 Gate Insulation Layer 316 Semiconductor Layer 318 Conductive Layer 320 Protective insulation layer 322 Sidewall insulating layer 324 Impurity region 325 Connection electrode 326 Insulating Layer 328 Electrode 329 Insulating Layer 330 Connection electrode 331 Connection electrode 332 Electrode 334 Connection electrode 336 Electrode 338 Connection Electrode 350 Transistors 400 Peripheral Circuits 402 Substrate 403 Element isolation insulating layer 404 Channel formation region 406 Impurity region 408 High concentration impurity region 410 Metal compounds area 411 Gate insulating layer 412 Gate electrode 414 Sidewall insulating layer 418a Source or drain electrode 418b Source or drain electrode 420 Interlayer insulation layer 422 Interlayer insulation layer 424a electrode 424b electrode 424c electrode 425 Insulating layer 426 Connection electrode 428 Electrode 430 Connection electrode 432 Wiring 434 Connection electrode 436 Electrode 438 Connection Electrode 440 Wiring 450 Transistors 452a Memory Cell 452b memory cell 801 Transistors 803 Transistor 804 Transistor 805 Transistor 806 Transistor 807 X Decoder 808 Y Decoder 811 Transistor 812 holding capacity 813X Decoder 814 Y decoder 901 RF circuit 902 Analog Baseband Circuit 903 Digital Baseband Circuit 904 Battery 905 Power supply circuit 906 Application Processor 907 CPU 908 DSP 909 Interface 910 Flash Memory 911 Display Controller 912 Memory Circuit 913 Display 914 Display section 915 Source Driver 916 Gate Driver 917 Voice Circuit 918 Keyboard 919 Touch Sensor 950 Memory Circuit 951 Memory Controller 952 Memory 953 Memory 954 Switch 955 Switch 956 Display Controller 957 Display 1001 Battery 1002 Power supply circuit 1003 Microprocessor 1004 Flash Memory 1005 Audio Circuit 1006 Keyboard 1007 Memory Circuit 1008 Touch Panel 1009 Display 1010 Display Controller

Claims

1. a first insulating layer having a trench; an oxide semiconductor layer having a region in contact with the first insulating layer on a bottom surface and an inner wall surface of the trench and in contact with an upper surface of the first insulating layer around the trench in a plan view; a first electrode having a region in contact with an upper surface of the oxide semiconductor layer and spaced apart from the trench in a plan view; a second electrode having a region in contact with an upper surface of the oxide semiconductor layer and spaced apart from the trench in a plan view; a gate insulating layer in contact with a bottom surface and an inner wall surface of the oxide semiconductor layer inside the trench, having a region in contact with an upper surface of the oxide semiconductor layer around the trench in a plan view, having a region in contact with a side surface of the first electrode, and having a region in contact with a side surface of the second electrode; a gate electrode having a region embedded in the trench, a region facing a side surface of the first electrode with the gate insulating layer interposed therebetween, and a region facing a side surface of the second electrode with the gate insulating layer interposed therebetween; The band gap of the oxide semiconductor layer is greater than 1.1 eV, the oxide semiconductor layer contains indium oxide, the gate electrode has a region disposed above the first electrode and a region disposed above the second electrode.

2. a first insulating layer having a trench; an oxide semiconductor layer having a region in contact with the first insulating layer on a bottom surface and an inner wall surface of the trench and in contact with an upper surface of the first insulating layer around the trench in a plan view; a first electrode having a region in contact with an upper surface of the oxide semiconductor layer and spaced apart from the trench in a plan view; a second electrode having a region in contact with an upper surface of the oxide semiconductor layer and spaced apart from the trench in a plan view; a gate insulating layer in contact with a bottom surface and an inner wall surface of the oxide semiconductor layer inside the trench, having a region in contact with an upper surface of the oxide semiconductor layer around the trench in a plan view, having a region in contact with a side surface of the first electrode, and having a region in contact with a side surface of the second electrode; a gate electrode having a region embedded in the trench, a region facing a side surface of the first electrode with the gate insulating layer interposed therebetween, and a region facing a side surface of the second electrode with the gate insulating layer interposed therebetween; the gate insulating layer comprises silicon oxide; The band gap of the oxide semiconductor layer is greater than 1.1 eV, the oxide semiconductor layer contains indium oxide, the gate electrode has a region disposed above the first electrode and a region disposed above the second electrode.

3. a first insulating layer having a trench; an oxide semiconductor layer having a region in contact with the first insulating layer on a bottom surface and an inner wall surface of the trench and in contact with an upper surface of the first insulating layer around the trench in a plan view; a first electrode having a region in contact with an upper surface of the oxide semiconductor layer and spaced apart from the trench in a plan view; a second electrode having a region in contact with an upper surface of the oxide semiconductor layer and spaced apart from the trench in a plan view; a gate insulating layer in contact with a bottom surface and an inner wall surface of the oxide semiconductor layer inside the trench, having a region in contact with an upper surface of the oxide semiconductor layer around the trench in a plan view, having a region in contact with a side surface of the first electrode, and having a region in contact with a side surface of the second electrode; a gate electrode having a region embedded in the trench, a region facing a side surface of the first electrode with the gate insulating layer interposed therebetween, and a region facing a side surface of the second electrode with the gate insulating layer interposed therebetween; the gate insulating layer comprises silicon oxide and hafnium oxide; The band gap of the oxide semiconductor layer is greater than 1.1 eV, the oxide semiconductor layer contains indium oxide, the gate electrode has a region disposed above the first electrode and a region disposed above the second electrode.

4. a first transistor and a second transistor on the first transistor; a first insulating layer having a trench; an oxide semiconductor layer that is in contact with the first insulating layer at a bottom surface and an inner wall surface of the trench and has a region that is in contact with an upper surface of the first insulating layer around the trench in a plan view, and has a channel formation region of the second transistor; a first electrode having a region in contact with an upper surface of the oxide semiconductor layer and spaced apart from the trench in a plan view; a second electrode having a region in contact with an upper surface of the oxide semiconductor layer and spaced apart from the trench in a plan view; a gate insulating layer in contact with a bottom surface and an inner wall surface of the oxide semiconductor layer inside the trench, having a region in contact with an upper surface of the oxide semiconductor layer around the trench in a plan view, having a region in contact with a side surface of the first electrode, and having a region in contact with a side surface of the second electrode; a gate electrode of the second transistor, the gate electrode having a region embedded in the trench, a region facing a side surface of the first electrode with the gate insulating layer interposed therebetween, and a region facing a side surface of the second electrode with the gate insulating layer interposed therebetween; The band gap of the oxide semiconductor layer is greater than 1.1 eV, the oxide semiconductor layer contains indium oxide, the gate electrode has a region disposed above the first electrode and a region disposed above the second electrode.

5. a first transistor and a second transistor on the first transistor; a first insulating layer having a trench; an oxide semiconductor layer that is in contact with the first insulating layer at a bottom surface and an inner wall surface of the trench and has a region that is in contact with an upper surface of the first insulating layer around the trench in a plan view, and has a channel formation region of the second transistor; a first electrode having a region in contact with an upper surface of the oxide semiconductor layer and spaced apart from the trench in a plan view; a second electrode having a region in contact with an upper surface of the oxide semiconductor layer and spaced apart from the trench in a plan view; a gate insulating layer in contact with a bottom surface and an inner wall surface of the oxide semiconductor layer inside the trench, having a region in contact with an upper surface of the oxide semiconductor layer around the trench in a plan view, having a region in contact with a side surface of the first electrode, and having a region in contact with a side surface of the second electrode; a gate electrode of the second transistor, the gate electrode having a region embedded in the trench, a region facing a side surface of the first electrode with the gate insulating layer interposed therebetween, and a region facing a side surface of the second electrode with the gate insulating layer interposed therebetween; the gate insulating layer comprises silicon oxide; The band gap of the oxide semiconductor layer is greater than 1.1 eV, the oxide semiconductor layer contains indium oxide; the gate electrode has a region disposed above the first electrode and a region disposed above the second electrode.

6. a first transistor and a second transistor on the first transistor; a first insulating layer having a trench; an oxide semiconductor layer that is in contact with the first insulating layer at a bottom surface and an inner wall surface of the trench and has a region that is in contact with an upper surface of the first insulating layer around the trench in a plan view, and has a channel formation region of the second transistor; a first electrode having a region in contact with an upper surface of the oxide semiconductor layer and spaced apart from the trench in a plan view; a second electrode having a region in contact with an upper surface of the oxide semiconductor layer and spaced apart from the trench in a plan view; a gate insulating layer in contact with a bottom surface and an inner wall surface of the oxide semiconductor layer inside the trench, having a region in contact with an upper surface of the oxide semiconductor layer around the trench in a plan view, having a region in contact with a side surface of the first electrode, and having a region in contact with a side surface of the second electrode; a gate electrode of the second transistor, the gate electrode having a region embedded in the trench, a region facing a side surface of the first electrode with the gate insulating layer interposed therebetween, and a region facing a side surface of the second electrode with the gate insulating layer interposed therebetween; the gate insulating layer comprises silicon oxide and hafnium oxide; The band gap of the oxide semiconductor layer is greater than 1.1 eV, the oxide semiconductor layer contains indium oxide, the gate electrode has a region disposed above the first electrode and a region disposed above the second electrode.

7. a first transistor and a second transistor on the first transistor; a channel formation region of the first transistor includes silicon; a first insulating layer having a trench; an oxide semiconductor layer that is in contact with the first insulating layer at a bottom surface and an inner wall surface of the trench and has a region that is in contact with an upper surface of the first insulating layer around the trench in a plan view, and has a channel formation region of the second transistor; a first electrode having a region in contact with an upper surface of the oxide semiconductor layer and spaced apart from the trench in a plan view; a second electrode having a region in contact with an upper surface of the oxide semiconductor layer and spaced apart from the trench in a plan view; a gate insulating layer in contact with a bottom surface and an inner wall surface of the oxide semiconductor layer inside the trench, having a region in contact with an upper surface of the oxide semiconductor layer around the trench in a plan view, having a region in contact with a side surface of the first electrode, and having a region in contact with a side surface of the second electrode; a gate electrode of the second transistor, the gate electrode having a region embedded in the trench, a region facing a side surface of the first electrode with the gate insulating layer interposed therebetween, and a region facing a side surface of the second electrode with the gate insulating layer interposed therebetween; The band gap of the oxide semiconductor layer is greater than 1.1 eV, the oxide semiconductor layer contains indium oxide, the gate electrode has a region disposed above the first electrode and a region disposed above the second electrode.

8. a first transistor and a second transistor on the first transistor; a channel formation region of the first transistor includes silicon; a first insulating layer having a trench; an oxide semiconductor layer that is in contact with the first insulating layer at a bottom surface and an inner wall surface of the trench and has a region that is in contact with an upper surface of the first insulating layer around the trench in a plan view, and has a channel formation region of the second transistor; a first electrode having a region in contact with an upper surface of the oxide semiconductor layer and spaced apart from the trench in a plan view; a second electrode having a region in contact with an upper surface of the oxide semiconductor layer and spaced apart from the trench in a plan view; a gate insulating layer in contact with a bottom surface and an inner wall surface of the oxide semiconductor layer inside the trench, having a region in contact with an upper surface of the oxide semiconductor layer around the trench in a plan view, having a region in contact with a side surface of the first electrode, and having a region in contact with a side surface of the second electrode; a gate electrode of the second transistor, the gate electrode having a region embedded in the trench, a region facing a side surface of the first electrode with the gate insulating layer interposed therebetween, and a region facing a side surface of the second electrode with the gate insulating layer interposed therebetween; the gate insulating layer comprises silicon oxide; The band gap of the oxide semiconductor layer is greater than 1.1 eV, the oxide semiconductor layer contains indium oxide, the gate electrode has a region disposed above the first electrode and a region disposed above the second electrode.

9. a first transistor and a second transistor on the first transistor; a channel formation region of the first transistor includes silicon; a first insulating layer having a trench; an oxide semiconductor layer that is in contact with the first insulating layer at a bottom surface and an inner wall surface of the trench and has a region that is in contact with an upper surface of the first insulating layer around the trench in a plan view, and has a channel formation region of the second transistor; a first electrode having a region in contact with an upper surface of the oxide semiconductor layer and spaced apart from the trench in a plan view; a second electrode having a region in contact with an upper surface of the oxide semiconductor layer and spaced apart from the trench in a plan view; a gate insulating layer in contact with a bottom surface and an inner wall surface of the oxide semiconductor layer inside the trench, having a region in contact with an upper surface of the oxide semiconductor layer around the trench in a plan view, having a region in contact with a side surface of the first electrode, and having a region in contact with a side surface of the second electrode; a gate electrode of the second transistor, the gate electrode having a region embedded in the trench, a region facing a side surface of the first electrode with the gate insulating layer interposed therebetween, and a region facing a side surface of the second electrode with the gate insulating layer interposed therebetween; the gate insulating layer comprises silicon oxide and hafnium oxide; The band gap of the oxide semiconductor layer is greater than 1.1 eV, the oxide semiconductor layer contains indium oxide, the gate electrode has a region disposed above the first electrode and a region disposed above the second electrode.

10. In any one of claims 7 to 9, A semiconductor integrated circuit, wherein a channel formation region of the first transistor is provided on a silicon substrate.

11. In any one of claims 1 to 10, The semiconductor integrated circuit, wherein the oxide semiconductor layer has a single crystal structure.

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