Error Correction Circuit

Abstract

An error correction circuit capable of changing correction performance according to line conditions and required performance is provided. [Solution] An error correction circuit 3 includes soft decision decoding units 230-235 each having a plurality of threshold tables 230a-230d, 231a-231d, 232a-232d, 233a-233d, 234a-234d, 235a-235d therein. Each soft decision decoding unit 230-235 selects one of the plurality of threshold tables 230a-230d, 231a-231d, 232a-232d, 233a-233d, 234a-234d, 235a-235d to increase or decrease the amount of error correction, thereby reducing erroneous correction.

Description

[Technical field]

[0001] The present invention relates to an error correction circuit for a digital coherent optical transmission system. On the road This is related to. [Background technology]

[0002] In coherent optical communication, in order to improve transmission characteristics, distortion and frequency / phase fluctuations that occur during transmission are compensated for by digital signal processing, and to further improve transmission characteristics, in addition to the above compensation function, an error correction device is installed between the transmitter and receiver to reduce data errors in the transmission characteristics. In general, the transmission side applies error correction coding to the data, and the receiving side applies error correction according to that coding, thereby improving transmission characteristics.

[0003] Well-known error correction methods include, for example, Hamming code, BCH code, Reed-Solomon code, convolutional code / Viterbi decoding, etc. In particular, in recent communication devices, the development of CPU computing power has made it possible to perform complex and large-volume processing, and high-performance error correction methods such as LDPC (low-density parity-check code) are used. Error correction processing includes hard decision, which performs correction processing based on the results of decoding to "1" or "0", and soft decision, which performs correction processing based on the coordinates on the complex plane of the received signal (before it is decoded to "1" or "0") (see Patent Document 1).

[0004] In soft-decision error correction processing, if it is a software process, the amount of correction can be adjusted by changing the multiplication coefficient for calculating the correction threshold. On the other hand, when implementing soft-decision error correction processing in hardware, it is difficult to implement a multiplication circuit that operates at high speeds, especially at a throughput of 1 Tbps.

[0005] For this reason, conventional digital coherent optical transmission systems generally implement soft-decision error correction circuits with a fixed correction threshold, which means that the correction performance cannot be changed according to line conditions or required performance.In addition, increasing the amount of correction also increases the number of miscorrections, which causes an error floor, resulting in degradation of performance. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] Patent No. 7179934 Summary of the Invention [Problem to be solved by the invention]

[0007] The present invention has been made to solve the above problems, and provides an error correction circuit capable of changing correction performance according to line conditions and required performance. The road The purpose is to provide. [Means for solving the problem]

[0008] The error correction circuit of the present invention comprises: a plurality of cascade-connected soft-decision decoding units, each of which performs error correction on a bit of data output from a previous stage, the bit having a smaller likelihood information value than a threshold value; different The above Multiple threshold tables that store thresholds Inside By selecting one of the plurality of threshold tables, the amount of error correction is increased or decreased, thereby reducing miscorrections. Furthermore, in one configuration example of the error correction circuit of the present invention, each of the plurality of soft-decision decoding units selects one of the plurality of threshold tables in its own circuit in accordance with a threshold control signal supplied from outside, thereby setting the threshold of each soft-decision decoding unit to be smaller than when the number of the soft-decision decoding units cascade-connected is small. Moreover, one configuration example of the error correction circuit of the present invention is characterized in that it further includes one or more hard-decision decoding units, and the one or more hard-decision decoding units are cascaded following the soft-decision decoding unit in the final stage.

[0009] In addition, in one configuration example of the error correction circuit of the present invention, each of the plurality of soft-decision decoding units selects one of the plurality of threshold tables in its own circuit in accordance with a threshold control signal supplied from outside, so that the thresholds of the plurality of soft-decision decoding units are set to increase stepwise toward the later stages. Moreover, one configuration example of the error correction circuit of the present invention is characterized in that it further includes a plurality of switches for individually setting whether or not to skip the plurality of soft decision decoding units in accordance with a switch control signal supplied from the outside. In addition, in one configuration example of the error correction circuit of the present invention, the multiple switches are set so that there are one or more soft decision decoding units that do not skip and one or more soft decision decoding units that do skip, and each of the multiple soft decision decoding units selects one of the multiple threshold tables in its own circuit in accordance with a threshold control signal supplied from the outside, so that the threshold of at least one of the soft decision decoding units that does not skip is set to be larger than when the number of the soft decision decoding units connected in cascade is large.

[0010] Moreover, one configuration example of the error correction circuit of the present invention is characterized in that it further includes a plurality of switches for individually setting whether or not to skip the plurality of soft decision decoding units and the one or more hard decision decoding units in accordance with a switch control signal supplied from the outside. In addition, in one configuration example of the error correction circuit of the present invention, the multiple switches are configured to cascade-connect the multiple soft-decision decoding units and skip the one or more hard-decision decoding units, and each of the multiple soft-decision decoding units selects one of the multiple threshold tables in its own circuit in accordance with a threshold control signal supplied from outside, so that the thresholds of the multiple soft-decision decoding units increase stepwise toward the later stage, and the threshold of at least one of the soft-decision decoding units is set to be larger than the case in which the one or more hard-decision decoding units are not skipped. Effect of the Invention

[0012] According to the present invention, by providing an error correction circuit with multiple threshold tables that store different threshold values, when the error correction circuit is implemented in hardware, it becomes possible to change the correction performance according to line conditions and required performance. [Brief description of the drawings]

[0013] [Figure 1] FIG. 1 is a block diagram showing a configuration of a transmitting device according to a first embodiment of the present invention. [Diagram 2] FIG. 2 is a block diagram showing a configuration of a receiving device according to a first embodiment of the present invention. [Diagram 3] FIG. 3 is a block diagram showing a configuration of an error correction circuit according to a first embodiment of the present invention. [Figure 4] FIG. 4 is a flowchart illustrating the operation of the error correction circuit according to the first embodiment of the present invention. [Diagram 5] FIG. 5 is a block diagram showing a configuration of an error correction coding circuit according to a first embodiment of the present invention. [Figure 6] FIG. 6 is a block diagram showing a configuration of an error correction circuit according to a third embodiment of the present invention. [Figure 7] FIG. 7 is a flowchart illustrating the operation of the error correction circuit according to the third embodiment of the present invention. [Figure 8] FIG. 8 is a block diagram showing a configuration of an error correction circuit according to a fourth embodiment of the present invention. [Figure 9] FIG. 9 is a flowchart illustrating the operation of the error correction circuit according to the fourth embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0014] [First Example] Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing the configuration of a transmitting device in a communication system according to a first embodiment of the present invention. The communication system is composed of a transmitting device 1 and a receiving device. The transmitting device 1 generates a transmission signal by encoding and modulating transmission data. The transmission signal is received by the receiving device via a wired or wireless communication path. The receiving device demodulates and decodes the received signal to generate received data.

[0015] The transmitting device 1 includes an error correction coding circuit 10, a symbol mapping circuit 11, a modulation circuit 12, and a DA conversion circuit 13. The error correction coding circuit 10 performs, for example, turbo coding or LDPC (Low Density Parity Check) coding on the transmission data to generate coded data.

[0016] The symbol mapping circuit 11 performs carrier modulation by allocating the coded data output from the error correction coding circuit 10 to symbol points such as QPSK (Quadrature Phase Shift Keying) and 16QAM (Quadrature Amplitude Modulation). The modulation circuit 12 performs, for example, OFDM (Orthogonal Frequency Division Multiplexing) modulation on the data carrier-modulated by the symbol mapping circuit 11, thereby generating a modulated signal.

[0017] The DA conversion circuit 13 converts the modulated signal from a digital signal to an analog signal to generate a transmission signal. The transmission signal is converted to an optical signal by an optical transmission module (not shown) and sent to an optical fiber transmission line.

[0018] 2 is a block diagram showing the configuration of a receiver in a communication system according to this embodiment. The receiver 2 includes an AD conversion circuit 20, a demodulation circuit 21, a symbol demapping circuit 22, an error correction circuit 23, and a control circuit 24.

[0019] An optical receiving module (not shown) of the receiving device 2 converts an optical signal received from an optical fiber transmission line into an analog received signal. The AD conversion circuit 20 converts the analog received signal into a digital signal. The demodulation circuit 21 performs demodulation processing corresponding to the OFDM modulation performed on the transmitting device 1 side on the signal output from the AD conversion circuit 20, and outputs the demodulated received signal to the symbol demapping circuit 22.

[0020] The symbol demapping circuit 22 outputs a bit string corresponding to an ideal signal point that is closest to the received signal (received symbol) by hard decision from the received signal output from the demodulation circuit 21. The error correction circuit 23 performs error correction decoding processing on the bit string output from the symbol demapping circuit 22 based on the likelihood information for each bit of the bit string.

[0021] 3 is a block diagram showing the configuration of the error correction circuit 23 of this embodiment. The error correction circuit 23 is made up of a plurality of cascaded soft decision decoders (SD-DEC) 230-235, and hard decision decoders (HD-DEC) 236, 237 cascaded after the final soft decision decoder 235. The number of hard decision decoders may be one or more, and the hard decision decoder may not be provided.

[0022] The soft decision decoding unit 230 includes four threshold tables 230a to 230d that store different threshold values, and can select one of the threshold tables 230a to 230d by a threshold control signal input from the outside. Similarly, the soft decision decoding units 231 to 235 include threshold tables 231a to 231d, 232a to 232d, 233a to 233d, 234a to 234d, and 235a to 235d, respectively, and can select one of the threshold tables 231a to 231d, 232a to 232d, 233a to 233d, 234a to 234d, and 235a to 235d by a threshold control signal input from the outside.

[0023] 4 is a flow chart for explaining the operation of the error correction circuit 23 in this embodiment. In this embodiment, the threshold value stored in the threshold table 230a, 231a, 232a, 233a, 234a, 235a is 10%, the threshold value stored in the threshold table 230b, 231b, 232b, 233b, 234b, 235b is 20%, the threshold value stored in the threshold table 230c, 231c, 232c, 233c, 234c, 235c is 30%, and the threshold value stored in the threshold table 230d, 231d, 232d, 233d, 234d, 235d is 40%. Here, the threshold value is set in 10% increments, but the range of the threshold value (10% to 40%) and the increment width (10%) are not limited to the values ​​in this embodiment.

[0024] First, the control circuit 24 of the receiving device 2 provides a threshold control signal to the soft decision decoding units 230-235 of the error correction circuit 23 according to an instruction from the user or designer of the receiving device 2. As a result, the soft decision decoding units 230-235 select one of the four threshold tables 230a-230d, 231a-231d, 232a-232d, 233a-233d, 234a-234d, and 235a-235d that they each have. In this embodiment, it is assumed that the soft decision decoding units 230-235 select the threshold tables 230b, 231b, 232b, 233b, 234b, and 235b, respectively. As a result, the thresholds of the soft decision decoding units 230-235 are each set to 20% (step S100 in FIG. 4).

[0025] Next, during operation of the receiving device 2 after the threshold is set, the first-stage soft decision decoding unit 230 calculates likelihood information indicating the likelihood of each bit of the data (symbol) output from the symbol demapping circuit 22, and performs error correction decoding processing on the data output from the symbol demapping circuit 22 based on the likelihood information (FIG. 4, step S101). A method for calculating the likelihood information is disclosed in, for example, Patent Document 1. The soft decision decoding unit 230 performs error correction on bits whose likelihood information value is smaller than the set threshold (20%). The soft decision decoding unit 230 outputs the data after error correction decoding.

[0026] The second-stage soft decision decoding unit 231 calculates likelihood information for each bit of the error-correction-decoded data output from the soft decision decoding unit 230, and performs error correction decoding processing on the data output from the soft decision decoding unit 230 based on the likelihood information (FIG. 4, step S102). The soft decision decoding unit 231 performs error correction on bits whose likelihood information value is smaller than a set threshold (20%). The soft decision decoding unit 231 outputs the error-correction-decoded data.

[0027] The third-stage soft decision decoding unit 232 calculates likelihood information for each bit of the error-correction-decoded data output from the soft decision decoding unit 231, and performs error correction decoding processing on the data output from the soft decision decoding unit 231 based on the likelihood information (FIG. 4, step S103). The soft decision decoding unit 232 performs error correction on bits whose likelihood information value is smaller than a set threshold (20%). The soft decision decoding unit 232 outputs the error-correction-decoded data.

[0028] The fourth-stage soft decision decoding unit 233 calculates likelihood information for each bit of the error-correction-decoded data output from the soft decision decoding unit 232, and performs error correction decoding processing on the data output from the soft decision decoding unit 232 based on the likelihood information (FIG. 4, step S104). The soft decision decoding unit 233 performs error correction on bits whose likelihood information value is smaller than a set threshold (20%). The soft decision decoding unit 233 outputs the error-correction-decoded data.

[0029] The fifth-stage soft decision decoding unit 234 calculates likelihood information for each bit of the error-correction-decoded data output from the soft decision decoding unit 233, and performs error correction decoding processing on the data output from the soft decision decoding unit 233 based on the likelihood information (FIG. 4, step S105). The soft decision decoding unit 234 performs error correction on bits whose likelihood information value is smaller than a set threshold (20%). The soft decision decoding unit 234 outputs the error-correction-decoded data.

[0030] The soft decision decoding unit 235 in the sixth stage calculates likelihood information for each bit of the data after error correction decoding output from the soft decision decoding unit 234, and performs error correction decoding processing on the data output from the soft decision decoding unit 234 based on the likelihood information (step S106 in FIG. 4). The soft decision decoding unit 235 performs error correction on bits whose likelihood information value is smaller than a set threshold (20%). The soft decision decoding unit 235 outputs the data after error correction decoding.

[0031] The seventh-stage hard-decision decoding unit 236 performs error correction decoding processing by hard decision on the error-correction-decoded data output from the soft-decision decoding unit 235, and outputs the error-correction-decoded data (step S107 in FIG. 4).

[0032] The hard-decision decoding unit 237 in the eighth stage performs error correction decoding processing by hard decision on the error-correction-decoded data output from the hard-decision decoding unit 236, and outputs the error-correction-decoded data (step S108 in FIG. 4).

[0033] As described above, in this embodiment, by providing multiple threshold tables, each storing a different threshold value, in the soft decision decoding units 230 to 235, when the error correction circuit 23 is realized in hardware, it becomes possible to change the correction performance according to the line conditions and the required performance.

[0034] In order to comply with this embodiment, on the transmitting device 1 side, the error correction coding circuit 10 must sequentially perform coding corresponding to the hard decision decoding unit 237, coding corresponding to the hard decision decoding unit 236, coding corresponding to the soft decision decoding unit 235, coding corresponding to the soft decision decoding unit 234, coding corresponding to the soft decision decoding unit 233, coding corresponding to the soft decision decoding unit 232, coding corresponding to the soft decision decoding unit 231, and coding corresponding to the soft decision decoding unit 230 on the transmission data.

[0035] 5 shows an example of the error correction coding circuit 10. The error correction coding circuit 10 is made up of an error correction coding unit 100 corresponding to the hard decision decoding unit 237, an error correction coding unit 101 corresponding to the hard decision decoding unit 236, an error correction coding unit 102 corresponding to the soft decision decoding unit 235, an error correction coding unit 103 corresponding to the soft decision decoding unit 234, an error correction coding unit 104 corresponding to the soft decision decoding unit 233, an error correction coding unit 105 corresponding to the soft decision decoding unit 232, an error correction coding unit 106 corresponding to the soft decision decoding unit 231, and an error correction coding unit 107 corresponding to the soft decision decoding unit 230.

[0036] In this embodiment, the number of stages of the soft decision decoding unit is six, and the threshold of each soft decision decoding unit is 20%, but the present invention is not limited to this. For example, the number of stages of the soft decision decoding unit may be three, and the threshold of each soft decision decoding unit may be 30%. Also, the number of stages of the soft decision decoding unit may be seven, and the threshold of each soft decision decoding unit may be 20%. In this way, by setting the threshold of each soft decision decoding unit to be smaller than when the number of stages of the soft decision decoding unit is small (three stages in the above example), the correction ability can be improved.

[0037] [Second Example] Next, a second embodiment of the present invention will be described. In this embodiment, the configurations of the transmitting device 1 and the receiving device 2 are similar to those in the first embodiment. In this embodiment, the control circuit 24 of the receiving device 2 provides a threshold control signal to the soft decision decoding units 230-235 of the error correction circuit 23, and causes the soft decision decoding units 230-235 to select the threshold tables 230b, 231b, 232c, 233c, 234d, and 235d, respectively. As a result, the thresholds of the soft decision decoding units 230 and 231 are set to 20%, the thresholds of the soft decision decoding units 232 and 233 are set to 30%, and the thresholds of the soft decision decoding units 234 and 235 are set to 40% (step S100 in FIG. 4). Other operations are the same as those in the first embodiment.

[0038] In this embodiment, the thresholds of the soft decision decoding units 230 to 235 are gradually increased toward the later stages, thereby improving the error correction performance more than in the first embodiment. Since increasing the amount of error correction also increases miscorrections, increasing the amount of error correction in the later stages can increase the amount of error correction while suppressing miscorrections.

[0039] [Third Example] Next, a third embodiment of the present invention will be described. Fig. 6 is a block diagram showing the configuration of an error correction circuit 23 of a receiving device 2 according to a third embodiment of the present invention, and the same components as those in Fig. 3 are given the same reference numerals.

[0040] The error correction circuit 23 of this embodiment is made up of soft decision decoding units 230 to 235, hard decision decoding units 236 and 237, and switches 238 to 244. In order to simplify the illustration, the threshold value tables in the soft decision decoding units 230 to 235 are omitted in FIG.

[0041] The switch 238 selects either the output of the soft decision decoding unit 230 or the output of the soft decision decoding unit 231 and inputs it to the soft decision decoding unit 232. The switch 239 selects either the output of the switch 238 or the output of the soft decision decoding unit 232 and inputs it to the soft decision decoding unit 233. The switch 240 selects either the output of the switch 239 or the output of the soft decision decoding unit 233 and inputs it to the soft decision decoding unit 234. The switch 241 selects either the output of the switch 240 or the output of the soft decision decoding unit 234 and inputs it to the soft decision decoding unit 235. The switch 242 selects either the output of the switch 241 or the output of the soft decision decoding unit 235 and inputs it to the hard decision decoding unit 236. The switch 243 selects either the output of the switch 242 or the output of the hard decision decoding unit 236 and inputs it to the hard decision decoding unit 237. The switch 244 selects either the output of the switch 243 or the output of the hard decision decoding unit 236.

[0042] FIG. 7 is a flow chart for explaining the operation of the error correction circuit 23 in this embodiment. First, the control circuit 24 of the receiving device 2 provides switch control signals to the switches 238-244 of the error correction circuit 23 in response to an instruction from the user or designer of the receiving device 2. In this embodiment, the switches 238 and 239 select the outputs of the soft decision decoding units 231 and 232, respectively. The switches 240-242 select the outputs of the switches 239-241, respectively. The switches 243 and 244 select the outputs of the hard decision decoding units 236 and 237, respectively (step S100a in FIG. 7). By setting the switches 238-244 in this way, the soft decision decoding units 233-235 are skipped and set not to be used.

[0043] Similarly to the first and second embodiments, the control circuit 24 provides threshold control signals to the soft decision decoding units 230-235 of the error correction circuit 23. In this embodiment, it is assumed that the soft decision decoding units 230-232 select the threshold tables 230d, 231d, and 232d, respectively. As a result, the thresholds of the soft decision decoding units 230-232 are each set to 40% (step S100a).

[0044] The processes of steps S101 to S103, S107, and S108 during operation of the receiving device 2 after the switch settings and threshold settings are the same as those in the first embodiment.

[0045] As described above, in this embodiment, the switches 238-244 for selecting whether or not to skip the decoding units 231-237 are provided at the rear of each of the decoding units 231-237. This makes it possible to vary the number of iterations of error correction. Between the soft decision decoding unit and the hard decision decoding unit, the soft decision decoding unit consumes more power. Therefore, in this embodiment, by setting not to use the soft decision decoding units 233-235, it is possible to reduce power consumption more than in the first embodiment. The magnitude of the threshold does not affect power consumption. Therefore, instead of using the soft decision decoding units 233-235, the threshold of the soft decision decoding units 230-232 that are not skipped is increased from 20% to 40% to increase the amount of correction, thereby reducing power consumption and achieving error correction capability equivalent to that of the first embodiment.

[0046] In order to comply with this embodiment, on the transmitting device 1 side, the error correction coding circuit 10 must sequentially perform coding corresponding to the hard decision decoding unit 237, coding corresponding to the hard decision decoding unit 236, coding corresponding to the soft decision decoding unit 232, coding corresponding to the soft decision decoding unit 231, and coding corresponding to the soft decision decoding unit 230 on the transmission data.

[0047] [Fourth Example] Next, a fourth embodiment of the present invention will be described. Fig. 8 is a block diagram showing the configuration of the error correction circuit 23 of the receiving device 2 according to the fourth embodiment of the present invention, and the same components as those in Figs. 3 and 6 are given the same reference numerals. As in the third embodiment, the error correction circuit 23 is made up of soft decision decoding units 230-235, hard decision decoding units 236, 237, and switches 238-244. In Fig. 8, in order to simplify the description, the threshold table in the soft decision decoding units 230-235 is omitted.

[0048] 9 is a flow chart for explaining the operation of the error correction circuit 23 in this embodiment. First, the control circuit 24 of the receiving device 2 provides switch control signals to the switches 238-244 of the error correction circuit 23 in response to an instruction from the user or designer of the receiving device 2. In this embodiment, the switches 238-242 select the outputs of the soft decision decoding units 231-235, respectively. The switches 243 and 244 select the outputs of the switches 242 and 243, respectively (step S100b in FIG. 9). With such settings of the switches 238-244, the hard decision decoding units 236 and 237 are skipped and set not to be used.

[0049] Similarly to the first to third embodiments, the control circuit 24 provides threshold control signals to the soft decision decoding units 230 to 235 of the error correction circuit 23. In this embodiment, the soft decision decoding unit 230 selects the threshold table 230a, the soft decision decoding units 231 and 232 select the threshold tables 231b and 232b, the soft decision decoding units 233 and 234 select the threshold tables 233c and 234c, and the soft decision decoding unit 235 selects the threshold table 235d. As a result, the threshold of the soft decision decoding unit 230 is set to 10%, the threshold of the soft decision decoding units 231 and 232 is set to 20%, the threshold of the soft decision decoding units 233 and 234 is set to 30%, and the threshold of the soft decision decoding unit 235 is set to 40% (step S100b).

[0050] The processes of steps S101 to S106 during operation of the receiving device 2 after the switch settings and threshold settings are the same as those in the first embodiment.

[0051] As described above, in this embodiment, by setting not to use the hard decision decoding units 236 and 237, it is possible to reduce latency more than in the first embodiment. The magnitude of the threshold does not affect the latency. Therefore, instead of using the hard decision decoding units 236 and 237, the thresholds of the soft decision decoding units 230 to 235 are gradually increased toward the latter stages, and the thresholds of the soft decision decoding units 232 to 235 are made larger than those of the first embodiment to increase the amount of correction, thereby reducing latency and achieving error correction capability equivalent to that of the first embodiment.

[0052] In order to comply with this embodiment, on the transmitting device 1 side, the error correction coding circuit 10 needs to sequentially perform coding corresponding to the soft decision decoding unit 235, coding corresponding to the soft decision decoding unit 234, coding corresponding to the soft decision decoding unit 233, coding corresponding to the soft decision decoding unit 232, coding corresponding to the soft decision decoding unit 231, and coding corresponding to the soft decision decoding unit 230 on the transmission data. [Industrial Applicability]

[0053] The present invention can be applied to a technique for decoding a received signal in a digital coherent optical transmission system. [Explanation of symbols]

[0054] 1... transmitting device, 2... receiving device, 10... error correction coding circuit, 11... symbol mapping circuit, 12... modulation circuit, 13... DA conversion circuit, 20... AD conversion circuit, 21... demodulation circuit, 22... symbol demapping circuit, 23... error correction circuit, 24... control circuit, 230-235... soft decision decoding units, 230a-230d, 231a-231d, 232a-232d, 233a-233d, 234a-234d, 235a-235d... threshold table, 236, 237... hard decision decoding units, 238-244... switches.

Claims

1. In an error correction circuit of a digital coherent optical transmission system, A plurality of soft decision decoding units are connected in cascade, Each of the multiple soft-decision decoding units performs error correction on bits of the data output from the previous stage whose likelihood information value is smaller than a threshold value, and the error correction circuit is characterized in that it has multiple threshold tables internally that store different threshold values, and by selecting one of the multiple threshold tables, the amount of error correction is increased or decreased, thereby reducing miscorrections.

2. 2. The error correction circuit according to claim 1, an error correction circuit characterized in that the threshold of each of the soft-decision decoding units is set to be smaller than when the number of the soft-decision decoding units cascade-connected is small, by selecting one of the multiple threshold tables in the circuit in accordance with a threshold control signal supplied from outside.

3. 2. The error correction circuit according to claim 1, One or more hard decision decoding units are further provided, 13. An error correction circuit, comprising: a soft-decision decoding unit in a final stage, and one or more hard-decision decoding units connected in cascade to the rear of the soft-decision decoding unit in the final stage.

4. 2. The error correction circuit according to claim 1, an error correction circuit characterized in that the thresholds of the soft-decision decoding units are set to increase stepwise toward the later stages by selecting one of the threshold tables in the circuit in accordance with a threshold control signal supplied from outside, the soft-decision decoding units being each set to have a threshold that is gradually increased toward the later stages.

5. 2. The error correction circuit according to claim 1, 11. An error correction circuit, further comprising a plurality of switches for individually setting whether or not to skip the plurality of soft decision decoding units in accordance with a switch control signal supplied from an external device.

6. 6. The error correction circuit according to claim 5, the plurality of switches are set so that there are one or more soft decision decoding units that do not skip and one or more soft decision decoding units that skip, an error correction circuit characterized in that the threshold of at least one of the soft decision decoding units that is not skipped is set to be larger than when the number of the soft decision decoding units connected in cascade is large, by each of the soft decision decoding units selecting one of the multiple threshold tables in its own circuit in accordance with a threshold control signal supplied from outside.

7. 4. The error correction circuit according to claim 3, An error correction circuit further comprising a plurality of switches for individually setting whether or not to skip the plurality of soft decision decoding units and the one or more hard decision decoding units in accordance with a switch control signal supplied from an external device.

8. 8. The error correction circuit according to claim 7, the plurality of switches are configured to cascade-connect the plurality of soft-decision decoding units and to skip the one or more hard-decision decoding units; an error correction circuit characterized in that each of the soft-decision decoding units selects one of the multiple threshold tables in its own circuit in accordance with a threshold control signal supplied from outside, so that the thresholds of the multiple soft-decision decoding units increase gradually toward the later stages, and the threshold of at least one of the soft-decision decoding units is set to be larger than in a case where the one or more hard-decision decoding units are not skipped.

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