Semiconductor Device

Abstract

To provide a semiconductor device which is capable of product-sum operation with less power consumption.SOLUTION: A semiconductor device includes first and second circuits, the first circuit comprising a first holding unit and a first transistor, the second circuit comprising a second holding unit and a second transistor. The first circuit and the second circuit are electrically connected to first and second input wiring and first and second wiring, respectively. The first holding unit has a function of holding a first current flowing in the first transistor. The second holding unit has a function of holding a second current flowing in the second transistor. The first and second currents are determined according to first data. When a potential according to second data is input to the first and second input wiring, the first circuit outputs a current to one of the first and second wiring, and the second circuit outputs a current to the other of the first and second wiring. The amount of the currents output by the first and second circuits to the first and second wiring is determined according to the first data and the second data.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] One embodiment of the present invention relates to a semiconductor device and an electronic device.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. The technical field of the invention disclosed in this specification relates to an object, a method, or a manufacturing method. Alternatively, one embodiment of the present invention relates to a process, a machine, manufacture, or a composition of matter. Therefore, more specifically, examples of the technical field of one embodiment of the present invention disclosed in this specification include semiconductor devices, display devices, liquid crystal display devices, light-emitting devices, power storage devices, imaging devices, memory devices, signal processing devices, processors, electronic devices, systems, driving methods thereof, manufacturing methods thereof, and testing methods thereof. [Background technology]

[0003] Currently, active development is underway on integrated circuits that mimic the workings of the human brain. These integrated circuits incorporate the workings of the brain as electronic circuits, and have circuits that correspond to the "neurons" and "synapses" of the human brain. For this reason, such integrated circuits are sometimes called "neuromorphic," "brain-morphic," or "brain-inspired." These integrated circuits have a non-von Neumann architecture, and are expected to be able to perform parallel processing with significantly less power consumption than von Neumann architectures, which consume more power as processing speed increases.

[0004] An information processing model that mimics a neural network having "neurons" and "synapses" is called an artificial neural network (ANN). For example, Non-Patent Documents 1 and 2 disclose a computing device that configures an artificial neural network using SRAM (Static Random Access Memory). [Prior art documents] [Non-patent literature]

[0005] [Non-Patent Document 1] M. Kang et al., “IEEE Journal Of Solid-State Circuits”, 2018, Volume 53, No.2, p.642-655. [Non-patent document 2] J. Zhang et al., “IEEE Journal Of Solid-State Circuits”, 2017, Volume 52, No.4, p.915-924. Summary of the Invention [Problem to be solved by the invention]

[0006] In an artificial neural network, a calculation is performed in which the connection strength (sometimes called a weighting coefficient) of a synapse connecting two neurons is multiplied by the signal transmitted between the two neurons. In particular, in a hierarchical artificial neural network, it is necessary to multiply and add up each of the connection strengths of the synapses between a plurality of first neurons in a first layer and one of the second neurons in a second layer by each of the signals input from the plurality of first neurons in the first layer to one of the second neurons in the second layer. The number of connection strengths and the number of parameters representing the signals, for example, depend on the scale of the artificial neural network. In other words, the greater the number of layers and neurons in an artificial neural network, the greater the number of circuits corresponding to "neurons" and "synapses," and the greater the amount of calculation required.

[0007] As the number of circuits in a chip increases, power consumption increases and the amount of heat generated during device operation also increases. In particular, the higher the amount of heat generated, the greater the impact on the characteristics of the circuit elements included in the chip. Therefore, it is preferable for the circuits that make up the chip to have circuit elements that are less susceptible to temperature effects. Furthermore, variations in the characteristics of the transistors and current sources included in the chip will also lead to variations in the calculation results.

[0008] An object of one embodiment of the present invention is to provide a semiconductor device or the like in which a hierarchical artificial neural network is built.An object of one embodiment of the present invention is to provide a semiconductor device or the like with low power consumption.An object of one embodiment of the present invention is to provide a semiconductor device or the like that is less susceptible to environmental temperature.An object of one embodiment of the present invention is to provide a semiconductor device or the like that is less susceptible to variations in characteristics of transistors.An object of one embodiment of the present invention is to provide a semiconductor device or the like that is less susceptible to variations in characteristics of current sources.An object of one embodiment of the present invention is to provide a novel semiconductor device or the like.

[0009] Note that the problems of one embodiment of the present invention are not limited to the problems listed above. The problems listed above do not preclude the existence of other problems. Note that the other problems are problems not mentioned in this section, which will be described below. Problems not mentioned in this section can be derived by a person skilled in the art from the description in the specification or drawings, and can be appropriately extracted from these descriptions. Note that one embodiment of the present invention solves at least one of the problems listed above and other problems. Note that one embodiment of the present invention does not necessarily solve all of the problems listed above and other problems. [Means for solving the problem]

[0010] (1) One aspect of the present invention is a semiconductor device having a first circuit and a second circuit, wherein the first circuit has a first holding unit and a first drive transistor, and the second circuit has a second holding unit and a second drive transistor, the first circuit is electrically connected to a first input wiring, a second input wiring, a first wiring, and a second wiring, and the second circuit is electrically connected to the first input wiring, the second input wiring, the first wiring, and the second wiring, the first holding unit has a function of holding a first potential according to a first current flowing from the first wiring between the source and drain of the first drive transistor, The second holding unit has a function of holding a second potential corresponding to a second current flowing from the second wiring between the source and drain of the second drive transistor, the first drive transistor has a function of causing a first current corresponding to the held first potential to flow between the source and drain of the first drive transistor, the second drive transistor has a function of causing a second current corresponding to the held second potential to flow between the source and drain of the second drive transistor, and the first circuit holds a first potential corresponding to a first level potential when a first level potential is input to the first input wiring and a second level potential is input to the second input wiring. The second circuit has a function of outputting a current to the first wiring, a function of outputting a first current to the second wiring when a second level potential is input to the first input wiring and the second input wiring and the first level potential is input to the second input wiring, and a function of not outputting the first current to the first wiring and the second wiring when a second level potential is input to the first input wiring and the second level potential is input to the second input wiring, and and a function of not outputting the second current to the first wiring or the second wiring when the second level potential is input to the first input wiring and the second level potential is input to the second input wiring, wherein the first current and the second current each have a current amount according to first data, and the first level potential and the second level potential input to the first input wiring, the second input wiring, the third input wiring, and the fourth input wiring, respectively, are determined according to the second data.

[0011] (2) Alternatively, one embodiment of the present invention is a semiconductor device including a first circuit and a second circuit, in which the first circuit includes a first holding unit and a first drive transistor, and the second circuit includes a second holding unit and a second drive transistor, the first circuit being electrically connected to a first input wiring, a second input wiring, the first wiring, and a second wiring, and the second circuit being electrically connected to the first input wiring, the second input wiring, the first wiring, and the second wiring, the first holding unit having a function of holding a first potential according to a first current flowing from the first wiring between a source and a drain of the first drive transistor, and the second holding unit having The second drive transistor has a function of holding a second potential corresponding to a second current flowing from the second wiring between the source and drain of the second drive transistor, the first drive transistor has a function of causing a first current to flow between the source and drain of the first drive transistor according to the first potential held, the second drive transistor has a function of causing a second current to flow between the source and drain of the second drive transistor according to the second potential held, and the first circuit causes the first current to flow through the first wiring when a first level potential is input to the first input wiring and a second level potential is input to the second input wiring during a first period. the second circuit has a function of outputting a first current to the second wiring when a second level potential is input to the first input wiring and the first level potential is input to the second input wiring during the first period, and a function of not outputting the first current to the first wiring and the second wiring when a second level potential is input to the first input wiring and the second level potential is input to the second input wiring during the first period; and a function of not outputting the second current to the first wiring or the second wiring when the second level potential is input to the first input wiring and the first level potential is input to the second input wiring during a first period, wherein the first current and the second current each have a current amount according to first data, and the first level potential and the second level potential input to the first input wiring and the second input wiring, respectively, and the length of the first period are determined according to the second data.

[0012] (3) Alternatively, one embodiment of the present invention is a semiconductor device in the above-described configuration (2), wherein the first period includes a second period and a third period, the first input wiring has a function of applying a first-level potential or a second-level potential to both the first circuit and the second circuit in the second period, the second input wiring has a function of outputting the first-level potential or the second-level potential to both the first circuit and the second circuit in the second period, the first input wiring has a function of applying the first-level potential or the second-level potential to both the first circuit and the second circuit in the third period, and the second input wiring has a function of outputting the first-level potential or the second-level potential to both the first circuit and the second circuit in the third period, and the length of the third period is twice the length of the second period.

[0013] (4) Alternatively, according to one aspect of the present invention, in any one of the configurations (1) to (3) above, the first circuit includes a first transistor, a second transistor, a third transistor, and a first capacitance; the second circuit includes a fourth transistor, a fifth transistor, a sixth transistor, and a second capacitance; the first holding unit includes a first transistor and the first capacitance; the second holding unit includes a fourth transistor and a second capacitance; a first terminal of the first transistor is electrically connected to a first terminal of the first capacitance and to a gate of the first driving transistor; a second terminal of the first transistor is electrically connected to a first wiring; the first terminal of the first driving transistor is electrically connected to a first terminal of the second transistor and a first terminal of the third transistor; the second terminal of the second transistor is electrically connected to the first wiring; a gate of the sixth transistor electrically connected to the first input wiring, a second terminal of the third transistor electrically connected to the second wiring, a gate of the third transistor electrically connected to the second input wiring, a first terminal of the fourth transistor electrically connected to a first terminal of the second capacitor and a gate of the second drive transistor, a second terminal of the fourth transistor electrically connected to the second wiring, a first terminal of the second drive transistor electrically connected to a first terminal of the fifth transistor and a first terminal of the sixth transistor, a second terminal of the fifth transistor electrically connected to the second wiring, a gate of the fifth transistor electrically connected to the first input wiring, a second terminal of the sixth transistor electrically connected to the first wiring, and a gate of the sixth transistor electrically connected to the second input wiring.

[0014] (5) Alternatively, one aspect of the present invention is a semiconductor device having the configuration of (4) above, wherein the first circuit has a seventh transistor, the second circuit has an eighth transistor, a first terminal of the seventh transistor is electrically connected to a first terminal of the first driving transistor, a first terminal of the second transistor, and a first terminal of the third transistor, a second terminal of the seventh transistor is electrically connected to one of the first terminal or the second terminal of the first transistor, a first terminal of the eighth transistor is electrically connected to a first terminal of the second driving transistor, a first terminal of the fifth transistor, and a first terminal of the sixth transistor, a second terminal of the eighth transistor is electrically connected to one of the first terminal or the second terminal of the fourth transistor, and a gate of the first transistor is electrically connected to a gate of the fourth transistor, a gate of the seventh transistor, and a gate of the eighth transistor.

[0015] (6) Alternatively, according to one aspect of the present invention, in any one of the configurations (1) to (3) above, the first circuit includes a first transistor, a second transistor, a third transistor, and a first capacitance; the second circuit includes a fourth transistor, a fifth transistor, a sixth transistor, and a second capacitance; the first holding unit includes a first transistor and the first capacitance; the second holding unit includes a fourth transistor and a second capacitance; a first terminal of the first transistor is electrically connected to a first terminal of the first capacitance and a gate of the first driving transistor; a first terminal of the first driving transistor is electrically connected to a second terminal of the first transistor, a first terminal of the second transistor, and a first terminal of the third transistor; a second terminal of the second transistor is electrically connected to the first wiring; a gate of the sixth transistor electrically connected to the first input wiring, a second terminal of the third transistor electrically connected to the second wiring, a gate of the third transistor electrically connected to the second input wiring, a first terminal of the fourth transistor electrically connected to a first terminal of the second capacitor and to a gate of the second drive transistor, a first terminal of the second drive transistor electrically connected to a second terminal of the fourth transistor, a first terminal of the fifth transistor, and a first terminal of the sixth transistor, the second terminal of the fifth transistor electrically connected to the second wiring, a gate of the fifth transistor electrically connected to the first input wiring, a second terminal of the sixth transistor electrically connected to the first wiring, and a gate of the sixth transistor electrically connected to the second input wiring.

[0016] (7) Alternatively, in one aspect of the present invention, in any one of the configurations (1) to (3) above, the first circuit has a third holding unit and a third drive transistor, the second circuit has a fourth holding unit and a fourth drive transistor, the first circuit is electrically connected to the third wiring, the second circuit is electrically connected to the third wiring, the third holding unit has a function of holding a third potential according to a third current flowing from the first wiring between the source and drain of the third drive transistor, and the fourth holding unit has a function of holding a third potential according to a fourth current flowing from the second wiring between the source and drain of the fourth drive transistor. The semiconductor device has a function of holding a fourth potential, and the third drive transistor has a function of passing a third current corresponding to the held third potential between the source and drain of the third drive transistor, and the fourth drive transistor has a function of passing a fourth current corresponding to the held fourth potential between the source and drain of the fourth drive transistor, and has a function of switching a first current flowing in one of the first wiring or the second wiring to the third current, and switching a second current flowing in the other of the first wiring or the second wiring to the fourth current, according to a signal input to the third wiring.

[0017] (8) Alternatively, one embodiment of the present invention is a semiconductor device having any one of the configurations (1) to (7) above, including a third circuit, a fourth circuit, and a fifth circuit. The third circuit has a function of supplying a first current according to first data to the first circuit via a first wiring and a function of supplying a second current according to the first data to the second circuit via a second wiring. The fourth circuit has a function of inputting a first-level potential or a second-level potential to the first input wiring according to the second data and a function of inputting the first-level potential or the second-level potential to the second input wiring according to the second data. The fifth circuit has a function of comparing currents flowing from the first wiring and the second wiring, and outputting a potential according to a product of the first data and the second data from an output terminal of the fifth circuit.

[0018] (9) Alternatively, one aspect of the present invention is a semiconductor device having a first circuit and a second circuit, wherein the first circuit has a first holding unit, a first drive transistor, and a third drive transistor, and the second circuit has a second holding unit, a second drive transistor, and a fourth drive transistor, the first circuit is electrically connected to a first input wiring, a second input wiring, a third input wiring, a fourth input wiring, a first wiring, and a second wiring, and the second circuit is electrically connected to the first input wiring, the second input wiring, the third input wiring, a fourth input wiring, a first wiring, and a second wiring, and the first holding unit transfers a first drive signal from the first wiring to the second input wiring. The second holding unit has a function of holding a first potential corresponding to a first current flowing between the source and drain of the second drive transistor, the second holding unit has a function of holding a second potential corresponding to a second current flowing from the second wiring between the source and drain of the second drive transistor, the first drive transistor has a function of causing a first current corresponding to the held first potential to flow between the source and drain of the first drive transistor, the second drive transistor has a function of causing a second current corresponding to the held second potential to flow between the source and drain of the second drive transistor, and the third drive transistor the fourth drive transistor has a function of causing a third current to flow between the source and drain of the fourth drive transistor in accordance with the held first potential, the fourth drive transistor has a function of causing a fourth current to flow between the source and drain of the fourth drive transistor in accordance with the held second potential, the first circuit has a function of outputting a first current to the first wiring when a first level potential is input to the first input wiring and a second level potential is input to the second input wiring, and a function of outputting a first current to the second wiring when a second level potential is input to the first input wiring and a first level potential is input to the second input wiring, a function of not outputting the first current to the first wiring and the second wiring when a second level potential is input and the second level potential is input to the second input wiring; a function of outputting a third current to the first wiring when a first level potential is input to the third input wiring and the second level potential is input to the fourth input wiring; a function of outputting a third current to the second wiring when a second level potential is input to the third input wiring and the first level potential is input to the fourth input wiring; and a function of outputting the third current to the first wiring and the second wiring when a second level potential is input to the third input wiring and the second level potential is input to the fourth input wiring.and a function of not outputting a second current to the second wiring, and the second circuit has a function of outputting a second current to the second wiring when a first level potential is input to the first input wiring and a second level potential is input to the second input wiring, a function of outputting a second current to the first wiring when a second level potential is input to the first input wiring and a first level potential is input to the second input wiring, a function of not outputting a second current to the first wiring and the second wiring when a second level potential is input to the first input wiring and a second level potential is input to the second input wiring, and a function of outputting a fourth current to the first wiring and the second wiring when a first level potential is input to the third input wiring and a second level potential is input to the fourth input wiring. a function of outputting a fourth current to the first wiring when a second level potential is input to the third input wiring and a first level potential is input to the fourth input wiring, and a function of not outputting the fourth current to the first wiring and the second wiring when the second level potential is input to the third input wiring and the second level potential is input to the fourth input wiring, wherein each of the first current, the second current, the third current, and the fourth current has a current amount according to first data, and the first level potential and the second level potential input to the first input wiring, the second input wiring, the third input wiring, and the fourth input wiring, respectively, are determined according to second data.

[0019] (10) Alternatively, one aspect of the present invention is a semiconductor device having a first circuit and a second circuit, wherein the first circuit has a first holding unit, a first drive transistor, and a third drive transistor, and the second circuit has a second holding unit, a second drive transistor, and a fourth drive transistor, the first circuit is electrically connected to a first input wiring, a second input wiring, a third input wiring, a fourth input wiring, a first wiring, and a second wiring, and the second circuit is electrically connected to the first input wiring, the second input wiring, the third input wiring, a fourth input wiring, a first wiring, and a second wiring, and the first holding unit transfers a first drive signal from the first wiring to the second input wiring. The second holding unit has a function of holding a first potential corresponding to a first current flowing between the source and drain of the second drive transistor, the second holding unit has a function of holding a second potential corresponding to a second current flowing from the second wiring between the source and drain of the second drive transistor, the first drive transistor has a function of causing a first current corresponding to the held first potential to flow between the source and drain of the first drive transistor, the second drive transistor has a function of causing a second current corresponding to the held second potential to flow between the source and drain of the second drive transistor, and the third drive transistor the fourth drive transistor has a function of causing a third current to flow between the source and drain of the fourth drive transistor in accordance with the held first potential, the fourth drive transistor has a function of causing a fourth current to flow between the source and drain of the fourth drive transistor in accordance with the held second potential, the first circuit has a function of outputting a first current to the first wiring when a first level potential is input to the first input wiring and a second level potential is input to the second input wiring during the first period, and a function of outputting the first current to the second wiring when a second level potential is input to the first input wiring and a first level potential is input to the second input wiring during the first period. a function of not outputting a first current to the first wiring and the second wiring when a second level potential is input to the first input wiring and the second level potential is input to the second input wiring during a first period; a function of outputting a third current to the first wiring when a first level potential is input to the third input wiring and the second level potential is input to the fourth input wiring during a first period; a function of outputting a third current to the second wiring when a second level potential is input to the third input wiring and the first level potential is input to the fourth input wiring during a first period;and a function of not outputting a third current to the first wiring and the second wiring when a second level potential is input to the fourth input wiring, and the second circuit has a function of outputting a second current to the second wiring when a first level potential is input to the first input wiring and a second level potential is input to the second input wiring during a first period, a function of outputting a second current to the first wiring when a second level potential is input to the first input wiring and a first level potential is input to the second input wiring during a first period, a function of not outputting the second current to the first wiring and the second wiring when a second level potential is input to the first input wiring and a second level potential is input to the second input wiring during a first period, and a function of outputting a third current to the first wiring and the second wiring when a first level potential is input to the third input wiring and a second level potential is input to the fourth input wiring during a first period. A semiconductor device having a function of outputting a fourth current to the second wiring when a second level potential is input, a function of outputting a fourth current to the first wiring when the second level potential is input to the third input wiring and the first level potential is input to the fourth input wiring during a first period, and a function of not outputting the fourth current to the first wiring and the second wiring when the second level potential is input to the third input wiring and the second level potential is input to the fourth input wiring during a first period, wherein the first current, the second current, the third current, and the fourth current each have a current amount according to first data, and the first level potential, the second level potential input to the first input wiring, the second input wiring, the third input wiring, and the fourth input wiring, and the length of the first period, are determined according to second data.

[0020] (11) Alternatively, in one aspect of the present invention, in the configuration of (10) above, the first period has a second period and a third period, the first input wiring has a function of applying a first level potential or a second level potential to both the first circuit and the second circuit in the second period, the second input wiring has a function of applying a first level potential or a second level potential to both the first circuit and the second circuit in the second period, the third input wiring has a function of applying a first level potential or a second level potential to both the first circuit and the second circuit in the second period, and the fourth input wiring has a function of applying a first level potential or a second level potential to both the first circuit and the second circuit in the second period. the first input wiring has a function of applying a first level potential or a second level potential to both the first circuit and the second circuit in a third period, the second input wiring has a function of applying the first level potential or the second level potential to both the first circuit and the second circuit in the third period, the third input wiring has a function of applying the first level potential or the second level potential to both the first circuit and the second circuit in the third period, and the fourth input wiring has a function of applying the first level potential or the second level potential to both the first circuit and the second circuit in the third period, and the length of the third period is twice the length of the second period.

[0021] (12) Alternatively, one embodiment of the present invention is a semiconductor device having the structure of any one of (9) to (11) above, including a third circuit, a fourth circuit, and a fifth circuit. The third circuit has a function of supplying a first current according to first data to the first circuit via a first wiring and a function of supplying a second current according to the first data to the second circuit via a second wiring. The fourth circuit has a function of inputting a first-level potential or a second-level potential to a first input wiring according to the second data, a function of inputting the first-level potential or the second-level potential to the second input wiring according to the second data, a function of inputting the first-level potential or the second-level potential to the third input wiring according to the second data, and a function of inputting the first-level potential or the second-level potential to the fourth input wiring according to the second data. The fifth circuit has a function of comparing currents flowing from the first wiring and the second wiring, and outputting a potential according to a product of the first data and the second data from an output terminal of the fifth circuit.

[0022] (13) Alternatively, one embodiment of the present invention is a semiconductor device including a first circuit and a second circuit, in which the first circuit includes a first holding unit and a first drive transistor, and the second circuit includes a second holding unit and a second drive transistor, the first circuit being electrically connected to a first input wiring and the first wiring, and the second circuit being electrically connected to the first input wiring and the second wiring, the first holding unit having a function of holding a first potential corresponding to a first current flowing from the first wiring between a source and a drain of the first drive transistor, the second holding unit having a function of holding a second potential corresponding to a second current flowing from the second wiring between a source and a drain of the second drive transistor, the first drive transistor having a function of causing a first current corresponding to the held first potential to flow between the source and a drain of the first drive transistor, the first circuit has a function of outputting the first current to the first wiring when a first level potential is input to the first input wiring, and a function of not outputting the first current to the first wiring when a second level potential is input to the first input wiring; the second circuit has a function of outputting the second current to the second wiring when a first level potential is input to the first input wiring, and a function of not outputting the second current to the second wiring when a second level potential is input to the first input wiring; each of the first current and the second current has a current amount corresponding to first data; and the first level potential and the second level potential input to the first input wiring and the second input wiring, respectively, are determined according to the second data.

[0023] (14) Alternatively, one embodiment of the present invention is a semiconductor device including a first circuit and a second circuit, in which the first circuit includes a first holding unit and a first drive transistor, and the second circuit includes a second holding unit and a second drive transistor, the first circuit being electrically connected to a first input wiring and the first wiring, the second circuit being electrically connected to the first input wiring and the second wiring, the first holding unit having a function of holding a first potential corresponding to a first current flowing from the first wiring between a source and a drain of the first drive transistor, the second holding unit having a function of holding a second potential corresponding to a second current flowing from the second wiring between a source and a drain of the second drive transistor, the first drive transistor having a function of causing a first current corresponding to the held first potential to flow between a source and a drain of the first drive transistor, and the second drive transistor having a function of causing a a first circuit having a function of outputting a first current to a first wiring when a first level potential is input to a first input wiring during a first period, and a function of not outputting the first current to the first wiring when a second level potential is input to the first input wiring during the first period; a second circuit having a function of outputting a second current to a second wiring when a first level potential is input to the first input wiring during a first period, and a function of not outputting the second current to the second wiring when a second level potential is input to the first input wiring during the first period; each of the first current and the second current has a current amount corresponding to first data; and the first level potential and the second level potential input to the first input wiring and the second input wiring, respectively, are determined according to second data.

[0024] (15) Alternatively, one embodiment of the present invention is a semiconductor device in which, in the configuration of (14), the first period includes a second period and a third period, the first input wiring has a function of applying a first level potential or a second level potential to both the first circuit and the second circuit in the second period, the first input wiring has a function of applying the first level potential or the second level potential to both the first circuit and the second circuit in the third period, and the length of the third period is twice the length of the second period.

[0025] (16) Alternatively, according to one aspect of the present invention, in any one of the configurations (13) to (15) above, the first circuit includes a first transistor, a second transistor, and a first capacitance; the second circuit includes a fourth transistor, a fifth transistor, and a second capacitance; the first holding unit includes a first transistor and a first capacitance; the second holding unit includes a fourth transistor and a second capacitance; a first terminal of the first transistor is electrically connected to a first terminal of the first capacitance and a gate of the first driving transistor; a second terminal of the first transistor is electrically connected to a first wiring; and the first terminal of the first driving transistor is electrically connected to a first terminal of the first capacitance and a gate of the second transistor. a first terminal of the fourth transistor electrically connected to a first terminal of the second capacitor and a gate of the second drive transistor, a second terminal of the fourth transistor electrically connected to a first wiring, a gate of the second transistor electrically connected to a first terminal of the second capacitor and a gate of the second drive transistor, a second terminal of the fourth transistor electrically connected to the second wiring, a first terminal of the second drive transistor electrically connected to a first terminal of the fifth transistor, a second terminal of the fifth transistor electrically connected to the second wiring, and a gate of the fifth transistor electrically connected to the first input wiring.

[0026] (17) Another embodiment of the present invention is an electronic device including the semiconductor device according to any one of (1) to (16) above and a housing, in which the semiconductor device performs calculations on a neural network.

[0027] In this specification and the like, a semiconductor device is a device that utilizes semiconductor characteristics, and refers to a circuit including a semiconductor element (transistor, diode, photodiode, etc.), a device having such a circuit, etc. It also refers to any device that can function by utilizing semiconductor characteristics. For example, an integrated circuit, a chip including an integrated circuit, or an electronic component in which a chip is housed in a package are examples of semiconductor devices. Furthermore, memory devices, display devices, light-emitting devices, lighting devices, electronic devices, etc. are themselves semiconductor devices and may include semiconductor devices.

[0028] Furthermore, when it is stated in this specification that X and Y are connected, it is understood that the following cases are disclosed in this specification: when X and Y are electrically connected, when X and Y are functionally connected, and when X and Y are directly connected. Therefore, it is not limited to a predetermined connection relationship, for example, a connection relationship shown in a figure or text, and it is understood that connections other than those shown in a figure or text are also disclosed in a figure or text. X and Y are understood to be objects (e.g., a device, an element, a circuit, wiring, an electrode, a terminal, a conductive film, a layer, etc.).

[0029] As an example of a case where X and Y are electrically connected, one or more elements (for example, a switch, a transistor, a capacitance element, an inductor, a resistance element, a diode, a display device, a light-emitting device, a load, etc.) that enable the electrical connection between X and Y can be connected between X and Y. The switch has a function of controlling on / off. In other words, the switch has a function of being in a conductive state (on state) or a non-conductive state (off state), and controls whether or not a current flows.

[0030] As an example of a case where X and Y are functionally connected, one or more circuits that enable the functional connection between X and Y (for example, logic circuits (inverters, NAND circuits, NOR circuits, etc.), signal conversion circuits (digital-analog conversion circuits, analog-digital conversion circuits, gamma correction circuits, etc.), potential level conversion circuits (power supply circuits (boosting circuits, step-down circuits, etc.), level shifter circuits that change the potential level of signals, etc.), voltage sources, current sources, switching circuits, amplifier circuits (circuits that can increase signal amplitude or current, operational amplifiers, differential amplifier circuits, source follower circuits, buffer circuits, etc.), signal generation circuits, memory circuits, control circuits, etc.) can be connected between X and Y. As an example, even if another circuit is sandwiched between X and Y, if a signal output from X is transmitted to Y, X and Y are considered to be functionally connected.

[0031] Note that when it is explicitly stated that X and Y are electrically connected, this includes the case where X and Y are electrically connected (i.e., when they are connected with another element or another circuit between them), the case where X and Y are functionally connected (i.e., when they are functionally connected with another circuit between them), and the case where X and Y are directly connected (i.e., when they are connected without another element or another circuit between them). In other words, when it is explicitly stated that X and Y are electrically connected, it is the same as when it is simply explicitly stated that they are connected.

[0032] Furthermore, for example, it can be expressed as follows: "X, Y, and the source (or first terminal, etc.) and drain (or second terminal, etc.) of the transistor are electrically connected to each other, and are electrically connected in the order of X, the source (or first terminal, etc.) of the transistor, the drain (or second terminal, etc.) of the transistor, and Y." Or, it can be expressed as follows: "The source (or first terminal, etc.) of the transistor is electrically connected to X, and the drain (or second terminal, etc.) of the transistor is electrically connected to Y, and X, the source (or first terminal, etc.) of the transistor, the drain (or second terminal, etc.) of the transistor, and Y are electrically connected in this order." Or, it can be expressed as follows: "X is electrically connected to Y via the source (or first terminal, etc.) and drain (or second terminal, etc.) of the transistor, and X, the source (or first terminal, etc.) of the transistor, the drain (or second terminal, etc.) of the transistor, and Y are provided in this connection order." By using expressions similar to these examples to define the order of connections in a circuit configuration, the source (or first terminal, etc.) and drain (or second terminal, etc.) of a transistor can be distinguished and the technical scope can be determined. Note that these expressions are merely examples and are not limiting. Here, X and Y are assumed to be objects (e.g., devices, elements, circuits, wiring, electrodes, terminals, conductive films, layers, etc.).

[0033] Note that even when independent components are shown electrically connected in a circuit diagram, one component may have the functions of multiple components. For example, if part of a wiring also functions as an electrode, one conductive film has the functions of both wiring and an electrode. Therefore, the term "electrically connected" in this specification also includes such cases where one conductive film has the functions of multiple components.

[0034] Furthermore, in this specification, etc., the term "resistance element" refers to a circuit element, wiring, etc. that has a resistance value. Therefore, in this specification, etc., the term "resistance element" includes wiring that has a resistance value, a transistor in which a current flows between the source and drain, a diode, a coil, etc. Therefore, the term "resistance element" can be replaced with terms such as "resistance," "load," or "region that has a resistance value," and conversely, the terms "resistance," "load," or "region that has a resistance value" can be replaced with terms such as "resistance element." The resistance value can be, for example, preferably 1 mΩ or more and 10 Ω or less, more preferably 5 mΩ or more and 5 Ω or less, and even more preferably 10 mΩ or more and 1 Ω or less. Furthermore, for example, the resistance value can be, for example, 1 Ω or more and 1×10 9 It may be set to Ω or less.

[0035] Furthermore, in this specification, the term "capacitive element" refers to a circuit element having a capacitance value, a wiring region having a capacitance value, parasitic capacitance, a transistor gate capacitance, etc. Therefore, in this specification, the term "capacitive element" refers not only to a circuit element including a pair of electrodes and a dielectric between the electrodes, but also to a parasitic capacitance appearing between wiring and one of the source or drain of a transistor and the gate, etc. Furthermore, terms such as "capacitive element," "parasitic capacitance," and "gate capacitance" can be replaced with terms such as "capacitance," and conversely, the term "capacitance" can be replaced with terms such as "capacitive element," "parasitic capacitance," and "gate capacitance." Furthermore, the term "pair of electrodes" in "capacitance" can be replaced with "pair of conductors," "pair of conductive regions," "pair of regions," etc. The capacitance value can be, for example, 0.05 fF or more and 10 pF or less. It can also be, for example, 1 pF or more and 10 μF or less.

[0036] In this specification, a transistor has three terminals called a gate, a source, and a drain. The gate is a control terminal that controls the conduction state of the transistor. The two terminals that function as a source or a drain are input / output terminals of the transistor. One of the two input / output terminals serves as a source and the other as a drain depending on the conductivity type (n-channel or p-channel) of the transistor and the level of the potential applied to the three terminals of the transistor. Therefore, in this specification, the terms source and drain are interchangeable. In addition, in this specification, when describing the connection relationship of a transistor, the terms "one of the source or drain" (or first electrode or first terminal) and "the other of the source or drain" (or second electrode or second terminal) are used. Note that, depending on the structure of the transistor, a backgate may be included in addition to the three terminals described above. In this case, in this specification, one of the gate or backgate of the transistor may be referred to as a first gate, and the other of the gate or backgate of the transistor may be referred to as a second gate. Furthermore, for the same transistor, the terms "gate" and "backgate" may be interchangeable. Furthermore, when a transistor has three or more gates, the gates may be referred to as a first gate, a second gate, a third gate, and so on in this specification and the like.

[0037] Furthermore, in this specification and the like, a node can be referred to as a terminal, a wiring, an electrode, a conductive layer, a conductor, an impurity region, etc. depending on the circuit configuration, device structure, etc. Furthermore, a terminal, a wiring, etc. can be referred to as a node.

[0038] Furthermore, in this specification and the like, "voltage" and "potential" can be interchanged as appropriate. "Voltage" refers to the potential difference from a reference potential. For example, if the reference potential is the ground potential (earth potential), then "voltage" can be interchanged with "potential." Ground potential does not necessarily mean 0V. Note that potential is relative, and the potential applied to wiring, etc. may change depending on the reference potential.

[0039] Furthermore, "electric current" refers to the phenomenon of charge transfer (electrical conduction). For example, the statement "electrical conduction of positively charged bodies is occurring" can be rephrased as "electrical conduction of negatively charged bodies is occurring in the opposite direction." Therefore, in this specification, unless otherwise specified, "electric current" refers to the phenomenon of charge transfer (electrical conduction) accompanying the movement of carriers. The carriers referred to here include electrons, holes, anions, cations, complex ions, etc., and the carriers differ depending on the system through which the current flows (e.g., semiconductor, metal, electrolyte, vacuum, etc.). Furthermore, the "direction of current" in wiring, etc., refers to the direction in which positive carriers move and is expressed as a positive current amount. In other words, the direction in which negative carriers move is opposite to the direction of current and is expressed as a negative current amount. Therefore, in this specification, etc., unless otherwise specified regarding the positive / negative sign of the current (or the direction of current), a statement such as "current flows from element A to element B" can be rephrased as "current flows from element B to element A," etc. Furthermore, statements such as "current is input to element A" can be rephrased as "current is output from element A" or the like.

[0040] Furthermore, in this specification, the ordinal numbers "first," "second," and "third" are used to avoid confusion between components. Therefore, they do not limit the number of components. Furthermore, they do not limit the order of the components. For example, a component referred to as "first" in one embodiment of this specification may be a component referred to as "second" in another embodiment or in the claims. Furthermore, for example, a component referred to as "first" in one embodiment of this specification may be omitted in another embodiment or in the claims.

[0041] Furthermore, in this specification, terms indicating position, such as "above" and "below," may be used for convenience in describing the positional relationship between components with reference to the drawings. Furthermore, the positional relationship between components changes as appropriate depending on the direction in which each component is depicted. Therefore, the terms are not limited to those used in the specification, and can be rephrased appropriately depending on the situation. For example, the expression "insulator located on the upper surface of a conductor" can be rephrased as "insulator located on the lower surface of a conductor" by rotating the orientation of the drawing 180 degrees.

[0042] Furthermore, the terms "above" and "below" do not limit the positional relationship of components to being directly above or below and in direct contact with each other. For example, the expression "electrode B on insulating layer A" does not require that electrode B be formed on insulating layer A in direct contact with it, and does not exclude the inclusion of other components between insulating layer A and electrode B.

[0043] Furthermore, in this specification and the like, terms such as "film" and "layer" can be interchanged depending on the situation. For example, the term "conductive layer" may be interchanged with the term "conductive film." Or, for example, the term "insulating film" may be interchanged with the term "insulating layer." Or, in some cases or depending on the situation, terms such as "film" and "layer" may not be used and may be interchanged with other terms. For example, the terms "conductive layer" or "conductive film" may be interchanged with the term "conductor." Or, for example, the terms "insulating layer" and "insulating film" may be interchanged with the term "insulator."

[0044] Furthermore, in this specification and the like, terms such as "electrode," "wiring," and "terminal" do not functionally limit these components. For example, an "electrode" may be used as part of a "wiring," and vice versa. Furthermore, the terms "electrode" and "wiring" include cases where multiple "electrodes" or "wirings" are integrally formed. Furthermore, for example, a "terminal" may be used as part of a "wiring" or "electrode," and vice versa. Furthermore, the term "terminal" includes cases where multiple "electrodes," "wirings," "terminals," etc. are integrally formed. Therefore, for example, an "electrode" can be part of a "wiring" or "terminal," and a "terminal" can be part of a "wiring" or "electrode." Furthermore, terms such as "electrode," "wiring," and "terminal" may be replaced with terms such as "region" in some cases.

[0045] Furthermore, in this specification and the like, terms such as "wiring," "signal line," and "power line" may be interchangeable depending on the circumstances. For example, the term "wiring" may be changed to the term "signal line." For example, the term "wiring" may be changed to the term "power line." Vice versa, terms such as "signal line" and "power line" may be changed to the term "wiring." A term such as "power line" may be changed to the term "signal line." Vice versa, terms such as "signal line" may be changed to the term "power line." Furthermore, the term "potential" applied to a wiring may be changed to the term "signal" depending on the circumstances. Vice versa, terms such as "signal" may be changed to the term "potential."

[0046] In this specification and the like, the term "impurities" in a semiconductor refers to, for example, elements other than the main components constituting a semiconductor layer. For example, an element with a concentration of less than 0.1 atomic % is an impurity. The presence of impurities may cause, for example, the formation of density of states (DOS) in the semiconductor, a decrease in carrier mobility, or a decrease in crystallinity. When the semiconductor is an oxide semiconductor, impurities that change the semiconductor characteristics include, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and transition metals other than the main components, particularly, for example, hydrogen (also contained in water), lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen. Specifically, when the semiconductor is a silicon layer, impurities that change the semiconductor characteristics include, for example, oxygen, Group 1 elements excluding hydrogen, Group 2 elements, Group 13 elements, and Group 15 elements.

[0047] In this specification and the like, a switch refers to a device that has the function of being in a conductive state (on state) or a non-conductive state (off state) and controlling whether or not a current flows. Alternatively, a switch refers to a device that has the function of selecting and switching a path through which a current flows. As an example, an electrical switch, a mechanical switch, or the like can be used. In other words, the switch is not limited to a specific one as long as it can control a current.

[0048] Examples of electrical switches include transistors (e.g., bipolar transistors, MOS transistors, etc.), diodes (e.g., PN diodes, PIN diodes, Schottky diodes, MIM (Metal Insulator Metal) diodes, MIS (Metal Insulator Semiconductor) diodes, diode-connected transistors, etc.), and logic circuits combining these. When a transistor is used as a switch, the "conductive state" of the transistor refers to a state in which the source electrode and drain electrode of the transistor can be considered to be electrically short-circuited. The "non-conductive state" of the transistor refers to a state in which the source electrode and drain electrode of the transistor can be considered to be electrically disconnected. When a transistor is operated simply as a switch, the polarity (conductivity type) of the transistor is not particularly limited.

[0049] An example of a mechanical switch is a switch that uses MEMS (microelectromechanical systems) technology. This switch has a mechanically movable electrode, and the movement of the electrode controls whether the switch is conductive or non-conductive.

[0050] In this specification, "parallel" refers to a state in which two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, it also includes cases where the angle is -5° or more and 5° or less. Furthermore, "substantially parallel" or "roughly parallel" refers to a state in which two straight lines are arranged at an angle of -30° or more and 30° or less. Furthermore, "perpendicular" refers to a state in which two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, it also includes cases where the angle is 85° or more and 95° or less. Furthermore, "substantially perpendicular" or "approximately perpendicular" refers to a state in which two straight lines are arranged at an angle of 60° or more and 120° or less. [Effects of the Invention]

[0051] According to one embodiment of the present invention, a semiconductor device or the like in which a hierarchical artificial neural network is constructed can be provided. According to one embodiment of the present invention, a semiconductor device or the like with low power consumption can be provided. According to one embodiment of the present invention, a semiconductor device or the like that is less susceptible to environmental temperature can be provided. According to one embodiment of the present invention, a semiconductor device or the like that is less susceptible to variations in characteristics of transistors can be provided. According to one embodiment of the present invention, a semiconductor device or the like that is less susceptible to variations in characteristics of current sources can be provided. According to one embodiment of the present invention, a novel semiconductor device or the like can be provided.

[0052] The effects of one embodiment of the present invention are not limited to the effects listed above. The effects listed above do not preclude the existence of other effects. The other effects are described below and are not mentioned in this section. Effects not mentioned in this section can be derived by a person skilled in the art from the description in the specification or drawings, and can be extracted as appropriate from these descriptions. One embodiment of the present invention has at least one of the effects listed above and other effects. Therefore, one embodiment of the present invention may not have the effects listed above in some cases. [Brief explanation of the drawings]

[0053] [Figure 1] 1A and 1B are diagrams illustrating a hierarchical neural network. [Figure 2] FIG. 2 is a circuit diagram showing an example of the configuration of a semiconductor device. [Figure 3] FIG. 3 is a circuit diagram showing an example of the configuration of a semiconductor device. [Figure 4] FIG. 4 is a circuit diagram showing an example of the configuration of a semiconductor device. [Figure 5] 5A, 5B, 5C, 5D, 5E, and 5F are circuit diagrams showing examples of the configuration of circuits included in the semiconductor device. [Figure 6] 6A, 6B, 6C, 6D, 6E, and 6F are circuit diagrams showing examples of the configuration of circuits included in the semiconductor device. [Figure 7] FIG. 7 is a circuit diagram showing an example of the configuration of a semiconductor device. [Figure 8] 8A, 8B, and 8C are circuit diagrams showing examples of the configuration of circuits included in the semiconductor device. [Figure 9] 9A, 9B, 9C, 9D, 9E, and 9F are circuit diagrams showing examples of the configuration of circuits included in the semiconductor device. [Figure 10] FIG. 10 is a circuit diagram showing an example of the configuration of a circuit included in a semiconductor device. [Figure 11] FIG. 11 is a circuit diagram showing an example of the configuration of a semiconductor device. [Figure 12] FIG. 12 is a circuit diagram showing an example of the configuration of a semiconductor device. [Figure 13] FIG. 13 is a circuit diagram showing an example of the configuration of a semiconductor device. [Figure 14] FIG. 14 is a circuit diagram showing an example of the configuration of a semiconductor device. [Figure 15] 15A, 15B, and 15C are circuit diagrams showing examples of the configuration of circuits included in the semiconductor device. [Figure 16] 16A and 16B are circuit diagrams showing examples of the configuration of circuits included in a semiconductor device. [Figure 17] 17A, 17B, and 17C are circuit diagrams showing examples of the configuration of circuits included in the semiconductor device. [Figure 18] 18A, 18B, and 18C are timing charts illustrating an example of the operation of the semiconductor device. [Figure 19] 19A, 19B, and 19C are timing charts illustrating an example of the operation of the semiconductor device. [Figure 20] 20A, 20B, and 20C are timing charts illustrating an example of the operation of the semiconductor device. [Figure 21] 21A and 21B are circuit diagrams showing examples of the configuration of circuits included in a semiconductor device. [Figure 22] 22A and 22B are circuit diagrams showing examples of the configuration of circuits included in a semiconductor device. [Figure 23]23A and 23B are circuit diagrams showing examples of the configuration of circuits included in a semiconductor device. [Figure 24] FIG. 24 is a circuit diagram showing an example of the configuration of a circuit included in a semiconductor device. [Figure 25] FIG. 25 is a circuit diagram showing an example of the configuration of a circuit included in a semiconductor device. [Figure 26] FIG. 26 is a circuit diagram showing an example of the configuration of a circuit included in a semiconductor device. [Figure 27] FIG. 27 is a circuit diagram showing an example of the configuration of a circuit included in a semiconductor device. [Figure 28] FIG. 28 is a circuit diagram showing an example of the configuration of a circuit included in a semiconductor device. [Figure 29] FIG. 29 is a circuit diagram showing an example of the configuration of a circuit included in a semiconductor device. [Figure 30] 30A and 30B are circuit diagrams showing examples of the configuration of circuits included in a semiconductor device. [Figure 31] FIG. 31 is a circuit diagram showing an example of the configuration of a circuit included in a semiconductor device. [Figure 32] FIG. 32 is a circuit diagram showing an example of the configuration of a circuit included in a semiconductor device. [Figure 33] FIG. 33 is a circuit diagram showing an example of the configuration of a circuit included in a semiconductor device. [Figure 34] FIG. 34 is a circuit diagram showing an example of the configuration of a circuit included in a semiconductor device. [Figure 35] FIG. 35 is a circuit diagram showing an example of the configuration of a circuit included in a semiconductor device. [Figure 36] FIG. 36 is a circuit diagram showing an example of the configuration of a circuit included in a semiconductor device. [Figure 37] FIG. 37 is a circuit diagram showing an example of the configuration of a circuit included in a semiconductor device. [Figure 38] FIG. 38 is a circuit diagram showing an example of the configuration of a circuit included in a semiconductor device. [Figure 39] FIG. 39 is a circuit diagram showing an example of the configuration of a circuit included in a semiconductor device. [Figure 40] FIG. 40 is a circuit diagram showing an example of the configuration of a circuit included in a semiconductor device. [Figure 41]41A, 41B, and 41C are circuit diagrams showing examples of the configuration of circuits included in the semiconductor device. [Figure 42] FIG. 42 is a circuit diagram showing an example of the configuration of a circuit included in a semiconductor device. [Figure 43] FIG. 43 is a circuit diagram showing an example of the configuration of a circuit included in a semiconductor device. [Figure 44] FIG. 44 is a circuit diagram showing an example of the configuration of a circuit included in a semiconductor device. [Figure 45] FIG. 45 is a circuit diagram showing an example of the configuration of a circuit included in a semiconductor device. [Figure 46] FIG. 46 is a circuit diagram showing an example of the configuration of a circuit included in a semiconductor device. [Figure 47] 47A and 47B are circuit diagrams showing examples of the configuration of a circuit included in a semiconductor device. [Figure 48] 48A, 48B, and 48C are timing charts illustrating an example of the operation of the semiconductor device. [Figure 49] 49A, 49B, and 49C are timing charts illustrating an example of the operation of the semiconductor device. [Figure 50] FIG. 50 is a circuit diagram showing an example of the configuration of a circuit included in a semiconductor device. [Figure 51] FIG. 51 is a circuit diagram showing an example of the configuration of a circuit included in a semiconductor device. [Figure 52] FIG. 52 is a circuit diagram showing an example of the configuration of a circuit included in a semiconductor device. [Figure 53] FIG. 53 is a circuit diagram showing an example of the configuration of a circuit included in a semiconductor device. [Figure 54] 54A and 54B are circuit diagrams showing examples of the configuration of circuits included in a semiconductor device. [Figure 55] 55A, 55B, and 55C are circuit diagrams showing examples of the configuration of circuits included in the semiconductor device. [Figure 56] 56A and 56B are circuit diagrams showing examples of the configuration of circuits included in a semiconductor device. [Figure 57] FIG. 57 is a circuit diagram showing an example of the configuration of a circuit included in a semiconductor device. [Figure 58]FIG. 58 is a circuit diagram showing an example of the configuration of a circuit included in a semiconductor device. [Figure 59] FIG. 59 is a circuit diagram showing an example of the configuration of a circuit included in a semiconductor device. [Figure 60] FIG. 60 is a circuit diagram showing an example of the configuration of a circuit included in a semiconductor device. [Figure 61] FIG. 61 is a cross-sectional view illustrating the configuration of a semiconductor device. [Figure 62] FIG. 62 is a cross-sectional view illustrating the configuration of a semiconductor device. [Figure 63] 63A, 63B, and 63C are cross-sectional schematic views illustrating the configuration of a semiconductor device. [Figure 64] 64A and 64B are cross-sectional schematic views illustrating examples of the configuration of a transistor. [Figure 65] FIG. 65 is a schematic cross-sectional view illustrating an example of the configuration of a semiconductor device. [Figure 66] 66A and 66B are cross-sectional schematic views illustrating examples of the configuration of a transistor. [Figure 67] FIG. 67 is a schematic cross-sectional view illustrating an example of the configuration of a semiconductor device. [Figure 68] FIG. 68A is a top view showing an example of the configuration of a capacitor, and FIGS. 68B and 68C are cross-sectional perspective views showing an example of the configuration of a capacitor. [Figure 69] FIG. 69A is a top view showing an example of the configuration of a capacitor, FIG. 69B is a cross-sectional view showing an example of the configuration of a capacitor, and FIG. 69C is a cross-sectional perspective view showing an example of the configuration of a capacitor. [Figure 70] FIG. 70A is a perspective view showing an example of a semiconductor wafer, FIG. 70B is a perspective view showing an example of a chip, and FIGS. 70C and 70D are perspective views showing an example of an electronic component. [Figure 71] FIG. 71 is a perspective view showing an example of an electronic device. [Figure 72] 72A, 72B, and 72C are perspective views showing examples of electronic devices. DETAILED DESCRIPTION OF THE INVENTION

[0054] In an artificial neural network (hereafter referred to as a neural network), the strength of synaptic connections can be changed by providing existing information to the neural network. This process of providing existing information to a neural network and determining connection strengths is sometimes called "learning."

[0055] Furthermore, by providing some information to a neural network that has undergone "learning" (with connection strengths determined), new information can be output based on the connection strengths. In this way, the process of outputting new information based on the provided information and connection strengths in a neural network is sometimes called "inference" or "cognition."

[0056] Neural network models include, for example, Hopfield and hierarchical types. In particular, neural networks with multi-layer structures are sometimes called "deep neural networks" (DNNs), and machine learning using deep neural networks is sometimes called "deep learning."

[0057] In this specification and the like, a metal oxide refers to an oxide of a metal in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also referred to as oxide semiconductors or simply as OSs), and the like. For example, when a metal oxide is used in the active layer of a transistor, the metal oxide may be referred to as an oxide semiconductor. That is, when a metal oxide can form a channel formation region of a transistor having at least one of an amplifying function, a rectifying function, and a switching function, the metal oxide can be referred to as a metal oxide semiconductor, or OS for short. Furthermore, an OS transistor can be referred to as a transistor having a metal oxide or an oxide semiconductor.

[0058] In this specification and the like, nitrogen-containing metal oxides may also be collectively referred to as metal oxides. Nitrogen-containing metal oxides may also be referred to as metal oxynitrides.

[0059] In this specification and the like, the configurations shown in each embodiment can be combined as appropriate with the configurations shown in other embodiments to form one aspect of the present invention. In addition, when multiple configuration examples are shown in one embodiment, the configuration examples can be combined as appropriate with each other.

[0060] In addition, the content (or even part of the content) described in one embodiment can be applied, combined, or replaced with at least one of another content (or even part of the content) described in that embodiment and another content (or even part of the content) described in one or more other embodiments.

[0061] The contents described in the embodiments refer to the contents described in each embodiment using various figures or the contents described using text in the specification.

[0062] Furthermore, a figure (or even a part thereof) described in one embodiment can be combined with another part of that figure, another figure (or even a part thereof) described in that embodiment, and at least one figure (or even a part thereof) described in one or more other embodiments to form even more figures.

[0063] The embodiments described in this specification are described with reference to the drawings. However, it will be readily understood by those skilled in the art that the embodiments can be implemented in many different ways, and that various changes in form and details can be made without departing from the spirit and scope of the invention. Therefore, the present invention should not be interpreted as being limited to the description of the embodiments. Note that in the configuration of the invention of the embodiments, the same reference numerals are used in different drawings for the same parts or parts having similar functions, and repeated description thereof may be omitted. Also, in perspective views and the like, the description of some components may be omitted to ensure clarity of the drawings.

[0064] In this specification, when the same symbol is used for multiple elements, and particularly when it is necessary to distinguish between them, an identification symbol such as “_1”, “[n]”, or “[m,n]” may be added to the symbol.

[0065] In addition, in the drawings of this specification, the size, layer thickness, or region may be exaggerated for clarity. Therefore, the drawings are not necessarily limited to the scale. Note that the drawings are schematic illustrations of ideal examples, and are not limited to the shapes or values ​​shown in the drawings. For example, variations in signals, voltages, or currents due to noise, or variations in signals, voltages, or currents due to timing differences may be included.

[0066] In addition, for this specification and the like, when it comes to In:Ga:Zn = 4:2:3 or in the vicinity thereof, with respect to the total number of atoms, when In is 4, Ga is 1 or more and 3 or less (1 ≤ Ga ≤ 3), and Zn is 2 or more and 4.1 or less (2 ≤ Zn ≤ 4.1). Also, when it comes to In:Ga:Zn = 5:1:6 or in the vicinity thereof, with respect to the total number of atoms, when In is 5, Ga is greater than 0.1 and 2 or less (0.1 < Ga ≤ 2), and Zn is 5 or more and 7 or less (5 ≤ Zn ≤ 7). Also, when it comes to In:Ga:Zn = 1:1:1 or in the vicinity thereof, with respect to the total number of atoms, when In is 1, Ga is greater than 0.1 and 2 or less (0.1 < Ga ≤ 2), and Zn is greater than 0.1 and 2 or less (0.1 < Zn ≤ 2). Also, when it comes to In:Ga:Zn = 5:1:3 or in the vicinity thereof, with respect to the total number of atoms, when In is 5, Ga is 0.5 or more and 1.5 or less (0.5 ≤ Ga ≤ 1.5), and Zn is 2 or more and 4.1 or less (2 ≤ Zn ≤ 4.1). Also, when it comes to In:Ga:Zn = 10:1:3 or in the vicinity thereof, with respect to the total number of atoms, when In is 10, Ga is 0.5 or more and 1.5 or less (0.5 ≤ Ga ≤ 1.5), and Zn is 2 or more and 4.1 or less (2 ≤ Zn ≤ 4.1). Also, when it comes to In:Zn = 2:1 or in the vicinity thereof, with respect to the total number of atoms, when In is 1, Zn is greater than 0.25 and 0.75 or less (0.25 < Zn ≤ 0.75). Also, when it comes to In:Zn = 5:1 or in the vicinity thereof, with respect to the total number of atoms, when In is 1, Zn is greater than 0.12 and 0.25 or less (0.12 < Zn ≤ 0.25). Also, when it comes to In:Zn = 10:1 or in the vicinity thereof, with respect to the total number of atoms, when In is 1, Zn is greater than 0.07 and 0.12 or less (0.07 < Zn ≤ 0.12).

[0067] (Embodiment 1) In this embodiment, an arithmetic circuit that performs neural network operations, which is a semiconductor device according to one aspect of the present invention, will be described.

[0068] <Hierarchical neural network> First, a hierarchical neural network will be described. A hierarchical neural network, for example, has one input layer, one or more intermediate layers (hidden layers), and one output layer, for a total of three or more layers. The hierarchical neural network 100 shown in FIG. 1A is an example of such a network, and the neural network 100 has layers 1 through R (where R can be an integer equal to or greater than four). In particular, the first layer corresponds to the input layer, the R layer corresponds to the output layer, and the other layers correspond to intermediate layers. Note that FIG. 1A illustrates layers (k-1) and k (where k is an integer equal to or greater than three and equal to or less than R-1) as intermediate layers, and does not illustrate the other intermediate layers.

[0069] Each layer of neural network 100 has one or more neurons. In FIG. 1A, the first layer is made up of neurons N1 (1) Neuron N p (1) (where p is an integer equal to or greater than 1), and the (k-1)th layer has neurons N1 (k-1) Neuron N m (k-1) (where m is an integer greater than or equal to 1), and the kth layer has neurons N1 (k) Neuron N n (k) (where n is an integer greater than or equal to 1), and the Rth layer has neurons N1 (R) Neuron N q (R) (where q is an integer equal to or greater than 1).

[0070] In addition, in Figure 1A, neuron N1 (1) , neuron N p (1) , neuron N1 (k-1) , neuron N m (k-1) , neuron N1 (k) , neuron N n (k) , neuron N1 (R) , neuron N q (R)In addition, the (k-1)th layer neuron N i (k-1) (where i is an integer between 1 and m), and the kth layer neuron N j (k) (where j is an integer between 1 and n) are also shown, and other neurons are omitted from the illustration.

[0071] Next, we will explain the transmission of signals from neurons in the previous layer to neurons in the next layer, and the signals input and output at each neuron. j (k) We are focusing on the following.

[0072] Figure 1B shows the kth layer neuron N j (k) and neuron N j (k) and the signal input to neuron N j (k) 10 shows the signal output from the

[0073] Specifically, the neuron N1 in the (k-1)th layer (k-1) Neuron N m (k-1) The output signal z1 (k-1) ~z m (k-1) But neuron N j (k) The output is directed to neuron N j (k) is z1 (k-1) ~z m (k-1) Depending on z j (k) Generate z j (k) is output as an output signal to each neuron in the (k+1)th layer (not shown).

[0074] The degree of signal transmission for a signal input from a neuron in the previous layer to a neuron in the next layer is determined by the connection strength (hereinafter referred to as a weighting coefficient) of the synapse connecting those neurons. In the neural network 100, the signal output from a neuron in the previous layer is multiplied by the corresponding weighting coefficient before being input to a neuron in the next layer. If i is an integer between 1 and m, then the (k-1)th layer neuron N i (k-1) and the k-th layer neuron N j (k) The weight coefficient of the synapse between i (k-1) j (k) Then, the k-th layer neuron N j (k) The signal input to can be expressed by equation (1.1).

[0075]

number

[0076] That is, the neuron N1 in the (k-1)th layer (k-1) Neuron N m (k-1) From each of these, the k-th layer neuron N j (k) When a signal is transmitted to the (k-1) ~z m (k-1) The weighting coefficients w1 corresponding to each signal are (k-1) j (k) Or even w m (k-1) j (k) Then, the k-th layer neuron N j (k) has w1 (k-1) j (k) z1 (k-1) Or even w m (k-1) j (k) z m (k-1)is input. At this time, the k-th layer neuron N j (k) The sum of the signals input to j (k) is expressed as equation (1.2).

[0077]

number

[0078] Also, the weighting factor w1 (k-1) j (k) Or even w m (k-1) j (k) and the neuron signal z1 (k-1) ~z m (k-1) The result of the sum of products of and can be given a bias. When the bias is b, equation (1.2) can be rewritten as the following equation.

[0079]

number

[0080] Neuron N j (k) u j (k) Depending on j (k) where neuron N j (k) Output signal z from j (k) is defined as follows:

[0081]

number

[0082] The function f(u j (k)) is an activation function in a hierarchical neural network, and can be a step function, a linear ramp function, a sigmoid function, etc. The activation function can be the same for all neurons or different for each layer. In addition, the activation functions of neurons can be the same or different for each layer.

[0083] The signals, weight coefficients w, or biases b output by neurons in each layer may be analog or digital values. Digital values ​​may be, for example, binary or ternary. Values ​​with even larger bit counts may also be used. For example, in the case of analog values, activation functions such as linear ramp functions and sigmoid functions may be used. In the case of binary digital values, step functions that output either -1 or 1, or either 0 or 1 may be used. Furthermore, signals output by neurons in each layer may be ternary or more. For example, activation functions that output three values ​​may be ternary or more, such as step functions that output either -1, 0, or 1, or step functions that output either 0, 1, or 2. Furthermore, activation functions that output five values ​​may be step functions that output either -2, -1, 0, 1, or 2. By using digital values ​​for at least one of the signals output by neurons in each layer, the weighting coefficient w, or the bias b, it is possible to reduce the circuit size, reduce power consumption, or increase the calculation speed, etc. Furthermore, by using analog values ​​for at least one of the signals output by neurons in each layer, the weighting coefficient w, or the bias b, it is possible to improve the accuracy of calculations.

[0084] When an input signal is input to the first layer (input layer), neural network 100 generates an output signal in each layer, from the first layer (input layer) to the last layer (output layer), based on the signal input from the previous layer, using equations (1.1), (1.2) (or (1.3)), and (1.4), and outputs the output signal to the next layer. The signal output from the last layer (output layer) corresponds to the result of calculation by neural network 100.

[0085] <Example of arithmetic circuit configuration> Here, we will explain an example of an arithmetic circuit that can perform the calculations of formula (1.2) (or formula (1.3)) and formula (1.4) in the above-mentioned neural network 100. In this arithmetic circuit, as an example, the weight coefficients of the synapse circuits of the neural network 100 are set to binary (a combination of "-1" and "+1", or a combination of "0" and "+1"), ternary (a combination of "-1", "0", and "1"), or multiple values ​​of four or more (in the case of a quinary value, a combination of "-2", "-1", "0", "1", and "2"), and the activation function of the neuron is set to a function that outputs binary (a combination of "-1" and "+1", or a combination of "0", "+1"), ternary (a combination of "-1", "0", and "1"), or multiple values ​​of four or more (in the case of a quaternary value, a combination of "0", "1", "2", and "3"). In this specification, either the weight coefficient or the value of a signal input from a neuron in a previous layer to a neuron in a next layer (sometimes referred to as a calculated value) may be referred to as first data, and the other as second data. Note that the weight coefficients and calculated values ​​of the synapse circuits of neural network 100 are not limited to digital values, and at least one of them may be an analog value.

[0086] 2 is a semiconductor device having, for example, an array section ALP, a circuit ILD, a circuit WLD, a circuit XLD, and a circuit AFP. The arithmetic circuit 110 corresponds to the neuron N1 in the k-th layer in FIGS. 1A and 1B. (k) Neuron N n (k)The signal z1 input to (k-1) ~z m (k-1) and neuron N1 (k) Neuron N n (k) The signal z1 output from each (k) ~z n (k) This is a circuit that generates

[0087] Note that the entire arithmetic circuit 110, or a part thereof, may be used for purposes other than neural networks or AI. For example, when performing product-sum operations or matrix operations in graphics calculations or scientific calculations, the entire arithmetic circuit 110, or a part thereof, may be used for the processing. In other words, the entire arithmetic circuit 110, or a part thereof, may be used not only for AI calculations but also for general calculations.

[0088] For example, the circuit ILD is electrically connected to wirings IL[1] to IL[n] and ILB[1] to ILB[n]. For example, the circuit WLD is electrically connected to wirings WLS[1] to WLS[m]. For example, the circuit XLD is electrically connected to wirings XLS[1] to XLS[m]. For example, the circuit AFP is electrically connected to wirings OL[1] to OL[n] and OLB[1] to OLB[n].

[0089] <<Array section ALP>> The array unit ALP has, for example, m×n circuits MP. The circuits MP are arranged in a matrix of m rows and n columns within the array unit ALP. In FIG. 2, the circuit MP located in the i-th row and j-th column (where i is an integer between 1 and m, and j is an integer between 1 and n) is represented as circuit MP[i,j]. However, in FIG. 2, only circuit MP[1,1], circuit MP[m,1], circuit MP[i,j], circuit MP[1,n], and circuit MP[m,n] are shown, and the other circuits MP are not shown.

[0090] As an example, the circuit MP[i,j] is electrically connected to wiring IL[j], wiring ILB[j], wiring WLS[i], wiring XLS[i], wiring OL[j], and wiring OLB[j].

[0091] The circuit MP[i,j] is, for example, a neuron N i (k-1) and neuron N j (k) Specifically, the circuit MP[i,j] holds information (such as potential, resistance, and current) corresponding to the first data (weighting coefficient) input from the wiring IL[j] and the wiring ILB[j]. The circuit MP[i,j] also holds information corresponding to the first data (weighting coefficient) input from the wiring IL[j] and the wiring ILB[j]. i (k-1) The signal z output from i (k-1) (It may be called the other of the first data or the second data. Here, it is called the second data) and the first data. As a specific example, the circuit MP[i,j] receives the second data z from the wiring XLS[i]. i (k-1) When the first data and the second data are input, information corresponding to the product of the first data and the second data (e.g., a current, a voltage, etc.) or information related to the product of the first data and the second data (e.g., a current, a voltage, etc.) is output to the wiring OL[j] and the wiring OLB[j]. Note that although an example in which the wiring IL[j] and the wiring ILB[j] are provided has been shown, one embodiment of the present invention is not limited to this. Only one of the wiring IL[j] and the wiring ILB[j] may be provided.

[0092] <<Circuit ILD>> For example, the circuit ILD transmits first data w1, which is a weighting coefficient, to each of the circuits MP[1,1] to MP[m,n] via the wirings IL[1] to IL[n] and the wirings ILB[1] to ILB[n]. (k-1) 1 (k) Or even w m (k-1) n(k) As a specific example, the circuit ILD has a function of inputting information (for example, potential, resistance value, current value, etc.) corresponding to the circuit MP[i,j]. i (k-1) j (k) Information corresponding to the above (for example, potential, resistance value, or current value) is supplied via the wiring IL[j] and wiring ILB[j].

[0093] <<Circuit XLD>> For example, the circuit XLD connects the neuron N1 to the circuits MP[1,1] to MP[m,n] via the wiring XLS[1] to the wiring XLS[n]. (k-1) Neuron N m (k) The second data z1 corresponds to the calculated value output from (k-1) ~z m (k-1) Specifically, the circuit XLD supplies neurons N i (k-1) The second data z output from i (k-1) Information (for example, a potential, a current value, or the like) corresponding to the signal is supplied through the wiring XLS[i]. Note that although an example in which the wiring XLS[i] is provided is shown, one embodiment of the present invention is not limited to this. For example, in the arithmetic circuit 110 in FIG. 2, the wiring XLS[i] may be replaced with a plurality of wirings. As a specific example, FIG. 3 illustrates an arithmetic circuit 120 in which the wiring XLS[i] electrically connected to the circuit MP[i,j] of the arithmetic circuit 110 is replaced with two wirings, namely, a wiring X1L and a wiring X2L. Note that although an example in which the wiring XLS[i] is provided is shown, one embodiment of the present invention is not limited to this. In addition to the wiring XLS[i], for example, a wiring for transmitting an inverted signal of a signal input to the wiring XLS[i] may be separately provided.

[0094] <<Circuit WLD>> For example, the circuit WLD has a function of selecting a circuit MP to which information (e.g., a potential, a resistance value, a current value, etc.) corresponding to the first data input from the circuit ILD is to be written. For example, when writing information (e.g., a potential, a resistance value, a current value, etc.) to the circuits MP[i,1] to MP[i,n] located in the i-th row of the array portion ALP, the circuit WLD may supply a signal to the wiring WLS[i] for turning on or off the write switching elements included in the circuits MP[i,1] to MP[i,n] and supply a potential to the wiring WLS for turning off the write switching elements included in the circuits MP other than the i-th row. Note that although an example in which the wiring WLS[i] is provided is shown, one embodiment of the present invention is not limited thereto. In addition to the wiring WLS[i], for example, a wiring for transmitting an inverted signal of a signal input to the wiring WLS[i] may be provided separately.

[0095] Although the arithmetic circuit 110 in FIG. 2 includes a wiring WLS[i], one embodiment of the present invention is not limited to this. For example, the wiring WLS[i] may be replaced with a plurality of wirings. For example, the wiring X1L[i] of the arithmetic circuit 120 in FIG. 3 may also serve as a selection signal line for writing data to the circuits MP[i,1] to MP[i,n]. Specifically, as in the arithmetic circuit 130 shown in FIG. 4, the wiring X1L[i] of the arithmetic circuit 120 may be used as a wiring WX1L[i], and the wiring WX1L may be electrically connected to the circuit WLD and the circuit XLD. Note that when a signal for turning on or off the write switching elements included in the circuits MP[i,1] to MP[i,n] is supplied to the wiring WX1L[i] from the circuit WLD, the circuit XLD preferably has a function of bringing the circuit XLD and the wiring WX1L into a non-conduction state. Also, through the wiring WX1L[i], neuron N1 (k-1) Neuron N m (k) The second data z1 corresponds to the calculated value output from (k-1) ~z m (k-1)When the signal is supplied from the circuit WLD to the circuits MP[i,1] to MP[i,n], the circuit WLD preferably has a function of bringing the circuit WLD and the wiring WX1L into a non-conductive state.

[0096] <<Circuit AFP>> The circuit AFP includes, for example, circuits ACTF[1] to ACTF[n]. For example, the circuit ACTF[j] is electrically connected to each of the wirings OL[j] and OLB[j]. For example, the circuit ACTF[j] generates a signal according to the information (e.g., potential, current value, etc.) input from the wirings OL[j] and OLB[j]. For example, the circuit ACTF[j] compares the information (e.g., potential, current value, etc.) input from the wirings OL[j] and OLB[j] and generates a signal according to the comparison result. The signal is input to the neuron N j (k) The signal z output from j (k) . That is, the circuits ACTF[1] to ACTF[n] function as, for example, circuits that perform the calculation of the activation function of the neural network described above. However, one embodiment of the present invention is not limited thereto. For example, the circuits ACTF[1] to ACTF[n] may have a function of converting an analog signal into a digital signal. Alternatively, the circuits ACTF[1] to ACTF[n] may have a function of amplifying and outputting an analog signal, that is, a function of converting output impedance. Alternatively, the circuits ACTF[1] to ACTF[n] may have a function of converting current or charge into voltage. Alternatively, the circuits ACTF[1] to ACTF[n] may have a function of initializing the potential of the wiring OL[j] or the wiring OLB[j].

[0097] 2 to 4 illustrate an example in which the circuit ACTF is provided in the arithmetic circuit 110, the arithmetic circuit 120, and the arithmetic circuit 130. However, one embodiment of the present invention is not limited to this. For example, the circuit ACTF does not necessarily have to be provided in the circuit AFP.

[0098] Next, the circuits ACTF[1] to ACTF[n] will be described. The circuits ACTF[1] to ACTF[n] can have the circuit configuration shown in FIG. 5A, for example. FIG. 5A shows an example in which a signal z j (k) Specifically, FIG. 5A shows a circuit that generates an output signal z j (k) 1 shows an example of an activation function calculation circuit that outputs

[0099] In FIG. 5A, the circuit ACTF[j] includes a resistor RE, a resistor REB, and a comparator CMP. The resistors RE and REB have the function of converting current to voltage. Therefore, any element or circuit having the function of converting current to voltage is not limited to a resistor. The wiring OL[j] is electrically connected to the first terminal of the resistor RE and the first input terminal of the comparator CMP, and the wiring OLB[j] is electrically connected to the first terminal of the resistor REB and the second input terminal of the comparator CMP. The second terminal of the resistor RE is electrically connected to the wiring VAL, and the second terminal of the resistor REB is electrically connected to the wiring VAL. The second terminal of the resistor RE and the second terminal of the resistor REB may be connected to the same wiring. Alternatively, they may be connected to different wirings having the same potential.

[0100] It is preferable that the resistance values ​​of the resistors RE and REB are equal to each other. For example, it is desirable that the difference between the resistance values ​​of the resistors RE and REB is within 10%, more preferably within 5%. However, one aspect of the present invention is not limited to this. In some cases or depending on the situation, the resistance values ​​of the resistors RE and REB may be different from each other.

[0101] For example, the wiring VAL functions as a wiring that applies a constant voltage. The constant voltage can be, for example, a high-level potential VDD, a low-level potential VSS, or a ground potential (GND). Preferably, the constant voltage is set appropriately depending on the configuration of the circuit MP. For example, the wiring VAL may be supplied with a pulse signal instead of a constant voltage.

[0102] The voltage between the first and second terminals of the resistor RE is determined according to the current flowing from the wiring OL[j]. Therefore, a voltage corresponding to the resistance value of the resistor RE and the current is input to the first input terminal of the comparator CMP. Similarly, the voltage between the first and second terminals of the resistor REB is determined according to the current flowing from the wiring OLB[j]. Therefore, a voltage corresponding to the resistance value of the resistor REB and the current is input to the second input terminal of the comparator CMP.

[0103] For example, the comparator CMP has a function of comparing the voltages input to the first input terminal and the second input terminal, and outputting a signal from the output terminal of the comparator CMP according to the comparison result. For example, the comparator CMP can output a high-level potential from the output terminal of the comparator CMP when the voltage input to the second input terminal is higher than the voltage input to the first input terminal, and can output a low-level potential from the output terminal of the comparator CMP when the voltage input to the first input terminal is higher than the voltage input to the second input terminal. In other words, the potential output from the output terminal of the comparator CMP can be either a high-level potential or a low-level potential, and therefore the output signal z output by the circuit ACTF[j] j (k) For example, the high-level potential and the low-level potential output from the output terminal of the comparator CMP are expressed as the output signal z j (k) In some cases, the high level potential and the low level potential output from the output terminal of the comparator CMP correspond to "+1" and "-1", respectively. j (k) may correspond to "+1" and "0".

[0104] Although the circuit ACTF[j] of FIG. 5A uses resistors RE and REB, any element or circuit capable of converting current to voltage may be used. Therefore, the resistors RE and REB in the circuit ACTF[j] of FIG. 5A can be replaced with other circuit elements. For example, the circuit ACTF[j] shown in FIG. 5B is a circuit in which the resistors RE and REB included in the circuit ACTF[j] of FIG. 5A are replaced with capacitors CE and CEB. This circuit can perform substantially the same operation as the circuit ACTF[j] of FIG. 5A. It is preferable that the capacitance values ​​of the capacitors CE and CEB are equal to each other. For example, it is desirable that the difference in capacitance values ​​between the capacitors CE and CEB be within 10%, more preferably within 5%. However, this is not a limitation of one embodiment of the present invention. A circuit for initializing the charges stored in the capacitors CE and CEB may be provided. For example, a switch may be provided in parallel with the capacitor CE. That is, the second terminal of the switch may be connected to the wiring VAL, and the first terminal of the switch may be connected to the first terminal of the capacitor CE, the wiring OL[j], and the first input terminal of the comparator CMP. Alternatively, the second terminal of the switch may be connected to a wiring other than the wiring VAL, and the first terminal of the switch may be connected to the first terminal of the capacitor CE, the wiring OL[j], and the first input terminal of the comparator CMP. The circuit ACTF[j] shown in FIG. 5C is a circuit in which the resistors RE and REB included in the circuit ACTF[j] of FIG. 5A are replaced with diode elements DE and DEB, and can perform substantially the same operation as the circuit ACTF[j] of FIG. 5A. It is desirable to appropriately change the orientation (anode-cathode connection points) of the diode elements DE and DEB depending on the magnitude of the potential of the wiring VAL.

[0105] 5A to 5C, the comparator CMP included in the circuit ACTF[j] can be replaced with an operational amplifier OP. The circuit ACTF[j] shown in Fig. 5D is a circuit diagram in which the comparator CMP of the circuit ACTF[j] in Fig. 5A is replaced with an operational amplifier OP.

[0106] 5B may also include switches S01a and S01b. This allows the circuit ACTF[j] to maintain potentials corresponding to the currents input from the wiring OL[j] and wiring OLB[j] to the capacitors CE and CEB, respectively. A specific example of such a circuit is shown in FIG. 5E. The first terminal of the switch S01a is electrically connected to the wiring OL[j]. The second terminal of the switch S01a is electrically connected to the first terminal of the capacitor CE and the first input terminal of the comparator CMP. The first terminal of the switch S01b is electrically connected to the wiring OLB[j]. The second terminal of the switch S01b is electrically connected to the first terminal of the capacitor CEB and the second input terminal of the comparator CMP. In the circuit ACTF[j] of FIG. 5E, the potentials of the wiring OL[j] and wiring OLB[j] are input to the first input terminal and the second input terminal of the comparator CMP, respectively, by turning on the switches S01a and S01b. Then, by turning off the switches S01a and S01b, the potentials input to the first and second input terminals of the comparator CMP can be held in the capacitors CE and CEB. The switches S01a and S01b can be, for example, electrical switches such as analog switches or transistors. The switches S01a and S01b can also be, for example, mechanical switches. When transistors are used as the switches S01a and S01b, the transistors can be OS transistors or transistors having silicon in their channel formation regions (hereinafter referred to as Si transistors). Alternatively, the voltages of the capacitors CE and CEB can be controlled by controlling the periods during which the switches S01a and S01b are kept on. For example, when the currents flowing through the capacitors CE and CEB are large, shortening the periods during which the switches S01a and S01b are kept on can prevent the voltages of the capacitors CE and CEB from becoming too large.

[0107] 5A to 5C and 5E, the comparator CMP included in the circuit ACTF[j] may be, for example, a chopper-type comparator. The comparator CMP shown in FIG. 5F is a chopper-type comparator, and includes switches S02a, S02b, and S03, a capacitor CC, and an inverter circuit INV3. Similar to the switches S01a and S01b described above, the switches S02a, S02b, and S03 may be mechanical switches or transistors such as OS transistors or Si transistors.

[0108] A first terminal of the switch S02a is electrically connected to the terminal VinT, a first terminal of the switch S02b is electrically connected to the terminal VrefT, and a second terminal of the switch S02a is electrically connected to the second terminal of the switch S02b and the first terminal of the capacitor CC. The second terminal of the capacitor CC is electrically connected to the input terminal of the inverter circuit INV3 and the first terminal of the switch S03. The terminal VoutT is electrically connected to the output terminal of the inverter circuit INV3 and the second terminal of the switch S03.

[0109] The terminal VinT functions as a terminal for inputting an input potential to the comparator CMP, the terminal VrefT functions as a terminal for inputting a reference potential to the comparator CMP, and the terminal VoutT functions as a terminal for outputting an output potential from the comparator CMP. The terminal VinT can correspond to one of the first terminal or the second terminal of the comparator CMP in Figures 5A to 5C and 5E, and the terminal VrefT can correspond to the other of the first terminal or the second terminal of the comparator CMP in Figures 5A to 5C and 5E.

[0110] The circuit ACTF[j] of FIGS. 5A to 5E outputs an output signal z j (k) The activation function circuit ACTF[j] outputs the output signal z j (k) may be configured to output as three or more values ​​or as an analog value.

[0111] 6A to 6F show the signal z in response to the current input from the wiring OL[j] and wiring OLB[j]. j (k) is a circuit that generates an output signal z represented by a ternary value. j (k) 1 shows an example of an activation function calculation circuit that outputs

[0112] The circuit ACTF[j] shown in Figure 6A includes a resistor RE, a resistor REB, a comparator CMPa, and a comparator CMPb. A wiring OL[j] is electrically connected to a first terminal of the resistor RE and a first input terminal of the comparator CMPa, and a wiring OLB[j] is electrically connected to a first terminal of the resistor REB and a first input terminal of the comparator CMPb. The second input terminal of the comparator CMPa and the second input terminal of the comparator CMPb are electrically connected to a wiring VrefL. Furthermore, the second terminal of the resistor RE is electrically connected to a wiring VAL, and the second terminal of the resistor REB is electrically connected to a wiring VAL.

[0113] The wiring VrefL is a constant voltage V ref acts as a voltage line that gives V ref It is preferable that V is, for example, equal to or higher than GND and equal to or lower than VDD. ref V may be at a potential lower than GND or higher than VDD. ref is treated as a reference potential (potential for comparison) in the comparators CMPa and CMPb.

[0114] The voltage between the first and second terminals of the resistor RE is determined according to the current flowing from the wiring OL[j]. Therefore, a voltage corresponding to the resistance value of the resistor RE and the current is input to the first input terminal of the comparator CMPa. Similarly, the voltage between the first and second terminals of the resistor REB is determined according to the current flowing from the wiring OLB[j]. Therefore, a voltage corresponding to the resistance value of the resistor REB and the current is input to the first input terminal of the comparator CMPb.

[0115] The comparator CMPa compares the voltages input to the first input terminal and the second input terminal, and outputs a signal from the output terminal of the comparator CMPa according to the comparison result. For example, the comparator CMPa detects that the voltage input to the second input terminal (V ref ) is high, a high-level potential is output from the output terminal of the comparator CMPa, and the voltage (V ref When the voltage input to the first input terminal is higher than the voltage input to the first input terminal, a low level potential can be output from the output terminal of the comparator CMPa.

[0116] Similar to the comparator CMPa, the comparator CMPb compares the voltages input to the first input terminal and the second input terminal, and outputs a signal from the output terminal of the comparator CMPb according to the comparison result. For example, the comparator CMPb detects that the voltage input to the second input terminal (V ref ) is high, a high-level potential is output from the output terminal of the comparator CMPb, and the voltage (V ref When the voltage input to the first input terminal is higher than the voltage input to the first input terminal of the comparator CMPb, a low level potential can be output from the output terminal of the comparator CMPb.

[0117] At this time, a ternary output signal z is generated according to the potentials output from the output terminals of the comparators CMPa and CMPb. j (k) For example, when a high-level potential is output from the output terminal of the comparator CMPa and a low-level potential is output from the output terminal of the comparator CMPb, the output signal z j (k) is set to "+1", and when a low level potential is output from the output terminal of the comparator CMPa and a high level potential is output from the output terminal of the comparator CMPb, the output signal z j (k) is set to "-1", and when a low level potential is output from the output terminal of the comparator CMPa and a low level potential is output from the output terminal of the comparator CMPb, the output signal z j (k) can be set to "+0".

[0118] Furthermore, the circuit ACTF[j] is not limited to the circuit configuration shown in FIG. 6A, and can be modified depending on the situation. For example, in the circuit ACTF[j] of FIG. 6A, if it is desired to combine the two output results of the comparators CMPa and CMPb into one signal, a conversion circuit TRF can be provided in the circuit ACTF[j]. The circuit ACTF[j] of FIG. 6B is a configuration example in which a conversion circuit TRF is provided in the circuit ACTF[j] of FIG. 6A, and the output terminals of the comparators CMPa and CMPb are electrically connected to the input terminals of the conversion circuit TRF. A specific example of the conversion circuit TRF is a digital-to-analog conversion circuit (in this case, the signal z j (k) is an analog value.)

[0119] 6A, the line VrefL electrically connected to the second input terminals of comparators CMPa and CMPb may be replaced with separate lines Vref1L and Vref2L. The circuit ACTF[j] in FIG. 6C is configured such that the second terminal of comparator CMPa included in the circuit ACTF[j] in FIG. 6A is electrically connected to line Vref1L instead of line VrefL, and the second terminal of comparator CMPb is electrically connected to line Vref2L instead of line VrefL. By setting the potentials input to line Vref1L and line Vref2L to different values, the reference potentials of comparators CMPa and CMPb can be set separately.

[0120] 6A to 6C, an amplifier circuit or an impedance conversion circuit may be used. For example, the circuit ACTF[j] shown in FIG. 6D can be applied to the circuit AFP of the arithmetic circuit 110 in FIG. 2. The circuit ACTF[j] in FIG. 6D has resistors RE, REB, and operational amplifiers OPa and OPb, and functions as an amplifier circuit.

[0121] The wiring OL[j] is electrically connected to the first terminal of the resistor RE and the non-inverting input terminal of the operational amplifier OPa, and the wiring OLB[j] is electrically connected to the first terminal of the resistor REB and the non-inverting input terminal of the operational amplifier OPb. The inverting input terminal of the operational amplifier OPa is electrically connected to the output terminal of the operational amplifier OPa, and the inverting input terminal of the operational amplifier OPb is electrically connected to the output terminal of the operational amplifier OPb. Furthermore, the second terminal of the resistor RE is electrically connected to the wiring VAL, and the second terminal of the resistor REB is electrically connected to the wiring VAL.

[0122] In other words, the operational amplifiers OPa and OPb included in the circuit ACTF[j] in Figure 6D are connected in a voltage follower configuration. As a result, the potential output from the output terminal of the operational amplifier OPa is approximately equal to the potential input to the non-inverting input terminal of the operational amplifier OPa, and the potential output from the output terminal of the operational amplifier OPb is approximately equal to the potential input to the non-inverting input terminal of the operational amplifier OPb. In this case, the output signal z j (k) are output from the circuit ACTF[j] as two analog values. The output terminal of the operational amplifier OPa and the output terminal of the operational amplifier OPb may be connected to the input terminal of the comparator CMP. Then, the output from the comparator CMP is used as the output signal z j (k) It may also be possible to use the following.

[0123] 6A to 6D, an integrating circuit or a current-voltage conversion circuit may be used. Furthermore, an operational amplifier may be used to configure the integrating circuit or the current-voltage conversion circuit. As an example, the circuit ACTF[j] shown in FIG. 6E can be applied to the circuit AFP of the arithmetic circuit 110 in FIG. 2. The circuit ACTF[j] in FIG. 6E includes operational amplifiers OPa and OPb, and loads LEa and LEb.

[0124] The wiring OL[j] is electrically connected to a first input terminal (e.g., inverting input terminal) of the operational amplifier OPa and a first terminal of the load LEa, and the wiring OLB[j] is electrically connected to a first input terminal (e.g., inverting input terminal) of the operational amplifier OPb and a first terminal of the load LEb. Furthermore, the second input terminal (e.g., non-inverting input terminal) of the operational amplifier OPa is electrically connected to the wiring Vref1L, and the second input terminal (e.g., non-inverting input terminal) of the operational amplifier OPb is electrically connected to the wiring Vref2L. The second terminal of the load LEa is electrically connected to the output terminal of the operational amplifier OPa, and the second terminal of the load LEa is electrically connected to the output terminal of the operational amplifier OPb.

[0125] The wiring Vref1L and wiring Vref2L function as wirings that supply the same voltage or different voltages. Therefore, the wiring Vref1L and wiring Vref2L can sometimes be combined into one wiring.

[0126] In the circuit ACTF[j] of FIG. 6E, the loads LEa and LEb can be, for example, resistors and capacitors. In particular, by using capacitors as the loads LEa and LEb, the operational amplifier OPa and the load LEa, and the operational amplifier OPb and the load LEb, respectively, function as integrating circuits. That is, a charge is stored in each capacitor (load LEa, load LEb) according to the amount of current flowing through the wiring OL[j] or wiring OLB[j]. That is, the current flowing from the wiring OL[j] or wiring OLB[j] is integrated by the integrating circuit, and the amount of current is converted into a voltage, which is output as a signal z j (k) The output terminal of the operational amplifier OPa and the output terminal of the operational amplifier OPb may be connected to the input terminal of the comparator CMP. Then, the output from the comparator CMP is output as the output signal z j (k)A circuit for initializing the charges accumulated in the capacitances of the loads LEa and LEb may be provided. For example, a switch may be provided in parallel with the load LEa (capacitor). That is, a second terminal of the switch may be connected to the output terminal of the operational amplifier OPa, and a first terminal of the switch may be connected to the line OL[j] and a first input terminal (e.g., the inverting input terminal) of the operational amplifier OPa.

[0127] Furthermore, in the circuit ACTF[j] of FIG. 6E, if you want to convert the current flowing from the wiring OL[j] and wiring OLB[j] into a voltage and output it, you can use resistors other than capacitors as the loads LEa and LEb.

[0128] 6A to 6E, the circuit ACTF[j] shown in Fig. 6F can be applied to the circuit AFP of the arithmetic circuit 110 in Fig. 2. The circuit ACTF[j] in Fig. 4F has a resistor RE, a resistor REB, an analog-to-digital conversion circuit ADCa, and an analog-to-digital conversion circuit ADCb.

[0129] The wiring OL[j] is electrically connected to the input terminal of the analog-to-digital conversion circuit ADCa and the first terminal of the resistor RE, the wiring OLB[j] is electrically connected to the input terminal of the analog-to-digital conversion circuit ADCb and the first terminal of the resistor REB, the second terminal of the resistor RE is electrically connected to the wiring VAL, and the second terminal of the resistor REB is electrically connected to the wiring VAL.

[0130] In the circuit ACTF[j] of FIG. 6F, the potentials of the first terminals of the resistors RE and REB are determined according to the currents flowing from the wirings OL[j] and OLB[j]. The circuit ACTF[j] then converts the analog potentials into digital values ​​of two or more values ​​(for example, 256 values) using the analog-to-digital converters ADCa and ADCb, and outputs the signal z j (k) It has the function of outputting as

[0131] 6A to 6D and 6F can be replaced with capacitances CE and CEB, or diode elements DE and DEB, as in the case of Figures 5B and 5C. In particular, when the resistances RE and REB shown in Figures 6A to 6D and 6F are replaced with capacitances CE and CEB, the potentials input from the wirings OL[j] and OLB[j] can be held by providing switches S01a and S01b, as in the case of Figure 5E.

[0132] 2 to 4 illustrate examples in which wirings IL, ILB, OL, and OLB are arranged in the arithmetic circuits 110, 120, and 130, respectively. However, one embodiment of the present invention is not limited to this. For example, in each of the arithmetic circuits 110, 120, and 130, the wirings IL and OL may be combined into one wiring, and the wirings ILB and OLB may be combined into one wiring. FIG. 7 illustrates a specific configuration. The arithmetic circuit 140 illustrated in FIG. 7 includes switching circuits TW[1] to TW[n].

[0133] Each of the switching circuits TW[1] to TW[n] has a terminal TSa, a terminal TSaB, a terminal TSb, a terminal TSbB, a terminal TSc, and a terminal TScB.

[0134] The terminal TSa is electrically connected to the wiring OL[j], the terminal TSbB is electrically connected to the circuit ILD, and the terminal TSc is electrically connected to the circuit ACTF[i]. The terminal TSaB is electrically connected to the wiring OLB[j], the terminal TSbB is electrically connected to the circuit ILD, and the terminal TScB is electrically connected to the circuit ACTF[j].

[0135] The switching circuit TW[j] has a function of establishing a conductive state between the terminal TSa and either the terminal TSb or the terminal TSc, and a non-conductive state between the terminal TSa and the other of the terminal TSb or the terminal TSc. The switching circuit TW[j] also has a function of establishing a conductive state between the terminal TSaB and either the terminal TSbB or the terminal TScB, and a non-conductive state between the terminal TSaB and the other of the terminal TSbB or the terminal TScB.

[0136] That is, the first data w1, which is a weighting coefficient, is assigned to any one of the circuits MP[1,j] to MP[m,j]. (k-1) 1 (k) Or even w m (k-1) n (k) When it is desired to input information (for example, a potential, a resistance value, a current value, etc.) corresponding to the first data w1 from the circuit ILD to the wiring OL[j] and the wiring OLB[j], the first data w1 is transmitted from the circuit ILD to the wiring OL[j] and the wiring OLB[j] by bringing the terminals TSa and TSb into a conductive state and bringing the terminals TSaB and TSbB into a conductive state in the switching circuit TW[j]. (k-1) 1 (k) Or even w m (k-1) n (k) It is possible to provide information (for example, potential, resistance value, current value, etc.) corresponding to the above.

[0137] Furthermore, when the circuit ACTF[j] wants to obtain the result of the sum of products (equation (1.2)) of the weight coefficients and the neuron signals calculated by the circuits MP[1,j] to MP[m,j], the switching circuit TW[j] can supply information (e.g., potential, current value, etc.) corresponding to the result of the sum of products from the wiring OL[j] and wiring OLB[j] to the circuit ACTF[j] by bringing the terminals TSa and TSc into a conductive state and bringing the terminals TSaB and TScB into a conductive state. Also, in the circuit ACTF[j], the value of the activation function is calculated from the input result of the sum of products, and the signal z is output as the neuron's output signal. j (k) can be obtained.

[0138] Next, a description will be given of the switching circuit TW[j] and the circuit ILD included in the arithmetic circuit 140. Fig. 8A shows a configuration example of the switching circuit TW[j] and the circuit ILD that can be applied to the arithmetic circuit 140. Note that Fig. 8A also shows a wiring OL[j], a wiring OLB[j], and a circuit AFP to show the configuration of the electrical connection between the switching circuit TW[j] and the circuit ILD.

[0139] The switching circuit TW[j] includes, for example, a switch SWI, a switch SWIB, a switch SWO, a switch SWOB, a switch SWL, a switch SWLB, a switch SWH, and a switch SWHB.

[0140] As an example, the circuit ILD includes a current source circuit ISC. However, one embodiment of the present invention is not limited to this. For example, a voltage source circuit may be provided instead of the current source circuit ISC. The current source circuit ISC has a function of supplying a current to the wiring OL[j] and / or the wiring OLB[j] according to a weighting coefficient (first data) input to the circuit MP. Note that at least one current source circuit ISC may be provided as a circuit for the wiring OL[j] and a circuit for the wiring OLB[j], as separate circuits. Alternatively, as shown in FIG. 8A, at least one current source circuit ISC may be provided for a pair of wirings, OL[j] and OLB[j].

[0141] The current source circuit ISC has one or more constant current sources. In FIG. 8A, as an example, the multiple constant current sources include constant current source circuit ISC1, constant current source circuit ISC2, and constant current source circuit ISC3. The current source circuit ISC also has, as an example, multiple switches for selecting the multiple constant current sources. In FIG. 8A, the multiple switches include switch SWC1, switch SWC2, and switch SWC3. If the current source circuit ISC has only one constant current source, the constant current source circuit ISC does not need to have a switch. Alternatively, if the constant current source circuit ISC1, constant current source circuit ISC2, and constant current source circuit ISC3 each have a function for controlling whether or not to output a current, then switches SWC1, SWC2, and SWC3 may not be provided.

[0142] As shown in FIG. 8A, it is preferable that the currents flowing through the wiring OL[j] and the wiring OLB[j] are generated by the same current source circuit ISC. If the currents flowing through the wiring OL[j] and the wiring OLB[j] are generated by different current source circuits, variations in the characteristics of the transistors due to factors such as the transistor manufacturing process may occur, resulting in differences in performance between the different current source circuits. On the other hand, if the same current source circuit is used, it is possible to supply the same amount of current to the wiring OL[j] and the wiring OLB[j], thereby improving calculation accuracy.

[0143] As for the switches SWI, SWIB, SWO, SWOB, SWL, SWLB, SWH, SWHB, SWC1, SWC2, and SWC3 described in FIG. 8A, similar to the switches S01a and S01b, analog switches, electrical switches such as transistors, mechanical switches, etc. can be applied.

[0144] In one example of the switching circuit TW[j], the terminal TSa is electrically connected to a first terminal of the switch SWI, a first terminal of the switch SWO, a first terminal of the switch SWL, and a first terminal of the switch SWH. The terminal TSaB is electrically connected to a first terminal of the switch SWIB, a first terminal of the switch SWOB, a first terminal of the switch SWLB, and a first terminal of the switch SWHB. The second terminal of the switch SWI is electrically connected to a terminal TSb1. The second terminal of the switch SWIB is electrically connected to a terminal TSbB1. The second terminal of the switch SWO is electrically connected to a terminal TSc. The second terminal of the switch SWOB is electrically connected to a terminal TScB. The second terminal of the switch SWL is electrically connected to a terminal TSb2. The second terminal of the switch SWLB is electrically connected to a terminal TSbB2. The second terminal of the switch SWH is electrically connected to a terminal TSb3. The second terminal of the switch SWHB is electrically connected to a terminal TSbB3.

[0145] Terminals TSb1, TSb2, and TSb3 shown in Fig. 8A correspond to the terminal TSb shown in Fig. 7. Furthermore, terminals TSbB1, TSbB2, and TSbB3 shown in Fig. 8A correspond to the terminal TSbB shown in Fig. 7.

[0146] In the current source circuit ISC included in the circuit ILD, the terminal TSb1 is electrically connected to a first terminal of the switch SWC1, a first terminal of the switch SWC2, and a first terminal of the switch SWC3. Furthermore, the terminal TSbB1 is electrically connected to a first terminal of the switch SWC1, a first terminal of the switch SWC2, and a first terminal of the switch SWC3. The second terminal of the switch SWC1 is electrically connected to the output terminal of the constant current source circuit ISC1, the second terminal of the switch SWC2 is electrically connected to the output terminal of the constant current source circuit ISC2, and the second terminal of the switch SWC3 is electrically connected to the output terminal of the constant current source circuit ISC3. The input terminal of the constant current source circuit ISC1, the input terminal of the constant current source circuit ISC2, and the input terminal of the constant current source circuit ISC3 are each electrically connected to the wiring VSO.

[0147] 8A, the constant current source circuits ISC1, ISC2, and ISC3 each have an output terminal electrically connected to a terminal of a switch and an input terminal electrically connected to a wiring VSO. However, one embodiment of the present invention is not limited to this. For example, the constant current source circuits ISC1, ISC2, and ISC3 may each have an input terminal electrically connected to a terminal of a switch and an output terminal electrically connected to a wiring VSO. Note that a wiring VCN2 may be provided to initialize the potentials of the wiring OL[j] and the wiring OLB[j] before a current is output from the circuit MP. The wiring VCN2 is connected to the wiring OL[j] via a switch SWH. The wiring VCN2 is also connected to the wiring OLB[j] via a switch SWHB. A potential different from that of the wiring VCN can be supplied to the wiring VCN2. For example, when VSS or a ground potential is supplied to the wiring VCN, VDD or the like is supplied to the wiring VCN2. This allows the potentials of the wiring OL[j] and the wiring OLB[j] to be changed by the current output from the circuit MP.

[0148] Specific configuration examples of the constant current source circuits ISC1, ISC2, and ISC3 are shown in Figures 8B and 8C. The constant current source circuit ISC1 (constant current source circuits ISC2 and ISC3) shown in Figure 8B has a p-channel transistor, a first terminal of which is electrically connected to the wiring VSO, a second terminal of which is electrically connected to the second terminal of the switch SWC1 (switches SWC2 and SWC3), and a gate of which is electrically connected to the wiring VB. The constant current source circuit ISC1 (constant current source circuits ISC2 and ISC3) shown in Figure 8C has an n-channel transistor, a first terminal of which is electrically connected to the wiring VSO, a second terminal of which is electrically connected to the second terminal of the switch SWC1 (switches SWC2 and SWC3), and a gate of which is electrically connected to the wiring VB. In each of the constant current source circuits ISC1 (constant current source circuits ISC2 and ISC3) in Figures 8B and 8C, the wiring VB functions as a wiring for inputting a bias voltage to the gate of each transistor. A pulse signal may be supplied to the wiring VB, thereby controlling whether or not a current is output from each constant current source circuit. In this case, the switches SWC1, SWC2, and SWC3 do not need to be provided. Alternatively, an analog voltage may be supplied to the wiring VB, thereby allowing an analog current to be supplied from the constant current source circuit.

[0149] The wiring VSO functions as a wiring that supplies a constant voltage to each of the constant current source circuits ISC1, ISC2, and ISC3. For example, when a current is supplied from the circuit ILD to the wiring OL or OLB via the switching circuit TW[j], the constant voltage is preferably a potential higher than ground potential (e.g., VDD). Furthermore, it is preferable to use the constant current source circuit ISC1 (constant current source circuit ISC2, constant current source circuit ISC3) shown in FIG. 8B. Furthermore, when a current is supplied from the circuit ILD to the wiring OL or OLB via the switching circuit TW[j], the constant voltage is preferably a potential higher than ground potential but lower than the high-level potential, such as ground potential. Furthermore, it is preferable to use the constant current source circuit ISC1 (constant current source circuit ISC2, constant current source circuit ISC3) shown in FIG. 8C. Note that in this specification, the current flowing from the circuit ILD to the wiring OL or OLB via the switching circuit TW[j] may be referred to as a positive current. Therefore, the current flowing from the wiring OL or the wiring OLB to the circuit ILD via the switching circuit TW[j] may be referred to as a negative current.

[0150] By the way, the current flowing from the constant current source circuit ISC1 is I ut As an example, the current flowing through the constant current source circuit ISC2 is 2I ut It is preferable that the current flowing from the constant current source circuit ISC3 is 4I ut That is, when the current source circuit ISC has P constant current sources (P is an integer of 1 or more), the current flowing from the p-th constant current source (p is an integer of 1 or more and P or less) is preferably 2 (p-1) ×I ut In this way, the magnitude of the current flowing from the current source circuit ISC can be changed.

[0151] For example, let us assume that the number of constant current sources in the current source circuit ISC is three (P=3). utIf you want to pass a current of 5I, you can turn on the switch SWI, turn off the switch SWIB, turn on the switch SWC1, and turn off the switches SWC2 and SWC3. ut To flow a current of 1, the switches SWC1 and SWC3 are turned on and the switch SWC2 is turned off. In other words, the current output from the current source circuit ISC can be one of eight values ​​("0", "I"). ut ", "2I ut ", "3I ut ", "4I ut ", "5I ut ", "6I ut ", "7I ut ) can be any one of eight values. If it is desired to output a current with more than eight values, the number of constant current sources should be four or more. Similarly, by turning the switch SWI off and the switch SWIB on, it is possible to pass any one of eight current values ​​through the wiring OLB[j]. If no current is to be output from the current source circuit ISC, the switches SWC1 to SWC3 of the current source circuit ISC may not be turned off, and the switches SWI and SWIB of the switching circuit TW may be turned off. By arranging multiple constant current sources in this way, it is possible to easily achieve DA conversion. It is also possible to arrange only one current source circuit and operate it to change the current value that is output in an analog manner.

[0152] In the circuit ILD, the terminal TSb2 is electrically connected to the wiring VCN, and the terminal TSbB2 is electrically connected to the wiring VCN.

[0153] The wiring VCN functions as a wiring that supplies a constant voltage to the wiring OL[j] and / or the wiring OLB[j]. For example, when a current (positive current) is supplied from the circuit ILD to the wiring OL or the wiring OLB via the switching circuit TW[j], the constant voltage provided by the wiring VCN is preferably a low-level potential (e.g., VSS). Furthermore, when a current (negative current) is supplied from the wiring OL or the wiring OLB to the circuit ILD via the switching circuit TW[j], the constant potential provided by the wiring VCN is preferably a high-level potential. Note that, as shown in FIGS. 42 to 45 (described later), if the capacitor C3 is connected to the source terminal of a transistor M1 or the like and the source terminal is not connected to a power supply line, when a positive current is supplied from the circuit ILD to the wiring OL or the wiring OLB via the switching circuit TW[j], the constant voltage provided by the wiring VCN is preferably a high-level potential (e.g., VDD). That is, when a constant voltage is supplied from the wiring VCN, it is desirable to make the potential difference across the capacitor C3 close to zero. In other words, it is desirable to supply a potential to the wiring VCN such that no current is output from the circuit MC.

[0154] In the circuit ILD, the terminal TSb3 is electrically connected to the wiring VCN2, and the terminal TSbB3 is electrically connected to the wiring VCN2.

[0155] The wiring VCN2 functions as a wiring that supplies a constant voltage to the wiring OL[j] and / or the wiring OLB[j]. For example, when a current (positive current) is supplied from the circuit ILD to the wiring OL or the wiring OLB via the switching circuit TW[j], the constant voltage supplied by the wiring VCN is preferably a high-level potential (e.g., VDD). Furthermore, for example, when a current (negative current) is supplied from the wiring OL or the wiring OLB to the circuit ILD via the switching circuit TW[j], the constant potential supplied by the wiring VCN is preferably a low-level potential.

[0156] The switching circuit TW[j] can change the circuit that is in a conductive state with the wiring OL[j] and the wiring OLB[j] by switching each of the switches SWI, SWIB, SWO, SWOB, SWL, SWLB, SWH, and SWHB to an on or off state.

[0157] Here, the weighting coefficients input to the circuit MP will be explained.

[0158] When a positive weighting coefficient is to be input to the circuit MP, a current corresponding to the weighting coefficient is input to the wiring OL[j], and a constant potential provided by the wiring VCN is input to the wiring OLB[j]. As an example, the current source circuit ISC and the wiring OL[j] are brought into a conductive state, the current source circuit ISC and the wiring OLB[j] are brought into a non-conductive state, the circuit AFP and the wiring OL[j] are brought into a non-conductive state, the circuit AFP and the wiring OLB[j] are brought into a non-conductive state, the wiring VCN and the wiring OL[j] are brought into a non-conductive state, the wiring VCN and the wiring OLB[j] are brought into a conductive state, the wiring VCN2 and the wiring OL[j] are brought into a non-conductive state, and the wiring VCN2 and the wiring OLB[j] are brought into a non-conductive state. That is, in the switching circuit TW[j], the switches SWI and SWLB are turned on, and the switches SWIB, SWO, SWOB, SWL, SWH, and SWHB are turned off. This brings the current source circuit ISC and the wiring OL[j] into a conductive state, allowing current to flow from the current source circuit ISC to the circuit MP via the wiring OL[j]. When the number of constant current sources in the current source circuit ISC is P, the current is calculated as follows: P The positive weighting coefficient input to the circuit MP is determined according to the current, so the weighting coefficient is 2 P The value can be any one of the values ​​−1. Furthermore, since the wiring VCN and the wiring OLB[j] are in a conductive state, a constant voltage is input from the wiring VCN to the wiring OLB[j].

[0159] Furthermore, when a negative weighting coefficient is to be input to the circuit MP, a current corresponding to the weighting coefficient is input to the wiring OLB[j], and a constant potential provided by the wiring VCN is input to the wiring OL[j]. As an example, the current source circuit ISC and the wiring OL[j] are brought into a non-conductive state, the current source circuit ISC and the wiring OLB[j] are brought into a conductive state, the circuit AFP and the wiring OL[j] are brought into a non-conductive state, the circuit AFP and the wiring OLB[j] are brought into a non-conductive state, the wiring VCN and the wiring OL[j] are brought into a conductive state, the wiring VCN and the wiring OLB[j] are brought into a non-conductive state, the wiring VCN2 and the wiring OL[j] are brought into a non-conductive state, and the wiring VCN2 and the wiring OLB[j] are brought into a non-conductive state. That is, in the switching circuit TW[j], the switches SWIB and SWL are turned on, and the switches SWI, SWO, SWOB, SWLB, SWH, and SWHB are turned off. This brings the current source circuit ISC and the wiring OLB[j] into a conductive state, allowing current to flow from the current source circuit ISC to the circuit MP via the wiring OLB[j]. When the number of constant current sources in the current source circuit ISC is P, the current is calculated as follows: P The negative weighting coefficient input to the circuit MP is determined according to the current, so the weighting coefficient is 2 P The value can be any one of the values ​​−1. Furthermore, since the wiring VCN and the wiring OL[j] are in a conductive state, a constant voltage is input from the wiring VCN to the wiring OL[j].

[0160] Furthermore, when a weighting coefficient of 0 is to be input to the circuit MP, the constant potential provided by the wiring VCN is input to each of the wirings OL[j] and OLB[j]. For example, the current source circuit ISC and the wiring OL[j] are brought into a non-conductive state, the current source circuit ISC and the wiring OLB[j] are brought into a non-conductive state, the circuit AFP and the wiring OL[j] are brought into a non-conductive state, the circuit AFP and the wiring OLB[j] are brought into a non-conductive state, the wiring VCN and the wiring OL[j] are brought into a conductive state, the wiring VCN and the wiring OLB[j] are brought into a conductive state, the wiring VCN2 and the wiring OL[j] are brought into a non-conductive state, and the wiring VCN2 and the wiring OLB[j] are brought into a non-conductive state. That is, in the switching circuit TW[j], the switches SWL and SWLB are turned on, and the switches SWI, SWIB, SWO, and SWOB are turned off. This brings about a state of conduction between the wiring VCN and the wiring OL[j], and between the wiring VCN and the wiring OLB[j], so that a constant voltage is input from the wiring VCN to the wiring OL[j] and OLB[j].

[0161] In other words, by setting the number of constant current sources in the current source circuit ISC to P, the number of weighting coefficients that can be input to the circuit MP (the sum of positive weighting coefficients, negative weighting coefficients, and 0 weighting coefficients) is 2 P+1 -1 piece.

[0162] Next, a case where information (for example, potential, current, etc.) is supplied from the circuit MP to the circuit AFP will be described.

[0163] Before supplying information (e.g., potential, current, etc.) from the circuit MP to the circuit AFP, it is preferable to set the wiring OL[j] and the wiring OLB[j] to a predetermined potential. For example, when a positive current flows from the circuit AFP to the circuit MP through the wiring OL or the wiring OLB, the predetermined potential is preferably a high-level potential. Furthermore, when a positive current flows from the circuit MP to the circuit AFP through the wiring OL or the wiring OLB, the predetermined potential is preferably a low-level potential. Therefore, before supplying information (e.g., potential, current, etc.) from the circuit MP to the circuit AFP, for example, the current source circuit ISC and the wiring OL[j] may be brought into a non-conductive state, the current source circuit ISC and the wiring OLB[j] may be brought into a non-conductive state, the circuit AFP and the wiring OL[j] may be brought into a non-conductive state, the circuit AFP and the wiring OLB[j] may be brought into a non-conductive state, the wiring VCN and the wiring OL[j] may be brought into a non-conductive state, the wiring VCN and the wiring OLB[j] may be brought into a conductive state, and the wiring VCN2 and the wiring OL[j] may be brought into a conductive state. That is, in the switching circuit TW[j], the switches SWH and SWHB may be turned on, and the switches SWI, SWIB, SWO, SWOB, SWL, and SWLB may be turned off. This brings about a state of conduction between the wiring OL[j] and the wiring VCN2, and between the wiring OLB[j] and the wiring VCN2, so that a constant voltage from the wiring VCN2 is input to the wiring OL and the wiring OLB.

[0164] When supplying information (e.g., potential, current, etc.) from the circuit MP[i,j] to the circuit AFP, for example, the current source circuit ISC and the wiring OL[j] may be brought into a non-conductive state, the current source circuit ISC and the wiring OLB[j] may be brought into a non-conductive state, the circuit AFP and the wiring OL[j] may be brought into a conductive state, the circuit AFP and the wiring OLB[j] may be brought into a conductive state, the wiring VCN and the wiring OL[j] may be brought into a non-conductive state, the wiring VCN and the wiring OLB[j] may be brought into a non-conductive state, the wiring VCN2 and the wiring OL[j] may be brought into a non-conductive state, and the wiring VCN2 and the wiring OLB[j] may be brought into a non-conductive state. That is, in the switching circuit TW[j], the switches SWO and SWOB may be turned on, and the switches SWI, SWIB, SWL, SWLB, SWH, and SWHB may be turned off. This brings the circuit AFP and the circuit MP[i,j] into a conductive state, so that information (for example, potential, current, etc.) can be supplied from the circuit MP[i,j] to the circuit AFP.

[0165] <<Circuit MP>> Next, an example of the configuration of the circuits MP[i,j] included in the arithmetic circuit 110, the arithmetic circuit 120, the arithmetic circuit 130, and the arithmetic circuit 140 will be described.

[0166] FIG. 9A shows an example of the configuration of a circuit MP[i,j] applicable to the arithmetic circuit 140. The circuit MP[i,j] includes, for example, a circuit MC and a circuit MCr. The circuit MC and the circuit MCr are circuits that calculate the product of the weight coefficient and the input signal (operation value) of the neuron in the circuit MP. The circuit MC can have the same configuration as the circuit MCr or a different configuration from the circuit MCr. Therefore, the circuit MCr is designated with an "r" in order to distinguish it from the circuit MC. Furthermore, the circuit elements included in the circuit MCr, which will be described later, are also designated with an "r."

[0167] For example, the circuit MC has a holding unit HC, and the circuit MCr has a holding unit HCr. The holding unit HC and the holding unit HCr each have a function of holding information (for example, potential, resistance value, current value, etc.). Note that the first data w set in the circuit MP[i,j] i (k-1) j (k) is determined according to the information (for example, potential, resistance value, current value, etc.) held in each of the holding units HC and HCr. i (k-1) j (k) The wiring OL[j] and the wiring OLB[j] are electrically connected to supply various pieces of information (for example, potential, resistance value, current value, etc.) according to the above.

[0168] In FIG. 9A, the circuit MP[i,j] is electrically connected to the wiring VE[j] and the wiring VEn[j]. The wiring VE[j] and the wiring VEn[j] function as wirings that supply a constant voltage. The wiring VE[j] also functions as a wiring that drains current from the wiring OL via the circuit MC. The wiring VEn[j] also functions as a wiring that drains current from the wiring OLB via the circuit MCr.

[0169] The wiring WL[i] shown in FIG. 9A corresponds to the wiring WL[i] in FIG. 7. The wiring WL[i] is electrically connected to the holding unit HC and the holding unit HCr. The first data w i (k-1) j (k) When writing information (for example, a potential, a resistance value, a current value, etc.) according to the first data w, a predetermined potential is supplied to the wiring WL[i], thereby bringing the wiring OL[j] and the holding unit HC into a conductive state, and bringing the wiring OLB[j] and the holding unit HCr into a conductive state. i (k-1) j (k)By supplying a potential or the like according to the data w, the potential or the like can be input to each of the holding units HC and HCr. After that, a predetermined potential is supplied to the wiring WL[i] to put the wiring OL[j] and the holding unit HC in a non-conductive state, and also put the wiring OLB[j] and the holding unit HCr in a non-conductive state. Then, the first data w is input to each of the holding units HC and HCr. i (k-1) j (k) Each current according to the above is maintained.

[0170] For example, the first data w i (k-1) j (k) Let us consider the case where the first data w takes one of three values: "-1", "0", or "1". i (k-1) j (k) When the first data w is "1", for example, a predetermined potential is held in the holding unit HC so that a current corresponding to "1" flows from the wiring OL[j] to the wiring VE[j] via the circuit MC, and a potential V0 is held in the holding unit HCr so that a current does not flow from the wiring OLB[j] to the wiring VE[j] via the circuit MCr. i (k-1) j (k) is "-1", for example, the potential V0 is held in the holding unit HC so that no current flows from the wiring OL[j] to the wiring VE[j] via the circuit MC, and a predetermined potential is held in the holding unit HCr so that a current corresponding to "-1" flows from the wiring OLB[j] to the wiring VE[j] via the circuit MCr. i (k-1) j (k) is "0", for example, the potential V0 is held in the holding unit HC so that no current flows from the wiring OL[j] to the wiring VE[j] via the circuit MC, and the potential V0 is held in the holding unit HCr so that no current flows from the wiring OLB[j] to the wiring VEr[j] via the circuit MC. Note that the potential V0 can be the potential provided by the wiring VCN in the description of FIG. 8.

[0171] As another example, the first data w i (k-1) j (k) Let us consider the case where the first data w is an analog value, specifically, a "negative analog value", "0", or a "positive analog value". i (k-1) j (k) is a "positive analog value," for example, a predetermined potential is held in the holding unit HC so that an analog current corresponding to the "positive analog value" flows from the wiring OL[j] to the wiring VE[j] via the circuit MC, and a potential V0 is held in the holding unit HCr so that no current flows from the wiring OLB[j] to the wiring VE[j] via the circuit MCr. i (k-1) j (k) is a "negative analog value," for example, a potential V0 is held in the holding unit HC so that no current flows from the wiring OL[j] to the wiring VE[j] via the circuit MC, and a predetermined potential is held in the holding unit HCr so that an analog current corresponding to the "negative analog value" flows from the wiring OLB[j] to the wiring VE[j] via the circuit MCr. i (k-1) j (k) is "0", for example, the potential V0 is held in the holding unit HC so that no current flows from the wiring OL[j] to the wiring VE[j] via the circuit MC, and the potential V0 is held in the holding unit HCr so that no current flows from the wiring OLB[j] to the wiring VEr[j] via the circuit MC. Note that the potential V0 can be the potential provided by the wiring VCN in the description of FIG. 8, as in the previous example.

[0172] Furthermore, as an example, the circuit MC has a function of outputting a current or the like corresponding to information (e.g., potential, resistance value, or current value) held in the holding unit HC to one of the wiring OL[j] or the wiring OLB[j], and the circuit MCr has a function of outputting a current or the like corresponding to information (e.g., potential, resistance value, or current value) held in the holding unit HCr to the other of the wiring OL[j] or the wiring OLB[j]. For example, when a first potential is held in the holding unit HC, the circuit MC flows a current having a first current value from the wiring OL[j] or the wiring OLB[j] to the wiring VE, and when a second potential is held in the holding unit HC, the circuit MC flows a current having a second current value from the wiring OL[j] or the wiring OLB[j] to the wiring VE. Similarly, when a first potential is held in the holding unit HCr, the circuit MCr flows a current having a first current value from the wiring OL[j] or wiring OLB[j] to the wiring VE, and when a second potential is held in the holding unit HCr, the circuit MCr flows a current having a second current value from the wiring OL[j] or wiring OLB[j] to the wiring VE. The magnitudes of the first current value and the second current value are respectively determined by the first data w i (k-1) j (k) The first current value is determined by the value of . As an example, the first current value may be greater than or less than the second current value. Furthermore, as another example, one of the first current value and the second current value may be zero current, i.e., the current value may be 0. Alternatively, the current having the first current value and the current having the second current value may flow in different directions.

[0173] In particular, for example, the first data w i (k-1) j (k) When the first data w takes one of the three values ​​"-1", "0", and "1", it is preferable to configure the circuits MC and MCr so that either the first current value or the second current value becomes zero. i (k-1) j (k)takes an analog value, for example, a "negative analog value," "0," or a "positive analog value," the first current value or the second current value can also take an analog value, for example.

[0174] However, when the current flowing from the wiring OL[j] or the wiring OLB[j] to the wiring VE through the circuit MC is made equal to the current flowing from the wiring OL[j] or the wiring OLB[j] to the wiring VE through the circuit MCr, the potential held in the circuit MC may not be equal to the potential held in the circuit MCr because the characteristics of the transistors may vary due to a manufacturing process of the transistors, etc. In the semiconductor device of one embodiment of the present invention, even if the characteristics of the transistors vary, the amount of current flowing from the wiring OL[j] or the wiring OLB[j] to the wiring VE through the circuit MC can be made approximately equal to the amount of current flowing from the wiring OL[j] or the wiring OLB[j] to the wiring VE through the circuit MC.

[0175] In this specification, the current or voltage corresponding to the information (e.g., potential, resistance value, or current value) stored in the storage unit HC and the storage unit HCr may be a positive current or voltage, a negative current or voltage, a zero current or zero voltage, or a mixture of positive, negative, and zero. In other words, for example, the above description "has the function of outputting a current or voltage corresponding to the information (e.g., potential, resistance value, or current value) held in the holding unit HC to one of the wiring OL[j] or the wiring OLB[j], and the circuit MCr has the function of outputting a current or voltage corresponding to the information (e.g., potential, resistance value, or current value) held in the holding unit HCr to the other of the wiring OL[j] or the wiring OLB[j]" can be rephrased as "has the function of discharging a current, voltage, etc. corresponding to the information (e.g., potential, resistance value, or current value) held in the holding unit HC from one of the wiring OL[j] or the wiring OLB[j], and the circuit MCr has the function of discharging a current, voltage, etc. corresponding to the information (e.g., potential, resistance value, or current value) held in the holding unit HCr from the other of the wiring OL[j] or the wiring OLB[j]."

[0176] The wiring X1L[i] and the wiring X2L[i] shown in FIG. 9A correspond to the wiring XLS[i] in FIG. 7. Note that the second data z i (k-1) For example, the second data z i (k-1) Each potential corresponding to the above is input.

[0177] The circuit MC is electrically connected to the wiring OL[j] and the wiring OLB[j], and the circuit MCr is electrically connected to the wiring OL[j] and the wiring OLB[j]. For example, the circuit MC and the circuit MCr transmit the first data w to the wiring OL[j] and the wiring OLB[j] in response to a potential or a current input to the wiring X1L[i] and the wiring X2L[i]. i (k-1) j (k) and the second data z i (k-1) and outputs a current or potential according to the product of these. As a specific example, the destination of the current output from the circuits MC and MCr is determined by the potentials of the wirings X1L[i] and X2L[i]. For example, the circuits MC and MCr are configured so that the current output from the circuit MC flows to either the wiring OL[j] or the wiring OLB[j], and the current output from the circuit MCr flows to the other wiring OL[j] or the wiring OLB[j]. In other words, the currents output from the circuits MC and MCr do not flow through the same wiring, but through different wirings. Note that, as an example, there may be cases where no current flows from the circuits MC and MCr to either the wiring OL[j] or the wiring OLB[j].

[0178] For example, the second data z i (k-1) Consider the case where the second data z takes one of three values: "-1", "0", or "1". i (k-1)is "1", the circuit MP brings the circuit MC and the wiring OL[j] into a conductive state, and brings the circuit MCr and the wiring OLB[j] into a conductive state. For example, i (k-1) is "-1", the circuit MP brings the circuit MC and the wiring OLB[j] into a conductive state, and brings the circuit MCr and the wiring OL[j] into a conductive state. For example, i (k-1) When is "0", in order to prevent the currents output by the circuits MC and MCr from flowing to either the wiring OL[j] or the wiring OLB[j], the circuit MP brings the circuit MC and the wiring OL[j] and the circuit MC and the wiring OLB[j] into a non-conductive state, and brings the circuit MCr and the wiring OL[j] and the circuit MC and the wiring OLB[j] into a non-conductive state.

[0179] An example of the above operations is shown below. i (k-1) j (k) When the first data w is "1", a current may flow from the wiring OL[j] or wiring OLB[j] to the wiring VE[j] via the circuit MC, and a current does not flow from the wiring OL[j] or wiring OLB[j] to the wiring VE[j] via the circuit MCr. i (k-1) j (k) When the second data z is "-1", current may not flow from the wiring OL[j] or wiring OLB[j] to the wiring VE[j] via the circuit MC, and current may flow from the wiring OL[j] or wiring OLB[j] to the wiring VEr[j] via the circuit MCr. i (k-1) When the second data z is "1", the circuit MC and the wiring OL[j], and the circuit MCr and the wiring OLB[j] are in a conductive state. i (k-1) When the first data w is "-1", the circuit MC and the wiring OLB[j], and the circuit MCr and the wiring OL[j] are in a conductive state. i (k-1) j (k)and the second data z i (k-1) When the product of the first data w is a positive value, a current flows from the wiring OL[j] to the wiring VE[j] via the circuit MCr, or a current flows from the wiring OL[j] to the wiring VEn[j] via the circuit MCr. i (k-1) j (k) and the second data z i (k-1) When the product of the first data w is a negative value, either a current flows from the wiring OL[j] to the wiring VEr[j] via the circuit MCr, or a current flows from the wiring OLB[j] to the wiring VE[j] via the circuit MC. i (k-1) j (k) and the second data z i (k-1) When the product is zero, no current flows from the wiring OL[j] or wiring OLB[j] to the wiring VE[j], and no current flows from the wiring OL[j] or wiring OLB[j] to the wiring VEr[j].

[0180] To take the above example as a specific example, the first data w i (k-1) j (k) is "1", and the second data z i (k-1) When the first data w is "1", for example, a current I1[i, j] having a first current value flows from the circuit MC to the wiring OL[j], and a current I2[i, j] having a second current value flows from the circuit MCr to the wiring OLB[j]. In this case, the magnitude of the second current value is, for example, zero. i (k-1) j (k) is "-1", and the second data z i (k-1) When the first data w is "1", for example, a current I1[i, j] having a second current value flows from the circuit MC to the wiring OL[j], and a current I2[i, j] having a first current value flows from the circuit MCr to the wiring OLB[j]. In this case, the magnitude of the second current value is, for example, zero. i (k-1)j (k) is "0", and the second data z i (k-1) When is "1", a current I1[i, j] having a second current value flows from the circuit MC to the wiring OL[j], and a current I2[i, j] having a second current value flows from the circuit MCr to the wiring OLB[j]. In this case, the magnitude of the second current value is, for example, zero.

[0181] Also, the first data i (k-1) j (k) is "1", and the second data z i (k-1) When the first data w is "-1", a current I1[i, j] having a first current value flows from the circuit MC to the wiring OLB[j], and a current I2[i, j] having a second current value flows from the circuit MCr to the wiring OL[j]. In this case, the magnitude of the second current value is, for example, zero. i (k-1) j (k) is "-1", and the second data z i (k-1) When the first data w is "-1", a current I1[i, j] having a second current value flows from the circuit MC to the wiring OLB[j], and a current I2[i, j] having a first current value flows from the circuit MCr to the wiring OL[j]. In this case, the magnitude of the second current value is, for example, zero. i (k-1) j (k) is "0", and the second data z i (k-1) is "-1", a current I1[i, j] having a second current value flows from the circuit MC to the wiring OLB[j], and a current I2[i, j] having a second current value flows from the circuit MCr to the wiring OL[j]. In this case, the magnitude of the second current value is, for example, zero.

[0182] Also, the second data z i (k-1)When the first data w is "0", for example, the circuit MC and the wiring OL[j] and the circuit MC and the wiring OLB[j] are in a non-conductive state. Similarly, the circuit MCr and the wiring OL[j] and the circuit MCr and the wiring OLB[j] are in a non-conductive state. Therefore, the first data w i (k-1) j (k) Whatever the value of is, no current is output from the circuit MC and the circuit MCr to the wiring OL[j] and the wiring OLB[j].

[0183] In this way, as an example, the first data w i (k-1) j (k) and the second data z i (k-1) When the product of the first data w and the second data w is a positive value, a current flows from either the circuit MC or the circuit MCr to the wiring OL[j]. i (k-1) j (k) When is a positive value, current flows from the circuit MC to the wiring OL[j], and the first data w i (k-1) j (k) When the first data w is a negative value, a current flows from the circuit MCr to the wiring OL[j]. i (k-1) j (k) and the second data z i (k-1) When the product of w and w is a negative value, a current flows from either the circuit MC or the circuit MCr to the wiring OLB[j]. i (k-1) j (k) When is a positive value, current flows from the circuit MC to the wiring OLB[j], and the first data w i (k-1) j (k)If is a negative value, a current flows from the circuit MCr to the wiring OLB[j]. Therefore, the sum of the currents output from the multiple circuits MC or circuits MCr connected to the wiring OL[j] flows through the wiring OL[j]. In other words, a current that is the sum of positive values ​​flows through the wiring OL[j]. On the other hand, the sum of the currents output from the multiple circuits MC or circuits MCr connected to the wiring OLB[j] flows through the wiring OLB[j]. In other words, a current that is the sum of negative values ​​flows through the wiring OLB[j]. As a result of the above operation, a product-sum operation can be performed by using the total current value flowing through the wiring OL[j], i.e., the sum of positive values, and the total current value flowing through the wiring OLB[j], i.e., the sum of negative values. For example, if the total current value flowing through the wiring OL[j] is greater than the total current value flowing through the wiring OLB[j], the product-sum operation result can be determined to be a positive value. If the total current value flowing through the wiring OL[j] is smaller than the total current value flowing through the wiring OLB[j], it can be determined that the result of the product-sum operation will be a negative value. If the total current value flowing through the wiring OL[j] and the total current value flowing through the wiring OLB[j] are approximately the same value, it can be determined that the result of the product-sum operation will be a zero value.

[0184] In addition, the second data z i (k-1) The same operation can be performed when the first data w is any one of two values ​​of "-1", "0", and "1", for example, when the first data w is either "-1" or "1", or when the first data w is either "0" or "1". i (k-1) j (k) The same operation can be performed when the value is any one of "-1", "0", and "1", for example, when the value is "-1" or "1", or when the value is "0" or "1".

[0185] In addition, the first data i (k-1) j (k)may take an analog value or a multi-bit (multi-valued) digital value. As a specific example, a "negative analog value" may be used instead of "-1", and a "positive analog value" may be used instead of "1". In this case, the magnitude of the current flowing from the circuit MC or the circuit MCr may also be, for example, the first data w i (k-1) j (k) It becomes an analog value according to the absolute value of the value.

[0186] Next, an example of a modification of the circuit MP[i,j] in Fig. 9A will be described. Note that, for the modification of the circuit MP[i,j], the differences from the circuit MP[i,j] in Fig. 9A will be mainly described, and a description of the parts common to the circuit MP[i,j] in Fig. 9A may be omitted.

[0187] The circuit MP[i,j] shown in FIG. 9B has a configuration in which the wiring W1L is replaced with a wiring WX1L. That is, in the circuit MP[i,j] of FIG. 9B, the wiring WX1L and the wiring WL function as wirings that supply a predetermined potential in order to switch the conductive state between the wiring OL[j] and the holding unit HC and the conductive state between the wiring OLB[j] and the holding unit HCr. Also, in the circuit MP[i,j] of FIG. 9B, the wiring X1L and the wiring X2L are used to supply the second data z input to the circuit MP[i,j]. i (k-1) It functions as wiring that provides current, voltage, etc. according to the

[0188] The circuit MP[i,j] in Fig. 9B can be applied to an arithmetic circuit having a wiring WX1L, such as the arithmetic circuit 130 shown in Fig. 13, and to an arithmetic circuit not having wirings IL and ILB, such as the arithmetic circuit 140 shown in Fig. 7. Specifically, the circuit MP[i,j] in Fig. 9B can be applied to the circuit MP[i,j] of the arithmetic circuit 150 shown in Fig. 11.

[0189] Next, an example of modifying the circuit MP[i,j] in FIG. 9A, which is different from FIG. 9B, will be described. The circuit MP[i,j] shown in FIG. 9C is a modified example of the circuit MP[i,j] in FIG. 9A. The circuit MP[i,j] in FIG. 9C has a circuit MC and a circuit MCr, similar to the circuit MP[i,j] in FIG. 9A. However, the circuit MP[i,j] in FIG. 9C is different from the circuit MP[i,j] in FIG. 9A in that the holding part HCr is not included in the circuit MCr.

[0190] Also, since the circuit MCr does not have the holding part HCr, the arithmetic circuit to which the circuit MP[i,j] in FIG. 9C is applied may not have the wiring ILB[j] for supplying the potential held in the holding part HCr. In addition, the circuit MCr may not be electrically connected to the wiring WL[i].

[0191] In the circuit MP[i,j] of FIG. 9C, the holding part HC included in the circuit MC is electrically connected to the circuit MCr. That is, the circuit MP[i,j] in FIG. 9C is configured such that the circuit MCr and the circuit MC share the holding part HC with each other. As an example, an inverted signal can be supplied from the holding part HC to the circuit MCr for the signal held in the holding part HC. Thereby, different operations can be performed by the circuit MC and the circuit MCr. Or, the internal circuit configurations of the circuit MC and the circuit MCr can be made different, and as a result, the magnitudes of the currents output by the circuit MC and the circuit MCr for the same signal held in the holding part HC can be made different. Here, the holding part HC holds the potential corresponding to the first data w i [[ID=?]] (k-1) [[ID=?]] j [[ID=?]] (k) holds the potential corresponding to the second data z i (k-1) By supplying the potential corresponding to the first data w to the wiring X1L[i] and the wiring X2L[i], the circuit MP[i,j] supplies the first data w i (k-1) j (k) and the second data z i (k-1) ]](END]to the wiring OL[j] and the wiring OLB[j], and can output a current corresponding to the product of the first data w

[0192] 9C to which the circuit MP is applied can be changed to the circuit configuration of the arithmetic circuit 160 shown in Fig. 12. The arithmetic circuit 160 has a configuration in which the wirings ILB[1] to ILB[m] are removed from the arithmetic circuit 110 in Fig. 2.

[0193] The circuit MP[i,j] shown in Fig. 9D is a modified example of the circuit MP[i,j] of Fig. 9A, and specifically, is a configuration example of the circuit MP[i,j] that can be applied to the arithmetic circuit 160 of Fig. 12. The circuit MP[i,j] of Fig. 9D includes a circuit MC and a circuit MCr, similar to the circuit MP[i,j] of Fig. 9A. However, the circuit MP[i,j] of Fig. 9D and the circuit MP[i,j] of Fig. 9A have different configurations of electrically connected wiring.

[0194] The wiring W1L[i] and wiring W2L[i] shown in Fig. 9D correspond to the wiring WLS[i] in Fig. 12. The wiring W1L[i] is electrically connected to the holding unit HC, and the wiring W2L[i] is electrically connected to the holding unit HCr.

[0195] Moreover, the wiring IL[j] is electrically connected to the holding portion HC and the holding portion HCr.

[0196] In the circuit MP[i,j] of Fig. 9D, when the holding unit HC and the holding unit HCr hold different information (for example, voltage, resistance, current, etc.), it is preferable to hold the information in the holding unit HC and the holding unit HCr sequentially rather than simultaneously. For example, when the first data w i (k-1) j (k)Consider a case where the first information can be expressed by storing the first information in the storage unit HC and the second information in the storage unit HCr. First, a predetermined potential is applied to each of the wires W1L[i] and W2L[i], thereby establishing a conductive state between the storage unit HC and the wire IL[j] and establishing a non-conductive state between the storage unit HCr and the wire IL[j]. Next, the first information can be provided to the storage unit HC by supplying a current, voltage, etc. corresponding to the first information to the wire IL[j]. After that, a predetermined potential is applied to each of the wires W1L[i] and W2L[i], thereby establishing a non-conductive state between the storage unit HC and the wire IL[j] and establishing a conductive state between the storage unit HCr and the wire IL[j]. Then, a current, voltage, etc. corresponding to the second information is supplied to the wire IL[j], thereby providing the second information to the storage unit HCr. As a result, the circuit MP[i,j] stores w as the first data. i (k-1) j (k) can be set.

[0197] In addition, when the holding unit HC and the holding unit HCr hold substantially the same information (for example, voltage, resistance value, current, etc.) (the first data w i (k-1) j (k) is set by storing approximately equal information in the holding unit HC and the holding unit HCr, respectively), a predetermined potential is applied to each of the wiring W1L[i] and the wiring W2L[i] so that a state of conduction is established between the holding unit HC and the wiring IL[j] and a state of conduction is established between the holding unit HCr and the wiring IL[j], and then a current, voltage, etc. according to the information is supplied from the wiring IL[j] to the holding unit HC and the holding unit HCr.

[0198] The circuit MP[i,j] in FIG. 9D stores the first data w in the holding unit HC and the holding unit HCr. i (k-1) j (k) and holds the potential according to the second data z i (k-1)9A , a potential corresponding to the first data w is supplied to the wiring OL[j] and the wiring OLB[j]. i (k-1) j (k) and the second data z i (k-1) It is possible to output a current according to the product of

[0199] The circuit MP[i,j] shown in Fig. 9E is a modified example of the circuit MP[i,j] of Fig. 9D. The circuit MP[i,j] of Fig. 9E includes a circuit MC and a circuit MCr, similar to the circuit MP[i,j] of Fig. 9D. However, the circuit MP[i,j] of Fig. 9E and the circuit MP[i,j] of Fig. 9D differ in the configuration of the electrically connected wiring.

[0200] Specifically, the circuit MP of Figure 9E is configured by adding wiring ILB[j] to the circuit MP of Figure 9D, and replacing the wiring W1L[i] and wiring W2L[i] electrically connected to the circuit MP of Figure 9D with wiring WL[i].

[0201] In the circuit MP of Fig. 9E, the wiring IL[j] is electrically connected to the holding unit HC, and the wiring ILB[j] is electrically connected to the holding unit HCr. That is, in the circuit MP of Fig. 9D, the wiring IL[j] functions as a wiring that supplies a current, a voltage, etc. corresponding to information (e.g., a voltage, a resistance value, a current, etc.) to each of the holding units HC and HCr, but in the circuit MP of Fig. 9E, the wiring IL[j] functions as a wiring that supplies a current, a voltage, etc. corresponding to the information to the holding unit HC, and the wiring ILB[j] functions as a wiring that supplies a current, a voltage, etc. corresponding to the information to the holding unit HC.

[0202] Furthermore, in the circuit MP of FIG. 9E, the wiring IL[j] and wiring ILB[j] are electrically connected to the holding unit HC and the holding unit HCr, respectively. This allows current, voltage, etc., corresponding to information (e.g., voltage, resistance, current, etc.) to be simultaneously supplied to each of the holding units HC and HCr. Therefore, the holding unit HC and the wiring IL[j] can be switched between conductive and non-conductive states, and the holding unit HCr and the wiring ILB[j] can be switched between conductive and non-conductive states simultaneously. In the circuit MP of FIG. 9D, wiring W1L is illustrated as the wiring that controls the switching between conductive and non-conductive states between the holding unit HC and the wiring IL[j], and wiring W2L is illustrated as the wiring that controls the switching between conductive and non-conductive states between the holding unit HCr and the wiring ILB[j]. However, in the circuit MP of FIG. 9E, wiring W1L and wiring W2L are illustrated as a combined wiring, WL[i].

[0203] The circuit MP in FIG. 9E can be applied to, for example, the arithmetic circuit 110 in FIG. 2 and the arithmetic circuit 120 in FIG.

[0204] The circuit MP[i,j] shown in Figure 9F is a modified example of the circuit MP[i,j] of Figure 9A. Like the circuit MP[i,j] of Figure 9A, the circuit MP[i,j] of Figure 9F includes a circuit MC and a circuit MCr. However, the circuit MP[i,j] of Figure 9F differs from the circuit MP[i,j] of Figure 9A in that the circuit MC is not electrically connected to the wiring OLB[j] and the circuit MCr is not electrically connected to the wiring OL[j].

[0205] The wiring WL[i] shown in Fig. 9F is electrically connected to the holding unit HC and the holding unit HCr, and the wiring XL[i] shown in Fig. 9F is electrically connected to the circuit MC and the circuit MCr.

[0206] As described below, in the circuit MP[i,j] in Fig. 9F, the circuit MC is not electrically connected to the wiring OLB[j], and the circuit MCr is not electrically connected to the wiring OL[j]. In other words, unlike the circuits MP[i,j] in Fig. 9A to 9E, the circuit MP[i,j] in Fig. 9F is configured such that the current output from the circuit MC does not flow through the wiring OLB[j], and the current output from the circuit MCr does not flow through the wiring OL[j].

[0207] Therefore, the circuit MP[i,j] of FIG. 9F receives the second data z i (k-1) is a binary value of "0" or "1", it is preferable to apply it to the arithmetic circuit. For example, i (k-1) is "1", the circuit MP brings the circuit MC and the wiring OL[j] into a conductive state, and brings the circuit MCr and the wiring OLB[j] into a conductive state. i (k-1) When is "0", the circuit MP prevents the currents output by the circuits MC and MCr from flowing to either the wiring OL[j] or the wiring OLB[j], thereby bringing the circuit MC and the wiring OL[j] and the circuit MC and the wiring OLB[j] into a non-conductive state, and brings the circuit MCr and the wiring OL[j] and the circuit MCr and the wiring OLB[j] into a non-conductive state.

[0208] The circuit MP[i,j] of FIG. 9F is applied to the arithmetic circuit 110 to obtain, for example, the first data w i (k-1) j (k) takes one of the three values ​​"-1", "0", or "1", and the second data z i (k-1) The first data w can be calculated when it takes two values, "0" and "1". i (k-1) j (k) It can also be operated when the first data w is any of two values ​​of "-1", "0", and "1", for example, when it is two values ​​of "-1" and "1", or when it is two values ​​of "0" and "1". i(k-1) j (k) may take an analog value or a multi-bit (multi-valued) digital value. As a specific example, a "negative analog value" may be used instead of "-1", and a "positive analog value" may be used instead of "1". In this case, the magnitude of the current flowing from the circuit MC or the circuit MCr may also be, for example, the first data w i (k-1) j (k) It becomes an analog value according to the absolute value of the value.

[0209] 9A, the circuit MP[i,j] shown in FIG. 10 has the first data w i (k-1) j (k) and the second data z i (k-1) 10 is a circuit capable of outputting a current according to the product of [i, j] and [i, j]. The circuit MP[i, j] in FIG. 10 can be applied to, for example, the arithmetic circuit 110 in FIG.

[0210] The circuit MP[i,j] in FIG. 10 includes a circuit MC, a circuit MCr, and a transistor MZ.

[0211] A first terminal of the transistor MZ is electrically connected to a first terminal of the circuit MC and a first terminal of the circuit MCr. A second terminal of the transistor MZ is electrically connected to the wiring VL. A gate of the transistor MZ is electrically connected to the wiring XL[i].

[0212] For example, the wiring VL functions as a wiring that applies a constant voltage. The constant voltage is preferably determined by the configuration of the circuit MP[i,j], the arithmetic circuit 110, etc. The constant voltage may be, for example, a high-level potential VDD, a low-level potential VSS, or a ground potential.

[0213] Moreover, the wiring WL[i] shown in Fig. 10 corresponds to the wiring WLS[i] in the arithmetic circuit 110 in Fig. 2. The wiring WL[i] is electrically connected to the holding unit HC and the holding unit HCr.

[0214] The wiring OL[j] is electrically connected to the second terminal of the circuit MC. The wiring OLB[j] is electrically connected to the second terminal of the circuit MCr.

[0215] Moreover, the wiring IL[j] is electrically connected to the holding unit HC, and the wiring ILB[j] is electrically connected to the holding unit HCr.

[0216] In the circuit MP[i,j] of Figure 10, for the operation when the holding unit HC and the holding unit HCr each hold a potential corresponding to the first data, please refer to the explanation of the operation of holding a potential corresponding to the first data in the circuit MP[i,j] of Figure 9A.

[0217] In the circuit MP[i,j] of Fig. 10, the circuit MC has a function of flowing a current corresponding to the potential held in the holding unit HC between the first and second terminals of the circuit MC when a constant voltage given by the wiring VL is supplied to the first terminal of the circuit MC. Also, the circuit MCr has a function of flowing a current corresponding to the potential held in the holding unit HCr between the first and second terminals of the circuit MCr when a constant voltage given by the wiring VL is supplied to the first terminal of the circuit MC. In other words, when the holding unit HC and the holding unit HCr of the circuit MP[i,j] are respectively supplied with the first data w i (k-1) j (k) By maintaining a potential according to the voltage VL, it is possible to determine the amount of current flowing between the first and second terminals of the circuit MC and the amount of current flowing between the first and second terminals of the circuit MCr. Note that when the constant voltage provided by the wiring VL is not supplied to the first terminal of the circuit MC (circuit MCr), the circuit MC (circuit MCr) may, for example, not allow current to flow between the first and second terminals of the circuit MC (circuit MCr).

[0218] For example, if the first data w of "1" is stored in each of the storage units HC and HCr, i (k-1) j (k) When a potential according to is held, a constant voltage is applied to the circuit MC by the wiring VL, and the circuit MC passes a predetermined current between the first and second terminals of the circuit MC. Therefore, a current flows between the circuit MC and the wiring OL. Note that at this time, the circuit MCr does not pass a current between the first and second terminals of the circuit MCr. Therefore, no current flows between the circuit MCr and the wiring OLB. Also, for example, when the first data w of "-1" is stored in each of the holding units HC and HCr, i (k-1) j (k) When a potential according to is held, a constant voltage given by the wiring VL is given to the circuit MC, and the circuit MCr passes a predetermined current between the first and second terminals of the circuit MCr. Therefore, a current flows between the circuit MCr and the wiring OLB. Note that at this time, the circuit MC does not pass a current between the first and second terminals of the circuit MC. Therefore, no current flows between the circuit MC and the wiring OL. Also, for example, when the first data w of "0" is stored in each of the holding units HC and HCr, i (k-1) j (k) is held, regardless of whether the constant voltage of the wiring VL is applied to the circuits MC and MCr, the circuit MC does not pass a current between its first and second terminals, and the circuit MCr does not pass a current between its first and second terminals. In other words, no current flows between the circuit MC and the wiring OL, and no current flows between the circuit MCr and the wiring OLB.

[0219] In the circuit MP[i,j] of FIG. 10, the first data w i (k-1) j (k)For a specific example of the potential corresponding to the potential, please refer to the description of the circuit MP[i,j] in Fig. 9A. In the circuit MP[i,j] in Fig. 10, the holding units HC and HCr may have the function of holding information such as a current or a resistance value instead of a potential, similar to the circuit MP[i,j] in Fig. 9A, and the circuits MC and MCr may have the function of flowing a current corresponding to the information.

[0220] The wiring XL[i] shown in FIG. 10 corresponds to the wiring XLS[i] in the arithmetic circuit 110 in FIG. 2. Note that the second data z i (k-1) For example, the potential and current of the wiring XL[i] are determined. Therefore, the gate of the transistor MZ is connected to the second data z i (k-1) A potential according to the voltage is input.

[0221] For example, the second data z i (k-1) Consider the case where the second data z takes either of the two values ​​"0" or "1". i (k-1) When the second data z is "1", a high-level potential is applied to the wiring XL[i]. At this time, the transistor MZ is turned on, so the circuit MP brings the wiring VL and the first terminal of the circuit MC into a conductive state, and brings the wiring VL and the first terminal of the circuit MCr into a conductive state. In other words, i (k-1) When the second data z i (k-1) When the second data z is "0", a low-level potential is applied to the wiring XL[i]. At this time, the circuit MP puts the circuit MC and the wiring OLB[j] in a non-conductive state, and puts the circuit MCr and the wiring OL[j] in a non-conductive state. That is, i (k-1) When is "0", the constant voltage is not applied to the circuit MC and the circuit MCr from the line VL.

[0222] Here, for example, the first data w i (k-1) j (k) is "1", and the second data z i (k-1) is "1", a current flows between the circuit MC and the wiring OL, and a current does not flow between the circuit MCr and the wiring OLB. i (k-1) j (k) is "-1", and the second data z i (k-1) is "1", no current flows between the circuit MC and the wiring OL, and a current flows between the circuit MCr and the wiring OLB. i (k-1) j (k) is "0", and the second data z i (k-1) is "1", no current flows between the circuit MC and the wiring OL, and between the circuit MCr and the wiring OLB. i (k-1) is "0", the first data w i (k-1) j (k) is "-1", "0", or "1", no current flows between the circuit MC and the wiring OL, and between the circuit MCr and the wiring OLB.

[0223] That is, the circuit MP[i,j] in FIG. 10, like the circuit MP[i,j] in FIG. 9F, uses, for example, the first data w i (k-1) j (k) takes one of the three values ​​"-1", "0", or "1", and the second data z i (k-1) 9F, the circuit MP[i,j] in FIG. 10 can perform calculations when the first data w i (k-1) j (k)It can also be operated when the first data w is any of two values ​​of "-1", "0", and "1", for example, when it is two values ​​of "-1" and "1", or when it is two values ​​of "0" and "1". i (k-1) j (k) may take an analog value or a multi-bit (multi-valued) digital value. As a specific example, a "negative analog value" may be used instead of "-1", and a "positive analog value" may be used instead of "1". In this case, the magnitude of the current flowing from the circuit MC or the circuit MCr may also be, for example, the first data w i (k-1) j (k) It becomes an analog value according to the absolute value of the value.

[0224] <Example of operation of an arithmetic circuit> Next, an example of the operation of the arithmetic circuit 140 in Fig. 7 will be described. In the description of this example of the operation, the arithmetic circuit 140 shown in Fig. 13 will be used as an example.

[0225] The arithmetic circuit 140 in Fig. 13 is illustrated by focusing on the circuit located in the j-th column of the arithmetic circuit 140 in Fig. 7. In other words, the arithmetic circuit 140 in Fig. 13 is similar to the circuit located in the j-th column of the neuron N in the neural network 100 shown in Fig. 1A. j (k) neuron N1 (k-1) Neuron N m (k-1) Signal z1 from (k-1) ~z m (k-1) and weighting factor w1 (k-1) j (k) Or even w m (k-1) j (k) 13 corresponds to a circuit that performs a product-sum operation of and an activation function operation using the result of the product-sum operation. Furthermore, the circuit MP included in the array unit ALP of the arithmetic circuit 110 in FIG. 13 is assumed to be the circuit MP of FIG. 9B.

[0226] First, in the arithmetic circuit 140, the first data w1 (k-1) j (k) Or even w m (k-1) j (k) The first data w is set. i (k-1) j (k) As a method of setting the first data, a predetermined potential is input to the wirings WLS[1] to WLS[m] in order by the circuit WLD to sequentially select the circuits MP[1,j] to MP[m,j], and a potential, current, or the like according to the first data is supplied from the circuit ILD to the holding units HC and HCr of the circuits MC and MCr included in the selected circuit MP via the switching circuit TW[j] and the wirings OL[j] and OLB[j]. After the supply of the potential, current, or the like, the circuit WLD deselects each of the circuits MP[1,j] to MP[m,j], thereby storing the first data w1 in the holding units HC and HCr of the circuits MC and MCr included in each of the circuits MP[1,j] to MP[m,j]. (k-1) j (k) Or even w m (k-1) j (k) As an example, the potential, current, etc. according to the first data w1 (k-1) j (k) Or even w m (k-1) j (k) When each of the first data w1 takes a positive value, a value corresponding to the positive value is input to the holding unit HC, and a value corresponding to zero is input to the holding unit HCr. (k-1) j (k) Or even w m (k-1) j (k) When each of the above takes a negative value, a value equivalent to zero is input to the holding unit HC, and a value corresponding to the absolute value of the negative value is input to the holding unit HCr.

[0227] Next, the circuit XLD applies second data z1 (k-1) ~z m (k-1) As a specific example, the second data z1 is supplied to the wiring X1L[i] and the wiring X2L[i]. (k-1) is supplied. The wiring X1L[i] and the wiring X2L[i] correspond to the wiring XLS[i] of the arithmetic circuit 140 shown in FIG.

[0228] Second data z1 input to each of the circuits MP[1,j] to MP[m,j] (k-1) ~z m (k-1) The conduction state between the circuits MC and MCr included in the circuits MP[i,j] to MP[m,j] and the wirings OL[j] and OLB[j] is determined according to the second data z i (k-1) Depending on the second data z1, the state may be one of the following: "the circuit MC and the wiring OL[j] are electrically connected, and the circuit MCr and the wiring OLB[j] are electrically connected," "the circuit MC and the wiring OLB[j] are electrically connected, and the circuit MCr and the wiring OL[j] are electrically connected," and "the circuit MC and the circuit MCr are electrically disconnected from the wiring OL[j] and the wiring OLB[j], respectively." (k-1) When the second data z1 is a positive value, a value that can bring the circuit MC and the wiring OL[j] into a conductive state and can bring the circuit MCr and the wiring OLB[j] into a conductive state is input to the wiring X1L[1]. Then, a value that can bring the circuit MC and the wiring OLB[j] into a non-conductive state and can bring the circuit MCr and the wiring OL[j] into a non-conductive state is input to the wiring X2L[1]. Then, the second data z1 (k-1)When the second data z1 is a negative value, a value that can bring the circuit MC and the wiring OLB[j] into a conductive state and can bring the circuit MCr and the wiring OL[j] into a conductive state is input to the wiring X1L[1]. Then, a value that can bring the circuit MC and the wiring OL[j] into a non-conductive state and can bring the circuit MCr and the wiring OLB[j] into a non-conductive state is input to the wiring X2L[1]. Then, the second data z1 (k-1) When the value of 0 is taken for the wiring X1L[1], a value that can bring the circuit MC and the wiring OLB[j] into a non-conductive state and can bring the circuit MCr and the wiring OL[j] into a non-conductive state is input to the wiring X1L[1]. Then, a value that can bring the circuit MC and the wiring OL[j] into a non-conductive state and can bring the circuit MCr and the wiring OLB[j] into a non-conductive state is input to the wiring X2L[1].

[0229] The second data z input to the circuit MP[i,j] i (k-1) The conduction state or non-conduction state between the circuit MC and the circuit MCr included in the circuit MP[i,j] and the wiring OL[j] and the wiring OLB[j] is determined in accordance with the first data w set in the circuit MP[i,j], and current is input and output between the circuit MC and the wiring OL[j] and the wiring OLB[j]. i (k-1) j (k) and / or second data z i (k-1) It is determined depending on.

[0230] For example, in the circuit MP[i,j], the current flowing from the wiring OL[j] to the circuit MC or the circuit MCr is I[i,j], and the current flowing from the wiring OLB[j] to the circuit MC or the circuit MCr is I B [i,j]. Then, the current flowing from the circuit ACTF[j] to the wiring OL[j] is I out [j], and the current flowing from wiring OLB[j] to circuit ACTF[j] is I Bout If [j], then I out [j] and I Bout[j] can be expressed by the following formula:

[0231]

number

[0232] In the circuit MP[i,j], as an example, the first data w i (k-1) j (k) When is "+1", the circuit MC outputs I(+1) and the circuit MCr outputs I(-1), and the first data w i (k-1) j (k) When is "-1", the circuit MC outputs I(-1) and the circuit MCr outputs I(+1), and the first data w i (k-1) j (k) When is "0", the circuit MC emits I(-1) and the circuit MCr emits I(-1).

[0233] Furthermore, the circuit MP[i,j] receives the second data z i (k-1) is "+1", the state is "conduction between the circuit MC and the wiring OL[j], conduction between the circuit MCr and the wiring OLB[j], non-conduction between the circuit MC and the wiring OLB[j], and non-conduction between the circuit MCr and the wiring OL[j]" and the second data z i (k-1) is "-1", the state is "conduction between the circuit MC and the wiring OLB[j], conduction between the circuit MCr and the wiring OL[j], non-conduction between the circuit MC and the wiring OL[j], and non-conduction between the circuit MCr and the wiring OLB[j]" and the second data z i (k-1) When is "0", the state is assumed as follows: "there is no conduction between the circuit MC and the wiring OL[j], and between the circuit MC and the wiring OLB[j], and there is no conduction between the circuit MCr and the wiring OL[j], and between the circuit MCr and the wiring OLB[j]."

[0234] At this time, in the circuit MP[i,j], the current I[i,j] flows from the wiring OL[j] to the circuit MC or the circuit MCr, and the current I B [i,j] is as shown in the table below. In some cases, the circuit MP[i,j] may be configured so that the current amount of I(-1) is 0. The current I[i,j] may be a current flowing from the circuit MC or the circuit MCr to the wiring OL[j]. Similarly, the current I B [i, j] may be a current flowing from the circuit MC or the circuit MCr to the wiring OLB[j].

[0235] [Table 1]

[0236] Then, I flowing from each of the wiring OL[j] and wiring OLB[j] out [j] and I Bout By inputting each of [j] to the circuit ACTF[j], the circuit ACTF[j] can be configured as follows, for example: out [j] and I Bout [j]. The circuit ACTF[j], for example, selects a neuron N j (k) is the signal z sent to the (k+1)th layer neuron. j (k) Output.

[0237] As an example, the arithmetic circuit 140 of FIG. j (k) neuron N1 (k-1) Neuron N m (k-1) Signal z1 from (k-1) ~z m (k-1) and weighting factor w1 (k-1) j (k) Or even w m (k-1) j (k)7. In other words, the operation circuit 140 of FIG. 7 can perform a multiplication and accumulation operation of the neuron N1 and an activation function calculation using the result of the multiplication and accumulation operation. Furthermore, by providing n rows of circuits MP in the array part ALP of the operation circuit of FIG. 13, a circuit equivalent to the operation circuit 140 of FIG. 7 can be configured. (k) Neuron N n (k) In each of the above, the product-sum operation and the calculation of the activation function using the result of the product-sum operation can be performed simultaneously.

[0238] <<Example of changing circuits included in the arithmetic circuit>> Each of the above-described arithmetic circuits 110, 120, 130, 140, 150, and 160 can be changed to a circuit that performs the operation of equation (1.3) instead of equation (1.2). Equation (1.3) corresponds to an operation in which a bias is applied to the product-sum result of equation (1.2). Therefore, each of the arithmetic circuits 110, 120, 130, 140, 150, and 160 may be provided with a circuit that applies a bias value to the wiring OL and the wiring OLB.

[0239] The arithmetic circuit 170 shown in FIG. 14 has a circuit configuration in which circuits BS[1] to BS[n] are added to the array section ALP of the arithmetic circuit 150 in FIG.

[0240] The circuit BS[j] is electrically connected to the wiring OL[j], the wiring OLB[j], the wiring WLBS, and the wiring WXBS.

[0241] The wiring WLBS functions as a wiring for supplying a signal for turning on or off the write switching elements included in the circuits BS[1] to BS[n], similar to the wirings WLS[1] to WLS[m] of the arithmetic circuit 110 in Fig. 2 and the wirings WL[1] to WL[m] of the arithmetic circuit 140 in Fig. 7. Therefore, the wiring WLBS is electrically connected to the circuit WLD, so that the signal can be supplied from the circuit WLD to the wiring WLBS.

[0242] The wire WXBS is connected to the neuron N in the same way as the wires XLS[1] to XLS[m] of the arithmetic circuit 110 in FIG. i (k-1) The second data z output from i (k-1) The wiring WXBS functions as a wiring that supplies information (for example, a potential, a current value, etc.) corresponding to the wiring WXBS to the circuits BS[1] to BS[n]. Therefore, when the wiring WXBS is electrically connected to the circuit XLD, the information can be supplied from the circuit XLD to the wiring WXBS.

[0243] The wiring WXBS may also serve as a selection signal line for writing data to the circuits BS[1] to BS[n], similar to the wirings WX1L[1] to WX1L[n] of the arithmetic circuit 140 in Fig. 7. In the arithmetic circuit 170 in Fig. 14, the wiring WXBS is electrically connected to the circuit WLD. In this configuration, the circuit WLD can supply signals to the wirings WLBS and WXBS for turning on or off the write switching elements included in the circuits BS[1] to BS[n].

[0244] In the jth column of the array portion ALP of the arithmetic circuit 170, the amount of current flowing from the circuits MP[1,j] to MP[m,j] to the wiring OL[j] or the wiring OLB[j] can be expressed by the formula (1.5) and the formula (1.6), respectively. In addition, since each of the wiring OL[j] and the wiring OLB[j] is electrically connected to the circuit BS[j], the current flowing from the circuit BS[j] to the wiring OL[j] can be expressed by I BIAS [j], the current flowing from circuit BS[j] to wiring OLB[j] is I BIASB When [j] is used, equations (1.5) and (1.6) can be rewritten as the equations below.

[0245]

number

[0246] This allows us to calculate the bias in equation (1.3) by using I out [j] and I Bout [j] can be generated. Also, I out [j] and I Bout [j] is input to the circuit ACTF[j], which biases the neuron N j (k) Output signal z from j (k) can be generated.

[0247] 14, the circuits BS[1] to BS[n] are provided in one row in the array portion ALP, but one embodiment of the present invention is not limited to this. For example, the circuits BS[1] to BS[n] may be provided in two or more rows in the array portion ALP.

[0248] As an example, some or all of the transistors included in each of the array portion ALP, the circuit ILD, the circuit WLD, the circuit XLD, the circuit AFP, the circuit MP, the switching circuit TW, and the like are preferably OS transistors. For example, in the case of a transistor for which a low off-state current is desired, a specific example of a transistor having a function of retaining charge accumulated in a capacitor or the like is preferably an OS transistor. In particular, when an OS transistor is used as the transistor, the OS transistor more preferably has the structure of the transistor described in Embodiment 4. The metal oxide included in the channel formation region of the OS transistor can be, for example, one or more materials selected from indium, an element M (the element M is aluminum, gallium, yttrium, or tin), and zinc. In particular, a metal oxide made of indium, gallium, or zinc is a semiconductor that has a wide band gap and is intrinsic (also referred to as I-type) or substantially intrinsic, and the carrier concentration of the metal oxide is 1×10 18 cm -3 Preferably, it is 1×10 or less. 17 cm -3 More preferably, it is less than 1×1016 cm -3 More preferably, it is less than 1×10 13 cm -3 More preferably, it is less than 1×10 12 cm -3 The off-state current of an OS transistor including the metal oxide in a channel formation region is preferably less than 10 aA (1×10 -17 A) or less, preferably 1 aA (1 × 10 -18 A) or less, and more preferably 10 zA (1 × 10 -20 A) or less, more preferably 1 zA (1 × 10 -21 A) or less, more preferably 100 yA (1 × 10 -22 A) or less. Furthermore, since the carrier concentration of the metal oxide in the OS transistor is low, the off-state current of the OS transistor remains low even when the temperature of the OS transistor changes. For example, even when the temperature of the OS transistor is 150° C., the off-state current can be 100 zA per 1 μm of channel width.

[0249] However, one embodiment of the present invention is not limited to the above. Transistors included in the array portion ALP, the circuit ILD, the circuit WLD, the circuit XLD, the circuit AFP, the circuit MP, the switching circuit TW, and the like do not necessarily have to be OS transistors. As an example, transistors other than OS transistors may be transistors containing silicon in their channel formation regions (hereinafter referred to as Si transistors). Furthermore, silicon may be, for example, single crystal silicon, hydrogenated amorphous silicon, microcrystalline silicon, or polycrystalline silicon. Furthermore, transistors other than OS transistors and Si transistors may include, for example, transistors with an active layer made of a semiconductor such as Ge, transistors with an active layer made of a compound semiconductor such as ZnSe, CdS, GaAs, InP, GaN, or SiGe, transistors with an active layer made of a carbon nanotube, and transistors with an active layer made of an organic semiconductor.

[0250] Note that, among the metal oxides in the semiconductor layers of OS transistors, n-type semiconductors can be fabricated using metal oxides containing indium (e.g., In oxide) or zinc (e.g., Zn oxide), but it may be difficult to fabricate p-type semiconductors due to mobility and reliability considerations. Therefore, the arithmetic circuits 110, 120, 130, 140, 150, 160, and 170 may be configured such that OS transistors are used as n-channel transistors in the array units ALP, ILD, WLD, XLD, AFP, and MP, and Si transistors are used as p-channel transistors.

[0251] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification.

[0252] (Embodiment 2) In this embodiment mode, a specific configuration example of the circuit MP described in Embodiment Mode 1 will be described.

[0253] In the first embodiment, the symbols of the circuits MP are accompanied by notations such as [1,1], [i,j], [m,n], etc., indicating their positions within the array section ALP. However, in the present embodiment, unless otherwise specified, notations such as [1,1], [i,j], [m,n], etc. are omitted from the symbols of the circuits MP.

[0254] <Configuration example 1> First, an example of a circuit configuration applicable to the circuit MP of Fig. 9B will be described. The circuit MP shown in Fig. 15A is an example of the configuration of the circuit MP of Fig. 9B, and the circuit MC included in the circuit MP of Fig. 15A includes, for example, transistors M1 to M4 and a capacitor C1. Note that, for example, a holding unit HC is configured by the transistor M2 and the capacitor C1.

[0255] 9B, the circuit MCr has a circuit configuration similar to that of the circuit MC, and therefore, the circuit elements of the circuit MCr are designated by the letter "r" to distinguish them from the circuit elements of the circuit MC.

[0256] The transistors M1 to M4 shown in FIG. 15A are, for example, n-channel transistors with a multi-gate structure having gates above and below the channel, and each of the transistors M1 to M4 has a first gate and a second gate. In particular, for example, it is preferable that the sizes of the transistors M3 and M4 are equal. For convenience, the present specification and the like distinguishes between the first gate (sometimes referred to as a front gate) and the second gate (sometimes referred to as a back gate), but the first gate and the second gate can be interchanged. Therefore, in the present specification and the like, the term "gate" can be interchanged with the term "back gate." Similarly, the term "back gate" can be interchanged with the term "gate." Specifically, a connection configuration in which "the gate is electrically connected to a first wiring, and the back gate is electrically connected to a second wiring" can be replaced with a connection configuration in which "the back gate is electrically connected to the first wiring, and the gate is electrically connected to the second wiring." For example, as shown in FIG. 15B, the back gate of the transistor M1 may be electrically connected to the first terminal of the capacitor C1 and the first terminal of the transistor M2.

[0257] Furthermore, the semiconductor device of one embodiment of the present invention does not depend on the connection configuration of the back gate of the transistor. Although the back gates of the transistors M1 to M4 in FIG. 15A are illustrated, the connection configuration of the back gates is not illustrated. However, the electrical connection destination of the back gates can be determined at the design stage. For example, in a transistor having a back gate, the gate and the back gate may be electrically connected to increase the on-state current of the transistor. That is, for example, the gate and the back gate of the transistor M2 may be electrically connected. Furthermore, in a transistor having a back gate, for example, a wiring electrically connected to an external circuit or the like may be provided so that a potential can be applied to the back gate of the transistor from the external circuit or the like to change the threshold voltage of the transistor or reduce the off-state current of the transistor. Note that this also applies to transistors described elsewhere in the specification or illustrated in other drawings, not just FIG. 15A.

[0258] Furthermore, the semiconductor device of one embodiment of the present invention does not depend on the structure of the transistor included in the semiconductor device. For example, the transistors M1 to M4 illustrated in FIG. 15A may have a structure without a back gate, that is, a single-gate structure, as illustrated in FIG. 15C. Alternatively, some of the transistors may have a back gate, and other transistors may not have a back gate. This applies not only to the circuit diagram illustrated in FIG. 15A but also to transistors described elsewhere in the specification or illustrated in other drawings.

[0259] Furthermore, in this specification and the like, transistors with various structures can be used as transistors. Therefore, the type of transistor to be used is not limited. Examples of transistors include transistors having single crystal silicon, and transistors having non-single crystal semiconductor films typified by amorphous silicon, polycrystalline silicon, and microcrystalline (also referred to as microcrystal, nanocrystal, or semi-amorphous) silicon. Alternatively, thin film transistors (TFTs) formed by thinning such semiconductors can be used. The use of TFTs offers various advantages. For example, TFTs can be manufactured at lower temperatures than single crystal silicon, thereby reducing manufacturing costs and increasing the size of the manufacturing equipment. The use of larger manufacturing equipment allows for manufacturing on a large substrate. Therefore, a large number of display devices can be manufactured simultaneously, resulting in low manufacturing costs. Alternatively, the low manufacturing temperature allows for the use of a substrate with poor heat resistance. Therefore, transistors can be manufactured on a light-transmitting substrate. Alternatively, light transmission through a display element can be controlled using a transistor on a light-transmitting substrate. Alternatively, the thin film thickness of the transistor allows light to pass through a portion of the film forming the transistor. Therefore, the aperture ratio can be improved.

[0260] Examples of transistors that can be used include transistors containing compound semiconductors (e.g., SiGe, GaAs, etc.) or oxide semiconductors (e.g., Zn-O, In-Ga-Zn-O, In-Zn-O, In-Sn-O (ITO), Sn-O, Ti-O, Al-Zn-Sn-O (AZTO), In-Sn-Zn-O, etc.). Alternatively, thin-film transistors formed by thinning these compound semiconductors or these oxide semiconductors can be used. This allows the manufacturing temperature to be lowered, making it possible to manufacture transistors at room temperature, for example. As a result, transistors can be formed directly on substrates with low heat resistance, such as plastic substrates or film substrates. These compound semiconductors or oxide semiconductors can be used not only for the channel portion of transistors but also for other applications. For example, these compound semiconductors or oxide semiconductors can be used as wiring, resistors, pixel electrodes, or light-transmitting electrodes. These can be deposited or formed simultaneously with transistors, thereby reducing costs.

[0261] As an example of a transistor, a transistor formed by an inkjet method or a printing method can be used. These methods allow manufacturing at room temperature, in a low vacuum, or on a large substrate. Therefore, manufacturing can be performed without using a mask (reticle), and the layout of the transistor can be easily changed. Furthermore, manufacturing can be performed without using a resist, which reduces material costs and the number of steps. Furthermore, since a film can be applied only to a necessary portion, materials are not wasted and costs can be reduced compared to a manufacturing method in which a film is formed on the entire surface and then etched.

[0262] As an example of a transistor, a transistor having an organic semiconductor or a carbon nanotube can be used. This allows a transistor to be formed on a flexible substrate. A device using a transistor having an organic semiconductor or a carbon nanotube can be made resistant to impacts.

[0263] It should be noted that various other structures of transistors can be used. For example, MOS transistors, junction transistors, bipolar transistors, etc. can be used as transistors. By using MOS transistors as transistors, the size of the transistors can be reduced. Therefore, a large number of transistors can be mounted. By using bipolar transistors as transistors, a large current can be passed. Therefore, the circuit can operate at high speed. It should be noted that MOS transistors and bipolar transistors can be mixed and formed on a single substrate. This can achieve low power consumption, miniaturization, high-speed operation, etc.

[0264] As an example of a transistor, a transistor with a structure in which gate electrodes are arranged above and below the active layer can be applied. By adopting a structure in which gate electrodes are arranged above and below the active layer, a circuit configuration is created in which multiple transistors are connected in parallel. This increases the channel formation region, making it possible to increase the current value. Alternatively, by adopting a structure in which gate electrodes are arranged above and below the active layer, it becomes easier to create a depletion layer, making it possible to improve the S value.

[0265] Examples of the transistor include a transistor having a structure in which a gate electrode is disposed above an active layer, a structure in which a gate electrode is disposed below an active layer, a staggered structure, an inverted staggered structure, a structure in which a channel region is divided into multiple regions, a structure in which active layers are connected in parallel, or a structure in which active layers are connected in series. Alternatively, the transistor may have various configurations, such as a planar type, a FIN type (fin type), a TRI-GATE type, a top gate type, a bottom gate type, and a double gate type (gates are disposed above and below the channel).

[0266] As an example of a transistor, a transistor having a structure in which a source electrode or a drain electrode overlaps with an active layer (or a part thereof) can be used. By adopting a structure in which a source electrode or a drain electrode overlaps with an active layer (or a part thereof), it is possible to prevent unstable operation due to charge accumulation in a part of the active layer.

[0267] As an example of a transistor, a structure with an LDD region can be applied. By providing the LDD region, it is possible to reduce the off-state current or improve the breakdown voltage (reliability) of the transistor. Also, by providing the LDD region, when operating in the saturation region, even if the voltage between the drain and source changes, the drain current does not change much, and a flat voltage-current characteristic can be obtained.

[0268] For example, in this specification, transistors can be formed using various substrates. The type of substrate is not limited to a specific one. Examples of such substrates include semiconductor substrates (e.g., single-crystal substrates or silicon substrates), SOI substrates, glass substrates, quartz substrates, plastic substrates, sapphire glass substrates, metal substrates, stainless steel substrates, substrates with stainless steel foil, tungsten substrates, substrates with tungsten foil, flexible substrates, laminated films, paper containing fibrous materials, and base films. Examples of glass substrates include barium borosilicate glass, aluminoborosilicate glass, and soda-lime glass. Examples of flexible substrates, laminated films, and base films include the following: plastics such as polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyethersulfone (PES), and polytetrafluoroethylene (PTFE). Another example is synthetic resins such as acrylic. Examples of suitable substrates include polypropylene, polyester, polyvinyl fluoride, and polyvinyl chloride. Examples of suitable substrates include polyamide, polyimide, aramid, epoxy resin, inorganic vapor-deposited film, and paper. In particular, by manufacturing transistors using semiconductor substrates, single-crystal substrates, and SOI substrates, it is possible to manufacture transistors with small size, high current capability, and little variation in characteristics, size, and shape. Constructing a circuit using such transistors can reduce the power consumption of the circuit or increase the circuit integration.

[0269] Alternatively, a flexible substrate may be used as the substrate, and the transistor may be formed directly on the flexible substrate. Alternatively, a peeling layer may be provided between the substrate and the transistor. The peeling layer can be used to separate a semiconductor device, after a part or all of the semiconductor device is completed thereon, from the substrate and transfer it to another substrate. In this case, the transistor can be transferred to a substrate with poor heat resistance or a flexible substrate. Note that the peeling layer may be, for example, a laminated structure of inorganic films such as a tungsten film and a silicon oxide film, or a structure in which an organic resin film such as polyimide is formed on a substrate.

[0270] That is, a transistor may be formed on a certain substrate, and then the transistor may be transferred to another substrate, and the transistor may be disposed on the other substrate. Examples of substrates onto which transistors may be transferred include, in addition to the substrates on which the transistors can be formed described above, paper substrates, cellophane substrates, aramid film substrates, polyimide film substrates, stone substrates, wood substrates, cloth substrates (including natural fibers (silk, cotton, linen), synthetic fibers (nylon, polyurethane, polyester), or recycled fibers (acetate, cupra, rayon, recycled polyester)), leather substrates, and rubber substrates. The use of these substrates allows for the formation of transistors with good characteristics, the formation of transistors with low power consumption, the manufacture of durable devices, the provision of heat resistance, and the reduction of weight and thickness.

[0271] It is possible to form all of the circuits required to achieve a given function on the same substrate (e.g., a glass substrate, a plastic substrate, a single-crystal substrate, or an SOI substrate), thereby reducing the number of components and thereby reducing costs, and improving reliability by reducing the number of connections to circuit components.

[0272] It is possible that not all of the circuits necessary to realize a predetermined function are formed on the same substrate. That is, a portion of the circuits necessary to realize a predetermined function may be formed on one substrate, and another portion of the circuits necessary to realize the predetermined function may be formed on another substrate. For example, a portion of the circuits necessary to realize a predetermined function may be formed on a glass substrate, and another portion of the circuits necessary to realize the predetermined function may be formed on a single-crystal substrate (or an SOI substrate). Then, the single-crystal substrate (also called an IC chip) on which the other portion of the circuits necessary to realize the predetermined function is formed may be connected to the glass substrate by COG (Chip-On-Glass) and the IC chip may be disposed on the glass substrate. Alternatively, the IC chip may be connected to the glass substrate using TAB (Tape Automated Bonding), COF (Chip-On-Film), SMT (Surface Mount Technology), a printed circuit board, or the like. In this way, forming a portion of the circuit on the same substrate as the pixel unit may reduce the number of components, thereby reducing costs, or reduce the number of connections with circuit components, thereby improving reliability. In particular, circuits with high drive voltages or high drive frequencies often consume a lot of power. Therefore, these circuits are formed on a substrate (such as a single-crystal substrate) separate from the pixel section to form an IC chip. Using this IC chip can prevent an increase in power consumption.

[0273] In the circuit MP of FIG. 15A, the first terminal of the transistor M1 is electrically connected to the wiring VE. The second terminal of the transistor M1 is electrically connected to the first terminal of the transistor M3 and the first terminal of the transistor M4. The gate of the transistor M1 is electrically connected to the first terminal of the capacitor C1 and the first terminal of the transistor M2. The second terminal of the capacitor C1 is electrically connected to the wiring VE. The second terminal of the transistor M2 is electrically connected to the wiring OL. The gate of the transistor M2 is electrically connected to the wiring WL. The second terminal of the transistor M3 is electrically connected to the wiring OL, and the gate of the transistor M3 is electrically connected to the wiring WX1L. The second terminal of the transistor M4 is electrically connected to the wiring OLB, and the gate of the transistor M4 is electrically connected to the wiring X2L.

[0274] A connection configuration in the circuit MCr that is different from that in the circuit MC will be described. The second terminal of the transistor M3r is electrically connected to the wiring OLB instead of the wiring OL, and the second terminal of the transistor M4r is electrically connected to the wiring OL instead of the wiring OLB. The first terminal of the transistor M1r and the first terminal of the capacitor C1r are electrically connected to the wiring VEr.

[0275] 16A, the first terminal of the transistor M1 may be electrically connected to another wiring VLm instead of the wiring VE. Similarly, the first terminal of the transistor M1r may be electrically connected to another wiring VEmr instead of the wiring VEr. In circuit diagrams of not only FIG. 15A but also other drawings, the first terminal of the transistor M1 may be electrically connected to another wiring VEm instead of the wiring VE, and / or the first terminal of the transistor M1r may be electrically connected to another wiring VEmr instead of the wiring VEr.

[0276] In the holding unit HC shown in FIG. 15A, the electrical connection point between the gate of the transistor M1, the first terminal of the capacitor C1, and the first terminal of the transistor M2 is defined as a node n1.

[0277] As described in the first embodiment, the holding unit HC has a function of holding a potential corresponding to the first data, for example. The holding unit HC included in the circuit MC of FIG. 15A holds the potential by inputting a potential from the wiring OL and writing it to the capacitor C1 when the transistors M2 and M3 are turned on, and then turning off the transistor M2. This allows the potential of the node n1 to be held as a potential corresponding to the first data. At this time, a current is input from the wiring OL, and a potential corresponding to the magnitude of the current can be held in the capacitor C1. This reduces the influence of variations in the current characteristics of the transistor M1.

[0278] In addition, since the transistor M1 holds the potential of the node n1 for a long time, it is preferable to use a transistor with low off-state current. For example, an OS transistor can be used as the transistor M1. Alternatively, a transistor with a back gate may be used as the transistor M1, and a low-level potential may be applied to the back gate to shift the threshold voltage to the positive side, thereby reducing the off-state current.

[0279] In the operation example described later, in order to simply explain the current flowing in and out of the circuit MP, both ends of the wiring OL shown in FIG. 15A are respectively referred to as node ina and node outa, and both ends of the wiring OLB are respectively referred to as node inb and node outb.

[0280] For example, the wiring VE functions as a wiring that supplies a constant voltage. When the transistor M3, the transistor M3r, the transistor M4, or the transistor M4r is an n-channel transistor, and / or when the potential applied by the wiring VSO in FIG. 8 is a high-level potential, the constant voltage can be, for example, a low-level potential VSS, a ground potential, or another low-level potential. Similarly to the wiring VE, each of the wirings VEm, VEr, and VLmr functions as a voltage line that supplies a constant voltage, and the constant voltage can be a low-level potential VSS, a low-level potential other than VSS, or a ground potential. Alternatively, the constant voltage can be a high-level potential VDD. In this case, when any of Figures 5A to 5E, 6A to 6D, and 6F is applied as the circuits ACTF[1] to ACTF[n] of the arithmetic circuit 110, the arithmetic circuit 120, the arithmetic circuit 130, the arithmetic circuit 140, the arithmetic circuit 150, and the arithmetic circuit 160, it is preferable that the constant voltage provided by the wiring VAL electrically connected to the circuits ACTF[1] to ACTF[n] is a potential higher than the potential VDD provided by the wiring VE and the wiring VEr.

[0281] Furthermore, the constant voltages supplied by the wirings VE, VEm, VEr, and VEmr may be different from one another, or some or all of them may be the same. Furthermore, if the voltages supplied by the wirings are the same, those wirings may be selected and used as the same wiring. For example, if the constant voltages supplied by the wirings VE, VEm, VEr, and VEmr are approximately equal, the wirings VEm, VEr, and VEmr can be used as the same wiring as the wiring VE, as shown in the circuit MP of FIG. 16B. Alternatively, for example, if the constant voltages supplied by the wirings VL and VLr are approximately equal, the wirings VL and VLr can be used as a single wiring. Alternatively, for example, if the constant voltages supplied by the wirings VLs and VLsr are approximately equal, the wirings VLs and VLsr can be used as a single wiring. 16A, for example, the wiring VL and the wiring VLr may be one and the same wiring, and the wiring VLm and the wiring VLmr may be one and the same wiring. Alternatively, for example, the wiring VL and the wiring VLmr may be one and the same wiring, and the wiring VLm and the wiring VLr may be one and the same wiring.

[0282] The configuration of the circuit MP of FIG. 15A can be changed depending on the situation. For example, as shown in FIG. 17A, the transistors M1, M1r, M3, M3r, M4, and M4r of the circuit MP of FIG. 15A may be replaced with p-channel transistors M1p, M1pr, M3p, M3pr, M4p, and M4pr, respectively. As an example, p-channel transistors having an SOI (Silicon On Insulator) structure can be used for the transistors M3p, M3pr, M4p, and M4pr. In this case, the constant voltage provided by the wiring VE and the wiring VEr is preferably a high-level potential VDD. 5A to 5E, 6A to 6D, and 6F are used as the circuits ACTF[1] to ACTF[n] of the arithmetic circuit 110, the arithmetic circuit 120, the arithmetic circuit 130, the arithmetic circuit 140, the arithmetic circuit 150, and the arithmetic circuit 160, the constant voltage applied by the wiring VAL electrically connected to the circuits ACTF[1] to ACTF[n] is preferably the ground potential or VSS. In this way, when the potential of the wiring is changed, the direction of the current flow is also changed.

[0283] Similarly, the transistor M2 may be replaced with a p-channel transistor.

[0284] 17B, ​​for example, the transistors M4 and M4r in the circuit MP in FIG. 15A may be replaced with p-channel transistors M4p and M4pr, respectively. By combining the wirings connected to the gates of the transistors M3, M3r, M4p, and M4pr into a single wiring WXL, the circuit MP can hold first data (e.g., a weighting coefficient) other than 0.

[0285] 17C, for example, the transistors M3, M3r, M4, and M4r in the circuit MP of FIG. 15A may be replaced with analog switches AS3, AS4, AS3r, and AS4r, respectively. FIG. 17C also illustrates lines WX1LB and X2LB for operating the analog switches AS3, AS4, AS3r, and AS4r. The line WX1LB is electrically connected to the analog switches AS3 and AS3r, and the line X2LB is electrically connected to the analog switches AS4 and AS4r. An inverted signal of a signal input to the line WX1L is input to the line WX1LB, and an inverted signal of a signal input to the line X2L is input to the line X2LB. Alternatively, the lines WX1L and X2L may be combined into a single line, and the lines WX1LB and X2LB may be combined into a single line (not shown). As an example, the analog switch AS3, the analog switch AS4, the analog switch AS3r, and the analog switch AS4r may have a CMOS configuration using n-channel transistors and p-channel transistors.

[0286] Furthermore, it is preferable that the sizes, for example, channel lengths and channel widths, of the transistors M3, M3r, M4, and M4r shown in FIGS. 15A to 15C and 16A to 16C are equal to each other. Such a circuit configuration may enable efficient layout. It may also be possible to equalize the currents flowing through the transistors M3, M3r, M4, and M4r. Similarly, it is preferable that the sizes of the transistors M1 and M1r shown in FIGS. 15A to 15C and 16A to 16C are equal to each other. Similarly, it is preferable that the sizes of the transistors M2 and M2r shown in FIGS. 15A to 15C and 16A to 16C are equal to each other. Similarly, it is preferable that the sizes of the transistors M1p and M1pr shown in FIG. 16C are equal to each other. Similarly, it is preferable that the sizes of the transistors M3p, M3pr, M4p, and M4pr shown in FIG. 16C are equal to each other.

[0287] <<Example of operation>> Next, an example of the operation of the circuit MP shown in FIG. 15A will be described. FIGS. 18 to 20 are timing charts showing an example of the operation of the circuit MP, each showing fluctuations in the potential of the wiring WL, the wiring WX1L, the wiring X2L, the node n1, and the node n1r. Note that "high" in FIGS. 18 to 20 indicates a high-level potential, and "low" indicates a low-level potential. In this example of operation, the amount of current output from the wiring OL to the node outa (or from the node outa to the wiring OL) is expressed as I OL In addition, the amount of current output from the wiring OLB to the node outb (or from the node outb to the wiring OLB) is I OLB In the timing charts shown in FIGS. 18 to 20, I OL , I OLB The change in the

[0288] In this operation example, the constant voltage applied by the wiring VE, wiring VEm, wiring VEr, and wiring VEmr is VSS (low-level potential). In this case, in FIG. 8, a high-level potential is applied to the wiring VSO, and a current flows from the wiring VSO to the wiring VE or wiring VAr via the switching circuit TW and wiring OL. Similarly, a current flows from the wiring VSO to the wiring VE or wiring VAr via the switching circuit TW and wiring OLB.

[0289] 8, the potential applied by the wiring VCN is VSS. By bringing electrical continuity between the wiring VCN and the second terminal of the transistor M1, VSS is applied to the second terminal of the transistor M1. As will be described in detail later, at this time, the potential of the gate of the transistor M1 also becomes VSS, so the transistor M1 is turned off. Similarly, by bringing electrical continuity between the wiring VCN and the second terminal of the transistor M1r, the potential of the second terminal and gate of the transistor M1r becomes VSS, so the transistor M1r is turned off.

[0290] In the circuit MP shown in FIG. 15A, when the transistors M2 and M3 are on, the transistor M1 is diode-connected. Therefore, when a current flows from the wiring OL to the circuit MC, the potentials of the second terminal of the transistor M1 and the gate of the transistor M1 are approximately equal. This potential is determined by the amount of current flowing from the wiring OL to the circuit MC and the potential of the first terminal of the transistor M1 (here, VSS). Here, by holding the potential of the gate of the transistor M1 in the capacitor C1 and then turning off the transistor M2, the transistor M1 functions as a current source that flows a current corresponding to the potential of the gate of the transistor M1. This reduces the effects of variations in the current characteristics of the transistor M1.

[0291] For example, when transistors M2 and M3 are on and a current I1 flows from wiring OL to wiring VE via circuit MC, the potential of the gate (node ​​n1) of transistor M1 becomes V1. Here, by turning transistor M2 off, V1 is held by the holding unit HC. This allows transistor M1 to flow a current I1, which is a current corresponding to the potential VSS of the first terminal of transistor M1 and the potential V1 of the gate of transistor M1, between the source and drain of transistor M1. In this specification, this type of operation is referred to as "transistor M1 has set the amount of current flowing between the source and drain of transistor M1 to I1," "transistor M1 has been programmed to the amount of current flowing between the source and drain of transistor M1 to I1," etc.

[0292] In this operation example, the amount of current flowing from the wiring OL to the circuit MC is assumed to be three levels: 0, I1, and I2. Therefore, the amount of current set to the transistor M1 is three levels: 0, I1, and I2. For example, when the gate potential of the transistor M1 held in the holding unit HC is VSS, the potentials of the first and second terminals of the transistor M1 are also VSS. Therefore, if the threshold voltage of the transistor M1 is higher than 0, the transistor M1 is in the off state. Therefore, no current flows between the source and drain of the transistor M1, and the amount of current flowing between the source and drain of the transistor M1 can be said to be set to 0. Also, for example, when the gate potential of the transistor M1 held in the holding unit HC is V1, if the threshold voltage of the transistor M1 is lower than V1-VSS, the transistor M1 is in the on state. In this case, the amount of current flowing through the transistor M1 is assumed to be I1. Therefore, when the gate potential of the transistor M1 is V1, the amount of current flowing between the source and drain of the transistor M1 can be said to be set to I1. Furthermore, for example, when the gate potential of transistor M1 held in holding unit HC is V2, if the threshold voltage of transistor M1 is lower than V2-VSS, transistor M1 is turned on. At this time, the amount of current flowing through transistor M1 is set to I2. Therefore, when the gate potential of transistor M1 is V2, the amount of current flowing between the source and drain of transistor M1 can be said to be set to I2.

[0293] It is assumed that the current amount of I1 is greater than 0 and smaller than I2. The potential V1 is higher than VSS and lower than V2. The threshold voltage of the transistor M1 is higher than 0 and lower than V1-VSS. I1 is, for example, the current I generated by the constant current source circuit ISC1 in the description of FIG. ut and I2 can be replaced by, for example, 2I generated by the constant current source circuit ISC2 in the description of FIG. ut can be replaced with

[0294] Before describing the operation example, the first data (here, a weighting coefficient, for example) held by the circuit MP will be defined as follows: When VSS is held at node n1 of the holding unit HC and VSS is held at node n1r of the holding unit HCr, the circuit MP will hold "0" as the first data (weighting coefficient). When V1 is held at node n1 of the holding unit HC and VSS is held at node n1r of the holding unit HCr, the circuit MP will hold "+1" as the first data (weighting coefficient). When V2 is held at node n1 of the holding unit HC and VSS is held at node n1r of the holding unit HCr, the circuit MP will hold "+2" as the first data (weighting coefficient). When VSS is held at node n1 of the holding unit HC and V1 is held at node n1r of the holding unit HCr, the circuit MP will hold "-1" as the first data (weighting coefficient). When VSS is held at node n1 of the holding unit HC and V2 is held at node n1r of the holding unit HCr, it is assumed that the circuit MP holds "-2" as the first data (weighting coefficient).

[0295] Furthermore, the second data (here, the neuron signal value (computed value)) input to the circuit MP is defined as follows: When a high-level potential is applied to the wire WX1L and a low-level potential is applied to the wire X2L, "+1" is input to the circuit MP as the second data (neuron signal value). When a low-level potential is applied to the wire WX1L and a high-level potential is applied to the wire X2L, "-1" is input to the circuit MP as the second data (neuron signal value). When a low-level potential is applied to the wire WX1L and a low-level potential is applied to the wire X2L, "0" is input to the circuit MP as the second data (neuron signal value). As an example, the high-level potential is VDD or a potential higher than VDD by 10% or more, or by 20% or more.

[0296] Furthermore, in this specification and the like, unless otherwise specified, the transistors M1 and M1r are considered to ultimately operate in the saturation region when they are on. That is, the gate voltage, source voltage, and drain voltage of each of the above-described transistors are considered to include a case where they are appropriately biased to a voltage range in which they operate in the saturation region. However, one aspect of the present invention is not limited to this. In order to reduce the amplitude of the supplied voltage, the transistors M1 and M1r may operate in the linear region. Note that when the first data (weighting coefficient) is an analog value, the transistors M1 and M1r may operate in both the linear region and the saturation region depending on the magnitude of the first data (weighting coefficient), for example.

[0297] Furthermore, in this specification and the like, unless otherwise specified, the transistors M2, M2r, M3, M3r, M4, and M4r are considered to ultimately operate in a linear region when they are on. That is, the gate voltage, source voltage, and drain voltage of each of the above-described transistors are considered to include a case where they are appropriately biased to a voltage within a range in which they operate in a linear region. However, one embodiment of the present invention is not limited thereto. For example, the transistors M2, M2r, M3, M3r, M4, and M4r may operate in a saturation region when they are on, or may operate in both a linear region and a saturation region.

[0298] Below, we will explain an example of the operation of circuit MP for each combination of values ​​that the first data (for example, referred to as a weighting coefficient below) and the second data (for example, referred to as the neuron signal value (calculated value) below) can take.

[0299] [Condition 1] First, as an example, consider the case where the first data (weighting coefficient) is "0" and the second data (value of the neuron signal (calculated value)) input to the circuit MP is "+1." Figure 18A is a timing chart of the circuit MP in this case.

[0300] Between time T1 and time T2, the holding units HC and HCr hold initial potentials. In Fig. 18A, for example, it is assumed that the nodes n1 and n1r hold potentials higher than the potential VSS as initial potentials.

[0301] A low-level potential is applied to the wiring WL, the wiring WX1L, and the wiring X2L, and as a result, a low-level potential is input to the gates of the transistors M2, M2r, M3, M3r, M4, and M4r, and therefore the transistors M2, M2r, M3, M3r, M4, and M4r are turned off.

[0302] Between time T2 and time T3, a high-level potential is applied to the wiring WL and the wiring WX1L, which causes the gates of the transistors M2, M2r, M3, and M3r to be turned on.

[0303] Although not shown in FIG. 18A, the wiring OL and the wiring OLB are each supplied with an initialization potential V ini Since the transistors M2, M2r, M3, and M3r are in the on state, the potentials of the node n1 of the holding unit HC and the node n1r of the holding unit HCr are V ini That is, between time T2 and time T3, the potentials of the node n1 of the holding unit HC and the node n1r of the holding unit HCr are initialized.

[0304] In addition, the initialization potential V ini For example, it is preferable to set the initial potential V ini The initial potential V may be VSS, a potential higher than the ground potential, or a potential lower than the ground potential. ini The wirings OL and OLB may have different potentials. ini It is not necessary to input the time T2. It is not necessary to provide a period from time T2 to time T3. Also, it is not necessary to perform initialization between time T2 and time T3.

[0305] Between time T3 and time T4, the potential VSS is input from the wiring OL to the circuit MC, and the potential VSS is input from the wiring OLB to the circuit MCr. In FIG. 8, this is achieved by turning on the switches SWL and SWLB and turning off the switches SWI, SWIB, SWO, SWOB, SWH, and SWHB. As a result, the potential of the node n1 of the holding unit HC becomes VSS, and the potential of the node n1r of the holding unit HCr becomes VSS. As a result, in the circuit MC, the transistor M1 is set to pass a current of 0, so no current flows from the wiring OL to the wiring VE via the circuit MC. Also, in the circuit MCr, the transistor M1r is set to pass a current of 0, so no current flows from the wiring OLB to the wiring VE via the circuit MCr. In other words, between time T3 and time T4, the transistors M1 and M1r are in the off state, so that there is no conduction between the wiring OL and the wiring VE, and there is no conduction between the wiring OLB and the wiring VEr.

[0306] Between time T4 and time T5, a low-level potential is applied to the wiring WL and the wiring WX1L. As a result, a low-level potential is input to the gates of the transistors M2, M2r, M3, and M3r, turning off the transistors M2, M2r, M3, and M3r. With the transistors M2 and M2r turned off, the potential VSS of the node n1 of the holding unit HC is maintained, and the potential VSS of the node n1r of the holding unit HCr is maintained. With the transistor M3 turned off, no current flows from the wiring OL to the wiring VE via the circuit MC. Similarly, with the transistor M3r turned off, no current flows from the wiring OLB to the wiring VEr via the circuit MCr. Between time T4 and time T5, the switches SWH and SWHB shown in FIG. 8A may be turned on to initialize the potentials of the wiring OL and the wiring OLB. By initializing the potentials of the wirings OL and OLB, the potentials of the wirings OL and OLB can be changed by the current output from the circuit MP after time T5.

[0307] By the operation from time T1 to time T5, "0" is set as the first data (weighting coefficient) of the circuit MP. After the first data (weighting coefficient) is set in the circuit MP, the switches SWI, SWIB, SWO, SWOB, SWL, and SWLB in FIG. 8 may be turned off. After the weighting coefficient is set in the circuit MP, the switches SWH and SWHB may be turned on to initialize the potentials of the wirings OL and OLB. After the potentials of the wirings OL and OLB are initialized, the switches SWH and SWHB may be turned off.

[0308] After time T5, a high-level potential is input to the wiring WX1L and a low-level potential is input to the wiring X2L as an input of the neuron signal (computed value) "+1" to the circuit MP. At this time, a high-level potential is input to the gates of the transistors M3 and M3r, and a low-level potential is input to the gates of the transistors M4 and M4r. As a result, the transistors M3 and M3r are turned on, and the transistors M4 and M4r are turned off. In other words, this operation brings about a conductive state between the circuit MC and the wiring OL and between the circuit MCr and the wiring OLB, and a non-conductive state between the circuit MC and the wiring OLB and between the circuit MCr and the wiring OL.

[0309] At this time, in FIG. 8, the switches SWO and SWOB are turned on, and the switches SWI, SWIB, SWL, SWLB, SWH, and SWHB are turned off, thereby establishing a conductive state between the wiring OL and the wiring OLB and the circuit AFP. Note that since the transistor M1 is turned off (since it is set to pass a current of 0), no current flows from the wiring OL and the wiring OLB to the wiring VE in the circuit MC. Similarly, since the transistor M1r is turned off (since it is set to pass a current of 0), no current flows from the wiring OL and the wiring OLB to the wiring VE in the circuit MCr. From the above, the current I output from the node outa of the wiring OL is OL , and the current I output from node outb of wiring OLB OLB does not change before and after time T5. Therefore, the current I OL does not flow, and the current I OLB does not flow.

[0310] In this condition, the first data (weighting coefficient) is set to "0" and the second data (neuron signal value (calculated value)) input to the circuit MP is set to "+1". Therefore, when using equation (1.1), the product of the first data (weighting coefficient) and the second data (neuron signal value) is "0". The result of the product of the first data (weighting coefficient) and the second data (neuron signal value) being "0" is that in the operation of the circuit MP, the current I OL and current I OLB The result of the product of the first data (weighting coefficient) and the second data (neuron signal value) being "0" corresponds to the case where the signal z j (k) is output as

[0311] Note that once the first data (e.g., weighting coefficient) is input, multiple product-sum operations may be performed by changing only the second data (e.g., neuron signal value or calculated value) without updating the first data. In this case, updating the first data (weighting coefficient) is not necessary, which reduces power consumption. Note that in order to reduce the frequency of updating the first data (weighting coefficient), the first data (weighting coefficient) needs to be held for a long period of time. In this case, for example, by using an OS transistor, the first data (weighting coefficient) can be held for a long period of time by taking advantage of its low off-state current.

[0312] [Condition 2] Next, as an example, consider a case where the first data (weighting coefficient) is "+1" and the second data (neuron signal value (calculated value)) input to the circuit MP is "+1." Figure 18B is a timing chart of the circuit MP in this case.

[0313] The operation from time T1 to time T3 is the same as the operation from time T1 to time T3 in condition 1, so the explanation of the operation from time T1 to time T3 in condition 1 will be taken into consideration.

[0314] Between time T3 and time T4, a current of I1 is input from the wiring OL to the circuit MC, and a potential VSS is input from the wiring OLB to the circuit MCr. This is achieved by turning on the switches SWI and SWLB in FIG. 8 and turning off the switches SWIB, SWO, SWOB, SWLB, SWH, and SWHB. As a result, the potential of the node n1 in the holding unit HC becomes V1, and the potential of the node n1r in the holding unit HCr becomes VSS. As a result, in the circuit MC, the transistor M1 is set to pass a current of I1, so that a current of I1 flows from the wiring OL to the wiring VE via the circuit MC. Furthermore, in the circuit MCr, the transistor M1r is set to pass a current of 0, so no current flows from the wiring OLB to the wiring VE via the circuit MCr.

[0315] Between time T4 and time T5, a low-level potential is applied to the wiring WL and the wiring WX1L. As a result, a low-level potential is input to the gates of the transistors M2, M2r, M3, and M3r, and the transistors M2, M2r, M3, and M3r are turned off. With the transistors M2 and M2r turned off, the potential V1 of the node n1 of the holding unit HC is held, and the potential VSS of the node n1r of the holding unit HCr is held. With the transistor M3 turned off, no current flows from the wiring OL to the wiring VE via the circuit MC. Similarly, with the transistor M3r turned off, no current flows from the wiring OLB to the wiring VEr via the circuit MCr. Between time T4 and time T5, the switches SWH and SWHB shown in FIG. 8A may be turned on to initialize the potentials of the wiring OL and the wiring OLB. By initializing the potentials of the wirings OL and OLB, the potentials of the wirings OL and OLB can be changed by the current output from the circuit MP after time T5.

[0316] Through the operation from time T1 to time T5, "+1" is set as the first data (weighting coefficient) of the circuit MP. After the first data (weighting coefficient) is set in the circuit MP, the switches SWI, SWIB, SWO, SWOB, SWL, and SWLB in FIG. 8 may be turned off. After the first data (weighting coefficient) is set in the circuit MP, the switches SWH and SWHB may be turned on to initialize the potentials of the wirings OL and OLB. After the potentials of the wirings OL and OLB are initialized, the switches SWH and SWHB may be turned off.

[0317] After time T5, a high-level potential is input to the wiring WX1L and a low-level potential is input to the wiring X2L as an input of second data (neuron signal value (computed value)) "+1" to the circuit MP. At this time, a high-level potential is input to the gates of the transistors M3 and M3r, and a low-level potential is input to the gates of the transistors M4 and M4r. As a result, the transistors M3 and M3r are turned on, and the transistors M4 and M4r are turned off. In other words, this operation brings about a conductive state between the circuit MC and the wiring OL and between the circuit MCr and the wiring OLB, and a non-conductive state between the circuit MC and the wiring OLB and between the circuit MCr and the wiring OL.

[0318] At this time, in FIG. 8, the switches SWO and SWOB are turned on, and the switches SWI, SWIB, SWL, SWLB, SWH, and SWHB are turned off, thereby establishing a conductive state between the wiring OL and the wiring OLB and the circuit AFP. In the circuit MC, the transistor M3 is turned on and the transistor M1r is turned on (since the amount of current I1 is set to flow), so a current flows from the wiring OL to the wiring VE. In the circuit MC, the transistor M4 is turned off, so no current flows from the wiring OLB to the wiring VE. Meanwhile, in the circuit MCr, the transistor M3r is turned on, but the transistor M1 is turned off (since the amount of current 0 is set to flow), so no current flows from the wiring OLB to the wiring VE. In the circuit MCr, the transistor M4r is turned off, so no current flows from the wiring OLB to the wiring VE. In the circuit MCr, the transistor M4r is turned off, so no current flows from the wiring OL to the wiring VE. From the above, the current I output from the node outa of the wiring OL is OL After time T5, I1 increases, and the current I output from node outb of wiring OLB OLB does not change before and after time T5. Therefore, a current I with a current magnitude I1 flows between the circuit AFP and the wiring OL. OL flows, and the current I flows between the circuit AFP and the wiring OLB. OLB does not flow.

[0319] In this condition, the first data (weighting coefficient) is set to "+1" and the second data (neuron signal value) input to the circuit MP is set to "+1". Therefore, using equation (1.1), the product of the first data (weighting coefficient) and the second data (neuron signal value) is "+1". The result of the product of the first data (weighting coefficient) and the second data (neuron signal value) being "+1" is that in the operation of the circuit MP, the current I OL I1 increases, and the current I OLB This corresponds to the case where the product of the first data (weight coefficient) and the second data (neuron signal value) is "+1", as shown in Figure 8, when the signal zj (k) is output as

[0320] Note that, during the period from time T3 to time T4 under this condition, for example, by setting the current flowing from the wiring OL to the circuit MC to I2 instead of I1, V2 can be held in the holding unit HC. As a result, "+2" is set as the first data (weighting coefficient) of the circuit MP. By setting the first data (weighting coefficient) to "+2" and the neuron signal input to the circuit MP to "+1", the product of the first data (weighting coefficient) and the second data (neuron signal value) becomes "+2" according to equation (1.1). As a result of the product of the first data (weighting coefficient) and the second data (neuron signal value) becoming "+2", in the operation of the circuit MP, the current I OL increases, and the current I OLB In this way, by holding VSS in the holding unit HCr in the circuit MCr and setting a current amount other than I1 in the circuit MC, a positive value other than "+1" can be set as the first data (weighting coefficient) of the circuit MP.

[0321] [Condition 3] Next, as an example, consider a case where the first data (weighting coefficient) w is "-1" and the second data (the value (calculated value) of the neuron signal) input to the circuit MP is "+1." Figure 18C is a timing chart of the circuit MP in this case.

[0322] The operation from time T1 to time T3 is the same as the operation from time T1 to time T3 in condition 1, so the explanation of the operation from time T1 to time T3 in condition 1 will be taken into consideration.

[0323] Between time T3 and time T4, a potential VSS is input from the wiring OL to the circuit MC, and a current I1 is input from the wiring OLB to the circuit MCr. This is achieved by turning on the switches SWIB and SWL in FIG. 8 and turning off the switches SWI, SWO, SWOB, SWLB, SWH, and SWHB. As a result, the potential of the node n1 in the holding unit HC becomes VSS, and the potential of the node n1r in the holding unit HCr becomes V1. As a result, in the circuit MCr, the transistor M1 is set to pass a current of 0, so no current flows from the wiring OL to the wiring VE via the circuit MC. Furthermore, in the circuit MCr, the transistor M1r is set to pass a current I1, so the current I1 flows from the wiring OLB to the wiring VE via the circuit MCr.

[0324] Between time T4 and time T5, a low-level potential is applied to the wiring WL and the wiring WX1L. As a result, a low-level potential is input to the gates of the transistors M2, M2r, M3, and M3r, and the transistors M2, M2r, M3, and M3r are turned off. With the transistors M2 and M2r turned off, the potential VSS of the node n1 of the holding unit HC is held, and the potential V1 of the node n1r of the holding unit HCr is held. With the transistor M3 turned off, no current flows from the wiring OL to the wiring VE via the circuit MC. Similarly, with the transistor M3r turned off, no current flows from the wiring OLB to the wiring VEr via the circuit MCr. Between time T4 and time T5, the switches SWH and SWHB shown in FIG. 8A may be turned on to initialize the potentials of the wiring OL and the wiring OLB. By initializing the potentials of the wirings OL and OLB, the potentials of the wirings OL and OLB can be changed by the current output from the circuit MP after time T5.

[0325] By the operation from time T1 to time T5, "-1" is set as the first data (weighting coefficient) of the circuit MP. After the first data (weighting coefficient) is set in the circuit MP, the switches SWI, SWIB, SWO, SWOB, SWL, and SWLB in FIG. 8 may be turned off. After the first data (weighting coefficient) is set in the circuit MP, the switches SWH and SWHB may be turned on to initialize the potentials of the wirings OL and OLB. After the potentials of the wirings OL and OLB are initialized, the switches SWH and SWHB may be turned off.

[0326] After time T5, a high-level potential is input to the wiring WX1L and a low-level potential is input to the wiring X2L as an input of second data (neuron signal value (computed value)) "+1" to the circuit MP. At this time, a high-level potential is input to the gates of the transistors M3 and M3r, and a low-level potential is input to the gates of the transistors M4 and M4r. As a result, the transistors M3 and M3r are turned on, and the transistors M4 and M4r are turned off. In other words, this operation brings about a conductive state between the circuit MC and the wiring OL and between the circuit MCr and the wiring OLB, and a non-conductive state between the circuit MC and the wiring OLB and between the circuit MCr and the wiring OL.

[0327] At this time, in FIG. 8, the switches SWO and SWOB are turned on, and the switches SWI, SWIB, SWL, SWLB, SWH, and SWHB are turned off, thereby establishing a conductive state between the wiring OL and the wiring OLB and the circuit AFP. In the circuit MC, the transistor M3 is turned on, but the transistor M1 is turned off (since the amount of current is set to 0), so no current flows from the wiring OL to the wiring VE. Also, in the circuit MC, the transistor M4 is turned off, so no current flows from the wiring OLB to the wiring VE. Meanwhile, in the circuit MCr, the transistor M3r is turned on, and the transistor M1r is turned on (since the amount of current is set to I1), so a current flows from the wiring OLB to the wiring VE. Also, in the circuit MCr, the transistor M4r is turned off, so no current flows from the wiring OL to the wiring VE. From the above, the current I output from the node outa of the wiring OL is OL does not change before and after time T5, and the current I output from node outb of wiring OLB OLB After time T5, I1 increases. Therefore, the current I OL does not flow, and a current I of magnitude I1 flows between the circuit AFP and the wiring OLB. OLB is playing.

[0328] In this condition, the first data (weighting coefficient) is set to "-1" and the second data (neuron signal value (calculated value)) input to the circuit MP is set to "+1". Therefore, when using formula (1.1), the product of the first data (weighting coefficient) and the second data (neuron signal value) is "-1". The result of the product of the first data (weighting coefficient) and the second data (neuron signal value) being "-1" is that in the operation of the circuit MP, the current I OL does not change, and the current I OLB corresponds to the case where I1 increases. In addition, the result of the product of the first data (weighting coefficient) and the second data (neuron signal value) being "-1" is the result of the signal zj (k) is output as

[0329] Note that, during the period from time T3 to time T4 under this condition, for example, by setting the current flowing from the wiring OLB to the circuit MCr to I2 instead of I1, V2 can be held in the holding unit HCr. As a result, "-2" is set as the first data (weighting coefficient) of the circuit MP. By setting the first data (weighting coefficient) to "-2" and the second data (neuron signal value) input to the circuit MP to "+1", the product of the first data (weighting coefficient) and the second data (neuron signal value) becomes "-2" according to equation (1.1). As a result of the product of the first data (weighting coefficient) and the second data (neuron signal value) becoming "-2", in the operation of the circuit MP, the current I OL does not change, and the current I OLB In this way, by holding VSS in the holding unit HC in the circuit MC and setting a current amount other than I1 in the circuit MCr, it is possible to set a positive value other than "+1" as the weighting coefficient of the circuit MP.

[0330] [Condition 4] In this condition, as an example, consider the operation of the circuit MP when the first data (weighting coefficient) is set to "0" and the second data (value of the neuron signal (calculated value)) input to the circuit MP is set to "-1." Figure 19A is a timing chart of the circuit MP in this case.

[0331] The operation from time T1 to time T5 is the same as the operation from time T1 to time T5 in condition 1, so the explanation of the operation from time T1 to time T5 in condition 1 will be taken into consideration.

[0332] After time T5, a low-level potential is input to the wiring WX1L and a high-level potential is input to the wiring X2L as an input of the second data (value (computed value) of the neuron signal) "-1" to the circuit MP. At this time, a low-level potential is input to the gates of the transistors M3 and M3r, and a high-level potential is input to the gates of the transistors M4 and M4r. As a result, the transistors M3 and M3r are turned off, and the transistors M4 and M4r are turned on. In other words, this operation causes a non-conductive state between the circuit MC and the wiring OL and between the circuit MCr and the wiring OLB, and a conductive state between the circuit MC and the wiring OLB and between the circuit MCr and the wiring OL.

[0333] 8, the switches SWO and SWOB are turned on, and the switches SWI, SWIB, SWL, and SWLB are turned off, so that the wirings OL and OLB are electrically connected to the circuit AFP. Note that since the transistor M1 is turned off (since it is set to pass zero current), no current flows from the wirings OL and OLB to the wiring VE in the circuit MC. In other words, the current I output from the node outa of the wiring OL is OL , and the current I output from node outb of wiring OLB OLB does not change before and after time T5. Similarly, since the transistor M1r is in the off state (since it is set to pass 0 as the amount of current), in the circuit MCr, no current flows through the wiring OL and between the wiring OLB and the wiring VEr. In other words, the current I output from the node outa of the wiring OL OL , and the current I output from node outb of wiring OLB OLB Therefore, the current I OL does not flow, and the current I OLB does not flow.

[0334] In this condition, the first data (weighting coefficient) is set to "0" and the second data (neuron signal value (calculated value)) input to the circuit MP is set to "-1", so when formula (1.1) is used, the product of the first data (weighting coefficient) and the second data (neuron signal value) is "0". The result of the product of the first data (weighting coefficient) and the second data (neuron signal value) being "0" is that in the operation of the circuit MP, the current I OL and current I OLB This corresponds to the case where none of the first data (weighting coefficient) and the second data (neuron signal value) are changed, which is the result of the circuit operation under condition 1. In addition, the result where the product of the first data (weighting coefficient) and the second data (neuron signal value) is "0" is the result where, as in condition 1, in FIG. 8, the signal z j (k) is output as

[0335] [Condition 5] In this condition, as an example, consider the operation of the circuit MP when the first data (weighting coefficient) is set to "+1" and the second data (value of the neuron signal (calculated value)) input to the circuit MP is set to "-1." Figure 19B is a timing chart of the circuit MP in this case.

[0336] The operation from time T1 to time T5 is similar to the operation from time T1 to time T5 in condition 2, so the explanation of the operation from time T1 to time T5 in condition 2 should be taken into consideration.

[0337] After time T5, a low-level potential is input to the wiring WX1L and a high-level potential is input to the wiring X2L as an input of the second data (value (computed value) of the neuron signal) "-1" to the circuit MP. At this time, a low-level potential is input to the gates of the transistors M3 and M3r, and a high-level potential is input to the gates of the transistors M4 and M4r. As a result, the transistors M3 and M3r are turned off, and the transistors M4 and M4r are turned on. In other words, this operation causes a non-conductive state between the circuit MC and the wiring OL and between the circuit MCr and the wiring OLB, and a conductive state between the circuit MC and the wiring OLB and between the circuit MCr and the wiring OL.

[0338] At this time, in FIG. 8, the switches SWO and SWOB are turned on, and the switches SWI, SWIB, SWL, SWLB, SWH, and SWHB are turned off, thereby establishing a conductive state between the wiring OL and the wiring OLB and the circuit AFP. In the circuit MC, the transistor M3 is turned off, so no current flows from the wiring OL to the wiring VE. In addition, in the circuit MC, the transistor M4 is turned on, and the transistor M1r is turned on (since the amount of current I1 is set to flow), so a current flows from the wiring OLB to the wiring VE. On the other hand, in the circuit MCr, the transistor M3r is turned off, so no current flows from the wiring OLB to the wiring VE. In addition, in the circuit MCr, the transistor M4r is turned on, but the transistor M1 is turned off (since the amount of current 0 is set to flow), so no current flows from the wiring OL to the wiring VE. From the above, the current I output from the node outa of the wiring OL is OL does not change before and after time T5, and the current I output from node outb of wiring OLB OLB After time T5, I1 increases. Therefore, the current I OLdoes not flow, and a current I of magnitude I1 flows between the circuit AFP and the wiring OLB. OLB is playing.

[0339] In this condition, the first data (weighting coefficient) is set to "+1" and the second data (neuron signal value (calculated value)) input to the circuit MP is set to "-1". Therefore, when using formula (1.1), the product of the first data (weighting coefficient) and the second data (neuron signal value) is "-1". The result of the product of the first data (weighting coefficient) and the second data (neuron signal value) being "-1" is that in the operation of the circuit MP, the current I OL does not change, and the current I OLB corresponds to the case where I1 increases, which coincides with the result of the circuit operation under condition 3. Note that the result of the product of the first data (weighting coefficient) and the second data (neuron signal value) being "-1" is the same as under condition 3, as shown in Figure 8, when the signal z j (k) is output as

[0340] As described in Condition 2, during the period from time T3 to time T4 under this condition, for example, the current flowing from the wiring OL to the circuit MC may be set to I2 instead of I1, and V2 may be held in the holding unit HC. As a result, "+2" is set as the first data (weighting coefficient) of the circuit MP. By setting the first data (weighting coefficient) to "+2" and the neuron signal input to the circuit MP to "-1", the product of the first data (weighting coefficient) and the second data (neuron signal value) becomes "-2" according to equation (1.1). As a result of the product of the first data (weighting coefficient) and the second data (neuron signal value) becoming "-2", in the operation of the circuit MP, the current I OL does not change, and the current I OLB In this way, by holding VSS in the holding unit HCr in the circuit MCr and setting a current amount other than I1 in the circuit MC, it is possible to set a positive value other than "+1" as the weighting coefficient of the circuit MP.

[0341] [Condition 6] In this condition, as an example, consider the operation of the circuit MP when the first data (weighting coefficient) is set to "-1" and the second data (value of the neuron signal (calculated value)) input to the circuit MP is set to "-1." Figure 19C is a timing chart of the circuit MP in this case.

[0342] The operation from time T1 to time T5 is similar to the operation from time T1 to time T5 in condition 3, so the explanation of the operation from time T1 to time T5 in condition 3 should be taken into consideration.

[0343] After time T5, a low-level potential is input to the wiring WX1L and a high-level potential is input to the wiring X2L as an input of the second data (value (computed value) of the neuron signal) "-1" to the circuit MP. At this time, a low-level potential is input to the gates of the transistors M3 and M3r, and a high-level potential is input to the gates of the transistors M4 and M4r. As a result, the transistors M3 and M3r are turned off, and the transistors M4 and M4r are turned on. In other words, this operation causes a non-conductive state between the circuit MC and the wiring OL and between the circuit MCr and the wiring OLB, and a conductive state between the circuit MC and the wiring OLB and between the circuit MCr and the wiring OL.

[0344] At this time, in FIG. 8, the switches SWO and SWOB are turned on, and the switches SWI, SWIB, SWL, SWLB, SWH, and SWHB are turned off, thereby establishing a conductive state between the wiring OL and the wiring OLB and the circuit AFP. In the circuit MC, the transistor M3 is turned off, so no current flows from the wiring OL to the wiring VE. Also, in the circuit MC, the transistor M4 is turned on, but the transistor M1 is turned off (since it is set to pass a current of 0), so no current flows from the wiring OLB to the wiring VE. On the other hand, in the circuit MCr, the transistor M3r is turned off, so no current flows from the wiring OLB to the wiring VE. Also, in the circuit MCr, the transistor M4r is turned on, and the transistor M1 is turned on (since it is set to pass a current of I1), so a current flows from the wiring OL to the wiring VE. From the above, the current I output from the node outa of the wiring OL is OL After time T5, I1 increases, and the current I output from node outb of wiring OLB OLB does not change before and after time T5. Therefore, a current I with a current magnitude I1 flows between the circuit AFP and the wiring OL. OL flows, and the current I flows between the circuit AFP and the wiring OLB. OLB does not flow.

[0345] In this condition, the first data (weighting coefficient) is set to "-1" and the second data (neuron signal value (calculated value)) input to the circuit MP is set to "-1". Therefore, when using formula (1.1), the product of the first data (weighting coefficient) and the second data (neuron signal value) is "+1". The result of the product of the first data (weighting coefficient) and the second data (neuron signal value) being "+1" is that in the operation of the circuit MP, the current I OL changes, and the current I OLBThis corresponds to the case where the value of the first data (weighting coefficient) and the value of the neuron signal are unchanged, which is consistent with the circuit operation result of condition 2. Note that the result of the product of the first data (weighting coefficient) and the first data (neuron signal value) being "+1" is the same as condition 2, in FIG. 8, when the signal z j (k) is output as

[0346] As described in Condition 3, during the period from time T3 to time T4 under this condition, for example, the current flowing from the wiring OLB to the circuit MCr may be set to I2 instead of I1, and V2 may be held in the holding unit HC. As a result, "-2" is set as the first data (weighting coefficient) of the circuit MP. By setting the first data (weighting coefficient) to "-2" and the second data (neuron signal value) input to the circuit MP to "-1", the product of the first data (weighting coefficient) and the second data (neuron signal value) becomes "+2" according to equation (1.1). As a result of the product of the first data (weighting coefficient) and the second data (neuron signal value) becoming "+2", in the operation of the circuit MP, the current I OL does not change, and the current I OLB In this way, by holding VSS in the holding unit HC in the circuit MC and setting a current amount other than I1 in the circuit MCr, it is possible to set a positive value other than "+1" as the weighting coefficient of the circuit MP.

[0347] [Condition 7] In this condition, as an example, the operation of the circuit MP is considered under the condition 7 where the first data (weighting coefficient) is "0" and the second data (value of the neuron signal (calculated value)) input to the circuit MP is "0." Figure 20A is a timing chart of the circuit MP in this case.

[0348] The operation from time T1 to time T5 is the same as the operation from time T1 to time T5 in condition 1, so the explanation of the operation from time T1 to time T5 in condition 1 will be taken into consideration.

[0349] After time T5, a low-level potential is input to the wiring WX1L and a low-level potential is input to the wiring X2L as an input of second data (neuron signal value (computed value)) "0" to the circuit MP. At this time, a low-level potential is input to the gates of the transistors M3, M3r, M4, and M4r. As a result, the transistors M3, M3r, M4, and M4r are each turned off. In other words, this operation causes a non-conductive state between the circuit MC and the wiring OL, between the circuit MCr and the wiring OLB, between the circuit MC and the wiring OLB, and between the circuit MCr and the wiring OL.

[0350] Therefore, in the circuit MC, regardless of the set amount of current flowing through the transistor M1, no current flows from the wiring OL to either the wiring VE or the wiring VEl. Similarly, in the circuit MCr, regardless of the set amount of current flowing through the transistor M1r, no current flows from the wiring OLB to the other of the wiring VE or the wiring VEl. In other words, the current I output from the node outa of the wiring OL OL , and the current I output from node outb of wiring OLB OLB Each of these does not change before and after time T5.

[0351] In addition, in FIG. 8, even if the switches SWO and SWOB are turned on and the switches SWI, SWIB, SWL, SWLB, SWH, and SWHB are turned off to establish electrical continuity between the wiring OL and the circuit AFP, as described above, the current I OL does not flow, and the current I OLB does not flow.

[0352] In this condition, the first data (weighting coefficient) is set to "0" and the second data (neuron signal value (calculated value)) input to the circuit MP is set to "0", so when formula (1.1) is used, the product of the first data (weighting coefficient) and the second data (neuron signal value) is "0". As a result of the product of the first data (weighting coefficient) and the second data (neuron signal value) being "0", in the operation of the circuit MP, the current I OL and current I OLB This corresponds to the case where none of the first data (weighting coefficient) and the second data (neuron signal value) change, which coincides with the results of the circuit operation under conditions 1 and 4. Note that, as with conditions 1 and 4, the result of the product of the first data (weighting coefficient) and the second data (neuron signal value) being "0" is the result of the signal z j (k) is output as

[0353] [Condition 8] In this condition, as an example, the operation of the circuit MP is considered under the condition 8 where the first data (weighting coefficient) is "+1" and the second data (value of the neuron signal (calculated value)) input to the circuit MP is "0." Figure 20B is a timing chart of the circuit MP in this case.

[0354] The operation from time T1 to time T5 is similar to the operation from time T1 to time T5 in condition 2, so the explanation of the operation from time T1 to time T5 in condition 2 should be taken into consideration.

[0355] After time T5, a low-level potential is input to the wire WX1L and a low-level potential is input to the wire X2L as an input of second data (value (computed value) of the neuron signal) "0" to the circuit MP. At this time, a low-level potential is input to the gates of the transistors M3, M3r, M4, and M4r. Therefore, the transistors M3, M3r, M4, and M4r are each turned off. That is, as in condition 7, this operation results in a non-conduction state between the circuit MC and the wire OL, between the circuit MCr and the wire OLB, between the circuit MC and the wire OLB, and between the circuit MCr and the wire OL, regardless of the set amount of current flowing through the transistor M1 and the transistor M1r. Therefore, no current flows from the wire OL to either the wire VE or the wire VAr, and no current flows from the wire OLB to the other of the wire VE or the wire VAr. Therefore, the current I output from the node outa of the wire OL is OL , and the current I output from node outb of wiring OLB OLB Each of these does not change before and after time T5.

[0356] In addition, in FIG. 8, even if the switches SWO and SWOB are turned on and the switches SWI, SWIB, SWL, and SWLB are turned off to establish electrical continuity between the wiring OL and the circuit AFP, as described above, the current I OL does not flow, and the current I OLB does not flow.

[0357] In this condition, the first data (weighting coefficient) is set to "+1" and the second data (neuron signal value (calculated value)) input to the circuit MP is set to "0", so when formula (1.1) is used, the product of the first data (weighting coefficient) and the second data (neuron signal value) is "0". The result of the product of the first data (weighting coefficient) and the second data (neuron signal value) being "0" is that in the operation of the circuit MP, the current I OLand current I OLB This corresponds to the case where none of the first data (weighting coefficient) and the second data (neuron signal value) change, which coincides with the results of the circuit operation under conditions 1, 4, and 7. Note that the result of the product of the first data (weighting coefficient) and the second data (neuron signal value) being "0" is the same as under conditions 1, 4, and 7, in FIG. 8, when the signal z j (k) is output as

[0358] [Condition 9] In this condition, as an example, the operation of the circuit MP is considered under the condition 9 where the first data (weighting coefficient) is "-1" and the second data (value of the neuron signal (calculated value)) input to the circuit MP is "0." Figure 20C is a timing chart of the circuit MP in this case.

[0359] The operation from time T1 to time T5 is similar to the operation from time T1 to time T5 in condition 3, so the explanation of the operation from time T1 to time T5 in condition 3 should be taken into consideration.

[0360] After time T5, a low-level potential is input to the wire WX1L and a low-level potential is input to the wire X2L as an input of second data (value (computed value) of the neuron signal) "0" to the circuit MP. At this time, a low-level potential is input to the gates of the transistors M3, M3r, M4, and M4r. Therefore, the transistors M3, M3r, M4, and M4r are each turned off. That is, as in condition 7, this operation results in a non-conduction state between the circuit MC and the wire OL, between the circuit MCr and the wire OLB, between the circuit MC and the wire OLB, and between the circuit MCr and the wire OL, regardless of the set amount of current flowing through the transistor M1 and the transistor M1r. Therefore, no current flows from the wire OL to either the wire VE or the wire VAr, and no current flows from the wire OLB to the other of the wire VE or the wire VAr. Therefore, the current I output from the node outa of the wire OL is OL , and the current I output from node outb of wiring OLBOLB Each of these does not change before and after time T5.

[0361] In addition, in FIG. 8, even if the switches SWO and SWOB are turned on and the switches SWI, SWIB, SWL, SWLB, SWH, and SWHB are turned off to establish electrical continuity between the wiring OL and the circuit AFP, as described above, the current I OL does not flow, and the current I OLB does not flow.

[0362] In this condition, the first data (weighting coefficient) is set to "-1" and the second data (neuron signal value (calculated value)) input to the circuit MP is set to "0", so when formula (1.1) is used, the product of the first data (weighting coefficient) and the second data (neuron signal value) is "0". The result of the product of the first data (weighting coefficient) and the second data (neuron signal value) being "0" is that in the operation of the circuit MP, the current I OL and current I OLB This corresponds to the case where none of the first data (weighting coefficient) and the second data (neuron signal value) change, which is the same as the case of conditions 1, 4, 7, and 8. The result of the product of the first data (weighting coefficient) and the second data (neuron signal value) being "0" is the same as the case of conditions 1, 4, 7, and 8, in Figure 8, when the signal z j (k) is output as

[0363] The following table summarizes the results of the operation examples under the above-described conditions 1 to 9. In the table below, a high level potential is written as "high" and a low level potential is written as "low."

[0364] [Table 2]

[0365] Here, an example is shown in which one circuit MC and one circuit MCr are connected to the wiring OL and wiring OLB, respectively. However, as shown in Figures 2, 3, 4, 7, 11, 12, 6, etc., if multiple circuits MC and multiple circuits MCr are connected to the wiring OL and wiring OLB, the currents output from each circuit MC and circuit MCr are added together based on Kirchhoff's current law. As a result, a sum operation is performed. In other words, a product operation is performed in the circuits MC and MCr, and a sum operation is performed by adding together the currents from the multiple circuits MC and MCr. As a result of the above, a product-sum operation is performed.

[0366] By the way, in the operation of circuit MP, by performing calculations with the first data (weighting coefficient) having only two values, "+1" and "-1", and the second data (neuron signal value) having only two values, "+1" and "-1", circuit MP can perform the same operation as an exclusive OR negation circuit (match circuit).

[0367] Furthermore, in the operation of circuit MP, by performing calculations in which the first data (weighting coefficient) has only two values, "+1" and "0", and the second data (neuron signal value) has only two values, "+1" and "0", circuit MP can perform the same operation as a logical product circuit.

[0368] In this operation example, the potentials held in the holding units HC and HCr of the circuits MC and MCr of the circuit MP are multi-valued, such as VSS, V1, and V2, but the holding units HC and HCr may hold potentials indicating two values ​​or analog values. For example, when the first data (weighting coefficient) is a "positive analog value," a high-level analog potential is held at the node n1 of the holding unit HC, and a low-level potential is held at the node n1r of the holding unit HCr. When the first data (weighting coefficient) is a "negative analog value," for example, a low-level potential is held at the node n1 of the holding unit HC, and a high-level analog potential is held at the node n1r of the holding unit HCr. Then, the current I OL and current I OLBThe magnitude of the current in the holding units HC and HCr corresponds to the analog potential. Holding a potential representing an analog value in the holding units HC and HCr is not limited to the operation example of the circuit MP shown in FIG. 15A, and may also be performed in other circuits MP shown in this specification.

[0369] This configuration example can be appropriately combined with other configuration examples shown in this specification.

[0370] <Configuration example 2> Next, an example of a circuit configuration that is different from the circuit configurations in FIGS. 15A to 15C, 16A, and 16B and that can be applied to the circuit MP shown in FIG. 9B will be described.

[0371] The circuit MP shown in Figure 21A shows an example configuration of the circuit MP of Figure 9B, and differs from the circuit MP of Figure 15A in that the second terminal of transistor M2 is electrically connected to the second terminal of transistor M1, the first terminal of transistor M3, and the first terminal of transistor M4 rather than to wiring OL, and the second terminal of transistor M2r is electrically connected to the second terminal of transistor M1r, the first terminal of transistor M3r, and the first terminal of transistor M4r rather than to wiring OLB.

[0372] The circuit MP of FIG. 21A can operate similarly to the circuit MP of FIG. 15A.

[0373] Next, another example of a circuit configuration that is different from that of Fig. 21A and can be applied to the circuit MP shown in Fig. 9B will be described. The circuit MP shown in Fig. 21B illustrates a configuration example of the circuit MP of Fig. 9B, and differs from the circuit MP of Fig. 15A in that the circuit MC includes a transistor M1c, and the first terminal of the transistor M4 is electrically connected to the transistor M1c, rather than to the second terminal of the transistor M1 and the second terminal of the transistor M3, and that the circuit MCr includes a transistor M1cr, and the first terminal of the transistor M4r is electrically connected to the transistor M1cr, rather than to the second terminal of the transistor M1r and the second terminal of the transistor M3r.

[0374] In this specification and the like, unless otherwise specified, the transistors M1c and M1cr are considered to ultimately operate in the saturation region when they are on. That is, the gate voltage, source voltage, and drain voltage of each of the above-described transistors are considered to be appropriately biased to voltages within the range in which they operate in the linear region. However, one aspect of the present invention is not limited to this. In order to reduce the amplitude of the supplied voltage, the transistors M1c and M1cr may operate in the linear region. In addition, when the first data (e.g., a weighting coefficient here) is an analog value, the transistors M1c and M1cr may operate in both the linear region and the saturation region depending on the magnitude of the first data (weighting coefficient).

[0375] 21B, a first terminal of the transistor M1c is electrically connected to the wiring VE. The gate of the transistor M1c is electrically connected to the gate of the transistor M1, a first terminal of the transistor M2, and a first terminal of the capacitor C1. In addition, a second terminal of the transistor M1c is electrically connected to a first terminal of the transistor M4.

[0376] 21B, the circuit MCr has a circuit configuration similar to that of the circuit MC, and therefore, the circuit elements of the circuit MCr are designated by the letter "r" to distinguish them from the circuit elements of the circuit MC.

[0377] Furthermore, explanations of the circuit MP in FIG. 21B and the circuit MP in FIG. 15A that have the same connection configuration will be omitted.

[0378] In the circuit MP of FIG. 21B, the currents flowing through the transistors M3 and M4 are determined by the gate potentials of the transistors M1 and M1c, respectively. For example, it is preferable that the sizes of the transistors M1 and M1c, such as the channel length and channel width, are equal to each other. Such a circuit configuration may enable an efficient layout. It may also be possible to align the currents flowing through the transistors M3 and M4.

[0379] The circuit MP of FIG. 21B can operate similarly to the circuit MP of FIG. 15A.

[0380] This configuration example can be appropriately combined with other configuration examples shown in this specification.

[0381] <Configuration example 3> Next, an example of a circuit configuration that can be applied to the circuit MP shown in FIG. 9E will be described.

[0382] The circuit MP shown in Figure 22A shows an example configuration of the circuit MP of Figure 9E, and differs from the circuit MP of Figure 15A in that the circuit MC includes a transistor M5, the circuit MCr includes a transistor M5r, and the circuit MP is electrically connected to the wiring IL and the wiring ILB.

[0383] In this specification and the like, unless otherwise specified, the on-state of the transistors M5 and M5r includes the case where they ultimately operate in a linear region, i.e., the gate voltage, source voltage, and drain voltage of each of the above-described transistors includes the case where they are appropriately biased to voltages within the range where they operate in a linear region.

[0384] 22A, the first terminal of the transistor M5 is electrically connected to the second terminal of the transistor M2 and the wiring IL. The second terminal of the transistor M5 is electrically connected to the second terminal of the transistor M1, the first terminal of the transistor M3, and the first terminal of the transistor M4. The gate of the transistor M5 is electrically connected to the wiring WL.

[0385] 22A, the circuit MCr has a circuit configuration similar to that of the circuit MC, and therefore, the circuit elements of the circuit MCr are designated by the letter "r" to distinguish them from the circuit elements of the circuit MC.

[0386] Furthermore, explanations of the circuit MP in FIG. 22A and the circuit MP in FIG. 15A that have the same connection configuration will be omitted.

[0387] 22A, similarly to Configuration Examples 1 and 2, the sizes (e.g., channel length and channel width) of transistors M1, M2, M3, and M4 are preferably equal to the sizes of transistors M1r, M2r, M3r, and M4r, respectively. Such a circuit configuration may enable an efficient layout. Additionally, the size of transistor M5 is preferably equal to the size of transistor M5r.

[0388] When setting currents in the circuits MC and MCr, a high-level potential is applied to the wiring WL to turn on the transistors M2, M2r, M5, and M5r. After setting currents in the circuits MC and MCr, a low-level potential is applied to the wiring WL to turn off the transistors M2, M2r, M5, and M5r in order to hold the potentials set in the holding units HC and HCr.

[0389] In the circuit MP described in the configuration examples 1 and 2, the wiring for transmitting the second data (for example, the value of a neuron signal here) and the wiring for supplying or holding information (for example, voltage, current, etc.) corresponding to the first data (for example, a weighting coefficient here) to the circuit MP are collectively designated as the wiring WX1L. However, by configuring the circuit MP in Fig. 22, the wiring for transmitting the second data (the value of a neuron signal) can be designated as the wiring X1L, and the wiring for supplying or holding information (for example, voltage, current, etc.) corresponding to the first data (weighting coefficient) to the circuit MP can be designated as the wiring WL. In other words, the circuit MP in Fig. 22 can be said to have a configuration in which the wiring WX1L of the circuit MP in the configuration examples 1 and 2 is divided by function.

[0390] FIG. 22B shows a circuit configuration different from the circuit MP of FIG. 22A.

[0391] The circuit MP shown in Fig. 22B has a configuration in which the electrical connections of the first terminals of the transistors M5 and M5r in the circuit MP of Fig. 22A are changed. Specifically, in the circuit MP of Fig. 22B, the first terminal of the transistor M5 is electrically connected to the first terminal of the transistor M2, the gate of the transistor M1, and the first terminal of the capacitor C1.

[0392] By configuring the circuit MP shown in FIG. 22B, the circuit MP of FIG. 22B operates in substantially the same manner as the circuit MP of FIG. 22A.

[0393] 22A and 22B may be configured such that the wirings IL and ILB are combined into wiring OL and wiring OLB, respectively. For example, in the circuit MP shown in FIG. 22A, the wirings IL and ILB are combined into wiring OL and wiring OLB, respectively, to form the circuit MP shown in FIG. 23A. Furthermore, in the circuit MP shown in FIG. 22B, the wirings IL and ILB are combined into wiring OL and wiring OLB, respectively, to form the circuit MP shown in FIG. 23B. Each of the circuits MP shown in FIGS. 23A and 23B has a circuit configuration applicable to the circuit MP shown in FIG. 9A. The operation of each of the circuits MP shown in FIGS. 23A and 23B should be described with reference to the description of the operation of the circuit MP in FIG. 15A.

[0394] This configuration example can be appropriately combined with other configuration examples shown in this specification.

[0395] <Configuration Example 4> The circuit MP shown in FIG. 24 is an example of a circuit that differs from the circuit MP in FIG. 15A in that it has not only a holding unit HC and a holding unit HCr but also a holding unit HCs and a holding unit HCsr.

[0396] The circuit MC included in the circuit MP of Fig. 24 includes, in addition to the circuit elements included in the circuit MP of Fig. 21A, transistors M1s, M2s, M6, M6s, and capacitance C1s. The circuit MCr included in the circuit MP of Fig. 20 includes the same circuit elements as the circuit MC, and therefore includes transistors M1sr, M2sr, M6r, M6sr, and capacitance C1sr, which correspond to the transistors M1s, M2s, M6, M6s, and capacitance C1s of the circuit MC, respectively. The transistor M2s and capacitance C1s are included in a holding unit HCs, and the transistor M2sr and capacitance C1sr are included in a holding unit HCs.

[0397] In this specification and the like, unless otherwise specified, the on-state of the transistors M2s, M6, M6s, M6r, and M6sr includes the case where they ultimately operate in a linear region. In other words, the gate voltage, source voltage, and drain voltage of each of the above-mentioned transistors includes the case where they are appropriately biased to voltages within the range where they operate in a linear region.

[0398] Next, a description will be given of the configuration of the circuit MP in Fig. 24. Note that in the circuit MP in Fig. 24, parts that have the same configuration as the circuit MP in Fig. 21A will be omitted.

[0399] In the circuit MP of FIG. 24, the second terminal of the transistor M1 is electrically connected to the second terminal of the transistor M2 and the first terminal of the transistor M6. The second terminal of the transistor M6 is electrically connected to the first terminal of the transistor M3 and the second terminal of the transistor M4. The gate of the transistor M6 is electrically connected to a wiring S1L. The first terminal of the transistor M1s is electrically connected to a wiring VE. The second terminal of the transistor M1s is electrically connected to the first terminal of the transistor M6s. The gate of the transistor M1s is electrically connected to the first terminal of the capacitor C1s and the first terminal of the transistor M2s. The second terminal of the capacitor C1s is electrically connected to the wiring VE. The second terminal of the transistor M2 is electrically connected to the second terminal of the transistor M1s and the first terminal of the transistor M6s. The second terminal of the transistor M6s is electrically connected to the first terminal of the transistor M3 and the second terminal of the transistor M4. The gate of the transistor M6s is electrically connected to a wiring S2L.

[0400] 24, the circuit MCr has a circuit configuration similar to that of the circuit MC, and therefore the circuit elements of the circuit MCr are designated by the letter "r" to distinguish them from the circuit elements of the circuit MC.

[0401] The wiring S1L functions as a voltage line that supplies a potential for turning on or off the transistor M6 and the transistor M6r, and the wiring S2L functions as a voltage line that supplies a potential for turning on or off the transistor M6s and the transistor M6sr.

[0402] 24, the sizes, such as the channel lengths and channel widths, of the transistors M6, M6s, M6r, and M6sr are preferably equal to one another. Such a circuit configuration may enable an efficient layout.

[0403] For example, by applying the configuration shown in the circuit MP of FIG. 24 to the arithmetic circuit 150 shown in FIG. 11, the circuit MP of the arithmetic circuit 150 can hold two pieces of first data (for example, weighting coefficients here). Specifically, the circuit MP of FIG. 24 can hold a potential corresponding to the first piece of first data (weighting coefficient) in the holding unit HC of the circuit MC and the holding unit HCr of the circuit MCr, and can hold a potential corresponding to the second piece of first data (weighting coefficient) in the holding unit HCs of the circuit MC and the holding unit HCsr of the circuit MC. Furthermore, the circuit MP of FIG. 24 can switch the first data (weighting coefficient) used in the arithmetic operation by the potentials applied from the wirings S1L and S2L. For example, the first data (weighting coefficient) w1 is stored in the holding units HC and HCr included in the circuits MP[1,j] to MP[m,j] of the arithmetic circuit 150. (k-1) j (k) Or even w m (k-1) j (k) and stores the first data (weighting coefficient) w1 in each of the holding units HCs and HCsr included in the circuits MP[1,j] to MP[m,j] of the arithmetic circuit 110. (k-1) h (k) Or even w m (k-1) h (k)(where h is an integer greater than or equal to 1 and not equal to j) is held, and the signal z1 (k-1) ~z m (k-1) At this time, a high-level potential is applied to the wiring S1L to turn on the transistors M6 and M6r, and a low-level potential is applied to the wiring S2L to turn off the transistors M6s and M6sr. This causes the circuits MP[1,j] to MP[m,j] in the arithmetic circuit 150 to calculate the weight coefficient w1 (k-1) j (k) Or even w m (k-1) j (k) and signal z1 (k-1) ~z m (k-1) In addition, by applying a low-level potential to the wiring S1L to turn off the transistors M6 and M6r, and by applying a high-level potential to the wiring S2L to turn on the transistors M6s and M6sr, the circuits MP[1,j] to MP[m,j] in the arithmetic circuit 150 can calculate the sum of products of the weight coefficient w1 (k-1) h (k) Or even w m (k-1) h (k) and signal z1 (k-1) ~z m (k-1) It is possible to perform product sum and activation function calculations.

[0404] As described above, by applying the circuit MP of FIG. 24 to the arithmetic circuit 150, two weighting coefficients can be held, and the weighting coefficients can be switched to perform product-sum and activation function calculations. The arithmetic circuit 150 including the circuit MP of FIG. 24 is effective, for example, when the number of neurons in the kth layer is greater than n, or when performing calculations in an intermediate layer other than the kth layer. Furthermore, in the circuit MP of FIG. 24, the circuits MC and MCr each have two holding units, but each of the circuits MC and MCr may have three or more holding units depending on the situation.

[0405] The circuit MP included in the semiconductor device of one embodiment of the present invention is not limited to the circuit MP in Figure 24. The circuit MP of the semiconductor device of one embodiment of the present invention can have a circuit configuration changed from the circuit MP in Figure 24 depending on the situation.

[0406] For example, the circuit MP shown in FIG. 25 has a circuit configuration obtained by modifying the circuit MP of FIG. 24. Specifically, the circuit MP of FIG. 25 includes transistors M3s, M4s, M3sr, and M4sr in addition to the circuit MP of FIG. 24, and the electrical connections are modified. The first terminal of the transistor M3s is electrically connected to the second terminal of the transistor M6s and the first terminal of the transistor M4s, the second terminal of the transistor M3s is electrically connected to the wiring OL, and the gate of the transistor M3s is electrically connected to the wiring WX1L. The second terminal of the transistor M4s is electrically connected to the wiring OLB, and the gate of the transistor M4s is electrically connected to the wiring X2L.

[0407] 25, the circuit MCr has a circuit configuration substantially similar to that of the circuit MC. Therefore, the circuit elements of the circuit MCr are denoted by the letter "r" to distinguish them from the circuit elements of the circuit MC. In the circuit MCr, the second terminal of the transistor M3sr is electrically connected to the wiring OL, and the second terminal of the transistor M4sr is electrically connected to the wiring OLB.

[0408] 25, the sizes, such as channel lengths and channel widths, of the transistors M3, M3s, M3r, M3sr, M4, M4s, M4r, and M4sr are preferably equal to one another. Such a circuit configuration may enable an efficient layout.

[0409] The circuit MP in Fig. 25 can hold two pieces of first data (weighting coefficients) by performing the same operation as the circuit MP in Fig. 24, and can switch the first data (weighting coefficients) to perform calculations of product sums and activation functions. In addition, in the circuit MP in Fig. 25, the circuit MC and the circuit MCr each have two holding units, but each of the circuit MC and the circuit MCr may have three or more holding units depending on the situation.

[0410] This configuration example can be appropriately combined with other configuration examples shown in this specification.

[0411] <Configuration example 5> 21A, the circuit MP shown in Fig. 26 includes, as examples, transistor M1, transistor M1-2b, and transistor M1-3b, each of which has a different ratio of channel width (hereinafter referred to as W length) to channel length (hereinafter referred to as L length) in the circuit MC. Note that the circuit MP may include more transistors than just transistor M1, transistor M1-2b, and transistor M1-3b, or may not include transistor M1-3b or transistor M1-2b.

[0412] The circuit MC included in the circuit MP of FIG. 26 further includes a transistor M3-2b, a transistor M4-2b, a transistor M3-3b, and a transistor M4-3b in addition to the circuit elements included in the circuit MP of FIG. 21A.

[0413] In this specification and the like, similar to the transistor M1, unless otherwise specified, the on-state of the transistors M1-2b and M1-3b includes the case where they ultimately operate in the saturation region. That is, the gate voltage, source voltage, and drain voltage of each of the above-described transistors includes the case where they are appropriately biased to voltages within the range where they operate in the saturation region. However, one aspect of the present invention is not limited to this. To reduce the amplitude of the supplied voltage, the transistors M1-2b and M1-3b may operate in the linear region. Note that when the first data (e.g., a weighting coefficient here) is an analog value, the transistors M1-2b and M1-3b may operate in both the linear region and the saturation region depending on the magnitude of the first data (weighting coefficient), for example.

[0414] Furthermore, in this specification and the like, unless otherwise sp...

Claims

1. A first wiring and a second wiring; a switching circuit having first to fourth switches; a first circuit having first and second constant current source circuits; a second circuit, the first switch is located between the first wiring and the first circuit; the second switch is located between the second wiring and the first circuit, the third switch is located between the first wiring and the second circuit; the fourth switch is located between the second wiring and the second circuit, the first circuit has a function of supplying a current according to a weighting coefficient by using the first and second constant current source circuits; The second circuit is a semiconductor device having a function of performing arithmetic operations.

2. In claim 1, The second circuit is a semiconductor device having a function of calculating an activation function of a neural network.

3. In claim 1, A third wiring is provided, the switching circuit further includes a fifth switch and a sixth switch; the fifth switch is located between the first wiring and the third wiring, The sixth switch is located between the second wiring and the third wiring.

4. In claim 1, The first to fourth switches are transistors each having an oxide semiconductor in a channel formation region.

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