Display device

Abstract

To propose a semiconductor device having a highly reliable thin-film transistor excellent in electrical properties, and also to propose a method for manufacturing the semiconductor device without variation.SOLUTION: A display device includes a thin-film transistor of a reverse stagger type (a bottom gate structure) using an oxide semiconductor film containing In, Ga and Zn as a semiconductor layer, having a buffer layer between a semiconductor layer, and a source electrode layer and a drain electrode layer. An ohmic contact is formed through intentionally disposing the buffer layer containing In, Ga and Zn having a higher carrier concentration than that of the semiconductor layer between the source electrode layer and the drain electrode layer, and the semiconductor layer.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] One embodiment of the present invention is a thin film transistor in which an oxide semiconductor film is used for a channel formation region (hereinafter, The present invention relates to a semiconductor device having a circuit formed of a thin film transistor (TFT) and a method for manufacturing the same. For example, electro-optical devices such as liquid crystal display panels and light-emitting display devices having organic light-emitting elements are included. This relates to electronic devices installed as accessories.

[0002] In this specification, a semiconductor device is a device that can function by utilizing semiconductor characteristics. Generally speaking, electro-optical devices, semiconductor circuits, and electronic devices are all semiconductor devices. [Background technology]

[0003] In recent years, a switch consisting of a thin film transistor (TFT) has been installed for each display pixel arranged in a matrix. Active matrix display devices (liquid crystal display devices and light-emitting display devices) equipped with etching elements Active matrix display devices (electrophoretic display devices) are being actively developed. A switching element is provided for each pixel (or each dot), and the display is a simple matrix type. In comparison, it is advantageous since it can be driven at a low voltage when the pixel density is increased.

[0004] In addition, thin film transistors (TFTs) and the like are fabricated using oxide semiconductor films in the channel formation region. The technology of fabricating oxide semiconductors and applying them to electronic and optical devices is attracting attention. TFTs that use ZnO as the thin film, and InGaO 3 (ZnO) m Examples of TFTs that use A TFT formed using these oxide semiconductor films is formed on a light-transmitting substrate. Technologies for use in switching elements of image display devices are described in Patent Documents 1 and 2. It has been disclosed. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] JP 2007-123861 A [Patent Document 2] JP 2007-96055 A Summary of the Invention [Problem to be solved by the invention]

[0006] Thin film transistors using an oxide semiconductor film for a channel formation region have high operating speed and The manufacturing process must be relatively simple and sufficiently reliable.

[0007] In forming a thin film transistor, the source electrode layer and the drain electrode layer are made of low-resistance gold. In particular, when manufacturing a display device that displays a large area, the signal loss caused by the resistance of the wiring is Therefore, materials with low electrical resistance are required for wiring and electrodes. On the other hand, it is desirable to use a source electrode made of a metal material with a low electrical resistance. The thin film transistor structure has a structure in which the electrode layer and the drain electrode layer are in direct contact with the oxide semiconductor film. The contact resistance may increase if the source voltage is too high. Schottky junctions are formed at the contact surfaces between the electrode layer and the oxide semiconductor film, and between the drain electrode layer and the oxide semiconductor film. This is thought to be one of the factors.

[0008] In addition, the source electrode layer and the drain electrode layer are in direct contact with the oxide semiconductor film. This leads to a decrease in the frequency response (called f-characteristics), which makes it difficult to operate the thin film transistor at high speed. It may hinder the work.

[0009] One aspect of the present invention is an oxide containing indium (In), gallium (Ga), and zinc (Zn). In a thin film transistor using an oxide semiconductor film, the contact between the source electrode and the oxide semiconductor layer Thin-film transistor with reduced drain resistance and contact resistance between drain electrode and oxide semiconductor layer One of the objectives of the present invention is to provide a stator and a method for manufacturing the same.

[0010] In addition, the operating characteristics of a thin film transistor using an oxide semiconductor film containing In, Ga, and Zn One of the challenges is to improve the reliability of the system.

[0011] In addition, the electrical characteristics of a thin film transistor using an oxide semiconductor film containing In, Ga, and Zn In particular, in liquid crystal display devices, it is necessary to reduce the variation in individual If there is a large variation between elements, the display will be uneven due to the variation in the TFT characteristics. There is a risk that this may happen.

[0012] In addition, in a display device having a light-emitting element, the pixel electrodes are arranged so that a constant current flows through them. The on-chip TFT (which supplies current to the driver circuit or the light-emitting element arranged in the pixel) Current (I on If the variation in the brightness of the display screen is large, the brightness of the display screen may vary. As described above, one aspect of the present invention has an object to solve at least one of the above problems. do. [Means for solving the problem]

[0013] One embodiment of the present invention is a semiconductor layer using an oxide semiconductor layer containing In, Ga, and Zn. An inverted staggered type (both The present invention relates to a thin film transistor having a Tom gate structure.

[0014] In this specification, a semiconductor formed using an oxide semiconductor film containing In, Ga, and Zn is The semiconductor layer is also referred to as the "IGZO semiconductor layer."

[0015] The source and drain electrode layers must have ohmic contact with the IGZO semiconductor layer. It is necessary to reduce the contact resistance as much as possible. The contact between the semiconductor electrode and the IGZO semiconductor layer must be ohmic. It is desirable to reduce the contact resistance as much as possible.

[0016] Therefore, an IGZO semiconductor is provided between the source electrode layer, the drain electrode layer and the IGZO semiconductor layer. By intentionally providing a buffer layer with a higher carrier concentration than the Form a contact.

[0017] The buffer layer is an oxide semiconductor film having n-type conductivity and containing In, Ga, and Zn. The buffer layer may contain an impurity element that imparts n-type conductivity. , for example, magnesium, aluminum, titanium, scandium, yttrium, zirconium nium, hafnium, boron, thallium, germanium, tin, lead, etc. can be used. By including magnesium, aluminum, titanium, etc. in the buffer layer, it becomes possible to block oxygen. The oxygen concentration in the semiconductor layer can be adjusted to an optimal range by heat treatment after film formation. can be held in

[0018] This buffer layer is + These layers act as drain and source regions. Cut.

[0019] One aspect of the present invention is a semiconductor device comprising a gate electrode, an insulating film covering the gate electrode, and a gate insulating film. A IGZO semiconductor layer is formed on the gate electrode through a film, and a channel forming region of the IGZO semiconductor layer is formed on the gate electrode through a film. A channel protection layer is placed in the overlapping area, and a source electrode layer and a drain electrode layer are placed on the IGZO semiconductor layer. and a thin film transistor having a buffer layer formed between the semiconductor layer and the source electrode layer and the drain electrode layer. The carrier concentration of the buffer layer is higher than that of the IGZO semiconductor layer. The IGZO semiconductor layer is electrically connected to the source electrode layer and the drain electrode layer via the buffer layer. To be continued.

[0020] In the above-mentioned structure, a carrier concentration between the semiconductor layer and the buffer layer is higher than that of the semiconductor layer, A second buffer layer may be provided that is lower than the n-type buffer layer. - Layer as machine It works.

[0021] As the carrier concentration of an oxide semiconductor film containing In, Ga, and Zn (IGZO film) increases, As the amount of In, Ga, and Zn increases, the hole mobility also increases. The relationship between the carrier concentration and the hole mobility of the oxide semiconductor film is as shown in FIG. In one embodiment, the carrier concentration range (channel concentration) of the IGZO film suitable for the channel of the semiconductor layer is The concentration range for the channel 1) is 1×10 17 atoms / cm 3 Less than (more preferably 1 × 10 11 atoms / cm 3 (above) Carrier concentration range of IGZO film suitable for use as a buffer layer (Buffer layer concentration range 2) is 1×10 18 atoms / cm 3 or more (1×10 22 at oms / cm 3 The carrier concentration of the IGZO film used as the semiconductor layer is preferably Where applicable, the values ​​are at room temperature and with no source, drain, or gate voltages applied.

[0022] The carrier concentration range of the IGZO film for the channel exceeds the above range (channel concentration range 1). If the thin film transistor is not formed in the above-mentioned state, it may become normally on.

[0023] The carrier concentration and Hall mobility of the IGZO film can be determined by Hall effect measurements. An example of a Hall effect measuring device is the resistivity / Hall measuring system ResiTest8. 310 (manufactured by Toyo Corporation). The Test8310 changes the direction and magnitude of the magnetic field at a constant rate and synchronizes it with the sample. It is possible to measure the AC (alternating current) Hall effect by detecting only the Hall voltage that appears in the pull. The Hall voltage can be detected even for materials with small capacitance and high resistivity.

[0024] In the above structure, it is preferable that the source electrode layer and the drain electrode layer contain titanium. For example, a multilayer film made by laminating a titanium film, an aluminum film, and a titanium film has low resistance. Moreover, hillocks are unlikely to occur in the aluminum film.

[0025] Since the thin film transistor of one embodiment of the present invention has a structure in which a channel protective layer is provided, The back channel, which is the area opposite to the surface of the IGZO semiconductor layer that contacts the gate insulating film, is fabricated. Damage during etching (film loss due to plasma or etching agent during etching, oxidation, etc.) Therefore, the reliability of the semiconductor device can be improved.

[0026] According to one embodiment of a method for manufacturing a semiconductor device of the present invention, a gate electrode layer is formed over a substrate, A gate insulating film is formed on the layer, an IGZO semiconductor layer is formed on the gate insulating film, and the IGZO semiconductor layer is formed. A channel protection layer is formed in the area overlapping the channel formation area on the conductor layer, and an IGZO semiconductor layer is formed. A pair of buffer layers having n-type conductivity are formed on the substrate, and a source electrode layer and a The drain electrode layer is formed, and a pair of buffer layers having n-type conductivity are made of In, Ga, and Z. The buffer layer is formed using an oxide semiconductor layer containing n, and the carrier concentration of the buffer layer is IGZO semiconductor layer The carrier concentration of the IGZO semiconductor layer is higher than that of the source electrode layer and the drain electrode layer. Electrical connection is made via the ferroelectric layer.

[0027] In addition, the gate insulating film, the semiconductor film, and the channel protection layer are successively formed without being exposed to the atmosphere. The membrane not only increases productivity, but also prevents atmospheric components such as water vapor and impurities floating in the air. This allows the formation of a lamination interface that is free from contamination by elements or dust, which improves thin-film transistor characteristics. It is possible to reduce the variation in the

[0028] In other words, the gate insulating film and the semiconductor film are made of an oxide semiconductor containing In, Ga, and Zn. The productivity can be improved by successively depositing the insulating film that serves as the channel protection layer without exposing it to the atmosphere. In addition, there is no contamination from atmospheric components such as water vapor, or impurities or debris floating in the air. Since a lamination interface can be formed, the variation in thin film transistor characteristics can be reduced. can be done.

[0029] In this specification, continuous film formation refers to a process from a first film formation process performed by sputtering to a second film formation process performed by sputtering. During the series of processes up to the film formation step, the atmosphere in which the substrate is placed is a polluted atmosphere such as air. Always keep the device in a vacuum or inert gas atmosphere (nitrogen or rare gas atmosphere) without exposing it to air. By performing continuous film formation, the substrate to be treated is cleaned. This allows film formation while avoiding re-adhesion of moisture and the like onto the plate.

[0030] A series of processes from the first film formation process to the second film formation process are carried out in the same chamber. is within the scope of continuous film formation in this specification.

[0031] In addition, a series of processes from the first film formation process to the second film formation process are performed in different chambers. In this case, after the first film formation process is completed, the substrate is transported between chambers without being exposed to the atmosphere. The application of a second film is also considered to be within the scope of successive film formation in this specification.

[0032] Between the first and second film formation processes, a substrate transfer process, an alignment process, and a slow cooling process are performed. or a step of heating or cooling the substrate to a temperature required for the second step. However, such a method is considered to be within the scope of continuous film formation in this specification.

[0033] However, the first step involves processes that use liquids, such as cleaning, wet etching, and resist formation. If the film formation step is between the first film formation step and the second film formation step, it does not fall within the scope of continuous film formation as used in this specification. Let's say that's not the case.

[0034] In addition, the gate insulating film, the semiconductor layer, and the channel protection layer are placed in an oxygen atmosphere (or oxygen concentration of 90% or more). By forming it with rare gas (argon, etc.) 10% or less, it is possible to prevent deterioration of reliability and thinning. It is possible to reduce the shift of the film transistor characteristics to the normally-on side. The buffer layer having n-type conductivity is preferably formed in a rare gas (argon, etc.) atmosphere. It is nice.

[0035] According to one embodiment of a method for manufacturing a semiconductor device of the present invention, a gate electrode layer is formed over a substrate, A gate insulating film is formed on the layer, an IGZO semiconductor layer is formed on the gate insulating film, and the IGZO semiconductor layer is formed. A channel protection layer is formed in the area overlapping the channel formation area on the conductor layer, and an IGZO semiconductor layer is formed. A pair of buffer layers having n-type conductivity are formed on the substrate, and a source electrode layer and a The drain electrode layer is formed, and a pair of buffer layers having n-type conductivity are made of In, Ga, and Z. The buffer layer is formed using an oxide semiconductor layer containing n, and the carrier concentration of the buffer layer is IGZO semiconductor layer The carrier concentration of the IGZO semiconductor layer is higher than that of the source electrode layer and the drain electrode layer. The gate insulating film, the semiconductor layer and the channel protection layer are electrically connected through the The film is formed continuously without any gaps.

[0036] One aspect of the semiconductor device of the present invention is a gate electrode, a gate insulating film covering the gate electrode, and a gate A semiconductor layer is formed on the gate electrode via a gate insulating film, and a region overlapping with a channel forming region of the semiconductor layer is formed. A channel protection layer, a source electrode layer and a drain electrode layer on the semiconductor layer, and a semiconductor layer and a source electrode layer on the semiconductor layer. A thin film transistor having a buffer layer formed between a source electrode layer and a drain electrode layer, The semiconductor layer and the buffer layer are made of an oxide semiconductor containing indium, gallium, and zinc. The carrier concentration of the buffer layer is higher than the carrier concentration of the semiconductor layer, and the semiconductor layer is The source electrode layer and the drain electrode layer are electrically connected to each other through a contact hole.

[0037] The buffer layer of the semiconductor device contains an n-type impurity.

[0038] The carrier concentration of the semiconductor layer is 1×10 17atoms / cm 3 Less than the buffer The carrier concentration of the layer is 1×10 18 atoms / cm 3 The above is the semiconductor device.

[0039] In addition, the carrier concentration between the semiconductor layer and the buffer layer is higher than that of the semiconductor layer, and the buffer layer is A semiconductor device having a low second buffer layer.

[0040] In addition, the source electrode layer and the drain electrode layer of the semiconductor device contain titanium.

[0041] Another embodiment of the disclosed invention is a method for forming a gate electrode layer on a substrate, An insulating film is formed, a semiconductor layer is formed on the gate insulating film, and a channel forming region on the semiconductor layer is formed. A channel protection layer is formed in the overlapping region, and a pair of buffer layers having n-type conductivity are formed on the semiconductor layer. A source electrode layer and a drain electrode layer are formed on the buffer layer, and a semiconductor layer and a n The buffer layer having the conductivity type is formed using an oxide semiconductor layer containing In, Ga, and Zn. The buffer layer has a higher carrier concentration than the semiconductor layer, and the semiconductor layer, the source electrode layer, and The method for manufacturing a semiconductor device includes electrically connecting a drain electrode layer through a buffer layer.

[0042] A gate electrode layer is formed on the substrate, a gate insulating film is formed on the gate electrode layer, and a gate A semiconductor layer is formed on the insulating film, and a channel protection layer is formed in a region overlapping with a channel formation region on the semiconductor layer. A protective layer is formed, a buffer layer having an n-type conductivity is formed on the semiconductor layer, and a conductive layer is formed on the buffer layer. A source electrode layer and a drain electrode layer are formed, and the semiconductor layer and the buffer layer are made of indium and gallium. The buffer layer is formed using an oxide semiconductor layer containing aluminum and zinc. The carrier concentration of the semiconductor layer is higher than that of the semiconductor layer, and the semiconductor layer and the source electrode layer and the drain electrode layer are buffered. The gate insulating film, the semiconductor layer and the channel protection layer are electrically connected through the insulating layer. This is a method for manufacturing a semiconductor device in which a plurality of layers are formed in succession without any need for wiring.

[0043] The gate insulating film, the semiconductor layer, and the channel protection layer are formed by sputtering. A method for manufacturing a semiconductor device.

[0044] The gate insulating film, the semiconductor layer, and the channel protection layer are formed in an oxygen atmosphere. This is a method for making the device.

[0045] In addition, in the method for manufacturing a semiconductor device, the buffer layer is formed under a rare gas atmosphere.

[0046] The carrier concentration of the semiconductor layer is 1×10 17 atoms / cm 3 Less than the buffer The carrier concentration of the layer is 1×10 18 atoms / cm 3 The above-mentioned method for manufacturing a semiconductor device be.

[0047] Also, a semiconductor device formed by containing magnesium, aluminum, or titanium in the buffer layer is This is a method for making the device. Effect of the Invention

[0048] According to one aspect of the present invention, a thin film transistor having a small photocurrent, a small parasitic capacitance, and a high on-off ratio can be obtained. It is possible to obtain a thin-film transistor with good dynamic characteristics (f characteristics). Therefore, a semiconductor device having a thin film transistor with excellent electrical characteristics and high reliability can be manufactured. We can provide it. [Brief description of the drawings]

[0049] [Figure 1] 1A to 1C illustrate a semiconductor device of one embodiment of the present invention. [Diagram 2] 1A to 1C illustrate a method for manufacturing a semiconductor device of one embodiment of the present invention. [Diagram 3] 1A to 1C illustrate a method for manufacturing a semiconductor device of one embodiment of the present invention. [Figure 4] 1A to 1C illustrate a method for manufacturing a semiconductor device of one embodiment of the present invention. [Diagram 5] 1A to 1C illustrate a semiconductor device of one embodiment of the present invention. [Figure 6] 1A to 1C illustrate a semiconductor device of one embodiment of the present invention. [Figure 7] 1A to 1C illustrate a semiconductor device of one embodiment of the present invention. [Figure 8] 1A to 1C illustrate a semiconductor device of one embodiment of the present invention. [Figure 9] Schematic top view of a multi-chamber manufacturing device. [Figure 10] FIG. 1 is a block diagram illustrating a display device. [Figure 11] FIG. 2 illustrates a configuration of a signal line driver circuit. [Figure 12] 4 is a timing chart illustrating the operation of the signal line driver circuit. [Figure 13] 4 is a timing chart illustrating the operation of the signal line driver circuit. [Figure 14] FIG. 2 is a diagram illustrating a configuration of a shift register. [Figure 15] 15 is a diagram for explaining a connection configuration of the flip-flop shown in FIG. 14. [Figure 16] 1A to 1C are diagrams illustrating a liquid crystal display device to which one embodiment of the present invention is applied. [Figure 17] 1A to 1C are diagrams illustrating electronic paper to which one embodiment of the present invention is applied. [Figure 18] 1A and 1B are diagrams illustrating a light-emitting display device to which one embodiment of the present invention is applied. [Figure 19] 1A and 1B are diagrams illustrating a light-emitting display device to which one embodiment of the present invention is applied. [Figure 20] 1A and 1B are diagrams illustrating a light-emitting display device to which one embodiment of the present invention is applied. [Figure 21] 1A and 1B are diagrams illustrating a light-emitting display device to which one embodiment of the present invention is applied. [Figure 22] 1A to 1C are diagrams illustrating a liquid crystal display device to which one embodiment of the present invention is applied. [Diagram 23] 1A to 1C are diagrams illustrating a liquid crystal display device to which one embodiment of the present invention is applied. [Figure 24] 1A to 1C are diagrams illustrating electronic devices to which one embodiment of the present invention is applied. [Diagram 25] 1A to 1C are diagrams illustrating electronic devices to which one embodiment of the present invention is applied. [Figure 26] 1A to 1C are diagrams illustrating electronic devices to which one embodiment of the present invention is applied. [Figure 27] 1A to 1C are diagrams illustrating electronic devices to which one embodiment of the present invention is applied. [Figure 28] 1A to 1C are diagrams illustrating electronic devices to which one embodiment of the present invention is applied. [Figure 29] FIG. 1 is a diagram illustrating the relationship between carrier concentration and Hall mobility. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0050] Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings. The present invention is not limited to the following description, and the embodiments and aspects thereof may be modified without departing from the spirit and scope of the present invention. It will be readily understood by those skilled in the art that various modifications may be made to the embodiments and details of the present invention. The present invention should not be construed as being limited to the following description of the embodiments. In the configuration of the present invention described in the above, the same parts or parts having similar functions are denoted by the same reference numerals. are commonly used among different drawings, and repeated explanations thereof will be omitted.

[0051] (Embodiment 1) In this embodiment mode, a thin film transistor and a manufacturing process thereof will be described with reference to FIGS. He explains.

[0052] FIG. 1 shows a thin film transistor having a bottom gate structure according to the present embodiment. FIG. 1(B) is a cross-sectional view taken along line A1-A2 in FIG. 1(A). In the thin film transistor shown in FIG. 1, a gate electrode 101 is formed on a substrate 100. A gate insulating film 102 is formed on the gate electrode 101. A semiconductor layer 103 made of an amorphous oxide semiconductor serving as a channel formation region is formed on the A region overlapping with a channel formation region of the semiconductor layer 103 made of an amorphous oxide semiconductor A channel protection layer 106 is formed on the semiconductor layer 103 made of an amorphous oxide semiconductor. Buffer layers 104a and 104b are formed, and the buffer layers 104a and 104b are in contact with each other. A source electrode layer and a drain electrode layer (105a and 105b) are formed thereon.

[0053] The semiconductor layer 103 is made of an oxide semiconductor containing In, Ga, and Zn. and between the drain electrode layer (105a, 105b) and the semiconductor layer 103, By intentionally providing buffer layers 104a and 104b having a higher carrier concentration than the The .mu.m contact is formed.

[0054] The buffer layers 104a and 104b are made of an oxide containing In, Ga, and Zn and having n-type conductivity. The buffer layer may be formed of a nitride semiconductor. The buffer layer may contain an impurity element that imparts n-type conductivity. Impurity elements include, for example, magnesium, aluminum, titanium, scandium, and indium. Tritium, zirconium, hafnium, boron, thallium, germanium, tin, lead, etc. Magnesium, aluminum, titanium, etc. can be included in the buffer layer. and the like, and the semiconductor layer 103 is prevented from being damaged by heat treatment or the like after the film formation. The oxygen concentration can be kept within an optimal range.

[0055] The buffer layers 104a and 104b are + layer, which acts as a drain or source region It can also be called.

[0056] A method for manufacturing the thin film transistor shown in FIG. 1 will be described with reference to FIG. A gate electrode 101, a gate insulating film 102, a semiconductor film 133, and a channel protection layer 106 are formed on the substrate. (See Figure 2(A)).

[0057] The substrate 100 may be made of barium borosilicate glass, aluminoborosilicate glass, or aluminum. Non-alkali glass base such as nosilicate glass produced by the fusion or float process In addition to plates and ceramic substrates, plastics that have heat resistance that can withstand the processing temperatures of this manufacturing process A substrate, etc. can be used. Also, an insulating film can be provided on the surface of a metal substrate such as a stainless steel alloy. When the substrate 100 is a mother glass, the size of the substrate is Generation (320mm x 400mm), 2nd generation (400mm x 500mm), 3rd generation (55 0mm×650mm), 4th generation (680mm×880mm, or 730mm×920 mm), 5th generation (1000mm x 1200mm or 1100mm x 1250mm), 6th generation (1500mm x 1800mm), 7th generation (1900mm x 2200mm), 8th generation (2160mm x 2460mm), 9th generation (2400mm x 2800mm, 24 50mm×3050mm), 10th generation (2950mm×3400mm), etc. can be done.

[0058] An insulating film may be formed as a base film on the substrate 100. The base film may be formed by a CVD method or the like. A silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a silicon nitride film is formed by using a sputtering method or the like. The insulating film 11 may be formed of a single layer or a multilayer of silicon dioxide films.

[0059] The gate electrode 101 is made of a metal material such as aluminum, chromium, Titanium, tantalum, molybdenum, copper, etc. are applicable. A suitable example of the gate electrode is aluminum. The barrier metal is a laminated structure of sulphur or aluminum. The barrier metal is made of high melting point metals such as titanium, molybdenum, and chromium. It is preferable to provide a layer for preventing hillocks and oxidation of the silicon.

[0060] The gate electrode is formed to a thickness of 50 nm to 300 nm. By setting the thickness to m or less, it is possible to prevent breakage of the semiconductor film or wiring to be formed later. By making the thickness of the gate electrode 150 nm or more, it is possible to reduce the resistance of the gate electrode. This makes it possible to fabricate a large-area device.

[0061] Since a semiconductor film and wiring are formed on the gate electrode 101, the end portion is made to be flat to prevent disconnection. It is desirable to process it so that it has a tapered shape. Also, although not shown, the gate is removed in this process. Wiring for connection to the electrodes and capacitance wiring can also be formed at the same time.

[0062] The gate electrode 101 is formed by sputtering, CVD, plating, printing, or by using silver, gold, or The conductive layer can be formed by using a conductive nano paste such as copper. The gate electrode can be formed by discharging the film by using a method such as the steps of:

[0063] In this example, as shown in FIG. 2(A), an aluminum film and a molybdenum film are formed on the substrate as conductive films. The first photomask in this embodiment is formed by laminating the above-mentioned layers by a sputtering method. The conductive film formed on the substrate is etched using a resist mask formed using the above method to form a gate. A contact electrode 101 is formed.

[0064] In this embodiment, an example is shown in which a multilayer film in which two insulating films are stacked is used as the gate insulating film 102. The first gate insulating film 102a and the second gate insulating film 102b each have a thickness of 50 to 1000 nm. It is formed of a 150 nm silicon oxide film, silicon nitride film, silicon oxynitride film, or silicon nitride oxide film. In this embodiment, the first gate insulating film 102a is a silicon nitride film or a nitride oxide film. A silicon nitride film is formed as the second gate insulating film 102b, and a silicon oxide film or a silicon oxynitride film is formed as the second gate insulating film 102b. The gate insulating film is not formed as a two-layer structure, but is formed by forming a silicon oxide film, a silicon nitride film, and a silicon nitride film. The insulating film can be formed of a single layer of a silicon oxynitride film, a silicon nitride oxide film, or a silicon nitride oxide film. A three-layer gate insulating film may be formed.

[0065] The first gate insulating film 102a is formed using a silicon nitride film or a silicon nitride oxide film. As a result, the adhesion between the substrate and the first gate insulating film 102a is increased, and a glass substrate is used as the substrate. In this case, impurities from the substrate can be prevented from diffusing into the oxide semiconductor film. Furthermore, it is possible to prevent the gate electrode 101 from being oxidized. In other words, it is possible to prevent the film from peeling off. At the same time, the electrical characteristics of the thin film transistor to be formed later can be improved. The first gate insulating film 102a and the second gate insulating film 102b each have a thickness of 50 nm or more. This is preferable because the unevenness of the gate electrode 101 can be covered.

[0066] Here, the silicon oxynitride film is a film whose composition contains more oxygen than nitrogen. The concentration range is 55 to 65 atomic percent for oxygen, 1 to 20 atomic percent for nitrogen, and 25 to 30 atomic percent for silicon. 35 atomic % and hydrogen in the range of 0.1 to 10 atomic %. Silicon oxynitride A bare film is a film whose composition contains more nitrogen than oxygen, and the concentration range is Oxygen is 15-30 atomic %, nitrogen is 20-35 atomic %, Si is 25-35 atomic %, and hydrogen is This refers to a content in the range of 15 to 25 atomic %.

[0067] The second gate insulating film 102b in contact with the semiconductor layer 103 is made of, for example, silicon oxide. Aluminum oxide, magnesium oxide, aluminum nitride, yttrium oxide, hafnium oxide You can use nium.

[0068] The first gate insulating film 102a and the second gate insulating film 102b are formed by a CVD method or a spa The first gate insulating film 102a can be formed by a dipping method or the like. As the insulating film, a silicon nitride film is formed by plasma CVD.

[0069] In particular, the second gate insulating film 102b in contact with the semiconductor film 133 and the semiconductor film 133 are formed continuously. By forming the film continuously, atmospheric components such as water vapor and impurities floating in the air can be prevented. Since a laminated interface that is free from contamination by pure elements or dust can be formed, the characteristics of thin-film transistors can be improved. This can reduce fluctuations.

[0070] In active matrix display devices, the electrical properties of thin film transistors that make up the circuits are The characteristics are important, and these electrical characteristics determine the performance of the display device. Among the electrical characteristics of , the threshold voltage (Vth) is important. If the threshold voltage is high or negative, the circuit cannot control it. It is difficult to achieve this. In the case of a thin-film transistor, when the driving voltage is low, it does not function as a switching element. If the threshold voltage is negative, Even if the gate voltage is 0V, current flows between the source and drain electrodes. This is called normally-on. This is likely to happen.

[0071] In the case of an n-channel thin-film transistor, the channel is turned on only when a positive voltage is applied to the gate. A transistor in which a channel is formed and a drain current flows out is desirable. There are transistors in which a channel does not form unless a negative voltage is applied, and transistors in which a channel forms even under negative voltage conditions. Transistors that allow drain current to flow are not suitable for use as thin-film transistors in circuits. Therefore, a thin film transistor using an oxide semiconductor film containing In, Ga, and Zn is also available. It is desirable for the gate voltage to form a channel with a positive threshold voltage as close as possible to 0V. It is nice.

[0072] The threshold voltage of a thin film transistor is determined by the interface between the semiconductor layer, that is, the interface between the semiconductor layer and the gate insulating film. It is believed that this will have a large effect on the interfaces. Therefore, it is important to form these interfaces in a clean state. This improves the electrical characteristics of thin-film transistors while preventing the manufacturing process from becoming complicated. This makes it possible to realize a thin-film transistor that is both easy to mass-produce and has high performance.

[0073] In particular, if moisture is present at the interface between the oxide semiconductor layer and the gate insulating film, the electrical conductivity of the thin film transistor may deteriorate. problems such as deterioration of electrical characteristics, variation in threshold voltage, and tendency to become normally on By successively forming the oxide semiconductor layer and the gate insulating film, it is possible to prevent such hydrogen compounds from being generated. can be eliminated.

[0074] Therefore, the gate insulating film and the oxide semiconductor film can be formed by sputtering without exposure to the air. By continuously forming the films under reduced pressure, the interface is excellent, the leakage current is low, and the current driving capability is high. Thus, a high-power thin film transistor can be realized.

[0075] The gate insulating film and the oxide semiconductor film containing In, Ga, and Zn are grown under an oxygen atmosphere (or It is preferable to form the film using an atmosphere of 90% or more oxygen and 10% or less rare gas (such as argon).

[0076] By using the sputtering method to continuously form films in this way, the productivity is high and the reliability of the thin film interface is high. In addition, the gate insulating film and the semiconductor layer are formed in an oxygen atmosphere, and the Doing so may result in a decrease in reliability due to degradation, or the thin-film transistor may become normally on. This can reduce the risk of injury.

[0077] In addition, the insulating film that will become the channel protection layer 106 is also formed continuously following the formation of the semiconductor film. By forming the films successively, the surface of the semiconductor film that contacts the gate insulating film is opposite to the surface of the semiconductor film that contacts the gate insulating film. The opposite area, the so-called back channel, contains atmospheric components such as water vapor and impurity elements floating in the air. This allows the formation of a lamination interface that is free from contamination by metals or dust, improving the thin-film transistor characteristics. The variation can be reduced.

[0078] As a method for continuous film formation, a multi-chamber sputtering system with multiple film formation chambers is used. A sputtering system with multiple targets or a pulsed laser deposition (P LD) device can be used.

[0079] When forming silicon oxide as an insulating film, the target is silicon oxide (artificial quartz) or Single crystal silicon is used, and it is deposited by high frequency sputtering or reactive sputtering. Film formation is possible.

[0080] In this example, a multi-chamber including a single crystal silicon target and a target for a semiconductor film was used. Using a groove-type sputtering device, the second layer of gate insulating film 102 that contacts the semiconductor film is b) is a silicon oxide film, and the semiconductor film is formed and the channel protection layer is formed without exposing it to the atmosphere. A silicon oxide film having the following structure is continuously formed.

[0081] The semiconductor layer 103 is formed of an amorphous oxide semiconductor film. is a composite oxide of elements selected from indium, gallium, aluminum, zinc and tin. For example, indium oxide containing zinc oxide (IZO), In, Ga, and oxides containing Zn (IGZO) or oxides consisting of zinc oxide and tin oxide (ZTO) can be cited as an example.

[0082] In the case of an oxide consisting of indium oxide, gallium oxide, and zinc oxide, the composition ratio of the metal elements is The degree of freedom is high, and it functions as a semiconductor layer in a wide range of mixing ratios. For example, 10% by weight of zinc oxide Indium oxide containing indium oxide, gallium oxide, and zinc oxide in equal moles The ratio of metal elements in the mixed material or film is In:Ga:Zn=2.2:2.2:1.0 As an example, mention may be made of oxides present in the ratio:

[0083] The semiconductor film 133 made of an oxide semiconductor used in the semiconductor layer 103 has a thickness of 2 nm to 200 nm. The thickness of the film is preferably 20 nm to 150 nm. As the number of defects increases, the carrier concentration increases, impairing the thin-film transistor characteristics. The composition is made to suppress oxygen deficiency.

[0084] The semiconductor film 133 made of an amorphous oxide semiconductor is formed by reactive sputtering, pulse laser deposition, or the like. The film can be formed by the laser deposition method (PLD method) or the sol-gel method. In terms of ease of controlling the composition, the PLD method is preferred, while in terms of mass production, the sputtering method is preferred, as mentioned above. Here, as an example of a method for forming the semiconductor film 133, a deposition method using In, Ga, and We will explain a method using an oxide containing Zn (IGZO).

[0085] Indium oxide (In 2 O 3 ) and gallium oxide (Ga 2 O 3 ) and zinc oxide (ZnO) The two compounds were mixed in equimolar amounts and sintered into a sintered 8-inch diameter target. The board was placed at 0 mm and a DC (Direct Current ) sputtering to form a semiconductor film 133. The chamber pressure is 0.4 Pa, and the gas The composition ratio is Ar / O 2 The film is formed at 50 nm under the condition of 10 / 5 sccm. The temperature was set higher than the deposition conditions for transparent conductive films such as indium tin oxide (ITO), and the deposition atmosphere was It is desirable to control the oxygen concentration in the air to suppress oxygen deficiency. The use of a power source is preferable because it reduces dust and makes the film thickness distribution of the semiconductor layer uniform.

[0086] Note that plasma treatment may be performed on the semiconductor layer 103. By performing the plasma treatment, The damage caused by etching of the semiconductor layer 103 can be repaired. 2 , N 2 O, preferably N containing oxygen 2 It is preferable to carry out the reaction under an atmosphere of He or Ar. In the above atmosphere, Cl 2 , C.F. 4 The plasma treatment may be performed in an atmosphere containing It is preferable to carry out the measurement without bias.

[0087] In this embodiment, a single crystal silicon target is used together with the target for the oxide semiconductor film. The second gate formed in the previous process was deposited on the substrate using a multi-chamber sputtering device equipped with a A semiconductor film is formed on the insulating film 102b without exposing the insulating film 102b to the atmosphere. The semiconductor film is then not exposed to the atmosphere, and in the next process, a channel protection layer 106 is formed on the semiconductor film. An insulating film is formed.

[0088] As shown in FIG. 2A, the channel protection layer 106 overlaps with the channel formation region of the semiconductor layer 103. The insulating film that functions as the channel protection layer 106 is made of an inorganic material ( Silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, etc. can be used. Photosensitive or non-photosensitive organic materials (organic resin materials) (polyimide, acrylic, polyamide , polyimide amide, resist, benzocyclobutene, etc.), or a film made of multiple types Alternatively, a laminate of these films may be used. Siloxane may also be used. .

[0089] The insulating film that becomes the channel protection layer 106 is formed by a vapor phase growth method such as a plasma CVD method or a thermal CVD method. The film can be formed by a wet coating method such as spin coating. In addition, a droplet ejection method and a printing method (such as screen printing or offset printing) can be used. Alternatively, the pattern may be selectively formed by a method such as forming a pattern ...

[0090] In this example, a multi-target system was used that had a single crystal silicon target and a target for an oxide semiconductor film. Using a chamber-type sputtering device, the oxide semiconductor formed in the previous process was deposited on the A silicon oxide film that becomes the channel protection layer 106 is formed without exposing the semiconductor film 133 to the atmosphere. do.

[0091] Next, a resist mask formed using the second photomask in this embodiment is used. The silicon oxide film formed on the semiconductor film 133 is selectively etched to obtain a semiconductor film as shown in FIG. Next, a channel protection layer 106 is formed.

[0092] Next, a resist mask formed using the third photomask in this embodiment is used. The semiconductor film 133 made of an oxide semiconductor formed on the gate insulating film is etched to form a semiconductor The conductor layer 103 is formed.

[0093] As a method for etching an oxide (IGZO) film containing In, Ga, and Zn, Wet etching can be used. Organic acids such as citric acid and oxalic acid are used as etchants. For example, a 50 nm thick oxide film containing In, Ga, and Zn (IG The ZO film can be etched in 150 seconds using ITO07N (manufactured by Kanto Chemical Co., Ltd.).

[0094] The pair of buffer layers 104a and 104b formed on the amorphous oxide semiconductor film are The insulating film is formed using an oxide semiconductor film having a conductivity type containing In, Ga, and Zn.

[0095] In addition, a different metal is added to an oxide semiconductor film having n-type conductivity and containing In, Ga, and Zn. It can also be used after doping. Dopants include magnesium, aluminum, , titanium, scandium, yttrium, zirconium, hafnium, boron, thallium, Germanium, tin, lead, etc. Magnesium, aluminum, titanium If the buffer layer contains such a material, it will have an oxygen blocking effect, and the heat treatment after film formation will By these means, the oxygen concentration in the semiconductor layer can be maintained within an optimum range.

[0096] In one embodiment of the present invention, the carrier concentration range of the semiconductor layer (channel concentration range 1) is 1× 10 17 atoms / cm 3 Less than (more preferably 1 × 10 11 atoms / cm 3 End ), and the carrier concentration range of the IGZO film suitable for the buffer layer (buffer layer concentration range 2) is , 1×10 18 atoms / cm 3 or more (1×10 22 atoms / cm 3 (hereinafter) It is also preferable that a layer having a higher carrier concentration than the semiconductor layer is provided between the semiconductor layer and the buffer layer. The carrier concentration is lower than that of the buffer layer. - A second buffer layer may be provided to act as a stomach.

[0097] The carrier concentration of the buffer layers 104a and 104b is an oxide containing In, Ga, and Zn (I Since it has higher conductivity than the semiconductor layer made of GZO, the source electrode layer and the drain electrode The contact resistance is reduced compared to when the layers (105a, 105b) and the semiconductor layer 103 are directly bonded to each other. In addition, the source electrode layer and the drain electrode layer (105a, 105b) and the semiconductor By sandwiching the buffer layers 104a and 104b at the bonding interface of the dielectric layer 103, the This can reduce the electric field that occurs during the measurement.

[0098] In order to ensure that the buffer layers 104a and 104b cover the semiconductor layer 103, As shown in FIG. 2B, the buffer layer is patterned so as to overlap a part of the channel protection layer 106. You may do so.

[0099] The buffer layers 104a and 104b are made of In, Ga, and Zn having n-type conductivity. The oxide semiconductor film is preferably formed to a thickness of 2 nm to 100 nm.

[0100] The buffer layers 104a and 104b are made of In, Ga, and Zn having n-type conductivity. The oxide semiconductor film is formed by sputtering or pulsed laser deposition (PLD). It is possible.

[0101] In this embodiment, a resist mask is formed using the fourth photomask. The semiconductor layer 103 and the channel protection layer 106 are formed on the semiconductor layer 103 and have an n-type conductivity. Dry etching or wet etching of an oxide semiconductor film containing In, Ga, and Zn Then, buffer layers 104a and 104b are formed by etching.

[0102] The source electrode layer and the drain electrode layer (105a, 105b) are made of a conductive film, and the gate electrode The same materials as 101 can be used, but in particular the layers in contact with the buffer layers 104a and 104b. The layer is preferably a titanium film. Specific examples of the conductive film include a titanium film alone, or is a laminated film of a titanium film and an aluminum film, or a laminated film of a titanium film, an aluminum film, and a titanium film Alternatively, a three-layer structure may be formed by stacking these in order.

[0103] Here, as shown in FIG. 2(C), a channel is formed on the buffer layers 104a and 104b and the channel protection layer. A three-layer laminate film consisting of a tantalum film, an aluminum film, and a titanium film is formed by sputtering. A resist mask formed using the fifth photomask of this embodiment is used. The conductive film formed on the channel protection layer 106 is etched and separated to form a source electrode layer and a drain electrode layer. The rain electrode layers (105a, 105b) are formed as shown in FIG. 2(D). The three-layer conductive film, which is made by stacking an aluminum film and a titanium film in order, is heated with hydrogen peroxide or Etching can be performed using hot hydrochloric acid as an etchant.

[0104] In this embodiment, the buffer layers 104a and 104b are formed, and the source electrode layer and In order to separately form the buffer layer 104a and the drain electrode layer (105a, 105b), , 104b and the overlap at the edge of the source electrode layer and the drain electrode layer (105a, 105b) The length of the spool can be easily controlled.

[0105] The oxide containing In, Ga, and Zn (IGZO) described in this embodiment is used as the semiconductor layer 10. The thin film transistor used in Example 3 has characteristics that change when the semiconductor layer 103 is heated. Specifically, the on-current increases and the variation in transistor characteristics decreases. .

[0106] The heat treatment temperature of the semiconductor layer 103 is preferably in the range of 300° C. to 400° C. The heat treatment is performed at 350° C. for one hour. The heat treatment may be performed at any time after the formation of the semiconductor layer 103. For example, after the insulating film that will become the semiconductor layer 103 and the channel protection layer 106 is continuously formed, Alternatively, the channel protection layer 106 may be patterned and formed, or the buffer layer 107 may be formed. 104a and 104b are oxide semiconductors containing In, Ga, and Zn and having n-type conductivity. Alternatively, the source electrode layer and the drain electrode layer (105a, 10 5b) may be formed after the conductive film is formed, or after the sealing film of the thin film transistor is formed. Alternatively, the thermal curing process of the flattening film formed on the thin film transistor may be performed by heating the semiconductor layer 103. This may also be used for processing.

[0107] According to the above description, the semiconductor layer 103 made of an amorphous oxide semiconductor shown in FIG. The panel protection layer 106, the buffer layers 104a, 104b, and the source and drain electrode layers (105a, 105b) is formed.

[0108] The thin film transistor according to one embodiment of the present invention includes a gate electrode, a gate insulating film, a semiconductor layer (In, G a, and an oxide semiconductor layer containing Zn), a buffer layer, a channel protection layer, a source electrode layer, and The drain electrode layer has a laminated structure. By using the silicon layer, the thickness of the semiconductor layer can be kept thin and the parasitic capacitance can be suppressed. It is possible.

[0109] The thin film transistor of one embodiment of the present invention has a structure in which a channel protective layer 106 is provided. Therefore, the region on the opposite side to the surface of the oxide semiconductor film that is in contact with the gate insulating film 102b, that is, the so-called back Damage to the channel during the process (film loss due to plasma or etching agent during etching, This can protect the thin film transistor from oxidation and other damages. This can be done.

[0110] The channel protection layer 106 is etched in the etching process for forming the semiconductor layer 103. Since it functions as a channel stopper, it can also be called a channel stopper layer.

[0111] In this embodiment, the source electrode layer and the drain electrode layer ( The ends of the buffer layers 104a, 104b are recessed from the ends of the buffer layers 104a, 104b. Since they are located apart from each other, the ripple between the source electrode layer and the drain electrode layer (105a, 105b) This can prevent leakage currents and short circuits.

[0112] Therefore, by applying one embodiment of the present invention, the photocurrent is small, the parasitic capacitance is small, and the on This allows the production of thin-film transistors with a high on-off ratio and excellent dynamic characteristics. Therefore, it is possible to fabricate a semiconductor device having a thin film transistor with high electrical characteristics and high reliability. A conductor device can be provided.

[0113] (Embodiment 2) In this embodiment, an n-type In, Ga, FIG. 1 shows the structure of a thin film transistor having a buffer layer made of an oxide semiconductor containing Zn. 3 will be used for the explanation. In this embodiment, the same parts as those in the first embodiment will be The same reference numerals are used and detailed explanations are omitted.

[0114] Through the same process as in the first embodiment, the channel protection layer 106 is semi-transparent as shown in FIG. An insulating film is formed in the region overlapping the channel forming region of the conductor layer 103. In the etching process of the layer 106, the surface of the semiconductor layer 103 that is bonded to the buffer layer 104 The oxide semiconductor layer and the buffer layer 104 may be etched as shown in FIG. By etching the bonding surface, a better bond with the buffer layer 104 can be obtained.

[0115] In other words, the gate electrode 101 on the semiconductor film 133 is formed through the same process as in the first embodiment. A channel protection layer 106 is formed in the region overlapping the channel protection layer 106. In this step, the surface of the semiconductor film 133 may be etched as shown in FIG. The surface of the semiconductor film 133 in the opening of the channel protection layer 106 is etched. As a result, the surface is covered with In, Ga, and SiO2, which have n-type conductivity and serve as a buffer layer to be subsequently formed. In this embodiment, the oxide semiconductor film 134 can be bonded well to the oxide semiconductor film 134 containing Zn. The explanation will be continued based on the embodiment in FIG.

[0116] In this embodiment, an oxide containing In, Ga, and Zn and having n-type conductivity is used as the buffer layer. The compound semiconductor film 134 is formed as shown in FIG. The oxide semiconductor film 134 containing In, Ga, and Zn was grown by the method described in Embodiment 1. Similarly, after forming the film, the source electrode layer and the drain electrode layer are formed without patterning as shown in FIG. 3(C). A conductive film 105 that will become electrode layers (105a, 105b) is laminated.

[0117] The conductive film 105 is formed in the same manner as in the first embodiment. For example, a three-layer laminated film is formed by sputtering as a source electrode layer or a drain electrode layer. Titanium films as the electrode layers (105a1, 105b1), (105a2, 105b2) For example, an aluminum film can be used as the first electrode 105a and a titanium film can be used as the second electrode 105b. .

[0118] In other words, the first conductive film is titanium, the second conductive film is aluminum, and the third conductive film is aluminum. The conductive film 105 is made of titanium. 105a1, 105b1) and a second conductive layer (105a2, 105 b2) and a third conductive layer (105a3, 105b3) made of titanium. A pole layer and a drain electrode layer (105a, 105b) are formed.

[0119] Next, a resist mask formed using the fourth photomask of this embodiment is used. Then, the conductive film 105 is etched.

[0120] First, the source electrode and the drain electrode (105a1, 105b1) are The source electrode layer and the drain electrode layer (105a2, 105a3, 105 b2, 105b3) are etched by wet etching. Using the same mask as in the etching, the source electrode layer or the drain electrode layer (105a1, 1 05b1), the buffer layers 104a and 104b and the semiconductor layer 103 are removed by dry etching. Therefore, as shown in FIG. 3(D), the source electrode layer 105a1 is The drain electrode layer 105b1 is connected to the end of the buffer layer 104b. The source electrode layer and the drain electrode layer (105a2, 105a3), The source electrode layer or drain electrode layer (105b2, 105b3) is a source electrode layer or a drain electrode layer. The ends are recessed from the first electrode layers (105a1, 105b1).

[0121] In other words, first, the titanium film, which is the third conductive film, is etched to form the third conductive layer (10 5a3, 105b3), and then a titanium film, which is a first conductive film, is formed as an etching stopper. The second conductive layer (105a) is then etched away from the aluminum film. 2, 105b2) are formed. Furthermore, the same resist mask as that used in the wet etching is used. The first conductive film was a titanium film and a second conductive film containing In, Ga, and Zn having n-type conductivity. The oxide semiconductor film 134 is dry-etched to form the third conductive layer (105a1, 105b 1) and buffer layers (104a, 104b) are formed. After the formation of the first and drain electrodes (105a, 105b), the first conductive layer (105a1, 105b1) coincides with the ends of the buffer layers (104a, 104b) and is connected to the second conductive layer (1 The first conductive layer (105a1, 105b1) and the second conductive layer (105a2, 105b2) are the first conductive layer. The end portion is recessed from (105a1, 105b1). The cross-sectional view at this stage is shown in FIG. As shown in.

[0122] In this manner, the conductive film used for the source electrode layer and the drain electrode layer, the buffer layer, and the semiconductor If the layer has a low selectivity in the etching process, it functions as an etching stopper. To this end, a conductive film having different etching conditions may be stacked and etching steps may be performed a number of times.

[0123] In addition, the formed semiconductor layer 103 is subjected to heat treatment in a manner similar to that in Embodiment Mode 1.

[0124] According to this embodiment, the buffer layers 104a and 104b, the source electrode layer, and the drain electrode layer Resist masks in which the patterns of (105a, 105b) are formed using the same photomask As a result, the number of photomasks used can be reduced compared to the first embodiment. By combining multiple processes into one, the number of processes can be reduced and the yield can be improved. , the manufacturing time can be shortened.

[0125] (Embodiment 3) In this embodiment, a buffer layer having a structure different from that in the first and second embodiments is used. The structure of the thin film transistor will be described with reference to FIG. Here, the same reference numerals are used for the same components as in the first embodiment, and detailed explanations will be omitted.

[0126] Through the same process as in the second embodiment, an oxide containing In, Ga, and Zn that will become the semiconductor layer 103 is formed. A channel protection layer 106 is formed on the IGZO semiconductor film 133 as shown in FIG. do.

[0127] In this embodiment, the semiconductor film 133 is selectively etched to form the semiconductor layer 103. The buffer layers 104a and 104b are formed on the semiconductor film 133. An oxide semiconductor film containing In, Ga, and Zn is formed by a method similar to that in Embodiment 2. A resist mask formed using the third photomask of this embodiment is used. As shown in FIG. 4B, buffer layers 104a and 104b and a semiconductor layer 103 are formed.

[0128] The source electrode layer and the drain electrode layer (105a, 105b) are made of a conductive film. In this example, the buffer layers 104a and 104b and the channel protection layer 10 A three-layer laminate consisting of a titanium film, an aluminum film, and a titanium film is sputtered on the 6 as a conductive film. Next, a laser beam formed using the fourth photomask in this embodiment is formed. The conductive film is etched and removed using a resist mask, and the source electrode layer is left as shown in Figure 4(D). and drain electrode layers (105a, 105b). FIG. 4(D) is a plan view. 4(C) is a cross-sectional view taken along line A1-A2 in FIG. 4(D).

[0129] In addition, the formed semiconductor layer 103 is subjected to heat treatment in a manner similar to that in Embodiment Mode 1.

[0130] According to this embodiment, the buffer layers 104a and 104b and the semiconductor layer 103 are patterned. Since these processes are performed simultaneously, the number of photomasks used can be reduced compared to the first embodiment. By combining multiple processes into one, the number of processes is reduced, yield is improved, The manufacturing time can be shortened.

[0131] (Embodiment 4) In this embodiment, a thin film transistor having a plurality of gate electrodes and a buffer layer electrically connected to each other is used. The transistor will be described with reference to Figs. 5 to 7. Fig. 5(A) is a plan view, and Fig. FIG. 6B is a cross-sectional view taken along the line A1-A2 in FIG. 5A. FIG. 6A is a plan view. FIG. 6B is a cross-sectional view taken along the line A1-A2 in FIG. 6A. 7(B) is a cross-sectional view taken along line A1-A2 in FIG. In this embodiment, the same reference numerals are used for the same components as those in the first embodiment, and detailed description is omitted. The explanation will be omitted.

[0132] In this embodiment, a structure in which two channel formation regions are connected is taken up. However, the present invention is not limited to this, and may be implemented using a triple gate structure in which three channel forming regions are connected. This is called a multi-gate structure (a structure having two or more channel forming regions connected in series). That's fine.

[0133] In the thin film transistor of this embodiment, two channel formation regions are connected to each other. The channel forming region is connected only by the buffer layer 104c (FIG. 5). 4c and a conductive layer 105c (FIG. 6), and 7, in which the connection is made by the dielectric layer 103, the buffer layer 104c, or the conductive layer 105c. The two first gate electrodes 101a and the second gate electrode 101b of the photomask of the corresponding layer are By changing the portion sandwiched between 1b and 1c, these thin film transistors can be made to have the same structure as in the first embodiment. It can be formed by a variety of methods.

[0134] Such a multi-gate structure is extremely effective in reducing the off-current value.

[0135] (Embodiment 5) In this embodiment, a thin film transistor having a buffer layer with a structure different from that in the above-mentioned embodiments 1 to 4 is used. The structure of the thin film transistor of this embodiment will be described with reference to FIG. Since the method is similar to that described in the first embodiment except for the buffer layer, the buffer layer Other detailed explanations will be omitted.

[0136] The buffer layer of this embodiment is composed of two layers, a first buffer layer and a second buffer layer. The buffer layers 104a and 104b in contact with the source electrode and the drain electrode are called first buffer layers. The second buffer layer is sandwiched between the first buffer layers 104a and 104b and the semiconductor layer 103. The layers are referred to as second buffer layers 114a and 114b, respectively.

[0137] In other words, the buffer layer of this embodiment is connected to one of the source electrode and the drain electrode. A first buffer layer 104a in contact with the other of the source electrode and the drain electrode. The buffer layer 104b and the second buffer layer sandwiched between the first buffer layer 104a and the semiconductor layer 103. A second buffer layer 114a is sandwiched between the first buffer layer 104b and the semiconductor layer 103. The first layer 114b is made of a ferroelectric material.

[0138] The first buffer layers 104a, 104b and the second buffer layers 114a, 114b together The gate electrode 11 is formed of an oxide semiconductor having n-type conductivity containing In, Ga, and Zn.

[0139] In addition, a different metal was doped onto an oxide semiconductor containing n-type In, Ga, and Zn. Dopants include magnesium, aluminum, Titanium, scandium, yttrium, zirconium, hafnium, boron, thallium, germanium Examples of doping include ruthenium, tin, and lead. The concentration of a can be increased.

[0140] As an example of a method for forming a buffer layer, an oxide containing In, Ga, and Zn (IGZO) is used. The sintered target and a compound target containing a dopant that gives n-type conductivity were simultaneously A co-sputtering method can also be used. According to the study, the compound containing In, Ga, and Zn oxide (IGZO) and dopants A mixed layer can be produced, and the first buffer layer 104a, 104b and the second buffer layer 104b can be formed. The layers 114a and 114b can be made separately.

[0141] The first buffer layers 104a, 104b and the second buffer layers 114a, 114b are The rear concentration is higher than that of the semiconductor layer 103 made of an oxide (IGZO) containing In, Ga, and Zn. The first buffer layers 104a and 104b have a higher conductivity than the second buffer layer 1. The composition is selected so that the carrier concentration is higher than that of the buffer layer 104a and 114b. a, 104b is n + layer, whereas the second buffer layer (buffer layer 114 a, 114b) is n - It functions as a layer.

[0142] The carrier concentration range of the semiconductor layer 103 (channel concentration range 1) is 1×10 17 atoms / cm 3 Less than (more preferably 1 × 10 11 atoms / cm 3 above), n + Layer as machine The carrier concentration range of the IGZO film suitable for the buffer layers 104a and 104b that can function as the buffer layers is The concentration range of the fa layer is 1×10 18 atoms / cm 3 More preferably, 1×1 0 22 atoms / cm 3 It is preferable to use the following:

[0143] From the semiconductor layer 103 to the source electrode layer and the drain electrode layer (105a, 105b) By providing a gradient so that the carrier concentration increases, the semiconductor layer 103 and the source electrode layer and the contact resistance between the drain electrode layer (105a, 105b) and the gate electrode layer (105a, 105b) can be reduced.

[0144] Also, from the semiconductor layer 103 to the source electrode layer and the drain electrode layer (105a, 105b) By inserting a buffer layer with a gradient in which the carrier concentration increases at the junction interface, The electric field concentrated at the joining interface can be reduced.

[0145] A thin film transistor having a stacked buffer layer according to one embodiment of the present invention has a low off-state current. A semiconductor device including such a thin film transistor has high electrical characteristics and high reliability. It is possible.

[0146] This embodiment mode can be implemented in appropriate combination with other embodiment modes.

[0147] (Embodiment 6) Here, at least the gate insulating film and the oxide semiconductor film are stacked continuously without being exposed to the air. The following describes an example of fabricating an inverted staggered thin film transistor. The steps up to the step of performing the film deposition are shown, and the subsequent steps are in accordance with any one of the first to fifth embodiments. A thin film transistor can be fabricated in this manner.

[0148] When performing continuous film formation without exposure to the atmosphere, a multi-chamber manufacturing method as shown in Figure 9 is used. It is preferable to use an apparatus.

[0149] The manufacturing apparatus is provided at its center with a transport mechanism (typically a transport robot 81) for transporting substrates. The transfer chamber 80 is provided with a transfer chamber 81 for transferring a plurality of substrates to and from the transfer chamber. A cassette chamber 82 for setting a cassette case to be stored is connected.

[0150] In addition, a plurality of processing chambers are connected to the transfer chamber via gate valves 84 to 88. Here, an example is shown in which five processing chambers are connected to a transfer chamber 80 having a hexagonal top surface shape. By changing the shape of the top surface of the transfer chamber, the number of process chambers that can be connected can be changed. For example, If it is shaped like a rectangle, three treatment chambers can be connected, and if it is shaped like an octagon, seven treatment chambers can be connected.

[0151] At least one of the five processing chambers is a sputtering chamber for sputtering. The sputtering chamber is provided with at least a sputtering target, A power application mechanism for sputtering the target, a gas introduction means, and a substrate holding means for holding the substrate in a predetermined position are also included. The sputtering chamber is also equipped with a substrate holder. The sputtering chamber is provided with a pressure control means for controlling the pressure within the chamber.

[0152] There are two types of sputtering: RF sputtering, which uses a high-frequency power source for the sputtering power supply, and DC sputtering. There is also the pulsed DC sputtering method, which applies a pulsed bias. The DC sputtering method is mainly used for depositing insulating films, while the DC sputtering method is mainly used for depositing metal films. It is used in.

[0153] There are also multi-target sputtering devices that can accommodate multiple targets of different materials. The equipment can deposit layers of different materials in the same chamber, or multiple types of films in the same chamber. It is also possible to form a film by discharging two or more materials at the same time.

[0154] Also, a sputtering apparatus using a magnetron sputtering method equipped with a magnet mechanism inside the chamber and ECR sputtering using plasma generated by microwaves without glow discharge. There is a sputtering apparatus that uses this method.

[0155] The sputtering chamber is suitably used for the various sputtering methods described above. In addition, the film formation method involves chemically reacting the target material with the sputtering gas components during film formation. The reactive sputtering method for forming these compound thin films and the application of voltage to the substrate during film formation are also used. There is also a bias sputtering method.

[0156] In addition, one of the five processing chambers is used for preheating the substrate before sputtering. a heating chamber for performing sputtering, a cooling chamber for cooling the substrate after sputtering, or This chamber performs plasma processing.

[0157] Next, an example of the operation of the manufacturing apparatus will be described.

[0158] A substrate cassette containing substrates 94 with the film-forming surface facing downward is set in the cassette chamber 82. The cassette chamber 82 is then placed in a decompressed state by a vacuum exhaust means provided in the cassette chamber 82. The inside of each processing chamber and the transfer chamber 80 is previously depressurized by a vacuum exhaust means provided therein. This prevents the substrate from coming into contact with the atmosphere while being transported between the processing chambers. It is possible to maintain a clean state without

[0159] The substrate 94 with the film-forming surface facing downward is provided with at least a gate electrode. For example, a silicon nitride film or a nitriding oxide film obtained by the plasma CVD method is used between the substrate and the gate electrode. A base insulating film such as a silicon nitride film may be provided. When a silicon substrate is used, the insulating film underneath is designed to prevent mobile ions such as sodium from the substrate from It penetrates into the body region and has the effect of suppressing changes in the electrical characteristics of the TFT.

[0160] Here, a silicon nitride film that covers the gate electrode is formed by plasma CVD, and the first gate layer is The silicon nitride film formed by the plasma CVD method is dense. By using it as the first gate insulating film, it is possible to prevent pinholes from occurring. In this example, the gate insulating film is a laminated film, but is not limited thereto. The above laminated layers may be used.

[0161] Next, the gate valve 83 is opened and the first substrate 94 is loaded into the cassette by the transfer robot 81. Then, the gate valve 84 is opened and the wafer is transferred into the first processing chamber 89. In the first processing chamber 89, the substrate is heated by a heater or a lamp heater. In particular, if the gate insulating film contains moisture, it can damage the TFT. Heating before sputtering is effective because the thermal properties may change. If the moisture is sufficiently removed at the stage when the substrate is set in the chamber 82, this heat treatment can be performed without It is not necessary.

[0162] In addition, a plasma processing means is provided in the first processing chamber 89, and a plasma is applied to the surface of the first gate insulating film. In addition, a heating means may be provided in the cassette chamber 82 to heat the cassette chamber 82. Heating may be performed to remove the residue.

[0163] Next, the gate valve 84 is opened and the substrate is transported to the transport chamber 80 by the transport robot 81. The gate valve 85 is opened, the substrate is transferred into the second processing chamber 90, and the gate valve 85 is closed.

[0164] Here, the second processing chamber 90 is a sputtering chamber using an RF magnetron sputtering method. In the second processing chamber 90, a silicon oxide film (SiO x film (x>0) is deposited. In addition to the silicon oxide film, Aluminum oxide film (Al 2 O 3 film), magnesium oxide film (MgOx film (x>0)), Aluminum nitride film (AlNx film (x>0)), yttrium oxide film (YOx film (x>0 )) etc. can be used.

[0165] In addition, small amounts of halogen elements, such as fluorine or chlorine, are added to the second-layer gate insulating film. Alternatively, mobile ions such as sodium may be immobilized. A gas containing a halogen element is introduced into the chamber to perform sputtering. When introducing a gas containing such a substance, it is necessary to provide a detoxification device in the exhaust means of the chamber. The concentration of halogen elements contained in the insulating film was measured using a SIMS (secondary ion mass spectrometer). The concentration peak obtained by analysis is 1×10 15 cm -3 More than 1×10 20 cm -3 below It is preferable to keep it within the range.

[0166] To obtain a SiOx film (x>0), artificial quartz is used as the target and rare gas, typically The sputtering method uses argon, and the target is single crystal silicon, and oxygen gas is used. The reactive sputtering method can be used to obtain a SiOx film (x>0) by chemically reacting with In this case, in order to incorporate as much oxygen as possible into the SiOx film (x>0), the target Artificial quartz was used as the substrate, and the atmosphere was oxygen only, or oxygen was 90% or more and Ar was Sputtering is performed in an atmosphere of 10% or less to form an oxygen-rich SiOx film (x>0). do.

[0167] After the SiOx film (x>0) is formed, the gate valve 85 is opened and the substrate is transported without being exposed to the air. The substrate is transferred to the transfer chamber 80 by the robot 81, and the gate valve 86 is opened to enter the third processing chamber. The substrate is transported into 91, and the gate valve 86 is closed.

[0168] Here, the third processing chamber 91 is a sputtering chamber using a DC magnetron sputtering method. In the third processing chamber 91, a metal oxide layer (IGZO film) is formed as a semiconductor layer. The oxide semiconductor terpene containing indium (In), gallium (Ga), and zinc (Zn) Using a get, the film can be formed under a rare gas atmosphere or an oxygen atmosphere. In order to incorporate as much oxygen as possible into the IGZO film, the targets are In, Ga, and and an oxide semiconductor containing Zn, in an atmosphere of oxygen only or an atmosphere of oxygen of 90% or more, The sputtering was performed by pulse DC sputtering in an atmosphere containing 10% Ar or less, and oxygen was An extra IGZO film is formed.

[0169] In this way, the oxygen-rich SiOx film (x>0) and the oxygen-rich IG By continuously depositing the ZO film, the interface between the films containing excess oxygen is stabilized, and the TF If the substrate is exposed to the air before the IGZO film is deposited, Moisture and other substances can adhere to the interface, adversely affecting the interface condition, causing variations in threshold voltages and deterioration of electrical characteristics. This can cause problems such as normally-on TFTs. By continuously depositing the film without exposure to the air, hydrogen compounds are prevented from existing at the interface. Therefore, by forming the films continuously, the variation in the threshold voltage can be eliminated. It reduces adhesion, prevents deterioration of electrical characteristics, and prevents the TFT from shifting to the normally-on side. The shift can be reduced, and preferably eliminated.

[0170] In addition, a synthetic quartz target and In, Ga, and Zn-containing oxide semiconductor targets were placed, and stacked in sequence using a shutter. It is also possible to perform lamination in the same chamber by successively depositing films using the shutter. The shutter is placed between the target and the substrate, and the target that is to be deposited is opened and the deposition is performed. The advantage of stacking in the same chamber is that This reduces the number of chambers used and reduces the amount of paper required to transport substrates between different chambers. The advantage is that it is possible to prevent tickles and the like from adhering to the substrate.

[0171] Next, the gate valve 86 is opened and the substrate is transferred by the transfer robot 81 without being exposed to the atmosphere. The substrate is transferred to the transfer chamber 80, the gate valve 87 is opened, the substrate is transferred to the fourth processing chamber 92, and the gate Close valve 87.

[0172] Here, the fourth processing chamber 92 is a sputtering chamber using an RF magnetron sputtering method. In the fourth processing chamber 92, a silicon oxide film ( A SiOx film (x>0) is deposited. A silicon oxide film is also deposited as a channel protection layer. In addition, aluminum oxide film (Al 2 O 3 film), magnesium oxide film (MgOx film (x>0 )), aluminum nitride film (AlNx film (x>0)), yttrium oxide film (YOx film ( x>0) etc. can be used.

[0173] In addition, a small amount of halogen elements, such as fluorine or chlorine, is added to the channel protection layer to form a nano-layer. Mobile ions such as thorium may be immobilized. Sputtering is performed by introducing a gas containing halogen elements. When introducing gas, it is necessary to provide a decontamination device to the exhaust means of the chamber. The concentration of halogen elements contained in the protective layer is analyzed using SIMS (secondary ion mass spectrometry). The concentration peak obtained by 15 cm -3 More than 1×10 20 cm -3 The following range It is preferable to set the temperature within 100° C.

[0174] When obtaining a SiOx film (x>0) as a channel protection layer, artificial quartz is used as the target. The sputtering method uses a rare gas, typically argon, and a single crystal silicon target. Reactive sputtering is a process in which a SiOx film (x>0) is obtained by chemically reacting the gas with oxygen. In this method, oxygen is contained in the SiOx film (x>0) as much as possible. In order to achieve this, artificial quartz was used as the target and the reaction was carried out under an atmosphere of only oxygen or an atmosphere of 90% oxygen. % or more and Ar or less, and the SiO Form an x ​​film (x>0).

[0175] In this way, the oxygen-rich SiOx film (x>0) and the oxygen-rich IG By successively depositing the ZO film and the oxygen-rich channel protection layer, all three layers are oxygen-rich. Because it is a film, the interface state is more stable, which improves the reliability of the TFT. If the substrate is exposed to the air before or after the film formation, moisture may adhere to the substrate, adversely affecting the interface condition. Symptoms such as variations in threshold values, deterioration of electrical characteristics, and normally-on TFTs Moisture is a hydrogen compound and can be used for continuous film formation without contact with the air. This makes it possible to eliminate the presence of hydrogen compounds at the interface of the IGZO film. Therefore, by forming the three layers in succession, the variation in threshold voltage and the deterioration of electrical characteristics can be reduced. It is also important to prevent the TFT from shifting to the normally-on side, and preferably to prevent the shift from occurring. It can be made.

[0176] In addition, a synthetic quartz target and In, Ga, and Zn-containing oxide semiconductor targets were placed, and stacked in sequence using a shutter. It is also possible to deposit three layers in succession in the same chamber. The advantage of stacking in a chamber is that it reduces the number of chambers used and allows for different It is advantageous in that it can prevent particles from adhering to the substrate while it is being transported between chambers. be.

[0177] The above steps are repeated to perform film formation on the substrates in the cassette case, and multiple substrates are processed. After completion, the vacuum in the cassette chamber is released to the atmosphere, and the substrates and cassette are removed.

[0178] Next, the channel protection layer is selectively etched to pattern the IGZO film. Then, the IGZO film is selectively etched. Alternatively, the etching may be performed in two separate steps, each of which may be selectively etched. At this stage, the surface of the gate insulating film is exposed in the area where the IGZO film has been removed.

[0179] Next, the channel protection layer is further formed at a position overlapping with the gate electrode, i.e., the channel shape of the IGZO film. The etching is performed leaving only the area that overlaps with the position of the channel protection layer. The etching conditions are such that the etching rate is sufficiently different from that of the IGZO film. If there is not enough difference in the etching rate during etching of the protective layer, the surface of the IGZO film will be partially The insulating film is selectively etched to form a region having a smaller thickness than the region overlapping with the channel protection layer. If the channel protection layer is made of the same material as the gate insulating film, this etching process can Therefore, in order to prevent the gate insulating film from being etched, In order to achieve this, it is preferable that the channel protection layer is made of a material different from that of the gate insulating film. In this embodiment, the gate insulating film is two layers, and the upper layer is a SiOx film (x>0). Although there is a risk of it being removed, the lower layer is a silicon nitride film and functions as an etching stopper. do.

[0180] Next, the substrate is set again in the cassette chamber of the multi-chamber type manufacturing apparatus shown in FIG. do.

[0181] Next, after the cassette chamber is depressurized, the substrate is transferred to the transfer chamber 80 and then to the third processing chamber 91. Here, the sputtering process is performed using the pulsed DC sputtering method under an atmosphere of only rare gas. The buffer layer is then formed by depositing an oxide semiconductor containing In, Ga, and Zn having n-type conductivity. The oxide semiconductor film containing In, Ga, and Zn and having n-type conductivity is formed. The oxygen concentration in the film is lower than that of the oxygen-excess IGZO film. As an oxide semiconductor film containing Ga and Zn, it has a higher capacitance than an oxygen-excess IGZO film. The target is preferably an oxide semiconductor containing In, Ga, and Zn. The conductor may further include Mg, Al, or Ti. These materials are easily oxidized. These materials are classified as In, Ga, and Z When n is added to an oxide semiconductor film, it has an oxygen blocking effect, and the like. Even if a process is performed, the oxygen concentration in the semiconductor layer can be kept within the optimal range. The oxide semiconductor film containing In, Ga, and Zn having a conductivity type is a source region or a drain region. Functions as a territory.

[0182] Next, the gate valve 87 is opened and the substrate is transferred by the transfer robot 81 without being exposed to the atmosphere. The wafer is transferred to the transfer chamber 80, the gate valve 88 is opened, the wafer is transferred to the fifth processing chamber 93, and the gate Close valve 88.

[0183] Here, the fifth processing chamber 93 is a sputtering chamber using a DC magnetron sputtering method. In the fifth processing chamber 93, a metal multilayer film that will become the source electrode and the drain electrode is formed. A titanium target and an aluminum target are placed in the sputtering chamber of the fifth processing chamber 93. By setting both targets and a shutter, the films are layered one after the other and continuously formed. Here, an aluminum film is laminated on a titanium film, and Furthermore, a titanium film is laminated on the aluminum film.

[0184] In this way, the semiconductor device containing In, Ga, and Zn having n-type conductivity can be manufactured without being exposed to the air. By successively depositing an oxide semiconductor film and a metal multilayer film, an n-type conductive I A good interface state can be achieved between an oxide semiconductor film containing n, gallium, and zinc and a metal multilayer film. This reduces the contact resistance.

[0185] The above steps are repeated to perform film formation on the substrates in the cassette case, and multiple substrates are processed. After completion, the vacuum in the cassette chamber is released to the atmosphere, and the substrates and cassette are removed.

[0186] Next, the metal multilayer film is selectively etched to form source and drain electrodes. Furthermore, etching is performed using the source electrode and drain electrode as a mask to form an n-type The source region is formed by selectively etching an oxide semiconductor film containing In, Ga, and Zn. A drain region is formed. The n-type conductivity type includes In, Ga, and Zn. In the etching of the oxide semiconductor film, the channel protection layer functions as an etching stopper. do.

[0187] Through the above steps, an inverted staggered thin film transistor having a channel protection layer can be fabricated.

[0188] In addition, in the above process, the oxygen-excess IGZO film and n-type In, Ga, and Z In the above example, the n-containing oxide semiconductor film is formed in the same chamber. However, the present invention is not limited to this. The layers may be formed in separate chambers.

[0189] Here, we have taken the example of a multi-chamber manufacturing device, but if the sputtering chamber is Using in-line manufacturing equipment connected in series, continuous film formation is performed without exposure to the atmosphere. This is also fine.

[0190] The device shown in FIG. 9 is a so-called face-down type in which the substrate is set with the surface on which the film is to be formed facing downwards. However, the substrate may be placed vertically in the processing chamber. The treatment chamber has the advantage of having a smaller footprint than a face-down treatment chamber. Furthermore, this is effective when using a large-area substrate that may bend due to its own weight.

[0191] (Embodiment 7) In this embodiment, at least a part of the driver circuit and a thin film transistor to be disposed in the pixel portion are formed on the same substrate. An example of fabricating a transistor will be described below.

[0192] The thin film transistor disposed in the pixel portion is formed according to any one of the first to fifth embodiments. The thin film transistors described in any of the embodiments 1 to 5 are n-channel TFTs. Therefore, some of the driver circuits can be configured with n-channel TFTs. The thin film transistors in the pixel portion are formed on the same substrate.

[0193] An example of a block diagram of an active matrix type liquid crystal display device is shown in FIG. The display device shown in (A) has a pixel unit 5300 having a plurality of pixels each having a display element on a substrate 5300. 301, a scanning line driver circuit 5302 for selecting each pixel, and a video signal to the selected pixel and a signal line driver circuit 5303 for controlling the input of the signal line.

[0194] The pixel portion 5301 includes a signal line driver circuit 5303 and a plurality of signal lines arranged in a column direction. The signal line driver circuit 5303 is connected to the signal line driver circuit 5303 by lines S1 to Sm (not shown). A plurality of scanning lines G1 to Gn (not shown) are arranged extending from 5302 in the row direction. The scanning line driver circuit 5302 is connected to the signal lines S1 to Sm and the scanning lines G1 to Gn. The image sensor has a plurality of pixels (not shown) arranged in a matrix. Signal line Sj (any one of signal lines S1 to Sm), scanning line Gi (any one of scanning lines G1 to Gn) Either one of them is connected.

[0195] The thin film transistors described in any of the embodiments 1 to 5 are n-channel TFTs. A signal line driver circuit configured with n-channel TFTs will be described with reference to FIG.

[0196] The signal line driver circuit shown in FIG. 02_M, a first wiring 5611, a second wiring 5612, a third wiring 5613 and a wiring 56 Each of the switch groups 5602_1 to 5602_M includes A first thin film transistor 5603a, a second thin film transistor 5603b, and a third thin film transistor It has a transistor 5603c.

[0197] The driver IC 5601 is connected to a first wiring 5611, a second wiring 5612, and a third wiring 5613. and are connected to the wirings 5621_1 to 5621_M. 5602_M are a first wiring 5611, a second wiring 5612, a third wiring 561 3 and wiring 5621_1 to 5621_5 corresponding to the switch groups 5602_1 to 5602_M, respectively. Each of the wirings 5621_1 to 5621_M is connected to the first A thin film transistor 5603a, a second thin film transistor 5603b, and a third thin film transistor For example, the wiring 5621 in the Jth column is connected to three signal lines via a resistor 5603c. _J (any one of the wirings 5621_1 to 5621_M) is a switch group 5602 The first thin film transistor 5603a, the second thin film transistor 5603b, and and the third thin film transistor 5603c, the signal line Sj-1, the signal line Sj, the signal line S j+1 is connected to

[0198] The first wiring 5611, the second wiring 5612, and the third wiring 5613 are each connected to a signal line. The number is entered.

[0199] It is preferable that the driver IC 5601 is formed on a single crystal substrate. The switch groups 5602_1 to 5602_M correspond to the screens shown in the first to fifth embodiments. It is desirable to form the driver IC 5601 on the same substrate as the base part. and the switch groups 5602_1 to 5602_M may be connected via FPCs or the like.

[0200] Next, the operation of the signal line driver circuit shown in FIG. 11 will be described with reference to the timing chart of FIG. The timing chart of FIG. 12 is explained with reference to the timing chart when the i-th scanning line Gi is selected. Further, during the selection period of the i-th scanning line Gi, is divided into a first sub-selection period T1, a second sub-selection period T2, and a third sub-selection period T3. Furthermore, when a scanning line of another row is selected, the signal line driver circuit of FIG. In this case, the same operation as in FIG. 12 is performed.

[0201] In the timing chart of FIG. 12, the wiring 5621_J in the Jth column is connected to the first thin-film transistor. a second thin film transistor 5603b, and a third thin film transistor 560 When connected to signal line Sj-1, signal line Sj, and signal line Sj+1 via 3c It shows.

[0202] In the timing chart of FIG. 12, the timing when the i-th scanning line Gi is selected, The on / off timing 5703a of the first thin film transistor 5603a, The on / off timing 5703b of the third thin film transistor 56 The on / off timing of 03c is input to 5703c and the wiring 5621_J of the Jth row. 5 shows signal 5721_J.

[0203] The wirings 5621_1 to 5621_M are connected to the first sub-selection period T1 and the second sub-selection period T2. In the first sub-selection period T2 and the third sub-selection period T3, different video signals are input. For example, the video signal input to the wiring 5621_J in the first sub-selection period T1 is The signal is input to the signal line Sj-1 and is input to the wiring 5621_J in the second sub-selection period T2. The video signal to be output is input to the signal line Sj, and the line 5621 is connected to the line Sj during the third sub-selection period T3. The video signal input to the first sub-selection period is input to the signal line Sj+1. In the period T1, the second sub-selection period T2, and the third sub-selection period T3, the wiring 5621_ The video signals input to J are Data_j-1, Data_j, and Data_j+ Let's say it's 1.

[0204] As shown in FIG. 12, in the first sub-selection period T1, the first thin film transistor 5603 a is turned on, and the second thin film transistor 5603b and the third thin film transistor 5603c At this time, Data_j-1 input to the wiring 5621_J is turned off. The signal is input to the signal line Sj-1 via the transistor 5603a. Second sub-selection period T2 In this case, the second thin film transistor 5603b is turned on, and the first thin film transistor 5603a is turned on. and the third thin film transistor 5603c are turned off. At this time, the input The Data_j to be output is input to the signal line Sj via the second thin film transistor 5603b. In the third sub-selection period T3, the third thin film transistor 5603c is turned on, and the first The first thin film transistor 5603a and the second thin film transistor 5603b are turned off. At this time, Data_j+1 input to the wiring 5621_J is input to the third thin film transistor 56 03c and input to the signal line Sj+1.

[0205] From the above, the signal line driver circuit in FIG. 11 divides one gate selection period into three. During one gate selection period, a video signal is input from one wiring 5621 to three signal lines. Therefore, the signal line driver circuit of FIG. The number of connections between the substrate on which the pixel area is formed and the substrate on which the pixel area is formed is reduced to about one-third of the number of signal lines. By reducing the number of connections to about one third, the signal line driver circuit of FIG. This can improve productivity and yield.

[0206] As shown in Figure 11, one gate selection period is divided into multiple sub-selection periods, and multiple sub-selection periods are During each selection period, a video signal is input from one line to each of multiple signal lines. As long as this can be achieved, the arrangement, number, driving method, etc. of the thin film transistors are not limited.

[0207] For example, three or more signal lines are connected to one wiring during each of three or more sub-selection periods. When a video signal is input to each of them, a thin film transistor and a thin film transistor are controlled. However, it is necessary to divide one gate selection period into four or more sub-selection periods. Therefore, one gate selection period is divided into two or It is preferably divided into three sub-selection periods.

[0208] As another example, as shown in the timing chart of FIG. 13, one selection period is precharged. The first sub-selection period T1, the second sub-selection period T2, and the third selection period T3 are Furthermore, in the timing chart of FIG. 13, the i-th scanning line Gi is selected. the timing of turning on and off the first thin film transistor 5603a; a, the on-off timing 5803b of the second thin film transistor 5603b, The on / off timing 5803c of the membrane transistor 5603c and the wiring 562 of the Jth column 13, the signal 5821_J input to the precharge In the period Tp, the first thin film transistor 5603a and the second thin film transistor 5603 At this time, the input to the wiring 5621_J is turned on. The input precharge voltage Vp is applied to the first thin film transistor 5603a, the second thin film transistor 5603b, and the and a third thin film transistor 5603c are connected to the signal line Sj- 1, signal line Sj, and signal line Sj+1. The thin film transistor 5603a is turned on, and the second thin film transistor 5603b and the third thin film transistor At this time, the signal Dat input to the wiring 5621_J is turned off. a_j-1 is input to the signal line Sj-1 via the first thin film transistor 5603a. In the second sub-selection period T2, the second thin film transistor 5603b is turned on, and the first thin film transistor The third thin film transistor 5603a and the third thin film transistor 5603c are turned off. Data_j input to the wiring 5621_J is input to the second thin film transistor 5603b. In the third sub-selection period T3, the third thin film transistor The first thin film transistor 5603a and the second thin film transistor 5603c are turned on. At this time, Data_j+1 input to the wiring 5621_J is The signal is input to the signal line Sj+1 via the third thin film transistor 5603c.

[0209] From the above, the signal line driver circuit of FIG. 11 to which the timing chart of FIG. 13 is applied By providing a precharge selection period before the sub selection period, the signal lines can be precharged. This allows high-speed writing of video signals to the pixels. In this embodiment, the same reference numerals are used for the same parts as those in FIG. 12, and the same parts or parts with similar functions are shown. A detailed description of the portion having the symbol will be omitted.

[0210] The configuration of the scanning line driver circuit will be described. The scanning line driver circuit includes a shift register, a buffer, and a In some cases, a level shifter may be included. In the circuit, a clock signal (CLK) and a start pulse signal (SP ) is input, the selection signal is generated. The generated selection signal is buffered The signal is buffered and amplified in the 10-bit signal line and then fed to the corresponding scan line. The gate electrodes of the transistors are connected. Since they must all be turned on at the same time, the buffer must be capable of passing a large current. Used.

[0211] One form of a shift register used as a part of a scanning line driving circuit is shown in FIG. 14 and FIG. 15. He explains.

[0212] The circuit configuration of the shift register is shown in Fig. 14. The shift register shown in Fig. 14 has multiple free Flip-flop 5701_i (any of flip-flops 5701_1 to 5701_n) Also, the first clock signal, the second clock signal, the start pulse It operates when a signal and a reset signal are input.

[0213] The connection relationship of the shift register in Fig. 14 will be described. The shift register in Fig. 14 has i-stage The first flip-flop 5701_i (flip-flops 5701_1 to 5701_n In either one of them, the first wiring 5501 shown in FIG. 15 is connected to the seventh wiring 5717_i-1. 15 is connected to the seventh wiring 5717_i+1. 15 is connected to the seventh wiring 5717_i, The sixth wiring 5506 is connected to the fifth wiring 5715 .

[0214] In addition, the fourth wiring 5504 shown in FIG. 15 corresponds to the second wiring in the odd-numbered flip-flops. 5712, and in the even-numbered flip-flops, it is connected to the third wiring 5713. The fifth wiring 5505 shown in FIG.

[0215] However, the first wiring 5501 shown in FIG. 15 of the first-stage flip-flop 5701_1 is 15 of the n-th flip-flop 5701_n. The second wiring 5502 is connected to the sixth wiring 5716 .

[0216] The first wiring 5711, the second wiring 5712, the third wiring 5713, and the sixth wiring 57 16 can be called the first signal line, the second signal line, the third signal line, and the fourth signal line, respectively. Furthermore, the fourth wiring 5714 and the fifth wiring 5715 are respectively connected to the first power supply line and the third power supply line. This may also be called the power line 2.

[0217] Next, the details of the flip-flop shown in FIG. 14 are shown in FIG. The flip-flop includes a first thin film transistor 5571, a second thin film transistor 5572, A third thin film transistor 5573, a fourth thin film transistor 5574, a fifth thin film transistor a sixth thin film transistor 5575, a seventh thin film transistor 5576, and and an eighth thin film transistor 5578. A second thin film transistor 5572, a third thin film transistor 5573, a fourth thin film transistor a fifth thin film transistor 5574, a fifth thin film transistor 5575, a sixth thin film transistor 5576, The seventh thin film transistor 5577 and the eighth thin film transistor 5578 are n-channel A transistor in which the gate-source voltage (Vgs) exceeds the threshold voltage (Vth). When this occurs, the device is in a conductive state.

[0218] Next, the connection configuration of the flip-flop shown in FIG. 14 will be described below.

[0219] A first electrode (either a source electrode or a drain electrode) of the first thin film transistor 5571 is connected to a fourth wiring 5504, and a second electrode (source) of the first thin film transistor 5571 is connected to The other of the source electrode and the drain electrode is connected to a third wiring 5503 .

[0220] A first electrode of the second thin film transistor 5572 is connected to the sixth wiring 5506. A second electrode of the thin film transistor 5572 is connected to a third wiring 5503 .

[0221] A first electrode of the third thin film transistor 5573 is connected to a fifth wiring 5505. The second electrode of the thin film transistor 5573 is the gate electrode of the second thin film transistor 5572. , and the gate electrode of the third thin film transistor 5573 is connected to the fifth wiring 5505. will be done.

[0222] A first electrode of the fourth thin film transistor 5574 is connected to a sixth wiring 5506. The second electrode of the thin film transistor 5574 is the gate electrode of the second thin film transistor 5572. , and the gate electrode of the fourth thin film transistor 5574 is connected to the first thin film transistor 5 It is connected to the gate electrode of 571.

[0223] A first electrode of the fifth thin film transistor 5575 is connected to a fifth wiring 5505. The second electrode of the thin film transistor 5575 is the gate electrode of the first thin film transistor 5571. , and the gate electrode of the fifth thin film transistor 5575 is connected to the first wiring 5501. will be done.

[0224] A first electrode of the sixth thin film transistor 5576 is connected to the sixth wiring 5506. The second electrode of the thin film transistor 5576 is the gate electrode of the first thin film transistor 5571. , and the gate electrode of the sixth thin film transistor 5576 is connected to the second thin film transistor 5 It is connected to the gate electrode of 572.

[0225] A first electrode of the seventh thin film transistor 5577 is connected to the sixth wiring 5506. The second electrode of the thin film transistor 5577 is the gate electrode of the first thin film transistor 5571. , and the gate electrode of the seventh thin film transistor 5577 is connected to the second wiring 5502. A first electrode of the eighth thin film transistor 5578 is connected to the sixth wiring 5506. The second electrode of the eighth thin film transistor 5578 is connected to the gate of the second thin film transistor 5572. The gate electrode of the eighth thin film transistor 5578 is connected to the first wiring 550. Connected to 1.

[0226] The gate electrode of the first thin film transistor 5571 and the gate electrode of the fourth thin film transistor 5574 the gate electrode of the fifth thin film transistor 5575, the second electrode of the sixth thin film transistor The connection point of the second electrode of the seventh thin film transistor 5576 and the second electrode of the seventh thin film transistor 5577 is Further, the gate electrode of the second thin film transistor 5572, the gate electrode of the third thin film transistor 5543, a second electrode of the fourth thin film transistor 5573; a second electrode of the fourth thin film transistor 5574; The gate electrode of the sixth thin film transistor 5576 and the gate electrode of the eighth thin film transistor 5578 The connection point of the two electrodes is designated as node 5544.

[0227] The first wiring 5501, the second wiring 5502, the third wiring 5503 and the fourth wiring 5504 are 504 are referred to as the first signal line, the second signal line, the third signal line, and the fourth signal line, respectively. Furthermore, the fifth wiring 5505 may be connected to a first power supply line, and the sixth wiring 5506 may be connected to a second power supply line. It may be called a line.

[0228] In addition, the signal line driver circuit and the scanning line driver circuit may be the same as those in the n-channel MOSFETs shown in any one of the first to fifth embodiments. It is also possible to manufacture the device using only a panel-type TFT. Since the mobility of the transistor is large, the driving frequency of the driving circuit can be increased. In addition, the n-channel TFTs described in any of the embodiments 1 to 5 can be The buffer layer reduces parasitic capacitance, resulting in high frequency characteristics (called f characteristics). For example, the scanning line driving circuit using the n-channel TFT shown in any one of the first to fifth embodiments may be Since the circuit can operate at high speed, it is possible to increase the frame frequency or It is also possible to realize things like screen insertion.

[0229] Furthermore, the channel width of the transistor of the scanning line driving circuit is increased, and multiple scanning lines By arranging the drive circuit, it is possible to achieve even higher frame frequencies. When multiple scanning line driving circuits are arranged, a scanning line driving circuit for driving the even-numbered scanning lines is provided. The circuit is placed on one side, and the scanning line driving circuit for driving the odd-numbered scanning lines is placed on the opposite side. By placing the pixel clock in the pixel clockwise direction, it is possible to realize a high frame frequency.

[0230] In addition, when an active matrix type light emitting display device is manufactured, multiple In order to arrange a large number of thin film transistors, it is preferable to arrange a plurality of scanning line driving circuits. FIG. 10B shows an example of a block diagram of an active matrix light-emitting display device.

[0231] The display device shown in FIG. 10B has a plurality of pixels each having a display element on a substrate 5400. A pixel section 5401, a first scanning line driver circuit 5402 for selecting each pixel, and a second scanning line driver A signal line driver circuit 5403 for controlling the input of a video signal to a selected pixel. and

[0232] When a video signal input to the pixel of the display device shown in FIG. 10B is in digital format, Pixels emit or do not emit light by switching transistors on and off. Therefore, gray scale display can be performed using the area gray scale method or the time gray scale method. This method divides one pixel into multiple sub-pixels, and each sub-pixel is driven independently based on a video signal. The time gray scale method is a driving method that displays gray scales by changing the time This is a driving method that displays gradations by controlling the interval.

[0233] Light-emitting elements have a higher response speed than liquid crystal elements, so they are more suitable for time gray scale modulation than liquid crystal elements. Specifically, when displaying using the time gray scale method, one frame period is divided into multiple subframes. Then, the light emitting element of the pixel is divided into sub-frame periods according to the video signal. By dividing the period into multiple subframes, The total length of time that pixels actually emit light during one frame is controlled by the video signal. It is possible to control the brightness and display gradation.

[0234] In the light-emitting device shown in FIG. 10B, a switching TFT and a current control TFT are provided in one pixel. When two TFTs are arranged, the first one is the gate wiring of the switching TFT, The signal input to the scanning line is generated by the first scanning line driving circuit 5402 and is input to the gate of the current control TFT. A signal to be input to the second scanning line, which is a transmission wiring, is generated by a second scanning line driver circuit 5404. The example shows a signal input to the first scanning line and a signal input to the second scanning line. The signal and the signal may be generated by one scanning line driving circuit. The operation of the switching element is controlled by the number of transistors that the switching element has. A plurality of first scanning lines may be provided for each pixel. The signals input to the first scanning line may all be generated by one scanning line driver circuit, or may be generated by multiple scanning line driver circuits. Alternatively, the signal may be generated by each of the scanning line driving circuits.

[0235] In addition, the driving circuit of the light emitting device can be configured with n-channel TFTs. A part of the driver circuit can be formed on the same substrate as the thin film transistor of the pixel portion. In addition, the signal line driver circuit and the scanning line driver circuit may be the n-channel type shown in any one of the first to fifth embodiments. It is also possible to fabricate the device using only rectangular TFTs.

[0236] The above-mentioned driving circuit is not limited to liquid crystal display devices and light emitting devices, but may also be used for switching elements and electrical The present invention may also be used in electronic paper, which uses electrically connected elements to drive electronic ink. The paper is also called an electrophoretic display (electrophoretic display) and has the same reading quality as paper. It has the advantages of being easy to use, consuming less power than other display devices, and being able to be made thin and light. It has.

[0237] Electrophoretic displays can take a variety of forms, but the first particle has a positive charge. A microcapsule containing a negatively charged second particle and a negatively charged second particle is immersed in a solvent or solute. By applying an electric field to the microcapsules, The particles in the capsule are moved in opposite directions to each other, and only the color of the particles that have gathered on one side is displayed. The first particles or the second particles contain a dye, and in the absence of an electric field, The first particles and the second particles are different in color (colorless). (including

[0238] Thus, electrophoretic displays operate in a manner such that materials with high dielectric constants migrate to areas of high electric field. This is a display that utilizes the so-called dielectrophoretic effect. Electrophoretic displays do not require polarizing plates or opposing substrates, which are necessary for display devices, and are half the thickness and weight. Reduce.

[0239] The microcapsules dispersed in a solvent are called electronic ink. The electronic ink can be printed on surfaces such as glass, plastic, fabric, and paper. A color display is also possible by using a color filter or particles having a pigment.

[0240] In addition, the above microphone is appropriately placed on the active matrix substrate so as to be sandwiched between two electrodes. By arranging multiple microcapsules, an active matrix display device is completed. Display can be achieved by applying an electric field to the cell. A positive matrix substrate can be used.

[0241] The first particles and the second particles in the microcapsules are made of a conductive material, an insulating material, Semiconductor materials, magnetic materials, liquid crystal materials, ferroelectric materials, electroluminescent materials, A material selected from the group consisting of magnetochromic material, magnetophoretic material, and a composite material thereof. Just use it.

[0242] (Embodiment 8) A thin film transistor according to one embodiment of the present invention is manufactured, and the thin film transistor is used in a pixel portion and a driving By using the semiconductor device in the operating circuit, a semiconductor device having a display function (also called a display device) can be manufactured. In addition, a part or an entire driver circuit using the thin film transistor of one embodiment of the present invention may be It is possible to form the element portion on the same substrate as the substrate, forming a system on panel.

[0243] The display device includes a display element. The display element may be a liquid crystal element (also called a liquid crystal display element), a light-emitting A light-emitting element (also called a light-emitting display element) can be used. A light-emitting element is a light-emitting element that emits light by applying a current or a voltage. This category includes elements whose brightness is controlled by a specific factor, such as inorganic EL (Electroluminescent) devices. Also, electronic inks and other electronic devices A display medium in which the contrast changes due to thermal effects can also be applied.

[0244] The display device includes a panel in which a display element is sealed, and a controller for the panel. and a module in which an IC or the like including the above-mentioned is mounted. Regarding the element substrate, which corresponds to one form before the display element is completed in the process of manufacturing a display device The element substrate includes a means for supplying a current to each of the plurality of pixels. Specifically, the substrate may be in a state where only pixel electrodes of the display element are formed, or the substrate may be in a state where only pixel electrodes of the display element are formed. After the conductive film that will become the electrode is formed, but before etching is performed to form the pixel electrode. It's fine to have one, and any form is acceptable.

[0245] In this specification, the term "display device" refers to an image display device, a display device, or an optical Also refers to connectors, such as FPC (Flexible Printed Circuit). inted circuit) or TAB (Tape Automated Bon ding tape or TCP (Tape Carrier Package) is used. Modules with printed wiring boards attached to the ends of TAB tape or TCP or the display element is mounted with an IC (integrated circuit) by the COG (Chip On Glass) method. The display device also includes all modules in which a display circuit (or other circuit) is directly mounted.

[0246] In this embodiment, a liquid crystal display device will be described as an example of a semiconductor device according to one embodiment of the present invention.

[0247] 16A and 16B show an active matrix liquid crystal display device to which one embodiment of the present invention is applied. FIG. 16(A) is a plan view of the liquid crystal display device, and FIG. 16(B) is a schematic diagram of the liquid crystal display device shown in FIG. 1 is a cross-sectional view of a thin film transistor 201 used in a semiconductor device. The thin film transistor can be manufactured in the same manner as in the thin film transistor described in the embodiment 4. A buffer layer made of an oxide semiconductor layer containing In, Ga, and Zn having a conductivity type of This is a highly reliable thin film transistor. The thin film transistor shown in the fifth embodiment is also applicable to the thin film transistor 201 of the present embodiment. It is also possible.

[0248] The liquid crystal display device of this embodiment shown in FIG. 16(A) includes a source wiring layer 202 and a multi-gate structure. The pixel includes an inverted staggered thin film transistor 201 , a gate wiring layer 203 , and a capacitance wiring layer 204 .

[0249] In addition, in FIG. 16B, the liquid crystal display device of the present embodiment has a thin film transistor having a multi-gate structure. A transistor 201, an insulating layer 211, an insulating layer 212, an insulating layer 213, and a display element The substrate 2 is provided with an electrode layer 255, an insulating layer 261 that functions as an alignment film, and a polarizing plate 268. 00, an insulating layer 263 that functions as an alignment film, an electrode layer 265 used for a display element, A colored layer 264 functioning as a filter, a substrate 266 provided with a polarizing plate 267, and a liquid crystal layer 268 are arranged in the liquid crystal layer 268. 62 and has a liquid crystal display element 260.

[0250] Although FIG. 16 shows an example of a transmissive liquid crystal display device, one embodiment of the present invention is a reflective liquid crystal display device. The present invention can also be applied to semi-transmissive liquid crystal display devices.

[0251] In the liquid crystal display device of FIG. 16, a polarizing plate 267 is provided on the outer side (the viewing side) of the substrate 266. In the example shown, a colored layer 264 and an electrode layer 265 used for a display element are provided in this order on the inside. The plate 267 may be provided on the inside of the substrate 266. Also, the laminated structure of the polarizing plate and the colored layer may be the same as that shown in FIG. However, the present invention is not limited to these values, and may be appropriately set depending on the materials of the polarizing plate and the coloring layer and the manufacturing process conditions. In addition, a light-shielding film that functions as a black matrix may be provided.

[0252] The electrode layers 255 and 265 functioning as pixel electrode layers are made of indium tungsten oxide. Oxide, indium zinc oxide with tungsten oxide, indium oxide with titanium oxide Indium tin oxide (ITO) ), indium zinc oxide, indium tin oxide doped with silicon oxide, etc. A conductive material having such a property can be used.

[0253] The electrode layers 255 and 265 are made of a conductive material including a conductive polymer. The pixel electrode formed by using the conductive composition can be formed by the following steps: Sheet resistance is 10,000 Ω / □ or less, and light transmittance at a wavelength of 550 nm is 70% or more. It is preferable that the resistivity of the conductive polymer contained in the conductive composition is 0.1 Ω cm. It is preferable that:

[0254] As the conductive polymer, a so-called π-electron conjugated conductive polymer can be used. For example, polyaniline or its derivatives, polypyrrole or its derivatives, polythiophene or or a derivative thereof, or a copolymer of two or more of these.

[0255] Through the above steps, a highly reliable liquid crystal display device can be manufactured as a semiconductor device. .

[0256] This embodiment mode can be implemented in appropriate combination with the configurations described in other embodiments. It is.

[0257] (Embodiment 9) In this embodiment, an example of electronic paper will be described as a semiconductor device of one embodiment of the present invention.

[0258] FIG. 17 shows an active matrix type semiconductor device as an example of a semiconductor device to which one embodiment of the present invention is applied. The thin film transistor 581 used in the semiconductor device is It can be fabricated in the same way as the thin-film transistor shown in Example 4, and has an IGZO semiconductor layer and an n-type conductivity. The buffer layer is made of an oxide semiconductor layer containing In, Ga, and Zn. The thin film transistor is a thin film transistor. A thin film transistor can also be applied as the thin film transistor 201 of this embodiment. .

[0259] The electronic paper in FIG. 17 is an example of a display device that uses the twisting ball display method. The spherical display method is an electrode layer that uses spherical particles painted in black and white as display elements. A potential difference is applied between the first electrode layer and the second electrode layer. This is a method of displaying information by controlling the orientation of spherical particles caused by the generation of light.

[0260] The thin film transistor 581 is an inverted staggered type thin film transistor having a multi-gate structure. The first electrode layer 587 and the insulating layer 585 are formed by a source electrode layer and a drain electrode layer. The first electrode layer 587 and the second electrode layer 588 are in contact with each other at the opening and are electrically connected. The liquid-filled container has a black area 590a and a white area 590b in between. A spherical particle 589 including a bit 594 is provided, and the spherical particle 589 is surrounded by a resin or the like. It is filled with a filler material 595 (see FIG. 17).

[0261] In FIG. 17, an electrode layer containing a transparent conductive polymer is used as the first electrode layer. An inorganic insulating film is provided on the first electrode layer 587a. It functions as a barrier film that prevents the diffusion of ionic impurities.

[0262] Also, instead of the twist ball, an electrophoretic element can be used. and a 10μm to 20μm diameter nanoparticle that contains positively charged white nanoparticles and negatively charged black nanoparticles. Microcapsules with a diameter of about 0 μm are used. When an electric field is applied to the microcapsules by the first and second electrode layers, the microcapsules emit white light. White particles and black particles move in opposite directions, allowing the display to be white or black. The display element that applies this principle is the electrophoretic display element, which is generally called electronic paper. Electrophoretic display elements have a higher reflectivity than liquid crystal display elements, so auxiliary lights are not required. It also consumes little power and the display can be seen even in dimly lit places. Even if power is not supplied to the display, the image that was displayed can be retained. Therefore, a semiconductor device with a display function (simply a display device, or a device equipped with a display device) is The ability to preserve the displayed image even when the device (also known as a semiconductor device) is moved away This becomes possible.

[0263] Through the above steps, electronic paper having high reliability as a semiconductor device can be manufactured. .

[0264] This embodiment mode can be implemented in appropriate combination with the configurations described in other embodiments. It is.

[0265] (Embodiment 10) In this embodiment, an example of a light-emitting display device will be described as a semiconductor device according to one embodiment of the present invention. As the display element of the device, a light-emitting element using electroluminescence is used here. The light-emitting element that utilizes electroluminescence uses an organic compound as the light-emitting material. Generally, the former are organic EL elements and the latter are inorganic compounds. These are called inorganic EL elements.

[0266] In an organic EL element, electrons and holes are released from a pair of electrodes by applying a voltage to the light-emitting element. are injected into layers containing light-emitting organic compounds, causing a current to flow. The rears (electrons and holes) recombine to form an excited state in the light-emitting organic compound. When the excited state returns to the ground state, light is emitted. Such a light-emitting element is called a current-excitation type light-emitting element.

[0267] Inorganic EL elements are divided into dispersion-type inorganic EL elements and thin-film-type inorganic EL elements according to their element structure. Dispersion-type inorganic EL elements have a light-emitting layer in which particles of a light-emitting material are dispersed in a binder. The emission mechanism is a donor-acceptor reaction that utilizes the donor and acceptor levels. Thin-film inorganic EL elements are made by sandwiching a light-emitting layer between dielectric layers. The structure is sandwiched between electrodes, and the light emission mechanism utilizes the inner shell electron transition of metal ions. In this example, the light-emitting element is an organic EL element. do.

[0268] 18A and 18B show an active matrix semiconductor device as an example of a semiconductor device to which one embodiment of the present invention is applied. FIG. 18(A) is a plan view of the light-emitting display device, and FIG. FIG. 19 is a cross-sectional view of the development device shown in FIG. 2 shows an equivalent circuit of the optical display device.

[0269] The thin film transistors 301 and 302 used in the semiconductor device are the same as those in the first embodiment and the second embodiment. The thin film transistor can be fabricated in the same manner as in the second embodiment. and a buffer layer made of an oxide semiconductor layer containing In, Ga, and Zn. In addition, the thin film transistors shown in any of the embodiments 3 to 5 are thin film transistors having high characteristics. A thin film transistor may also be used as the thin film transistors 301 and 302 in this embodiment.

[0270] The light-emitting display device of this embodiment shown in FIG. 18(A) and FIG. 19 is a thin film having a multi-gate structure. A transistor 301, a light emitting element 303, a capacitance element 304, a source wiring layer 305, a gate wiring The thin film transistors 301 and 302 are n-channel thin film transistors. It is a transistor.

[0271] In addition, in FIG. 18B, the light-emitting display device of this embodiment mode has a thin film transistor 302 , the insulating layer 311, the insulating layer 312, the insulating layer 313, the partition wall 321, and the light-emitting element 303. The light-emitting device has a first electrode layer 320 , an electroluminescent layer 322 , and a second electrode layer 323 .

[0272] The insulating layer 313 is made of an organic resin such as acrylic, polyimide, or polyamide, or siloxane. It is preferable to form the insulating film using the above method.

[0273] In this embodiment, since the thin film transistor 302 of the pixel is an n-type transistor, the first It is preferable to use a cathode as the first electrode layer 320. Materials with small functions, such as Ca, Al, CaF, MgAg, and AlLi, can be used. can.

[0274] The partition wall 321 is formed using an organic resin film, an inorganic insulating film, or an organic polysiloxane. A photosensitive material is used to form an opening on the first electrode layer 320, and the sidewall of the opening is continuous. It is preferable to form the inclined surface so as to have a continuous curvature.

[0275] The electroluminescent layer 322 may be composed of a single layer or a plurality of layers may be laminated. It doesn't matter whether it's

[0276] A second electrode layer 323 using an anode is formed so as to cover the electroluminescent layer 322. The electrode layer 323 is made of a conductive material having a light transmitting property as listed as the pixel electrode layer in the seventh embodiment. In addition to the above-mentioned transparent conductive film, a titanium nitride film or A titanium film may be used for the first electrode layer 320, the electroluminescent layer 322, and the second electrode layer 32 3 are overlapped to form the light emitting element 303. In order to prevent the intrusion of air (oxygen, hydrogen, moisture, carbon dioxide, etc.), the second electrode layer 323 and A protective film may be formed on the partition wall 321. The protective film may be a silicon nitride film or a silicon oxynitride film. , DLC films, etc. can be formed.

[0277] Furthermore, in practice, once the process up to Figure 18(B) is completed, the structure is made airtight to prevent it from being exposed to the outside air. Protective films with high heat resistance and low degassing (laminated films, UV curable resin films, etc.) It is preferable to package (enclose) the container in a container-type container or a cover material.

[0278] Next, the configuration of the light-emitting element will be described with reference to FIG. The cross-sectional structure of a pixel will be described using the example of the type shown in Figures 20(A), (B), and (C). The driving TFTs 7001, 7011, and 7021 used in the semiconductor device are the same as those in the first embodiment. The thin-film transistor shown in Fig. 1 can be fabricated in the same manner as the thin-film transistor shown in Fig. 1. The I A highly reliable thin film transistor including a buffer layer made of an oxide semiconductor layer containing n, Ga, and Zn. The thin film transistor shown in the second, third or fourth embodiment is also The transistors can also be used as the driving TFTs 7001, 7011, and 7021.

[0279] The light emitting element only needs to have at least one of the anode and cathode transparent in order to extract light. Then, a thin film transistor and a light emitting element are formed on the substrate, and light is taken from the surface opposite to the substrate. Top emission, bottom emission, and side emission. There is a light-emitting element having a dual emission structure in which light is emitted from the side of the substrate. The present invention can be applied to any light emitting element with any emission structure.

[0280] A light emitting element having a top emission structure will be described with reference to FIG.

[0281] In FIG. 20A, a driving TFT 7001 is an n-type TFT, and light emitted from a light-emitting element 7002 is FIG. 20A shows a cross-sectional view of a pixel when the light emitting element 70 The cathode 7003 of the TFT 7002 is electrically connected to the driving TFT 7001. A light-emitting layer 7004 and an anode 7005 are laminated on the cathode in this order. Various materials can be used as long as they are conductive and light-reflecting. For example, The light-emitting layer 7004 is preferably made of a single It may be configured as a layer or as a laminate of a plurality of layers. In the case where the cathode 7003 is composed of a plurality of layers, an electron injection layer, an electron transport layer, an emitting layer, a hole injection layer, and a hole transport layer are formed on the cathode 7003. The hole transport layer and the hole injection layer are laminated in this order. Note that it is not necessary to provide all of these layers. The electrode 7005 is formed using a conductive material having a light transmitting property, for example, tungsten oxide. Indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, titanium oxide Indium oxide containing tungsten, indium tin oxide containing titanium oxide, indium tin oxide ITO, indium zinc oxide, indium doped with silicon oxide A light-transmitting conductive film such as a tin oxide film may be used.

[0282] The region where the light-emitting layer 7004 is sandwiched between the cathode 7003 and the anode 7005 constitutes the light-emitting element 7002. In the case of the pixel shown in FIG. 20(A), the light emitted from the light emitting element 7002 is The light is emitted toward the anode 7005 as indicated by the mark.

[0283] Next, a light emitting element having a bottom emission structure will be described with reference to FIG. When 011 is an n-type light emitting element and light emitted from the light emitting element 7012 is emitted to the cathode 7013 side, FIG. 20B shows a cross-sectional view of a pixel. A cathode 7013 of a light-emitting element 7012 is formed on a light-transmitting conductive film 7017. A light-emitting layer 7014 and an anode 7015 are laminated in this order on the cathode 7013. When the anode 15 has a light-transmitting property, a shielding layer for reflecting or blocking light is provided so as to cover the anode. The cathode 7013 may have a film 7016 formed thereon, as in the case of FIG. Various conductive materials with small thermal coefficients can be used. However, the thickness of the material should be The thickness is set to a level that allows light to pass through (preferably, about 5 nm to 30 nm). For example, a 20 nm film An aluminum film having a thickness of 700 nm can be used as the cathode 7013. 014 may be composed of a single layer, as in FIG. 20(A), or may be composed of multiple layers. The anode 7015 does not need to transmit light, but as shown in FIG. As in the case of 20(A), the insulating film 20 can be formed using a conductive material having light-transmitting properties. The shielding film 7016 may be made of, for example, a metal that reflects light, but is not limited to a metal film. For example, a resin containing a black pigment may be used.

[0284] The region where the light-emitting layer 7014 is sandwiched between the cathode 7013 and the anode 7015 is the light-emitting element 7012. In the case of the pixel shown in FIG. 20B, the light emitted from the light-emitting element 7012 corresponds to The light is emitted toward the cathode 7013 as shown by the arrow.

[0285] Next, a light emitting element having a dual emission structure will be described with reference to FIG. In this example, a conductive film 7027 having a light-transmitting property and electrically connected to the driving TFT 7021 is formed on the substrate 7022. A cathode 7023 of the light-emitting element 7022 is formed, and a light-emitting layer 7024 is formed on the cathode 7023. The anode 7025 is laminated in order. The cathode 7023 is, as in the case of FIG. Various conductive materials with small thermal coefficients can be used. However, the thickness of the material should be For example, the cathode 7023 is made of Al having a thickness of 20 nm. The light-emitting layer 7024 can be formed of a single layer, as in FIG. The anode 70 may be configured as a single layer or as a laminate of multiple layers. 25 is formed using a conductive material having a light transmitting property, similar to FIG. It is possible.

[0286] The overlapping portion of the cathode 7023, the light-emitting layer 7024, and the anode 7025 constitutes the light-emitting element 70. In the case of the pixel shown in FIG. 20C, the light emitted from the light emitting element 7022 is is emitted toward both the anode 7025 side and the cathode 7023 side as indicated by the arrows.

[0287] Although the organic EL element has been described as the light-emitting element here, inorganic EL elements can also be used as the light-emitting element. It is also possible to provide an L element.

[0288] In this embodiment, a thin film transistor (driving TFT) that controls driving of a light emitting element is Although an example in which the light-emitting element is electrically connected has been shown, the current between the driving TFT and the light-emitting element is A control TFT may be connected.

[0289] Note that the semiconductor device described in this embodiment mode is not limited to the configuration shown in FIG. Various modifications based on the technical concept of the present invention are possible.

[0290] Through the above steps, a light-emitting display device having high reliability as a semiconductor device can be manufactured. .

[0291] This embodiment mode can be implemented in appropriate combination with the configurations described in other embodiments. It is.

[0292] (Embodiment 11) Next, a structure of a display panel, which is one embodiment of a semiconductor device of the present invention, will be described below. In the embodiment, a liquid crystal display panel, which is one type of liquid crystal display device having a liquid crystal element as a display element, is used. A liquid crystal panel is one form of a semiconductor device having a light-emitting element as a display element. A light-emitting display panel (also called a light-emitting panel) will be described below.

[0293] Next, the appearance and cross section of a light-emitting display panel, which is one embodiment of a semiconductor device of the present invention, will be described. The following description will be given with reference to FIG. 21. FIG. 21 shows an IGZO semiconductor layer and a n The buffer layer is made of an oxide semiconductor layer containing In, Ga, and Zn having a conductivity type of 1000 nm. A highly reliable thin film transistor and light emitting element are sandwiched between the second substrate and the substrate by a sealant. FIG. 21(B) is a top view of the sealed panel, and FIG. 21(A) is a cross-section taken along line HI. Corresponding to the figure.

[0294] A pixel portion 4502, a signal line driver circuit 4503a, and a signal line driver circuit 4504 are provided on a first substrate 4501. A sealant 4505 is formed to surround the gate driver circuits 4504a and 4504b. In addition, a pixel portion 4502, signal line driver circuits 4503a and 4503b, and A second substrate 4506 is provided on the scanning line driver circuits 4504a and 4504b. The pixel portion 4502, the signal line driver circuits 4503a and 4503b, and the scanning line driver circuit 45 4504a and 4504b are a first substrate 4501, a sealant 4505, and a second substrate 4506. 4507. It is sealed together with the filler material 4507 by

[0295] A pixel portion 4502, a signal line driver circuit 4503a, and a fourth 503b and the scanning line driver circuits 4504a and 4504b each have a plurality of thin film transistors. In FIG. 21B, a thin film transistor 4510 included in a pixel portion 4502 and a signal 45, a thin film transistor 4509 included in a line driver circuit 4503a is illustrated.

[0296] The thin film transistors 4509 and 4510 are I-type transistors having an IGZO semiconductor layer and an n-type conductivity type. A thin film transistor including a buffer layer made of an oxide semiconductor layer containing n, Ga, and Zn. The thin film transistors described in any of Embodiments 1 to 5 can be used. In this embodiment mode, the thin film transistors 4509 and 4510 are n-channel thin film transistors. It is a ninja.

[0297] In addition, 4511 corresponds to a light-emitting element, and a first electrode which is a pixel electrode of the light-emitting element 4511 is The layer 4517 is electrically connected to the source electrode layer or the drain electrode layer of the thin film transistor 4510. Note that the structure of the light-emitting element 4511 is not limited to that shown in this embodiment mode. The structure of the light emitting element 4511 is adjusted according to the direction of the light to be extracted from the light emitting element 4511. The composition can be changed as appropriate.

[0298] In addition, signal line driver circuits 4503a and 4503b, scanning line driver circuits 4504a and 4504b Various signals and potentials applied to the pixel portion 4502 are It is supplied by b.

[0299] In this embodiment mode, the insulating film covering the thin film transistors 4509 and 4510 is provided with a The pixel portion 4502, the signal line driver circuits 4503a and 4503 b, or the wiring 4516 connected to the scanning line driver circuits 4504a and 4504b. The electrode layer or drain electrode layer is formed using the same material. A connection terminal 4515 is formed over the wiring 4516 using the same material as the first electrode layer 4517. do.

[0300] The connection terminal 4515 is connected to a terminal of the FPC 4518a via an anisotropic conductive film 4519. are electrically connected.

[0301] The second substrate 4506 located in the direction in which light is extracted from the light emitting element 4511 must be transparent. In this case, a glass plate, a plastic plate, a polyester film or A light-transmitting material such as an acrylic film is used.

[0302] In addition, filler 4507 can be inert gas such as nitrogen or argon, or ultraviolet-curing resin. It can be made of oil or thermosetting resin, and can be made of PVC (polyvinyl chloride), acrylic, Polyimide, epoxy resin, silicone resin, PVB (polyvinyl butyral) or EV A (ethylene vinyl acetate) can be used. In this embodiment, nitrogen is used as the filler. The substance was used.

[0303] If necessary, a polarizing plate or a circular polarizing plate (including an elliptical polarizing plate) may be provided on the light-emitting surface of the light-emitting element. Optical films such as retardation plates (λ / 4 plates, λ / 2 plates) and color filters may be provided as appropriate. In addition, the polarizing plate or the circular polarizing plate may be provided with an anti-reflection film. Anti-glare treatment can be applied to diffuse reflected light and reduce glare.

[0304] The signal line driver circuits 4503a and 4503b and the scanning line driver circuits 4504a and 4504b are A driving circuit formed of a single crystal semiconductor film or a polycrystalline semiconductor film on a separately prepared substrate is Also, only the signal line driver circuit, or a part of the signal line driver circuit, or the scanning line driver circuit may be mounted. Only the path or only a part of the path may be separately formed and mounted. In this embodiment, the structure shown in FIG. Not limited.

[0305] Next, the appearance and cross section of a liquid crystal display panel, which is one embodiment of a semiconductor device of the present invention, will be described. The following description will be given with reference to Figure 22. Figure 22 shows an IGZO semiconductor formed on a first substrate 4001. A buffer layer is formed of an oxide semiconductor layer containing In, Ga, and Zn having n-type conductivity. The thin film transistors 4010 and 4011 each having a highly reliable insulating layer and the liquid crystal element 4013 are 4005. FIG. 4006 is a top view of the panel sealed between the panel and a second substrate 4006. FIG. 22B corresponds to the cross-sectional view taken along line MN in FIGS. 22A1 and 22A2.

[0306] A pixel portion 4002 and a scanning line driver circuit 4004 are provided on a first substrate 4001. In this manner, a sealant 4005 is provided. A second substrate 4006 is provided on the path 4004. The line driver circuit 4004 is made up of a first substrate 4001, a sealant 4005, and a second substrate 4006. The liquid crystal layer 4008 is sealed together with the first substrate 4001. In a region different from the region surrounded by the material 4005, a single crystal is formed on a separately prepared substrate. A signal line driver circuit 4003 formed of a semiconductor film or a polycrystalline semiconductor film is mounted.

[0307] The method of connecting the separately formed drive circuit is not particularly limited, and may be a COG method, A wire bonding method, a TAB method, or the like can be used. FIG. 22(A2) shows an example of mounting a signal line driver circuit 4003 by the COG method. This is an example in which a signal line driver circuit 4003 is mounted by the TAB method.

[0308] A pixel portion 4002 and a scanning line driver circuit 4004 are provided on a first substrate 4001. In FIG. 22B, the thin film transistor included in the pixel portion 4002 is A transistor 4010 and a thin film transistor 4011 included in the scanning line driver circuit 4004 The following are given as examples:

[0309] The thin film transistors 4010 and 4011 are I-type transistors having an IGZO semiconductor layer and an n-type conductivity type. A thin film transistor including a buffer layer made of an oxide semiconductor layer containing n, Ga, and Zn. The thin film transistors described in any of Embodiments 1 to 5 can be used. In this embodiment, the thin film transistors 4010 and 4011 are n-channel thin film transistors. It is a ninja.

[0310] In addition, a pixel electrode layer 4030 of the liquid crystal element 4013 is connected to the thin film transistor 4010. The counter electrode layer 4031 of the liquid crystal element 4013 is electrically connected to the second substrate 40. 06. A pixel electrode layer 4030, a counter electrode layer 4031, and a liquid crystal layer 4008 are formed on the liquid crystal layer 4006. The overlapping portion corresponds to a liquid crystal element 4013. The electrode layer 4031 is provided with insulating layers 4032 and 4033 which function as alignment films. A liquid crystal layer 4008 is sandwiched between insulating layers 4032 and 4033 .

[0311] The first substrate 4001 and the second substrate 4006 may be made of glass or metal (typically, stainless steel). Stainless steel, ceramics, and plastics can be used. , FRP (Fiberglass-Reinforced Plastics) board, PV F (polyvinyl fluoride) film, polyester film, polyester film Alternatively, acrylic resin film can be used. Aluminum foil can also be used as a PVF film. A sheet having a structure sandwiched between films or polyester films can also be used.

[0312] Also, 4035 is a columnar spacer obtained by selectively etching the insulating film. In order to control the distance (cell gap) between the pixel electrode layer 4030 and the counter electrode layer 4031 A spherical spacer may also be used.

[0313] A signal line driver circuit 4003 and a scanning line driver circuit 4004 or a pixel section 4 Various signals and potentials are applied to 002 via FPC4018.

[0314] In this embodiment, the connection terminal 4015 is connected to the pixel electrode layer 4030 of the liquid crystal element 4013. The wiring 4016 is formed from the same conductive film as the thin film transistors 4010 and 4011. The gate electrode layer is formed from the same conductive film.

[0315] The connection terminal 4015 is electrically connected to a terminal of the FPC 4018 via an anisotropic conductive film 4019. are electrically connected.

[0316] In FIG. 22, a signal line driver circuit 4003 is formed separately and mounted on a first substrate 4001. However, the present embodiment is not limited to this configuration. Alternatively, a part of the signal line driver circuit or a part of the scanning line driver circuit may be formed separately and mounted. Alternatively, the circuit board may be formed separately and mounted.

[0317] FIG. 23 shows a semiconductor device using a TFT substrate 2600 manufactured according to one embodiment of the present invention. 1 shows an example of a liquid crystal display module.

[0318] FIG. 23 shows an example of a liquid crystal display module, in which a TFT substrate 2600 and an opposing substrate 2601 are connected. The substrate 2602 is fixed to the substrate 2601 by a bonding material 2602, and a pixel portion 2603 including a TFT and the like and a liquid crystal layer are disposed between the substrate 2601 and the substrate 2602. A display element 2604 and a colored layer 2605 are provided to form a display area. is necessary for color display, and in the case of the RGB method, it corresponds to each color of red, green, and blue. A colored layer is provided corresponding to each pixel. On the outside, a polarizing plate 2606, a polarizing plate 2607, and a diffusion plate 2613 are arranged. It is composed of a cathode ray tube 2610 and a reflector 2611, and a circuit board 2612 is a flexible wiring board. A wiring board 2609 is connected to the wiring circuit section 2608 of the TFT board 2600, and the controller The LCD has external circuits such as a filter circuit and a power supply circuit. The layers may be laminated with a retardation plate interposed therebetween.

[0319] The LCD module is available in TN (Twisted Nematic) mode, IPS (In-plane Switching) mode, n-Plane-Switching mode, FFS (Fringe Field Switching) switching mode, MVA (Multi-domain Vertical A alignment) mode, PVA(Patterned Vertical Alignment) mode nment) mode, ASM(Axially Symmetric aligned Micro-cell mode, OCB (Optical Compensated B) irefringence mode, FLC (Ferroelectric Liqui d Crystal) mode, AFLC (AntiFerroelectric Liq. uid Crystal) mode can be used.

[0320] Through the above steps, a highly reliable display panel can be manufactured as a semiconductor device.

[0321] This embodiment mode can be implemented in appropriate combination with the configurations described in other embodiments. It is.

[0322] (Embodiment 12) The semiconductor device according to the present invention can be applied to various electronic devices (including gaming machines). The electronic device may be, for example, a television device (television or television receiver) (also called "displays"), computer monitors, electronic paper, digital cameras, digital video digital cameras, digital photo frames, mobile phones (also called mobile phones or mobile phone devices) , portable game machines, personal digital assistants, audio playback devices, pachinko machines and other large game machines. In particular, as shown in the eighth to eleventh embodiments, the thin film transistor according to the present invention By applying the transistor to liquid crystal display devices, light-emitting devices, electrophoretic display devices, etc. The present invention can be used in the display unit of electronic devices. Specific examples are given below.

[0323] The semiconductor device of one embodiment of the present invention can be applied to electronic paper as described in Embodiment 9. Electronic paper can be used in all kinds of electronic devices that display information. For example, electronic books, postal mail, etc. can be displayed on electronic paper. Used for advertisements on trains and other vehicles, and on credit cards and other cards. An example of the electronic device is shown in FIG. 24 and FIG.

[0324] FIG. 24(A) shows a poster 1601 made of electronic paper. In the case of printed matter, the advertisements are replaced manually. By using electronic paper with a body device, advertisement display can be changed in a short time. In addition, the display is stable without distortion because thin-film transistors with good electrical characteristics are used. The poster may be configured to transmit and receive information wirelessly.

[0325] FIG. 24B shows an advertisement 1602 on a train or other vehicle. In the case of paper printouts, the advertisements are exchanged manually. By using electronic paper with a semiconductor device, advertisements can be displayed in a short time without much manpower. In addition, since thin-film transistors with good electrical characteristics are used, the display The display can be displayed in a stable manner without any distortion. It may be configured as follows.

[0326] FIG. 25 also shows an example of an electronic book 2700. For example, the electronic book 2700 is The device is made up of two housings, a housing 2701 and a housing 2703. The body 2703 is integrated with a shaft portion 2711, and the shaft portion 2711 is used as an axis for opening and closing movement. This configuration allows the device to operate like a paper book. It becomes.

[0327] A display unit 2705 is incorporated in the housing 2701, and a display unit 2707 is incorporated in the housing 2703. The display unit 2705 and the display unit 2707 are configured to display a continuous screen. Alternatively, a different screen may be displayed. For example, a text is displayed on the right display (display 2705 in FIG. 25) and An image can be displayed on the display unit 2707 in FIG.

[0328] FIG. 25 shows an example in which the housing 2701 is provided with an operation unit. 701, a power supply 2721, operation keys 2723, a speaker 2725, etc. The operation keys 2723 can be used to turn pages. The configuration may include a touch panel, a touch screen, a pointing device, etc. On the side, there are external connection terminals (earphone terminal, USB terminal, or AC adapter and USB A configuration including a terminal that can be connected to various cables such as a cable, a recording medium insertion section, etc. Furthermore, the electronic book 2700 may be configured to have a function as an electronic dictionary. This is also fine.

[0329] The electronic book 2700 may be configured to transmit and receive information wirelessly. The desired book data can be purchased and downloaded from the electronic book server. is also possible.

[0330] FIG. 26A shows an example of a television device 9600. The display unit 9603 is incorporated in the housing 9601. In addition, the stand 9605 supports the housing 9601. The display unit 9603 is the same as that shown in the eighth to eleventh embodiments. A display device having such a configuration can be applied.

[0331] The television device 9600 can be operated using an operation switch on the housing 9601 or a separate remote control. This can be done by the remote control operation device 9610. The channel and volume can be controlled by the 9609, and the display 9603 shows In addition, the remote control unit 9610 can control the video. A display portion 9607 for displaying information output from 9610 may be provided.

[0332] The television device 9600 includes a receiver and a modem. It can receive more general television broadcasts, and can also be connected to a modem via wired or wireless connection. By connecting to a network, communication can be one-way (sender to receiver) or two-way. It is also possible to communicate information (between a sender and a receiver, or between receivers).

[0333] FIG. 26B shows an example of a digital photo frame 9700. The photo frame 9700 includes a display unit 9703 built into a housing 9701. The unit 9703 is capable of displaying various images, for example images captured by a digital camera. By displaying the image data, it can function like a normal photo frame.

[0334] The Digital Photo Frame 9700 is equipped with an operation unit, external connection terminals (USB terminal, US A terminal that can be connected to various cables such as B cable, etc., and a recording medium insertion section, etc. These components may be installed on the same surface as the display unit, but they may be installed on the side or back. It is preferable to have a digital photo frame with a built-in memory card because it improves the design. A memory that stores image data taken with a digital camera is inserted into the body insertion section. The captured image data can be displayed on the display portion 9703 .

[0335] The digital photo frame 9700 may also be configured to transmit and receive information wirelessly. It is also possible to wirelessly import and display desired image data.

[0336] FIG. 27 shows an example of a digital player 2100, which is a portable audio device. The digital player 2100 includes a main body 2130, a display unit 2131, a memory unit 2132, and a , an operation unit 2133, an earphone 2134, a control unit 2137, etc. Instead of the display unit 2134, a headphone or a wireless earphone can be used. The display devices shown in the eighth to eleventh embodiments can be applied.

[0337] In addition, by using the memory unit 2132 and operating the operation unit 2133, video and audio ( The display unit 2131 has white characters on a black background. By displaying the above, power consumption can be reduced. It may be configured to be removable.

[0338] FIG. 28 shows an example of a mobile phone 1000. The mobile phone 1000 has a housing 100 In addition to the display unit 1002 incorporated in the device 1, the device 1002 also includes an operation button 1003, an external connection port 1004, The display unit 1002 includes a speaker 1005, a microphone 1006, and the like. The display device shown in the eleventh embodiment can be applied.

[0339] The mobile phone 1000 shown in FIG. 28 allows users to input information by touching the display unit 1002 with a finger or the like. In addition, operations such as making a phone call or typing an e-mail can be performed by pointing at the display unit 1002. This can be done by touching it with a

[0340] The screen of the display unit 1002 has three main modes. The first is a display mode that is mainly used for displaying images. The first mode is a display mode, the second is an input mode for inputting information such as characters, and the third mode is a display mode. This is a display + input mode that combines the display mode and the input mode.

[0341] For example, when making a call or composing an e-mail, the display unit 1002 is used for inputting characters. The main character input mode is to input characters displayed on the screen. It is preferable to display a keyboard or number buttons on most of the screen of the display unit 1002. I wish.

[0342] In addition, a sensor for detecting tilt, such as a gyro or an acceleration sensor, is installed inside the mobile phone 1000. By providing a detection device having the above configuration, the orientation of the mobile phone 1000 (portrait or landscape) can be determined and the display The screen display of the display unit 1002 can be automatically switched.

[0343] The screen mode can be changed by touching the display unit 1002 or by operating the housing 1001. This is done by operating the button 1003. Also, depending on the type of image displayed on the display unit 1002, For example, the image signal to be displayed on the display unit is a moving image. If it is data, the mode is switched to display mode, and if it is text data, the mode is switched to input mode.

[0344] In the input mode, the optical sensor of the display unit 1002 detects a signal and displays If there is no input by touch operation of the part 1002 for a certain period of time, the screen mode is changed to the input mode. Alternatively, the display mode may be switched from the normal mode to the display mode.

[0345] The display unit 1002 can also function as an image sensor. By touching the palm or fingers to the sensor 02, the palm print, fingerprint, etc. can be captured and identity authentication can be performed. In addition, the display unit may be equipped with a backlight that emits near-infrared light or a sensor that emits near-infrared light. By using a scanning light source, it is also possible to image finger veins, palm veins, etc.

[0346] This embodiment mode can be implemented in appropriate combination with the configurations described in other embodiments. It is. [Explanation of symbols]

[0347] 80 Delivery Room 81 Transport Robot 82 Cassette Room 83 Gate Valve 84 Gate Valve 85 Gate Valve 86 Gate Valve 87 Gate Valve 88 Gate Valve 89 Processing Room 90 Processing Room 91 Processing Room 92 Processing Room 93 Processing Room 94 Substrate 100 Substrates 101 Gate electrode 101a Gate electrode 101b Gate electrode 102 Gate insulating film 102a Gate insulating film 102b Gate insulating film 103 Semiconductor layer 104 Buffer Layer 104a Buffer layer 104b Buffer layer 104c Buffer layer 105 Conductive film 105a, 105b Source electrode layer and drain electrode layer 105a1 Source electrode layer 105b1 Drain electrode layer 105a2 Source electrode layer 105b2 Drain electrode layer 105c conductive layer 106 Channel Protection Layer 114a Buffer layer 114b Buffer layer 133 Semiconductor Film 134 Oxide Semiconductor Film 200 boards 201 Thin-film transistor 202 Source wiring layer 203 Gate wiring layer 204 Capacitive wiring layer 211 Insulating layer 212 Insulating layer 213 Insulating Layer 255 Electrode layer 260 Liquid crystal display element 261 Insulating Layer 262 Liquid crystal layer 263 Insulating Layer 264 Colored layer 265 Electrode layer 266 Substrate 267 Polarizing Plate 268 Polarizing Plate 301 Thin-film transistor 302 Thin-film transistor 303 Light emitting element 304 Capacitive element 305 Source wiring layer 306 Gate wiring layer 307 Power line 311 Insulating layer 312 Insulating layer 313 Insulating Layer 320 Electrode layer 321 Bulkhead 322 Electroluminescent layer 323 Electrode layer 504 Scanning line driver circuit 581 Thin Film Transistor 585 Insulation Layer 587 Electrode layer 587a Electrode layer 588 Electrode layer 589 Spherical particles 590a black area 590b White area 594 Cavity 595 Filling material 1000 Mobile Phones 1001 Case 1002 Display section 1003 Operation button 1004 External connection port 1005 Speaker 1006 Mike 1601 Poster 1602 In-car advertising 2100 Digital Player 2130 Main Unit 2131 Display section 2132 Memory section 2133 Operation unit 2134 Earphones 2137 Control Unit 2600 TFT substrate 2601 Opposing substrate 2602 Sealing material 2603 Pixel section 2604 Display element 2605 Colored layer 2606 Polarizing plate 2607 Polarizing plate 2608 Wiring circuit section 2609 Flexible wiring board 2610 cold cathode tube 2611 Reflector 2612 Circuit Board 2613 Diffuser 2700 e-books 2701 Case 2703 Case 2705 ​​Display section 2707 Display section 2711 Shaft 2721 Power supply 2723 Operation key 2725 Speaker 4001 Substrate 4002 Pixel section 4003 Signal line driver circuit 4004 Scanning line driver circuit 4005 Sealing material 4006 Substrate 4008 Liquid crystal layer 4010 Thin film transistor 4011 Thin film transistor 4013 Liquid crystal element 4015 Connection terminal 4016 Wiring 4018 FPC 4019 Anisotropic conductive film 4030 Pixel electrode layer 4031 Counter electrode layer 4032 Insulation layer 4501 Board 4502 Pixel section 4503a Signal line driver circuit 4504a Scanning line driver circuit 4505 Sealing material 4506 Board 4507 Filling material 4509 Thin-film transistor 4510 Thin-film transistor 4511 Light emitting element 4515 Connection terminal 4516 Wiring 4517 Electrode layer 4518a FPC 4519 Anisotropic conductive film 5300 Board 5301 Pixel unit 5302 Scanning line driver circuit 5303 Signal line driver circuit 5400 Board 5401 Pixel unit 5402 Scanning line driver circuit 5403 Signal line driver circuit 5404 Scanning line driver circuit 5501 Wiring 5502 Wiring 5503 Wiring 5504 Wiring 5505 Wiring 5506 Wiring 5543 nodes 5544 nodes 5571 Thin-film transistor 5572 Thin Film Transistor 5573 Thin Film Transistor 5574 Thin Film Transistor 5575 Thin Film Transistor 5576 Thin Film Transistor 5577 Thin Film Transistor 5578 Thin Film Transistor 5601 Driver IC 5602 Switches 5603a Thin Film Transistor 5603b Thin Film Transistor 5603c Thin Film Transistor 5611 Wiring 5612 Wiring 5613 Wiring 5621 Wiring 5701 Flip-flop 5703a Timing 5703b Timing 5703c Timing 5711 Wiring 5712 Wiring 5713 Wiring 5714 Wiring 5715 Wiring 5716 Wiring 5717 Wiring 5721 Signal 5803a Timing 5803b Timing 5803c Timing 5821 Signal 7001 Driving TFT 7002 Light emitting element 7003 Cathode 7004 Light-emitting layer 7005 Anode 7011 Driving TFT 7012 Light emitting element 7013 Cathode 7014 Light-emitting layer 7015 Anode 7016 Shielding membrane 7017 Conductive film 7021 Driving TFT 7022 Light emitting element 7023 Cathode 7024 Light-emitting layer 7025 Anode 7027 Conductive film 8310 Resistivity / Hall Measurement System ResiTest 9600 Television Equipment 9601 Case 9603 Display section 9605 Stand 9607 Display section 9609 Operation key 9610 Remote control device 9700 Digital Photo Frame 9701 Case 9703 Display section

Claims

1. A plurality of pixels arranged in a matrix form, At least one of the pixels includes a first transistor, a second transistor, and a capacitance element; a display device in which one of a source electrode and a drain electrode of the second transistor is electrically connected to a gate electrode of the first transistor and one of an electrode of the capacitance element, a first conductive layer having a first region functioning as a gate electrode of the first transistor and a second region functioning as one electrode of the capacitor; an oxide semiconductor layer having a region located above the first conductive layer and including a channel formation region of the first transistor; an insulating layer having a region located above the oxide semiconductor layer and overlapping with the channel formation region; a second conductive layer having a region functioning as a gate electrode of the second transistor and a region functioning as a scan line; a third conductive layer having a region functioning as one of a source electrode and a drain electrode of the second transistor, In a plan view, the insulating layer overlaps with the first region, In a plan view, the insulating layer does not overlap with the second region, the second region has a region located between the second conductive layer and the first region in a plan view, In a plan view of the pixel, the region functioning as the scanning line extends along a first direction, a width of the second region in the first direction is greater than a width of the first region in the first direction; A display device, wherein, in a plan view, the third conductive layer has a region that is arranged alongside the second region along the first direction.

2. A plurality of pixels arranged in a matrix form, At least one of the pixels includes a first transistor, a second transistor, and a capacitance element; a display device in which one of a source electrode and a drain electrode of the second transistor is electrically connected to a gate electrode of the first transistor and one of an electrode of the capacitance element, a first conductive layer having a first region functioning as a gate electrode of the first transistor and a second region functioning as one electrode of the capacitor; a first insulating layer having a region overlying the first conductive layer; an oxide semiconductor layer having a region located above the first insulating layer and including a channel formation region of the first transistor; a second insulating layer having a region located above the oxide semiconductor layer and overlapping with the channel formation region; a second conductive layer having a region functioning as a gate electrode of the second transistor and a region functioning as a scan line; a third conductive layer having a region functioning as one of a source electrode and a drain electrode of the second transistor; a fourth conductive layer having a region located above the first conductive layer and having a third region that functions as the other electrode of the capacitance element; In a plan view, the second insulating layer overlaps with the first region, In a plan view, the second insulating layer does not overlap with the second region, In a plan view, the second insulating layer does not overlap with the third region, the second region has a region located between the second conductive layer and the first region in a plan view, In a plan view of the pixel, the region functioning as the scanning line extends along a first direction, a width of the second region in the first direction is greater than a width of the first region in the first direction; A display device, wherein, in a plan view, the third conductive layer has a region that is arranged alongside the second region along the first direction.

3. A plurality of pixels arranged in a matrix form, At least one of the pixels includes a first transistor, a second transistor, and a capacitance element; a display device in which one of a source electrode and a drain electrode of the second transistor is electrically connected to a gate electrode of the first transistor and one of an electrode of the capacitance element, a first conductive layer having a first region functioning as a gate electrode of the first transistor and a second region functioning as one electrode of the capacitor; an oxide semiconductor layer having a region located above the first conductive layer and including a channel formation region of the first transistor; an insulating layer having a region located above the oxide semiconductor layer and overlapping with the channel formation region; a second conductive layer having a region functioning as a gate electrode of the second transistor and a region functioning as a scan line; a third conductive layer having a region functioning as one of a source electrode and a drain electrode of the second transistor, In a plan view, the insulating layer overlaps with the first region, In a plan view, the insulating layer does not overlap with the second region, the second region has a region located between the second conductive layer and the first region in a plan view, the third conductive layer has a region in contact with the first conductive layer, In a plan view of the pixel, the region functioning as the scanning line extends along a first direction, a width of the second region in the first direction is greater than a width of the first region in the first direction; A display device, wherein, in a plan view, the third conductive layer has a region that is arranged alongside the second region along the first direction.

4. A plurality of pixels arranged in a matrix form, At least one of the pixels includes a first transistor, a second transistor, and a capacitance element; a display device in which one of a source electrode and a drain electrode of the second transistor is electrically connected to a gate electrode of the first transistor and one of an electrode of the capacitance element, a first conductive layer having a first region functioning as a gate electrode of the first transistor and a second region functioning as one electrode of the capacitor; a first insulating layer having a region overlying the first conductive layer; an oxide semiconductor layer having a region located above the first insulating layer and including a channel formation region of the first transistor; a second insulating layer having a region located above the oxide semiconductor layer and overlapping with the channel formation region; a second conductive layer having a region functioning as a gate electrode of the second transistor and a region functioning as a scan line; a third conductive layer having a region functioning as one of a source electrode and a drain electrode of the second transistor; a fourth conductive layer having a region located above the first conductive layer and having a third region that functions as the other electrode of the capacitance element; In a plan view, the second insulating layer overlaps with the first region, In a plan view, the second insulating layer does not overlap with the second region, In a plan view, the second insulating layer does not overlap with the third region, the second region has a region located between the second conductive layer and the first region in a plan view, the third conductive layer has a region in contact with the first conductive layer, In a plan view of the pixel, the region functioning as the scanning line extends along a first direction, a width of the second region in the first direction is greater than a width of the first region in the first direction; A display device, wherein, in a plan view, the third conductive layer has a region that is arranged alongside the second region along the first direction.

5. In claim 2 or claim 4, the first insulating layer has a function as a gate insulating layer of the first transistor and a function as a dielectric film of the capacitance element.

Images