Array substrate and display panel

Abstract

This solves the problem that the storage capacitor in existing OLED panels cannot be set large. [Solution] The substrate 10 includes a first thin film transistor 01 arranged in the pixel region, and a first electrode plate 301 and a second electrode plate 302 arranged in a capacitor region, which are different layers and arranged opposite each other, the first thin film transistor 01 includes a first active layer 012, a first gate layer 017, and a first source-drain layer 204, the first capacitor 30 further includes a first dielectric layer 303 arranged between the first electrode plate 301 and the second electrode plate 302, the first dielectric layer 303 includes a first sub-dielectric layer 3031 having a high dielectric constant and a second sub-dielectric layer 3032 having a low dielectric constant, and the orthogonal projection of the active layer on the substrate is positioned within the orthogonal projection of the second sub-dielectric layer 3032, thereby increasing the capacitance value of the first active layer 012 and reducing the risk of failure of the first active layer 012.

Description

[Technical field]

[0001] The present invention relates to the field of display technology, in particular to the manufacture of display devices, and in particular to array substrates and display panels. [Background technology]

[0002] Panel components such as OLED (Organic Light Emitting Diode) have a simple structure, low production costs, high energy efficiency, and are flexible, making them suitable for a wide range of applications.

[0003] Here, the pixel driving circuit of a panel such as an OLED generally includes a storage capacitor for storing a gray-scale voltage for determining the driving current, and if the storage capacitor is set too small, the luminance of the light-emitting device will decrease. However, if the capacitor is made larger by setting a two-layer or multi-layer capacitor structure, the number of process lanes of the panel will increase, and if the relative area of ​​the capacitor electrode plate is increased, the occupied area of ​​the subpixel will increase, which will have a negative impact on high-resolution products.

[0004] Therefore, the storage capacitor of existing OLED panels cannot be set large, and improvement is urgently needed. Summary of the Invention [Problem to be solved by the invention]

[0005] SUMMARY OF THE PRESENT EMBODIMENT An object of the present invention is to provide an array substrate and a display panel for solving the problem that the storage capacitor in the existing OLED panel cannot be set large. [Means for solving the problem]

[0006] An array substrate provided in an embodiment of the present invention includes: a substrate on which a pixel region and a capacitor region are defined; a first thin film transistor disposed on the substrate in the pixel region, the first thin film transistor including a first active layer, a first gate layer disposed on a side of the first active layer closer to the substrate or farther from the substrate, and a first source-drain layer disposed on a side of the first active layer farther from the substrate and electrically connected to the first active layer; and a first capacitor including a first electrode plate and a second electrode plate disposed in different layers and opposite to each other, the first electrode plate and the second electrode plate being disposed in the capacitor region, the first capacitor further including a first dielectric layer disposed between the first electrode plate and the second electrode plate, the first dielectric layer including a first sub-dielectric layer and a second sub-dielectric layer disposed on a side of the first sub-dielectric layer closer to the first active layer, the second sub-dielectric layer being disposed in the pixel region and the capacitor region; The dielectric constant of the first sub-dielectric layer is greater than the dielectric constant of the second sub-dielectric layer, and an orthogonal projection of the first active layer on the substrate is disposed within an orthogonal projection of the second sub-dielectric layer on the substrate.

[0007] In one embodiment, the composition material of the first dielectric sub-layer includes at least one of alumina and zirconia, and the composition material of the second dielectric sub-layer includes silicon oxide.

[0008] In one embodiment, the first gate layer is disposed on a side of the first active layer farther from the substrate, the first electrode plate and the first gate layer are disposed in the same layer, a composition material of the first electrode plate is the same as a composition material of the first gate layer, and the second electrode plate is disposed on a side of the first electrode plate farther from the substrate or closer to the substrate.

[0009] In one embodiment, the second electrode plate is disposed on a side of the first electrode plate that is farther from the substrate, the second electrode plate is disposed between the first electrode plate and the first source / drain layer, or the second electrode plate and the first source / drain layer are disposed in the same layer.

[0010] In one embodiment, the second electrode plate is disposed on a side of the first electrode plate closer to the substrate, the first thin film transistor further includes a gate insulating layer disposed between the first active layer and the first gate layer, the gate insulating layer is disposed opposite the first gate layer, and the first dielectric layer and the gate insulating layer are disposed in the same layer.

[0011] In one embodiment, the array substrate further includes a light-shielding layer disposed on a side of the first active layer closer to the substrate, the second electrode plate is disposed on a side of the first electrode plate closer to the substrate, and the second electrode plate and the light-shielding layer are disposed in the same layer.

[0012] In one embodiment, the first gate layer is disposed on a side of the first active layer closer to the substrate, the first electrode plate and the first gate layer are disposed in the same layer, a composition material of the first electrode plate is the same as a composition material of the first gate layer, and the second electrode plate is disposed on a side of the first electrode plate farther from the substrate.

[0013] In one embodiment, the first thin film transistor is a double-gate thin film transistor, and the double-gate thin film transistor includes a first sub-gate layer arranged on a side of the first active layer farther from the substrate, and a second sub-gate layer arranged on a side of the first active layer closer to the substrate.

[0014] In one embodiment, the first electrode plate and the first sub-gate layer are disposed in the same layer, the first electrode plate and the first sub-gate layer are made of the same composition material, and the second electrode plate is disposed on the side of the first electrode plate farther from the substrate or closer to the substrate; Alternatively, the first electrode plate and the second sub-gate layer are arranged in the same layer, the first electrode plate and the second sub-gate layer are made of the same composition material, and the second electrode plate is arranged on the side of the first electrode plate farther from the substrate or closer to the substrate.

[0015] In one embodiment, the substrate further defines a non-display area, the array substrate further includes a second thin film transistor, the second thin film transistor is disposed in the non-display area, there is a gap between the orthogonal projection of the second thin film transistor on the substrate and the orthogonal projection of the first thin film transistor on the substrate, the second thin film transistor includes a second active layer, the first active layer is disposed on a side of the second active layer closer to the substrate, a first sub-gate insulating layer and a second gate layer are disposed on the second active layer from a side farther from the substrate, a second sub-gate insulating layer, a third sub-gate insulating layer and a first gate layer are disposed on the first active layer from a side farther from the substrate, a fourth sub-gate insulating layer is disposed on a side of the second active layer closer to the substrate, a composition material of the first sub-gate insulating layer is the same as a composition material of the third sub-gate insulating layer, and a composition material of the second sub-gate insulating layer is the same as a composition material of the fourth sub-gate insulating layer.

[0016] In one embodiment, the second sub-dielectric layer is further disposed in the non-display area, and an orthogonal projection of the second active layer on the substrate is disposed within an orthogonal projection of the second sub-dielectric layer on the substrate.

[0017] A display panel provided in an embodiment of the present invention includes an array substrate according to any one of the above embodiments, a metal adapter layer disposed on a side of the first thin film transistor away from the substrate, and a pixel layer disposed on a side of the metal adapter layer away from the substrate, wherein the metal adapter layer electrically connects the first source drain layer and the pixel layer.

[0018] The array substrate and the display panel provided in the embodiment of the present invention include a substrate on which a pixel area and a capacitor area are defined; a first thin film transistor disposed in the pixel region on the substrate, the first thin film transistor including: a first active layer; a first gate layer disposed on a side of the first active layer closer to the substrate or a side farther from the substrate; and a first source-drain layer disposed on a side of the first active layer farther from the substrate and electrically connected to the first active layer; a first capacitor including a first electrode plate and a second electrode plate arranged in different layers facing each other, (the first electrode plate and the second electrode plate are arranged in the capacitor area), the first capacitor further including a first dielectric layer arranged between the first electrode plate and the second electrode plate, the first dielectric layer including a first sub-dielectric layer and a second sub-dielectric layer arranged on a side of the first sub-dielectric layer closer to the first active layer, (the second sub-dielectric layer is arranged in the pixel area and the capacitor area); Effect of the Invention

[0019] According to the present invention, the dielectric constant of the first sub-dielectric layer is set to be greater than the dielectric constant of the second sub-dielectric layer, thereby increasing the capacitance value of the first capacitor, and the orthogonal projection of the active layer on the substrate is positioned within the orthogonal projection of the second sub-dielectric layer on the substrate, thereby reducing the risk of failure of the first active layer. [Brief description of the drawings]

[0020] Hereinafter, the present invention will be described in more detail with reference to the drawings. Of course, the described embodiments are only some of the embodiments of the present invention, and are not all of the embodiments. Based on the embodiments of the present invention, all other embodiments that a person skilled in the art can come up with without making creative efforts are included in the protection scope of the present invention. [Figure 1] FIG. 2 is a schematic cross-sectional view of one of nine display panels provided in an embodiment of the present invention. [Diagram 2] FIG. 2 is a schematic cross-sectional view of one of nine display panels provided in an embodiment of the present invention. [Diagram 3] FIG. 2 is a schematic cross-sectional view of one of nine display panels provided in an embodiment of the present invention. [Figure 4] FIG. 2 is a schematic cross-sectional view of one of nine display panels provided in an embodiment of the present invention. [Diagram 5] FIG. 2 is a schematic cross-sectional view of one of nine display panels provided in an embodiment of the present invention. [Figure 6] FIG. 2 is a schematic cross-sectional view of one of nine display panels provided in an embodiment of the present invention. [Figure 7] FIG. 2 is a schematic cross-sectional view of one of nine display panels provided in an embodiment of the present invention. [Figure 8] FIG. 2 is a schematic cross-sectional view of one of nine display panels provided in an embodiment of the present invention. [Figure 9] FIG. 2 is a schematic cross-sectional view of one of nine display panels provided in an embodiment of the present invention. [Figure 10a] FIG. 2 is a schematic diagram illustrating one scene of a method for manufacturing a display panel provided in an embodiment of the present invention. [Figure 10b] FIG. 2 is a schematic diagram illustrating one scene of a method for manufacturing a display panel provided in an embodiment of the present invention. [Figure 10c] FIG. 2 is a schematic diagram illustrating one scene of a method for manufacturing a display panel provided in an embodiment of the present invention. [Figure 11a]FIG. 2 is a schematic diagram illustrating a scene of another display panel manufacturing method provided in an embodiment of the present invention. [Figure 11b] FIG. 2 is a schematic diagram illustrating a scene of another display panel manufacturing method provided in an embodiment of the present invention. [Figure 11c] FIG. 2 is a schematic diagram illustrating a scene of another display panel manufacturing method provided in an embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0021] The following clearly and completely describes the technical solutions of the embodiments of the present invention in conjunction with the drawings of the embodiments of the present invention. Of course, the described embodiments are only some of the embodiments of the present invention, and are not all of the embodiments. Based on the embodiments of the present invention, all other embodiments that a person skilled in the art can come up with without making creative efforts are included in the protection scope of the present invention.

[0022] In the present specification, the orientation or positional relationship indicated by terms such as "upper", "lower", "nearer", and "farther" is based on the orientation or positional relationship shown in the drawings, for example, "upper" refers only to the upper surface of the object, and specific designations such as directly above, diagonally above, or above the upper surface may refer to the object being above a horizontal level. The above-mentioned orientation or positional relationship is merely for the purpose of facilitating and simplifying the description of the present invention, and is not intended to indicate or suggest that the devices or components referred to have a particular orientation, are configured, or must operate in a particular orientation, and thus should not be construed as a limitation of the present invention.

[0023] In addition, the drawings show only relatively strict structures and processes related to the present invention, and details unrelated to the present invention are omitted, and the drawings are presented for the purpose of simplifying the drawings to clarify the key points of the invention, and are not intended to show that the actual devices and methods are the same as those in the drawings, and are not intended to limit the actual devices and methods.

[0024] The present invention provides an array substrate and a display panel including the array substrate, the display panel and the array substrate including, but not limited to, the following embodiments and combinations between the following embodiments:

[0025] 1 to 9, a display panel 100 and an array substrate 200 included therein include a display area A1 and a non-display area A2, and include a substrate 10, a thin film transistor 20, and a first capacitor 30. The thin film transistor 20 is disposed on the substrate 10 and disposed corresponding to at least one of the display area A1 and the non-display area A2, and includes an active layer 201, a gate layer 202 disposed on a side of the active layer 201 closer to the substrate 10 or a side farther from the substrate 10, and a source / drain layer 204 disposed on a side of the active layer 201 farther from the substrate 10 and electrically connected to the active layer 201. The first capacitor 30 is disposed on the substrate 10 and corresponds to the display area A1, and includes a first electrode plate 301 and a second electrode plate 302, which are different layers and arranged opposite to each other, and a first dielectric layer 303 arranged between the first electrode plate 301 and the second electrode plate 302. The first dielectric layer 303 includes the first dielectric layer 303, a first sub-dielectric layer 3031, and a second sub-dielectric layer 3032 arranged on a side of the first sub-dielectric layer 3031 closer to the active layer 201. The dielectric constant of the first sub-dielectric layer 3031 is larger than the dielectric constant of the second sub-dielectric layer 3032, and the orthogonal projection of the active layer 201 on the substrate 10 is disposed within the orthogonal projection of the second sub-dielectric layer 3032 on the substrate 10.

[0026] Here, as shown in FIG. 2, the display area A1 can be defined into a pixel area A11 and a capacitor area A12. The display area A1 is provided with a transistor (i.e., a first thin film transistor 01) disposed in the pixel area A11 and for driving light emission from a sub-pixel, and a corresponding storage capacitor (i.e., a first capacitor 30) disposed in the capacitor area A12. It can be understood that FIG. 1, FIG. 3 to FIG. 9 are diagrams illustrating only the display area A1, and FIG. 2 is diagrams illustrating a non-display area A2 disposed around the display area A1 in comparison with FIG. 1, FIG. 3 to FIG. 7, and the transistor in the display area A1 in FIG. 2 is specifically the first thin film transistor 01, and the transistor in the non-display area A2 in FIG. 2 is specifically the second thin film transistor 02.

[0027] It should be noted that there are two possible interpretations of "the orthogonal projection of the active layer 201 on the substrate 10 is located within the orthogonal projection of the second sub-dielectric layer 3032 on the substrate 10". (1) When the thin film transistor 20 includes at least a first thin film transistor 01, as shown in Figures 1 and 3 to 9, the second sub-dielectric layer 3032 extends further from the capacitor region to a location disposed in the pixel region A11, and the orthogonal projection of the first active layer 012 on the substrate 10 in the first thin film transistor 01 is disposed within the orthogonal projection of the second sub-dielectric layer 3032 on the substrate 10. (2) When the thin film transistor 20 includes at least a second thin film transistor 02, as shown in FIG. 2, the second sub-dielectric layer 3032 extends further from the capacitor area to be disposed in the non-display area A2, and the orthogonal projection of the second active layer 011 on the substrate 10 in the second thin film transistor 02 is disposed within the orthogonal projection of the second sub-dielectric layer 3032 on the substrate 10.

[0028] 1 and 3 to 9, the relative positional relationship between the first thin film transistor 01 and the first capacitor 30 will be described as an example. The first thin film transistor 01 includes a first active layer 012 (included in the active layer 201), a first gate layer 017 (included in the gate layer 202) arranged on the side of the first active layer 012 closer to the substrate 10 or on the side farther from the substrate 10, and a first source / drain layer 2041 (included in the source / drain layer 204) arranged on the side of the first active layer 012 farther from the substrate 10 and electrically connected to the first active layer 012.

[0029] Specifically, as shown in FIG. 1 to FIG. 7, the substrate 10 may include a glass substrate 101, a flexible substrate 102, and a barrier layer 103 arranged in a laminated manner. The composition material of the glass substrate 101 may include at least one of glass and quartz, but is not limited thereto. The composition material of the flexible substrate 102 may include, but is not limited to, polyimide. The flexible substrate 102 may include two layers of flexible material and a buffer material disposed between them. The composition material of the barrier layer 103 may include, but is not limited to, at least one of silicon nitride, silicon oxide, and silicon oxynitride, and is used to prevent the diffusion of impurity ions and the penetration of moisture and outside air, and can perform a surface flattening function.

[0030] Here, as shown in FIG. 1 to FIG. 7, the display panel 100 may include a plurality of thin film transistors 20 arranged on a substrate 10 and electrically connected, and light emission of the display panel 100 can be realized by loading an electric signal. Specifically, each thin film transistor 20 may include an active layer 201 for realizing on and off, and the composition material of the active layer 201 may include amorphous silicon, polycrystalline silicon or an oxide semiconductor, and the polycrystalline silicon may include low-temperature polysilicon, and the oxide semiconductor may include any of oxides of titanium (Ti), hafnium (Hf), zirconium (Zr), aluminum (Al), tantalum (Ta), germanium (Ge), zinc (Zn), gallium (Ga), tin (Sn) or indium (In) or their composite oxides. Here, the active layer 201 manufactured using low-temperature polysilicon technology can have a higher electron mobility because it has a higher charging speed. The active layer 201 fabricated using amorphous silicon or oxide can have a low leakage current to reduce leakage from the thin film transistor 20 causing interference to the signal. Additionally, the active layer 201 may include a channel region and doped regions disposed on either side of the channel region, the doped regions being more conductive and less resistive than the channel region.

[0031] Specifically, as shown in FIG. 1 to FIG. 7, the pixel driving circuit in the display panel 100 includes a plurality of first thin film transistors 01, and further includes a storage capacitor for storing a gray scale voltage to determine a driving current. The first capacitor 30 in this embodiment is used to configure the above-mentioned storage capacitor. The first capacitor 30 may include a first electrode plate 301 and a second electrode plate 302 arranged in different layers facing each other, and a first dielectric layer 303 arranged between them. Here, the capacitance value of the first capacitor 30 may be equal to ε*S / (4πkd), where ε is the dielectric constant of the first dielectric layer 303, S is the facing area of ​​the first electrode plate 301 and the second electrode plate 302, d is the distance between the first electrode plate 301 and the second electrode plate 302, and k is an electrostatic force constant.

[0032] In this embodiment, it can be understood that the first dielectric layer 303 of the first capacitor 30 is arranged to include a first sub-dielectric layer 3031 and a second sub-dielectric layer 3032 arranged in a stacked manner, and the dielectric constant of the first sub-dielectric layer 3031 is arranged to be larger than the dielectric constant of the second sub-dielectric layer 3032. Compared with only arranging the second sub-dielectric layer 3032 having a small dielectric constant or other film layer arranged between both electrode plates, arranging the first dielectric layer 303 having a large dielectric constant can effectively increase the dielectric constant ε of the first dielectric layer 303, thereby increasing the capacitance value of the first capacitor 30 and reducing the risk of reducing the luminance of the light-emitting device. At the same time, in this embodiment, taking the first active layer 012 as an example, a second sub-dielectric layer 3032 having a small dielectric constant is arranged on the side of the first sub-dielectric layer 3031 closer to the first active layer 012, and the orthogonal projection of the first active layer 012 on the substrate 10 is arranged within the orthogonal projection of the second sub-dielectric layer 3032 on the substrate 10, thereby effectively preventing impurities such as hydrogen elements from diffusing from above to the first active layer 012, and reducing the risk of the first active layer 012 failing.

[0033] Here, the content of hydrogen element in the second sub-dielectric layer 3032 is considered to be lower than the content of hydrogen element in the first sub-dielectric layer 3031, and the second sub-dielectric layer 3032 is considered to be more stable than the first sub-dielectric layer 3031. The second sub-dielectric layer 3032 may be composed of silicon element, oxygen element, and metal element, for example, but is not limited to, silicon oxide. The dielectric constant of the first sub-dielectric layer 3031 may be greater than 4, and the composition material of the first sub-dielectric layer 3031 may include at least one of alumina and zirconia, but is not limited to these.

[0034] In one embodiment, as shown in Figures 1 to 4 and 9, taking the first gate layer 017 in the gate layer 202 as an example, the first gate layer 017 is arranged on the side of the first active layer 012 farther from the substrate 10, the first electrode plate 301 and the first gate layer 017 are arranged in the same layer, the composition material of the first electrode plate 301 and the composition material of the first gate layer 017 are the same, and the second electrode plate 302 is arranged on the side of the first electrode plate 301 farther from the substrate 10 (see Figures 1 to 3) or the side closer to the substrate 10 (see Figure 4).

[0035] Here, the composition material of the gate layer 202 (including the first gate layer 017) may include one or more metals selected from molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), tungsten (W), and copper (Cu), but is not limited thereto. As shown in Figures 1 and 2, in this embodiment, only the thin film transistor 20 having a top gate structure is shown as an example. Specifically, a gate insulating layer 203 may be disposed between the gate layer 202 and the active layer 201, and the gate insulating layer 203 is used to insulate the gate layer 202 and the active layer 201, so that the orthogonal projection of the gate insulating layer 203 on the substrate 10 exceeds at least the orthogonal projection of the gate layer 202 on the substrate 10, and of course, the gate insulating layer 203 can also extend beyond the active layer 201 and the buffer layer 50. Here, the composition material of the gate insulating layer 203 may include, but is not limited to, silicon compounds, metal oxides, etc., and may include at least one of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, tantalum oxide, hafnium oxide, zirconium oxide, and titanium oxide.

[0036] Here, the composition material of the source drain layer 204 (including the first source drain layer 2041) can refer to the composition material of the gate layer 202. They may be the same or different. The array substrate 200 may further include a wiring portion 11 disposed in the same layer as the source drain layer 204, and the wiring portion 11 may be electrically connected to the first source drain layer 2041 to enable signal transmission.

[0037] 1 to 4, since the gate layer 202 (including the first gate layer 017) has good conductivity, the phrase "the first electrode plate 301 and the first gate layer 017 are disposed in the same layer" in this embodiment can be understood to mean that the first electrode plate 301 and the first gate layer 017 are manufactured at the same time using the same material. Since the first active layer 012 is disposed between the first gate layer 017 and the buffer layer 50, the horizontal position of the first gate layer 017 is higher than the horizontal position of the first electrode plate 301 in the thickness direction of the film layer. Furthermore, when the gate insulating layer 203 is formed by patterning and disposed opposite the first gate layer 017, generally, the entire layer of the gate insulating film for the later manufacturing of the gate insulating layer 203 can be formed first, and then the patterned first gate layer 017 and the first electrode plate 301 are simultaneously formed on the gate insulating film, and then the gate insulating film is etched, and the first gate layer 017 and the first electrode plate 301 are shielded to avoid the portions of the gate insulating film corresponding to both being etched and remaining, so that the gate insulating layer 203 corresponding to the lower part of the first gate layer 017 and the first pad part 3041 corresponding to the lower part of the first gate plate 301 are formed. The thickness of the first pad part 3041 is close to the thickness of the gate insulating layer 203.

[0038] Specifically, as shown in FIGS. 1 to 3, the second electrode plate 302 is disposed on the side of the first electrode plate 301 farther from the substrate 10 (here, the specific position of the film layer where the second electrode plate 302 is located is not limited), and the first dielectric layer 303 is also disposed on the side of the first active layer 012 farther from the substrate 10. Since the first sub-dielectric layer 3031 having a large dielectric constant is disposed farther from the substrate 10 than the second sub-dielectric layer 3032 having a small dielectric constant, the first sub-dielectric layer 3031 and the first active layer 012 are disposed on the side of the first active layer 012 farther from the substrate 10. Since the second sub-dielectric layer 3032 is disposed between the first active layer 3031 and the second sub-dielectric layer 3032 and the composition material of the second sub-dielectric layer 3032 contains silicon oxide and the first sub-dielectric layer 3031 has a large dielectric constant (the composition material may include, but is not limited to, alumina and zirconia), the second sub-dielectric layer 3032 is considered to have more stable and dense characteristics, and the risk of impurities such as hydrogen elements diffusing from above into the first active layer 3032 can be reduced compared to the case where only the first sub-dielectric layer 3031 is disposed.

[0039] Specifically, as described above, when the gate insulating layer 203 is disposed opposite the first gate layer 017 as shown in Figures 1 to 3, the orthogonal projection of the first active layer 012 on the substrate 10 exceeds the orthogonal projection of the gate insulating layer 203 on the substrate 10, and therefore both ends of the first active layer 012 are not shielded by the gate insulating layer 203. In order to reduce the effect of the diffusion of hydrogen elements described above on the first active layer 012, it is necessary to dispose a second sub-dielectric layer 3032 that completely exceeds the first active layer 012 on the side of the first gate layer 017 away from the substrate 10.

[0040] The hydrogen element may be generated during the manufacturing process of other film layers in the array substrate or the corresponding display panel, or may be generated from the external environment, for example, water vapor in the air.

[0041] Furthermore, based on the top gate structure, as shown in Figures 1 to 3, the array substrate 200 further includes a light-shielding layer 40 disposed on the side of the first active layer 012 closer to the substrate 10, and the light-shielding layer 40 may be disposed opposite to the first active layer 012, and is used to block the irradiation or reflection of light to the first active layer 012, thereby reducing the risk of the first active layer 012 failing. The composition material of the light-shielding layer 40 may include one or more metals selected from molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), tungsten (W), and copper (Cu). Furthermore, in order to prevent the penetration of unwanted components such as impurities or moisture, a buffer layer 50 may be disposed between the light-shielding layer 40 and the first active layer 012, and the composition material of the buffer layer 50 may include at least one of silicon nitride (SiNx) and silicon oxide (SiOx), but is not limited thereto.

[0042] In one embodiment, as shown in FIG. 2 , the thin film transistor 20 includes a second thin film transistor 02 disposed in the non-display area A2 and a first thin film transistor 01 disposed in a pixel area A11 in the display area A1, the active layer 201 includes a second active layer 011 of the second thin film transistor 02 and a first active layer 012 of the first thin film transistor 01, the second active layer 011 and the first active layer 012 are disposed in different layers, there is a gap between the orthogonal projection of the second thin film transistor 02 on the substrate 10 and the orthogonal projection of the first thin film transistor 01 on the substrate 10, the first active layer 012 is disposed in the orthogonal projection of the second thin film transistor 02 on the substrate 10, and the substrate 10 is a pixel region in which the first active layer 011 is disposed. 10, a first sub-gate insulating layer 013 and a second gate layer 014 are arranged in order from the side furthest from the substrate 10 of the second active layer 011, a second sub-gate insulating layer 015, a third sub-gate insulating layer 016 and a first gate layer 017 are arranged in order from the side furthest from the substrate 10 of the first active layer 012, and a fourth sub-gate insulating layer 018 is arranged on the side closer to the substrate 10 of the second active layer 011, a composition material of the first sub-gate insulating layer 013 is the same as a composition material of the third sub-gate insulating layer 016, and a composition material of the second sub-gate insulating layer 015 is the same as a composition material of the fourth sub-gate insulating layer 018.

[0043] In this case, based on the fact that the gate layer 202 includes the second gate layer 014 and the first gate layer 017 which are arranged independently, the first electrode plate 301, the second gate layer 014, and the first gate layer 017 may be arranged in the same layer, and the three composition materials are all the same.

[0044] Here, the composition material of the second active layer 011 and the composition material of the first active layer 012 may be different so that the second thin film transistor 02 and the first thin film transistor 01 are used to form different circuits, for example, they are used to form a gate drive circuit and a pixel drive circuit, respectively. In this case, since the second thin film transistor 02 is disposed in the non-display area A2 and it is considered that the second active layer 011 of the second thin film transistor 02 is not irradiated with light, it is not necessary to dispose the light-shielding layer 40 below the second active layer 011. Therefore, in this embodiment, "the second active layer 011 and the first active layer 012 are disposed in different layers" can be understood to mean that the second active layer 011 and the first active layer 012 are separately manufactured from different materials. For example, here, the first active layer 012 can be formed in the corresponding region first, and then the second active layer 011 can be formed in another region, and in order to avoid contact between the two materials, the first active layer 012 can be formed first, and before forming the second active layer 011, the first insulating material (i.e., the composition material for forming the above-mentioned second sub-gate insulating layer 015, the fourth sub-gate insulating layer 018, and the first pad height portion 3041) can be formed on the entire surface first, and here, the second gate layer 014 and the first gate layer 017 can also be formed simultaneously using the same material. As can be seen by combining the above, the first electrode plate 301, the second gate layer 014, and the first gate layer 017 can be formed simultaneously, i.e., arranged in the same layer. Similarly, in order to avoid contact between the material of the second gate layer 014 and the material of the second active layer 011, a second insulating material (i.e., a composition material for forming the above-mentioned first sub-gate insulating layer 013, third sub-gate insulating layer 016, and second pad portion 3042 disposed on the first pad portion 3041) can be formed over the entire surface before forming the second gate layer 014.

[0045] Similarly, when the gate insulating layer 203 is formed by patterning and disposed opposite to the first gate layer 017, generally, a full-layer gate insulating film for the later fabrication of the gate insulating layer 203 is first formed, and then the patterned first gate layer 017 (including the second gate layer 014 and the first gate layer 017) and the first electrode plate 301 are simultaneously formed on the gate insulating film, and then the gate insulating film is etched, and the first gate layer 017 and the first electrode plate 301 are simultaneously formed on the gate insulating film. By shielding 01, the portions of the gate insulating layer corresponding to both are prevented from being etched away and left unetched, and a gate insulating layer 203 corresponding to the area below the first gate layer 017 (including a first sub-gate insulating layer 013 corresponding to the area below the second gate layer 014 and a third sub-gate insulating layer 016 corresponding to the area below the first gate layer 017) is formed, and a second pad portion 3042 corresponding to the area below the first electrode plate 301 is formed, the thickness of which is close to the thickness of the third sub-gate insulating layer 016.

[0046] 2, the second thin film transistor 02 and the first thin film transistor 01 are only described as having a top gate structure, but at least one of them may have a bottom gate structure or a double gate structure. Here, the bottom gate structure and the double gate structure can be referred to in the description below.

[0047] In one embodiment, taking a top gate structure as an example, the second electrode plate is disposed on the side of the first electrode plate 302 farther from the substrate, and as shown in FIG. 1 and FIG. 2, the second electrode plate 302 is disposed between the first electrode plate 301 and the first source drain layer 204, or as shown in FIG. 3, the second electrode plate 302 and the first source drain layer 204 are disposed in the same layer.

[0048] Specifically, as shown in Figures 1 to 3, the array substrate 200 may further include an interlayer insulating layer 205 disposed between the first gate layer 017 and the first source drain layer 204. The interlayer insulating layer 205 is used to insulate the first gate layer 017 and the first source drain layer 204, and may extend over the entire film layer to achieve planarization. The composition material of the interlayer insulating layer 205 may include at least one of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, tantalum oxide, hafnium oxide, zirconium oxide, and titanium oxide, but is not limited thereto.

[0049] As can be seen, as shown in Figures 1 and 2, the second electrode plate 302 in this embodiment may be disposed between the first electrode plate 301 and the first source drain layer 204, for example, after forming the first electrode plate 301 and the first gate layer 017 in the first thin film transistor 01, and before forming the first source drain layer 204, the second electrode plate 302 can be formed alone (its composition material may include metal, alloy, and must also be disposed under the interlayer insulating layer 205), so that the distance between the first electrode plate 301 and the second electrode plate 302 is smaller, and the capacitance value of the first capacitor 30 can be increased. At this time, the second sub-dielectric layer 3032 and the first sub-dielectric layer 3031 may be disposed on the first electrode plate 301 in order.

[0050] It can be understood that, as shown in FIG. 3, the second electrode plate 302 and the first source drain layer 204 in this embodiment may be disposed in the same layer to save the number of process passes. At the same time, since the second electrode plate 302 is disposed on the interlayer insulating layer 205, the first sub-dielectric layer 3031 disposed on the second sub-dielectric layer 3032 may be multiplexed from the interlayer insulating layer 205. At this time, the material and structural properties of the interlayer insulating layer 205 need to be compatible with the material and structural properties of both the interlayer insulating layer 205 and the first sub-dielectric layer 3031, and specifically, the above can be referred to.

[0051] Specifically, based on the example of a top gate structure, as shown in FIG. 4, when the second electrode plate 302 is disposed on the side of the first electrode plate 301 far from the substrate 10 (here, the specific position of the film layer where the second electrode plate 302 is located is not limited), the first dielectric layer 303 is also disposed on the side of the first active layer 012 far from the substrate 10. Furthermore, based on the presence of the gate insulating layer 203, as shown in FIG. 4, the first dielectric layer 303 (i.e., the first pad portion 3041 corresponding to the lower side of the first electrode plate 301 described above) and the gate insulating layer 203 are disposed in the same layer. Furthermore, the first dielectric layer 303 is formed so as to extend at least from the gate insulating layer 203 to a portion disposed on the side of the first electrode plate 301 close to the substrate 10, that is, the first pad portion 3041 and the gate insulating layer 203 may be integrally formed.

[0052] Here, the gate insulating layer 203 can also extend from above the first active layer 012 to the side of the first electrode plate 301 close to the substrate 10 in order to form the first dielectric layer 303, so that it is possible to avoid manufacturing the first dielectric layer 303 alone and to save the number of process passes. Here, the second electrode plate 302 may be disposed in the same layer as the light-shielding layer 40, that is, the composition materials of both are the same and can be manufactured at the same time, further saving the number of process passes. Furthermore, the second electrode plate 302 is formed so as to extend from the light-shielding layer 40 to the side where it is disposed opposite the first electrode plate 301. The buffer layer 50 disposed on the light-shielding layer 40 may be multiplexed as the first dielectric layer 303 since it is disposed between the first electrode plate 301 and the second electrode plate 302.

[0053] Here, as shown in FIG. 4, the first dielectric layer 303 in this embodiment may be disposed at least one between the first active layer 012 and the buffer layer 50, or between the buffer layer 50 and the light-shielding layer. Furthermore, since the buffer layer 50 and the gate insulating layer 203 are in contact with the lower surface and the upper surface of the first active layer 012, respectively, it is considered that the protective effect of the first active layer 012 of both is equivalent. Therefore, it is not limited to which of the two is the first sub-dielectric layer 3031 and which is the second sub-dielectric layer 3032, and the selection of the materials of both must be compatible with the characteristics of the corresponding first sub-dielectric layer 3031 or second sub-dielectric layer 3032. Considering the operational characteristics of the gate insulating layer 203 and the buffer layer 50 themselves, the buffer layer 50 can be multiplexed as the second sub-dielectric layer 3032, and the gate insulating layer 203 can be multiplexed as the first sub-dielectric layer 3031.

[0054] In one embodiment, as shown in FIG. 5 and FIG. 6, the first thin film transistor 01 may also be a bottom gate structure, that is, the first gate layer 017 is disposed on the side of the first active layer 012 closer to the substrate 10, the first electrode plate 301 and the first gate layer 017 are disposed in the same layer, the composition material of the first electrode plate 301 is the same as the composition material of the first gate layer 017, and the second electrode plate 302 is disposed on the side of the first electrode plate 301 farther from the substrate 10.

[0055] 5 and 6 can be set large so that the orthogonal projection of the first active layer 012 on the substrate 10 is located within the orthogonal projection of the first gate layer 017 on the substrate 10, and the above-mentioned light-shielding layer can be omitted. Similarly, a gate insulating layer 203 can be disposed between the first gate layer 017 and the first active layer 012.

[0056] Based on the first electrode plate 301 and the first gate layer 017 being arranged in the same layer, the second electrode plate 302 can be arranged in a film layer arranged above the first gate layer 017. For example, as shown in FIG. 5, the second electrode plate 302 may be arranged on the first source drain layer 204. Based on this, a first dielectric layer 303 can be arranged between the first source drain layer 204 and the second electrode plate 302 to both form the first capacitor 30 and insulate the first source drain layer 204 and the second electrode plate 302. Furthermore, the gate insulating layer 203 can also both form the first dielectric layer 303 and insulate the first gate layer 017 and the first active layer 012. Here, the first sub-dielectric layer 3031 is disposed between the first source drain layer 204 and the second electrode plate 302, and the gate insulating layer 203 is multiplexed as the second sub-dielectric layer 3032, but this is not limited to the above (because the first sub-dielectric layer 3031 and the second sub-dielectric layer 3032 are released from the upper and lower surfaces of the first active layer 012, respectively). In addition, as shown in FIG. 6, for example, the second electrode plate 302 may be disposed in the same layer as the first source drain layer 204. Based on this, the gate insulating layer 203 may be disposed to include the first sub-dielectric layer 3031 and the second sub-dielectric layer 3032, and may be disposed to bring the second sub-dielectric layer 3032 closer to the first active layer 012.

[0057] In one embodiment, as shown in Figures 7 and 8, the first thin film transistor 01 is a double-gate thin film transistor, which includes a first sub-gate layer 2021 arranged on a side of the first active layer 012 farther from the substrate 10, and a second sub-gate layer 2022 arranged on a side of the first active layer 012 closer to the substrate 10.

[0058] Here, the double-gate thin film transistor has two gates (i.e., the first sub-gate layer 2021 and the second sub-gate layer 2022), which are a control gate and a feedback gate, respectively. By applying a constant voltage between the control gate (one of the first sub-gate layer 2021 and the second sub-gate layer 2022) and the source, the current flow between the source and the drain in the double-gate thin film transistor can be controlled. Meanwhile, by applying a constant voltage between the feedback gate (the other of the first sub-gate layer 2021 and the second sub-gate layer 2022) and the source, the current flow between the control gate and the source can be controlled, thereby achieving the control of the entire double-gate thin film transistor. The double-gate thin film transistor has the advantages of low power consumption, high speed, etc.

[0059] In one embodiment, as shown in FIG. 7, the first electrode plate 301 and the first sub-gate layer 2021 are disposed in the same layer, the first electrode plate 301 and the first sub-gate layer 2021 are made of the same composition material, and the second electrode plate 302 is disposed on the side of the first electrode plate 301 farther from the substrate 10 or closer to the substrate 10 (specifically, refer to the description of the related embodiment in the above-mentioned FIG. 1 to FIG. 5, and FIG. 7 only shows that the second electrode plate 302 is disposed on the side of the first electrode plate 301 farther from the substrate 10). ), or as shown in FIG. 8, the first electrode plate 301 and the second sub-gate layer 2022 are arranged in the same layer, the first electrode plate 301 and the second sub-gate layer 2022 are made of the same composition material, and the second electrode plate 302 is arranged on the side of the first electrode plate 301 farther from the substrate 10 or closer to the substrate 10 (specifically, refer to the description of the related embodiments in FIG. 1 to FIG. 5 above, and FIG. 8 only shows that the second electrode plate 302 is arranged on the side of the first electrode plate 301 farther from the substrate 10).

[0060] Here, even if the first electrode plate 301 is arranged in the same layer as the first sub-gate layer 2021 or the second sub-gate layer 2022, when the second electrode plate 302 is arranged on the side of the first electrode plate 301 closer to the substrate 10, it is considered that the second electrode plate 302 is arranged between the substrate 10 and the first electrode plate 301, and the first dielectric layer 303 is arranged between the first electrode plate 301 and the second electrode plate 302.

[0061] As shown in Figures 1 to 9, the display panel 100 provided by the present invention includes, in addition to any one of the array substrates 200 described above, a metal adapter layer 60 arranged on the side of the first thin film transistor 01 (the first source drain layer 204 thereof) farther from the substrate 10, and a pixel layer (including an anode layer 70) arranged on the side of the metal adapter layer 60 farther from the substrate 10, and the metal adapter layer 60 electrically connects the first source drain layer 204 and the pixel layer (the anode layer 70 thereof).

[0062] Of course, in another alternative embodiment, as shown in FIG. 9, both the first electrode plate 301 and the second electrode plate 302 may be disposed on the first gate layer 017, for example, the first electrode plate 301 may be disposed in the same layer as the first source drain layer 2041 (included in the source drain layer 204), and the second electrode plate 302 may be disposed in the same layer as the metal adapter layer 60. Correspondingly, the second planar layer 802 disposed between the first source drain layer 204 and the metal adapter layer 60 may be disposed to include a first sub-dielectric layer 3031 and a second sub-dielectric layer 3032, and the second sub-dielectric layer 3032 may be disposed closer to the first active layer 012.

[0063] Specifically, as shown in FIGS. 1 to 9, the display panel 100 may further include a first planar layer 801 that is covered and planarized on the metal adapter layer 60. The thickness of the first planar layer 801 is usually large and is used to provide a flat surface for the deposition of the anode layer 70. The composition material of the first planar layer 801 may include at least one of inorganic insulating materials, organic insulating materials such as polyacrylate resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene ether resin, polyphenylene sulfide resin, benzocyclobutene, and photosensitive materials, but is not limited thereto. In addition, the display panel 100 may further include a pixel definition layer 90 disposed on the first planar layer 801. The pixel definition layer 90 may form a plurality of openings, and a corresponding anode layer 70 may be disposed in each opening. In addition, a second planar layer 802 may be disposed between the metal adapter layer 60 and the first source / drain layer 204, and the thickness of the second planar layer 802 is usually large, and is used to provide a flat surface for the deposition of the metal adapter layer 60. The composition material of the second planar layer 802 may refer to the description of the composition material of the first planar layer 801 described above.

[0064] 3 and 5, based on the first electrode plate 301 and the first source drain layer 204 (included in the source drain layer 204) in this embodiment being arranged in the same layer, the second electrode plate 302 can be modified to be arranged in the same layer as the metal adapter layer 60, that is, the second electrode plate 302 and the metal adapter layer 60 can be simultaneously manufactured on the second flat layer 802, thereby saving the number of process passes. As described above, the second flat layer 802 may include a first sub-dielectric layer 3031 and a second sub-dielectric layer 3032.

[0065] Of course, compared with the embodiment shown in Fig. 9, the first electrode plate 301 can be modified to be disposed in the same layer as the anode layer 70. In order to save the number of process passes, the first electrode plate 301 and the anode layer 70 disposed in the same layer can be manufactured simultaneously, and at this time, it can be understood that the first flat layer 801 may be disposed to include the above-mentioned first sub-dielectric layer 3031 and second sub-dielectric layer 3032.

[0066] In the above, only the possible arrangements of the first capacitor 30 are described, but in reality, a second capacitor (not shown) may be arranged on the substrate 10 based on the first capacitor 30, and the second capacitor includes a third electrode plate and a fourth electrode plate arranged in a different layer and facing each other, and a second dielectric layer arranged between the third electrode plate and the fourth electrode plate. Based on the specific film layers of the light-shielding layer 40, the metal adapter layer 60, and the first thin film transistor 01 described above, unlike the arrangement of the first capacitor 30 described above, the second dielectric layer in the second capacitor may be composed only of a film layer between the third electrode plate and the fourth electrode plate, not like the arrangement of the first dielectric layer. For example, the third electrode plate may be disposed in the same layer as one of the light-shielding layer 40, the metal adapter layer 60, the gate layer 202, and the source-drain layer 204; the fourth electrode plate may be disposed in the same layer as the other of the light-shielding layer 40, the metal adapter layer 60, the gate layer 202, and the source-drain layer 204; or the fourth electrode plate may be disposed in the same layer as a film layer disposed between the source-drain layer 204 and the gate layer 202.

[0067] In order to better describe the above-mentioned film layer structure of the display panel, the present invention further provides a method for manufacturing a display panel, the method includes but is not limited to the following steps and the combinations between the following steps. Hereinafter, the schematic diagrams of the scenes shown in Figures 10(a), 10(b), and 10(c) are described in combination with the schematic diagrams of the scenes shown in Figures 11(a), 11(b), and 11(c), which are respectively used to form a display panel as shown in Figures 1 and 2.

[0068] S01: Provide one substrate. Specifically, as shown in FIGS. 10(a) to 10(c) and 11(a) to 11(c), the specific structure and composition materials of the substrate 10 can be referred to the relevant descriptions above.

[0069] S02: The substrate is cleaned, and a metal material is deposited to a thickness of 1000 angstroms to 10000 angstroms, and then patterned to form a light-shielding layer. Specifically, as shown in Figures 10(a) to 10(c) and 11(a) to 11(c), the composition material of the light-shielding layer 40 can refer to the relevant descriptions above, and may further include at least one of Mo, Cr, Al, Cu, and Ti, but is not limited to these.

[0070] S03: A buffer layer is formed by depositing a single layer or multiple layers of an inorganic material on the light-shielding layer. 10(a) to 10(c) and 11(a) to 11(c), the above-mentioned related descriptions can be referred to for the composition materials of the buffer layer 50. Furthermore, the buffer layer 50 may be a single-layer silicon nitride (SiNx) film layer, a single-layer silicon oxide (SiOx) film layer, or a silicon nitride (SiNx) film layer and a silicon oxide (SiOx) film layer arranged in a stacked manner, and the thickness of the buffer layer 50 is 1000 angstroms to 5000 angstroms.

[0071] S04: Deposit and pattern a metal oxide on the buffer layer to form a first active layer. Specifically, as shown in FIG. 10(a) to FIG. 10(c) and FIG. 11(a) to FIG. 11(c), the composition material of the first active layer 012 can refer to the above related description. Furthermore, the metal oxide here may include at least one of IGTO, ITZO, and IGZTO, but is not limited thereto. The thickness of the first active layer 012 may be 100 angstroms to 1000 angstroms. In particular, as shown in FIG. 5, it is considered that the first active layer 012 in the first thin film transistor 01 is formed at this time.

[0072] S05: Deposit an inorganic material on the first active layer to form a gate insulating layer. Here, as shown in FIG. 10(a) to FIG. 10(c) and FIG. 11(a) to FIG. 11(c), the inorganic material film layer for forming the gate insulating layer 203 may include, but is not limited to, a single silicon nitride (SiNx) film layer, a single silicon oxide (SiOx) film layer, or a silicon nitride (SiNx) film layer and a silicon oxide (SiOx) film layer arranged in a laminated manner. As shown in FIG. 10(a) to FIG. 10(c), the thickness of the gate insulating layer 203 may be 1000 angstroms to 3000 angstroms. As shown in FIG. 11(a) to FIG. 11(c), at this time, the gate insulating layer 203 (second sub-gate insulating layer 015) in the first thin film transistor 01 is formed, and the thickness may be 500 angstroms to 2000 angstroms, and at the same time, the fourth sub-gate insulating layer 018 as described above is also formed. 11(a) to 11(c), after step S05, the method further includes forming a second active layer 011 in the second thin film transistor 02, and the thickness and composition material of the second active layer 011 can refer to the description of the first active layer 012 above. Furthermore, after forming the second active layer 011, the method further includes forming a first sub-gate insulating layer 013 in the second thin film transistor 02, and the thickness of the first sub-gate insulating layer 013 may be 1000 angstroms to 3000 angstroms, and at the same time, the third sub-gate insulating layer 016 as described above is also formed.

[0073] S06: A layer of a metal material for forming a gate layer is deposited on the film layer of an inorganic material for forming a gate insulating layer. Specifically, the composition materials of the gate layer 202 (including the first gate layer 017 in Figures 10(a) to 10(c) and 11(a) to 11(c) and the second gate layer 014 in Figures 11(a) to 11(c)) may refer to the relevant descriptions above. Furthermore, the composition materials of the gate layer 202 may include at least one of Mo, Al, Cu, and Ti, but are not limited to these. The thickness of the gate layer 202 may be 2000 angstroms to 8000 angstroms.

[0074] S07: In order to form a gate layer by using a yellow light process, a metal material for forming a gate layer is first etched, and then, with the metal pattern of the gate layer being self-aligned, an inorganic material for forming a gate insulating layer is etched to form a gate insulating layer 203. As shown in Figures 10(a) to 10(c) and 11(a) to 11(c), it can be seen that the gate insulating layer 203 exists only under the metal pattern having the gate layer 202, and the inorganic materials in the remaining areas are all removed by etching. In addition, to increase the conductivity of the exposed oxide area in the active layer 201, a plasma treatment can be selected to be performed on the entire surface. As mentioned above, the first electrode plate 301 and the gate layer 202 can be formed by the same patterning, and similarly, as shown in Figures 10(a) to 10(c), a corresponding first pad part 3041 is formed below the first electrode plate 301 beforehand, which is disposed in the same layer as the gate insulating layer 203. In particular, as shown in Figures 11(a) to 11(c), this step can simultaneously form the second gate layer 014 in the second thin film transistor 02 and the first gate layer 017 in the first thin film transistor 01. Similarly, as shown in Figure 5, a corresponding first pad portion 3041 is formed below the first electrode plate 301 beforehand, the corresponding first pad portion 3041 being disposed in the same layer as the fourth sub-gate insulating layer 018 and the second sub-gate insulating layer 015, and a corresponding second pad portion 3042 is formed in the same layer as the first sub-gate insulating layer 013 and the third sub-gate insulating layer 016.

[0075] S08: Deposit an insulating material to form a second sub-dielectric layer. 10(a) to 10(c) and 11(a) to 11(c), the composition material of the second sub-dielectric layer 3032 may include, but is not limited to, silicon oxide, and the thickness of the second sub-dielectric layer 3032 may be 500 angstroms to 2000 angstroms.

[0076] S09: Deposit an insulating material on the second sub-dielectric layer to form a first sub-dielectric layer. Here, as shown in Figures 10(a) to 10(c) and 11(a) to 11(c), the dielectric constant of the first sub-dielectric layer 3031 may be greater than 4, and the composition material of the first sub-dielectric layer 3031 may refer to the above related descriptions. As shown in Figure 4, the thickness of the first sub-dielectric layer 3031 may be 800 angstroms to 3000 angstroms. As shown in Figure 5, the thickness of the first sub-dielectric layer 3031 may be 500 angstroms to 3000 angstroms.

[0077] S10: Deposit and pattern a layer of metallic material on the first sub-dielectric layer to form a second electrode plate. 10(a) to 10(c) and 11(a) to 11(c), the composition material of the second electrode plate 302 may refer to the above related description, and may include, for example, at least one of Mo, Al, Cu, and Ti, but is not limited thereto. The thickness of the second electrode plate 302 may be 2000 angstroms to 8000 angstroms.

[0078] S11: Depositing an insulating material on the second electrode plate and the first sub-dielectric layer to form an interlayer insulating layer, and forming a first through hole penetrating at least the interlayer insulating layer. Here, as shown in Figures 10(a) to 10(c) and 11(a) to 11(c), the interlayer insulating layer 205 may include, but is not limited to, a single layer of silicon nitride (SiNx) film layer, a single layer of silicon oxide (SiOx) film layer, or a silicon nitride (SiNx) film layer and a silicon oxide (SiOx) film layer arranged in a stacked manner.

[0079] S12: A metal material is deposited on the interlayer insulating layer and in the first through hole, and is patterned to form a source / drain layer. Here, the composition material of the source drain layer 204 (including the first source drain layer 2041 shown in FIG. 10(a) to FIG. 10(c) and FIG. 11(a) to FIG. 11(c) and the second source drain layer 2042 shown in FIG. 11(a) to FIG. 11(c)) may refer to the above related description, and may include, for example, at least one of Mo, Al, Cu, and Ti, but is not limited thereto. The thickness of the source drain layer 204 may be 2000 angstroms to 8000 angstroms, and the source drain layer 204 may be electrically connected to the active layer 201 and the light-shielding layer 40 via the metal material in the first through hole.

[0080] S13: Deposit an insulating material on the source / drain layer and the interlayer insulating layer to form a passivation layer. Here, the passivation layer may include, but is not limited to, a single silicon nitride (SiNx) film layer, a single silicon oxide (SiOx) film layer, or a silicon nitride (SiNx) film layer and a silicon oxide (SiOx) film layer arranged in a stacked manner. The thickness of the passivation layer may be 1000 angstroms to 5000 angstroms. Furthermore, as shown in Figures 10(a) to 10(c) and 11(a) to 11(c), a second flat layer 802 may be formed on the passivation layer, and the composition material of the second flat layer 802 may refer to the above related description. Furthermore, a second through hole may be formed in the second flat layer 802.

[0081] S14: Form an anode layer on the passivation layer. 10(a) to 10(c) and 11(a) to 11(c), the composition materials of the anode layer 70 may refer to the above related descriptions. As described above, before forming the anode layer 70, the second planar layer 802, the metal adapter layer 60, the first planar layer 801 and the pixel definition layer 90 may be formed on the passivation layer.

[0082] Specifically, the above display panel 100 can be used as a liquid crystal display panel, a Mini LED (sub-millimeter light emitting diode), a Micro LED (micro light emitting diode display), or an organic light emitting semiconductor.

[0083] The array substrate and the display panel provided in the embodiment of the present invention include a substrate on which a pixel area and a capacitor area are defined; a first thin film transistor disposed in the pixel region on the substrate, the first thin film transistor including: a first active layer; a first gate layer disposed on a side of the first active layer closer to the substrate or a side farther from the substrate; and a first source-drain layer disposed on a side of the first active layer farther from the substrate and electrically connected to the first active layer; a first capacitor including a first electrode plate and a second electrode plate arranged in different layers facing each other, (the first electrode plate and the second electrode plate are arranged in the capacitor area), the first capacitor further including a first dielectric layer arranged between the first electrode plate and the second electrode plate, the first dielectric layer including a first sub-dielectric layer and a second sub-dielectric layer arranged on a side of the first sub-dielectric layer closer to the first active layer, (the second sub-dielectric layer is arranged in the pixel area and the capacitor area);

[0084] The structures of the array substrate and the display panel provided by the embodiments of the present invention have been described in detail above, and specific examples are applied in this specification to explain the principles and embodiments of the present invention, and the description of the above examples is only used to help understand the technical solutions of the present invention and its core ideas. It is still possible to modify the technical solutions described in the above embodiments, or to replace some of their technical features with equivalents. These modifications or replacements do not take the nature of the corresponding technical solutions out of the scope of the technical solutions in each embodiment of the present invention.

Claims

1. An array substrate, a substrate on which a pixel area and a capacitor area are defined; a first thin film transistor disposed in the pixel region on the substrate, the first thin film transistor including: a first active layer; a first gate layer disposed on a side of the first active layer closer to the substrate or a side farther from the substrate; a gate insulating layer disposed between the first gate layer and the first active layer; and a first source-drain layer disposed on a side of the first active layer farther from the substrate and electrically connected to the first active layer, wherein an orthogonal projection of the first active layer on the substrate exceeds an orthogonal projection of the gate insulating layer on the substrate; a first capacitor including a first electrode plate and a second electrode plate which are different layers and arranged opposite to each other, the first electrode plate and the second electrode plate being arranged in the capacitor region, the first capacitor further including a first dielectric layer arranged between the first electrode plate and the second electrode plate, the first dielectric layer including a first sub-dielectric layer and a second sub-dielectric layer arranged on a side of the first sub-dielectric layer closer to the first active layer, the second sub-dielectric layer being arranged in the pixel region and the capacitor region; a dielectric constant of the first sub-dielectric layer is greater than a dielectric constant of the second sub-dielectric layer, and an orthogonal projection of the first active layer on the substrate is disposed within an orthogonal projection of the second sub-dielectric layer on the substrate; 1. An array substrate comprising:

2. The composition material of the first sub-dielectric layer includes at least one of alumina and zirconia; The composition material of the second sub-dielectric layer includes silicon oxide; 2. The array substrate according to claim 1.

3. the first gate layer is disposed on a side of the first active layer remote from the substrate; The first electrode plate and the first gate layer are disposed in the same layer, a composition material of the first electrode plate is the same as a composition material of the first gate layer, and the second electrode plate is disposed on a side of the first electrode plate farther from the substrate or closer to the substrate.

2. The array substrate according to claim 1.

4. the second electrode plate is disposed on a side of the first electrode plate farther from the substrate, the second electrode plate is disposed between the first electrode plate and the first source / drain layer, or the second electrode plate and the first source / drain layer are disposed in the same layer; 4. The array substrate according to claim 3.

5. the second electrode plate is disposed on a side of the first electrode plate closer to the substrate, and the gate insulating layer is disposed opposite the first gate layer; The first dielectric layer and the gate insulating layer are disposed in the same layer.

4. The array substrate according to claim 3.

6. the array substrate further includes a light-shielding layer disposed on a side of the first active layer closer to the substrate, the second electrode plate being disposed on a side of the first electrode plate closer to the substrate; The second electrode plate and the light-shielding layer are disposed in the same layer.

6. The array substrate according to claim 5.

7. the first gate layer is disposed on a side of the first active layer closer to the substrate, the first electrode plate and the first gate layer are disposed in the same layer, a composition material of the first electrode plate is the same as a composition material of the first gate layer, and the second electrode plate is disposed on a side of the first electrode plate farther from the substrate; 2. The array substrate according to claim 1.

8. the first thin film transistor is a double-gate thin film transistor, the double-gate thin film transistor including a first sub-gate layer disposed on a side of the first active layer farther from the substrate, and a second sub-gate layer disposed on a side of the first active layer closer to the substrate; 2. The array substrate according to claim 1.

9. The first electrode plate and the first sub-gate layer are disposed in the same layer, the first electrode plate and the first sub-gate layer are made of the same composition material, and the second electrode plate is disposed on a side of the first electrode plate farther from the substrate or closer to the substrate; Alternatively, the first electrode plate and the second sub-gate layer are disposed in the same layer, the first electrode plate and the second sub-gate layer are made of the same composition material, and the second electrode plate is disposed on the side of the first electrode plate farther from the substrate or closer to the substrate.

9. The array substrate according to claim 8.

10. The substrate further defines a non-display area, and the array substrate further includes a second thin film transistor; the second thin film transistor is disposed in the non-display area, there is a gap between an orthogonal projection of the second thin film transistor on the substrate and an orthogonal projection of the first thin film transistor on the substrate, the second thin film transistor includes a second active layer, and the first active layer is disposed on a side of the second active layer closer to the substrate; a first sub-gate insulating layer and a second gate layer are disposed in this order from the side of the second active layer farthest from the substrate, a second sub-gate insulating layer, a third sub-gate insulating layer and a first gate layer are disposed in this order from the side of the first active layer farthest from the substrate, and a fourth sub-gate insulating layer is disposed on a side of the second active layer close to the substrate; a composition material of the first sub-gate insulating layer is the same as a composition material of the third sub-gate insulating layer, and a composition material of the second sub-gate insulating layer is the same as a composition material of the fourth sub-gate insulating layer; 10. The array substrate according to claim 1, wherein the first and second electrodes are arranged in a first direction.

11. the second sub-dielectric layer is further disposed in the non-display area, and an orthogonal projection of the second active layer on the substrate is disposed within an orthogonal projection of the second sub-dielectric layer on the substrate.

11. The array substrate according to claim 10.

12. A display panel, An array substrate according to any one of claims 1 to 9, a metal adapter layer disposed on a side of the first thin film transistor away from the substrate; a pixel layer disposed on a side of the metal adapter layer away from the substrate; the metal adapter layer electrically connects the first source-drain layer and the pixel layer; A display panel characterized by:

Images