Semiconductor Device

Abstract

To provide a high-quality semiconductor device.SOLUTION: A semiconductor device of an embodiment includes an input end, an output end, a control end, and a first and a second transistor between the input end and the output end. The first transistor comprises a first end, a second end, a first gate, and a first body. The second transistor comprises a third end, a fourth end, a second gate, and a second body. The third end is connected to the second end. The semiconductor device further includes a first resistor connected to the first end, a second resistor between the first resistor and the second end, a third resistor connected to the third end, a fourth resistor between the third resistor and the fourth end, a first diode between the first body and a node connecting the third resistor and the fourth resistor, and a second diode between the second body and a node connecting the first resistor and the second resistor.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The embodiments relate to a semiconductor device. [Background technology]

[0002] 2. Description of the Related Art Switch circuits used in portable terminals and the like are known. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] U.S. Pat. No. 10,715,133 Summary of the Invention [Problem to be solved by the invention]

[0004] To provide a high-quality semiconductor device. [Means for solving the problem]

[0005] a first resistor connected to the first end, a second resistor connected between the first resistor and the second end, a third resistor connected to the third end, a fourth resistor connected between the third resistor and the fourth end, a first diode having an anode connected to the first body and a cathode connected to a node connecting the third resistor and the fourth resistor, and a second diode having an anode connected to the second body and a cathode connected to a node connecting the first resistor and the second resistor. [Brief description of the drawings]

[0006] [Figure 1] 1 is a block diagram showing an example of the configuration of a wireless device including a switch circuit according to a first embodiment. [Diagram 2] FIG. 2 is a diagram showing an example of a circuit configuration of a switch circuit according to the first embodiment. [Diagram 3] FIG. 2 is a diagram for explaining the structure of a transistor in the switch circuit according to the first embodiment. [Figure 4] 5A and 5B are diagrams for explaining various bias voltages used in the switch circuit according to the first embodiment. [Diagram 5] 3 is a diagram for explaining various currents flowing through the switch circuit according to the first embodiment while the switch circuit is in an off state. FIG. [Figure 6] FIG. 4 is a diagram showing an example of a circuit configuration of a switch circuit according to a comparative example of the first embodiment. [Figure 7]FIG. 11 is a diagram showing an example of a graph illustrating the relationship between a high-frequency power associated with a high-frequency signal and the bias voltages of a first terminal, a gate, and a body of a transistor when a high-frequency signal is input to a switch circuit according to the first embodiment while the switch circuit is in an off state. [Figure 8] FIG. 11 is a diagram showing an example of a circuit configuration of a switch circuit according to a second embodiment. [Figure 9] FIG. 11 is a diagram showing an example of a circuit configuration of a switch circuit according to a third embodiment. [Figure 10] FIG. 13 is a diagram showing an example of a circuit configuration of a switch circuit according to a fourth embodiment. [Figure 11] FIG. 13 is a diagram showing an example of a circuit configuration of a switch circuit according to a fifth embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0007] Hereinafter, the embodiments will be described with reference to the drawings. In the following description, components having the same function and configuration are given common reference symbols. When multiple components having a common reference symbol are to be distinguished from each other, a subscript is added to the common reference symbol. When no particular distinction is required between multiple components, only the common reference symbol is given to the multiple components, and no subscript is added.

[0008] Each functional block can be realized by either hardware or software, or a combination of both. Moreover, it is not essential that each functional block is distinguished as described below. For example, some functions may be executed by a functional block other than the illustrated functional block. Furthermore, the illustrated functional block may be further divided into smaller functional sub-blocks. Moreover, the names of each functional block and each component in the following description are for convenience and do not limit the configuration and operation of each functional block and each component.

[0009] First Embodiment The semiconductor device according to the first embodiment will be described below. Hereinafter, the semiconductor device will also be referred to as a switch circuit 1.

[0010] [Configuration example] (1) Wireless equipment FIG. 1 is a block diagram showing an example of the configuration of a wireless device WD including a switch circuit 1 according to the first embodiment. The wireless device WD is, for example, a smartphone, a feature phone, a mobile terminal (e.g., a tablet terminal), a personal computer, a game device, a router, a base station, etc. The wireless device WD transmits and receives signals using communication standards such as LTE (registered trademark) (Long Term Evolution) and / or Wifi. Reference symbols 1a, 1b, 1c, and 1d shown in FIG. 1 will be referred to in the description of the following embodiments.

[0011] In addition to the switch circuit 1, the wireless device WD includes, for example, an antenna ANT, switch circuits 2, 3, and 4, signal processing circuits 5 and 6, and a control circuit .

[0012] The antenna ANT receives radio frequency signals from other devices (eg, base stations or other radio devices) and also enables the transmission of radio frequency signals from the radio device WD to other devices.

[0013] The control circuit 7 transmits control signals CNT to, for example, the switch circuits 1, 2, 3, and 4 and to the signal processing circuits 5 and 6. For each of the switch circuits 1, 2, 3, and 4, whether the switch circuit is in an on state or an off state is controlled by the control signal CNT that the switch circuit receives from the control circuit 7. While a certain switch circuit is in an on state, the switch circuit is capable of transmitting a signal between the first terminal and the second terminal of the switch circuit. On the other hand, while a certain switch circuit is in an off state, the switch circuit does not transmit a signal between the first terminal and the second terminal of the switch circuit. Each of the signal processing circuits 5 and 6 processes a signal based on the control signal CNT that it receives from the control circuit 7.

[0014] A first terminal of the switch circuit 1 is connected to the antenna ANT, and a second terminal of the switch circuit 1 is connected to the signal processing circuit 5. The switch circuit 1 receives a control signal CNT1 from the control circuit 7. While the switch circuit 1 is in an on state based on the control signal CNT1, the switch circuit 1 transmits, for example, a high-frequency signal received by the wireless device WD via the antenna ANT to the signal processing circuit 5.

[0015] A first terminal of the switch circuit 2 is connected to a signal path between the switch circuit 1 and the signal processing circuit 5. A second terminal of the switch circuit 2 is, for example, grounded.

[0016] The switch circuit 2 receives a control signal CNT2 from the control circuit 7. For example, the switch circuit 2 is in an on state based on the control signal CNT2 while the switch circuit 1 is in an off state. While in the on state, the switch circuit 2 fixes the potential of the signal path between the switch circuit 1 and the signal processing circuit 5 to the ground potential.

[0017] The signal processing circuit 5 receives the high-frequency signal transmitted via the switch circuit 1, and executes various processes on the high-frequency signal based on a control signal CNT3 received from the control circuit .

[0018] A first end of the switch circuit 3 is connected to the antenna ANT, and a second end of the switch circuit 3 is connected to the signal processing circuit 6. The switch circuit 3 receives, for example, a control signal CNT2 from the control circuit 7. While the switch circuit 3 is in an on state based on the control signal CNT2, the switch circuit 3 transmits, for example, a high-frequency signal received by the wireless device WD via the antenna ANT to the signal processing circuit 6. The frequency band of the high-frequency signal transmitted by the switch circuit 3 is different from, for example, the frequency band of the high-frequency signal transmitted by the switch circuit 1. The switch circuit 1 and the switch circuit 3 are selectively turned on under the control of, for example, the control circuit 7.

[0019] A first end of the switch circuit 4 is connected to a signal path between the switch circuit 3 and the signal processing circuit 6. A second end of the switch circuit 4 is, for example, grounded. The switch circuit 4 receives, for example, a control signal CNT1 from the control circuit 7. For example, the switch circuit 4 is in an on state based on the control signal CNT1 while the switch circuit 3 is in an off state. While in the on state, the switch circuit 4 fixes the potential of the signal path between the switch circuit 3 and the signal processing circuit 6 to the ground potential.

[0020] The signal processing circuit 6 receives the high-frequency signal transmitted via the switch circuit 3, and executes various processes on the high-frequency signal based on a control signal CNT4 received from the control circuit .

[0021] In the above, the switch circuits 1 and 3 are described as transmitting high-frequency signals received by the wireless device WD from other devices. The switch circuits 1 and 3 are not limited to this. Either of the switch circuits 1 and 3 may transmit high-frequency signals that the wireless device WD transmits to other devices.

[0022] The following description will focus on switch circuit 1, but the same description as for switch circuit 1 can also be applied to each of switch circuits 2, 3, and 4.

[0023] (2) Switch circuit Fig. 2 shows an example of a circuit configuration of the switch circuit 1 according to the first embodiment. In Fig. 2, various voltages VD, VG, and VB are shown, and these voltages may be referred to in the description of the effects described later.

[0024] The switch circuit 1 includes, for example, 2n (n is a natural number) transistors M1, M2, M3, M4, M5, M6, . . . , M(2n-1), and M(2n). Each of these transistors is, for example, a field effect transistor (FET) such as an n-channel metal oxide semiconductor (MOS) transistor. In FIG. 2, a first end and a second end of the switch circuit 1 are indicated as a terminal IN and a terminal OUT, respectively.

[0025] The switch circuit 1 further includes resistors Rg1, Rg2, Rg3, Rg4, Rg5, Rg6, . . ., Rg(2n-1), and Rg(2n). The switch circuit 1 further includes resistors Rds(1,1), Rds(1,2), Rds(2,1), Rds(2,2), Rds(3,1), Rds(3,2), Rds(4,1), Rds(4,2), Rds(5,1), Rds(5,2), Rds(6,1), Rds(6,2), . . ., Rds(2n-1,1), Rds(2n-1,2), Rds(2n,1), and Rds(2n,2).

[0026] The resistance values ​​of the resistors Rds(1,1), Rds(1,2), Rds(2,1), Rds(2,2), Rds(3,1), Rds(3,2), Rds(4,1), Rds(4,2), Rds(5,1), Rds(5,2), Rds(6,1), Rds(6,2), . . ., Rds(2n-1,1), Rds(2n-1,2), Rds(2n,1), and Rds(2n,2) are, for example, substantially the same R1. Below, a description will be given of the case where the resistance values ​​of these resistors Rds are substantially the same.

[0027] Between the terminal IN and the terminal OUT, the transistors M1, M2, M3, M4, M5, M6, . . . , M(2n-1), and M(2n) are connected in series. More specifically, it is as follows. A first terminal of the transistor M1 is connected to the terminal IN, and a first terminal of the transistor M2 is connected to the second terminal of the transistor M1. A first terminal of the transistor M3 is connected to the second terminal of the transistor M2, and a first terminal of the transistor M4 is connected to the second terminal of the transistor M3. The same applies to the connection relationship of the transistors M4, M5, M6, . . . , M(2n-1), and M(2n), and the terminal OUT is connected to the second terminal of the transistor M(2n).

[0028] One end of the resistor Rg1 is connected to the gate of the transistor M1 (hereinafter, may also be referred to as the control end). One end of the resistor Rg2 is connected to the gate of the transistor M2. One end of the resistor Rg3 is connected to the gate of the transistor M3. The same applies to the resistors Rg4, Rg5, Rg6, . . . , Rg(2n-1), and Rg(2n). The other end of the resistor Rg1, the other end of the resistor Rg2, the other end of the resistor Rg3, . . . , the other end of the resistor Rg(2n-1), and the other end of the resistor Rg(2n) are connected to a node to which the signal GB is input. In FIG. 2, a control end to which the signal GB is input to the switch circuit 1 is shown. The signal GB is, for example, the control signal CNT1 described with reference to FIG. 1. The signal GB can be changed between a high (H) level and a low (L) level, for example, by the control circuit 7. In this specification, when the term level is used, it refers to a voltage level unless otherwise specified.

[0029] One end of resistor Rds(1,1) is connected to a first end of transistor M1, one end of resistor Rds(1,2) is connected to the other end of resistor Rds(1,1), and a second end of transistor M1 is connected to the other end of resistor Rds(1,2). One end of resistor Rds(2,1) is connected to a first end of transistor M2, one end of resistor Rds(2,2) is connected to the other end of resistor Rds(2,1), and a second end of transistor M2 is connected to the other end of resistor Rds(2,2). One end of resistor Rds(3,1) is connected to a first end of transistor M3, one end of resistor Rds(3,2) is connected to the other end of resistor Rds(3,1), and a second end of transistor M3 is connected to the other end of resistor Rds(3,2). The same is true for resistances Rds(4,1), Rds(4,2), Rds(5,1), Rds(5,2), Rds(6,1), Rds(6,2), ..., Rds(2n-1,1), Rds(2n-1,2), Rds(2n,1), and Rds(2n,2).

[0030] The switch circuit 1 further includes diodes D(1,1), D(2,1), D(3,1), D(4,1), D(5,1), D(6,1), . . . , D(2n-1,1), and D(2n,1). Each of the diodes referred to herein with the symbol D is, for example, a diode formed of a PN junction.

[0031] The anode of diode D(1,1) is connected to the body (hereinafter may be referred to as the backgate) of transistor M1, and the cathode of diode D(1,1) is connected to the gate of transistor M1. The anode of diode D(2,1) is connected to the body of transistor M2, and the cathode of diode D(2,1) is connected to the gate of transistor M2. The anode of diode D(3,1) is connected to the body of transistor M3, and the cathode of diode D(3,1) is connected to the gate of transistor M3. The same is true for diodes D(4,1), D(5,1), D(6,1), ..., D(2n-1,1), and D(2n,1).

[0032] The switch circuit 1 further includes diodes D(1,2), D(2,2), D(3,2), D(4,2), D(5,2), D(6,2), . . . , D(2n-1,2), and D(2n,2) as components of a feedback circuit. The following explanation applies to each case where the integer k is 1 to n.

[0033] The anode of the diode D(2k-1,2) is connected to the body of the transistor M(2k-1), and the cathode of the diode D(2k-1,2) is connected to the node connecting the resistors Rds(2k,1) and Rds(2k,2). Thus, the diode D(2k-1,2) is connected between the body of the transistor M(2k-1) and the second end of the transistor M(2k).

[0034] The anode of the diode D(2k,2) is connected to the body of the transistor M(2k), and the cathode of the diode D(2k,2) is connected to the node connecting the resistors Rds(2k-1,1) and Rds(2k-1,2). Thus, the diode D(2k,2) is connected between the body of the transistor M(2k) and the first end of the transistor M(2k-1).

[0035] In this manner, in the switch circuit 1, for example, diodes D(2k-1,2) and D(2k,2) are connected as components of the feedback circuit in units of a pair of transistors M(2k-1) and M(2k). For example, only diode D(2k-1,2) is connected to the body of transistor M(2k-1) as a component of the feedback circuit, and only diode D(2k,2) is connected to the body of transistor M(2k) as a component of the feedback circuit. When integer k is 2 or more, for example, no diode is provided between the body of transistor M(2k-1) and the first end of transistor M(2k-2). When integer k is n-1 or less, for example, no diode is provided between the body of transistor M(2k) and the second end of transistor M(2k+1).

[0036] While the signal GB is at H level, the transistors M1, M2, M3, M4, M5, M6, . . . , M(2n-1), and M(2n) are each in an ON state, that is, the switch circuit 1 is in an ON state.

[0037] While the signal GB is at the L level, the transistors M1, M2, M3, M4, M5, M6, . . . , M(2n-1), and M(2n) are each in an OFF state, i.e., the switch circuit 1 is in an OFF state. While the switch circuit 1 is in an OFF state, due to the connection relationship of the resistor Rds described above, a voltage obtained by dividing the voltage applied between the terminal IN and the terminal OUT is applied to each of the transistors M1, M2, M3, M4, M5, M6, . . . , M(2n-1), and M(2n). The voltages applied to the transistors M1, M2, M3, M4, M5, M6, . . . , M(2n-1), and M(2n) are substantially the same.

[0038] If the potential (hereinafter also referred to as voltage) of the body of transistor M1 is higher than the voltage of the gate of transistor M1, current can flow from the body via diode D(1,1).

[0039] The above description is given in relation to the diode D(1,1) connected between the body and gate of the transistor M1. The same description is also true for each of the other transistors M in relation to the diode D connected between the body and gate of the transistor M.

[0040] If the voltage of the body of transistor M1 is higher than the voltage of the node connecting resistors Rds(2,1) and Rds(2,2), current may flow from the body through diode D(1,2).

[0041] If the voltage of the body of transistor M2 is higher than the voltage of the node connecting resistors Rds(1,1) and Rds(1,2), current may flow from the body through diode D(2,2).

[0042] The above description relates to the diodes D(1,2) and D(2,2) connected to the bodies of the transistors M1 and M2, respectively. The same description applies to each of the other transistors M, in terms of the diode D connected to the body of the transistor M as a component of the feedback circuit.

[0043] In the above description, for example, the cathode of the diode D(2,2) has been described as being connected to the node connecting the resistors Rds(1,1) and Rds(1,2). In this connection relationship, for example, if the resistance value of the resistor Rds(1,1) is extremely small, it can also be interpreted that the cathode of the diode D(2,2) is connected to the first end of the transistor M1 without passing through a resistive element. If the resistance value of the resistor Rds(1,1) is extremely small, for example, the resistance value of the resistor Rds(1,2) differs from the resistance value of the resistor Rds(1,1). The same applies to the other diodes D described as being connected in a similar manner.

[0044] Fig. 3 is a diagram for explaining the structure of the transistor M2 of the switch circuit 1 according to the first embodiment. Fig. 3 shows a part of the cross-sectional structure of the switch circuit 1. The structure of the transistor M2 will be described below as an example, but the other transistors M may have a similar structure to that described below. As an example, a case will be described in which the switch circuit 1 is provided on an SOI (Silicon On Insulator) substrate.

[0045] An oxide film BOX is provided on the upper surface of the semiconductor substrate SB. A semiconductor layer is provided as a body layer BD on the upper surface of the oxide film BOX. The body layer BD is doped with, for example, boron (B) to form a p + The body layer BD is used as an impurity diffusion layer. A source region SR and a drain region DR are provided on the surface of the body layer BD with a space therebetween. The source region SR and the drain region DR are each doped with, for example, phosphorus (P) to form an n +The gate electrode G is provided on the upper surface of the body layer BD between the source region SR and the drain region DR via a gate insulator GI. The transistor M2 includes the source region SR, the drain region DR, and the gate electrode G.

[0046] The gate of the transistor M2 is connected to other components via a contact plug (not shown) or the like provided on the upper surface of the gate electrode G. Similarly, a first end of the transistor M2 is connected to other components, and a second end of the transistor M2 is connected to other components via contact plugs (not shown) or the like provided on the upper surfaces of the drain region DR and the source region SR, respectively.

[0047] For example, when the voltage of the drain region DR is higher than the voltage of the body layer BD, a leakage current Ib may flow from the drain region DR to the body layer BD. Similarly, when the voltage of the source region SR is higher than the voltage of the body layer BD, a leakage current Ib may flow from the source region SR to the body layer BD.

[0048] When such a leakage current Ib occurs, the voltage of the body of the transistor M2 may rise. The rise in the voltage is suppressed by the current flowing through the diode D connected to the body of the transistor M2 as described above.

[0049] [Example] An operation example of the switch circuit 1 according to the first embodiment will be described below with reference to Fig. 4 and Fig. 5. For the sake of simplicity, Fig. 4 and Fig. 5 show the circuit configuration of the switch circuit 1 when n is 1. The following description will be given for the case where n is 1. The same description as below also applies when n is another integer.

[0050] 4 is a diagram for explaining various bias voltages used in the switch circuit 1 according to the first embodiment. The voltage values ​​mentioned in the following description are merely examples for the sake of simplicity.

[0051] FIG. 4(a) shows an example of various bias voltages used when the switch circuit 1 is in the on state.

[0052] A voltage of 0 volts (V) is applied to the terminal IN and the terminal OUT as a bias voltage.

[0053] The voltage of the signal GB is at the H level of 3V, that is, the bias potentials (hereinafter also referred to as bias voltages) of the gates of the transistors M1 and M2 are each 3V.

[0054] The bodies of the transistors M1 and M2 are in a floating state, and the bias voltage of the bodies of the transistors M1 and M2 is, for example, 0 V. This is based on, for example, parasitic capacitances occurring between the body and the first terminal of the transistor M1, between the body and the second terminal of the transistor M1, between the body and the first terminal of the transistor M2, and between the body and the second terminal of the transistor M2, respectively.

[0055] Due to this bias voltage relationship, the voltage of the body of transistor M1 is lower than the voltage of the gate of transistor M1. Therefore, no current flows through diode D(1,1). Therefore, the body bias voltage of transistor M1 is maintained at 0V. Similarly, the body bias voltage of transistor M2 is also maintained at 0V.

[0056] FIG. 4(b) shows an example of various bias voltages used when the switch circuit 1 is in the off state.

[0057] A voltage of 0 V is applied to the terminals IN and OUT as a bias voltage.

[0058] The voltage of the signal GB is at the L level of −3 V, that is, the bias voltages of the gates of the transistors M1 and M2 are each −3 V.

[0059] As mentioned above, when the body bias voltage of transistor M1 is 0V, if the body voltage of transistor M1 is higher than the gate voltage of transistor M1, current flows from the body via diode D(1,1). This causes the body bias voltage to drop and stabilize at -2.4V, which is higher than the gate bias voltage of -3V by the threshold voltage of diode D(1,1). Similarly, the body bias voltage of transistor M2 also stabilizes at -2.4V.

[0060] FIG. 5 is a diagram for explaining various currents that flow through the switch circuit 1 according to the first embodiment while the switch circuit 1 is in an off state.

[0061] When a certain high-frequency signal is input to the terminal IN, the leakage current Ib described with reference to Fig. 3 may occur in each of the transistors M1 and M2. In the switch circuit 1, a current described below may flow through the feedback circuit.

[0062] The bias voltage of the body of the transistor M1 may increase based on the leakage current Ib generated in the transistor M1. If the voltage of the body is higher than the voltage of the node connecting the resistors Rds(2,1) and Rds(2,2), a current may flow from the body to the node connecting the resistor Rds(2,2) and the second end of the transistor M2 through the diode D(1,2) and the resistor Rds(2,2). This may suppress an increase in the bias voltage of the body.

[0063] The bias voltage of the body of the transistor M2 may increase based on the leakage current Ib generated in the transistor M2. If the voltage of the body is higher than the voltage of the node connecting the resistors Rds(1,1) and Rds(1,2), a current may flow from the body through the diode D(2,2) and the resistor Rds(1,1) to the node connecting the resistor Rds(1,1) and the first end of the transistor M1. This may suppress an increase in the bias voltage of the body.

[0064] [effect] FIG. 6 shows an example of a circuit configuration of a switch circuit 1x according to a comparative example of the first embodiment. The circuit configuration of the switch circuit 1x shown in Fig. 6 corresponds to the circuit configuration of the switch circuit 1 when n is 1, except that no diode is provided as a component of the feedback circuit, and the body of the transistor M1 is connected to a node to which the signal BB is input via a resistor Rb1, and the body of the transistor M2 is connected to a node to which the signal BB is input via a resistor Rb2. The voltage of the signal BB is set, for example, according to the voltage of the signal GB. In Fig. 6, the resistor connected between the first and second terminals of the transistor M1 is indicated as resistor Rds1x, and the resistor connected between the first and second terminals of the transistor M2 is indicated as resistor Rds2x.

[0065] The operation of the switch circuit 1x while the switch circuit 1x is in the off state will be described. When a certain high-frequency signal is input to the terminal IN, the leakage current Ib described with reference to FIG. 3 may occur in each of the transistors M1 and M2 in the switch circuit 1x as well.

[0066] Such leakage current Ib may increase the bias voltage of the bodies of the transistors M1 and M2. More specifically, the following occurs.

[0067] Such leakage current Ib may contribute to a current flow from the body of transistor M1 through resistor Rb1, and from the body of transistor M2 through resistor Rb2. This causes the voltage drops across the various resistors Rb to change. The amount of increase in the body bias voltage of each of transistors M1 and M2 described above corresponds to the amount of this change.

[0068] Furthermore, due to such leakage current Ib, the bias voltages of the second terminal of the transistor M1 and the first terminal of the transistor M2 may drop.

[0069] Such a leakage current Ib may contribute to a current flowing from the terminal IN through the resistor Rds1x to a node connecting the second terminal of the transistor M1 and the first terminal of the transistor M2, and a current flowing from the terminal OUT to the node through the resistor Rds2x. This causes the voltage drop amount in each resistor Rds to change. The amount of drop in the bias voltage at the second terminal of the transistor M1 and the first terminal of the transistor M2 described above corresponds to the amount of this change.

[0070] In the above, the case where two transistors M are connected in series between the terminal IN and the terminal OUT has been described. A similar description is also valid when the number of transistors M connected in series between the terminal IN and the terminal OUT is other than the above. That is, due to the leakage current Ib generated in each transistor M, the bias voltage of the body of each transistor M may increase, and the bias voltage of the first terminal and / or the second terminal of each transistor M may decrease.

[0071] As a result, when the potential difference between the body and drain of a certain transistor M becomes small, the parasitic bipolar transistor between the drain and source of the transistor M becomes more likely to be turned on. When the parasitic bipolar transistor of a certain transistor M is turned on, the voltage applied to each of the other transistors M increases, that is, the withstand voltage of the switch circuit 1x decreases.

[0072] In the switch circuit 1 according to the first embodiment, as described with reference to FIG. 5, a current flows through the feedback circuit, thereby suppressing, for example, an increase in the bias voltage of the body of each transistor M and also suppressing a decrease in the bias voltage of the first terminal and / or the second terminal of each transistor M.

[0073] 7 shows an example of a graph showing the relationship between a high-frequency power Pin associated with a high-frequency signal and the bias voltages of the first terminal, the gate, and the body of the transistor M2 when the high-frequency signal is input to the switch circuit 1 according to the first embodiment while the switch circuit 1 is in an off state. A similar graph for a switch circuit 1x according to a comparative example of the first embodiment is also shown in FIG.

[0074] 7A shows the relationship between the high frequency power Pin and the bias voltage VDbias at the first terminal of the transistor M2. The horizontal axis shows the value of the high frequency power Pin. The vertical axis shows the value of the bias voltage VDbias.

[0075] In the switch circuit 1x according to the comparative example, as the radio frequency power Pin increases, the leakage current Ib occurs in the transistor M2, and the bias voltage VDbias decreases, as described above. On the other hand, in the switch circuit 1 according to the first embodiment, the bias voltage VDbias does not decrease even when the radio frequency power Pin increases, as described above.

[0076] 7B shows the relationship between the high frequency power Pin and the bias voltage VGbias of the gate of the transistor M2. The horizontal axis shows the value of the high frequency power Pin. The vertical axis shows the value of the bias voltage VGbias.

[0077] In the switch circuit 1x according to the comparative example, the bias voltage VGbias is substantially constant regardless of the radio frequency power Pin. In the switch circuit 1 according to the first embodiment, the bias voltage VGbias is also substantially constant regardless of the radio frequency power Pin, but FIG. 7B shows, as an example, how the bias voltage VGbias decreases in a region where the radio frequency power Pin becomes even larger.

[0078] The graph shown in Fig. 7(c) shows the relationship between the high frequency power Pin and the bias voltage VBbias of the body of the transistor M2. The horizontal axis shows the value of the high frequency power Pin. The vertical axis shows the value of the bias voltage VBbias. Note that the comparative example shows a case where the voltage of the signal BB is substantially the same as the L level voltage of the signal GB.

[0079] In the switch circuit 1x according to the comparative example, as the high frequency power Pin increases, as described above, the leak current Ib occurs in the transistor M2, and the bias voltage VBbias increases. On the other hand, in the switch circuit 1 according to the first embodiment, the bias voltage VBbias does not increase as described above, even if the high frequency power Pin increases and the leak current Ib occurs in the transistor M2 from a voltage higher than the L level voltage of the signal GB by the threshold voltage of the diode D(2,1). FIG. 7(c) shows, as an example, a state in which the bias voltage VBbias decreases as the high frequency power Pin increases. As described above, the decrease is also based on the fact that the diode D(2,2) rectifies the voltage based on the AC voltage applied to both ends of the diode D(2,2) and a current flows through the diode D(2,2). The decrease of the bias voltage VGbias shown in FIG. 7(b) is based on the fact that, for example, the AC signal generated in the body of the transistor M2 also affects the voltage applied to the diode D(2,1) between the gate and body of the transistor M2.

[0080] 5, even if a leakage current Ib occurs in a transistor M, the switch circuit 1 according to the first embodiment suppresses an increase in the bias voltage of the body of the transistor M and suppresses a decrease in the bias voltage of the first terminal and / or the second terminal of the transistor M. Therefore, the switch circuit 1 according to the first embodiment prevents a decrease in the withstand voltage of the switch circuit 1 caused by the leakage current Ib occurring in the transistor M.

[0081] 4, while the switch circuit 1 according to the first embodiment is in an off state, the diode D between the body and gate of each transistor M is forward biased and the impedance of the diode D is low, whereas while the switch circuit 1 is in an on state, the diode D is reverse biased and the impedance of the diode D is high. Therefore, according to the switch circuit 1 according to the first embodiment, while the switch circuit 1 is in an on state, the gate impedance for the channel of each transistor M is high and the loss of the high frequency signal transmitted by the switch circuit 1 via the transistor M is small.

[0082] Furthermore, in the switch circuit 1 according to the first embodiment, the following explanation holds true for each case in which the integer k is from 1 to n. The anode of the diode D(2k-1,2) is connected to the body of the transistor M(2k-1), and the cathode of the diode D(2k-1,2) is connected to the node connecting the resistors Rds(2k,1) and Rds(2k,2). The resistors Rds(2k,1) and Rds(2k,2) are connected in series between the first terminal and the second terminal of the transistor M(2k).

[0083] The anode of the diode D(2k,2) is connected to the body of the transistor M(2k), and the cathode of the diode D(2k,2) is connected to the node connecting the resistors Rds(2k-1,1) and Rds(2k-1,2). The resistors Rds(2k-1,1) and Rds(2k-1,2) are connected in series between the first terminal and the second terminal of the transistor M(2k-1).

[0084] In this manner, the diodes D(2k-1,2) and D(2k,2) as components of the feedback circuit are uniformly connected in units of a pair of transistors M(2k-1) and M(2k).

[0085] Furthermore, in the switch circuit 1 according to the first embodiment, the number of diodes D provided for each transistor M as a component of the feedback circuit can be reduced, for example, compared to the case where the cathode of the diode D(2k-1,2) is connected to the second end of the transistor M(2k) without a resistor and the cathode of the diode D(2k,2) is connected to the first end of the transistor M(2k-1) without a resistor. In the example of FIG. 2, the number is 1. This is due to the voltage relationship described below. When a certain high-frequency signal is input to the terminal IN, the maximum voltage that can be applied between the body of the transistor M(2k-1) and the node connecting the resistors Rds(2k,1) and Rds(2k,2) is smaller than the maximum voltage that can be applied between the body and the second end of the transistor M(2k). In addition, the maximum voltage that can be applied between the body of transistor M(2k) and the node connecting resistors Rds(2k-1,1) and Rds(2k-1,2) is smaller than the maximum voltage that can be applied between the body and the first terminal of transistor M(2k-1).

[0086] Therefore, in the switch circuit 1 according to the first embodiment, for example, the connection of the diode D used as a feedback circuit does not become uneven, so that the withstand voltage is improved and the circuit configuration is simplified and reduced in size.

[0087] <Second embodiment> The switch circuit 1a according to the second embodiment will be described below. The configuration, operation, and effects of the switch circuit 1a according to the second embodiment will be described, focusing on the differences from the switch circuit 1 according to the first embodiment.

[0088] The explanation given with reference to Fig. 1 in relation to switch circuit 1 also applies to switch circuit 1a. More specifically, the explanation given in relation to Fig. 1 applies if switch circuit 1 is replaced with switch circuit 1a. The following explanation focuses on switch circuit 1a, but the same explanation as for switch circuit 1a can also apply to each of switch circuits 2, 3, and 4.

[0089] FIG. 8 shows an example of a circuit configuration of a switch circuit 1a according to the second embodiment. The switch circuit 1a includes 2n diodes D(1,3), D(2,3), D(3,3), D(4,3), D(5,3), D(6,3), . . . , D(2n-1,3), and D(2n,3) in addition to the components included in the switch circuit 1. The switch circuit 1a has a circuit configuration in which the number of diodes D provided for each transistor M as components of the feedback circuit is changed from 1 to 2 in the circuit configuration of the switch circuit 1 described with reference to FIG. 2. More specifically, it is as follows.

[0090] The anode of diode D(1,3) is connected to the cathode of diode D(1,2), and the cathode of diode D(1,3) is connected to the node connecting resistors Rds(2,1) and Rds(2,2). The anode of diode D(2,3) is connected to the cathode of diode D(2,2), and the cathode of diode D(2,3) is connected to the node connecting resistors Rds(1,1) and Rds(1,2). The same is true for diodes D(3,3), D(4,3), D(5,3), D(6,3), ..., D(2n-1,3), and D(2n,3).

[0091] In the above, an example is shown in which the number of diodes D provided for each transistor M as components of the feedback circuit is two. This embodiment is not limited to this. As described above, the number of diodes D provided for each transistor M as components of the feedback circuit may be three or more.

[0092] In this way, according to the switch circuit 1a according to the second embodiment, the number of diodes D provided for each transistor M as components of the feedback circuit can be appropriately changed in consideration of, for example, the withstand voltage of the diodes D. The number may be based on, for example, the amplitude of a high-frequency signal that can be input to the terminal IN.

[0093] <Third embodiment> The switch circuit 1b according to the third embodiment will be described below. The configuration, operation, and effects of a switch circuit 1b according to the third embodiment will be described, focusing on the differences from the switch circuit 1 according to the first embodiment.

[0094] The explanation given with reference to Fig. 1 in relation to switch circuit 1 also applies to switch circuit 1b. More specifically, the explanation given in Fig. 1 applies if switch circuit 1 is replaced with switch circuit 1b. The following explanation focuses on switch circuit 1b, but the same explanation as for switch circuit 1b can also be applied to each of switch circuits 2, 3, and 4.

[0095] FIG. 9 shows an example of a circuit configuration of a switch circuit 1b according to the third embodiment. The circuit configuration of the switch circuit 1b is obtained by replacing the resistors connected between the first terminal and the second terminal of each of the transistors M1, M2, M3, ..., and M(2n) in the circuit configuration of the switch circuit 1 described with reference to Fig. 2 with those resistors as follows: The following explanation applies to each case where the integer i is 1 to n.

[0096] The resistors connected between the first and second terminals of the transistor M(2i-1) are replaced from the resistors Rds(2i-1,1) and Rds(2i-1,2) to resistors Rds(2i-1,1)b and Rds(2i-1,2)b. More specifically, one terminal of the resistor Rds(2i-1,1)b is connected to the first terminal of the transistor M(2i-1), one terminal of the resistor Rds(2i-1,1)b is connected to the other terminal of the resistor Rds(2i-1,2)b, and the second terminal of the transistor M(2i-1) is connected to the other terminal of the resistor Rds(2i-1,2)b.

[0097] The resistors connected between the first and second terminals of the transistor M(2i) are replaced from the resistors Rds(2i,1) and Rds(2i,2) to resistors Rds(2i,1)b and Rds(2i,2)b. More specifically, one terminal of the resistor Rds(2i,1)b is connected to the first terminal of the transistor M(2i), one terminal of the resistor Rds(2i,1)b is connected to the other terminal of the resistor Rds(2i,2)b, and the second terminal of the transistor M(2i) is connected to the other terminal of the resistor Rds(2i,2)b.

[0098] The cathode of the diode D(2i-1,2) is connected to the node connecting the resistors Rds(2i,1)b and Rds(2i,2)b. The cathode of the diode D(2i,2) is connected to the node connecting the resistors Rds(2i-1,1)b and Rds(2i-1,2)b.

[0099] In any case where the integer i is from 1 to n, the resistance values ​​of resistors Rds(2i-1,1)b and Rds(2i,2)b are, for example, substantially the same as R2, and the resistance values ​​of resistors Rds(2i-1,2)b and Rds(2i,1)b are, for example, substantially the same as three times R2.

[0100] In the above, for example, an example in which the resistance value of the resistor Rds(1,1)b is R2 and the resistance value of the resistor Rds(1,2)b is three times R2 has been described. However, this embodiment is not limited to this. The ratio between the resistance value of the resistor Rds(1,1)b and the resistance value of the resistor Rds(1,2)b may be another value. For example, the resistance value of the resistor Rds(1,1)b is between 1 / 3 and 3 times the resistance value of the resistor Rds(1,2)b. The same is true for the other resistors Rds(2,1)b, Rds(2,2)b, Rds(3,1)b, Rds(3,2)b, . . ., Rds(2n,1)b, and Rds(2n,2)b.

[0101] The switch circuit 1b according to the third embodiment makes it possible to adjust the maximum voltage that can be applied to each diode D as a component of the feedback circuit when a high-frequency signal is input to the terminal IN. By this adjustment, it is possible to adjust the effect of the feedback circuit in drawing current from the body of each transistor M while taking into account, for example, the withstand voltage of each diode D as a component of the feedback circuit.

[0102] <Fourth embodiment> The switch circuit 1c according to the fourth embodiment will be described below. The configuration, operation, and effects of the switch circuit 1c according to the fourth embodiment will be described, focusing on the differences from the switch circuit 1 according to the first embodiment.

[0103] The explanation given with reference to Fig. 1 in relation to switch circuit 1 also applies to switch circuit 1c. More specifically, the explanation given in relation to Fig. 1 applies if switch circuit 1 is replaced with switch circuit 1c. The following explanation focuses on switch circuit 1c, but the same explanation as for switch circuit 1c can also be applied to each of switch circuits 2, 3, and 4.

[0104] FIG. 10 shows an example of a circuit configuration of a switch circuit 1c according to the fourth embodiment. The circuit configuration of the switch circuit 1c corresponds to the circuit configuration of the switch circuit 1, in which the body of each of the transistors M1, M2, M3, ..., and M(2n) is connected via a certain resistor to a node to which a signal BB is input. The switch circuit 1c includes resistors Rb1, Rb2, Rb3, Rb4, Rb5, Rb6, ..., Rb(2n-1), and Rb(2n) as such resistors.

[0105] One end of resistor Rb1 is connected to the body of transistor M1. One end of resistor Rb2 is connected to the body of transistor M2. One end of resistor Rb3 is connected to the body of transistor M3. The same applies to resistors Rb4, Rb5, Rb6, . . . , Rb(2n-1), and Rb(2n). The other end of resistor Rb1, the other end of resistor Rb2, the other end of resistor Rb3, . . . , the other end of resistor Rb(2n-1), and the other end of resistor Rb(2n) are connected to a node to which a signal BB is input. FIG. 10 also shows a control end to which a signal BB is input to switch circuit 1c. The signal BB is supplied by, for example, a control circuit 7. The voltage of signal BB is set according to the voltage of signal GB, for example.

[0106] The bias voltage of the bodies of transistors M1, M2, M3, . . . , and M(2n) is, for example, the voltage of signal BB.

[0107] According to the switch circuit 1c of the fourth embodiment, the body bias voltage of each transistor M when the switch circuit 1c is in an on state and an off state can be easily adjusted based on the voltage of the signal BB so as to improve, for example, the withstand voltage of the switch circuit 1c.

[0108] <Fifth embodiment> A switch circuit 1d according to the fifth embodiment will be described below. The configuration, operation, and effects of a switch circuit 1d according to the fifth embodiment will be described, focusing on the differences from the switch circuit 1 according to the first embodiment.

[0109] The explanation given with reference to Fig. 1 in relation to switch circuit 1 also applies to switch circuit 1d. More specifically, the explanation given in Fig. 1 applies if switch circuit 1 is replaced with switch circuit 1d. The following explanation focuses on switch circuit 1d, but the same explanation as for switch circuit 1d can also be applied to each of switch circuits 2, 3, and 4.

[0110] FIG. 11 shows an example of a circuit configuration of a switch circuit 1d according to the fifth embodiment. In addition to the components included in the switch circuit 1, the switch circuit 1d includes a transistor M(2n+1), a resistor Rg(2n+1), a resistor Rds(2n+1,1), a resistor Rds(2n+1,2), a diode D(2n+1,1), and a diode D(2n+1,2) as a component of the feedback circuit.

[0111] Between the terminal IN and the terminal OUT, the transistors M1, M2, M3, M4, M5, M6, . . . , M(2n-1), M(2n), and M(2n+1) are connected in series. The first terminal of the transistor M(2n+1) is connected to the second terminal of the transistor M(2n), and the terminal OUT is connected to the second terminal of the transistor M(2n+1).

[0112] One end of a resistor Rg(2n+1) is connected to the gate of the transistor (2n+1), and the other end of the resistor Rg(2n+1) is connected to a node to which a signal GB is input.

[0113] One end of resistor Rds(2n+1,1) is connected to a first end of transistor M(2n+1), one end of resistor Rds(2n+1,2) is connected to the other end of resistor Rds(2n+1,1), and a second end of transistor M(2n+1) is connected to the other end of resistor Rds(2n+1,2). The resistance values ​​of resistors Rds(1,1), Rds(1,2), Rds(2,1), Rds(2,2), ..., Rds(2n+1,1), and Rds(2n+1,2) are, for example, substantially the same.

[0114] The anode of diode D(2n+1,1) is connected to the body of transistor M(2n+1), and the cathode of diode D(2n+1,1) is connected to the gate of transistor M(2n+1).

[0115] The anode of the diode D(2n+1,2) is connected to the body of the transistor M(2n+1), and the cathode of the diode D(2n+1,2) is connected to the node connecting the resistors Rds(2n,1) and Rds(2n,2). Thus, the diode D(2n+1,2) is connected between the body of the transistor M(2n+1) and the first end of the transistor M(2n). For example, only the diode D(2n+1,2) is connected to the body of the transistor M(2n+1) as a component of the feedback circuit.

[0116] In this way, also in the switch circuit 1d according to the fifth embodiment, for example, the connection of the diode D used as a feedback circuit is not uneven. More specifically, for each transistor M, for example, one diode D is provided as a component of the feedback circuit, which is provided between the body of the transistor M and the first end or the second end of the transistor M adjacent to the transistor M. That is, in the switch circuit 1d, even though the switch circuit 1d includes an odd number of transistors M, the circuit configuration is simplified and reduced in size in the same manner as described in the first embodiment.

[0117] 2, a current can flow from the body of transistor M(2n+1) via diode D(2n+1,2). This current can contribute to suppressing an increase in the bias voltage of the body of transistor M(2n+1) caused by leakage current Ib generated in transistor (2n+1).

[0118] In the above, a case where a transistor M(2n+1) is further provided between the transistor M(2n) and the terminal OUT in addition to the configuration of the switch circuit 1 according to the first embodiment has been described. This embodiment is not limited to this. The same description as above also applies to a case where another transistor M is further provided between the terminal IN and the transistor M1 in addition to the configuration of the switch circuit 1 according to the first embodiment.

[0119] <Other embodiments> In this specification, the term "connection" refers to an electrical connection, and does not exclude, for example, the interposition of another element therebetween. Furthermore, in this specification, the term "resistance" may be a resistive element or a parasitic resistance.

[0120] Instead of the diode consisting of a PN junction described above as being used in the switch circuit, a diode-connected transistor may be used. When simply referring to a "diode" in this specification, it is intended that either a diode-connected transistor or a diode consisting of a PN junction may be used as the diode.

[0121] In this specification, expressions such as "identical," "matched," "constant," and "maintained" are intended to include cases where there is an error within the design range when implementing the technology described in the embodiment. The same applies to cases where the term "substantially" is used in combination with these expressions, such as "substantially identical." Furthermore, expressions such as "applying or supplying a certain voltage" are intended to include both controlling the application or supply of the voltage and actually applying or supplying the voltage. Furthermore, applying or supplying a certain voltage may include, for example, applying or supplying a voltage of 0V.

[0122] Although some embodiments have been described above, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included in the scope and spirit of the invention, and are included in the scope of the invention and its equivalents described in the claims. [Explanation of symbols]

[0123] 1, 1a, 1b, 1c, 1d, 1x, 2, 3, 4...switch circuit, 5, 6...signal processing circuit, 7...control circuit, WD...wireless device, ANT...antenna, M...transistor, Rg, Rds, Rb...resistor, D...diode, SB...semiconductor substrate, BOX...oxide film, BD...body layer, DR...drain region, SR...source region, G...gate electrode, GI...gate insulator.

Claims

1. an input end, an output end, and a first control end; a first transistor and a second transistor connected in series between the input terminal and the output terminal, the first transistor having a first terminal and a second terminal used in the series connection, a first gate connected to the first control terminal, and a first body, the second transistor having a third terminal and a fourth terminal used in the series connection, a second gate connected to the first control terminal, and a second body, the third terminal being connected to the second terminal; A first resistor connected to the first end; a second resistor connected between the first resistor and the second end; a third resistor connected to the third end; a fourth resistor connected between the third resistor and the fourth terminal; a first diode having an anode connected to the first body and a cathode connected to a node connecting the third resistor and the fourth resistor; a second diode having an anode connected to the second body and a cathode connected to a node connecting the first resistor and the second resistor; A semiconductor device comprising:

2. 2 . The semiconductor device according to claim 1 , wherein said first resistor and said fourth resistor have the same resistance value, and said second resistor and said third resistor have the same resistance value.

3. 3. The semiconductor device according to claim 1, wherein a resistance value of the first resistor is between 1 / 3 and 3 times a resistance value of the second resistor, and a resistance value of the fourth resistor is between 1 / 3 and 3 times a resistance value of the third resistor.

4. a third transistor and a fourth transistor connected in series with the first transistor and the second transistor between the input terminal and the output terminal, the third transistor having a fifth terminal and a sixth terminal used in the series connection, a third gate connected to the first control terminal, and a third body, the fourth transistor having a seventh terminal and an eighth terminal used in the series connection, a fourth gate connected to the first control terminal, and a fourth body, the seventh terminal being connected to the sixth terminal, and the eighth terminal being connected to the first terminal; A fifth resistor connected to the fifth end; a sixth resistor connected between the fifth resistor and the sixth terminal; A seventh resistor connected to the seventh end; an eighth resistor connected between the seventh resistor and the eighth terminal; a third diode having an anode connected to the third body and a cathode connected to a node connecting the seventh resistor and the eighth resistor; a fourth diode having an anode connected to the fourth body and a cathode connected to a node connecting the fifth resistor and the sixth resistor; The semiconductor device according to claim 1 , further comprising:

5. no diode is provided between the first body and a node connecting the seventh resistor and the eighth resistor; no diode is provided between the fourth body and a node connecting the first resistor and the second resistor; The semiconductor device according to claim 4.

6. one or more diodes connected between a cathode of the first diode and a node connecting the third resistor and the fourth resistor; one or more diodes connected between the cathode of the second diode and a node connecting the first resistor and the second resistor; The semiconductor device according to claim 1 , further comprising:

7. a fifth transistor connected in series with the first transistor and the second transistor between the input terminal and the output terminal, the fifth transistor having a ninth terminal and a tenth terminal used in the series connection, a fifth gate connected to the first control terminal, and a fifth body, the ninth terminal being connected to the fourth terminal; a ninth resistor connected to the ninth end; a sixth resistor connected between the ninth resistor and the tenth terminal; a fifth diode having an anode connected to the fifth body and a cathode connected to a node connecting the third resistor and the fourth resistor; The semiconductor device according to claim 1 , further comprising:

8. a sixth diode having an anode connected to the first body and a cathode connected to the first gate; a seventh diode having an anode connected to the second body and a cathode connected to the second gate; The semiconductor device according to claim 1 , further comprising:

9. The semiconductor device according to claim 1 , further comprising a second control terminal connected to said first body and said second body.

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