3D memory device with deep isolation structure

Abstract

A method for forming a three-dimensional memory device includes forming a peripheral circuit on a first side of a first substrate, the peripheral circuit including first and second peripheral devices, a first interconnect layer, and a shallow trench isolation (STI) structure between the first and second peripheral devices, and forming a memory array on a second substrate, the memory array including a plurality of memory cells and a second interconnect layer. The method includes bonding the first and second interconnect layers, forming an isolation trench through the first substrate, and exposing a portion of the STI structure. The isolation trench is formed through a second side of the first substrate opposite the first side. The method includes disposing an isolation material to form an isolation structure in the isolation trench, and performing a planarization process to remove the portion of the isolation material disposed on the second side of the first substrate.

Description

[Technical field]

[0001] The present disclosure relates generally to the field of semiconductor technology, and more particularly to methods for reducing stress in semiconductor wafers used to form three-dimensional (3D) memory devices. [Background technology]

[0002] Planar memory cells are being scaled to smaller sizes by improving process technology, circuit design, programming algorithms, and fabrication processes. However, as memory cell feature sizes approach lower limits, planar processes and fabrication techniques become difficult and costly. As such, memory density for planar memory cells is approaching an upper limit. Three-dimensional (3D) memory architectures can address the density limitations of planar memory cells. Summary of the Invention [Means for solving the problem]

[0003] DETAILED DESCRIPTION OF THE DRAWINGS Embodiments of a three-dimensional (3D) capacitor structure for a memory device and a method for forming the same are described in the present disclosure.

[0004] In some embodiments, a method for forming a three-dimensional memory device includes forming a peripheral circuit on a first side of a first substrate, the peripheral circuit including a first and a second peripheral device, a first interconnect layer, and a shallow trench isolation (STI) structure between the first and second peripheral devices. The method also includes forming a memory array on a second substrate, the memory array including a plurality of memory cells and a second interconnect layer. The method further includes bonding the first and the second interconnect layers and forming an isolation trench through the first substrate to expose a portion of the STI structure. The isolation trench is formed through a second side of the first substrate opposite the first side. The method further includes disposing an isolation material and forming an isolation structure in the isolation trench, and performing a planarization process to remove a portion of the isolation material disposed on the second side of the first substrate.

[0005] In some embodiments, the first substrate is thinned through the second side after the step of bonding the first and second interconnect layers.

[0006] In some embodiments, thinning the first substrate includes exposing a deep well on the second side of the first substrate.

[0007] In some embodiments, a liner layer is disposed in the isolation trench prior to disposing the isolation material.

[0008] In some embodiments, a dielectric layer is disposed on the second side of the first substrate.

[0009] In some embodiments, the bonding step comprises direct bonding.

[0010] In some embodiments, another STI structure is formed adjacent to the first peripheral device, and another deep isolation trench is formed through the first substrate to expose the another STI structure.

[0011] In some embodiments, the isolation material is disposed in a separate deep isolation trench.

[0012] In some embodiments, providing an isolation material includes depositing a silicon oxide material.

[0013] In some embodiments, bonding the first and second interconnect layers includes a dielectric-dielectric bond and a metal-metal bond at the bond interface.

[0014] In some embodiments, a method for forming a three-dimensional memory device includes forming a peripheral circuit having a plurality of peripheral devices and a first interconnect layer on a first side of a first substrate. The method also includes forming a plurality of shallow trench isolation (STI) structures in the first substrate, each STI structure of the plurality of STI structures being formed between adjacent peripheral devices of the plurality of peripheral devices. The method further includes forming a memory array on a second substrate, the memory array including a plurality of memory cells and a second interconnect layer. The method further includes bonding the first and second interconnect layers, such that at least one peripheral device of the plurality of peripheral devices is electrically coupled to at least one memory cell of the plurality of memory cells. The method further includes thinning the first substrate through a second side of the first substrate, the second side being opposite the first side. The method further includes forming a plurality of isolation trenches through the first substrate to expose portions of the STI structures of the plurality of STI structures, the plurality of isolation trenches being formed through a second side of the first substrate. The method further includes disposing an isolation material in the plurality of isolation trenches and performing a planarization process to remove portions of the isolation material disposed on the second side of the first substrate.

[0015] In some embodiments, the bonding step comprises direct bonding.

[0016] In some embodiments, a dielectric layer is disposed on the second side of the first substrate, and a plurality of isolation trenches extend through the dielectric layer.

[0017] In some embodiments, a liner layer is disposed in the isolation trench prior to disposing the isolation material.

[0018] In some embodiments, disposing an isolation material includes disposing a silicon oxide material.

[0019] In some embodiments, the three-dimensional memory device includes a peripheral circuit wafer, the peripheral circuit wafer including a first substrate, a plurality of peripheral devices formed on a first side of the first substrate, and a first interconnect layer. The peripheral circuit wafer also includes a plurality of shallow trench isolation (STI) structures in the first substrate, at least one STI structure formed between adjacent peripheral devices of the plurality of peripheral devices. The peripheral circuit wafer also includes a plurality of deep isolation structures formed on a second side of the first substrate opposite the first side, at least one deep isolation structure of the plurality of deep isolation structures being in physical contact with the at least one STI structure. The three-dimensional memory device also includes a memory array wafer, the memory array wafer including a plurality of memory cells, at least one peripheral device of the plurality of peripheral devices being electrically coupled to at least one memory cell of the plurality of memory cells. The memory array wafer also includes a second interconnect layer in physical contact with the first interconnect layer.

[0020] In some embodiments, the at least one deep isolation structure includes a liner layer and an isolation material, the liner layer being between the isolation material and the first substrate.

[0021] In some embodiments, the physical contact comprises a chemical bond formed between the first interconnect layer and the second interconnect layer.

[0022] In some embodiments, at least one deep isolation structure comprises silicon oxide.

[0023] In some embodiments, the width of the at least one deep isolation structure is about 0.2 μm.

[0024] The accompanying drawings, which are incorporated in and form a part of the specification, illustrate embodiments of the present disclosure and, together with the description, serve to explain the principles of the disclosure and to enable those skilled in the art to make and use the disclosure. [Brief description of the drawings]

[0025] [Figure 1A] 1 is a schematic top view of an exemplary three-dimensional (3D) memory die, in accordance with some embodiments of the present disclosure. [Figure 1B] 1 is a schematic top view of an area of ​​a 3D memory die, according to some embodiments of the present disclosure. [Diagram 2] 1 is a perspective view of a portion of an exemplary 3D memory array structure according to some embodiments of the present disclosure. [Diagram 3] 1 is a flow diagram for forming a 3D memory array with deep isolation structures according to some embodiments of the present disclosure. [Figure 4] 1 is a cross-sectional view of a peripheral circuit according to some embodiments of the present disclosure. [Diagram 5] 1 is a cross-sectional view of a memory array according to some embodiments of the present disclosure. [Figure 6] 1 is a cross-sectional view of a 3D memory device after bonding peripheral circuits and a memory array in accordance with some embodiments of the present disclosure. [Figure 7] 1A-1D are cross-sectional views of a 3D memory device at various process stages according to some embodiments of the present disclosure. [Figure 8] 1A-1D are cross-sectional views of a 3D memory device at various process stages according to some embodiments of the present disclosure. [Figure 9] 1A-1D are cross-sectional views of a 3D memory device at various process stages according to some embodiments of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0026] Features and advantages of the present invention will become more apparent from the detailed description set forth below when taken in conjunction with the drawings, in which like reference numerals identify corresponding elements throughout. In the drawings, like reference numerals generally indicate identical, functionally similar, and / or structurally similar elements. The drawing in which an element first appears is indicated by the left-most digit(s) among the corresponding reference numerals.

[0027] Embodiments of the present disclosure will now be described with reference to the accompanying drawings.

[0028] While specific configurations and arrangements are discussed, it should be understood that this is done for illustrative purposes only. Those skilled in the art will recognize that other configurations and arrangements can be used without departing from the spirit and scope of the present disclosure. It will be apparent to those skilled in the art that the present disclosure can also be used in a variety of other applications.

[0029] It is noted that references herein to "one embodiment," "an embodiment," "an exemplary embodiment," "some embodiments," and the like, indicate that the embodiment being described may include a particular feature, structure, or characteristic, but that all embodiments may not necessarily include that particular feature, structure, or characteristic. Moreover, such phrases do not necessarily refer to the same embodiment. Furthermore, when a particular feature, structure, or characteristic is described in connection with an embodiment, it will be within the knowledge of one of ordinary skill in the art to implement such feature, structure, or characteristic in connection with other embodiments, whether or not explicitly described.

[0030] Generally, terminology may be understood, at least in part, from usage in context. For example, the term "one or more" as used herein may be used in a singular sense to describe any feature, structure, or characteristic, or in a plural sense to describe a combination of features, structures, or characteristics, depending at least in part on the context. Similarly, terms such as "a," "an," or "the," etc., may be understood to convey singular usage or plural usage, again, depending at least in part on the context. In addition, it may be understood that the term "based on" is not necessarily intended to convey an exclusive set of factors, but instead may allow for the existence of additional factors not necessarily explicitly recited, again, depending at least in part on the context.

[0031] It should be readily understood that the meanings of "on," "above," and "over" in this disclosure should be interpreted in the broadest manner, with "on" intended to include not only meaning "directly on" something, but also meaning "on" something with an intermediate feature or layer between them. Moreover, it should be readily understood that "above" or "over" can include not only meaning "above" or "over" something, but also meaning it is "above" or "over" something (i.e., directly on) with no intermediate feature or layer between them.

[0032] Additionally, spatially relative terms such as "below," "below," "lower," "above," and "upper" may be used herein to describe the relationship of one element or feature to another element or feature as illustrated in the figures for ease of description. The spatially relative terms are intended to encompass different orientations of the device during use or process steps in addition to the orientation shown in the figures. The device may be otherwise oriented (rotated 90 degrees or in other orientations) and the spatially relative descriptors used herein may be interpreted accordingly.

[0033] As used herein, the term "substrate" refers to a material on which subsequent layers of material are added. The substrate includes a "top" surface and a "bottom" surface. The top surface of the substrate is typically where the semiconductor devices are formed, and thus the semiconductor devices are formed on the top side of the substrate unless otherwise stated. The bottom surface is opposite to the top surface, and thus the bottom side of the substrate is opposite to the top side of the substrate. The substrate itself may be patterned. Materials added on top of the substrate may be patterned or may remain unpatterned. Moreover, the substrate may include a variety of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, and the like. Alternatively, the substrate may be made of a non-conductive material, such as glass, plastic, or a sapphire wafer.

[0034] As used herein, the term "layer" refers to a portion of material that includes a region having a predetermined thickness. A layer has a top side and a bottom side, where the bottom side of the layer is relatively closer to the substrate and the top side is relatively farther from the substrate. A layer can extend throughout an underlying or overlying structure, or can have an extent that is less than the extent of the underlying or overlying structure. Additionally, a layer can be a region of a homogeneous or heterogeneous continuous structure that has a thickness that is less than the thickness of the continuous structure. For example, a layer can be positioned between any set of horizontal planes between (or at) the top and bottom surfaces of a continuous structure. A layer can extend horizontally, vertically, and / or along a tapered surface. A substrate can be a layer and can include one or more layers therein and / or have one or more layers on, above, and / or below it. A layer can include multiple layers. For example, the interconnect layer may include one or more conductive layers and contact layers (having contacts, interconnect lines, and / or vertical interconnect accesses (VIAs) formed therein) and one or more dielectric layers.

[0035] In this disclosure, for ease of explanation, "tier" is used to refer to elements of substantially the same height along the vertical direction. For example, a wordline and an underlying gate dielectric layer may be referred to as a "tier," a wordline and an underlying insulating layer together may be referred to as a "tier," wordlines of substantially the same height may be referred to as a "tier of wordlines" or the like, and so forth.

[0036] As used herein, the term "nominal / nominal" refers to a desired (or target) value of a characteristic or parameter for a component or process step that is set during the design phase of a product or process, along with a range of values ​​above and / or below the desired value. The range of values ​​may be due to slight variations in the manufacturing process or tolerances. As used herein, the term "about" refers to a value of a given quantity that may vary based on a particular technology node associated with the semiconductor device of interest. Based on a particular technology node, the term "about" can refer to a value of a given quantity that varies, for example, within 10-30% of the value (e.g., ±10%, ±20%, or ±30% of the value).

[0037] In this disclosure, the term "horizontal / horizontally / lateral / laterally" means nominally parallel to a lateral surface of the substrate, and the term "vertical" or "vertically" means nominally perpendicular to a lateral surface of the substrate.

[0038] As used herein, the term "3D memory" refers to a three-dimensional (3D) semiconductor device that comprises vertically oriented strings of memory cell transistors (referred to herein as "memory strings" (e.g., NAND strings)) on a laterally oriented substrate, such that the memory strings extend perpendicular to the substrate.

[0039] High voltage devices, such as high voltage n-type or p-type devices, are implemented in the 3D memory cell to facilitate cell operation. As the development of 3D memory (e.g., 3D NAND flash memory) progresses toward high density and high capacity memory cells, the number of devices and the number of metal wirings are continually increasing. As the isolation between devices continues to shrink, high quality isolation structures become more important to prevent crosstalk between adjacent devices.

[0040] Various embodiments according to the present disclosure provide structures and fabrication methods for isolation structures that improve isolation between structures of a 3D memory structure. A peripheral device wafer containing CMOS devices can be bonded to an array wafer containing a 3D memory array. Isolation structures can be implemented in the bonded peripheral / memory array wafer to prevent crosstalk between adjacent structures (e.g., between wells of different doping types). Isolation structures can be formed by thinning the dielectric layer of the peripheral wafer and by forming through silicon isolation (TSI) structures to effectively isolate different functional regions. By using isolation structures, rather than relying on greater isolation between devices or increasing the dopant levels of those functional regions, the overall memory density and manufacturing cost of 3D NAND flash memory can be improved.

[0041] FIG. 1A illustrates a top view of an exemplary three-dimensional (3D) memory device 100 according to some embodiments of the present disclosure. The 3D memory device 100 may be a memory chip (package), a memory die, or any portion of a memory die, and may include one or more memory planes 101, each of which may include multiple memory blocks 103. Identical and simultaneous operations may be performed in each memory plane 101. The memory blocks 103 may be megabytes (MB) in size, and the memory blocks 103 may be a minimum size for performing an erase operation. As shown in FIG. 1, the exemplary 3D memory device 100 includes four memory planes 101, each of which includes six memory blocks 103. Each memory block 103 may include multiple memory cells, where each memory cell may be addressed through interconnects such as bit lines and word lines. The bit lines and word lines may be laid out vertically (e.g., in rows and columns, respectively) to form an array of metal lines. The bit line and word line directions are labeled as "BL" and "WL" in FIG. 1. In this disclosure, the memory block 103 is also referred to as a "memory array" or "array." The memory array is the core area in a memory device and performs the storage function.

[0042] The 3D memory device 100 also includes a peripheral region 105 (the area surrounding the memory plane 101). The peripheral region 105 may contain many digital, analog, and / or mixed-signal circuits to support the functionality of the memory array (e.g., page buffers, row and column decoders, and sense amplifiers). The peripheral circuits use active and / or passive semiconductor devices (e.g., transistors, diodes, capacitors, resistors, etc.), as will be apparent to one skilled in the art.

[0043] It is noted that the arrangement of memory planes 101 in the 3D memory device 100 and the arrangement of memory blocks 103 in each memory plane 101 illustrated in FIG. 1 are provided merely as examples and are not intended to limit the scope of the present disclosure.

[0044] Referring to FIG. 1B, an enlarged top view of the region 108 in FIG. 1A is illustrated according to some embodiments of the present disclosure. The region 108 of the 3D memory device 100 can include a staircase region 210 and a channel structure region 211. The channel structure region 211 can include an array of memory strings 212, each of which includes a plurality of stacked memory cells. The staircase region 210 can include a staircase structure and an array of contact structures 214 formed on the staircase structure. In some embodiments, a plurality of slit structures 216 extend in the WL direction across the channel structure region 211 and the staircase region 210, and the plurality of slit structures 216 can divide the memory block into a plurality of memory fingers 218. At least some of the slit structures 216 can function as a common source contact for the array of memory strings 212 in the channel structure region 211. A top select gate cut 220 is disposed in the center of each memory finger 218 and can split the top select gate (TSG) of the memory finger 218 into two parts, thereby dividing the memory finger into two programmable (read / write) pages. The erase operation of the 3D NAND memory can be performed at the memory block level, while the read and write operations can be performed at the memory page level. The pages can be kilobytes (KB) in size. In some embodiments, the region 108 also includes dummy memory strings for process variation control during fabrication and / or for additional mechanical support.

[0045] 2 illustrates a perspective view of a portion of an exemplary three-dimensional (3D) memory array structure 200 according to some embodiments of the present disclosure. The memory array structure 200 includes a substrate 330, an insulating film 331 above the substrate 330, a level of lower select gates (LSG) 332 above the insulating film 331, and multiple levels of control gates 333 (also referred to as "word lines (WL)") stacked on the LSG 332 to form a film stack 335 of alternating conductive and dielectric layers. Dielectric layers adjacent to the levels of control gates are not shown in FIG. 2 for clarity.

[0046] The control gates of each level are separated by slit structures 216-1 and 216-2 through the film stack 335. The memory array structure 200 also includes a level of top select gates (TSGs) 334 above the stack of control gates 333. The stack of TSGs 334, the control gates 333, and the LSGs 332 are also referred to as "gate electrodes." The memory array structure 200 further includes memory strings 212 and doped source line regions 344 in the portions of the substrate 330 between adjacent LSGs 332. Each memory string 212 includes a channel hole portion 336 that extends through the insulating film 331 and the film stack 335 of alternating conductive and dielectric layers. The memory string 212 may also include a memory film 337 on the sidewalls of the channel hole portion 336, a channel layer 338 above the memory film 337, and a core fill film 339 surrounded by the channel layer 338. A memory cell 340 may be formed at the intersection of a control gate 333 and a memory string 212. The memory array structure 200 further includes a number of bit lines (BL) 341 connected to the memory strings 212 above the TSG 334. The memory array structure 200 also includes a number of metal interconnect lines 343 connected to the gate electrodes through a number of contact structures 214. The edges of the film stack 335 are configured in a staircase shape to allow electrical connection to each level of the gate electrodes.

[0047] In FIG. 2, for illustrative purposes, three levels of control gates 333-1, 333-2, and 333-3 are shown, along with one level of TSG 334 and one level of LSG 332. In this example, each memory string 212 may include three memory cells 340-1, 340-2, and 340-3, which correspond to control gates 333-1, 333-2, and 333-3, respectively. In some embodiments, the number of control gates and the number of memory cells may be greater than three to increase storage capacity. The memory array structure 200 may also include other structures, such as, for example, TSG cuts, common source contacts, and dummy channel structures. These structures are not shown in FIG. 2 for simplicity.

[0048] To achieve higher storage density, the number of vertical WL stacks of 3D memory, or the number of memory cells per memory string, has been significantly increased, for example, from 24 stacked WL layers (i.e., 24L) to 128 layers or more. To further reduce the size of 3D memory, the memory array can be stacked on the peripheral circuitry, or vice versa. For example, the peripheral circuitry can be fabricated on a first substrate, and the memory array can be fabricated on a second substrate. The memory array and the peripheral circuitry can then be electrically coupled (e.g., electrically connected or physically contacted and connected) through various interconnects by bonding the first and second substrates together. As such, not only can the 3D memory density be increased, but the communication between the peripheral circuitry and the memory array can achieve higher bandwidth and lower power consumption. This is because the interconnect length can be shorter through substrate (wafer) bonding.

[0049] As the density and performance of 3D memory devices increases, improved peripheral circuitry is also required to provide functional support for the memory array (e.g., reading, writing, and erasing data in memory cells). Isolation structures can be implemented in the combined peripheral / memory array wafer to prevent crosstalk between adjacent structures (e.g., between wells of different doping types). Isolation structures can be formed by thinning the dielectric layer of the peripheral wafer and by forming Through Silicon Isolation (TSI) structures to effectively separate different functional regions.

[0050] FIG. 3 is a flow diagram of an exemplary method 300 for forming an isolation structure in a 3D memory device according to some embodiments of the present disclosure. The 3D memory device may be formed by connecting a peripheral circuit wafer with a memory array wafer through wafer bonding and by forming deep isolation structures in the peripheral circuit wafer to prevent crosstalk. The operations of the method 300 may be performed in a different order and / or may vary, and the method 300 may include more operations not described for simplicity. FIGS. 3-9 are cross-sectional views of fabricating an exemplary semiconductor structure 300 incorporating an isolation structure. FIGS. 3-9 are provided as exemplary cross-sectional views to facilitate the description of the method 300. Although a fabrication process for forming an isolation structure in a dielectric layer is described herein as an example, the fabrication process may be applied over a variety of other layers (e.g., over an interlayer dielectric, an insulating layer, a conductive layer, and any other suitable layer, etc.). The fabrication process provided herein is exemplary, and alternative processes according to the present disclosure not shown in these figures may be implemented.

[0051] In operation 302, a peripheral circuit wafer of a 3D memory device is formed according to some embodiments of the present disclosure. With reference to Figure 4, the peripheral circuit 400 can include various components of a 3D memory device, such as a first substrate 430, peripheral devices 450A and 450B, shallow trench isolation (STI) 452, wells 454, gate stacks 456, gate spacers 458, and peripheral interconnect layers 462.

[0052] The first substrate 430 can include silicon (e.g., single crystal silicon), silicon germanium (SiGe), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), gallium arsenide (GaAs), gallium nitride, silicon carbide, glass, III-V compounds, any other suitable material, or any combination thereof. In some embodiments, the first substrate 430 can be double-sided polished prior to peripheral device fabrication. In this example, the first substrate 430 includes surfaces on the top and bottom sides (also referred to as the first side 430-1 and second side 430-2, or front side and back side, respectively) that are both polished and processed to provide a smooth surface for high quality semiconductor devices. The first and second sides are opposite sides of the first substrate 430.

[0053] The peripheral circuit 400 may include one or more peripheral devices 450A and 450B on a first substrate 430. The peripheral devices 450A and 450B may be adjacent to one another and formed on the first substrate 430, with all or a portion of the peripheral devices 450A and 450B formed in (e.g., below an upper surface of) and / or directly on the first substrate 430. The peripheral devices 450A and 450B may include any suitable semiconductor devices, for example, the peripheral device 450A may be a low-voltage p-type device and the peripheral device 450B may be a high-voltage p-type device. Also, the peripheral devices 450A and 450B may be metal oxide semiconductor field effect transistors (MOSFETs), bipolar junction transistors (BJTs), diodes, resistors, capacitors, inductors, etc. Among semiconductor devices, p-type and / or n-type MOSFETs (i.e., CMOS) are widely implemented in logic circuit design and are used as examples for peripheral devices 450A and 450B in this disclosure. Therefore, peripheral circuit 400 may also be referred to as CMOS wafer 400. Peripheral device 450 may be either p-channel MOSFET or n-channel MOSFET and may include, but is not limited to, an active device region surrounded by shallow trench isolation (STI) 452, a well 454 formed in the active device region with n-type or p-type doping, a gate stack 456 including a dielectric, a gate conductor, and / or a gate hard mask. Peripheral devices 450A and 450B may also include source / drain extensions and / or halo regions (not shown in FIG. 4), gate spacers 458 and source / drain 460 positioned on each side of the gate stack. Peripheral devices 450A and 450B may further include a silicide contact area (not shown) on the top portion of the source / drain. Other suitable devices may also be formed on the first substrate 430.

[0054] The STI 452 may be formed through patterning a substrate using lithography and etching, filling with insulating material, polishing the insulating material, and forming a coplanar surface on the first substrate 430. The insulating material for the STI may include silicon oxide, silicon oxynitride, TEOS, low temperature oxide (LTO), high temperature oxide (HTO), silicon nitride, and the like. The insulating material for the STI 452 may be disposed using techniques such as, for example, chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma enhanced CVD (PECVD), low pressure chemical vapor deposition (LPCVD), high density plasma (HDP) chemical vapor deposition, rapid thermal chemical vapor deposition (RTCVD), metal organic chemical vapor deposition (MOCVD), atomic layer deposition (ALD), sputtering, thermal oxidation or thermal nitridation, or combinations thereof, and the like. The formation of the STI 452 may also include a high temperature annealing step to densify the disposed insulating material for improved electrical isolation.

[0055] The wells 454 of the peripheral devices 450A and 450B may contain p-type doping for n-channel MOSFETs or n-type doping for p-channel MOSFETs, and are referred to as p-wells and n-wells, respectively. The dopant profile and concentration of the wells 454 affect the device characteristics of the peripheral devices 450A or 450B. A low threshold voltage (V t For MOSFET devices with high V t For MOSFETs with , well 454 can be doped at a higher concentration to form a high-voltage p-well or a high-voltage n-well. In some embodiments, a deep n-well is used to provide electrical isolation from the p-type substrate. tIn some embodiments, peripheral device 450A is a low voltage device while peripheral device 450B is a high voltage device and well 454 can be an n-type well buried in substrate 430, which can be a p-type substrate.

[0056] The formation of the n-well can include any suitable n-type dopant, such as phosphorus, arsenic, antimony, etc., and / or any combination thereof. The formation of the p-well can include any suitable p-type dopant, such as boron. The dopant incorporation can be achieved through ion implantation (followed by an activation anneal) or through in-situ doping during epitaxy for the active device regions.

[0057] The gate stacks 456 of the peripheral devices 450A and 450B may be formed by a "gate first" scheme, where the gate stacks 456 are deposited and patterned before source / drain formation, or by a "swap" scheme, where a sacrificial gate stack may be formed first and then replaced by a high-k dielectric layer and gate conductor after source / drain formation.

[0058] In some embodiments, the gate dielectric may be made of silicon oxide, silicon nitride, silicon oxynitride, and / or high-k dielectric films, such as hafnium oxide, zirconium oxide, aluminum oxide, tantalum oxide, magnesium oxide, or lanthanum oxide films, and / or combinations thereof. The gate dielectric may be disposed by any suitable method, such as CVD, PVD, PECVD, LPCVD, RTCVD, sputtering, MOCVD, ALD, thermal oxidation or nitridation, or combinations thereof.

[0059] In some embodiments, the gate conductor may be formed from a metal or metal alloy, such as, for example, tungsten, cobalt, nickel, copper, or aluminum, and / or combinations thereof. In some embodiments, the gate conductor may include a conductive material, such as, for example, titanium nitride (TiN), tantalum nitride (TaN), etc. The gate conductor may be formed by any suitable deposition method, such as, for example, sputtering, thermal evaporation, e-beam evaporation, ALD, PVD, and / or combinations thereof.

[0060] In some embodiments, the gate conductor may include a polycrystalline semiconductor, such as polycrystalline silicon, polycrystalline germanium, polycrystalline germanium-silicon, and any other suitable material and / or combinations thereof. In some embodiments, the polycrystalline material may incorporate any suitable type of dopant, such as boron, phosphorous, or arsenic. In some embodiments, the gate conductor may also be an amorphous semiconductor with the above-mentioned materials.

[0061] In some embodiments, the gate conductor is a metal silicide (WSi x , CoSi x , NiSi x , or AlSi x The metal silicide material may be formed from a metal layer and a polycrystalline semiconductor layer, including a polysemiconductor layer, a polycrystalline semiconductor layer, and the like. The formation of the metal silicide material may include forming a metal layer and a polycrystalline semiconductor layer using similar techniques as described above. The formation of the metal silicide may further include applying a thermal annealing process on the deposited metal layer and the polycrystalline semiconductor layer, followed by removal of unreacted metal.

[0062] The gate spacer 458 may be formed through depositing an insulating material and then performing an anisotropic etch. The insulating material for the gate spacer 458 can be any insulator, including silicon oxide, silicon nitride, silicon oxynitride, TEOS, LTO, HTO, and the like. The gate spacer 458 may be deposited using techniques such as CVD, PVD, PECVD, LPCVD, RTCVD, MOCVD, ALD, sputtering, or combinations thereof, and the like. The anisotropic etch of the gate spacer 458 includes dry etching, for example, reactive ion etching (RIE).

[0063] The length of the gate stack 456 between the source / drain 460 is a key feature of the MOSFET. The gate length L determines the magnitude of the drive current of the MOSFET and is therefore aggressively scaled down for logic circuits. The gate length can be less than about 100 nm. In some embodiments, the gate length can range between about 5 nm and about 30 nm. Patterning of gate stacks with such small dimensions is very challenging and can use techniques including optical proximity correction, double exposure and / or double etching, self-aligned double patterning, etc.

[0064] In some embodiments, the source / drain 460 of the peripheral devices 450A and 450B incorporate a high concentration of dopants. For n-type MOSFETs, the dopants for the source / drain 460 can include any suitable n-type dopant, such as phosphorus, arsenic, antimony, etc., and / or any combination thereof. For p-type MOSFETs, the dopants for the source / drain 460 can include any suitable p-type dopant, such as boron. Dopant incorporation can be achieved through ion implantation followed by a dopant activation anneal. The source / drain 460 can be made of the same material (e.g., silicon) as the first substrate 430. In some embodiments, the source / drain 460 of the peripheral devices 450A and 450B can be made of a different material than the first substrate 430 to achieve high performance. For example, on a silicon substrate, the source / drain 460 for the p-type MOSFET can include SiGe, and the source / drain 460 for the n-type MOSFET can incorporate carbon. Forming the source / drain 460 with a different material can include etching back the substrate material in the source / drain area and depositing new source / drain material using techniques such as epitaxy, etc. Also, doping for the source / drain 460 can be achieved through in-situ doping during epitaxy.

[0065] The peripheral devices 450A and 450B may also have optional source / drain extensions and / or halo regions (not shown in FIG. 2) along each side of the gate stack 456. The source / drain extensions and / or halo regions are located inside the active device region below the gate stack and are primarily implemented for improved short channel control for peripheral devices 450A and 450B having channel lengths less than about 0.5 μm. The formation of the source / drain extensions and / or halo regions may be similar to the formation of the source / drain 460, but different implantation conditions (e.g., dose, angle, energy, species, etc.) may be used to obtain optimized doping profiles, depths, or concentrations.

[0066] The peripheral devices 450A and 450B may be formed on a first substrate 430 with a planar active device area (as shown in FIG. 4), where the MOSFET's channel and current direction are parallel to the surface of the first substrate 430. In some embodiments, the peripheral devices 450A and 450B may be formed on a first substrate 430 with a 3D active device area (e.g., a so-called "FINFET" (not shown) shaped like a "FIN"), where the MOSFET's gate stack is encapsulated in the FIN and the MOSFET's channel lies along three sides of the FIN (the top and two sidewalls under the gate).

[0067] In some embodiments, the peripheral circuit 400 may include a peripheral interconnect layer 462 (or a first interconnect layer) above the peripheral devices 450A and 450B to provide electrical connections between the different peripheral devices 450A and 450B and external devices (e.g., another chip that provides power, an I / O device, etc.). The peripheral interconnect layer 462 may include one or more interconnect structures, such as one or more vertical contact structures 464 and one or more lateral conductive lines 466. The contact structures 464 and the conductive lines 466 may broadly include any suitable type of interconnect, such as, for example, middle-of-line (MOL) interconnects and back-end-of-line (BEOL) interconnects. The contact structures 464 and conductive lines 466 in the peripheral circuitry 400 may be made of any suitable conductive material, such as tungsten (W), cobalt (Co), copper (Cu), titanium (Ti), tantalum (Ta), aluminum (Al), titanium nitride (TiN), tantalum nitride (TaN), nickel silicide (WSi x , CoSi x , NiSi x , AlSi x The conductive material may include a metal alloy, a conductive material such as a conductive material ...

[0068] The peripheral interconnect layer 462 may further include an insulating layer 468. The insulating layer 468 in the peripheral interconnect layer 462 may include an insulating material, such as silicon oxide, silicon nitride, silicon oxynitride, doped silicon oxide (e.g., F, C, N, or H doped oxide), tetraethoxysilane (TEOS), polyimide, spin-on glass (SOG), low-k dielectric materials such as porous SiCOH, silsesquioxane (SSQ), or any combination thereof. The insulating material may be deposited by one or more thin film deposition processes, such as CVD, PVD, PECVD, ALD, high density plasma CVD (HDP-CVD), sputtering, spin coating, or any combination thereof.

[0069] 4, two conductive levels 470-1 and 470-2 (also referred to as "metal levels") are illustrated by way of example, where each metal level may include contact structures 464 and conductive lines 466, with the conductive lines 466 of the same metal level positioned at the same distance from the first substrate 430. The number of metal levels 470 for the peripheral circuitry 400 is not limited and can be any number optimized for the performance of the 3D memory.

[0070] The peripheral interconnect layer 462 may be formed by stacking metal levels 470 from the bottom to the top of the peripheral circuit 400. In the example of the peripheral circuit 400 of FIG. 4, a bottom metal level 470-1 may be formed first, and then an upper metal level 470-2 may be formed on top of the bottom metal level 470-1. The fabrication process of each metal level 470 may include, but is not limited to, disposing a portion of an insulating layer 468 having a thickness required for the metal level, patterning the portion of the insulating layer 468 using photolithography and dry / wet etching to form contact holes for the contact structures 464 and the conductive lines 466, disposing a conductive material to fill the contact holes for the contact structures 464 and the conductive lines 466, and removing the excess conductive material outside the contact holes by using a planarization process such as chemical mechanical polishing (CMP) or reactive ion etching (RIE).

[0071] Also, in some embodiments, the peripheral circuitry 400 may include one or more substrate contacts 472, where the substrate contacts 472 provide electrical connection to the first substrate 430. The substrate contacts 472 may include one or more conductive levels 470 with multiple levels of vertical contact structures 464 and lateral conductive lines 466. In FIG. 4, a substrate contact 472 with one level of contact structures and conductive lines is shown as an example, where the vertical contact structures of the substrate contact 472 extend through the insulating layer 468 and electrically contact the first substrate 430.

[0072] In some embodiments, the top conductive line 466 (e.g., 466-2 in FIG. 4) may be exposed as a top surface of the peripheral circuit 400, where the top conductive line 466-2 may be directly connected to a conductive line on another chip or an external device.

[0073] In some embodiments, the top conductive line 466-2 may be embedded inside an insulating layer 468 (as shown in FIG. 4), where the insulating material on top of the conductive line 466 provides scratch protection during shipping or handling. Electrical connection to the top conductive line 466 may be established subsequently by forming a metal VIA or simply by etching back the insulating layer 468 using a dry / wet etch.

[0074] However, the peripheral devices 450A and 450B are not limited to MOSFETs. Structures of other devices (e.g., diodes, resistors, capacitors, inductors, BJTs, etc.) can be formed simultaneously during MOSFET fabrication through different mask designs and layouts. To form devices other than MOSFETs, process steps can be added or modified in the MOSFET process flow, such as to obtain different dopant profiles, film thicknesses, or material stacks. Also, in some embodiments, peripheral devices other than MOSFETs 450A and 450B can be fabricated through additional designs and / or lithography mask levels to achieve specific circuit requirements.

[0075] In some embodiments, multiple peripheral devices 450A and 450B can be used to form any digital, analog, and / or mixed-signal circuitry for operation of peripheral circuit 400. Peripheral circuit 400 can perform, for example, row / column decoding, timing and control, reading, writing, and erasing data of a memory array, etc.

[0076] In some embodiments, a deep well 455 may be formed in the first substrate 430 while forming the well 454 for the MOSFET. The deep well 455 may be p-type doped or n-type doped. The n-type dopant may be phosphorus, arsenic, antimony, etc. The p-type dopant may be, for example, boron. The dopant incorporation may be achieved through ion implantation of the first substrate 430 followed by an activation anneal. In some embodiments, the deep well 455 may be formed on the first substrate 430 through epitaxy and in situ doping. The implantation for the deep well 455 may be performed immediately before or after the implantation of the well 454. The dopant activation anneal for the deep well 455 may be performed simultaneously with that for the well 454. In some embodiments, a deep well contact 473 may be formed to provide an electrical connection to the deep well 455. In some embodiments, the deep well contact 473 forms an ohmic contact with the deep well 455. The deep well contact 473 can form an electrical connection with corresponding circuitry of the peripheral circuitry 400 through contact structures 464 and conductive lines 466 in the peripheral interconnect layer 462. For example, the deep well contact 473 can be connected to ground, a substrate contact 472 of the first substrate 430, a source or drain 460, or a gate stack 456 of the peripheral devices 450A and 450B, etc.

[0077] In operation 304, a 3D memory array according to some embodiments of the present disclosure is formed. With reference to FIG. 5, the 3D memory array 500 can be a 3D NAND memory array and can include a second substrate 530, memory cells 540, and an array interconnect layer 562 (or a second interconnect layer). The second substrate 530 can be similar to the first substrate 430. The memory cells 540 can be similar to the memory cells 340-1, 340-2, or 340-3 described above with reference to FIG. 2. The array interconnect layer 562 can be similar to the peripheral interconnect layer 462 and can be formed using similar materials and similar processes. For example, the interconnect structures (e.g., contact structures 564 and conductive lines 566) and the insulating layer 568 of the array interconnect layer 562 are similar to the interconnect structures (e.g., contact structures 464, conductive lines 466) and the insulating layer 468 of the peripheral interconnect layer 462, respectively.

[0078] In some embodiments, the 3D memory array 500 can be a memory array for a 3D NAND flash memory, in which the memory cells 540 can be stacked vertically as memory strings 212. The memory strings 212 extend through a plurality of conductor layer 574 and dielectric layer 576 pairs. The plurality of conductor / dielectric layer pairs are also referred to herein as "alternating conductor / dielectric stacks" 578. The conductor layers 574 and dielectric layers 576 in the alternating conductor / dielectric stacks 578 alternate vertically. In other words, each conductor layer 574 can be sandwiched by two dielectric layers 576 on both sides, except at the top or bottom of the alternating conductor / dielectric stacks 578, and each dielectric layer 576 can be sandwiched by two conductor layers 574 on both sides. The conductor layers 574 can have the same thickness or different thicknesses. Similarly, the dielectric layers 576 can have the same thickness or different thicknesses. In some embodiments, the alternating conductor / dielectric stack 578 includes more conductor layers or more dielectric layers having different materials and / or thicknesses than the conductor / dielectric layer pairs. The conductor layers 574 can include a conductor material such as tungsten, cobalt, copper, aluminum, titanium, tantalum, titanium nitride, tantalum nitride, nickel, doped silicon, silicide (e.g., NiSix, WSix, CoSix, TiSix), or any combination thereof. The dielectric layers 576 can include a dielectric material such as silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof.

[0079] As shown in FIG. 5, each memory string 212 can include a channel layer 338 and a memory film 337. In some embodiments, the channel layer 338 includes silicon, such as amorphous silicon, polysilicon, or single crystal silicon. In some embodiments, the memory film 337 is a composite layer including a tunneling layer, a storage layer (also known as a "charge trap / storage layer"), and a blocking layer. Each memory string 212 can have a cylindrical shape (e.g., a pillar shape). According to some embodiments, the channel layer 338, the tunneling layer, the storage layer, and the blocking layer are arranged in this order along a direction from the center toward the outer surface of the pillar. The tunneling layer can include silicon oxide, silicon nitride, or any combination thereof. The blocking layer can include silicon oxide, silicon nitride, a high dielectric constant (high-k) dielectric, or any combination thereof. The storage layer can include silicon nitride, silicon oxynitride, silicon, or any combination thereof. In some embodiments, the memory film 337 includes an ONO dielectric (eg, a tunneling layer comprising silicon oxide, a storage layer comprising silicon nitride, and a blocking layer comprising silicon oxide).

[0080] In some embodiments, each conductor layer 574 in the alternating conductor / dielectric stack 578 can serve as a control gate (e.g., control gate 333 of FIG. 3 ) for each memory cell of the memory string 212. As shown in FIG. 5 , the memory string 212 can include a lower select gate 332 (e.g., source select gate) at a lower end of the memory string 212. The memory string 212 can also include an upper select gate 334 (e.g., drain select gate) at an upper end of the memory string 212. As used herein, an “upper end” of a component (e.g., memory string 212) is an end that is farther away from the second substrate 530 in the z-direction, and a “lower end” of a component (e.g., memory string 212) is an end that is closer to the second substrate 530 in the z-direction. As shown in FIG. 5 , for each memory string 212, the drain select gate 334 can be above the source select gate 332. In some embodiments, the select gates 332 / 334 include a conductive material, such as tungsten, cobalt, copper, aluminum, doped silicon, silicide, or any combination thereof.

[0081] In some embodiments, the 3D memory array 500 can include an epitaxial layer 580 at a lower end of the channel layer 338 of the memory string 212. The epitaxial layer 580 can include a semiconductor material (e.g., silicon, etc.). The epitaxial layer 580 can be epitaxially grown from a semiconductor layer 582 on the second substrate 530. The semiconductor layer 582 can be undoped, partially doped (in the thickness direction and / or width direction), or fully doped with p-type or n-type dopants. With respect to each memory string 212, the epitaxial layer 580 is referred to herein as an “epitaxial plug.” The epitaxial plug 580 at the lower end of each memory string 212 can contact both the channel layer 338 and a doped region of the semiconductor layer 582. The epitaxial plug 580 may function as a channel for the lower select gate 332 at the lower end of the memory string 212 .

[0082] In some embodiments, the array device further includes a number of word line contact structures 214 (also referred to as word line contacts) in the staircase region 210. Each word line contact structure 214 makes electrical contact with a corresponding conductor layer 574 in the alternating conductor / dielectric stack 578 and is capable of individually controlling the memory cells 340. The word line contact structures 214 may be formed by dry / wet etching of contact holes followed by filling with a conductor, such as tungsten, titanium, titanium nitride, copper, tantalum nitride, aluminum, cobalt, nickel, or any combination thereof.

[0083] 5, the 3D memory array 500 also includes bit line contacts 584 formed over the memory strings 212 and providing individual access to the channel layers 338 of the memory strings 212. The word line contact structures 214 and the conductive lines connected with the bit line contacts 584 form the word lines and bit lines, respectively, of the 3D memory array 500. Typically, the word lines and bit lines are oriented perpendicular to one another (e.g., in rows and columns, respectively) to form a memory "array."

[0084] In some embodiments, the 3D memory array 500 also includes substrate contacts 572 of the second substrate 530. The substrate contacts 572 may be formed using similar materials and processes as the substrate contacts 472 of the first substrate 430. The substrate contacts 572 may provide electrical connection to the second substrate 530 of the 3D memory array 500.

[0085] In operation 306, the peripheral circuit wafer and the 3D memory array wafer according to some embodiments of the present disclosure are bonded. Referring to FIG. 6, the 3D memory device 600 is formed by wafer bonding the peripheral circuit 400 fabricated on the first substrate 430 and the 3D memory array 500 fabricated on the second substrate 530. As shown in FIG. 6, the peripheral circuit 400 is flipped upside down and bonded with the 3D memory array 500 through a suitable wafer bonding process (e.g., direct bonding or hybrid bonding, etc.). At the bonding interface 688, the peripheral circuit 400 and the 3D memory array 500 are electrically connected through a plurality of interconnect VIA 486 / 586.

[0086] In some embodiments, the bonding interface 688 of the 3D memory device 600 is located between the insulating layer 468 of the peripheral interconnect layer 462 and the insulating layer 568 of the array interconnect layer 562. The interconnect VIAs 486 and 586 are joined at the bonding interface 688 and can electrically connect any conductive line 466 or contact structure 464 of the peripheral interconnect layer 462 and any conductive line 566 or contact structure 564 of the array interconnect layer 562. As such, the peripheral circuitry 400 and the 3D memory array 500 can be electrically connected.

[0087] In some embodiments, the bonding interface 688 of the 3D memory device 600 is located inside the bonding layer 690. In this example, the interconnect vias 486 and 586 extend through the bonding layer 690 and form electrical connections between any conductive lines 466 or contact structures 464 of the peripheral interconnect layer 462 and the conductive lines 566 or contact structures 564 of the array interconnect layer 562. As such, the peripheral circuitry 400 and the 3D memory array 500 may also be electrically connected.

[0088] In some embodiments, the bonding layer 690 may be disposed on the peripheral circuitry 400 (FIG. 4) and / or the 3D memory array 500 (FIG. 5) prior to the bonding process. The bonding layer 690 may include a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. The bonding layer 690 may also include an adhesive material, such as an epoxy resin, a polyimide, a dry film, a photosensitive polymer, or the like. The bonding layer 690 may be formed by one or more thin film deposition processes, such as CVD, PVD, PECVD, ALD, high density plasma CVD (HDP-CVD), sputtering, spin coating, or any combination thereof.

[0089] In some embodiments, after forming the bonding layer 690, the interconnects VIA 486 and 586 may be formed for the peripheral circuitry 400 and the 3D memory array 500, respectively. The interconnects VIA 486 / 586 may include a metal or metal alloy, such as copper (Cu), tin (Sn), nickel (Ni), gold (Au), silver (Ag), titanium (Ti), aluminum (Al), titanium nitride (TiN), tantalum nitride (TaN), or the like, or any combination thereof. The metal or metal alloy of the interconnects VIA 486 / 586 may be disposed by one or more thin film deposition processes, such as chemical vapor deposition (CVD), plasma enhanced CVD (PECVD), physical vapor deposition (PVD), atomic layer deposition (ALD), electroplating, electroless plating, sputtering, evaporation, or any combination thereof. The fabrication process of the interconnect VIA486 / 586 may further include, but is not limited to, photolithography, wet / dry etching, planarization (eg, CMP, or RIE etchback), and so on.

[0090] In some embodiments, the peripheral circuitry 400 and the 3D memory array 500 can be bonded together at the die level (e.g., die-to-die or chip-to-chip) or at the wafer level (e.g., wafer-to-wafer or chip-to-wafer) depending on the product design and manufacturing strategy. Bonding at the wafer level can provide high throughput, where all dies / chips on the first substrate 430 with the peripheral circuitry 400 can be bonded simultaneously to the second substrate 530 with the 3D memory array 500. The individual 3D memory devices 600 can be diced after wafer bonding. On the other hand, bonding at the die level can be performed after dicing and die testing, where functional dies of the peripheral circuitry 400 and the 3D memory array 500 can be selected first and then bonded to form the 3D memory device 600, allowing a higher yield of the 3D memory device 600.

[0091] In some embodiments, during the bonding process, the peripheral interconnect layer 462 may be aligned with the array interconnect layer 562 as the interconnect vias 486 of the peripheral circuitry 400 are aligned with corresponding interconnect vias 586 of the 3D memory array 500. As a result, the corresponding interconnect vias 486 / 586 may be connected at the bonding interface 688 and the 3D memory array 500 may be electrically connected with the peripheral circuitry 400.

[0092] In some embodiments, the peripheral circuitry 400 and the 3D memory array 500 may be joined by hybrid bonding. Hybrid bonding, particularly metal / dielectric hybrid bonding, is a direct bonding technique (e.g., forming a bond between surfaces without using an intermediate layer (e.g., solder or adhesive)) that simultaneously obtains metal-metal bonding and dielectric-dielectric bonding. During the bonding process, chemical bonds may be formed at the metal-metal bonding surfaces and the dielectric-dielectric surfaces.

[0093] In some embodiments, the peripheral circuitry 400 and the 3D memory array 500 may be bonded by using a bonding layer 690. At the bonding interface 688, bonding may be between silicon nitride and silicon nitride, silicon oxide and silicon oxide, or silicon nitride and silicon oxide, in addition to metal to metal bonding. In some embodiments, the bonding layer may also include an adhesive material (e.g., epoxy resin, polyimide, dry film, etc.) to enhance the bond strength.

[0094] In some embodiments, a treatment process may be used to enhance the bonding strength at the bond interface 688. The treatment process may prepare the surfaces of the array interconnect layer 562 and the peripheral interconnect layer 462 such that the surfaces of the insulating layer 568 / 468 form chemical bonds. The treatment process may include, for example, a plasma treatment (e.g., with a plasma containing F, Cl, or H) or a chemical process (e.g., with formic acid). In some embodiments, the treatment process may include a thermal process, which may be performed at a temperature of about 250° C. to about 600° C. in a vacuum or inert environment (e.g., with nitrogen or argon). The thermal process may cause metal interdiffusion between the interconnect vias 486 and 586. As a result, the metal materials in the corresponding pairs of interconnect vias may mix with each other or form an alloy after the bonding process.

[0095] After bonding the peripheral interconnect layer and the array interconnect layer together, at least one peripheral device of the peripheral circuitry 400 fabricated on the first substrate 430 may be electrically connected to at least one memory cell of the 3D memory array 500 fabricated on the second substrate 530. Although FIG. 6 illustrates the peripheral circuitry 400 being coupled on top of the 3D memory array 500, the 3D memory array 500 may also be coupled on top of the peripheral circuitry 400.

[0096] Through bonding, the 3D memory device 600 can function similarly to a 3D memory in which the peripheral circuits and memory array are fabricated on the same substrate (as shown in FIG. 1). By stacking the 3D memory array 500 and the peripheral circuits 400 on top of each other, the density of the 3D memory device 600 can be increased. Meanwhile, by using a stacked design, the bandwidth of the 3D memory device 600 can be increased due to the fact that the interconnect distance between the peripheral circuits 400 and the 3D memory array 500 can be reduced. After the bonding process, the peripheral circuits 400 have a backside 430-2 exposed and ready for subsequent processing.

[0097] In operation 308, the peripheral circuitry wafer is thinned and a dielectric layer is disposed, according to some embodiments of the present disclosure. Referring to Figure 7, a 3D memory device 700 is illustrated similar to the 3D memory device 600 of Figure 6 and also includes the peripheral circuitry 400 and the 3D memory array 500. The peripheral circuitry 400 is bonded to the 3D memory array 500 at a bonding interface 688. The 3D memory device 700 may be formed by thinning the first substrate 430 of the peripheral circuitry 400 after forming the 3D memory device 600 through bonding.

[0098] In some embodiments, the first substrate 430 of the peripheral circuitry 400 may be thinned from the backside 430-2. In some embodiments, the substrate thinning process may include one or more of grinding, dry etching, wet etching, and chemical mechanical polishing (CMP). The thickness T of the first substrate 430 after thinning may range from about 1 μm to about 5 μm. For example, the thickness T may be between about 2 μm to about 4 μm. In some embodiments, the thinning process may continue until the deep well 455 is exposed.

[0099] After the first substrate 430 is thinned, a dielectric layer 792 may be disposed on the backside 430-1 (or second side) of the first substrate 430. The dielectric layer 792 may be any suitable semiconductor material, such as silicon oxide, silicon nitride, silicon oxynitride, doped silicon oxide (e.g., F, C, N, or H doped oxide), tetraethoxysilane (TEOS), polyimide, spin-on glass (SOG), low-k dielectric materials such as porous SiCOH, silsesquioxane (SSQ), or any combination thereof. The insulating material may be deposited by one or more thin film deposition processes, such as CVD, PVD, PECVD, ALD, high density plasma CVD (HDP-CVD), sputtering, spin coating, or any combination thereof. After deposition, the dielectric layer 792 covers the entire surface of the first substrate 430. In some embodiments, the thickness t of the dielectric layer 792 can be between about 100 nm and about 1 μm. In some embodiments, the thickness t can be between about 300 nm and about 600 nm. For example, the thickness t can be about 500 nm.

[0100] In operation 310, deep isolation trenches are formed in the peripheral circuit wafer and between adjacent devices. Referring to FIG. 8, a 3D memory device 800 includes a plurality of deep isolation trenches 894 formed in the backside 430-2 of the first substrate 430. The isolation trenches penetrate the dielectric layer 792 and a portion of the first substrate 430 until the STIs 452 are exposed at the bottom of the isolation trenches 894. In some embodiments, the deep isolation trenches 894 also expose portions of the wells 454 and other structures of the peripheral devices 450A and 450B.

[0101] The cross-sectional shape and number of deep isolation trenches may be determined by various factors, such as the amount of need for device isolation and the type of device. For example, a single deep isolation structure may be formed over the STI 452. In some embodiments, two or more deep isolation structures may be formed over the STI 452. In some embodiments, any suitable number of deep isolation trenches may be used. Also, the deep isolation trenches may have any suitable cross-sectional shape. For example, the cross-sectional shape of the deep isolation trench 894 illustrated in FIG. 8 may have a trapezoidal shape and have a top width W1 measured at the top of the deep isolation trench 894 and a bottom width W2 measured at the bottom of the deep isolation trench 894. As illustrated in FIG. 8, the deep isolation trench 894 may have a larger width at the top than at the bottom of the structure, and such a configuration may prevent voids in the subsequently deposited isolation material. In some embodiments, the width W1 may range between about 0.1 μm and about 5 μm. In some embodiments, the width W2 can range between about 0.05 μm and about 0.25 μm. In some embodiments, the widths W1 and W2 can be substantially the same. For example, the widths W1 and W2 can be about 0.2 μm. In some embodiments, the top-bottom ratio R1 of W1 to W2 can be between about 1.5 and about 2.5. For example, R1 can be about 2. In some embodiments, when the deep isolation trench 894 can penetrate both the dielectric layer 792 and a portion of the first substrate 430, the depth D of the deep isolation trench 894 can range between about 1 μm and about 6 μm. In some embodiments, the depth of the STI 452 can range between about 300 nm and about 450 nm.In some embodiments, the ratio of the depth D to the combined thickness (thicknesses T and t) of the thinned first substrate 430 and the dielectric layer 792 can be between about 60% and 95%. In some embodiments, the aspect ratio of the deep isolation structure can be in a range between about 10 and about 20. In some embodiments, the aspect ratio can be greater than about 20. In some embodiments, the angle α between the bottom surface and the sidewall surface of the deep isolation trench 894 can be in a range between about 90° and about 45°. In some embodiments, the deep isolation trench 894 can have sidewalls that are substantially perpendicular to its bottom surface.

[0102] In operation 312, an isolation material is disposed in the deep isolation trenches and a planarization process is performed according to some embodiments of the present disclosure. Referring to FIG. 9, a deep isolation structure 994 is formed in the deep isolation trenches 894 of the 3D memory device 900 by depositing an isolation material and performing a planarization process. The deep isolation structure 994 may be used to prevent possible crosstalk between adjacent devices (such as, for example, peripheral devices 450A and 450B) through the first substrate 430. The deep isolation structure 994 may also prevent the peripheral devices 450A and 450B from affecting any other surrounding devices. The deep isolation structure 994 may be in physical contact with the STI structure 452. The isolation material may be any suitable material that prevents crosstalk between adjacent devices. For example, the isolation material may be a low-k material (e.g., having a dielectric constant less than about 3.9). In some embodiments, the isolation material can be silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, fluoride doped silicate glass (FSG), any suitable dielectric material, and / or combinations thereof. In some embodiments, a liner layer can be disposed in the deep isolation trench 894 prior to the deposition of the isolation material. For example, the liner layer (not shown in FIG. 9 ) can be a catalyst layer that promotes adhesion of a subsequently deposited isolation material or a barrier layer that can prevent possible contamination of the first substrate due to the subsequent deposition of the isolation material. For example, the liner layer can be silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, titanium nitride, tantalum nitride, any suitable material, and / or combinations thereof. In some embodiments, the liner layer is positioned between the isolation material and the first substrate 430.

[0103] In some embodiments, the isolation material may be disposed by a blanket deposition process until the deep isolation trenches 894 are completely filled with the isolation material, followed by a planarization process that removes any excess isolation material disposed over the top surface of the dielectric layer 792. The planarization process can be a chemical mechanical polishing (CMP), a reactive ion etching (RIE) process, a wet etching process, a suitable process, and / or a combination thereof. The planarization process may be performed until the deep isolation structures 994 and the top surface of the dielectric layer 792 are substantially coplanar (e.g., horizontal). In some embodiments, the deep isolation structures 994 may be formed in any suitable location of the 3D memory device 900 where device isolation is required.

[0104] Various embodiments according to the present disclosure provide structures and fabrication methods for isolation structures that improve isolation between structures of a 3D memory structure. A peripheral device wafer containing CMOS devices can be bonded to an array wafer containing a 3D memory array. Isolation structures can be implemented in the bonded peripheral / memory array wafer to prevent crosstalk between adjacent structures (e.g., between wells of different doping types). Isolation structures can be formed by thinning the dielectric layer of the peripheral wafer and by forming through silicon isolation (TSI) structures to effectively separate different functional regions.

[0105] Thus, the foregoing description of specific embodiments will fully disclose the general nature of the present disclosure such that others may, by applying knowledge within the scope of those skilled in the art, readily modify and / or adapt such specific embodiments for various applications without departing from the general concept of the present disclosure and without undue experimentation. Such adaptations and modifications are therefore intended to be within the meaning and range of equivalents of the disclosed embodiments, based on the disclosure and guidance presented herein. It should be understood that the phraseology or terminology herein is for purposes of description and not limitation, and that the terminology or terminology herein is to be interpreted by those of skill in the art in light of the disclosure and guidance.

[0106] The embodiments of the present disclosure have been described above with the help of functional building blocks illustrating the implementation of certain functions and relationships thereof. The boundaries of these functional building blocks have been arbitrarily defined herein for the convenience of description. Alternative boundaries may be defined so long as the certain functions and relationships thereof are appropriately implemented.

[0107] The Summary and Abstract sections may describe one or more (but not all) exemplary embodiments of the disclosure contemplated by the inventors and are therefore not intended to be in any way limiting of the scope of the disclosure and the appended claims.

[0108] The breadth and scope of the present disclosure should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents. [Explanation of symbols]

[0109] 100 Three-dimensional (3D) memory devices 101 Memory Plane 103 Memory Blocks 105 Peripheral Area 108 areas 200 Memory Array Structure 210 Stairs area 211 Channel Structure Region 212 Memory String 214 Contact structure 216 Slit Structure 216-1 Slit structure 216-2 Slit structure 218 Memory Finger 220 Upper selective gate cut 300 Exemplary Methods 330 Substrate 331 Insulating film 332 Lower Select Gate (LSG) 333, 333-1, 333-2, 333-3 Control gate 334 Top Select Gate (TSG) 335 Film Stack 336 Channel Hole Section 337 Memory Film 338 Channel Layer 339 Core-filled film 340, 340-1, 340-2, 340-3 memory cells 341 Bit Line (BL) 343 Metal Interconnect Lines 344 Source Line Area 400 Peripheral circuits, CMOS wafer 430 First Substrate 430-1 First side 430-2 Second side 450A, 450B Peripheral Devices 451 First Well 452 Shallow Trench Isolation (STI) 454 well 455 Deepwell 456 Gate Stack 457 Third Well 458 Gate Spacer 460 Source / Drain 462 Peripheral Interconnect Layer 464 Contact structure 466, 466-2 Conductive Line 468 Insulating Layer 470 Metal Level 470-1 Bottom Metal Level, Conductive Level 470-2 Upper metal level, conductive level 471 Contact part 472 Board contact part 473 Deep well contact 500 Memory Array 530 Second Board 540 memory cells 562 Array Interconnect Layer 564 Contact structure 566 Conductive Line 568 Insulating Layer 572 Board contact part 574 Conductor Layer 576 First Dielectric Layer 578 Alternating Conductor / Dielectric Stacks 580 Epitaxial layer, epitaxial plug 582 Semiconductor Layer 584 bit line contact 586 Interconnect VIA 600 3D Memory Devices 688 bonding interface 690 Bonding Layer 700 3D Memory Device 701 area 792 Dielectric Layer 800 3D Memory Devices 894 Deep Isolation Trench 896 Trench 900 3D Memory Device 994 Deep Isolation Structure D Depth L Length T, t thickness W1 Upper width W2 bottom width α angle

Claims

1. 1. A method for forming a three dimensional memory device, comprising: forming a peripheral circuit on a first side of a first substrate, the peripheral circuit including first and second peripheral devices, a first interconnect layer, and a shallow trench isolation (STI) structure between the first peripheral device and the second peripheral device; forming a memory array on the second substrate, the memory array including a plurality of memory cells and a second interconnect layer; bonding the first and second interconnect layers; forming a deep isolation trench through the first substrate and exposing a portion of the STI structure, the deep isolation trench being formed through a second side of the first substrate opposite the first side; depositing an isolation material to form a deep isolation structure in the deep isolation trench; performing a planarization process to remove portions of the isolation material disposed on the second side of the first substrate; Including, The method further includes forming another STI structure adjacent to the first peripheral device, and forming another deep isolation trench through the first substrate to expose the another STI structure.

2. The method of claim 1 , further comprising the step of thinning the first substrate through the second side after bonding the first and second interconnect layers.

3. 2. The method of claim 1, wherein the first substrate includes a deep well, and thinning the first substrate includes exposing the deep well on the second side of the first substrate.

4. 10. The method of claim 1, further comprising disposing a liner layer in the deep isolation trench prior to disposing the isolation material.

5. The method of claim 1 , further comprising disposing a dielectric layer on the second side of the first substrate.

6. The method of claim 1 , wherein the step of coupling comprises direct bonding.

7. The method of claim 1 further comprising disposing the isolation material in the another deep isolation trench.

8. The method of claim 1 , wherein the step of depositing an isolation material comprises depositing a silicon oxide material.

9. 2. The method of claim 1, wherein bonding the first and second interconnect layers comprises a dielectric-to-dielectric bond and a metal-to-metal bond at a bonding interface.

10. 1. A method for forming a three dimensional memory device, comprising: forming a peripheral circuit on a first side of a first substrate, the peripheral circuit including a plurality of peripheral devices and a first interconnect layer; forming a plurality of shallow trench isolation (STI) structures in the first substrate, each STI structure of the plurality of STI structures being formed between adjacent peripheral devices of the plurality of peripheral devices; forming a memory array on the second substrate, the memory array including a plurality of memory cells and a second interconnect layer; coupling the first and second interconnect layers such that at least one peripheral device of the plurality of peripheral devices is electrically coupled to at least one memory cell of the plurality of memory cells; thinning the first substrate through a second side of the first substrate, the second side being opposite the first side; forming a plurality of deep isolation trenches through the first substrate to expose portions of STI structures of the plurality of STI structures, the plurality of deep isolation trenches being formed through the second side of the first substrate; disposing an isolation material in the plurality of deep isolation trenches; performing a planarization process to remove portions of the isolation material disposed on the second side of the first substrate; Including, The method further includes forming another STI structure adjacent to the first peripheral device, and forming another deep isolation trench through the first substrate to expose the another STI structure.

11. The method of claim 10 , wherein the step of coupling comprises direct bonding.

12. 11. The method of claim 10, further comprising disposing a dielectric layer on the second side of the first substrate, the plurality of deep isolation trenches extending through the dielectric layer.

13. The method of claim 10 , further comprising disposing a liner layer in the deep isolation trench prior to disposing the isolation material.

14. The method of claim 10 , wherein the step of disposing an isolation material comprises disposing a silicon oxide material.

15. A three-dimensional memory device, comprising: A peripheral circuit wafer; Memory array wafer and Including, The peripheral circuit wafer includes: A first substrate; a plurality of peripheral devices and a first interconnect layer formed on a first side of the first substrate; a plurality of shallow trench isolation (STI) structures in the first substrate, the plurality of shallow trench isolation (STI) structures being formed between adjacent ones of the plurality of peripheral devices; a dielectric layer formed on a second side of the first substrate opposite the first side; a plurality of deep isolation structures formed on a second side of the first substrate opposite the first side, the plurality of deep isolation structures being in physical contact with the at least one STI structure and extending into the dielectric layer; Including, The memory array wafer comprises: a plurality of memory cells, at least one peripheral device of the plurality of peripheral devices being electrically coupled to at least one memory cell of the plurality of memory cells; a second interconnect layer in physical contact with the first interconnect layer; A three-dimensional memory device comprising:

16. 16. The three dimensional memory device of claim 15, wherein the at least one deep isolation structure comprises a liner layer and an isolation material, the liner layer being between the isolation material and the first substrate.

17. The three-dimensional memory device of claim 15, wherein the physical contact between the first interconnect layer and the second interconnect layer includes a chemical bond formed between the first interconnect layer and the second interconnect layer.

18. 16. The three dimensional memory device of claim 15, wherein the at least one deep isolation structure comprises silicon oxide.

19. 16. The three dimensional memory device of claim 15, wherein the at least one deep isolation structure has a width of approximately 0.2 μm.

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