Semiconductor Structures and Memories

Abstract

A semiconductor structure and a memory are provided, the semiconductor structure including: a first active area, a first gate located above the first active area, the first active area and the first gate being used to form a first transistor, a second active area, the second active area and the first active area being arranged along a first direction, the second active area and the first active area being independent of each other, and a second gate located above the second active area, the second active area and the second gate being used to form a second transistor, where the sizes of the first transistor and the second transistor are the same, the deviation between the electrical parameters of the first transistor and the electrical parameters of the second transistor are within a predetermined threshold, and the first transistor and the second transistor belong to one cross-coupled amplification unit.

Description

[Technical field]

[0001] (CROSS-REFERENCE TO RELATED APPLICATIONS) This application claims priority to a Chinese patent application filed with the China Patent Office on June 27, 2022, bearing application number 202210744736.4 and entitled "Semiconductor Structure and Memory", the entire contents of which are incorporated herein by reference.

[0002] The present disclosure relates to the field of semiconductors, and more particularly to semiconductor structures and memories. [Background technology]

[0003] In memory, a sense amplifier (SA) is an important functional component, which can amplify and output data signals output by memory units, or amplify external signals and write them to memory units. A sense amplifier consists of a pair of P-type transistors (called PSA) and a pair of N-type transistors (called NSA). However, during the manufacturing process, there are some deviations or mismatch problems in the PSA, which will reduce the performance of the sense amplifier. Summary of the Invention [Problem to be solved by the invention]

[0004] The present disclosure provides a semiconductor structure and a memory that can improve the symmetry of transistors in a cross-coupled structure, improve noise caused by transistor mismatch, and improve signal amplification performance. [Means for solving the problem]

[0005] In a first aspect, embodiments of the present disclosure provide a semiconductor structure, the semiconductor structure comprising: A first active area; a first gate located above the first active area, the first active area and the first gate being used to form a first transistor; and a second active area, the second active area and the first active area being arranged along a first direction, and the second active area and the first active area being independent of each other; a second gate located above the second active area, the second active area and the second gate being used to form a second transistor; Here, a size of the first transistor is the same as a size of the second transistor, a deviation between an electrical parameter of the first transistor and an electrical parameter of the second transistor is within a predetermined threshold, and the first transistor and the second transistor belong to one cross-coupled amplification unit.

[0006] In some embodiments, the shape of the first gate is the same as the shape of the second gate, and in a first direction, an upper edge of the first gate is higher than an upper edge of the first active area, a lower edge of the first gate is lower than a lower edge of the first active area, an upper edge of the second gate is higher than an upper edge of the second active area, and a lower edge of the second gate is lower than a lower edge of the second active area.

[0007] In some embodiments, in a first direction, a height difference between an upper edge of the first active area and an upper edge of the first gate is a first value, a height difference between an upper edge of the second active area and an upper edge of the second gate is a second value, where the first value and the second value are the same, a height difference between a lower edge of the first active area and a lower edge of the first gate is a third value, and a height difference between a lower edge of the second active area and a lower edge of the second gate is a fourth value, where the third value and the fourth value are the same.

[0008] In some embodiments, the semiconductor device further includes a first contact region located on the first active area, a second contact region located on the first active area, where the first contact region, the first gate, and the second contact region are sequentially arranged along a second direction, and a third contact region located on the second active area, and a fourth contact region located on the second active area, where the third contact region, the second gate, and the fourth contact region are sequentially arranged along the second direction.

[0009] In some embodiments, in the second direction, the distance between the first contact area and the first gate is a fifth value, the distance between the third contact area and the second gate is a sixth value, and the fifth value and the sixth value are the same, the distance between the second contact area and the first gate is a seventh value, the distance between the fourth contact area and the second gate is an eighth value, and the seventh value and the eighth value are the same.

[0010] In some embodiments, in a first direction, an upper edge of the second contact area is flush with an upper edge of the first contact area and a lower edge of the second contact area is lower than a lower edge of the first contact area, a lower edge of the fourth contact area is flush with a lower edge of the third contact area and an upper edge of the fourth contact area is higher than an upper edge of the third contact area.

[0011] In some embodiments, in the first direction, an upper edge of the second contact area is higher than an upper edge of the first contact area and a lower edge of the second contact area is lower than a lower edge of the first contact area, an upper edge of the fourth contact area is higher than an upper edge of the third contact area and a lower edge of the fourth contact area is lower than a lower edge of the third contact area.

[0012] In some embodiments, in a first direction, the distance between an upper edge of the first contact area and an upper edge of the second contact area is a ninth value, the distance between an upper edge of the third contact area and an upper edge of the fourth contact area is a tenth value, where the ninth value and the tenth value are the same, the distance between a lower edge of the first contact area and a lower edge of the second contact area is an eleventh value, and the distance between a lower edge of the third contact area and a lower edge of the fourth contact area is a twelfth value, where the eleventh value and the twelfth value are the same.

[0013] In some embodiments, the ninth value, the tenth value, the eleventh value, and the twelfth value are all the same.

[0014] In some embodiments, the semiconductor structure further includes a third gate located above the first active area and disposed on one side of the second contact region away from the first gate, the first active area and the third gate being used to form a third transistor, and a fourth gate located above the second active area and disposed on one side of the fourth contact region away from the second gate, the second active area and the fourth gate being used to form a fourth transistor, where the third transistor and the fourth transistor belong to another cross-coupled amplification unit.

[0015] In some embodiments, the semiconductor structure further includes a fifth contact region located on the first active region, the fifth contact region being disposed on one side of the third gate away from the second contact region, and a sixth contact region located on the second active region, the sixth contact region being disposed on one side of the fourth gate away from the fourth contact region.

[0016] In some embodiments, the shape of the first contact region is the same as the shape of the fifth contact region, the shape of the third contact region is the same as the shape of the sixth contact region, in a first direction, a center point of the first contact region is at the same position as a center point of the fifth contact region, a center point of the third contact region is at the same position as a center point of the sixth contact region, the first gate and the third gate are centrosymmetric with respect to the second contact region, and the second gate and the fourth gate are 4th contact area It is centrosymmetric with respect to .

[0017] In some embodiments, the first active area, the second active area, the first gate to the fourth gate, and the first contact area to the sixth contact area together constitute one repeating unit, and a plurality of repeating units are arranged along the second direction, and a distance between the first gate and the third gate in the same repeating unit is a 13th value, a distance between the first gate and the third gate in an adjacent repeating unit is a 14th value, a distance between the second gate and the fourth gate in the same repeating unit is a 15th value, and a distance between the second gate and the fourth gate in an adjacent repeating unit is a 16th value, where the 13th value, the 14th value, the 15th value, and the 16th value are all the same.

[0018] In some embodiments, a seventh contact region is disposed on the first gate, an eighth contact region is disposed on the second gate, a ninth contact region is disposed on the third gate, and a tenth contact region is disposed on the fourth gate, where the seventh contact region and the tenth contact region are centrosymmetric, and the eighth contact region and the ninth contact region are centrosymmetric.

[0019] In a second aspect, an embodiment of the present disclosure provides a memory including a semiconductor structure according to the first aspect.

[0020] An embodiment of the present disclosure provides a semiconductor structure and a memory, the semiconductor structure including: a first active area; a first gate located above the first active area, the first active area and the first gate being used to form a first transistor; a second active area, the second active area and the first active area are arranged along a first direction, and the second active area and the first active area are independent of each other; and a second gate located above the second active area, the second active area and the second gate being used to form a second transistor, where a size of the first transistor is the same as that of a second transistor, a deviation between an electrical parameter of the first transistor and an electrical parameter of the second transistor is within a predetermined threshold, and the first transistor and the second transistor belong to one cross-coupled amplification unit. In this way, since the first active area and the second active area are independent of each other, the overlapping areas and shapes of the gates and active areas of the first transistor and the second transistor are more similar, which improves the symmetry of the first transistor and the second transistor and reduces the deviation of the electrical parameters between them, thereby improving the signal amplification ability of the cross-coupled amplification unit, and ultimately improving the performance of the sense amplifier in the memory. [Brief description of the drawings]

[0021] [Figure 1] FIG. 2 is a schematic diagram showing a structure of a sense amplifier. [Diagram 2] FIG. 2 is a schematic diagram showing a detailed structure of a sense amplifier. [Diagram 3] FIG. 1 is a schematic diagram showing the process structure of PSA. [Figure 4] 1 is a schematic diagram illustrating a semiconductor structure provided by an embodiment of the present disclosure. [Diagram 5] FIG. 2 is a schematic diagram illustrating a layout of a semiconductor structure provided by an embodiment of the present disclosure. [Figure 6]FIG. 2 is a schematic diagram illustrating another semiconductor structure provided by an embodiment of the present disclosure. [Figure 7] 1 is a schematic diagram illustrating another semiconductor structure provided by an embodiment of the present disclosure. [Figure 8] FIG. 2 is a schematic diagram illustrating yet another semiconductor structure provided by an embodiment of the present disclosure. [Figure 9] FIG. 2 is a schematic diagram illustrating yet another semiconductor structure provided by an embodiment of the present disclosure. [Figure 10] FIG. 2 is a schematic diagram illustrating yet another semiconductor structure provided by an embodiment of the present disclosure. [Figure 11] 1 illustrates the performance of a semiconductor structure provided by an embodiment of the present disclosure. [Figure 12] FIG. 2 is a schematic diagram illustrating a structure of a memory provided by an embodiment of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0022] The technical solutions of the embodiments of the present disclosure will be described below clearly and completely with reference to the drawings of the embodiments of the present disclosure. It should be understood that the specific embodiments described in the specification are only used to describe the present application, and do not limit the present application. It should also be noted that, for ease of description, only the parts related to the related application are shown in the drawings.

[0023] Unless otherwise specified, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art of this disclosure. The terms used herein are only used to describe the embodiments of this disclosure and are not intended to limit the disclosure.

[0024] In the following description, "some embodiments" refers to a subset of all possible embodiments, but it will be understood that "some embodiments" may be the same or different subsets of all possible embodiments and may be combined with each other without conflict.

[0025] It should be noted that the terms "first / second / third" and the like used herein are not intended to limit a particular order but are intended to distinguish between similar objects. It should be understood that "first / second / third" can be used to interchange a particular order or order when appropriate, so that the embodiments of the present invention described herein can be performed in an order other than that shown or described herein.

[0026] The following English abbreviations are relevant to this disclosure: MOS (Metal-Oxide-Semiconductor Field-Effect Transistor): Metal-oxide-semiconductor field-effect transistor. PMOS: P-type MOS transistor, a semiconductor that mainly conducts holes, also known as a P-type transistor. NMOS: N-type MOS transistor, a semiconductor that mainly conducts electrons, also known as an N-type transistor. BL(Bit Line):Bit line. WL (Word Line): Word line.

[0027] In integrated circuits, MOS transistors are still the most commonly used unit components. For a sense amplifier (SA) in a memory, a cross-coupled amplification unit composed of an NMOS pair and a PMOS pair is the core. Referring to FIG. 1, a schematic diagram of the structure of a sense amplifier is shown. As shown in FIG. 1, a sense amplifier (sense amplifier circuit) reads data signals from a memory unit to local data lines (represented by / LIO and LIO) or writes data signals from local data lines to a memory unit by disposing a sense amplifier between a bit line pair (represented by / BL and BL) and amplifying a small signal representing data "0" or data "1" via a first reference signal SAP and a second reference signal SAN. Referring to FIG. 2, a schematic diagram of the detailed structure of a sense amplifier is shown. As shown in FIG. 1 or FIG. 2, the PMOS pair of the cross-coupled amplifier unit composed of transistor P1 and transistor P2 is also called PSA, and the NMOS pair of the cross-coupled amplifier unit composed of transistor N1 and transistor N2 is also called NSA, and the amplification effect of the cross-coupled amplifier unit is greatly affected by the difference between the two components in the pair. In addition, the other components in FIG. 1 realize the pre-charge function or are used as transfer switches. In FIG. 2, transistor M1 and transistor M2 are used to reduce the noise caused by the mismatch of NSA, transistor M3 and transistor M4 are used for isolation, and transistor M6 is used for pre-charge processing. The principle of the circuits in FIG. 1 and FIG. 2 may be inferred by combining components, and the contents of this part do not affect the implementation of the embodiments of the present disclosure, and will not be repeated here.

[0028] As shown in Figure 2, the sense amplifier (sense amplifier circuit) has dedicated transistors M1 and M2 for solving the mismatch problem of the NSA, but no dedicated functional components for solving the mismatch problem of the PSA. Therefore, improving the symmetry of the PSA to improve the mismatch problem has significant significance for the performance of the sense amplifier.

[0029] Referring to Fig. 3, a schematic diagram of the process structure of PSA is shown. As shown in Fig. 3, in PSA, the active areas of transistor P1 and transistor P2 are connected, and at this time, the overlapping areas between the gates and active areas of transistor P1 and transistor P2 are significantly different, specifically refer to position (1) and position (2) and position (3) and position (4) in Fig. 3, so that the transistor pairs in this PSA have significant differences in electrical characteristics, which reduces the amplification performance of the sense amplifier and further affects the performance of the memory.

[0030] An embodiment of the present disclosure provides a semiconductor structure, the semiconductor structure including: a first active area; a first gate located above the first active area, the first active area and the first gate being used to form a first transistor; a second active area, the second active area and the first active area are arranged along a first direction, and the second active area and the first active area are independent of each other; and a second gate located above the second active area, the second active area and the second gate being used to form a second transistor, where a size of the first transistor is the same as that of the second transistor, a deviation between an electrical parameter of the first transistor and an electrical parameter of the second transistor is within a predetermined threshold, and the first transistor and the second transistor belong to one cross-coupled amplification unit. In this way, since the first active area and the second active area are independent of each other, the overlapping areas and shapes between the gates and the active areas of the first transistor and the second transistor are more similar, which improves the symmetry of the first transistor and the second transistor and reduces the deviation of the electrical parameters between them, thereby improving the signal amplification ability of the cross-coupled amplification unit, and ultimately improving the performance of the sense amplifier in the memory.

[0031] Each embodiment of the present disclosure will be described in detail below with reference to the drawings.

[0032] In one embodiment of the present disclosure, referring to Figure 4, there is shown a schematic diagram of a semiconductor structure 10 provided according to an embodiment of the present disclosure. As shown in Figure 4, the semiconductor structure 10 includes: A first active area 11; a first gate 12 located above a first active region 11, the first active region 11 and the first gate 12 being used to form a first transistor; a second active area 13, the second active area 13 and the first active area 11 being arranged along a first direction, the second active area 13 and the first active area 11 being independent of each other; a second gate 14 located above the second active area 13, the second active area 13 and the second gate 14 being used to form a second transistor; Here, the size of the first transistor is the same as that of the second transistor, the deviation between the electrical parameters of the first transistor and the electrical parameters of the second transistor is within a predetermined threshold, and the first transistor and the second transistor belong to one cross-coupled amplification unit.

[0033] It should be noted that the semiconductor structure 10 provided by the embodiment of the present disclosure can be used to form a circuit of a sense amplifier, and the first transistor and the second transistor are all PMOS, that is, the first transistor and the second transistor can be PSA in a cross-coupled amplification unit.

[0034] In addition, the first transistor and the second transistor may be an NSA in a cross-coupled amplifier unit, or may be applied to other similar circuit structures. The following description will be given by taking only the PSA as an example of the embodiment of the present disclosure, but is not limited thereto.

[0035] In this way, as shown in FIG. 4, since the first active area and the second active area are independent of each other, the overlapping areas and shapes of the gates and active areas of the first transistor and the second transistor are more similar, thereby improving the symmetry of the first transistor and the second transistor, and making the deviation of the electrical parameters between them smaller, which can improve the signal amplification ability of the cross-coupled amplification unit, and finally improve the performance of the sense amplifier in the memory.

[0036] Correspondingly, referring to Figure 5, a schematic diagram of the layout of a semiconductor structure provided by an embodiment of the present disclosure is shown. As shown in Figure 5, the shape of the polysilicon gate PG of the first transistor (i.e., the first gate 12) and the shape of the polysilicon gate PG of the second transistor (i.e., the second gate 14) are the same, where the metal layer M0 realizes the electrical connection of the contact area, and the active area ACTIVE of the first transistor (i.e., the first active area 11) and the active area ACTIVE of the second transistor (i.e., the second active area 13) are mutually independent, which can improve the symmetry between the first transistor and the second transistor, and finally improve the performance of the memory.

[0037] 4 or 5, in some embodiments, the shape of the first gate 12 is the same as the shape of the second gate 14, the shape of the first active area 11 is the same as the shape of the second active area 13, and in a first direction, an upper edge of the first gate 12 is higher than an upper edge of the first active area 11, a lower edge of the first gate 12 is lower than a lower edge of the first active area 11, an upper edge of the second gate 14 is higher than an upper edge of the second active area 13, and a lower edge of the second gate 14 is lower than a lower edge of the second active area 13. Furthermore, in a second direction, an outer edge of the first active area 11 is located outside an outer edge of the first gate 12, and an outer edge of the second active area 13 is located outside an outer edge of the second gate 14.

[0038] In some embodiments, as shown in FIG. 6 , in a first direction, the height difference between the upper edge of the first active area 11 and the upper edge of the first gate 12 (see circled number "1" in FIG. 6 ) is a first value, the height difference between the upper edge of the second active area 13 and the upper edge of the second gate 14 (see circled number "2" in FIG. 6 ) is a second value, where the first value and the second value are the same, the height difference between the lower edge of the first active area 11 and the lower edge of the first gate 12 (see circled number "3" in FIG. 6 ) is a third value, and the height difference between the lower edge of the second active area 13 and the lower edge of the second gate 14 (see circled number "4" in FIG. 6 ) is a fourth value, where the third value and the fourth value are the same.

[0039] In this way, by controlling the height difference between the outer edge of the gate and the outer edge of the active area, the "overlap area between the active area and the gate" in the first transistor and the second transistor can be further controlled to be the same, improving the symmetry of the PSA, improving noise due to PSA mismatch, and ultimately improving memory performance.

[0040] In some embodiments, as shown in FIG. 6, a semiconductor structure 10 includes: a first contact area 15 located in the first active area 11; a second contact region 16 located in the first active region 11, the first contact region 15, the first gate 12, and the second contact region 16 being arranged in this order along a second direction; a third contact area 17 located in the second active area 13; The semiconductor device further includes a fourth contact region 18 located in the second active region 13, the fourth contact region 18 being arranged along the second direction in the order of the third contact region 17, the second gate 14, and the fourth contact region 18.

[0041] The contact regions are used later to form contact plugs to apply voltage to the transistors or draw current from the transistors.

[0042] In some embodiments, the shape of the first contact region 15 is the same as the shape of the third contact region 17, and the shape of the second contact region 16 is the same as the shape of the fourth contact region 18. Furthermore, in the second direction, the distance between the first contact region 15 and the first gate 12 is a fifth value, the distance between the third contact region 17 and the second gate 14 is a sixth value, and the fifth and sixth values ​​are the same, the distance between the second contact region 16 and the first gate 12 is a seventh value, and the distance between the fourth contact region 18 and the second gate 14 is an eighth value, and the seventh and eighth values ​​are the same.

[0043] 6, in the first direction, the upper edge of the first contact region 15 is flush with the upper edge of the second contact region 16, and since the length of the second contact region 16 is longer, the lower edge of the second contact region 16 is lower than the lower edge of the first contact region 15. The lower edge of the third contact region 17 is flush with the lower edge of the fourth contact region 18, and since the length of the fourth contact region 18 is longer, the upper edge of the fourth contact region 18 is higher than the upper edge of the third contact region 17. In such a structure, the current from source to drain in the transistor is specifically shown by the black dashed line in FIG. 6, and at this time, the two components are still asymmetric.

[0044] Therefore, the second contact region can be moved upward and the fourth contact region can be moved downward to further improve the performance of the semiconductor structure 10. Based on this idea, and referring to FIG. 7 based on FIG. 6, a schematic diagram of yet another semiconductor structure 10 provided by an embodiment of the present disclosure is shown. As shown in FIG. 7, for the semiconductor structure 10, in the first direction, the upper edge of the second contact region 16 is higher than the upper edge of the first contact region 15 and the lower edge of the second contact region 16 is lower than the lower edge of the first contact region 15, the upper edge of the fourth contact region 18 is higher than the upper edge of the third contact region 17 and the lower edge of the fourth contact region 18 is lower than the lower edge of the third contact region 17.

[0045] As shown in FIG. 7, in the first direction, the distance between the upper edge of the first contact area 15 and the upper edge of the second contact area 16 (see the circled number "9" in FIG. 7) is a ninth value, the distance between the upper edge of the third contact area 17 and the upper edge of the fourth contact area 18 (see the circled number "10" in FIG. 7) is a tenth value, where the ninth value and the tenth value are the same, the distance between the lower edge of the first contact area 15 and the lower edge of the second contact area 16 (see the circled number "11" in FIG. 7) is an eleventh value, and the distance between the lower edge of the third contact area 17 and the lower edge of the fourth contact area 18 is a twelfth value (see the circled number "12" in FIG. 7), where the eleventh value and the twelfth value are the same.

[0046] In addition, the specific values ​​of the first to twelfth values ​​can be determined according to the actual application scenario, under the condition that the above-mentioned restrictions are satisfied. In this way, the relative positions of the source and the drain are the same in the first and second transistors, thereby further improving the mismatch between the first and second transistors, and making the deviation between the electrical parameters of the first and second transistors smaller. That is, on the premise that the original wiring scheme is not changed, the semiconductor structure provided by the embodiment of the present disclosure can make the contact area in the PSA symmetrical, which not only saves unnecessary costs, but also effectively improves the mismatch of the PSA.

[0047] Furthermore, the ninth value, the tenth value, the eleventh value, and the twelfth value can all be set to be the same, thereby better ensuring the symmetry of the current paths between the first transistor and the second transistor.

[0048] It should be understood that there are a large number of memory units in the memory, which need to be controlled by different bit lines and word lines, whereas there are multiple cross-coupled amplifier units in the memory, which can perform signal amplification for different bit lines.

[0049] In some embodiments, as shown in FIG. 6 or FIG. 7, the semiconductor structure 10 includes: a third gate 21 located above the first active region 11, the third gate 21 being disposed on one side of the second contact region 16 away from the first gate 12, the first active region 11 and the third gate 21 being used to form a third transistor; and a fourth gate 22 located above the second active region 13, the fourth gate 22 being disposed on one side of the fourth contact region 18 away from the second gate 14, the second active region 13 and the fourth gate 22 being used to form a fourth transistor.

[0050] In addition, the third transistor and the fourth transistor belong to another cross-coupled amplifier unit, i.e., the third transistor and the fourth transistor are PSA in another cross-coupled amplifier unit, where the two cross-coupled amplifier units share an active area, thereby saving process costs.

[0051] Similarly, contact regions are present for the third and fourth transistors. In some embodiments, the semiconductor structure 10 may include, as shown in FIG.

[0052] a fifth contact region 23 located in the first active region 11, the fifth contact region 23 being disposed on one side of the third gate 21 away from the second contact region 16; The sixth contact region 24 further includes a sixth contact region 24 located in the second active region 13, the sixth contact region 24 being disposed on one side of the fourth gate 22 away from the fourth contact region 18.

[0053] Additionally, the third transistor and the first transistor share a second contact region 16 , and the fourth transistor and the second transistor share a fourth contact region 18 .

[0054] The shape of the fifth contact region 23 is the same as the shape of the first contact region 15, and the shape of the sixth contact region 24 is the same as the shape of the second contact region 16. In the first direction, the center point of the first contact region 15 is at the same position as the center point of the fifth contact region 23, and the center point of the third contact region 17 is at the same position as the center point of the sixth contact region 24. The first gate 12 and the third gate 21 are centrosymmetric with respect to the second contact region 16, and the second gate 14 and the fourth gate 22 are 4th contact area It is centrosymmetric with respect to 18.

[0055] 8, in some embodiments, the first gate 12 is disposed with a seventh contact region, the second gate 14 is disposed with an eighth contact region, the third gate 21 is disposed with a ninth contact region, and the fourth gate 22 is disposed with a tenth contact region, where the seventh contact region and the tenth contact region are centrosymmetric, and the eighth contact region and the ninth contact region are centrosymmetric, so that the layout of the metal layer M0 is more convenient.

[0056] It should be understood that the contact area of ​​each gate actually comprises two portions, and the seventh contact area of ​​the first gate 12 comprises the two portions enclosed by the dashed line in FIG.

[0057] In some embodiments, the first active area 11, the second active area 13, the first gate 12 to the fourth gate 22, and the first contact area 15 to the sixth contact area 24 together constitute one repeating unit, and the multiple repeating units are arranged along the second direction, and the distance between the first gate 12 and the third gate 21 in the same repeating unit is a value of 13, the distance between the first gate 12 and the third gate 21 in an adjacent repeating unit is a value of 14, the distance between the second gate 14 and the fourth gate 22 in the same repeating unit is a value of 15, and the distance between the second gate 14 and the fourth gate 22 in an adjacent repeating unit is a value of 16.

[0058] In an embodiment of the present disclosure, the shapes of each of the first gate 12, the second gate 14, the third gate 21, and the fourth gate 22 can be trimmed by OPC (Optical Proximity Correction), thereby ensuring that the 13th value, the 14th value, the 15th value, and the 16th value are all the same.

[0059] Illustratively, the thirteenth value, the fourteenth value, the fifteenth value, and the sixteenth value are all 60 nm.

[0060] In one specific example, as shown in Figures 6 to 9, the first gate 12 and the second gate 14 are all L-shaped, the third gate 21 and the fourth gate 22 are inverted L-shaped, the first gate 12 forms the leg of the L shape by extending away from the third gate 21, the third gate 21 forms the leg of the inverted L shape by extending away from the first gate 12, the second gate 14 forms the leg of the L shape by extending away from the fourth gate 22, and the fourth gate 22 forms the leg of the inverted L shape by extending away from the second gate 14.

[0061] As shown in FIG. 9, the heads of the first gate 12, the second gate 14, the third gate 21, and the fourth gate 22 are trimmed larger and more rounded by OPC, and the distance between the first gate 12 and the third gate 21 in the same repeating unit (see circled number "13" in FIG. 9), the distance between the head of the first gate 12 and the foot of the third gate 21 in an adjacent repeating unit (see circled number "14" in FIG. 9), and the distance between the foot of the first gate 12 in the adjacent repeating unit (see circled number "15" in FIG. 9) are reduced. The distance between the head of the second gate 14 and the foot of the fourth gate 22 in the same repeating unit (see circled number "16" in Figure 9), the distance between the head of the second gate 14 and the foot of the fourth gate 22 in an adjacent repeating unit (see circled number "17" in Figure 9), and the distance between the foot of the second gate 14 and the head of the fourth gate 22 in an adjacent repeating unit (see circled number "18" in Figure 9) are all the same.

[0062] In summary, based on separating the active areas of the two PSAs, by adjusting the positions of the contact areas and trimming the shapes of the gates, the symmetry of the two PSAs can be further ensured. Referring to FIG. 10, a schematic diagram of another semiconductor structure provided by an embodiment of the present disclosure is shown. As shown in FIG. 10, by moving the position of the second contact area downward and moving the position of the fourth contact area (not shown in FIG. 10 but can be understood in conjunction with the above description) upward, the symmetry of the contact areas can be improved and the current of the first transistor and the current of the second transistor can be the same. In addition, the distances between the different gates are 63.154 nm, 66.242 nm, and 59.969 nm, respectively, so that the heads of the gates can be trimmed to be rounder and larger by OPC, ensuring that the distances between the different gates are all 60 nm, further improving the symmetry of the PSA, improving the mismatch problem of the PSA, and ensuring that the electrical parameters of the different cross-coupled amplification units are the same.

[0063] Based on FIG. 10, taking the sense amplifier as the test object, referring to FIG. 11, a schematic diagram of the function of the semiconductor structure provided by the embodiment of the present disclosure is shown. FIG. 11(a) shows the mismatch located at the center of the chip of the cross-coupled amplification structure, and FIG. 11(b) shows the mismatch located at the edge of the chip of the cross-coupled amplification structure. In FIG. 11, the control group means that the cross-coupled amplification structure adopts the semiconductor structure as shown in FIG. 3, the experimental group means that the cross-coupled amplification structure adopts the semiconductor structure as shown in FIG. 10, the vertical axis (Y axis) means the offset between the first transistor and the second transistor, and the horizontal axis (X axis) means the statistical coordinate. On the one hand, as can be seen from FIG. 11, the experimental group passes through the origin, so the mismatch of the experimental group is smaller. On the other hand, after the statistics of FIG. 11, it can be obtained that the variance of the offset of the experimental group is 16.4, and the offset is smaller than 1, and the variance of the offset of the control group is 16.5, and the offset is about 4, that is, the offset of the experimental group is smaller. That is, compared to the conventional gate, the gate adjusted by OPC has better symmetry and uniformity because the offset of the experimental group is smaller and closer to the origin compared to the control group.

[0064] In summary, the embodiment of the present disclosure optimizes the PSA structure to improve the mismatch problem of the PSA and improve the amplification performance of the sense amplifier structure in the memory. First, the embodiment of the present disclosure separates two active regions in the PSA to control the overlapping region between the gate (PG) and the active region (ACTIVE) to be the same in different transistors, as shown in FIGS. 4 to 9. Based on the above, since the position of the contact region still has an adverse effect on the symmetry of the two parts in the PSA, the embodiment of the present disclosure further adjusts the position of the contact region to make the relative positions of the source and drain of each transistor the same, so that the two parts are more symmetrical, as shown in FIGS. 7 and 9. Based on the above, the embodiment of the present disclosure largely trims the foot of the gate by OPC to control the distance between the gates to be 60 nm in total, further improving the symmetry of the PSA, as shown in FIGS. 9 and 10. That is, the embodiments of the present disclosure improve the mismatch of the PSA by changing the position of the active area and the position of the contact area in the PSA, which means that the electrical parameters of the two components in the PSA become more symmetrical.

[0065] An embodiment of the present disclosure provides a semiconductor structure, the semiconductor structure including: a first active region; a first gate located above the first active region, where the first active region and the first gate are used to form a first transistor; a second active region, where the second active region and the first active region are arranged along a first direction, and the second active region and the first active region are independent of each other; and a second gate located above the second active region, where the second active region and the second gate are used to form a second transistor, where a size of the first transistor is the same as a size of the second transistor, a deviation between an electrical parameter of the first transistor and an electrical parameter of the second transistor is within a predetermined threshold, and the first transistor and the second transistor belong to one cross-coupled amplification unit. In this way, since the first active area and the second active area are independent of each other, the overlapping areas and shapes of the gates and active areas of the first and second transistors are more similar, which improves the symmetry of the first and second transistors and reduces the deviation of the electrical parameters between them, thereby improving the signal amplification capability of the cross-coupled amplification unit, and ultimately improving the performance of the sense amplifier in the memory.

[0066] In another embodiment of the present disclosure, referring to Fig. 12, there is shown a schematic diagram of a structure of a memory 30 provided by an embodiment of the present disclosure. As shown in Fig. 12, the memory 30 includes the semiconductor structure 10.

[0067] For the memory 30, the memory 30 includes a semiconductor structure 10, in which a first active area and a second active area are independent of each other, so that for the first transistor and the second transistor, the overlapping areas and shapes between the gates and the active areas are more similar, thereby improving the symmetry between the first transistor and the second transistor, and the deviation value of the electrical parameters between the first transistor and the second transistor is smaller, which can improve the signal amplification ability of the cross-coupled amplification unit, and ultimately improve the performance of the sense amplifier in the memory.

[0068] The above description is merely a preferred embodiment of the present disclosure and is not intended to limit the scope of protection of the present disclosure. In this specification, the terms "comprise", "include", or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article, or apparatus that includes a set of elements includes not only those elements, but also other elements not expressly listed, or the inherent elements of such a process, method, article, or apparatus. Unless otherwise limited, an element defined in the sentence "includes ..." does not exclude that the process, method, article, or apparatus that includes the element has other identical elements. The numbers of the above examples of the present disclosure do not represent the superiority or inferiority of the examples, but are for convenience of explanation. The methods disclosed in the examples of some methods provided in the examples of the present disclosure can be arbitrarily combined without conflict to obtain a new example of the method. The above content is merely a specific embodiment of the present disclosure, and the scope of protection of the examples of the present disclosure is not limited thereto, and all modifications or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this disclosure should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure is the scope of the claims. [Industrial Applicability]

[0069] In the embodiment of the present disclosure, since the first active area and the second active area are independent of each other, the overlapping areas and shapes of the gates and active areas of the first transistor and the second transistor are more similar, which improves the symmetry of the first transistor and the second transistor and reduces the deviation of the electrical parameters between them, thereby improving the signal amplification ability of the cross-coupled amplification unit, and ultimately improving the performance of the sense amplifier in the memory.

Claims

1. 1. A semiconductor structure comprising: A first active area; a first gate located above the first active area, the first active area and the first gate being used to form a first transistor; and a second active area, the second active area and the first active area being arranged along a first direction, the second active area and the first active area being independent of each other; a second gate located above the second active area, the second active area and the second gate being used to form a second transistor; wherein the first gate and the second gate are both L-shaped, i.e., a shape of an overlapping region between the first active region and the first gate is the same as a shape of an overlapping region between the second active region and the second gate, the shape of the overlapping region is approximately L-shaped, a size of the first transistor is the same as a size of the second transistor, a deviation between an electrical parameter of the first transistor and an electrical parameter of the second transistor is within a predetermined threshold, and the first transistor and the second transistor belong to one cross-coupled amplification unit.

2. the shape of the first gate is the same as the shape of the second gate; In a first direction, an upper edge of the first gate is higher than an upper edge of the first active area, a lower edge of the first gate is lower than a lower edge of the first active area, an upper edge of the second gate is higher than an upper edge of the second active area, and a lower edge of the second gate is lower than a lower edge of the second active area. The semiconductor structure of claim 1 .

3. In a first direction, a height difference between an upper edge of the first active area and an upper edge of the first gate is a first value, and a height difference between an upper edge of the second active area and an upper edge of the second gate is a second value, where the first value and the second value are equal; a height difference between a lower edge of the first active area and a lower edge of the first gate is a third value, and a height difference between a lower edge of the second active area and a lower edge of the second gate is a fourth value, where the third value and the fourth value are equal. The semiconductor structure of claim 2 .

4. The semiconductor structure comprises: a first contact area located on the first active area; a second contact region located on the first active region, the first contact region, the first gate, and the second contact region being sequentially arranged along a second direction; a third contact area located on the second active area; a fourth contact region located in the second active region, the third contact region, the second gate, and the fourth contact region being sequentially arranged along a second direction. The semiconductor structure of claim 1 .

5. In a second direction, the distance between the first contact area and the first gate is a fifth value, the distance between the third contact area and the second gate is a sixth value, and the fifth value and the sixth value are equal, the distance between the second contact area and the first gate is a seventh value, the distance between the fourth contact area and the second gate is an eighth value, and the seventh value and the eighth value are equal, The semiconductor structure of claim 4.

6. In a first direction, an upper edge of the second contact area is flush with an upper edge of the first contact area, and a lower edge of the second contact area is lower than a lower edge of the first contact area, a lower edge of the fourth contact area is flush with a lower edge of the third contact area, and an upper edge of the fourth contact area is higher than an upper edge of the third contact area. The semiconductor structure of claim 4.

7. In a first direction, an upper edge of the second contact area is higher than an upper edge of the first contact area and a lower edge of the second contact area is lower than a lower edge of the first contact area, an upper edge of the fourth contact area is higher than an upper edge of the third contact area and a lower edge of the fourth contact area is lower than a lower edge of the third contact area. The semiconductor structure of claim 4.

8. In a first direction, a distance between an upper edge of the first contact area and an upper edge of the second contact area is a ninth value, and a distance between an upper edge of the third contact area and an upper edge of the fourth contact area is a tenth value, where the ninth value and the tenth value are equal; a distance between a lower edge of the first contact area and a lower edge of the second contact area is an eleventh value, and a distance between a lower edge of the third contact area and a lower edge of the fourth contact area is a twelfth value, where the eleventh value and the twelfth value are the same; 8. The semiconductor structure of claim 7.

9. The ninth value, the tenth value, the eleventh value, and the twelfth value are all the same; 9. The semiconductor structure of claim 8.

10. The semiconductor structure comprises: a third gate located above the first active area, the third gate being disposed on one side of the second contact region away from the first gate, the first active area and the third gate being used to form a third transistor; and a fourth gate located above the second active area, the fourth gate being disposed on one side of the fourth contact region away from the second gate, the second active area and the fourth gate being used to form a fourth transistor; Here, the third transistor and the fourth transistor belong to different cross-coupled amplification units. The semiconductor structure of claim 4.

11. The semiconductor structure comprises: a fifth contact region located on the first active region, the fifth contact region being disposed on one side of the third gate away from the second contact region; a sixth contact region located on the second active region, the sixth contact region being disposed on one side of the fourth gate away from the fourth contact region.

11. The semiconductor structure of claim 10.

12. the first contact area has a shape identical to the fifth contact area, the third contact area has a shape identical to the sixth contact area, In a first direction, a center point of the first contact area is at the same position as a center point of the fifth contact area, and a center point of the third contact area is at the same position as a center point of the sixth contact area; the first gate and the third gate are centrosymmetric with respect to the second contact region, and the second gate and the fourth gate are centrosymmetric with respect to the fourth contact region.

12. The semiconductor structure of claim 11.

13. the first active region, the second active region, the first gate to the fourth gate, and the first contact region to the sixth contact region together constitute one repeat unit, and a plurality of repeat units are arranged along a second direction; a distance between the first gate and the third gate in the same repeating unit is a value of 13, and a distance between the first gate and the third gate in an adjacent repeating unit is a value of 14; a distance between the second gate and the fourth gate in the same repeating unit is a value of 15, and a distance between the second gate and the fourth gate in an adjacent repeating unit is a value of 16; Here, the thirteenth value, the fourteenth value, the fifteenth value, and the sixteenth value are all the same.

13. The semiconductor structure of claim 12.

14. a seventh contact region disposed on the first gate, an eighth contact region disposed on the second gate, a ninth contact region disposed on the third gate, and a tenth contact region disposed on the fourth gate, wherein: the seventh contact region and the tenth contact region are centrosymmetric, and the eighth contact region and the ninth contact region are centrosymmetric; 13. The semiconductor structure of claim 12.

15. A memory, A memory comprising a semiconductor structure according to claim 1 .

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