Semiconductor Device

Abstract

To improve a numerical aperture of a semiconductor device.SOLUTION: On the same substrate, a drive circuit having a first thin-film transistor and a pixel having a second thin-film transistor are formed. The first thin-film transistor has: a first gate electrode layer; a gate insulating layer; a first oxide semiconductor layer; a first oxide conductive layer and a second oxide conductive layer; an oxide insulating layer in contact with a part of the first oxide semiconductor layer, and in contact with the circumference and lateral faces of the first and second oxide conductive layers; a first source electrode layer; and a first drain electrode layer. The second thin-film transistor has: a second gate electrode layer; a second oxide semiconductor layer; and a second source electrode layer and a second drain electrode layer configured by a material having light transmissivity.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a semiconductor device including an oxide semiconductor and a manufacturing method thereof.

[0002] In this specification, a semiconductor device is a device that can function by utilizing semiconductor characteristics. This generally refers to electro-optical devices such as display devices, semiconductor circuits, and electronic devices. be. [Background technology]

[0003] In recent years, semiconductor thin films (thickness of several to several hundred nm) formed on substrates with insulating surfaces have been used Thin film transistors (also called TFTs: Thin Film Transistors) Thin-film transistors are used in electronic devices such as ICs and electro-optical devices. It is widely used in child devices, and development is particularly urgent as a switching element for image display devices. Metal oxides exist in a wide variety of forms and are used in a wide range of applications. Indium nitride is a well-known material and is used as a transparent electrode material in liquid crystal displays and other devices. It is used as a fee.

[0004] Some metal oxides exhibit semiconducting properties. Examples of the oxide include tungsten oxide, tin oxide, indium oxide, and zinc oxide. Thin film transistors that use metal oxides with such semiconducting properties as the channel formation region are already known. (Patent Document 1 and Patent Document 2). [Prior art documents] [Patent documents]

[0005] [Patent Document 1] JP 2007-123861 A [Patent Document 2] JP 2007-96055 A Summary of the Invention [Problem to be solved by the invention]

[0006] When multiple thin film transistors are fabricated on an insulating surface, for example, gate wiring, source wiring, At the intersection, there is a gate wiring and a gate line having a different potential. An insulating layer is provided between the source wirings, and the insulating layer acts as a dielectric to generate capacitance. This is also called parasitic capacitance between wiring, and there is a risk that the signal waveform may become distorted. If the amount is too large, the signal transmission may be slowed down.

[0007] In addition, an increase in parasitic capacitance can cause crosstalk, which is when electrical signals leak between wiring, and can also lead to increased power consumption. This leads to increased power.

[0008] In an active matrix display device, the signal wiring for supplying a video signal is If a large parasitic capacitance is formed between the wiring or the electrode, the display quality may be deteriorated. be.

[0009] Furthermore, when miniaturizing circuits, the distance between wirings becomes narrower, and the parasitic capacitance between wirings increases. There is a risk of this happening.

[0010] One embodiment of the present invention provides a semiconductor device having a structure capable of sufficiently reducing parasitic capacitance between wirings. One of the goals is to

[0011] In addition, when a driver circuit is formed on an insulating surface, the operation of a thin film transistor used in the driver circuit A faster speed is preferable.

[0012] For example, the channel length (also called L) of a thin-film transistor can be shortened, or the channel width (W However, shortening the channel length increases the speed of the transistor. In addition, the switching characteristics, for example the on-off ratio, become smaller. This causes a problem of increasing the capacitive load of the thin film transistor itself.

[0013] In addition, a semiconductor device having a thin film transistor with stable electrical characteristics even if the channel length is short is also provided. It is also an object of the present invention to provide a body device.

[0014] In addition, when forming a plurality of different circuits on an insulating surface, for example, a pixel portion and a driver circuit may be formed on the same substrate. When formed on a substrate, the thin film transistor used in the pixel portion must have excellent switching characteristics. For example, a large on-off ratio is required, and the thin film transistors used in the drive circuits Fast operation speed is required. In particular, the higher the resolution of the display device, Since the writing time for the display image needs to be short, the thin-film transistors used in the driver circuits It is preferable that the motor has a high operating speed.

[0015] In addition, one embodiment of the present invention is to prevent a complicated process and an increase in manufacturing cost, and to achieve the same Multiple types of circuits are formed on the substrate, and multiple types of thin film transistors are used to match the characteristics of each of the multiple circuits. An object of the present invention is to provide a semiconductor device including a transistor. [Means for solving the problem]

[0016] One embodiment of the present invention includes a driver circuit and a pixel portion over the same substrate, Each of them has a thin film transistor. The driver circuit and the pixel section are fabricated on the same substrate. This will help reduce manufacturing costs.

[0017] In one embodiment of the present invention, a thin film transistor (also called a first thin film transistor) of a driving circuit The thin film transistor in the pixel portion (also called the second thin film transistor) is a bottom gate thin film transistor. These are thin-film transistors with a gate electrode (also called a gate electrode layer), A source electrode (also called a source electrode layer), a drain electrode (also called a drain electrode layer), and and a semiconductor layer having a channel formation region.

[0018] In one embodiment of the present invention, a gate electrode, a source electrode, and a drain electrode of a thin film transistor in a pixel portion are The drain electrode is made of a conductive layer having light-transmitting properties, and the semiconductor layer is made of a semiconductor layer having light-transmitting properties. That is, the thin film transistor in the pixel section is made of a transparent material. This improves the aperture ratio of the pixel portion.

[0019] In one embodiment of the present invention, a gate electrode of a thin film transistor of a driver circuit is The same material as the gate electrode of the thin film transistor or the gate electrode of the thin film transistor in the pixel area The thin film transistors of the drive circuit are constructed using a material with a lower resistance than the material used. The source electrode and the drain electrode are the source electrode and the drain electrode of the thin film transistor of the pixel portion. The thin film transistor in the pixel area is made of a material with a lower resistance than the electrode. The resistance values ​​of the source and drain electrodes of the thin film transistors of the driving circuits are higher than the resistance of the in-electrode.

[0020] In one embodiment of the present invention, the thin film transistor of the driver circuit includes a semiconductor layer and a source electrode. The structure has a conductive layer between the layers and between the semiconductor layer and the drain electrode. is preferably lower than that of the semiconductor layer and higher than that of the source electrode layer and the drain electrode layer. This improves the operating speed of the drive circuit.

[0021] In one embodiment of the present invention, the thin film transistor of the driver circuit is in contact with a part of the semiconductor layer. and the periphery and sides of the conductive layer between the semiconductor layer and the source electrode and between the semiconductor layer and the drain electrode. The oxide insulating layer is formed on the surface of the semiconductor substrate. As a result, the gate electrode layer and the wiring layer (source wiring layer and capacitance wiring layer) formed above or around the gate electrode layer By increasing the distance between the semiconductor device and the semiconductor layer, the parasitic capacitance is reduced. This makes it possible to suppress distortion of the signal waveform. In the present invention, a source electrode, a conductive layer provided between the semiconductor layer and the source electrode, and a drain The drain electrode is in contact with a conductive layer provided between the semiconductor layer and the drain electrode.

[0022] One embodiment of the present invention is a driver circuit having a first thin film transistor and a second thin film transistor, both of which are provided on the same substrate. The pixel has a first thin film transistor, and the first thin film transistor has a first gate electrode layer and A gate insulating layer is provided on the first gate electrode layer, and the first gate insulating layer is sandwiched between the gate insulating layer and the second gate electrode. a first oxide semiconductor layer provided on the base electrode layer and having a first channel formation region; a first oxide conductive layer and a second oxide conductive layer provided over a first oxide semiconductor layer; The first oxide conductive layer and the second oxide conductive layer are in contact with each other. a first oxide insulating layer in contact with the first and second side surfaces of the first source electrode layer; a first drain electrode layer in contact with the oxide conductive layer of the second thin film transistor; A second gate electrode layer made of a light-transmitting material and a gate insulating layer are sandwiched between the first gate electrode layer and the second gate electrode layer. a second oxide semiconductor layer provided on the second gate electrode layer and having a second channel formation region; a second oxide semiconductor layer formed of a light-transmitting material over the second oxide semiconductor layer; The semiconductor device has a first source electrode layer and a second drain electrode layer.

[0023] In one embodiment of the present invention, a source electrode layer and a drain electrode layer of a first thin film transistor are made of Al A conductive layer mainly composed of an element selected from the group consisting of Cr, Cu, Ta, Ti, Mo, and W, or A semiconductor device having a laminated structure combining these may also be used.

[0024] In one embodiment of the present invention, a source electrode layer and a drain electrode layer of the second thin film transistor are made of an oxide Indium oxide, indium tin oxide alloy, indium oxide zinc oxide alloy, or zinc oxide It may be a semiconductor device.

[0025] One embodiment of the present invention is a thin film transistor having a first thin film transistor and a second thin film transistor formed on the same substrate. The capacitor section has a capacitance wiring and a capacitance electrode overlapping the capacitance wiring, The capacitance electrode may be a semiconductor device having light-transmitting properties.

[0026] In one embodiment of the present invention, a first oxide semiconductor layer is formed on an oxide insulating layer of a first thin film transistor. The semiconductor device may have a conductive layer overlapping with the channel formation region.

[0027] In one embodiment of the present invention, the first oxide conductive layer and the second oxide conductive layer are a second thin film transistor. The semiconductor device may be made of the same material as the source and drain electrode layers of the transistor. .

[0028] One embodiment of the present invention is a driving circuit having a first thin film transistor and a second thin film transistor, both of which are provided on the same substrate. A method for manufacturing a semiconductor device having a pixel portion having a transistor, comprising: forming a gate electrode layer on the first gate electrode layer and a second gate electrode layer; A gate insulating layer is formed, and a first oxide semiconductor is formed on the first gate electrode layer with the gate insulating layer sandwiched therebetween. A conductor layer is formed, and a second oxide semiconductor is formed on the second gate electrode layer with a gate insulating layer interposed therebetween. A dielectric layer is formed, and the first oxide semiconductor layer and the second oxide semiconductor layer are dehydrated or dehydrogenated. Then, an oxide conductive film is formed over the first oxide semiconductor layer and the second oxide semiconductor layer, and an oxide A part of the oxide conductive film is removed to form a first oxide conductive layer on the first oxide semiconductor layer. and forming a second oxide conductive layer and forming a second source electrode layer on the second oxide semiconductor layer. and a second drain electrode layer, and forming an oxide insulating layer on the second source electrode layer and the second drain electrode layer; A portion of the edge layer is removed to expose a portion of the first oxide conductive layer and a portion of the second oxide conductive layer. forming a first source electrode layer in contact with the exposed first oxide conductive layer, and A semiconductor device comprising: a first drain electrode layer in contact with the second oxide conductive layer. This is a method for producing the above.

[0029] One embodiment of the present invention is to form a resist mask using a multi-tone mask, By performing etching using the above, the first oxide semiconductor layer, the second oxide semiconductor layer, and the first oxide semiconductor layer are A first oxide conductive layer, a second oxide conductive layer, a second source electrode layer, and a second drain electrode layer. The present invention may also be a method for manufacturing a semiconductor device, characterized in that a layer is formed.

[0030] The oxide semiconductor used in this specification is, for example, InMO 3 (ZnO)m(m> There is a metal oxide represented by the formula: A thin film transistor was fabricated using the compound semiconductor layer. M is Ga, Fe, Ni, It represents one or more metal elements selected from Mn and Co. For example, M is G In addition to the case of a, there are cases where the above metal elements other than Ga are included, such as Ga and Ni or Ga and Fe. In addition, in the above oxide semiconductor, in addition to the metal element contained as M, Impurity elements include Fe, Ni, other transition metal elements, or oxides of the transition metals. In this specification, InMO 3 (ZnO)m (m>0, and m is Among oxide semiconductor layers having a structure represented by the formula (not an integer), oxide semiconductor layers having a structure containing Ga as M are The compound semiconductor is called an In-Ga-Zn-O oxide semiconductor, and the thin film is called an In-Ga-Zn- It is also called an O-based semiconductor film.

[0031] In addition to the above, metal oxides that can be used for the oxide semiconductor layer include In-Sn-Zn-O In-Al-Zn-O, Sn-Ga-Zn-O, Al-Ga-Zn-O, Sn -Al-Zn-O series, In-Zn-O series, Sn-Zn-O series, Al-Zn-O series, In- Metal oxides of O, Sn-O, and Zn-O can be used. The oxide semiconductor layer made of such a material may contain silicon oxide.

[0032] The oxide semiconductor is preferably an oxide semiconductor containing In, more preferably an oxide semiconductor containing In and In order to make the oxide semiconductor layer i-type (intrinsic), Hydrogenation or dehydrogenation is effective.

[0033] In the manufacturing process of the semiconductor device, nitrogen or a rare gas (such as argon or helium) is used. When the heat treatment is performed under an inert gas atmosphere, the oxide semiconductor layer It becomes oxygen-deficient and has low resistance, i.e., it becomes N-type (N - Then, the oxide semiconductor layer is The oxide insulating layer is formed in contact with the oxide semiconductor layer, and the oxide semiconductor layer is made in an oxygen-excess state. This makes the semiconductor layer highly resistive, i.e., I-type. This results in good electrical properties. It is possible to manufacture and provide a semiconductor device having a highly reliable thin film transistor. .

[0034] In the manufacturing process of the semiconductor device, nitrogen or rare gas is used for dehydration or dehydrogenation. In an inert gas atmosphere (argon, helium, etc.), 350°C or higher, preferably 40 0° C. or higher and lower than the distortion point of the substrate, for example, 400° C. or higher and 700° C. or lower, more preferably, 420° C. or higher. Heat treatment is performed at a temperature higher than or equal to 570° C. to reduce impurities such as moisture contained in the oxide semiconductor layer. do.

[0035] The oxide semiconductor layer that has been dehydrated or dehydrogenated was measured using thermal desorption spectroscopy (TDS). Even when measurements were taken up to 50°C, there were two peaks for water, at least one that appeared near 300°C. No peak was detected. Even if thin-film transistors are measured up to 450°C using TDS, the temperature remains at least around 300°C. The water peak that appears in the

[0036] In the manufacturing process of the semiconductor device, the oxide semiconductor layer is not exposed to the air. It is important not to allow water or hydrogen to be mixed into the oxide semiconductor layer again. The oxide semiconductor layer is then siliconized to reduce its resistance, i.e., to become an N-type (N - After the hydrogen is absorbed, oxygen is supplied. By supplying the oxide semiconductor layer with a high resistance, a thin film transistor can be fabricated. In this case, the threshold voltage value of the thin film transistor can be made positive, and the so-called normally-off A switching element can be realized. The gate voltage of the thin film transistor is as close to 0V as possible. It is desirable for the channel to be formed at a positive threshold voltage. If the threshold voltage is negative, even if the gate voltage is 0V, For example, in an active matrix type In display devices, the electrical characteristics of the thin-film transistors that make up the circuits are important. The electrical characteristics of thin film transistors affect the performance of display devices. For example, thin film transistors have high field effect mobility characteristics. Even if it has a high threshold voltage, or if the threshold voltage is negative, the circuit In addition, in the case of thin film transistors with high threshold voltages, When the driving voltage is low, the TFT cannot perform its switching function and the load For example, in the case of an n-channel thin film transistor, a positive potential is applied to the gate electrode. The desired transistor is one in which a channel is formed and drain current begins to flow only when a voltage is applied. It is preferable to use transistors that do not form a channel unless the driving voltage is high, or transistors that operate under negative voltage conditions. However, the transistor in which the channel is formed and the drain current flows is the thin film transistor used in the circuit. It is not suitable as a transistor.

[0037] In addition, the gas atmosphere that is cooled from the heating temperature T is the same as the gas atmosphere that is heated to the heating temperature T. A different gas atmosphere may be used. For example, a large amount of hydrogen may be added to the same furnace in which dehydration or dehydrogenation was performed. The inside of the furnace is filled with high-purity oxygen gas or N 2 Fill with O gas and cool. cormorant.

[0038] The moisture content in the film is reduced by a heat treatment for dehydration or dehydrogenation, and then the film is heated to remove the moisture. The mixture was cooled slowly (or cooled) in a dew-free atmosphere (dew point below -40°C, preferably below -60°C). By using an oxide semiconductor film, the electrical characteristics of a thin film transistor can be improved and mass productivity can be improved. This will realize a thin-film transistor that has both high performance and low noise.

[0039] In this specification, the method is carried out under an inert gas atmosphere of nitrogen or a rare gas (argon, helium, etc.). The heat treatment is referred to as heat treatment for dehydration or dehydrogenation. Therefore, H 2 Dehydrogenation does not only mean the elimination of hydrogen, but also the elimination of hydrogen such as H and OH. For the sake of convenience, the removal of these compounds will be referred to as dehydration or dehydrogenation.

[0040] In the manufacturing process of the semiconductor device, the inert gas of nitrogen or rare gas (argon, helium, etc.) is not used. When heat treatment is performed in an active gas atmosphere, the oxide semiconductor layer is oxygen-deficient due to the heat treatment. It becomes depleted type and has low resistance, that is, N type (N - As a result, the oxide semiconductor layer In the HRS region, the source electrode layer overlaps with the oxygen-deficient high-resistance source region (HRS). The drain electrode layer is overlapped with the resistance source region. The high resistance drain region (HRD) is an oxygen-deficient region. A region called a rain region is formed.

[0041] Specifically, the carrier concentration in the high-resistance drain region is 1×10 18 / cm 3 That's all. At least the carrier concentration in the channel formation region (1×10 18 / cm 3 (less than) The carrier concentration in this specification is the carrier concentration obtained by Hall effect measurement at room temperature. Points to a value.

[0042] In addition, a low-resistance source region (L RS (Low Resistance Source) region and low resistance drain It forms a region (also called a LRD (Low Resistance Drain) region) Specifically, the carrier concentration of the low-resistance drain region is set to be higher than that of the high-resistance drain region (HR D region), e.g., 1×10 20 / cm 3 More than 1×10 21 / cm 3 The following categories It is within the range.

[0043] Then, at least a part of the dehydrated or dehydrogenated oxide semiconductor layer is made into an oxygen-excess state. By this, the oxide semiconductor layer is made more highly resistant, that is, made into an i-type, and a channel formation region is formed. Note that a method for making a dehydrated or dehydrogenated oxide semiconductor layer into an oxygen-excess state is as follows. For example, a sputtering In addition, the oxide insulating layer may be formed by a coating method. Afterwards, heat treatment (for example, heat treatment in an oxygen-containing atmosphere) or heating in an inert gas atmosphere Then, the mixture is cooled in an oxygen atmosphere, or in ultra-dry air (dew point below -40°C, preferably -6 A cooling process to a temperature of 0°C or lower may also be performed.

[0044] In addition, at least a part of the dehydrated or dehydrogenated oxide semiconductor layer (which overlaps with the gate electrode layer) In order to make the upper part of the oxide semiconductor layer (the upper part) into a channel formation region, the oxide semiconductor layer is selectively made into an oxygen-excess state. The conductor layer can be made highly resistive, i.e., I-type. Form source and drain electrode layers made of metal electrodes such as Ti on the semiconductor layer. and selectively oxidizing an exposed region of the oxide semiconductor layer that does not overlap with the source electrode layer or the drain electrode layer. A channel formation region can be formed by selectively removing the oxide semiconductor layer. When the oxygen concentration is increased, the high-resistance source region overlapping the source electrode layer and the drain electrode A high-resistance drain region is formed overlying the layer, and the high-resistance source region and the high-resistance drain region are formed. The region between the source electrode layer and the drain electrode layer is a channel forming region. The gate electrode layer is formed in a self-aligned manner between the drain electrode layers.

[0045] According to one embodiment of the present invention, a semiconductor having a thin film transistor with favorable electrical characteristics and high reliability is provided. It becomes possible to manufacture and provide the device.

[0046] Note that a high-resistance drain electrode layer (and a source electrode layer) is formed in the oxide semiconductor layer overlapping the drain electrode layer (and the source electrode layer). By forming a drain region (and a high-resistance source region), the reliability of the drive circuit is improved. Specifically, by forming a high-resistance drain region, The conductivity is gradually increased from the drain electrode layer to the high-resistance drain region and the channel formation region. Therefore, the drain electrode layer can be connected to a high power supply potential V When electrically connecting to the wiring that supplies DD, the gate electrode layer and the drain electrode layer Even if a high electric field is applied between the drain and the drain, the high resistance drain region acts as a buffer to prevent localized electric field concentration. This can improve the breakdown voltage of the transistor.

[0047] In addition, by forming a high resistance drain region (and a high resistance source region), Specifically, the high resistance source region and the high resistance drain region are By forming a drain region, the current between the drain electrode layer and the source electrode layer of the transistor The leakage current flows through the drain electrode layer, the high-resistance drain region, the channel formation region, and the high-resistance source At this time, in the channel formation region, the The leakage current flowing in the channel formation region is transferred to the gate, which has high resistance when the transistor is in the off state. The back channel region ( To reduce leakage current in a part of the surface of the channel forming region that is separated from the gate electrode layer It is possible.

[0048] In addition, a high resistance source region overlapping the source electrode layer and a high resistance drain region overlapping the drain electrode layer are The gate region overlaps a part of the gate electrode layer via the gate insulating layer, depending on the width of the gate electrode layer. By adopting this structure, the electric field strength near the end of the drain electrode layer can be more effectively alleviated. It is possible to do so.

[0049] The ordinal numbers such as 1st and 2nd are used for convenience and do not indicate the order of steps or stacking. In addition, the specific names used in this specification are not intended to identify the invention. This does not indicate the

[0050] In addition to liquid crystal display devices, display devices having a driving circuit include light-emitting devices using light-emitting elements. display devices, and display devices also called electronic paper using electrophoretic display elements. .

[0051] In a light-emitting display device using a light-emitting element, a pixel portion has a plurality of thin film transistors. In the elemental area, the gate electrode of a thin-film transistor and the source wiring (so The point where the source wiring layer or drain wiring (also called drain wiring layer) is connected In addition, in a driving circuit of a light-emitting display device using a light-emitting element, a thin-film transistor The gate electrode of the thin film transistor is connected to the source wiring or drain wiring of the thin film transistor. It has some parts that allow you to do so.

[0052] In addition, in a liquid crystal display device, when a pixel portion and a driver circuit are formed on the same substrate, In this paper, logic gates such as inverter circuits, NAND circuits, NOR circuits, and latch circuits are used. The thin-film transistors that make up the MOSFET, as well as the analog components such as the sense amplifier, constant voltage generator, and VCO The thin-film transistors that make up the gate circuit have only positive polarity between the source and drain electrodes, or Therefore, the width of the high resistance drain region, which is required to withstand voltage, is set to the high resistance. The width of the high-resistance source region and the high-resistance drain region may be designed to be wider than that of the high-resistance source region. The width of the in-region overlapping with the gate electrode layer may be increased.

[0053] In addition, the thin-film transistors arranged in the drive circuits are single-gate thin-film transistors. However, if necessary, a multi-gate structure having a plurality of channel formation regions may be used. Thin film transistors can also be formed.

[0054] Moreover, in order to prevent deterioration of the liquid crystal, the liquid crystal display device is driven by an alternating current. As a result, the polarity of the signal potential applied to the pixel electrode layer is changed to positive or negative at regular intervals. The TFT electrically connected to the pixel electrode layer has a pair of electrodes that alternately switch between the source electrode layer and the pixel electrode layer. It serves as a drain electrode layer. In this specification, for convenience, a pair of thin film transistors of a pixel One of the electrodes is called the source electrode layer and the other is called the drain electrode layer. During flow driving, one electrode alternately functions as a source electrode layer and a drain electrode layer. In order to reduce leakage current, the width of the gate electrode layer of the thin film transistor arranged in the pixel is driven. The width of the gate electrode layer of the thin film transistor of the driving circuit may be narrower than that of the gate electrode layer of the thin film transistor of the driving circuit. In order to reduce the number of layers, the gate electrode layer of the thin film transistor arranged in the pixel is formed as a source electrode layer or It may be designed so as not to overlap with the drain electrode layer. Effect of the Invention

[0055] According to one embodiment of the present invention, a thin film transistor having stable electrical characteristics is manufactured and provided. Therefore, a semiconductor having a thin film transistor with good electrical characteristics and high reliability can be obtained. An apparatus can be provided. [Brief description of the drawings]

[0056] [Figure 1] 1A to 1C are diagrams illustrating a semiconductor device. [Diagram 2]1A to 1C illustrate a method for manufacturing a semiconductor device. [Diagram 3] 1A to 1C illustrate a method for manufacturing a semiconductor device. [Figure 4] 1A to 1C illustrate a method for manufacturing a semiconductor device. [Diagram 5] 1A to 1C illustrate a method for manufacturing a semiconductor device. [Figure 6] 1A to 1C are diagrams illustrating a semiconductor device. [Figure 7] 1A to 1C are diagrams illustrating a semiconductor device. [Figure 8] 1A to 1C are diagrams illustrating a semiconductor device. [Figure 9] 1A to 1C are diagrams illustrating a semiconductor device. [Figure 10] 1A to 1C are diagrams illustrating a semiconductor device. [Figure 11] 1A to 1C are diagrams illustrating a semiconductor device. [Figure 12] 1A and 1B are diagrams illustrating a pixel equivalent circuit of a semiconductor device. [Figure 13] 1A to 1C are diagrams illustrating a semiconductor device. [Figure 14] FIG. 1 is a block diagram illustrating a semiconductor device. [Figure 15] 2A to 2C are diagrams illustrating a configuration and operation of a signal line driver circuit. [Figure 16] FIG. 1 is a circuit diagram showing a configuration of a shift register. [Figure 17] 1A and 1B are diagrams for explaining the configuration and operation of a shift register; [Figure 18] 1A to 1C are diagrams illustrating a semiconductor device. [Figure 19] 1A to 1C are diagrams illustrating a semiconductor device. [Figure 20] FIG. 1 is an external view showing an example of an electronic book. [Figure 21] FIG. 1 is an external view showing an example of a television device and a digital photo frame. [Figure 22] FIG. 1 is an external view showing an example of a gaming machine. [Figure 23] FIG. 1 is an external view showing an example of a portable computer and a mobile phone. [Figure 24] 1A to 1C are diagrams illustrating a semiconductor device. [Diagram 25] 1A to 1C are diagrams illustrating a semiconductor device. [Figure 26] 1A to 1C are diagrams illustrating a semiconductor device. [Figure 27] 1A to 1C are diagrams illustrating a semiconductor device. [Figure 28] 1A to 1C are diagrams illustrating a semiconductor device. [Figure 29] 1A to 1C are diagrams illustrating a semiconductor device. [Diagram 30] 1A to 1C are diagrams illustrating a semiconductor device. [Diagram 31] 1A to 1C are diagrams illustrating a semiconductor device. [Diagram 32] 1A to 1C are diagrams illustrating a semiconductor device. [Diagram 33] 1A to 1C are diagrams illustrating a semiconductor device. [Diagram 34] 1A to 1C are diagrams illustrating a semiconductor device. [Diagram 35] 1A to 1C are diagrams illustrating a semiconductor device. [Diagram 36] 1A to 1C are diagrams illustrating a semiconductor device. [Figure 37] 1A to 1C are diagrams illustrating a semiconductor device. [Figure 38] 1A to 1C are diagrams illustrating a semiconductor device. [Figure 39] 1A to 1C illustrate a method for manufacturing a semiconductor device. [Diagram 40] 1A to 1C illustrate a method for manufacturing a semiconductor device. [Diagram 41] 1A to 1C illustrate a method for manufacturing a semiconductor device. [Diagram 42] 1A to 1C are diagrams illustrating a semiconductor device. [Diagram 43] 1A to 1C are diagrams illustrating a semiconductor device. [Diagram 44] 1A to 1C illustrate a method for manufacturing a semiconductor device. [Diagram 45] 1A to 1C are diagrams illustrating a semiconductor device. [Diagram 46] 1A to 1C illustrate a method for manufacturing a semiconductor device. [Figure 47] 1A to 1C are diagrams illustrating a semiconductor device. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0057] The embodiment will be described in detail with reference to the drawings. However, the present invention is not limited to the following description. It is understood by those skilled in the art that various changes in form and detail may be made without departing from the spirit and scope of the present invention. Therefore, the present invention should be interpreted as being limited to the following description of the embodiment. In the configuration described below, parts having the same parts or similar functions are not included. The same reference numerals are used in common between different drawings for the corresponding parts, and the repeated explanations will be omitted.

[0058] The contents of each embodiment may be combined or substituted with each other as appropriate. Cut.

[0059] (Embodiment 1) A semiconductor device and a method for manufacturing the semiconductor device will be described with reference to FIGS. The cross-sectional structure of two thin-film transistors fabricated on a substrate is shown in FIG. The thin film transistor 410 and the thin film transistor 420 are bottom-gate transistors. .

[0060] FIG. 1(A1) is a plan view of a thin film transistor 410 disposed in a driving circuit. 2) is a plan view of a thin film transistor 420 disposed in a pixel, and FIG. 1(B) is a plan view of a thin film transistor 420 disposed in a pixel. A1) of the cross-sectional structure taken along line C1-C2 and a cross-sectional structure taken along line D1-D2 in FIG. 1(A2) FIG. 1(C) is a cross-sectional view taken along line C3-C4 in FIG. 1(A1). 2 is a cross-sectional view showing the structure and the cross-sectional structure taken along line D3-D4 in FIG.

[0061] The thin film transistor 410 disposed in the driving circuit is formed on a substrate 400 having an insulating surface. A gate electrode layer 411, a gate insulating layer 402, at least a channel forming region 413, and a high resistance An oxide semiconductor layer 412 having an anti-source region 414a and a high-resistance drain region 414b A low-resistance source region 408a, a low-resistance drain region 408b, a source electrode layer 415a, The thin film transistor 410 also includes a low resistance source / drain electrode layer 415b. The periphery and side surface of the region 408a and the low-resistance drain region 408b, and the oxide semiconductor layer 4 12 includes an oxide insulating layer 416 in contact with the substrate 12 .

[0062] The high-resistance source region 414a is self-aligned to the bottom surface of the low-resistance source region 408a. The high-resistance drain region 414b is formed in a symmetrical manner. The channel forming region 413 is formed in a self-aligned manner in contact with the bottom surface of the oxidized layer 412. The high-resistance source region 414a and the high-resistance drain region 414b are in contact with the insulating layer 416. The region is also a high resistance region (I-type region).

[0063] The source electrode layer 415a is in contact with the low-resistance source region 408a, and the drain electrode layer 415b is in contact with the low-resistance source region 408a. , contacting the low-resistance drain region 408b.

[0064] The source electrode layer 415a and the drain electrode layer 415b are formed by using It is preferable to use a metallic material.

[0065] In addition, by providing a low-resistance source region 408a and a low-resistance drain region 408b, Compared to the Schottky junction, the oxide semiconductor layer provides a more stable thermal operation. By intentionally providing a low-resistance drain region with a higher carrier concentration than the Form a contact.

[0066] A conductive layer 417 overlapping the channel forming region 413 is formed above the channel forming region 413. The conductive layer 417 is electrically connected to the gate electrode layer 411 and has the same potential. The oxide semiconductor layer 412 disposed between the gate electrode layer 411 and the conductive layer 417 is provided with gate electrodes from above and below. In addition, the gate electrode layer 411 and the conductive layer 417 can be set to different potentials. For example, when the potential is a fixed potential, GND potential, or 0V, the electrical characteristics of the TFT, for example, the threshold That is, the gate electrode layer 411 and the conductive layer 417 can be controlled. One of the layers functions as a first gate electrode layer, and the other of the gate electrode layer 411 and the conductive layer 417 functions as a second gate electrode layer. The thin film transistor 410 is configured as a four-terminal thin film transistor by using the second gate electrode layer as the second gate electrode layer. It can be used as a transistor.

[0067] In addition, the conductive layer 417, the source electrode layer 415a, the drain electrode layer 415b, and the oxide A planarization insulating layer 404 is provided between the material insulating layers 416 .

[0068] The thin film transistor 420 disposed in the pixel is formed on a substrate 400 having an insulating surface, and has a gate An electrode layer 421, a gate insulating layer 402, at least a channel forming region 423, and a high resistance so an oxide semiconductor layer 422 including a source region 424a and a high-resistance drain region 424b; The thin film transistor includes a source electrode layer 409a and a drain electrode layer 409b. 420 includes an oxide insulating layer 416 in contact with an oxide semiconductor layer 422 .

[0069] The high-resistance source region 424a is in contact with the lower surface of the source electrode layer 409a in a self-aligned manner. The high-resistance drain region 424b is formed on the lower surface of the drain electrode layer 409b. The channel formation region 423 is formed in a self-aligned manner in contact with the oxide insulating layer. 416 and has a higher resistance than the high-resistance source region 424a and the high-resistance drain region 424b. This region is called type I region.

[0070] Note that the oxide semiconductor layer 412 corresponds to the source electrode layer 415a and the drain electrode layer 415b. The oxide semiconductor layer 412 is connected to the gate electrode via the gate insulating layer 402. That is, the gate electrode layer 411 is overlapped with the gate insulating layer 402. The oxide semiconductor layer 422 is provided under the oxide semiconductor layer 412. The oxide semiconductor layer 409 is partially overlapped with the electrode layer 409a and the drain electrode layer 409b. 422 overlaps with the gate electrode layer 421 via the gate insulating layer 402. The gate electrode layer 421 is provided under the oxide semiconductor layer 422 with the gate insulating layer 402 interposed therebetween. can be.

[0071] The source electrode layer 409a and the drain electrode layer 409b are made of a thin, light-transmitting In order to realize a display device with a high aperture ratio as a film transistor, a material with light transmission properties is required. Note that the source electrode layer 415a and the drain electrode layer 415b are formed by using a source electrode It is preferable to use a material having a lower resistance than the layer 409a and the drain electrode layer 409b.

[0072] The gate electrode layer 421 is also formed using a light-transmitting material.

[0073] In addition, in the pixel in which the thin film transistor 420 is disposed, the pixel electrode layer 427 and other Translucent to visible light as an electrode layer (capacitor electrode layer, etc.) or wiring layer (capacitor wiring layer, etc.) By using a conductive layer having the above structure, a display device having a high aperture ratio is realized. 2. The oxide insulating layer 416 and the planarization insulating layer 404 are also formed of a film that transmits visible light. It is preferable to form it using

[0074] In addition, the pixel electrode layer 427, the source electrode layer 409a, the drain electrode layer 409b, and A planarization insulating layer 404 is provided between the oxide insulating layers 416 .

[0075] The pixel electrode layer 427 is formed through an opening (also called a contact hole) provided in the oxide insulating layer 416. and contacts the drain electrode layer 409b through an opening provided in the planarization insulating layer 404. do.

[0076] Note that the oxide semiconductor layers 412 and 422 are formed using an oxide semiconductor Heat treatment to reduce impurities such as moisture after film formation (for dehydration or dehydrogenation) After the heat treatment for dehydration or dehydrogenation and slow cooling, the formed The oxide insulating layer is formed in contact with the oxide semiconductor layer 412 and the oxide semiconductor layer 422. The carrier concentration of the oxide semiconductor layer is reduced by performing the above-mentioned process. This leads to improved electrical characteristics and reliability of the film transistor 420.

[0077] In this specification, a film that is transparent to visible light has a visible light transmittance of 75 If the film is conductive, it is called a transparent conductive film. Also, the gate electrode layer, the source electrode layer, the drain electrode layer, the pixel electrode layer, Other electrode layers and wiring layers may be formed using conductive films that are semitransparent to visible light. Being semi-transparent to light means that the visible light transmittance is 50 to 75%.

[0078] In the semiconductor device shown in FIG. 1, a thin film transistor 410 and a thin film transistor The channel lengths of the driver 420 are the same, but the present invention is not limited to this. Thin-film transistors for display are required to operate faster than thin-film transistors for pixels, so they are thinner. The channel length of the thin film transistor 410 is narrower than the channel length of the thin film transistor 420. In this case, the channel length of the thin film transistor 410 may be, for example, about 1 μm to 5 μm. It is preferable that the channel length of the thin film transistor 420 is 5 μm to 20 μm. It is preferred.

[0079] As described above, the semiconductor device shown in FIG. 1 has a first thin film transistor on the same substrate. A structure having a pixel having a driver circuit and a second thin film transistor, The first thin film transistor is made of a light-transmitting material, and the second thin film transistor is made of a light-transmitting material. The material has a lower resistance than the material having a lower resistance. The operating speed of the drive circuit can be improved. By providing a driving circuit and a pixel on a substrate, a wiring for electrically connecting the driving circuit and the pixel is formed. This allows for a reduction in the number of lines and the overall length of the wiring that electrically connects the driver circuit and the pixels. This makes it possible to reduce the size and cost of the semiconductor device.

[0080] In the semiconductor device shown in FIG. 1, the source electrode layer and A low-resistance source is provided between the drain electrode layer and the oxide semiconductor layer in which the channel formation region is formed. The structure has a low-resistance source region and a low-resistance drain region. By providing a switching region, the frequency characteristics of the peripheral circuits (drive circuits) can be improved. Compared with the direct contact between the metal electrode layer and the oxide semiconductor layer, the This is because the contact with the low-resistance drain region can reduce the contact resistance. Electrode layer using molybdenum (e.g., stack of molybdenum layer, aluminum layer, molybdenum layer) ) have a high contact resistance with the oxide semiconductor layer, which is due to the fact that molybdenum, for example, is more resistant to contact with titanium. Since the oxide semiconductor layer is not easily oxidized, the action of extracting oxygen from the oxide semiconductor layer is weak. However, the contact interface between the oxide semiconductor layer and the source electrode is not n-type. A low-resistance source region and a low-resistance drain region are interposed between the electrode layer and the drain electrode layer. This reduces the contact resistance and improves the frequency characteristics of the peripheral circuits (drive circuits). In addition, by providing a low-resistance source region and a low-resistance drain region, The channel length of the MOSFET is determined by the etching of the layers that will become the low-resistance source and drain regions. Since the channel length is determined at the time of purchase, the channel length can be made shorter.

[0081] In addition, the semiconductor device shown in FIG. 1 has a thin film transistor of a driver circuit, and an oxide semiconductor layer and on a part of the oxide conductive layer in contact with the source electrode layer and the drain electrode layer. The oxide insulating layer is in contact with the surface of the thin film transistor. Wiring in the same layer as the gate electrode layer and wiring in the same layer as the source electrode layer and the drain electrode layer are provided on the side portions. When the insulating layer is sandwiched between the gate electrode layer and the gate electrode layer, the insulating layer is formed in the same layer as the gate electrode layer. The distance between the wiring and the wiring in the same layer as the source electrode layer and the drain electrode layer can be increased. Therefore, the parasitic capacitance can be reduced.

[0082] In addition, in the semiconductor device shown in FIG. 1, an oxide insulating layer and The planarizing insulating layer is sandwiched between the channel forming region and the insulating layer, and the planarizing insulating layer is overlapped with the channel forming region. The planarizing insulating layer is made of a light-transmitting material. This allows the structure to have a conductive layer that controls the threshold voltage of the thin film transistor. It is possible.

[0083] Furthermore, the transistor of this embodiment mode can also have a structure shown in FIG. In comparison with the semiconductor device shown in FIG. 1, the gate insulating layer of the semiconductor device is a laminate of multiple insulating layers. and has a protective insulating layer on the oxide insulating layer in contact with the semiconductor layer. That is, the semiconductor device shown in FIG. 6 has a gate insulating layer 402 instead of the gate insulating layer 402 shown in FIG. 1. The oxide insulating layer 41 shown in FIG. 6 has a protective insulating layer 403 on the upper surface of the semiconductor device. In this case, the parts common to the semiconductor device shown in FIG. 1 will be appropriately referred to in the description of the semiconductor device shown in FIG. The description here will be omitted.

[0084] The gate insulating layer 402a and the gate insulating layer 402b may be, for example, the gate insulating layer shown in FIG. Materials applicable to the layer 402 can be used. For the gate insulating layer 402a, for example, A nitride insulating layer can be used, and the gate insulating layer 402b can be, for example, an oxide insulating layer. can be used.

[0085] Hereinafter, the thin film transistor 41 will be described with reference to FIGS. 2(A) to 2(E) and FIGS. 3(A) to 3(D). An example of a manufacturing process of the thin film transistor 420 will be described.

[0086] First, a light-transmitting conductive film is formed on a substrate 400 having an insulating surface, and then a first photo A resist mask is formed on a part of the conductive film by a lithography process. The conductive film is etched using a etch mask to form gate electrode layers 411 and 421. In addition, the pixel portion is formed of the same material and the same first photolithography as the gate electrode layers 411 and 421. The capacitance wiring (also called the capacitance wiring layer) is formed by the film process. If a capacitance is required for the circuit, a capacitance wiring is also formed in the driving circuit. The resist mask may be formed by an inkjet method. Since no photomask is used, manufacturing costs can be reduced.

[0087] There is no significant limitation on the substrate that can be used for the substrate 400 having an insulating surface. In any case, it is necessary for the insulating surface to have sufficient heat resistance to withstand subsequent heat treatment. The substrate 400 may be, for example, a glass substrate.

[0088] In addition, for glass substrates, if the temperature of the subsequent heat treatment is high, the distortion point is 730°C or higher. The glass substrate may be, for example, an aluminosilicate glass. Glass materials such as aluminoborosilicate glass and barium borosilicate glass are used. In addition, by containing more barium oxide (BaO) than boric acid, it is more practical. Heat-resistant glass is obtained. 2 O 3 By using a glass substrate containing more BaO, is preferred.

[0089] Instead of the above glass substrate, the substrate 400 may be a ceramic substrate, a quartz substrate, or a sapphire substrate. Alternatively, a substrate made of an insulating material such as a glass substrate may be used as the substrate 400. etc. can be used.

[0090] In addition, an insulating film serving as a base film may be provided between the substrate 400 and the gate electrode layers 411 and 421. The undercoat film has a function of preventing the diffusion of impurity elements from the substrate 400. A film or a plurality of films selected from a silicon oxide film, a silicon nitride oxide film, and a silicon oxynitride film. The insulating film can be formed by laminating the above-mentioned films.

[0091] The gate electrode layers 411 and 421 can be formed of a conductive material that transmits visible light. For example, In-Sn-Zn-O, In-Al-Zn-O, Sn-Ga-Zn-O, A l-Ga-Zn-O series, Sn-Al-Zn-O series, In-Zn-O series, Sn-Zn-O series , Al-Zn-O, In-Sn-O, In-O, Sn-O, Zn-O conductivity Metal oxide can be used, and the thickness of the gate electrode layer 411, 421 is set to 50 nm or more. The thickness of the gate electrode layers 411 and 421 is in the range of 00 nm or less. Examples of deposition methods include sputtering, vacuum deposition (electron beam deposition, etc.), and arc discharge ion deposition. The plating method or spray method is used. When the sputtering method is used, Si O 2 The film is formed using a target containing 2% by weight or more and 10% by weight or less of The conductive film has a high crystallization inhibitor SiO x (x>0) may be included. This Prevents crystallization during the heat treatment for dehydration or dehydrogenation in the subsequent process. It is possible.

[0092] Next, the resist mask is removed, and a gate electrode layer is formed on the gate electrode layer 411 and the gate electrode layer 421. An insulating layer 402 is formed.

[0093] The gate insulating layer 402 is a silicon oxide layer formed by using a plasma CVD method, a sputtering method, or the like. A silicon nitride layer, a silicon oxynitride layer, or a silicon nitride oxide layer is formed as a single layer or a laminated layer. For example, when forming a silicon oxynitride layer, the deposition gas is SiH 4 , oxygen and A silicon oxynitride layer may be formed by plasma CVD using silicon and nitrogen. The thickness of the insulating layer 402 is set to 100 nm or more and 500 nm or less. In the case of a laminated layer, for example, A first gate insulating layer having a thickness of 50 nm to 200 nm, and a second gate insulating layer having a thickness of 5 The second gate insulating layer is laminated to a thickness of not less than 300 nm.

[0094] In this embodiment, a silicon nitride layer having a thickness of 200 nm or less is formed by plasma CVD. The insulating layer 402 is a thin film.

[0095] Next, an oxide semiconductor film 430 having a thickness of 2 nm to 200 nm is formed over the gate insulating layer 402. After the oxide semiconductor film 430 is formed, the oxide semiconductor film 430 is dehydrated or dehydrogenated. Even if heat treatment for the formation of the oxide semiconductor layer is performed, the oxide semiconductor layer to be formed later is in an amorphous state. The oxide semiconductor film 430 is preferably thinned to a thickness of 50 nm or less. In this way, when heat treatment is performed after the formation of the oxide semiconductor film 430, the oxide semiconductor film 430 formed later can be prevented from being damaged. This can prevent the body layer from crystallizing.

[0096] Note that before the oxide semiconductor film 430 is formed by a sputtering method, argon gas is introduced. The plasma is generated by reverse sputtering, and the dust adhering to the surface of the gate insulating layer is removed. It is preferable to remove the target. Reverse sputtering is a method of sputtering a target by applying no voltage to the target. In a nitrogen atmosphere, a voltage is applied to the substrate side using an RF power source to generate plasma near the substrate. This is a method for modifying the surface. Note that nitrogen, helium, oxygen, etc. can be used instead of argon atmosphere. It's fine.

[0097] The oxide semiconductor film 430 may be an In-Ga-Zn-O based non-single crystal film, an In-Sn-Zn -O system, In-Al-Zn-O system, Sn-Ga-Zn-O system, Al-Ga-Zn-O system, Sn-Al-Zn-O series, In-Zn-O series, Sn-Zn-O series, Al-Zn-O series, I The oxide semiconductor films used in this study are n-Sn-O, In-O, Sn-O, and Zn-O. In this embodiment, sputtering is performed using an In-Ga-Zn-O oxide semiconductor target. The film is formed by a method under a rare gas (typically argon) atmosphere, an oxygen atmosphere, or Oxide is deposited by sputtering in an atmosphere of rare gas (typically argon) and oxygen. A semiconductor film 430 can be formed. When a sputtering method is used, SiO 2 The oxide semiconductor film 430 is formed using a target containing 2 wt % to 10 wt % of In this case, the oxide semiconductor film 430 may contain SiOx (x>0) which inhibits crystallization. This prevents the formation of the later-formed fluorine-containing ... Therefore, crystallization of the oxide semiconductor layer can be suppressed.

[0098] Next, a resist mask is formed over the oxide semiconductor film 430 by a second photolithography process. Then, the resist mask is used to selectively etch the oxide semiconductor. The semiconductor film 430 is processed into an island-shaped oxide semiconductor layer. A resist mask for this purpose may be formed by an inkjet method. When the film is formed by the jet method, a photomask is not used, and therefore the manufacturing cost can be reduced.

[0099] Next, the resist mask is removed, and the oxide semiconductor layer is dehydrated or dehydrogenated. The temperature of the first heat treatment for dehydrogenation is 400° C. or higher and lower than the distortion point of the substrate, for example, 40 The temperature is from 0°C to 700°C, preferably from 425°C to 700°C. If the temperature is below 700°C, the heat treatment time can be up to 1 hour. The processing time is set to be longer than one hour. The substrate 400 having the oxide semiconductor layer formed thereon is introduced into a furnace, and the oxide semiconductor layer is After the heat treatment in a nitrogen atmosphere, the oxide semiconductor layer was By preventing re-mixing of water or hydrogen, the resistance of the oxide semiconductor layers 431 and 432 is reduced (FIG. 2(B) In this embodiment, the heating temperature T The same furnace is used to heat the material up to a temperature that is high enough to prevent water and hydrogen from entering again. The temperature is gradually cooled in a nitrogen atmosphere until the temperature drops by 100°C or more below T. First, dehydration or dehydrogenation is performed under a rare gas atmosphere such as helium, neon, or argon. This is also fine.

[0100] In the first heat treatment, nitrogen, helium, neon, argon, or the like is used. It is preferable that the rare gas does not contain water, hydrogen, etc. The purity of rare gases such as nitrogen, helium, neon, and argon is 6N (99.9999%) or more. Preferably, the nitrogen introduced into the heat treatment device is 7N (99.99999%) or more. The impurity concentration of rare gases such as helium, neon, and argon is kept below 1 ppm, preferably below 0.1 It is preferable to keep it below ppm.

[0101] Depending on the conditions of the first heat treatment or the material of the oxide semiconductor layer, the oxide semiconductor layer may be annealed. In some cases, the layer may crystallize to form a microcrystalline or polycrystalline layer.

[0102] The first heat treatment is performed on an oxide semiconductor film before it is processed into an island-shaped oxide semiconductor layer. In that case, after the first heat treatment, the substrate is taken out of the heating device and is then heated with a photo A lithography process is performed to form a resist mask, and the resist mask is used to selectively The oxide semiconductor film is processed by etching.

[0103] In addition, before the formation of the oxide semiconductor film, an inert gas atmosphere (nitrogen, helium, neon, or arsenic) is used. Heat treatment in an oxygen atmosphere (400°C or higher but below the distortion point of the substrate) under a rare gas such as argon. impurities such as hydrogen and water contained in the gate insulating layer may be removed.

[0104] Next, an oxide conductive film is formed over the oxide semiconductor layers 431 and 432 and the gate insulating layer 402. Then, resist masks 433a and 433b are formed by a third photolithography process. Then, selective etching is performed to form oxide conductive layers 406 and 407 (see FIG. 2C). The material of the oxide conductive film is a conductive material that is transparent to visible light, such as In. -Sn-Zn-O, In-Al-Zn-O, Sn-Ga-Zn-O, Al-Ga- Zn-O series, Sn-Al-Zn-O series, In-Zn-O series, Sn-Zn-O series, Al-Z nO series, In-Sn-O series, Al-Zn-ON series, In-O series, Sn-O series, Zn- O-based conductive metal oxides can be used, and the thickness of the oxide conductive film can be set to 50 nm or more. The thickness of the oxide conductive film is appropriately selected within the range of 0 nm or less. When using the coating method, SiO 2 The target contains 2% by weight or more and 10% by weight or less. The conductive film is then coated with a SiO film that inhibits crystallization. x (x>0) may be included This allows the later-formed fluorine-containing ... This can prevent the oxide conductive layers 406 and 407 from being crystallized.

[0105] Note that in the method for manufacturing a semiconductor device in this embodiment, the above-described dehydration or Dehydrogenation (first heat treatment) is performed to form oxide conductive films or oxide conductive layers 406 and 407. It can also be done after

[0106] Here, an oxide semiconductor target containing In, Ga, and Zn (In 2 O 3 :Ga 2 O 3 :ZnO=1:1:1[mol ratio], In:Ga:Zn=1:1:0.5[atom The distance between the substrate and the target was set to 100 mm, the pressure was 0.2 Pa, and the direct current ( DC) power supply 0.5kW, argon and oxygen (argon:oxygen = 30sccm:20scc The oxide semiconductor film 430 is formed in an atmosphere of 1000 MPa (oxygen flow rate: 40%). It is preferable to use a DC power source, as this reduces dust and makes the film thickness distribution uniform. The thickness of the n-Ga-Zn-O based non-single crystal film is set to 5 nm to 200 nm. In the present study, an In-Ga-Zn-O oxide semiconductor target was used to form the oxide semiconductor film. A 20 nm thick In-Ga-Zn-O non-single crystal film is formed by sputtering. In addition, the oxide semiconductor target material may be, for example, In:Ga:ZnO=1:1:1, or A target material such as In:Ga:ZnO=1:1:4 can also be used.

[0107] In addition, the sputtering method uses RF sputtering, which uses a high-frequency power source as the sputtering power source. There are two methods: DC sputtering and DC sputtering. There is also a method called pulsed DC There is also the sputtering method. The RF sputtering method is mainly used to deposit insulating films. The DC sputtering method is mainly used for forming metal films.

[0108] There are also multi-target sputtering devices that can accommodate multiple targets of different materials. The sputtering equipment can deposit layers of different materials in the same chamber, or multiple layers in the same chamber. It is also possible to form films by discharging multiple types of materials simultaneously using the bar.

[0109] In addition, a magnetron sputtering method using a magnet mechanism inside the chamber is used. E using a plasma generating device using microwaves instead of glow discharge. There is a sputtering device that uses the CR sputtering method.

[0110] In addition, as a method for forming a film using a sputtering method, a target material and a sputtering method are used during film formation. Reactive sputtering is a method in which a compound thin film is formed by chemically reacting the components of the sputtering gas with the There are also sputtering methods in which a voltage is applied to the substrate during deposition, and bias sputtering methods in which a voltage is also applied to the substrate during deposition.

[0111] Next, the resist masks 433a and 433b are removed, and a fourth photolithography is performed. A resist mask 436a and a resist mask 436b are formed by a lithography process. By selectively etching the low resistance source region 408a and the low A resistive drain region 408b and a source electrode layer 409a and a drain electrode layer 409b are formed. (See FIG. 2(D)). Note that the low-resistance source region 408a and the low-resistance drain region 4 08b and a resist for forming the source electrode layer 409a and the drain electrode layer 409b. The resist mask may be formed by an inkjet method. This eliminates the need for a photomask, thereby reducing manufacturing costs.

[0112] In this etching process, the oxide semiconductor layer 431 and the oxide semiconductor layer 4 It is preferable to set the etching conditions appropriately so that 32 is not etched. For example, the etching time may be controlled.

[0113] In addition, the materials for the oxide semiconductor layers 431 and 432 and the oxide conductive layers 406 and It is preferable to use materials having a high etching selectivity as the materials constituting 407. For example, the oxide semiconductor layers 431 and 432 may be formed of a metal containing Sn. Oxide materials (e.g. SnZnO x (x>0), or SnGaZnO x (x>0, etc.) The oxide conductive layers 406 and 407 are made of Al-Zn-O-based materials, Al -Zn-ON-based materials, Zn-O-based materials, etc. can be used. The material to be used can be etched, for example, using an alkaline solution. Materials containing aluminum, such as l-Zn-O and Al-Zn-ON materials, are used. In this case, the oxide conductive layer is removed together with the resist mask used for etching. It is preferable to remove the resist mask using a method that does not easily remove the resist mask. For example, a dry By removing the resist mask by etching, the oxide conductive layer is not removed and the resist The stamp mask can be removed.

[0114] Next, the oxide insulating layer 4 in contact with the exposed surfaces of the oxide semiconductor layer 431 and the oxide semiconductor layer 432 is Form 16.

[0115] The oxide insulating layer 416 has a thickness of at least 1 nm and is formed by an oxide insulating method such as a sputtering method. The insulating layer 416 can be formed by using an appropriate method that does not allow impurities such as water and hydrogen to be mixed in. In this embodiment, a silicon oxide film having a thickness of 300 nm is formed by sputtering. The oxide insulating layer 416 is formed by the above-mentioned method. The substrate temperature during the film formation is set to room temperature or higher and 300° C. In this embodiment, the temperature is set to 100° C. The deposition is carried out under a rare gas (typically argon) atmosphere, an oxygen atmosphere, or a rare gas (typically The target can be formed in an atmosphere of argon and oxygen. A silicon oxide target or a silicon target can be used. For example, a silicon target A silicon oxide film is formed by sputtering in an oxygen and nitrogen atmosphere using the above. The oxide insulating layer 416 in contact with the low-resistance oxide semiconductor layers 431 and 432 Examples include water, hydrogen ions, and OH - It does not contain impurities such as The insulating film is typically a silicon oxide film or a silicon nitride oxide film. The insulating film is formed using an aluminum oxide film, an aluminum oxynitride film, or the like. The nitride insulating layer 416 is formed using a silicon target material doped with boron. By using a silicon oxide film, impurities (water, hydrogen ions, OH - Invasion of This can suppress the inflow of

[0116] Next, a second heat treatment (preferably 200 ℃ or higher and 400 ℃ or lower, for example, 250 ℃ or higher and 350 ℃ or lower). For example, in a nitrogen atmosphere The second heat treatment is performed at 250° C. for 1 hour. The oxide semiconductor layer 431 and part of the oxide semiconductor layer 432 are heated while in contact with the oxide insulating layer 416. .

[0117] Through the above steps, the resistance of the oxide semiconductor layers 431 and 432 is reduced, and the oxide A part of the semiconductor layers 431 and 432 is selectively made to have an excess of oxygen. The channel forming region 413 overlapping the electrode layer 411 is I-shaped, and the channel forming region 413 overlapping the gate electrode layer 421 is I-shaped. The channel formation region 423 is an i-type oxide semiconductor layer overlapping the source electrode layer 415a. A high resistance source region 414a is formed in a self-aligned manner in the layer 431, and a drain electrode layer 4 A high-resistance drain region 414b is formed in a self-aligned manner in a portion of the oxide semiconductor layer 431 overlapping with the drain region 15b. A high-resistance source is formed in a portion of the oxide semiconductor layer 432 that overlaps with the source electrode layer 409a. The region 424a is formed in a self-aligned manner, and the oxide semiconductor layer 424b overlaps the drain electrode layer 409b. A high-resistance drain region 424b is formed in a self-aligned manner in the portion 432 (see FIG. 2(E)). ).

[0118] In addition, the oxide overlapping the low-resistance drain region 408b (and the low-resistance source region 408a) In the semiconductor layer 431, the high-resistance drain region 414b (or the high-resistance source region 414a) By forming a high resistance layer, the reliability of the driving circuit can be improved. By forming the anti-drain region 414b, the transistor is The conductivity is gradually changed from the high resistance drain region 414b to the channel formation region 413. Therefore, the drain electrode layer can be connected to a high power supply potential VD When the transistor is operated by electrically connecting the gate electrode layer 41 to a wiring that supplies D, Even if a high electric field is applied between the drain electrode layer 415b and the high resistance drain region 414b (or the high resistance source region 414a) acts as a buffer to prevent localized electric field concentration, This can improve the dielectric strength of the transistor.

[0119] In addition, the oxide layer overlapping the low-resistance drain region 408b (and the low-resistance source region 408a) In the semiconductor layer 431, the high-resistance drain region 414b (or the high-resistance source region 414a) By forming the transistor, the leakage current of the driver circuit can be reduced. can.

[0120] In addition, the oxide semiconductor layer overlapping with the drain electrode layer 409b (and the source electrode layer 409a) In step 432, a high-resistance drain region 424b (or a high-resistance source region 424a) is formed. By this, the reliability of the pixel can be improved. By forming the region 424b, the transistor is connected to the drain electrode layer 409b via a high resistance drain. The conductivity can be changed stepwise from the in-region 424b to the channel formation region 423. Therefore, the drain electrode layer 409b is connected to a high power supply potential VDD. When the transistor is operated by electrically connecting to a supply wiring, the gate electrode layer 421 and Even if a high electric field is applied between the drain electrode layer 409b and the high resistance drain region 424b, the high resistance drain region 424b is This acts as a buffer to prevent localized electric field concentration, improving the dielectric strength of the transistor. Cut.

[0121] In addition, the oxide semiconductor layer overlapping with the drain electrode layer 409b (and the source electrode layer 409a) In step 432, a high-resistance drain region 424b (or a high-resistance source region 424a) is formed. This makes it possible to reduce leakage current of the transistor in the pixel.

[0122] Note that in the semiconductor device of this embodiment, a protective insulating layer is provided over the oxide insulating layer 416. In the case where a protective insulating layer is provided, an RF sputtering method is used in this embodiment mode. It is preferable to form a protective insulating layer by forming a silicon nitride film using RF sputtering. The ring method is suitable for mass production and is therefore preferred as a method for forming the protective insulating layer. Water, hydrogen ions, and OH - It does not contain impurities such as these, and prevents them from entering from the outside. A blocking inorganic insulating film is used, for example, a silicon nitride film, an aluminum nitride film, a silicon oxynitride film, Of course, the protective insulating layer is a light-transmitting insulating film. It is.

[0123] Next, a fifth photolithography step is performed to form a resist mask, and an oxide insulating layer 4 16 is etched to expose a region 418 of the low-resistance source region 408a. , a region 419 where a part of the low-resistance drain region 408b is exposed, and the drain electrode layer 409 b, a contact hole 426 is formed so that the oxide insulating layer 416 is in contact with the oxide semiconductor layer 43 1, as well as the periphery and the periphery of the low-resistance source region 408a and the low-resistance drain region 408b. A structure that contacts the side surface is formed (see FIG. 3(A)). Note that the resist mask here is If the resist mask is formed by the inkjet method, the photoresist can be formed by the inkjet method. Since no mask is used, manufacturing costs can be reduced.

[0124] Next, after removing the resist mask, at least the exposed low-resistance source region 408a and A conductive film is formed on the low-resistance drain region 408b and the oxide insulating layer 416. Resist masks 438a and 438b are formed on the conductive film by a photolithography process. The conductive film is selectively etched to form the source electrode layer 415a and the drain electrode layer 415b. (See Figure 3(B)).

[0125] As a material for the conductive film for forming the source electrode layer 415a and the drain electrode layer 415b, is an element selected from Al, Cr, Cu, Ta, Ti, Mo, and W, or a combination of the above elements. There are alloys that contain only one of the above elements, or alloys that combine the above elements.

[0126] The conductive film may be a titanium film, an aluminum film provided on the titanium film, and a conductive film formed on the aluminum film. A three-layer laminate film of a titanium film provided on a molybdenum film, or a molybdenum film, A three-layer structure of an aluminum film and a molybdenum film formed on the aluminum film. It is preferable to use a laminated film. Of course, the metal conductive film may be a single layer film, a two-layer laminate film, or a four-layer laminate film. A laminated film of more than one layer may be used. When a laminated conductive film of titanium is used, etching is performed by dry etching using chlorine gas. It is possible.

[0127] A resist mask for forming a conductive layer may be formed by an ink-jet method. When a resist mask is formed using the inkjet method, no photomask is used, so manufacturing costs are reduced. This can reduce the

[0128] Next, the planarization insulating layer 404 is formed over the oxide insulating layer 416. Examples include polyimide, acrylic resin, benzocyclobutene resin, polyamide, and epoxy resin. In addition to the above organic materials, organic materials having low dielectric constant can be used. Dielectric constant material (low-k material), siloxane resin, PSG (phosphorus glass), BPSG (phosphorus The planarization insulating layer 404 may be made of a material such as boron nitride glass. The planarization insulating layer 404 may be formed by stacking a plurality of insulating films made of the same material.

[0129] The siloxane-based resin is a Si-O- formed material that is formed from a siloxane-based material. It corresponds to a resin containing Si bonds. In addition, siloxane resins have organic groups (e.g. For example, an alkyl group or an aryl group, or a fluoro group may be used.

[0043]

[0130] The method for forming the planarization insulating layer 404 is not particularly limited. Depending on the material, it may be formed by sputtering. coating method, SOG method, spin coating, dip coating, spray coating, droplet ejection method (ink jet printing, screen printing, offset printing, etc.), doctor knife, roll coater, car Tools such as a ten coater or a knife coater can be used.

[0131] Next, a seventh photolithography step is performed to form a resist mask and a planarization insulating layer 4 A contact hole 441 reaching the drain electrode layer 409b is formed by etching in step 04. (See FIG. 3C). Note that the gate electrode layers 411 and 421 are etched. A contact hole reaching the drain electrode layer 409b is also formed. A resist mask for forming the through holes 441 may be formed by an ink-jet method. When a resist mask is formed using the inkjet method, no photomask is used, so manufacturing costs are reduced. This can reduce costs.

[0132] Next, after removing the resist mask, a light-transmitting conductive film is formed. Indium (In 2 O 3 ) film and indium tin oxide alloy (In 2 O 3 - SnO 2 , IT O) film is formed by sputtering or vacuum deposition. A light-transmitting conductive film is formed. As the light-transmitting conductive film, an Al- Zn-O non-single crystal film, i.e. Al-Zn-ON non-single crystal film and Zn-ON non-single crystal film Alternatively, a single crystal film or a Sn-Zn-ON non-single crystal film may be used. The composition ratio (atomic %) of zinc in the non-single crystal film is set to 47 atomic % or less, and the aluminum in the non-single crystal film is set to 1. The composition ratio (atomic percent) of aluminum in the Al-Zn-ON non-single crystal film is larger than that of aluminum. The composition ratio (atomic %) of nitrogen in the Al-Zn-ON non-single crystal film is The etching process for films of such materials is carried out using hydrochloric acid based solutions. In addition, since etching of ITO film is prone to leaving residue, Indium oxide zinc oxide alloy (In 2 O 3 -ZnO) may also be used.

[0133] The composition ratio of the light-transmitting conductive film is expressed in atomic percent. (EPMA:Electron Probe X-ray MicroAnalyzer ) is used to evaluate the composition ratio of the light-transmitting conductive film.

[0134] Next, an eighth photolithography step is performed to form a resist mask and to form a The pixel electrode layer 427 and the conductive layer 417 are formed by removing unnecessary portions of the conductive film having a light-transmitting property. Then, the resist mask is removed (see FIG. 3(D)).

[0135] Through the above steps, the thin film transistor 410 and the thin film transistor 420 are formed on the same substrate using eight masks. The film transistor 420 can be fabricated separately for the driver circuit or pixel portion. Therefore, the manufacturing cost can be reduced compared to the case where the pixel section and the driver circuit are manufactured in separate processes. The thin film transistor 410 for the driving circuit is a high resistance source. The oxide semiconductor layer 414 includes a high-resistance drain region 414b and a channel forming region 413. The thin film transistor is a pixel transistor including a semiconductor layer 412. The transistor 420 includes a high-resistance source region 424a, a high-resistance drain region 424b, and a channel region 424c. The thin film transistor includes an oxide semiconductor layer 422 having a panel formation region 423. The transistor 410 and the thin film transistor 420 have a high resistance source even when a high electric field is applied. region 414a, high-resistance drain region 414b, high-resistance source region 424a, and high-resistance The drain region 424b acts as a buffer to prevent localized electric field concentration, improving the dielectric strength of the transistor. It is designed to improve pressure.

[0136] In the method for manufacturing the semiconductor device shown in FIGS. 2 and 3, the gate insulating layer 402 is used as a dielectric. The storage capacitor formed by the capacitance wiring and the capacitance electrode (also called the capacitance electrode layer) is also a thin-film transistor. The thin film transistor 410 and the thin film transistor 420 can be formed on the same substrate. The pixel section is composed of a matrix of resistors 420 and storage capacitors corresponding to each pixel. By disposing a driver circuit having a thin film transistor 410 around the pixel portion, The present invention can be used as one of the substrates for manufacturing a display device of a positive matrix type. For convenience, such a substrate is called an active matrix substrate.

[0137] The pixel electrode layer 427 is formed through a contact hole 441 and a contact hole 442 formed in the planarization insulating layer 404. The oxide insulating layer 416 is electrically connected to the capacitor electrode layer through a contact hole 426 formed therein. A number of contact holes are formed to electrically connect the lower electrode layer and the upper electrode layer. By connecting the layers together, contact holes can be easily formed even if the insulating layer is made thick. Therefore, contact failure can be suppressed. 9a and the drain electrode layer 409b can be formed using the same material and in the same process.

[0138] In addition, the conductive layer 417 is provided so as to overlap with the channel formation region 413 of the oxide semiconductor layer. This is a bias-thermal stress test (hereafter referred to as "stress test") to check the reliability of thin-film transistors. In the test, the threshold voltage of the thin film transistor 410 before and after the BT test is In addition, the conductive layer 417 has a potential that is different from that of the gate electrode layer 41. 1 or different and can also function as a gate electrode layer. The conductive layer 417 is in a GND state, a state in which a potential of 0V is applied, or a floating state. The device may be in a locking state.

[0139] In addition, a resist mask for forming the conductive layer 417 and the pixel electrode layer 427 is formed by ink jet printing. If the resist mask is formed by the ink-jet method, the photomask Since no additional heat is used, the manufacturing cost can be reduced.

[0140] (Embodiment 2) In this embodiment mode, an example in which the first heat treatment is different from that in Embodiment Mode 1 is shown in FIG. Since this is the same as 3 except for some differences in the process, the same symbols are used for the same parts and A detailed description will be omitted.

[0141] 4A to 4C are cross-sectional views showing a manufacturing process of two thin film transistors.

[0142] First, a gate electrode is formed on a substrate 400 having an insulating surface according to the manufacturing process shown in the first embodiment. The pole layers 411 and 421 are formed.

[0143] Next, the gate insulating layer 402 is formed on the gate electrode layers 411 and 421 .

[0144] Next, an oxide semiconductor film 430 having a thickness of 2 nm to 200 nm is formed over the gate insulating layer 402. (See FIG. 4(A)). The steps up to this point are the same as those in the first embodiment. ,Figure 4(A) corresponds to Figure 2(A).

[0145] Next, the oxide semiconductor film 480 is dehydrated or oxidized under an inert gas atmosphere or reduced pressure. The temperature of the first heat treatment for dehydration or dehydrogenation is 350° C. or higher. The temperature is set to be lower than the distortion point of the substrate, preferably 400° C. or higher. The substrate is placed in an electric furnace, and the oxide semiconductor film is subjected to heat treatment in a nitrogen atmosphere. After that, the oxide semiconductor film is not exposed to the air, and water and hydrogen are prevented from re-mixing into the oxide semiconductor film. The membrane is made oxygen-deficient to reduce resistance, i.e., N-type (N - After that, in the same furnace, High purity oxygen gas or high purity N 2 O2 gas or ultra-dry air (dew point below -40℃) Cooling is performed by introducing oxygen gas or N 2 O gas, water, It is preferable that hydrogen and the like are not included. Alternatively, oxygen gas or N 2 The purity of O gas is 6N (99.9999%) or more, preferably 7N (99.9999%). 9%) or more (i.e. oxygen gas or N 2 The impurity concentration in the O gas is preferably 1 ppm or less. It is preferable that the concentration of the ion exchange resin is 0.1 ppm or less.

[0146] After the first heat treatment for dehydration or dehydrogenation, the temperature is preferably 200° C. or higher and 400° C. or lower. or in an oxygen gas atmosphere at a temperature between 200°C and 300°C, or in an N 2 Under O gas atmosphere Or heating in an ultra-dry air atmosphere (dew point below -40°C, preferably below -60°C) Processing may be carried out.

[0147] By carrying out the above steps, the entire oxide semiconductor film 430 is made to have an oxygen excess state. Then, the oxide semiconductor film 434 is formed by making the oxide semiconductor film 434 have a high resistance, that is, an i-type oxide semiconductor film (see FIG. 4B). As a result, the reliability of the thin film transistor to be formed later can be improved.

[0148] Note that in this embodiment, an example in which dehydration or dehydrogenation is performed after the oxide semiconductor film is formed is described. However, the present invention is not limited to this embodiment. In the first heat treatment, an island-shaped oxide semiconductor It can also be carried out after processing into layers.

[0149] In addition, the oxide semiconductor film is dehydrated or dehydrogenated under an inert gas atmosphere. After cooling under a reactive gas atmosphere, a resist mask is formed by a photolithography process. The oxide semiconductor film 434 is selectively etched using the resist mask, An island-shaped oxide semiconductor layer is formed, and then the oxide semiconductor layer is heated at 200° C. or higher and 400° C. or lower. , preferably at a temperature of 200°C to 300°C in an oxygen gas atmosphere, 2 Under O gas atmosphere or in an ultra-dry air atmosphere (dew point is -40°C or less, preferably -60°C or less), The theory may also be carried out.

[0150] In addition, before the oxide semiconductor film 434 is formed, an inert gas atmosphere (nitrogen, helium, or neodymium) is In an oxygen atmosphere or ultra-dry air (dew point below -40°C, preferably - 60℃ or less) atmosphere (400℃ or more but below the distortion point of the substrate), and Impurities such as hydrogen and water contained in the insulating layer may be removed.

[0151] Next, the oxide semiconductor film 434 is subjected to a second photolithography process. A resist mask is formed over the oxide semiconductor film 434 using the resist mask. By selectively etching, the oxide semiconductor layer 443, which is an island-shaped oxide semiconductor layer, Form 445.

[0152] After that, the resist mask is removed, and the structure is formed as shown in FIG. 2(C), FIG. 2(D), FIG. 2(E), As in FIG. 3A, FIG. 3B, and FIG. 3C, the low resistance The source region 408a and the low-resistance drain region 408b are formed. The top surface, and the periphery and side surfaces of the low-resistance source region 408a and the low-resistance drain region 408b. On the other hand, in the pixel portion, the oxide insulating layer 416 is formed in contact with the oxide semiconductor layer 44. 5, the source electrode layer 409a and the drain electrode layer 409, which are light-transmitting conductive layers, are in contact with the Then, the oxide insulating layer 416 in contact with the oxide semiconductor layer 445 is formed.

[0153] Next, a second heat treatment is performed in an inert gas atmosphere or an oxygen gas atmosphere. The treatment conditions are the same as those in the manufacturing method of the semiconductor device shown in Embodiment 1. For example, a second heat treatment is performed at 250° C. for 1 hour in a nitrogen atmosphere.

[0154] Next, a part of the low-resistance source region 408a and the low-resistance drain region 408b are exposed, and an oxide A contact hole is formed in the nitride insulating layer 416, reaching the drain electrode layer 409b. Then, a conductive film is formed over the oxide insulating layer 416, and the conductive film is selectively etched to form a low-resistance semiconductor layer. A source electrode layer 415a contacting the source region 408a and a low-resistance drain region 408b contacting the source electrode layer 415b are formed on the low-resistance drain region 408b. The drain electrode layer 415b is formed. Next, a planarization insulating layer 416 is formed in contact with the oxide insulating layer 416. 4, a contact hole is formed in the planarization insulating layer 404, the contact hole reaching the drain electrode layer 409b. A light-transmitting conductive film is formed over the contact holes and the planarization insulating layer 404. The light-transmitting conductive film is selectively etched to electrically connect the drain electrode layer 409b to the drain electrode layer 409b. A pixel electrode layer 427 and a conductive layer 417 to be connected are formed (see FIG. 4C).

[0155] Through the above steps, the entire oxide semiconductor layer was formed on the same substrate using eight masks. A thin film transistor 449 and a thin film transistor 451 are connected to a driver circuit or a pixel circuit. The thin film transistor 449 for the driver circuit is an I-type transistor. The thin film transistor is a thin film transistor for a pixel including an oxide semiconductor layer 443. The thin film transistor 451 also includes an oxide semiconductor layer 445 whose entire structure is i-type.

[0156] In addition, the gate insulating layer 402 serves as a dielectric, and the storage capacitor formed by the capacitance wiring and the capacitance electrode also The thin film transistor 449 and the thin film transistor 451 can be formed over the same substrate. The thin film transistors 451 and storage capacitors are arranged in a matrix in correspondence with each pixel. A pixel portion is formed, and a driver circuit having a thin film transistor 449 is arranged around the pixel portion. This makes it possible to fabricate one of the substrates for an active matrix display device. Cut.

[0157] In addition, the conductive layer 417 is provided so as to overlap with a channel formation region of the oxide semiconductor layer 443. As a result, in the BT test, the threshold voltage of the thin film transistor 449 before and after the BT test was In addition, the conductive layer 417 has a potential that is different from that of the gate electrode layer 4. 11 may be the same as or different from the gate electrode layer. The conductive layer 417 is in a GND state, a state in which a potential of 0V is applied, or a floating state. The device may be in a ring state.

[0158] (Embodiment 3) A method for manufacturing a semiconductor device different from that in the first embodiment will be described with reference to FIG. A part or a part having a similar function and a process can be performed in the same manner as in the first embodiment. , and a repeated explanation will be omitted.

[0159] 5A to 5C are cross-sectional views showing a manufacturing process of two thin film transistors.

[0160] First, as in FIG. 2(A) of the first embodiment, a gate electrode layer is formed on a substrate 400 having an insulating surface. 411, a gate electrode layer 421 is formed, and a gate electrode layer 421 is formed on the gate electrode layer 411 and the gate electrode layer 421. A gate insulating layer 402 is formed, and an oxide semiconductor film 430 is formed over the gate insulating layer 402. (See FIG. 5(A)).

[0161] Next, a resist mask is formed on the oxide semiconductor film 430 by a second photolithography process. The oxide semiconductor film 430 is selectively etched using the resist mask. In this manner, an island-shaped oxide semiconductor layer is formed.

[0162] Next, the resist mask is removed, and the first heat treatment is carried out in the same manner as in FIG. 2(B) of the first embodiment. The oxide semiconductor layer is dehydrated or dehydrogenated by the first treatment. The conditions for the heat treatment are the same as those for the manufacturing method of the semiconductor device described in Embodiment 1. Here, an oxide semiconductor layer is formed in an electric furnace, which is one type of heat treatment device. The oxide semiconductor layer was subjected to heat treatment in a nitrogen atmosphere. The oxide semiconductor layer 4 is formed without contact with the air, preventing the re-incorporation of water and hydrogen into the oxide semiconductor layer. 31, 432 is obtained (see FIG. 5(B)).

[0163] Next, an oxide conductive film is formed over the oxide semiconductor layers 431 and 432 and the gate insulating layer 402. After that, resist masks 445a and 445b are formed by a third photolithography process. Then, the resist masks 445a and 445b are used to selectively etch the , a low-resistance source region 408a, a low-resistance drain region 408b, a source electrode layer 409a, and A drain electrode layer 409b is formed (see FIG. 5C). The same materials as those in the first embodiment can be used.

[0164] In this etching process, the oxide semiconductor layer 431 and the oxide semiconductor layer 4 It is preferable that 32 is not etched. In order to prevent etching, the etching conditions are For example, the etching time may be controlled.

[0165] In addition, the materials constituting the oxide semiconductor layers 431 and 432 and the low-resistance source region 408a A low-resistance drain region 408b, a source electrode layer 409a, and a drain electrode layer 409b are formed. It is preferable to use materials having a high etching selectivity for each of the layers. For example, a metal oxide material containing Sn (e.g., SnZn Ox(x>0) or SnGaZnO x (x>0, etc.) to form an oxide conductive layer. Examples of materials that can be used include Al-Zn-O, Al-Zn-ON, and Zn-O materials. Such a material containing zinc oxide as a main component can be used, for example, by using an alkaline solution. In addition, Al-Zn-O and Al-Zn-ON materials can be etched. When using materials that contain aluminum, such as aluminum alloys, the resist used for etching The resist mask is removed by a method in which the oxide conductive layer is not removed together with the mask. For example, the resist mask is preferably removed by dry etching. In this manner, the resist mask can be removed without removing the oxide conductive layer.

[0166] The oxide semiconductor layer preferably has a thickness of 50 nm or less in order to maintain an amorphous state. For example, the average thickness of the final thin-film transistor is set to 5 nm or more and 20 nm or less. It is preferable that

[0167] Next, similarly to FIG. 2E of the first embodiment, the oxide semiconductor layer 431 and the oxide semiconductor layer 4 The oxide insulating layer 416 is formed in contact with the gate electrode layer 411. A channel forming region 413 overlapping with the gate electrode layer 421 is made to be an I-type. The region 423 is I-shaped, and the high-resistance source region 414a overlapping the low-resistance source region 408a is A high-resistance drain region 414 formed in a self-aligned manner and overlapping the low-resistance drain region 408b. b is formed in a self-aligned manner, and a high resistance source region 424a overlapping the source electrode layer 409a is formed. A high-resistance drain region 424b is formed in a self-aligned manner and overlaps the drain electrode layer 409b. The second heat treatment is performed in a self-aligned manner. The same conditions as in the fabrication method of the device can be used.

[0168] Next, a fourth photolithography process is performed in the same manner as in FIG. 3(A) of the first embodiment to form a resist pattern. A mask is formed and the oxide insulating layer 416 is etched to form a low-resistance source region. A region 418 in which a portion of the low-resistance drain region 408a is exposed and a region 418 in which a portion of the low-resistance drain region 408b is exposed A contact hole 426 is formed on the contact region 419 and the drain electrode layer 409b. The oxide insulating layer 416 is formed on a part of the oxide semiconductor layer 431 and the low-resistance source region 408a. And it has a structure in contact with the periphery and side surfaces of the low-resistance drain region 408b.

[0169] Next, similarly to FIG. 3(B) of the first embodiment, the resist mask is removed, and then at least the exposed On the exposed low-resistance source region 408a and low-resistance drain region 408b, contact holes A conductive film is formed over the oxide insulating layer 426 and the oxide insulating layer 416, and a fifth photolithography process is performed. Then, resist masks 438a and 438b are formed on the conductive film by selective etching. A source electrode layer 415a and a drain electrode layer 415b are formed by performing a process.

[0170] Next, similarly to FIG. 3C of the first embodiment, the resist masks 438a and 438b are removed. Then, the source electrode layer 415a, the drain electrode layer 415b, and the oxide insulating layer 416 are A planarization insulating layer 404 is formed on the insulating film 402, and a sixth photolithography step is performed. The planarization insulating layer 404 is then etched to form a contact that reaches the drain electrode layer 409b. A contact hole 441 is formed.

[0171] Next, after forming a contact hole in the same manner as in FIG. 3(D) of the first embodiment, a light-transmitting A conductive film is formed, a seventh photolithography step is performed, a resist mask is formed, and an etching process is performed. Unnecessary portions are removed by etching to form a pixel electrode layer 427 and a conductive layer 417 .

[0172] Through the above steps, the thin film transistor 410 and the thin film transistor 420 are formed on the same substrate using seven masks. The film transistor 420 can be separately manufactured for the driver circuit or pixel portion, In addition, the number of masks can be reduced compared to the manufacturing process of the first embodiment. The transistor 410 includes a high-resistance source region 414a, a high-resistance drain region 414b, and a channel region 414c. A thin film transistor including an oxide semiconductor layer 412 having a panel formation region 413, The thin film transistor 420 has a high resistance source region 424a and a high resistance drain region 424b. b, and a thin film transistor including an oxide semiconductor layer 422 having a channel formation region 423. The thin film transistor 410 and the thin film transistor 420 are High-resistance source region 414a, high-resistance drain region 414b, high-resistance source region 424a, In addition, the high-resistance drain region 424b acts as a buffer to prevent localized electric field concentration, This configuration improves the dielectric strength voltage of the stator.

[0173] (Embodiment 4) A semiconductor device and a manufacturing method of the semiconductor device different from those in Embodiment 1 will be described with reference to FIGS. Figure 38(B) and (C) show two thin films with different structures fabricated on the same substrate. An example of a cross-sectional structure of a transistor is shown in FIG. The transistor 470 is a transistor with a bottom gate structure.

[0174] FIG. 38(A1) is a plan view of a thin film transistor 460 disposed in a driving circuit. FIG. 38(A2) is a plan view of a thin film transistor 470 disposed in a pixel, and FIG. The cross-sectional structure along the line G1-G2 in FIG. 38(A1) and the cross-sectional structure along the line H1-H2 in FIG. FIG. 38(C) is a cross-sectional view showing a cross-sectional structure in the state shown in FIG. 38(A1). 4 and a cross-sectional structure taken along line H3-H4 in FIG. 38(A2). be.

[0175] The thin film transistor 460 disposed in the driving circuit is formed on a substrate 450 having an insulating surface. A gate electrode layer 461, a gate insulating layer 452, at least a channel forming region 463, and a high resistance so The oxide semiconductor layer 462 includes a source region 464a and a high-resistance drain region 464b. The low-resistance source region 446a, the low-resistance drain region 446b, the source electrode layer 465a, and the drain The thin film transistor 460 also includes a drain electrode layer 465b. 6a and the periphery and side surface of the low-resistance drain region 446b, and part of the oxide semiconductor layer 462 In this structure, an oxide insulating layer 466 is provided in contact with the insulating portion.

[0176] The high-resistance source region 464a is in contact with the lower surface of the low-resistance source region 446a in a self-aligned manner. The high-resistance drain region 464b is formed in a substantially uniform manner. The channel forming region 463 is formed in a self-aligned manner in contact with the bottom surface of the semiconductor substrate 462. The high-resistance source region 464a and the high-resistance drain region 464b are in contact with the insulating layer 466. The region is also a high resistance region (I-type region).

[0177] The source electrode layer 465a is in contact with the low-resistance source region 446a, and the drain electrode layer 465b is in contact with the low-resistance source region 446a. , contacting the low-resistance drain region 446b.

[0178] The thin film transistor 460 also includes a low-resistance source region 446a and a low-resistance drain region 44 By providing 6b, the operation is more stable thermally than in the case of a Schottky junction. As shown in FIG. 1, the low-resistance source region and the low-resistance drain region have a higher carrier concentration than the oxide semiconductor layer. An ohmic contact is formed by intentionally providing a contact region.

[0179] In order to reduce the resistance of the wiring of the thin film transistor 460, the source electrode layer 465a and the drain electrode layer 465b are It is preferable to use a metal material for the rain electrode layer 465b.

[0180] A conductive layer 467 overlapping the channel formation region 463 is formed above the channel formation region 463. The conductive layer 467 is electrically connected to the gate electrode layer 461 and has the same potential. The oxide semiconductor layer 462 disposed between the gate electrode layer 461 and the conductive layer 467 is provided with gate electrodes from above and below. In addition, the gate electrode layer 461 and the conductive layer 467 can be set to different potentials. For example, when the potential is a fixed potential, GND potential, or 0V, the electrical characteristics of the TFT, for example, the threshold That is, the gate electrode layer 461 and the conductive layer 467 can be controlled. One of the layers functions as a first gate electrode layer, and the other of the gate electrode layer 461 and the conductive layer 467 functions as a second gate electrode layer. As a result, the thin film transistor 460 is a four-terminal thin film transistor. It can be used as a transistor.

[0181] In addition, the conductive layer 467, the source electrode layer 465a, the drain electrode layer 465b, and the oxide insulating layer Between the border layers 466 a planarizing insulating layer 454 is deposited.

[0182] The thin film transistor 470 disposed in the pixel is formed on a substrate 450 having an insulating surface, and has a gate An electrode layer 471, a gate insulating layer 452, at least a channel forming region 473, a high resistance source The oxide semiconductor layer 472 having the region 474a and the high-resistance drain region 474b, The gate electrode layer 447 includes a drain electrode layer 447a, and a drain electrode layer 447b.

[0183] The high-resistance source region 474a is in contact with the lower surface of the source electrode layer 447a in a self-aligned manner. The high-resistance drain region 474b is formed on the lower surface of the drain electrode layer 447b. The channel formation region 473 is formed in a self-aligned manner in contact with the oxide insulating layer. 466 and has a higher resistance than the high-resistance source region 474a and the high-resistance drain region 474b. The region is called the anti-type I region.

[0184] Note that the oxide semiconductor layer 462 is formed under the source electrode layer 465a and the drain electrode layer 465b. The oxide semiconductor layer 462 is formed on the gate electrode layer 461 and partially overlaps with the gate electrode layer 461. The gate electrode layer 461 overlaps the gate insulating layer 452. The oxide semiconductor layer 472 is provided under the oxide semiconductor layer 472 with the edge layer 452 interposed therebetween. The insulating layer 447 is formed below and partially overlaps with the source electrode layer 447a and the drain electrode layer 447b. The oxide semiconductor layer 472 is formed by interposing the gate electrode layer 471 and the gate insulating layer 452 therebetween. That is, the gate electrode layer 471 is connected to the oxide semiconductor layer 452 via the gate insulating layer 452. It is provided under the conductor layer 472 .

[0185] In order to realize a display device having a high aperture ratio, the source electrode layer of the thin film transistor 470 The drain electrode layer 447a and the drain electrode layer 447b are formed using a light-transmitting conductive film.

[0186] In addition, a gate electrode layer 471 of the thin film transistor 470 is also formed using a light-transmitting conductive film. It is done.

[0187] In addition, in the pixel in which the thin film transistor 470 is disposed, the pixel electrode layer 477 and other The electrode layer (capacitor electrode layer, etc.) and the wiring layer (capacitor wiring layer, etc.) are transparent to visible light. By forming the display device using a conductive film having a high aperture ratio, a display device having a high aperture ratio can be realized. The gate insulating layer 452 and the oxide insulating layer 466 are also formed using a film that transmits visible light. is preferred.

[0188] The pixel electrode layer 477 is formed by contacting the opening in the oxide insulating layer 466 and the planarization insulating layer 454. The oxide insulating layer 466 is in contact with the drain electrode layer 447b through the opening. The opening provided in the is not necessarily required.

[0189] Note that the oxide semiconductor layer 462 and the oxide semiconductor layer 472 are each a semiconductor film having a thickness of at least 100 nm. Heat treatment to reduce impurities such as moisture after film formation (heat treatment for dehydration or dehydrogenation) After heat treatment for dehydration or dehydrogenation and slow cooling, the oxide semiconductor is The carrier concentration of the oxide semiconductor layer is reduced by forming an oxide insulating film in contact with the semiconductor layer. This leads to improved electrical characteristics and reliability of the thin film transistor 460 and the thin film transistor 470. It leads to improved sexuality.

[0190] In the semiconductor device shown in FIG. 38, a thin film transistor 460 and a thin film transistor The channel length of the transistor 470 is the same, but not limited to this. The transistors are required to operate faster than the thin-film transistors in the pixel area, so The channel length of the thin film transistor 460 may be narrower than the channel length of the thin film transistor 470. At this time, for example, the channel length of the thin film transistor 460 is about 1 μm to 5 μm. It is preferable that the channel length of the thin film transistor 470 is about 5 μm to 20 μm. is preferred.

[0191] As described above, the semiconductor device shown in FIG. 38 has a first thin film transistor on the same substrate. The pixel has a driver circuit and a second thin film transistor. The first thin film transistor is made of a light-transmitting material. The pixel portion is made of a material having a lower resistance than the material having an opening. The efficiency can be improved, and the operating speed of the drive circuit can be improved. By providing a driver circuit and a pixel portion on the same substrate, a wiring for connecting the driver circuit and the pixel portion is provided. The number of lines and the length of the wiring can be reduced, which contributes to the miniaturization and cost reduction of semiconductor devices. It is possible.

[0192] In addition, in the semiconductor device shown in FIG. 38, a source electrode layer in a thin film transistor of a driver circuit A low-resistance solenoid is provided between the drain electrode layer and the oxide semiconductor layer in which a channel formation region is formed. The structure has a low-resistance source region and a low-resistance drain region. By providing an in-region, it is possible to improve the frequency characteristics of the peripheral circuits (drive circuits). Compared with the contact between the metal electrode layer and the oxide semiconductor layer, the contact between the metal electrode layer and the low resistance source region and This is because contact with the low-resistance drain region can reduce the contact resistance. Electrode layers using molybdenum (e.g., stacking of molybdenum layer, aluminum layer, molybdenum layer, etc.) The contact resistance with the oxide semiconductor layer is high because molybdenum is less susceptible to oxidation than titanium. Therefore, the effect of extracting oxygen from the oxide semiconductor layer is weak, and the molybdenum layer and the oxide semiconductor layer However, the contact interface between the oxide semiconductor layer and the source electrode layer and the drain electrode layer does not become n-type. A low-resistance source region and a low-resistance drain region are interposed between the drain electrode layer and the contact. The resistance can be reduced, and the frequency characteristics of the peripheral circuits (drive circuits) can be improved. By providing a low resistance source region and a low resistance drain region, The channel length is determined during etching of the layers that will become the low resistance source and drain regions. Therefore, the channel length can be made shorter.

[0193] In the semiconductor device illustrated in FIG. 38, the end portion of the oxide semiconductor layer of the first thin film transistor is low. The second thin film transistor is provided with an oxide layer that protrudes from the ends of the resistive source region and the low-resistive drain region. The end of the nitride semiconductor layer protrudes beyond the ends of the source electrode layer and the drain electrode layer. .

[0194] In addition, the semiconductor device shown in FIG. 38 includes a driver circuit having a thin film transistor including an oxide semiconductor. a part of the oxide conductive layer, and a part of the oxide conductive layer in contact with the source electrode layer and the drain electrode layer; The oxide insulating layer is in contact with the side of the thin film transistor. The wiring in the same layer as the gate electrode layer and the wiring in the same layer as the source electrode and drain electrode are provided in the peripheral area. When the insulating layer is sandwiched between the gate electrode layer and the gate electrode layer, the insulating layer is formed on the same layer as the gate electrode layer. Since the distance between the wiring and the wiring in the same layer as the source electrode and the drain electrode can be increased, The parasitic capacitance can be reduced.

[0195] Furthermore, the transistor of this embodiment can also have a structure shown in FIG. 38B, the semiconductor device shown in FIG. 38B has a gate insulating layer including a plurality of insulating layers. The insulating layer is formed by laminating insulating layers, and has a protective insulating layer on the oxide insulating layer in contact with the semiconductor layer. That is, the semiconductor device shown in FIG. 42 differs from the semiconductor device shown in FIG. 38. The gate insulating layer 452a and the gate insulating layer 452b are stacked instead of the gate insulating layer 2. The structure has a protective insulating layer 453 on an oxide insulating layer 466. In the configuration of the semiconductor device, the parts common to the semiconductor device shown in FIG. The description of the conductor device will be used as appropriate and will not be repeated here.

[0196] The gate insulating layer 452a and the gate insulating layer 452b may be, for example, a gate insulating layer shown in FIG. Materials applicable to the edge layer 452 can be used, and the gate insulating layer 452a can be, for example, For example, a nitride insulating layer can be used as the gate insulating layer 452b, and for example, an oxide insulating layer can be used as the gate insulating layer 452c. A layer may be used.

[0197] The protective insulating layer 453 is a gate insulating layer 452a or a base insulating layer provided under the oxide insulating layer 466. It is preferable that the insulating film is in contact with the insulating film, which is a barrier against moisture and hydrogen ions from the side of the substrate. On and OH - In particular, the oxide insulating layer 466 It is effective to use a silicon nitride film for the gate insulating layer 452a in contact with the gate insulating layer 452 or a base insulating film. That is, when a silicon nitride layer is provided so as to surround the lower surface, the upper surface, and the side surfaces of the oxide semiconductor layer, the semiconductor The reliability of the body device is improved.

[0198] In the following, using Figs. 39(A) to (E) and Figs. 40(A) to (D), A manufacturing process of the transistor 460 and the thin film transistor 470 will be described.

[0199] First, a light-transmitting conductive film is formed on a substrate 450 having an insulating surface, and then a first photo A resist mask is formed on the conductive film by a lithography process, and the resist mask is used to By selectively etching the gate electrode layers 461 and 471, In the pixel portion, the same material as the gate electrode layers 461 and 471 is used, and the same first photolithography process is used. In addition, if capacitance is required not only for the pixel section but also for the driver circuit, A capacitance wiring is also formed in the driver circuit. The resist mask is formed by the ink-jet method. If the resist mask is formed by the inkjet method, a photomask is not required. This reduces manufacturing costs.

[0200] There is no significant limitation on the substrate that can be used for the substrate 450 having an insulating surface, but at least In any case, it is necessary for the insulating surface to have sufficient heat resistance to withstand subsequent heat treatment. The substrate 450 may be, for example, a glass substrate.

[0201] In addition, for glass substrates, if the temperature of the subsequent heat treatment is high, the distortion point is 730°C or higher. The glass substrate may be made of, for example, aluminosilicate glass, alumina glass, or the like. Glass materials such as lumino borosilicate glass and barium borosilicate glass are used. Compared to boric acid, it contains more barium oxide (BaO), making it more practical and heat-resistant. Glass is obtained. 2 O 3 It is possible to use a glass substrate containing more BaO. preferable.

[0202] Instead of the above glass substrate, the substrate 450 may be a ceramic substrate, a quartz substrate, or a surface treatment substrate. Alternatively, a substrate made of an insulator such as a fiber substrate may be used. For example, vitreous glass can be used.

[0203] In addition, an insulating film serving as a base film may be provided between the substrate 450 and the gate electrode layers 461 and 471. The undercoat film has a function of preventing the diffusion of impurity elements from the substrate 450. A film or a plurality of films selected from a silicon oxide film, a silicon nitride oxide film, and a silicon oxynitride film. The insulating film can be formed by laminating the above-mentioned films.

[0204] The gate electrode layers 461 and 471 can be formed of a conductive material that transmits visible light. For example, In-Sn-Zn-O, In-Al-Zn-O, Sn-Ga-Zn-O, A l-Ga-Zn-O series, Sn-Al-Zn-O series, In-Zn-O series, Sn-Zn-O series , Al-Zn-O, In-Sn-O, In-O, Sn-O, Zn-O conductivity Metal oxide can be used, and the thickness of the gate electrode layer 461, 471 is set to 50 nm or more. The conductive film used for the gate electrode layers 461 and 471 is formed by a method of forming the conductive film. Examples of deposition methods include sputtering, vacuum deposition (electron beam deposition, etc.), and arc discharge ion deposition. The plating method or spray method is used. When the sputtering method is used, Si O 2 The film is formed using a target containing 2% by weight or more and 10% by weight or less of The conductive film may contain SiOx (x>0) which inhibits crystallization. Prevents crystallization during the heat treatment for dehydration or dehydrogenation in the subsequent process. It is possible.

[0205] Next, the resist mask is removed, and the gate insulating layer 452 is formed over the gate electrode layer 461. .

[0206] The gate insulating layer 452 is a silicon oxide layer formed by using a plasma CVD method, a sputtering method, or the like. A silicon nitride layer, a silicon oxynitride layer, or a silicon nitride oxide layer is formed as a single layer or a laminated layer. For example, when forming a silicon oxynitride layer, the deposition gas is SiH 4 ,acid A silicon oxynitride layer may be formed by a plasma CVD method using silicon and nitrogen.

[0207] The thickness of the gate insulating layer 452 is set to 100 nm or more and 500 nm or less. For example, a first gate insulating layer having a thickness of 50 nm to 200 nm and a The second gate insulating layer has a thickness of 5 nm to 300 nm.

[0208] In this embodiment, a silicon nitride layer having a thickness of 200 nm or less is formed by plasma CVD. This is referred to as insulating layer 452.

[0209] Next, an oxide semiconductor film 480 with a thickness of 2 nm to 200 nm is formed over the gate insulating layer 452. After the oxide semiconductor film 480 is formed, the oxide semiconductor film 480 is dehydrated or dehydrogenated. Even if the heat treatment for the above-mentioned step is performed, the oxide semiconductor layer to be formed later is kept in an amorphous state. In particular, the thickness of the oxide semiconductor film 480 is preferably as thin as 50 nm or less. In this way, when heat treatment is performed after the formation of the oxide semiconductor film 480, the oxide semiconductor film This can prevent the conductor layer from being crystallized.

[0210] Note that before the oxide semiconductor film 480 is formed by a sputtering method, argon gas is introduced. The reverse sputtering is performed by introducing the silicon into the gate insulating layer 452 to generate plasma. It is preferable to remove the dust that is generated by the sputtering. In an argon atmosphere, a voltage is applied to the substrate side using an RF power supply to form plasma near the substrate. In addition, nitrogen, helium, oxygen, etc. can be used instead of argon atmosphere. Either may be used.

[0211] The oxide semiconductor film 480 is an In—Ga—Zn—O-based non-single-crystal film or an In—Sn—Zn— O-based, In-Al-Zn-O-based, Sn-Ga-Zn-O-based, Al-Ga-Zn-O-based, S n-Al-Zn-O series, In-Zn-O series, Sn-Zn-O series, Al-Zn-O series, In - Uses an oxide semiconductor film of Sn-O, In-O, Sn-O, or Zn-O. In this embodiment, sputtering is performed using an In-Ga-Zn-O based oxide semiconductor target. The oxide semiconductor film 480 is formed by a ring method. Gas (typically argon) atmosphere, oxygen atmosphere, or rare gas (typically argon) atmosphere The oxide semiconductor film 480 is formed by a sputtering method in an oxygen atmosphere. In addition, when the sputtering method is used, SiO 2 2% by weight or more and 10% by weight The oxide semiconductor film 480 is formed using a target containing the following: It is also possible to include SiOx (x>0) which inhibits crystallization. This allows the During the heat treatment for dehydration or dehydrogenation, the oxide semiconductor layer formed later is crystallized. This can prevent the item from being put away.

[0212] Next, the oxide semiconductor film 480 is dehydrated or dehydrogenated. The temperature of the heat treatment in step 1 is 400° C. or higher and lower than the distortion point of the substrate, for example, 400° C. or higher and 700° C. or lower. The temperature is preferably 425°C or higher and 700°C or lower. If the temperature is less than 425℃, the heat treatment time should be less than 1 hour. In this case, the oxide film is placed on the top of an electric furnace, which is a type of heat treatment device, and the The substrate 450 on which the semiconductor film is formed is introduced, and the oxide semiconductor film is heated in a nitrogen atmosphere. After the heat treatment, the oxide semiconductor film is prevented from being exposed to the air and from being recontaminated with water or hydrogen. In this embodiment, the oxide semiconductor film is prevented from being oxidized, and the resistance of the oxide semiconductor film is reduced (see FIG. 39B). From the heating temperature T at which the compound semiconductor film 480 is dehydrated or dehydrogenated, water or hydrogen does not enter again. The same furnace is used until the temperature reaches a sufficient level, specifically, the heating temperature T is 100°C or more lower. The mixture is slowly cooled in a nitrogen atmosphere until the temperature reaches 100° C. The atmosphere is not limited to nitrogen, and may be helium, neon, or arsenic. The dehydration or dehydrogenation may be carried out under a rare gas atmosphere such as argon.

[0213] In the first heat treatment, nitrogen or a rare gas such as helium, neon, or argon is used. It is preferable that the nitrogen introduced into the heat treatment device does not contain water, hydrogen, or the like. The purity of rare gases such as helium, neon, and argon is preferably 6N (99.9999%) or higher. or 7N (99.99999%) or more (i.e. impurity concentration is 1 ppm or less, preferably It is preferable to keep the concentration of the ion exchange resin at 0.1 ppm or less.

[0214] Depending on the conditions of the first heat treatment or the material of the oxide semiconductor film 480, the oxide semiconductor film 480 may be crystallized. In some cases, the film may be microcrystalline or polycrystalline.

[0215] In addition, before the oxide semiconductor film 480 is formed, an inert gas atmosphere (nitrogen, helium, or neodymium) is Heat treatment (400°C or higher but below the distortion point of the substrate) in an oxygen atmosphere (e.g., nitrogen, argon, etc.). Impurities such as hydrogen and water contained in the gate insulating layer 452 may be removed by this treatment.

[0216] Next, an oxide conductive film is formed over the oxide semiconductor film 480 and then subjected to a second photolithography process. The resist masks 482a and 482b are formed by the process. The oxide conductive film and the oxide semiconductor film 480 are selectively and At the same time, etching is performed to form island-shaped oxide semiconductor layers 462 and 472. , and oxide conductive layers 442 and 444 are formed (see FIG. 38C). The resist masks 482a and 482b may be formed by an ink-jet method. If the mask is formed by the inkjet method, no photomask is used, so the manufacturing cost is reduced. can be reduced.

[0217] The oxide conductive film can be formed by sputtering or vacuum deposition (electron beam deposition, etc.). The conductive oxide film is made of a thin film of a 100% Cr-doped ... The material has a resistance higher than that of the oxide semiconductor film 480 and is A material having a lower resistance than the electrode layer 465b can be used, for example, In--Sn--Zn-- O-based, In-Al-Zn-O-based, Sn-Ga-Zn-O-based, Al-Ga-Zn-O-based, S n-Al-Zn-O series, In-Zn-O series, Sn-Zn-O series, Al-Zn-O series, In -Applying conductive metal oxides such as Sn-O, In-O, Sn-O, and Zn-O In addition, the thickness of the oxide conductive film can be appropriately selected within the range of 50 nm to 300 nm. In addition, when the sputtering method is used, SiO 2 Contains 2% by weight or more and 10% by weight or less The film is formed using a target containing SiOx( x>0) may be included. This can prevent the oxide conductive film from crystallizing. .

[0218] Here, an oxide semiconductor target containing In, Ga, and Zn (In 2 O 3 :Ga 2 O 3 :ZnO=1:1:1[mol ratio], In:Ga:Zn=1:1:0.5[atom Using the ratio, the distance between the substrate 450 and the target was set to 100 mm, the pressure was 0.2 Pa, and the Current (DC) power supply 0.5 kW, argon and oxygen (argon:oxygen = 30 sccm: 20 s The oxide conductive film is formed in an atmosphere of 40 ccm oxygen flow rate (40%). It is preferable to use an In-V DC power source, since it reduces dust and makes the film thickness distribution uniform. The thickness of the Ga-Zn-O based non-single crystal film is set to 5 nm to 200 nm. The oxide semiconductor film was prepared by sputtering using an In-Ga-Zn-O oxide semiconductor target. A 20 nm thick In-Ga-Zn-O non-single crystal film is formed by a deposition method. The oxide semiconductor target material is, for example, In:Ga:ZnO=1:1:1, or In It is also possible to use a target material such as Ga:ZnO=1:1:4.

[0219] In this embodiment, the resist masks 482a and 482b are recessed. In other words, it is a resist mask having a plurality of regions (herein) with different thicknesses. In this case, it can be said that the resist mask is made up of two regions. In the resist mask 482a or resist mask 482b, the thick region is masked with the resist mask 482a or resist mask 482b. The thin areas are called convex portions of the resist mask 482a or the resist mask 482b. This is called the recess of Ku 482b.

[0220] In the resist mask 482a and the resist mask 482b, the source electrode layer and A protrusion is formed in the area where the drain electrode layer is to be formed, and later a channel formation region is formed below. A recess is formed in the portion where the metal is formed.

[0221] The resist mask 482a and the resist mask 482b are formed by using a multi-tone mask. A multi-tone mask is a mask that can perform exposure with multiple levels of light intensity. Typically, the exposure is performed at three levels of light intensity: exposed area, semi-exposed area, and unexposed area. By using a multi-tone mask, multiple (substitute) patterns can be produced in a single exposure and development process. Generally, it is possible to form resist masks having different thicknesses. By using a gradation mask, the number of photomasks can be reduced.

[0222] By exposing and developing using a multi-tone mask, a resist mask with regions of different thicknesses is created. A mask 482a and a resist mask 482b can be formed. However, this is not limited to this. The resist mask 482a and the resist mask 48 are not formed without using a multi-tone mask. 2b may be formed.

[0223] Next, the resist masks 482a and 482b are retracted (reduced). To reduce the resist mask, an oxygen plate is used. By using ashing with Zuma, the resist mask can be reduced. As a result, the oxide semiconductor layer 462 and the oxide semiconductor layer 472 are partly exposed.

[0224] Next, selective etching is performed using the resist mask 487a and the resist mask 487b. By this, a low resistance source region 446a, a low resistance drain region 446b, and A source electrode layer 447a and a drain electrode layer 447b are formed (FIG. 39(D)).

[0225] As shown in FIG. 39(D), the resist masks 482a and 482b are recessed (reduced). The resist mask 487a and the resist mask 487b are used for etching to form an oxide film. The end of the compound semiconductor layer 462 is a low-resistance source region 446a and a low-resistance drain region 446b. The end of the oxide semiconductor layer 472 is connected to the source electrode layer 447a and the drain electrode It protrudes beyond the end of layer 447b.

[0226] In this etching process, the oxide semiconductor layer 462 and the oxide semiconductor layer 4 The etching conditions may be appropriately set so that the layer 72 remains. For example, the etching time It is sufficient to control the above.

[0227] In addition, the materials constituting the oxide semiconductor layers 462 and 472 and the oxide conductive layers 442 and 4 It is preferable to use materials having a high etching selectivity as the materials constituting 44. For example, a metal oxide material containing Sn (e.g., SnZnO x (x>0), or SnGaZnO x (x>0, etc.) and an oxide conductive layer The materials that make up the material are Al-Zn-O-based materials, Al-Zn-ON-based materials, and Zn-O-based materials. Such a material containing zinc oxide as a main component may be, for example, an alkaline It can be etched using a solution. When using materials that contain aluminum, such as aluminum-based materials, The resist is removed by a method in which the oxide conductive layer is not removed together with the resist mask. It is preferable to remove the resist mask by, for example, dry etching. By removing the resist mask, the oxide conductive layer is not removed and the resist mask can be removed. .

[0228] Next, the resist masks 487a and 487b are removed, and then, an oxide semiconductor The oxide insulating layer 466 is formed in contact with part of the layer 462 and the oxide semiconductor layer 472 .

[0229] The oxide insulating layer 466 has a thickness of at least 1 nm and is formed by an oxide insulating method such as a sputtering method. The oxide insulating layer 466 is formed by an appropriate method that does not allow impurities such as water and hydrogen to be mixed into the oxide insulating layer 466. In this embodiment, the oxide insulating layer 466 can be formed to a thickness of 300 nm. A silicon oxide film with a thickness of 1 μm is formed by sputtering. The substrate temperature during film formation is set to 300 μm above room temperature. The temperature is set to 100° C. in this embodiment. The deposition by the argon method is carried out under a rare gas (typically argon) atmosphere, an oxygen atmosphere, or a rare gas atmosphere. The target can be heated to 300° C. (typically, argon) and oxygen atmosphere. A silicon oxide target or a silicon target can be used as the target. Using a get, a silicon oxide film is formed by sputtering in an oxygen and nitrogen atmosphere. The oxide insulating layer in contact with the oxide semiconductor layer 462 and the oxide semiconductor layer 472 can be formed by 466 is water, hydrogen ions, OH - It does not contain impurities such as The inorganic insulating film is typically a silicon oxide film or a silicon nitride oxide film. The insulating film is formed using an aluminum oxide film, an aluminum oxynitride film, or the like. An oxide insulating layer 466 is deposited using boron doped silicon target material. By forming the silicon oxide film, impurities (water, hydrogen ions, OH - etc. ) can be suppressed.

[0230] Next, a second heat treatment (preferably at 200° C. or higher and 400° C. or lower, for example at 250° C. or higher and 35° C. or lower) is performed. For example, a second heat treatment is performed at 250° C. for 1 hour in a nitrogen atmosphere. By the second heat treatment, part of the oxide semiconductor layer 462 and part of the oxide semiconductor layer 472 are oxidized. The insulating layer 466 is heated while in contact with the insulating layer 466 .

[0231] Through the above steps, the oxide semiconductor layer 462 and the oxide semiconductor layer 472 can be formed into a low-resistance oxide semiconductor layer. By this, parts of the oxide semiconductor layer 462 and the oxide semiconductor layer 472 are selectively made into an oxygen-excess state. As a result, the channel formation region 463 overlapping with the gate electrode layer 461 has an i-type structure. Thus, the channel formation region 473 overlapping with the gate electrode layer 471 becomes an I-type, and a low resistance source A high-resistance source region 464a is self-aligned in a portion of the oxide semiconductor layer 462 that overlaps the region 446a. A high-resistance semiconductor layer is formed in a portion of the oxide semiconductor layer 462 that overlaps with the low-resistance drain region 446b. A resistive drain region 464b is formed in a self-aligned manner and is oxidized to overlap the source electrode layer 447a. A high-resistance source region 474a is formed in a self-aligned manner in the portion of the compound semiconductor layer 472, and a drain A high-resistance drain region 474b is formed in a portion of the oxide semiconductor layer 472 that overlaps with the electrode layer 447b. It is formed in a self-aligning manner (see FIG. 39(E)).

[0232] In addition, the oxide overlapping the low-resistance source region 446a (and the low-resistance drain region 446b) In the semiconductor layer 462, a high-resistance drain region 464b (or a high-resistance source region 464a) By forming a high resistance layer, the reliability of the driving circuit can be improved. By forming the anti-drain region 464b, the transistor is The conductivity is gradually changed from the high-resistance drain region 464b to the channel formation region 463. Therefore, the drain electrode layer can be connected to the high power supply potential VDD When the transistor is operated by electrically connecting the gate electrode layer 461 to a wiring that supplies Even if a high electric field is applied between the drain electrode layer 465b and the drain electrode layer 465c, the high resistance drain region is a buffer. As a result, local electric field concentration does not occur, and the dielectric strength of the transistor can be improved.

[0233] In addition, the oxide layer overlapping the low-resistance source region 446a (and the low-resistance drain region 446b) In the semiconductor layer 462, a high-resistance drain region 464b (or a high-resistance source region 464a ) to reduce the leakage current of the transistor in the drive circuit. can be done.

[0234] In addition, the oxide semiconductor layer overlapping with the drain electrode layer 447b (and the source electrode layer 447a) In 472, a high-resistance drain region 474b (or a high-resistance source region 474a) is formed. By doing so, the reliability of the pixel can be improved. By forming the region 474b, the transistor is connected to the drain electrode layer 447b via a high resistance drain electrode layer 447b. The conductivity can be changed stepwise from the drain region 474b to the channel formation region 473. Therefore, the drain electrode layer 447b can be connected to a high power supply potential VDD When electrically connecting to a wiring supplying power, the gate electrode layer 471 and the drain electrode Even if a high electric field is applied between the drain region 474b and the layer 447b, the high resistance drain region 474b acts as a buffer. A structure can be obtained in which no local electric field concentration occurs and the withstand voltage of the transistor is improved.

[0235] In addition, the oxide semiconductor layer overlapping with the drain electrode layer 447b (and the source electrode layer 447a) In step 472, a high-resistance drain region 474b (and a high-resistance source region 474a) is formed. This makes it possible to reduce leakage current of the transistor in the pixel.

[0236] Note that in the semiconductor device of this embodiment, a protective insulating layer is provided over the oxide insulating layer 466. In the case where a protective insulating layer is provided, an RF sputtering method is used in this embodiment mode. The RF sputtering method is suitable for mass production, so it is suitable for forming a protective insulating layer. It is preferable as a membrane method. For example, water, hydrogen ions, OH - Does not contain impurities such as A protective insulating layer is formed using an inorganic insulating film that blocks these substances from entering from the outside. Silicon nitride film, aluminum nitride film, silicon oxynitride film, aluminum oxynitride film, etc. The protective insulating layer can be formed using a film or the like. Of course, the protective insulating layer has a light-transmitting property. It is an insulating layer.

[0237] Next, a third photolithography process is performed to form a resist mask, and an oxide insulating layer 4 The etching of 66 exposes a portion of the low-resistance source region 446a in region 428. The drain region 446b is exposed in the region 429, and the drain electrode layer 447b is exposed in the region 429. The contact hole 437 is formed so that the oxide insulating layer 466 is not exposed to the upper surface of the oxide semiconductor layer 462. and the low-resistance source region 446a and the low-resistance drain region 446b. A structure is formed (see FIG. 40(A)). Note that the resist mask here is an inkjet type. If the resist mask is formed by the inkjet method, the photomask Since no wiring is used, manufacturing costs can be reduced.

[0238] Next, after removing the resist mask, at least the exposed low-resistance source region 446a and A conductive film is formed on the low-resistance drain region 446b and the oxide insulating layer 466. Resist masks 491a and 491b are formed on the conductive film by a lithography process. The conductive film is selectively etched to form the source electrode layer 405a and the drain electrode layer 405b. (See FIG. 40(B)).

[0239] As a material of the conductive film for forming the source electrode layer 405a and the drain electrode layer 405b, is an element selected from Al, Cr, Cu, Ta, Ti, Mo, and W, or a combination of the above elements. There are alloys that contain only one of the above elements, or alloys that combine the above elements.

[0240] The conductive film may be a titanium film, an aluminum film provided on the titanium film, and a conductive film formed on the aluminum film. A three-layer laminate film of a titanium film provided on a molybdenum film, or a molybdenum film, A three-layer structure of an aluminum film and a molybdenum film formed on the aluminum film. It is preferable to use a laminated film. Of course, the conductive film may be a single layer film, a laminated film of two layers, or a film of four or more layers. The above laminated film may be used. In addition, a titanium film, an aluminum film, and a titanium When a laminated conductive film of the film is used, etching is performed by dry etching using chlorine gas. It is possible.

[0241] Next, a planarization insulating layer 454 is formed over the oxide insulating layer 466. Examples include polyimide, acrylic resin, benzocyclobutene resin, polyamide, and epoxy resin. In addition to the above organic materials, organic materials having low dielectric constant can be used. Dielectric constant material (low-k material), siloxane resin, PSG (phosphorus glass), BPSG (phosphorus The planarization insulating layer 454 can be made of a material such as boron nitride glass. The planarization insulating layer 454 may be formed by stacking a plurality of insulating films made of the same material.

[0242] The method for forming the planarization insulating layer 454 is not particularly limited. Depending on the material, it may be formed by sputtering. coating method, SOG method, spin coating, dip coating, spray coating, droplet ejection method (ink jet printing, screen printing, offset printing, etc.), doctor knife, roll coater, car Tools such as a ten coater or a knife coater can be used.

[0243] Next, a fifth photolithography step is performed to form a resist mask, and a planarization insulating layer 4 A contact hole 494 reaching the drain electrode layer 447b is formed by etching 54. (See FIG. 39B). In addition, the gate electrode layers 461 and 47 are etched. A contact hole reaching the drain electrode layer 447b is also formed. A resist mask for forming a resist hole may be formed by an ink-jet method. If the mask is formed by the inkjet method, no photomask is used, so the manufacturing cost is reduced. can be reduced.

[0244] Next, after removing the resist mask, a light-transmitting conductive film is formed. Indium (In 2 O 3 ) and indium tin oxide alloy (In 2 O 3 - SnO 2 , ITO The film is formed by sputtering or vacuum deposition, etc. A conductive film having a light-transmitting property is formed by using an Al film containing nitrogen. -Zn-O based non-single crystal film, i.e. Al-Zn-ON based non-single crystal film and Zn-ON based non-single crystal film A crystalline film or a Sn-Zn-ON non-single crystal film may be used. The composition ratio (atomic %) of zinc in the Al-Zn-ON non-single crystal film is 47 atomic % or less. The composition ratio (atomic percent) of aluminum in the non-single crystal film is larger than that in the non-single crystal film. The composition ratio (atomic %) of aluminum in the crystal film is 100% of that of nitrogen in the Al-Zn-ON non-single crystal film. The composition ratio (atomic percentage) of the element is larger than that of the element. The etching process for the film containing such a material is carried out using a hydrochloric acid-based However, etching of ITO is particularly prone to leaving residues, so Indium oxide zinc oxide alloy (InO2) was used to improve the machining processability. 2 O 3 -ZnO) It's fine.

[0245] Next, a sixth photolithography process is performed to form a resist mask and to form a By removing unnecessary portions of the light-transmitting conductive film and removing the resist mask, A pixel electrode layer 477 and a conductive layer 467 are formed (see FIG. 39D).

[0246] Through the above steps, the thin film transistor 460 and the thin film transistor 470 are formed on the same substrate using six masks. The film transistor 470 can be fabricated separately for the driver circuit or pixel portion. The thin film transistor 460 for the driving circuit has a high resistance source region 464a, a high resistance drain A thin film transistor including the oxide semiconductor layer 462 having the region 464b and the channel formation region 463 is formed. The pixel thin film transistor 470 includes a high resistance source region 474a, a high An oxide semiconductor layer 472 including a resistor drain region 474b and a channel formation region 473 The thin film transistor 460 and the thin film transistor 470 include Even when a high electric field is applied, the high resistance source region 464a, the high resistance drain region 464b, and the high resistance The anti-source region 474a and the high-resistance drain region 474b act as buffers to reduce the local electric field This configuration prevents concentration and improves the dielectric strength of the transistor.

[0247] In the method for manufacturing a semiconductor device shown in FIGS. 39 and 40, the gate insulating layer 452 is The storage capacitor formed by the capacitance wiring and the capacitance electrode is also a thin film transistor 460 and a thin film transistor The thin film transistor 470 and the holding The capacitors are arranged in a matrix to correspond to each pixel, forming a pixel section, and a thin By disposing a driving circuit having a film transistor 460, an active matrix type It can be one of the substrates for manufacturing a display device.

[0248] The pixel electrode layer 477 is formed through a contact hole 494 formed in the planarization insulating layer 454. The oxide insulating layer 466 is electrically connected to the capacitor electrode layer through a contact hole 437 formed therein. The capacitive electrode layer is electrically connected to the source electrode layer 447a and the drain electrode layer 447b. They can be formed using the same materials and processes.

[0249] In addition, the conductive layer 467 is provided so as to overlap with the channel formation region 463 of the oxide semiconductor layer 462. Bias-thermal stress test to check the reliability of thin-film transistors by (hereinafter referred to as BT test), the thin film transistor 460 before and after the BT test The amount of change in the threshold voltage can be reduced. It may be the same as layer 461 or may be different and may also function as a gate electrode layer. The conductive layer 467 can be in a GND state, a state in which a potential of 0V is applied, or a floating state. The device may be in a loading state.

[0250] In addition, a resist mask for forming the pixel electrode layer 477 and the conductive layer 467 is formed by ink jet printing. If the resist mask is formed by the ink-jet method, the photomask Since no additional heat is used, the manufacturing cost can be reduced.

[0251] (Embodiment 5) In this embodiment, an example in which the first heat treatment is different from that in the fourth embodiment is shown in FIG. Since the process is the same as that shown in FIG. 40 except for some differences, the same reference numerals are used for the same parts. A detailed description of the same points will be omitted.

[0252] 41A to 41C are cross-sectional views showing a manufacturing process of two thin film transistors.

[0253] First, according to the fourth embodiment, gate electrode layers 461 and 462 are formed on a substrate 450 having an insulating surface. Form 71.

[0254] Next, the gate insulating layer 452 is formed over the gate electrode layers 461 and 471 .

[0255] Next, an oxide semiconductor film 480 with a thickness of 2 nm to 200 nm is formed over the gate insulating layer 452. (See FIG. 41(A)). The steps up to this point are the same as those in the fourth embodiment. Therefore, FIG. 41(A) corresponds to FIG. 39(A).

[0256] Next, the oxide semiconductor film 480 is dehydrated or oxidized under an inert gas atmosphere or reduced pressure. The temperature of the first heat treatment for dehydration or dehydrogenation is 350° C. or higher. The temperature is set to be lower than the distortion point of the substrate, preferably 400° C. or higher. The substrate is placed in an electric furnace, and the oxide semiconductor film is subjected to heat treatment in a nitrogen atmosphere. After that, the oxide semiconductor film is not exposed to the air, and water and hydrogen are prevented from re-mixing into the oxide semiconductor film. The membrane is made oxygen-deficient to reduce resistance, i.e., N-type (N - After that, in the same furnace, High purity oxygen gas or high purity N 2 O2 gas or ultra-dry air (dew point below -40℃) Cooling is performed by introducing oxygen gas or N 2 O gas, water, It is preferable that hydrogen and the like are not included. Alternatively, oxygen gas or N 2 The purity of O gas is 6N (99.9999%) or more, preferably 7N (99.9999%). 9%) or more (i.e. oxygen gas or N 2 The impurity concentration in the O gas is preferably 1 ppm or less. It is preferable that the concentration of the ion exchange resin is 0.1 ppm or less.

[0257] After the first heat treatment for dehydration or dehydrogenation, the temperature is preferably 200° C. or higher and 400° C. or lower. or in an oxygen gas atmosphere at a temperature between 200°C and 300°C, or in an N 2 Under O gas atmosphere Or heating in an ultra-dry air atmosphere (dew point below -40°C, preferably below -60°C) Processing may be carried out.

[0258] Through the above steps, the entire oxide semiconductor layer is made into an oxygen-excess state, and the resistance is increased. That is, the oxide semiconductor film 496 is formed by making the oxide semiconductor film i-type (see FIG. 41B). This can improve the reliability of the thin film transistor formed on the substrate.

[0259] In addition, the oxide semiconductor film is dehydrated or dehydrogenated under an inert gas atmosphere. After cooling under a reactive gas atmosphere, a resist mask is formed by a photolithography process. The oxide semiconductor film 496 is selectively etched using the resist mask, An island-shaped oxide semiconductor layer is formed, and then the oxide semiconductor layer is heated at 200° C. or higher and 400° C. or higher. Preferably, the temperature is 200° C. or higher and 300° C. or lower, and ... 2 O gas In an atmosphere, or in an ultra-dry air atmosphere (dew point is -40°C or less, preferably -60°C or less), Heat treatment may be carried out at .

[0260] In addition, before the oxide semiconductor film 480 is formed, an inert gas atmosphere (nitrogen, helium, or neodymium) is Under oxygen atmosphere, ultra-dry air (dew point below -40℃, preferably -60℃) Heat treatment (400°C or higher but below the distortion point of the substrate) is then performed in an atmosphere (400°C or higher but below the distortion point of the substrate) to form a gate insulation film. Impurities such as hydrogen and water contained within the layer may be removed.

[0261] 39(C), 39(D), 39(E), 40(A), and 4 40B and 40C, oxide semiconductor layers 497 and 498 are formed. A low-resistance source region 446a and a low-resistance drain region 446b are formed in contact with the conductor layer 497. In addition, a part of the oxide semiconductor layer 497, the low-resistance source region 446a, and the low-resistance drain region An oxide insulating layer 466 is formed in contact with the periphery and side surfaces of the region 446b. The source electrode layer 447a is in contact with the oxide semiconductor layer 498 and is a light-transmitting conductive layer. and a drain electrode layer 447b is formed. Layer 466 is formed.

[0262] Next, a second heat treatment (preferably 200 The second heat treatment is performed at a temperature of 250° C. or higher and 400° C. or lower, for example, 250° C. or higher and 350° C. or lower. For the manufacturing method, the same conditions as those in the manufacturing method of the semiconductor device described in Embodiment 4 can be used. For example, a second heat treatment is performed in a nitrogen atmosphere at 250° C. for 1 hour.

[0263] Next, a part of the low-resistance source region 446a and the low-resistance drain region 446b are exposed, and an oxide A contact hole is formed in the oxide insulating layer 466 to reach the drain electrode layer 447b. A conductive film is formed on the insulating layer 466, and the conductive film is selectively etched to form the low-resistance source region 4. A source electrode layer 465a in contact with the low-resistance drain region 446b and a drain electrode layer 465b in contact with the low-resistance drain region 446b are provided. A pole layer 465b is formed, and a planarizing insulating layer 454 is formed in contact with the oxide insulating layer 466. A contact hole is formed in the insulating layer 454 to reach the drain electrode layer 447b. A light-transmitting conductive film is formed over the holes and the planarization insulating layer 454. A pixel electrode layer electrically connected to the drain electrode layer 447b by selectively etching the conductive film. A conductive layer 477 is formed, and then a conductive layer 467 is formed (see FIG. 41C).

[0264] Through the above steps, the entire oxide semiconductor layer was formed into an I-type structure on the same substrate using six masks. The thin film transistor 492 and the thin film transistor 493 are formed in a driver circuit or a pixel portion. The thin film transistor 492 for the driver circuit is an I-type transistor. The thin film transistor 4 for a pixel includes an oxide semiconductor layer 497. Reference numeral 93 denotes a thin film transistor including an oxide semiconductor layer 498 which is entirely i-type.

[0265] In addition, the storage capacitor formed by the capacitance wiring layer and the capacitance electrode with the gate insulating layer 452 as a dielectric is The thin film transistor 492 and the thin film transistor 493 can be formed over the same substrate. The thin film transistors 493 and storage capacitors are arranged in a matrix in correspondence with each pixel. A pixel portion is formed, and a driver circuit having a thin film transistor 492 is arranged around the pixel portion. This makes it possible to fabricate one of the substrates for an active matrix display device. Cut.

[0266] In addition, the conductive layer 467 is provided so as to overlap with a channel formation region of the oxide semiconductor layer 497. As a result, in the BT test, the threshold voltage of the thin film transistor 492 before and after the BT test In addition, the conductive layer 467 has a potential that is different from that of the gate electrode layer 4 61 may be the same as or different from the gate electrode layer. The conductive layer 467 is in a GND state, a state in which a potential of 0V is applied, or a floating state. The device may be in a ring state.

[0267] (Embodiment 6) A semiconductor device and a manufacturing method of the semiconductor device different from those in Embodiment Mode 1 will be described with reference to FIGS. explain.

[0268] The semiconductor device shown in FIG. 43 has a thin-film transistor in a driver circuit, which is different from the semiconductor device shown in FIG. The structures of the conductive layer overlapping the source electrode, drain electrode, and channel forming region of the MOSFET are different. Therefore, other parts that are the same as those of the semiconductor device shown in FIG. The explanation will be cited as appropriate and will not be repeated here.

[0269] FIG. 43(A1) is a plan view of a thin film transistor 440 disposed in a driving circuit. FIG. 43(A2) is a plan view of a thin film transistor 420 disposed in a pixel, and FIG. 43(B) is a plan view of a thin film transistor 420 disposed in a pixel. 43(A1) and the cross-sectional structure along the line C5-C6 in FIG. 43(A2) FIG. 43(C) is a cross-sectional view showing the cross-sectional structure of the semiconductor device shown in FIG. 43(A1). 43(A2) and a cross-sectional structure taken along line D7-D8 in FIG. do.

[0270] The thin film transistor 440 disposed in the driving circuit is formed on a substrate having an insulating surface, as in FIG. On the substrate 400, a gate electrode layer 411, a gate insulating layer 402, and at least a channel forming region are formed. 413, a high-resistance source region 414a, and a high-resistance drain region 414b. A semiconductor layer 412, a low-resistance source region 408a and a low-resistance drain region 408b, and a source The thin film transistor includes a source electrode layer 405a and a drain electrode layer 405b. 440 denotes the periphery and side of the low-resistance source region 408a and the low-resistance drain region 408b; and an oxide insulating layer 416 in contact with the oxide semiconductor layer.

[0271] The high-resistance source region 414a is self-aligned to the bottom surface of the low-resistance source region 408a. The high-resistance drain region 414b is formed in a symmetrical manner. The channel forming region 413 is formed in a self-aligned manner in contact with the bottom surface of the oxidized layer 412. The high-resistance source region 414a and the high-resistance drain region 414b are in contact with the insulating layer 416. The region is a region of higher resistance than the region of the junction (type I region).

[0272] In the semiconductor device shown in FIG. 43, a high-resistance source region is provided in the oxide semiconductor layer of the thin film transistor. However, the present invention is not limited to this structure, and may also include a high resistance source region and a high resistance drain region. In addition, a high-resistance drain region is not provided, and the oxide semiconductor layer is entirely a high-resistance region (i-type region). It is also possible to make the structure.

[0273] The source electrode layer 405a is in contact with the low-resistance source region 408a, and the drain electrode layer 405b is in contact with the low-resistance source region 408a. , contacting the low-resistance drain region 408b.

[0274] In addition, the driver circuit shown in FIG. The conductive layer 405c is electrically connected to the gate electrode layer 411. By setting the potentials at the same level, the oxide layer 411 and the conductive layer 405c are A gate voltage can be applied to the semiconductor layer 412 from above and below. When the potentials of the conductive layer 405c and the conductive layer 405b are different, for example, a fixed potential, GND, or 0V, the TF The electrical properties of T, such as the threshold voltage, can be controlled.

[0275] The source electrode layer 405a, the drain electrode layer 405b, and the conductive layer 405c are formed using the same material. It can be formed of any material, and it is preferable to use, for example, a metal material.

[0276] The driver circuit includes a conductive layer 405c, a source electrode layer 405a, and a drain electrode layer 405b. A planarization insulating layer 404 is provided over the oxide insulating layer 416 .

[0277] Furthermore, the structure of the thin film transistor 420 disposed in the pixel is the same as that of the semiconductor device shown in FIG. Since the description is the same as that of the semiconductor device shown in FIG. 1, the description thereof will be omitted here.

[0278] In the semiconductor device shown in FIG. 43, a thin film transistor 440 and a thin film transistor The channel length of the transistor 420 is the same, but not limited to this. The transistors are required to operate faster than the thin-film transistors in the pixel area, so The channel length of the thin film transistor 440 may be narrower than the channel length of the thin film transistor 420. At this time, the channel length of the thin film transistor 440 is, for example, about 1 μm to 5 μm. It is preferable that the channel length of the thin film transistor 420 is about 5 μm to 20 μm. is preferred.

[0279] As described above, the semiconductor device shown in FIG. 43 has a first thin film transistor on the same substrate. and a pixel portion having a second thin film transistor. The transistor is made of a light-transmitting material, and the first thin film transistor is The pixel section is made of a material having a lower resistance than the material having a higher resistance. The throughput can be improved, and the operating speed of the driver circuit can be improved. By providing a driver circuit and a pixel portion on the same substrate, the driver circuit and the pixel portion are connected to each other. The number of wirings and the length of wirings can be reduced, which leads to miniaturization and cost reduction of semiconductor devices. is possible.

[0280] In addition, the semiconductor device shown in FIG. 43 includes a driver circuit having a thin film transistor formed of an oxide semiconductor. a part of the oxide conductive layer, and a part of the oxide conductive layer in contact with the source electrode layer and the drain electrode layer; The oxide insulating layer is in contact with the side of the thin film transistor. The wiring in the same layer as the gate electrode layer and the wiring in the same layer as the source electrode and drain electrode are provided in the peripheral area. When the insulating layer is sandwiched between the gate electrode layer and the gate electrode layer, the insulating layer is formed on the same layer as the gate electrode layer. Since the distance between the wiring and the wiring in the same layer as the source electrode and the drain electrode can be increased, The parasitic capacitance can be reduced.

[0281] In addition, in the semiconductor device shown in FIG. 43, in the thin film transistor of the driver circuit, A low-resistance solenoid is provided between the drain electrode layer and the oxide semiconductor layer in which a channel formation region is formed. The structure has a low-resistance source region and a low-resistance drain region. By providing an in-region, it is possible to improve the frequency characteristics of the peripheral circuits (drive circuits). Compared with the contact between the metal electrode layer and the oxide semiconductor layer, the contact between the metal electrode layer and the low resistance source region and This is because contact with the low-resistance drain region can reduce the contact resistance. Electrode layers using molybdenum (e.g., stacking of molybdenum layer, aluminum layer, molybdenum layer, etc.) The contact resistance with the oxide semiconductor layer is high because molybdenum is less susceptible to oxidation than titanium. Therefore, the effect of extracting oxygen from the oxide semiconductor layer is weak, and the molybdenum layer and the oxide semiconductor layer However, the contact interface between the oxide semiconductor layer and the source electrode layer and the drain electrode layer does not become n-type. A low-resistance source region and a low-resistance drain region are interposed between the drain electrode layer and the contact. The resistance can be reduced, and the frequency characteristics of the peripheral circuits (drive circuits) can be improved. By providing a low resistance source region and a low resistance drain region, The channel length (L) is determined by the etching of the layers that will become the low-resistance source region and the low-resistance drain region. Since the channel length can be determined, the channel length can be made shorter.

[0282] In addition, the semiconductor device shown in FIG. 43 has an oxide insulating layer in the thin film transistor of the driver circuit. The source electrode layer and the drain electrode layer are made of the same material as the drain electrode layer. A structure having a conductive layer formed thereon can be obtained, which reduces the threshold voltage of the thin film transistor. The conductive layer can be used as a source electrode of a thin film transistor of a driving circuit. Since the drain electrode layer and the drain electrode layer are made of the same material, the wiring resistance can be reduced. Since the conductive layer is the same layer as the source electrode layer and the drain electrode layer, It is preferable that the conductive layer is disposed so as not to contact the positive electrode layer or the drain electrode layer. A conductive layer is provided on the upper layer via an insulating layer, and a contact hole is provided in the insulating layer. By forming an electrically connected structure, the conductive layer can be routed.

[0283] Further, similarly to the first embodiment, the semiconductor device of the present embodiment has a gate electrode for a thin film transistor. Alternatively, the oxide insulating layer may be made into a two-layer structure with a protective insulating layer on top of the oxide insulating layer. do.

[0284] In the following, referring to FIG. 44, a thin film transistor 440 and a thin film transistor 420 are formed on the same substrate. An example of a method for producing the above will be described.

[0285] First, referring to FIG. 2(A), FIG. 2(B), FIG. 2(C), FIG. 2(D), FIG. 2(E) of the first embodiment, 3A, a gate electrode layer 411 and a gate electrode layer 421 are formed on a substrate 400. A gate insulating layer 402 is formed over the gate electrode layer 411 and the gate electrode layer 421. An oxide semiconductor layer 412 is formed over a gate electrode layer 411 with a gate insulating layer 402 interposed therebetween; In addition, the oxide semiconductor layer 422 is formed on the gate electrode layer 421 with the gate insulating layer 402 interposed therebetween. Then, first heat treatment is performed to dehydrate or remove the oxide semiconductor layers 412 and 422. A low-resistance semiconductor layer including an oxide conductive layer is formed on the oxide semiconductor layer 412. The source region 408a and the low-resistance drain region 408b are formed, and the oxide semiconductor layer 422 is A source electrode layer 409a and a drain electrode layer 409b are formed of an oxide conductive layer on the The low-resistance source region 408a and the low-resistance drain region 408b are formed in the oxide semiconductor layer 412. The periphery and side surfaces of the region 408b, the source electrode layer 409a, and the drain electrode layer 409b The oxide insulating layer 416 is formed in contact with the oxide insulating layer 416. 4, a part of the low-resistance source region 408a and a part of the low-resistance drain region 408b are exposed. A contact hole 44 is formed in the oxide insulating layer 416 so as to reach the drain electrode layer 409b. Form 26.

[0286] Further, a conductive film is formed over the oxide insulating layer 416, and a resist film is formed by a photolithography process. Then, resist masks 448a, 448b, and 448c are formed. The source electrode layer 405a, the drain electrode layer 405b, and Furthermore, a conductive layer 405c is formed (see FIG. 44A).

[0287] In this etching process, the low-resistance source region 408a and the low-resistance drain region 408b are The region 408b, the source electrode layer 409a, the drain electrode layer 409b, and the oxide semiconductor layer 412 It is preferable that the oxide semiconductor layer 422 is not etched. For example, the etching time can be controlled. .

[0288] In addition, the materials constituting the oxide semiconductor layers 412 and 422 and the low-resistance source region 408a A low-resistance drain region 408b, a source electrode layer 409a, and a drain electrode layer 409b are formed. It is preferable to use materials having a high etching selectivity for each of the layers. For example, a metal oxide material containing Sn (e.g., SnZn O x (x>0), or SnGaZnO x (x>0, etc.) to form an oxide conductive layer. Examples of materials that can be used include Al-Zn-O, Al-Zn-ON, and Zn-O materials. Such a material containing zinc oxide as a main component can be used, for example, by using an alkaline solution. In addition, Al-Zn-O and Al-Zn-ON materials can be etched. When using materials that contain aluminum, such as aluminum alloys, the resist used for etching The resist mask is removed by a method in which the oxide conductive layer is not removed together with the mask. For example, the resist mask is preferably removed by dry etching. In this manner, the resist mask can be removed without removing the oxide conductive layer.

[0289] Next, the resist masks 448a to 448c are removed, and then the source electrode layer 405a and the drain electrode layer 405b are A planarizing insulating layer 405 is formed on the conductive layer 405b and the oxide insulating layer 416. 4, a photolithography process is performed to form a resist mask, and a planarizing insulating layer 4 A contact hole 441 reaching the drain electrode layer 409b is formed by etching in step 04. (See Figure 44(B)).

[0290] Next, after removing the resist mask, a conductive film having light transmitting properties is formed, and then photolithography is performed. A resist mask is formed, and unnecessary parts are removed by etching to form pixel electrodes. The pole layer 427 is formed (see FIG. 44(C)).

[0291] In the method for manufacturing the semiconductor device of the present embodiment, as shown in FIG. The source electrode layer 409a and the drain electrode layer 409b are connected to the low-resistance drain region 408a and the low-resistance drain region 408b. The electrode layer 409b can also be formed using one mask.

[0292] Through the above steps, thin film transistors 44 are formed on the same substrate using seven or eight masks. 0 and the thin film transistor 420 are separately fabricated in the driver circuit or pixel portion. The thin film transistor 440 of the driving circuit has a high resistance source region 414a, a high resistance drain region 414b, and a The thin film including the oxide semiconductor layer 412 including the drain region 414b and the channel formation region 413 is The thin film transistor 420 in the pixel portion is a high resistance source region 424a , the high-resistance drain region 424b, and the channel formation region 423. 2. The thin film transistor 440 and the thin film transistor 420 Even when a high electric field is applied, the high resistance source region 414a, the high resistance drain region 414b, and the high The resistive source region 424a and the high-resistive drain region 424b act as buffers to reduce local This configuration prevents field concentration and improves the dielectric strength of the transistor.

[0293] In addition, in the method for manufacturing the semiconductor device of this embodiment mode, In the same process as the source electrode layer and the drain electrode layer, a conductive layer overlapping the channel formation region of the semiconductor layer is formed. This allows the device to be manufactured without increasing the number of steps. do.

[0294] (Embodiment 7) A semiconductor device and a manufacturing method thereof which are different from those in Embodiment Mode 6 will be described with reference to FIGS. explain.

[0295] The semiconductor device shown in FIG. 45 has a driving circuit different from that of the semiconductor device shown in FIG. 38 of the fourth embodiment. A conductive layer overlapping a source electrode, a drain electrode, and a channel forming region of a thin film transistor of the line The layer structure is different. Therefore, the same parts as those in the semiconductor device shown in FIG. The description of the semiconductor device shown in FIG. 8 will be used as appropriate, and the description will be omitted here.

[0296] FIG. 45(A1) is a plan view of a thin film transistor 490 disposed in a driving circuit. FIG. 45(A2) is a plan view of a thin film transistor 470 disposed in a pixel, and FIG. 45(B) is a plan view of a thin film transistor 470 disposed in a pixel. 45(A1) and the cross-sectional structure along the line G5-G6 of FIG. 45(A2) FIG. 45(C) is a cross-sectional view showing the cross-sectional structure of the semiconductor device shown in FIG. 45(A1) along line G7-G8. 45(A2) and FIG. 45(A3) are cross-sectional views showing a cross-sectional structure taken along line H7-H8 in FIG. do.

[0297] The thin film transistor 490 disposed in the driving circuit is formed on a substrate having an insulating surface, as in FIG. On the plate 450, a gate electrode layer 461, a gate insulating layer 452, and at least a channel forming region are formed. 463, an oxide semiconductor having a high-resistance source region 464a and a high-resistance drain region 464b; The body layer 462, the low-resistance source region 446a, the low-resistance drain region 446b, and the source electrode layer 4 The thin film transistor 490 also includes a low resistance The periphery and side of the low-resistance source region 446a and the low-resistance drain region 446b, as well as the oxide semiconductor This structure includes a protective insulating layer 453 that is in contact with a part of the conductor layer 462 .

[0298] The high-resistance source region 464a is in contact with the lower surface of the low-resistance source region 446a in a self-aligned manner. The high-resistance drain region 464b is formed in a substantially uniform manner. The channel forming region 463 is formed in a self-aligned manner in contact with the bottom surface of the protective layer 462. The insulating layer 453 is in contact with the high-resistance source region 464a and the high-resistance drain region 464b. This is a high resistance region (I type region).

[0299] In the semiconductor device shown in FIG. 45, a high-resistance source region is provided in the oxide semiconductor layer of the thin film transistor. However, the present invention is not limited to this structure, and may also include a high resistance source region and a high resistance drain region. In addition, a high-resistance drain region is not provided, and the oxide semiconductor layer is entirely a high-resistance region (i-type region). It is also possible to adopt a structure in which

[0300] The source electrode layer 495a is in contact with the low-resistance source region 446a, and the drain electrode layer 495b is in contact with the low-resistance source region 446a. , contacting the low-resistance drain region 446b.

[0301] In addition, the driver circuit shown in FIG. The conductive layer 495c is electrically connected to the gate electrode layer 461. By setting the potentials at the same level, the oxide layer 461 and the conductive layer 495c are A gate voltage can be applied to the semiconductor layer 462 from above and below. When the potentials of the conductive layer 495c and the conductive layer 495b are different, for example, a fixed potential, GND, or 0V, the TF The electrical properties of T, such as the threshold voltage, can be controlled.

[0302] The source electrode layer 495a, the drain electrode layer 495b, and the conductive layer 495c are formed using the same material. It can be formed of any material, and it is preferable to use, for example, a metal material.

[0303] The driver circuit includes a conductive layer 495c, a source electrode layer 495a, and a drain electrode layer 495b. A planarization insulating layer 454 is provided between the insulating layer 454 and the oxide insulating layer 466 .

[0304] Furthermore, FIG. 45(A2) is a plan view of a thin film transistor 470 disposed in a pixel. The structure of the membrane transistor 470 is the same as that of the semiconductor device shown in FIG. The description of the semiconductor device will be omitted here.

[0305] In the semiconductor device shown in FIG. 45, a thin film transistor 490 and a thin film transistor The channel length of the transistor 470 is the same, but not limited to this. The transistors are required to operate faster than the thin-film transistors in the pixel area, so The channel length of the thin film transistor 490 may be narrower than the channel length of the thin film transistor 470. At this time, for example, the channel length of the thin film transistor 490 is about 1 μm to 5 μm. It is preferable that the channel length of the thin film transistor 470 is about 5 μm to 20 μm. is preferred.

[0306] As described above, the semiconductor device shown in FIG. 45 has a first thin film transistor on the same substrate. and a pixel portion having a second thin film transistor. The transistor is made of a light-transmitting material, and the first thin film transistor is The pixel section is made of a material having a lower resistance than the material having a higher resistance. The throughput can be improved, and the operating speed of the driver circuit can be improved. By providing a driver circuit and a pixel portion on the same substrate, the driver circuit and the pixel portion are connected to each other. The number of wirings and the length of wirings can be reduced, which leads to miniaturization and cost reduction of semiconductor devices. is possible.

[0307] In the semiconductor device illustrated in FIG. 45, an end portion of the oxide semiconductor layer of the first thin film transistor is low. The second thin film transistor is provided with an oxide layer that protrudes from the ends of the resistive source region and the low-resistive drain region. The end of the nitride semiconductor layer protrudes beyond the ends of the source electrode layer and the drain electrode layer. .

[0308] In addition, in the semiconductor device shown in FIG. 45, in the thin film transistor of the driver circuit, A low-resistance solenoid is provided between the drain electrode layer and the oxide semiconductor layer in which a channel formation region is formed. The structure has a low-resistance source region and a low-resistance drain region. By providing an in-region, it is possible to improve the frequency characteristics of the peripheral circuits (drive circuits). Compared with the contact between the metal electrode layer and the oxide semiconductor layer, the contact between the metal electrode layer and the low resistance source region and This is because contact with the low-resistance drain region can reduce the contact resistance. Electrode layers using molybdenum (e.g., stacking of molybdenum layer, aluminum layer, molybdenum layer, etc.) The contact resistance with the oxide semiconductor layer is high because molybdenum is less susceptible to oxidation than titanium. Therefore, the effect of extracting oxygen from the oxide semiconductor layer is weak, and the molybdenum layer and the oxide semiconductor layer However, the contact interface between the oxide semiconductor layer and the source electrode layer and the drain electrode layer does not become n-type. A low-resistance source region and a low-resistance drain region are interposed between the drain electrode layer and the contact. The resistance can be reduced, and the frequency characteristics of the peripheral circuits (drive circuits) can be improved. By providing a low resistance source region and a low resistance drain region, The channel length (L) is determined by the etching of the layers that will become the low-resistance source region and the low-resistance drain region. Since the channel length can be determined, the channel length can be made shorter.

[0309] In addition, the semiconductor device shown in FIG. 45 includes a driver circuit having a thin film transistor including an oxide semiconductor a part of the oxide conductive layer, and a part of the oxide conductive layer in contact with the source electrode layer and the drain electrode layer; The oxide insulating layer is in contact with the side of the thin film transistor. The wiring in the same layer as the gate electrode layer and the wiring in the same layer as the source electrode and drain electrode are provided in the peripheral area. When the insulating layer is sandwiched between the gate electrode layer and the gate electrode layer, the insulating layer is formed on the same layer as the gate electrode layer. Since the distance between the wiring and the wiring in the same layer as the source electrode and the drain electrode can be increased, The parasitic capacitance can be reduced.

[0310] In addition, in the semiconductor device shown in FIG. 45, an oxide insulating layer is formed in the thin film transistor of the driver circuit. The source electrode layer and the drain electrode layer are made of the same material as the drain electrode layer. A structure having a conductive layer formed thereon can be obtained, which reduces the threshold voltage of the thin film transistor. The conductive layer can be used as a source electrode of a thin film transistor of a driving circuit. Since the drain electrode layer and the drain electrode layer are made of the same material, the wiring resistance can be reduced. do.

[0311] Further, as in the fourth embodiment, the semiconductor device of the present embodiment has a gate electrode for a thin film transistor. Alternatively, the oxide insulating layer may be made into a two-layer structure with a protective insulating layer on top of the oxide insulating layer. do.

[0312] In the following, referring to FIG. 46, a thin film transistor 490 and a thin film transistor 470 are formed on the same substrate. An example of a method for producing the above will be described.

[0313] First, referring to FIG. 39(A), FIG. 39(B), FIG. 39(C), FIG. 39(D), and FIG. 40(A), a gate electrode layer 461 and a gate electrode layer 462 are formed on a substrate 450. A gate electrode layer 461 is formed on the gate electrode layer 471, and a gate insulating layer 45 is formed on the gate electrode layer 461 and the gate electrode layer 471. 2, an oxide semiconductor film 480 is formed over the gate insulating layer 452, and first heat treatment is performed. The oxide semiconductor film is dehydrated or dehydrogenated to obtain an oxide semiconductor film 481. An oxide conductive film is formed over the oxide semiconductor film 481, and a resist mask is formed using a multi-tone mask. A resist mask 482a and a resist mask 482b are formed. The oxide semiconductor film 481 and the oxide conductive film are etched using the mask 482b. Thus, the oxide semiconductor layer 462 is formed on the gate electrode layer 461 with the gate insulating layer 452 interposed therebetween. The oxide semiconductor layer 47 is formed on the gate electrode layer 471 with the gate insulating layer 452 interposed therebetween. 2, the resist mask 482a and the resist mask 482b are removed, and an oxide semiconductor A low-resistance source region 446a and a low-resistance drain region 446b are formed of an oxide conductive layer on the dielectric layer 462. The drain region 446b is formed, and the oxide semiconductor layer 472 is formed of an oxide conductive layer. A source electrode layer 447a and a drain electrode layer 447b are formed on the oxide semiconductor layer. the peripheral edges and side surfaces of the low-resistance source region 446a and the low-resistance drain region 446b; The oxide insulating layer 466 is formed in contact with the source electrode layer 447a and the drain electrode layer 447b. Then, a second heat treatment is performed to remove a part of the oxide insulating layer 466, and the low-resistance source region 4 46a and a portion of the low resistance drain region 446b are exposed, and the drain is then covered with an oxide insulating layer 466. A contact hole 437 is formed that reaches the drain electrode layer 409b.

[0314] Further, a conductive film is formed over the oxide insulating layer 466, and a resist film is formed by a photolithography process. Then, masks 455a, 455b, and 455c are formed and selectively etched to form source electrodes. A pole layer 495a, a drain electrode layer 495b, and a conductive layer 495c are formed (FIG. 46(A) reference).

[0315] In this etching process, the low-resistance source region 446a and the low-resistance drain region 446b are The region 446b, the source electrode layer 447a, the drain electrode layer 447b, and the oxide semiconductor layer 462 It is preferable that the oxide semiconductor layer 472 is not etched. For example, the etching time can be controlled. .

[0316] In addition, the materials constituting the oxide semiconductor layers 462 and 472 and the low-resistance source region 446a A low-resistance drain region 446b, a source electrode layer 447a, and a drain electrode layer 447b are formed. It is preferable to use materials having a high etching selectivity for each of the layers. For example, a metal oxide material containing Sn (e.g., SnZn Ox, SnGaZnOx, etc.) is used as the material constituting the oxide conductive layer, and Al-Z For example, nO-based materials, Al-Zn-ON-based materials, Zn-O-based materials, etc. may be used. Such zinc oxide-based materials can be etched using, for example, an alkaline solution. In addition, aluminum can be used in materials such as Al-Zn-O and Al-Zn-ON. When using a material containing It is preferable to remove the resist mask using a method that does not remove the oxide conductive layer together. For example, the resist mask is removed by dry etching, thereby forming the oxide conductive layer. Therefore, the resist mask can be removed without being removed.

[0317] Next, the resist masks 455a to 455c are removed, and then the source electrode layer 495a and the drain electrode layer 495b are A planarization insulating layer 45 is formed on the oxide insulating layer 466 and the conductive layer 495c. 4, a photolithography process is performed to form a resist mask, and a planarizing insulating layer 4 A contact hole 494 reaching the drain electrode layer 447b is formed by etching 54. (See Figure 46(B)).

[0318] Next, after removing the resist mask, a conductive film having light transmitting properties is formed, and then photolithography is performed. A resist mask is formed, and unnecessary parts are removed by etching to form pixel electrodes. A pole layer 477 is formed.

[0319] Through the above steps, the thin film transistor 490 and the thin film transistor 491 are formed on the same substrate using six masks. The film transistor 470 can be separately manufactured for the driver circuit or pixel portion, In addition, the number of masks can be reduced compared to the manufacturing process of the sixth embodiment. The transistor 490 includes a high-resistance source region 464a, a high-resistance drain region 464b, and a channel region 464c. A thin film transistor including an oxide semiconductor layer 462 including a panel formation region 463 is provided. The thin film transistor 470 has a high resistance source region 474a and a high resistance drain region 474b. and a thin film transistor including an oxide semiconductor layer 472 including a channel formation region 473. The thin film transistor 490 and the thin film transistor 470 have high resistance even when a high electric field is applied. A high-resistance source region 464a, a high-resistance drain region 464b, a high-resistance source region 474a, The anti-drain region 474b acts as a buffer to prevent localized electric field concentration, and the transistor insulation This structure improves edge pressure resistance.

[0320] In addition, in the method for manufacturing the semiconductor device of this embodiment mode, In the same process as the source electrode layer and the drain electrode layer, a conductive layer overlapping the channel formation region of the semiconductor layer is formed. This allows the device to be manufactured without increasing the number of steps. do. Note that this embodiment mode can be appropriately combined with other embodiment modes.

[0321] (Embodiment 8) In this embodiment mode, the active matrix substrate shown in Embodiment 1 is used to This embodiment shows an example of manufacturing a liquid crystal display device of a matrix type. The present invention can also be applied to the active matrix substrates shown in Nos. 2 to 7.

[0322] FIG. 7A shows an example of a cross-sectional structure of an active matrix substrate.

[0323] In the first to seventh embodiments, the thin film transistors of the driver circuit and the pixel section are formed on the same substrate. In the present embodiment, in addition to the above thin film transistors, The storage capacitor, the gate wiring, the terminal portion of the source wiring, and the wiring intersection portion are also illustrated. The terminals of the gate wiring and the source wiring and the wiring intersections are formed by the same method as in the first to seventh embodiments. It can be formed in the same process as any of the semiconductor device manufacturing processes, and the number of photomasks can be reduced. This can be fabricated without increasing the number of steps or adding additional processing. In the above-mentioned portion, the gate wiring, the source wiring, and the capacitor wiring layer are all made of a conductive film having light transmitting properties. This realizes a high aperture ratio. The layer can be made of metal wiring to reduce the wiring resistance. As an example of a thin film transistor for a driving circuit, a thin film transistor 440 shown in FIG. The case where the thin film transistor shown in FIG. 43 is used as an example of the thin film transistor in the pixel portion will be described. Although a case where a transistor 420 is used will be described, the present invention is not limited to this.

[0324] In FIG. 7A, a thin film transistor 210 is a thin film transistor provided in a driving circuit. The thin film transistor 220 electrically connected to the pixel electrode layer 227 is provided in the pixel portion. It is a thin film transistor that can be used

[0325] In this embodiment, the thin film transistor 220 formed above the substrate 200 is a thin film transistor shown in FIG. The thin film transistor 440 has the same structure as that of the thin film transistor 440 described above.

[0326] A layer formed of the same material and process as the gate electrode layer of the thin film transistor 220. The capacitor wiring layer 230 is connected to the capacitor electrode layer 231 via the gate insulating layer 202 which serves as a dielectric. The capacitor electrode layer 231 overlaps with the thin film transistor 220 to form a storage capacitor. A material having the same light-transmitting property as the source electrode layer or the drain electrode layer and formed in the same process Therefore, in addition to the thin film transistor 220 having light transmission properties, Since the film also has light-transmitting properties, the aperture ratio can be improved.

[0327] It is important for the storage capacitor to have light transmittance in order to improve the aperture ratio. In the following small LCD panels, the number of gate wirings is increased to improve the resolution of the displayed image. Even if the pixel size is reduced to achieve high resolution, a high aperture ratio can be achieved. By using a film having light transmitting properties as the constituent members of the thin film transistor 220 and the storage capacitor, To achieve a wide viewing angle, a high aperture ratio is achieved even when one pixel is divided into multiple sub-pixels. That is, even if a high density group of thin film transistors is arranged, a large aperture ratio can be obtained. For example, two to four pixels can be arranged in one pixel, and a sufficient area can be secured for the display area. When the device has four sub-pixels and a storage capacitor, the thin film transistor is transparent. In addition, each storage capacitor is transparent, so that the aperture ratio can be improved. do.

[0328] The storage capacitor is provided below the pixel electrode layer 227, and the capacitance electrode layer 231 is disposed below the pixel electrode layer 227. 227.

[0329] In this embodiment, a storage capacitor is formed using a capacitor electrode layer 231 and a capacitor wiring layer 230. However, the structure for forming the storage capacitor is not particularly limited. No line layer is provided, and the pixel electrode layer is connected to the gate wiring of the adjacent pixels, the planarization insulating layer, the oxide insulating layer, A storage capacitor may be formed by overlapping the gate insulating layer therebetween.

[0330] In addition, in FIG. 7A, the storage capacitor has a large capacitance, so the capacitance wiring and the capacitance electrode Only the gate insulating layer 202 is provided between the wirings, and the wiring intersections are provided with a gate insulating layer 202 to reduce parasitic capacitance. Between the gate wiring layer 232 and the wiring formed above it, the gate insulating layer 202 and the oxide insulating layer In order to increase the storage capacitance, the thickness of the gate insulating layer is made thin. Therefore, when the oxide insulating layer 266 is selectively etched, the capacitance wiring is not exposed to the insulating layer 266. The gate insulating layer may be thinned.

[0331] In addition, the gate wiring, source wiring, and capacitance wiring layer are provided in multiple lines according to the pixel density. In addition, in the terminal section, a terminal electrode having the same potential as the gate wiring, a A terminal electrode having the same potential as the capacitance wiring layer, a terminal electrode having the same potential as the capacitance wiring layer, etc. are arranged in a row. The number of terminal electrodes may be any number, and may be determined appropriately by the implementer. That's good.

[0332] In the terminal portion, the terminal electrode having the same potential as the gate line has the same light-transmitting property as the pixel electrode layer 227. The terminal electrode, which has the same potential as the gate wiring, can be formed of a material that can be used to The contact hole is electrically connected to the gate wiring. The tact hole is for connecting the drain electrode layer of the thin film transistor 220 and the pixel electrode layer 227. The same photomask as that for the contact holes for the electrical connection is used to form the planarized insulating layer 204. , the oxide insulating layer 266 and the gate insulating layer 202 are selectively etched.

[0333] In addition, the gate electrode layer of the thin film transistor 210 of the driving circuit is provided above the oxide semiconductor layer. In that case, the thin film transistor may be electrically connected to the conductive layer 405c. A contact for electrically connecting the drain electrode layer of the transistor 220 and the pixel electrode layer 227. Using the same photomask as that for the contact holes, the planarization insulating layer 204, the oxide insulating layer 266, The gate insulating layer 202 is selectively etched to form a contact hole. The conductive layer 405c and the gate electrode layer of the thin film transistor 210 of the driving circuit are connected to each other through a contact hole. and electrically connect them.

[0334] The terminal electrode layer 235, which has the same potential as the terminal electrode layer 234 of the driving circuit, is connected to the pixel electrode layer 227. The terminal electrode layer 235 can be formed of a material having the same light-transmitting property as the terminal electrode layer 23. 4. The terminal electrode is electrically connected to the terminal electrode layer 234 through a contact hole that reaches the terminal electrode 234. The layer 234 is a metal wiring, and is made of the same material and process as the source electrode layer of the thin film transistor 210. They are formed during the process and have the same potential.

[0335] The third terminal electrode having the same potential as the capacitance wiring layer 230 has the same light-transmitting property as the pixel electrode layer 227. In addition, the contact hole reaching the capacitance wiring layer 230 can be formed of a material having the above-mentioned properties. 2, which is a contact hole for electrically connecting the capacitance electrode layer 231 to the pixel electrode layer 227. They can be formed using the same photomask and the same process.

[0336] In addition, when an active matrix type liquid crystal display device is manufactured, A liquid crystal layer is provided between a substrate and a counter substrate on which a counter electrode (also called a counter electrode layer) is provided. The active matrix substrate and the opposing substrate are fixed together. A common electrode electrically connected to the electrode is provided on the active matrix substrate. A fourth terminal electrode is provided on the terminal portion for connecting the common electrode to the The fourth terminal electrode is a terminal for setting the potential, for example, GND, 0V, etc. It can be made of the same light-transmitting material as the pole layer 227 .

[0337] In addition, the gate electrode layer of the thin film transistor 210 of the driving circuit or the terminal having the same potential as the gate electrode layer The drain electrode layer or the drain electrode layer of the thin film transistor 210 of the driving circuit The potential terminal electrode is a contact hole provided by etching the gate insulating layer 202. For example, as shown in FIG. 7, the electrode 272 can be electrically connected to the gate electrode 272. The insulating layer 202 is electrically connected to the electrode 271 through a contact hole formed therein. At this time, it is preferable to remove part of the oxide insulating layer 266. A good contact can be obtained and the contact resistance can be reduced. The number of openings can be reduced, and the occupied area can be reduced.

[0338] In FIG. 7, the gate electrode layer of the thin film transistor 210 of the driver circuit A terminal electrode having the same potential as the drain electrode layer or a terminal electrode having the same potential as the drain electrode layer is connected to the gate. An example in which electrical connection is made through a contact hole provided in the insulating layer 202 will be described. However, the present invention is not limited to this, and the gate electrode layer or the gate A terminal electrode having the same potential as the drain electrode layer or a terminal electrode having the same potential as the drain electrode layer and are electrically connected to each other through a contact hole provided in the gate insulating layer 202. It can also be constructed as

[0339] In addition, the source electrode layer of the thin film transistor 220 and the source electrode layer of the thin film transistor 210 The configuration for electrically connecting the source of the thin film transistor 220 is not particularly limited. A connection electrode that connects the electrode layer and the source electrode layer of the thin film transistor 210 is formed on the pixel electrode layer 227. In addition, in the portion other than the display region, the thin film transistor 2 may be formed in the same process. The source electrode layer of the thin film transistor 20 and the source electrode layer of the thin film transistor 210 are overlapped in contact with each other. This is also fine.

[0340] The cross-sectional structure of the gate wiring layer 232 of the driving circuit is shown in FIG. Since this embodiment is an example of a small liquid crystal display panel of 10 inches or less, the gate wiring layer of the driving circuit is The gate electrode layer 232 is made of the same light-transmitting material as the gate electrode layer of the thin film transistor 220. do.

[0341] In addition, a gate electrode layer, a source electrode layer, a drain electrode layer, a pixel electrode layer, or other electrode layers If the same material is used for the other wiring layers, common sputtering targets and common manufacturing processes can be used. The equipment can be used, and the material cost and the etchant (or This reduces the cost of etching gas, resulting in reduced manufacturing costs. It is possible.

[0342] In the structure of FIG. 7A, a photosensitive resin material is used as the planarizing insulating layer 204. In this case, the step of forming a resist mask can be omitted.

[0343] FIG. 7B shows a cross-sectional structure that is partially different from that shown in FIG. Since the same as A) except that the planarization insulating layer 204 is not present, the same parts are designated by the same reference numerals. In FIG. 7B, the oxide insulating layer 266 is in contact with the oxide insulating layer 266. The pixel electrode layer 227 and the conductive layer 405c are formed on the terminal electrode layer 234. Form.

[0344] When the structure of FIG. 7B is used, the step of forming the planarization insulating layer 204 can be omitted.

[0345] (Embodiment 9) In this embodiment, the size of the liquid crystal display panel exceeds 10 inches, and is 60 inches or even When using a 120-inch display, the wiring resistance of the light-transmitting wiring may become a problem. An example in which a part of the gate wiring is made into a metal wiring to reduce the wiring resistance will be shown.

[0346] In FIG. 8(A), the same reference numerals are used for the same parts as in FIG. 7(A), and detailed explanations of the same parts will be omitted. Note that this embodiment mode is the same as the embodiment mode 1 to 7. can be applied to.

[0347] FIG. 8A shows a gate wiring of a driving circuit that is partly made of metal wiring, and a thin film transistor 210 In this example, the gate electrode layer is formed in contact with a wiring having the same light-transmitting property as the gate electrode layer. Therefore, the number of photomasks increases compared to the eighth embodiment.

[0348] First, a material capable of withstanding a first heat treatment for dehydration or dehydrogenation is provided on the substrate 200. A heat-resistant conductive material film (thickness: 100 nm to 500 nm) is formed.

[0349] In this embodiment, a tungsten film with a thickness of 370 nm and a tantalum nitride film with a thickness of 50 nm are used. Here, the conductive film is a laminate of a tantalum nitride film and a W film, but there is no particular limitation. An element selected from Ta, W, Ti, Mo, Al, and Cu, or a composite material containing the above elements. Formed from gold, an alloy film combining the above elements, or a nitride containing the above elements The heat-resistant conductive material film is not limited to a single layer containing the above-mentioned elements, but may be a laminate of two or more layers. It can be used.

[0350] A metal wiring is formed by a first photolithography process, and a first metal wiring layer 236 and a second The metal wiring layer 237 is formed. The tungsten film and the tantalum nitride film are etched using I CP (Inductively Coupled Plasma) The etching method is recommended. The ICP etching method is used, and the etching conditions (coil type) The amount of power applied to the electrode, the amount of power applied to the electrode on the substrate side, the electrode temperature on the substrate side, etc. By appropriately adjusting the thickness, the film can be etched into a desired tapered shape. The metal wiring layer 236 and the second metal wiring layer 237 are tapered to be in contact with each other. This can reduce defects in the formation of a light-transmitting conductive film.

[0351] Next, a light-transmitting conductive film is formed, and then a gate is formed by a second photolithography process. The wiring layer 238, the gate electrode layer of the thin film transistor 210, the gate The light-transmitting conductive film is transparent to visible light as described in Embodiment 1. A conductive material having optical properties is used.

[0352] Depending on the material of the conductive film having light transmitting properties, for example, the gate wiring layer 238 may be a first gold If there is an interface in contact with the metal wiring layer 236 or the second metal wiring layer 237, the interface may be damaged by a subsequent heat treatment or the like. Therefore, the second metal wiring layer 237 is It is preferable to use a metal nitride film that prevents the first metal wiring layer 236 from being oxidized.

[0353] Next, a gate insulating layer and an oxide film are formed in the same process as in any one of the processes of the first to seventh embodiments. The subsequent steps are performed in accordance with the first embodiment. A substrate is prepared.

[0354] In this embodiment, after the planarization insulating layer 204 is formed, the terminal This shows an example of selectively removing the planarizing insulating layer in the terminal area. It is preferable not to do this in order to ensure a good connection with the FPC.

[0355] In addition, the wiring intersection is formed in the gate wiring layer 238 and above in order to reduce parasitic capacitance. A gate insulating layer 202 and an oxide insulating layer 266 are provided between the wirings. In order to increase the amount of GaN, it is preferable to make the gate insulating layer thinner. The gate insulating layer on the capacitance wiring is thinned during selective etching of the edge layer 266. You may do so.

[0356] In FIG. 8(A), the terminal electrode layer 235 is formed on the terminal electrode layer 234. In A), the gate wiring layer 238 is shown overlapping a part of the second metal wiring layer 237. Alternatively, the first metal wiring layer 236 and the second metal wiring layer 237 may be entirely covered by the gate wiring layer. That is, the first metal wiring layer 236 and the second metal wiring layer 237 form a gate wiring layer 238. It can be said to be an auxiliary wiring for reducing resistance.

[0357] In the terminal portion, the first terminal electrode layer 234, which has the same potential as the gate wiring, is 03 and electrically connects to the second metal wiring layer 237. The lines are also formed from metal wiring.

[0358] In addition, the gate wiring layer and the capacitance wiring layer in the non-display area are made to have low wiring resistance. Metal wiring, that is, the first metal wiring layer 236 and the second metal wiring layer 237 are used as auxiliary wiring. It can also be used.

[0359] Also, a gate electrode layer of a thin film transistor of a driving circuit or a terminal electrode having the same potential as the gate electrode layer and a terminal voltage having the same potential as the drain electrode layer or the drain electrode layer of the thin film transistor of the driver circuit. The electrode is electrically connected to the gate insulating layer 202 via a contact hole formed by etching the gate insulating layer 202. For example, as shown in FIG. 8, the electrode 272 can be electrically connected to the gate insulating layer 20. 2, a metal wiring layer 283 is provided on the upper part through a contact hole provided in the The wiring layer 281 and the metal wiring layer 282 can be electrically connected to each other. A part of the oxide insulating layer 266 may be removed in advance. This allows for good contact. Therefore, the number of openings can be reduced. This reduction in size allows for a reduction in the area occupied.

[0360] In FIG. 8, the gate electrode layer of the thin film transistor of the driver circuit or the gate electrode layer The terminal electrode and the drain electrode layer or a terminal electrode having the same potential as the drain electrode layer are connected to a gate insulator. The example in which electrical connection is made via a contact hole provided in layer 202 has been described. However, the present invention is not limited to this, and may be applied to a gate electrode layer of a thin film transistor in a pixel portion or a gate electrode layer of the same layer. A terminal electrode having a potential equal to that of the drain electrode layer or the drain electrode layer is connected to the gate A structure in which electrical connection is made via a contact hole provided in the insulating layer 202 It is also possible.

[0361] FIG. 8B shows a cross-sectional structure that is partially different from that shown in FIG. A) is the same as A, except that the material of the gate electrode layer of the thin film transistor in the driver circuit is different. Therefore, the same reference numerals are used for the same parts, and detailed explanations of the same parts are omitted.

[0362] FIG. 8B shows an example in which the gate electrode layer of the thin film transistor of the driver circuit is formed of a metal wiring. In the driver circuit, the material for the gate electrode layer is not limited to a light-transmitting material.

[0363] In FIG. 8B, a thin film transistor 240 of the driving circuit is formed by metal wiring on a metal wiring layer 241. The metal wiring layer 241 is a gate electrode layer formed by stacking the metal wiring layer 242. The metal wiring layer 242 can be formed of the same material and in the same process as the second It can be formed using the same material and process as the metal wiring layer 237.

[0364] In addition, when the metal wiring layer 241 is electrically connected to the conductive layer 405c, To prevent oxidation, the metal wiring layer 242 is preferably a metal nitride film.

[0365] In this embodiment, the wiring resistance is reduced by partially using metal wiring, and the size of the liquid crystal display panel is Even if the display size exceeds 10 inches and is increased to 60 inches or even 120 inches, It is possible to achieve high definition and a high aperture ratio.

[0366] (Embodiment 10) In this embodiment, a configuration of a storage capacitor different from that of the eighth embodiment is shown in FIG. FIG. 9(B) shows the same as FIG. 7(A) except for the configuration of the storage capacitor. Therefore, the same parts are designated by the same reference numerals, and detailed explanations of the same parts are omitted. 1A shows the cross-sectional structure of a thin film transistor 220 and a storage capacitor in a pixel portion.

[0367] FIG. 9(A) shows a dielectric layer including an oxide insulating layer 266, a protective insulating layer 203, and a planarizing insulating layer 20. 4, a pixel electrode layer 227 and a capacitance electrode layer 231 overlapping the pixel electrode layer 227 form a storage capacitance. The capacitor electrode layer 231 is an example of forming a source of the thin film transistor 220 in the pixel portion. Since the electrode layer is formed of the same material having the same light-transmitting property and in the same process, the thin film transistor 2 It is laid out so as not to overlap with the source wiring layer 20.

[0368] In the storage capacitor shown in FIG. 9A, a pair of electrodes and a dielectric material are transparent, and the entire storage capacitor The body is translucent.

[0369] FIG. 9B shows an example of a storage capacitor configuration different from that shown in FIG. 9A. Since this is the same as 7(A) except for the difference in the configuration of the storage capacitor, the same symbols are used for the same parts. Detailed explanations of the same parts will be omitted.

[0370] FIG. 9B shows a capacitor wiring layer 230 and an oxide semiconductor layer 251 overlapping the capacitor wiring layer 230. In this example, a storage capacitor is formed by laminating an oxide semiconductor layer 25 and a capacitance electrode layer 231. 1 is laminated under and in contact with the capacitance electrode layer 231 and functions as one electrode of the storage capacitance. The capacitive electrode layer 231 is a source electrode layer or a drain electrode layer of the thin film transistor 220. The capacitor wiring layer 230 is formed of the same material having the same light-transmitting property as the electrode layer, and in the same process. Since the gate electrode layer of the transistor 220 is formed using the same material and process as the gate electrode layer of the transistor 220, Therefore, it is laid out so as not to overlap with the gate wiring layer of the thin film transistor 220.

[0371] In addition, the capacitive electrode layer 231 is electrically connected to the pixel electrode layer 227 .

[0372] The storage capacitor shown in FIG. 9B also has a pair of electrodes and a dielectric material that are transparent, and the entire storage capacitor The body is translucent.

[0373] The storage capacitor shown in FIG. 9(A) and FIG. 9(B) has a light-transmitting property, and the number of gate wirings is In order to increase the resolution of displayed images, it is necessary to increase the capacity of the display even if the pixel size is reduced. It is possible to obtain a high aperture ratio.

[0374] This embodiment mode can be appropriately combined with other embodiment modes.

[0375] (Embodiment 11) In this embodiment, at least a part of the driver circuit and a semiconductor device disposed in a pixel portion are formed on the same substrate. Exemplary devices are described below.

[0376] The thin film transistor disposed in the pixel portion is formed according to any one of the first to seventh embodiments. The thin film transistors described in any of the embodiments 1 to 7 are n-channel TFTs. Therefore, some of the driver circuits can be configured with n-channel TFTs. The thin film transistors in the pixel portion are formed on the same substrate.

[0377] An example of a block diagram of an active matrix display device is shown in FIG. A pixel portion 5301, a first scanning line driver circuit 5302, a second scanning line driver circuit 5303, and a third scanning line driver circuit 5304 are provided on a substrate 5300. The pixel portion 5301 includes a signal line driver circuit 5303 and a signal line driver circuit 5304. are arranged extending from a signal line driver circuit 5304, and a plurality of scanning lines are arranged in a first scanning line driver circuit The first scanning line driver circuit 5302 and the second scanning line driver circuit 5303 are arranged to extend from each other. At the intersections of the signal lines and the display elements, pixels each having a display element are arranged in a matrix. In addition, the substrate 5300 of the display device is a flexible printed circuit board (FPC). A timing control circuit 5305 (controller, control Also called an IC.

[0378] In FIG. 14A, a first scanning line driver circuit 5302, a second scanning line driver circuit 5303, a signal The line driver circuit 5304 is formed on the same substrate 5300 as the pixel portion 5301. This reduces the number of external components such as drive circuits, and therefore reduces costs. In addition, when a driving circuit is provided outside the substrate 5300, the wiring is extended to provide a connection portion. The number of connections can be reduced, and the reliability and yield can be improved.

[0379] The timing control circuit 5305 is, for example, The first scanning line driving circuit start signal (GSP1), the first scanning line driving circuit clock The timing control circuit 5305 also supplies a second scan line driver (GCK1). For example, a start signal for the second scanning line driver circuit (GSP2) is (also called start pulse), supplies the clock signal (GCK2) for the second scanning line driver circuit In addition, the timing control circuit 5305 is, for example, The signal line driver circuit start signal (SSP), the signal line driver circuit clock signal (SCK ), data for video signal (DATA) (also simply called video signal), latch signal (LAT Each clock signal may be a plurality of clock signals with different periods. The signal may be supplied together with an inverted signal (CKB) of the lock signal. By omitting either the first scanning line driver circuit 5302 or the second scanning line driver circuit 5303, is possible.

[0380] In FIG. 14B, a circuit with a low driving frequency (for example, the first scanning line driving circuit 5302, The second scanning line driver circuit 5303) is formed on the same substrate 5300 as the pixel portion 5301, and the signal line driver The configuration in which the driving circuit 5304 is formed on a substrate different from that of the pixel portion 5301 is shown. Due to its structure, the field effect mobility is smaller than that of a transistor using a single crystal semiconductor. The driving circuit formed on the substrate 5300 can be configured by the thin film transistor. Therefore, it is possible to increase the size of the display device, reduce the number of steps, reduce costs, or improve yields. It is possible to plan this.

[0381] The thin film transistors described in any of the embodiments 1 to 7 are n-channel TFTs. In FIG. 15(A) and FIG. 15(B), a signal line driver circuit configured with an n-channel TFT is shown. An example of the configuration and operation will be described.

[0382] The signal line driver circuit includes a shift register 5601 and a switching circuit 5602 . The switching circuit 5602 includes a plurality of switching circuits. 02_1 to 5602_N (N is a natural number of 2 or more) are thin film transistors 5603_ It has multiple transistors, numbered 1 to 5603_k (k is a natural number of 2 or more). An example in which the transistors 5603_1 to 5603_k are N-channel TFTs will be described.

[0383] The connection relationship of the signal line driver circuit will be described using the switching circuit 5602_1 as an example. The first terminals of the thin film transistors 5603_1 to 5603_k are respectively connected to the wiring 5604_1 The second terminals of the thin film transistors 5603_1 to 5603_k are connected to are connected to the signal lines S1 to Sk, respectively. The gate of k is connected to the wiring 5605_1.

[0384] The shift register 5601 sequentially outputs H level (H signal) to the wirings 5605_1 to 5605_N. , or high power supply potential level), and the switching circuits 5602_1 to 56 It has the function of selecting 02_N in sequence.

[0385] The switching circuit 5602_1 includes wirings 5604_1 to 5604_k and signal lines S1 to Sk. The function of controlling the conduction state (conduction between the first terminal and the second terminal) with the wiring 5604_ The switches have a function of controlling whether or not potentials of 1 to 5604_k are supplied to the signal lines S1 to Sk. In this way, the switching circuit 5602_1 has a function as a selector. The film transistors 5603_1 to 5603_k are connected to the wirings 5604_1 to 5604_k, respectively. and the signal lines S1 to Sk, that is, the wirings 5604_1 to 5604_k The thin film transistor 56 has a function of supplying the potential to the signal lines S1 to Sk. Each of 03_1 to 5603_k has a function as a switch.

[0386] In addition, the wirings 5604_1 to 5604_k each carry video signal data (DATA). The video signal data (DATA) is an analog signal corresponding to the image information or image signal. This is often a signal that

[0387] Next, the operation of the signal line driver circuit of FIG. 15(A) will be described with reference to the timing chart of FIG. 15(B). FIG. 15B shows signals Sout_1 to Sout_N and An example of Vdata_1 to Vdata_k is shown. These are examples of output signals of the shift register 5601, and signals Vdata_1 to Vdata _k are examples of signals input to the wirings 5604_1 to 5604_k, respectively. One operation period of the signal line driving circuit corresponds to one gate selection period in the display device. The selection period is divided into periods T1 to TN, for example. This is a period for writing video signal data (DATA) to the pixels belonging to the selected row. be.

[0388] In the drawings of the present embodiment, the signal waveforms of the components are not rounded for clarity. Therefore, the scale may not necessarily be limited to the actual scale. It should be noted that

[0389] During the period T1 to the period TN, the shift register 5601 outputs an H-level signal to the wiring 560 For example, in the period T1, the shift registers 5 601 outputs a high-level signal to the wiring 5605_1. Since 5603_1 to 5603_k are turned on, wiring 5604_1 to 5604_k and signal At this time, the wirings 5604_1 to 5604_k are in a conductive state. Data(S1)~Data(Sk) are input. Data(S1)~Data(Sk ) belong to a selected row via thin film transistors 5603_1 to 5603_k. In this way, during the periods T1 to TN, Then, the video signal data (DATA) is sent to the pixels in the selected row in order of k columns. It will be written.

[0390] As described above, video signal data (DATA) is written to the pixels in multiple columns. This makes it possible to reduce the number of video signal data (DATA) or the number of wirings. This reduces the number of connections to external circuits. By writing directly to the memory, the writing time can be increased, and the video signal can be written more quickly. This can prevent under-crowding.

[0391] The shift register 5601 and the switching circuit 5602 may be the same as those in the first embodiment. It is possible to use a circuit configured with the thin film transistors shown in the seventh embodiment. In this case, the polarity of all the transistors in the shift register 5601 is changed to N-channel type, can be constructed of only one polarity of P-channel type.

[0392] Furthermore, a part of the scanning line driving circuit and the signal line driving circuit, or the scanning line driving circuit or the signal line An example of a shift register used as part of a driver circuit will be described.

[0393] The scanning line driving circuit has a shift register. In some cases, it may also have a level shifter or a buffer. In the scanning line driver circuit, a clock signal is input to the shift register. The selection signal is generated by inputting the clock (CLK) and start pulse signal (SP). The generated selection signal is buffered and amplified in a buffer and then supplied to the corresponding scan line. The gate electrodes of the transistors of the pixels for one line are connected to the scanning line. Since the transistors of the pixels in one line must be turned on simultaneously, The capacitor used is capable of carrying a large current.

[0394] Furthermore, a part of the scanning line driving circuit and the signal line driving circuit, or the scanning line driving circuit or the signal line One form of a shift register used in a part of a driving circuit will be explained with reference to FIGS. 16 and 17. do.

[0395] The shift register includes a first pulse output circuit 10_1 to an N-th pulse output circuit 10_N ( N is a natural number of 3 or more (see FIG. 16(A)). The first pulse output circuit 10_1 to the N-th pulse output circuit 10_N of the register are A first clock signal CK1 is transmitted from a wiring 11, and a second clock signal CK2 is transmitted from a second wiring 12. , a third clock signal CK3 is output from a third wiring 13, and a fourth clock signal CK4 is output from a fourth wiring 14. In the first pulse output circuit 10_1, a signal CK4 is supplied from the fifth wiring 15. A start pulse SP1 (first start pulse) is input. In the pulse output circuit 10_n (n is a natural number between 2 and N), A signal from the line 10_(n-1) (called the previous stage signal OUT(n-1)) is input. The first pulse output circuit 10_1 receives a signal from the third pulse output circuit 10_3, which is two stages behind. In the n-th pulse output circuit 10_n in the second stage or later, the (n+2 ) the signal from the pulse output circuit 10_(n+2) (called the next stage signal OUT(n+2)) Therefore, the pulse output circuit of each stage outputs the pulses of the following stage and / or the two stages before it. a first output signal OUT(1)(SR) through OUT(N)(SR) for input to the input circuit; The second output signals OUT(1) to OUT(N) are outputted to be inputted to another circuit or the like. As shown in FIG. 16A, the last two stages of the shift register are connected to the rear stage signal OUT Since (n+2) is not input, for example, the second start pulse SP2 and the third The start pulse SP3 may be input to each of the first and second inputs.

[0396] The clock signal (CK) goes between H and L levels (L signal, low power supply potential) at regular intervals. Here, the first clock signal (CK1) to the second clock signal (CK2) are The fourth clock signal (CK4) is delayed by 1 / 4 cycle in sequence. The first clock signal (CK1) to the fourth clock signal (CK4) are used to generate a pulse output circuit. The clock signal is GCK depending on the input drive circuit. It is sometimes called SCK, but here we will use the term CK for explanation.

[0397] The first input terminal 21, the second input terminal 22, and the third input terminal 23 are connected to the first wiring 11. 16A to 14. In the first pulse output circuit 10_1, the first input terminal 21 is electrically connected to the first wiring 11. The second input terminal 22 is electrically connected to the second wiring 12, and the third input terminal 23 is electrically connected to the is electrically connected to the third wiring 13. In addition, the second pulse output circuit 10_2 is The first input terminal 21 is electrically connected to the second wiring 12, and the second input terminal 22 is The third input terminal 23 is electrically connected to the fourth wiring 14. is.

[0398] Each of the first pulse output circuit 10_1 to the N-th pulse output circuit 10_N has a first input terminal a first input terminal 21, a second input terminal 22, a third input terminal 23, a fourth input terminal 24, a fifth input terminal The input terminal 25, the first output terminal 26, and the second output terminal 27 (see FIG. 16(B)). In the first pulse output circuit 10_1, a first clock signal is input to a first input terminal 21. A first clock signal CK1 is input to the first input terminal 22, a second clock signal CK2 is input to the third input terminal 23, and a third clock signal CK3 is input to the second input terminal 24. A third clock signal CK3 is input to the input terminal 23 of the second clock CLK1, and a start signal CK4 is input to the fourth input terminal 24 of the third clock CLK2. A pulse is input, the next stage signal OUT(3) is input to the fifth input terminal 25, and the first output A first output signal OUT(1)(SR) is output from a terminal 26, and a second output signal OUT(1)(SR) is output from a second output terminal 27. The second output signal OUT(1) is output.

[0399] The first pulse output circuit 10_1 to the N-th pulse output circuit 10_N are each a three-terminal thin-film transistor. In addition to TFTs (also called Thin Film Transistors), The four-terminal thin film transistor described in the above embodiment can be used. In the document, when a thin film transistor has two gate electrodes via a semiconductor layer, The gate electrode below the semiconductor layer is called the lower gate electrode, and the gate electrode above the semiconductor layer is called the upper gate electrode. It is also called the gate electrode.

[0400] When an oxide semiconductor is used for a semiconductor layer including a channel formation region of a thin film transistor, The threshold voltage may shift to the negative or positive side depending on the process. Therefore, in a thin film transistor in which an oxide semiconductor is used for a semiconductor layer including a channel formation region, A configuration capable of controlling the threshold voltage is preferable. The threshold voltage is determined by gate insulating films provided above and below the channel formation region of a thin-film transistor. By providing a gate electrode and controlling the potential of the upper and / or lower gate electrodes, a desired The value can be controlled.

[0401] Next, an example of a specific circuit configuration of the pulse output circuit will be described with reference to FIG.

[0402] The first pulse output circuit 10_1 includes a first transistor 31 to a thirteenth transistor 43. In addition, the first input terminal 21 to the fifth input terminal 25 and the first output In addition to the first input terminal 26 and the second output terminal 27, a power supply line 5 to which a first high power supply potential VDD is supplied is also provided. 1, a power supply line 52 to which a second high power supply potential VCC is supplied, A signal or The power supply potential is supplied to the power supply lines. The magnitude relationship of the power supply potentials of the power supply lines in FIG. 16C is as follows: The first power supply potential VDD is set to a potential equal to or higher than the second power supply potential VCC, and the second power supply potential VCC is set to The potential is set to be higher than the third power supply potential VSS. The fourth clock signal (CK4) is a signal that alternates between H and L levels at regular intervals. Assume that the potential at the H level is VDD and the potential at the L level is VSS. In this case, the potential VDD of the power supply line 51 is set higher than the potential VCC of the power supply line 52. The potential applied to the gate electrode of the transistor can be kept low without affecting the This can reduce the shift in the threshold voltage of the transistor and suppress deterioration. Among the first transistor 31 to the thirteenth transistor 43, the first transistor 31, The sixth transistor 36 to the ninth transistor 39 are four-terminal transistors. It is preferable that the first transistor 31, the sixth transistor 36 to the ninth transistor The operation of the transistor 39 is performed by the gate electrodes of the transistors 33 and 40. A transistor in which the potential of the gate electrode is switched by a control signal. The response to the control signal input to the pole is fast (the rise of the on-current is steep), This reduces the risk of malfunction in the pulse output circuit. This allows the threshold voltage to be controlled, resulting in a pulse output that can reduce malfunctions. It can be a circuit.

[0403] A thin film transistor is defined as a transistor having at least three elements including a gate, a drain, and a source. A thin film transistor is an element having a terminal. A thin film transistor has a channel in a region overlapping with a gate. It has a semiconductor region (also called a channel formation region) in which a region is formed, and controls the potential of the gate By this, it is possible to control the current flowing between the drain and the source through the channel region. Here, the source and drain can be determined depending on the structure and operating conditions of the thin film transistor. Since the capacitance varies depending on the semiconductor device, it is difficult to determine which is the source and which is the drain. Here, the regions that function as a source and a drain are not called a source or a drain. In that case, for example, they may be written as the first terminal and the second terminal, respectively. do.

[0404] In FIG. 16C, the first transistor 31 has a first terminal electrically connected to a power supply line 51. a second terminal electrically connected to a first terminal of a ninth transistor 39; (the first gate electrode and the second gate electrode) are electrically connected to the fourth input terminal 24. The second transistor 32 has a first terminal electrically connected to the power supply line 53 and a second terminal a gate electrode electrically connected to the first terminal of the ninth transistor 39 and a gate electrode electrically connected to the first terminal of the fourth transistor The third transistor 33 is electrically connected to the gate electrode of the first terminal The first terminal is electrically connected to the first input terminal 21, and the second terminal is electrically connected to the first output terminal 26. The fourth transistor 34 has a first terminal electrically connected to the power supply line 53, The second terminal is electrically connected to the first output terminal 26. The fifth transistor 35 is The first terminal is electrically connected to the power supply line 53, and the second terminal is connected to the gate of the second transistor 32. The electrode of the fourth transistor 34 is electrically connected to the gate electrode of the fourth transistor 34. The sixth transistor 36 has a first terminal electrically connected to the power supply line 52, and the second terminal is electrically connected to the gate electrode of the second transistor 32 and the gate electrode of the fourth transistor 33. The gate electrode (first gate electrode and The gate electrode of the seventh transistor (2) is electrically connected to the fifth input terminal 25. The eighth transistor 37 has a first terminal electrically connected to the power supply line 52 and a second terminal electrically connected to the eighth transistor 38. and a gate electrode (a first gate electrode and a second gate electrode) electrically connected to the second terminal of the is electrically connected to the third input terminal 23. The eighth transistor 38 is is electrically connected to the gate electrode of the second transistor 32 and the gate electrode of the fourth transistor 34. and the gate electrodes (the first gate electrode and the second gate electrode) are connected to the second input terminal The ninth transistor 39 has a first terminal electrically connected to the first transistor 22. The second terminal is electrically connected to the second terminal of the second transistor 31 and the second terminal of the second transistor 32. The gate electrode of the third transistor 33 and the gate electrode of the tenth transistor 40 are connected to The gate electrodes (the first gate electrode and the second gate electrode) are electrically connected to the power supply line 52. The tenth transistor 40 has a first terminal electrically connected to the first input terminal 2. 1, the second terminal is electrically connected to the second output terminal 27, and the gate electrode is electrically connected to the second terminal of the ninth transistor 39. 41 has a first terminal electrically connected to the power supply line 53 and a second terminal electrically connected to the second output terminal 27. The gate electrodes of the second transistor 32 and the fourth transistor The twelfth transistor 42 is electrically connected to the gate electrode of the first terminal of the transistor 34. The first terminal is electrically connected to the power supply line 53, and the second terminal is electrically connected to the second output terminal 27. The gate electrode of the seventh transistor 37 (the first gate electrode and the second gate electrode) The thirteenth transistor 43 has a first terminal electrically connected to the power supply line 5 3, the second terminal is electrically connected to the first output terminal 26, and the gate electrode The gate electrodes (first gate electrode and second gate electrode) of the seventh transistor 37 are electrically connected to the are electrically connected.

[0405] In FIG. 16C, the gate electrode of the third transistor 33 and the gate electrode of the tenth transistor 4 The connection point of the gate electrode of transistor 0 and the second terminal of transistor 939 is referred to as node A. In addition, the gate electrode of the second transistor 32, the gate electrode of the fourth transistor 34, the second terminal of the fifth transistor 35, the second terminal of the sixth transistor 36, the second terminal of the eighth transistor The connection point of the first terminal of the transistor 38 and the gate electrode of the eleventh transistor 41 is node B. Let us assume that.

[0406] In addition, in FIG. 16(C) and FIG. 17(A), node A is made floating, so that the boost A capacitor may be provided separately to perform a test strap operation. In order to maintain the capacitance, a capacitor having one electrode electrically connected to the node B may be provided separately.

[0407] Here, the timing of the shift register having a plurality of pulse output circuits shown in FIG. The shift register is a scanning line driver circuit. In this case, the period 61 in FIG. 17(B) is a vertical blanking period, and the period 62 corresponds to a gate selection period. Correct.

[0408] As shown in FIG. 17A, the ninth transistor in which the second power supply potential VCC is applied to the gate electrode By providing the transistor 39, the following can be achieved before and after the bootstrap operation: The advantages are as follows:

[0409] In the absence of the ninth transistor 39 having the gate electrode to which the second potential VCC is applied, the boot When the potential of the node A rises due to the strap operation, the second terminal of the first transistor 31 The potential of the source, which is the first power supply potential VDD, increases and becomes higher than the first power supply potential VDD. The source of the first transistor 31 is switched to the first terminal side, that is, the power supply line 51 side. In the first transistor 31, the gate and source, and the gate and drain are In addition, a large bias voltage is applied, which causes a large stress and leads to deterioration of the transistor. Therefore, the ninth transistor, whose gate electrode is applied with the second power supply potential VCC, By providing the transistor 39, the potential of the node A is set by the bootstrap operation. However, the potential of the second terminal of the first transistor 31 does not increase. That is, by providing the ninth transistor 39, The negative bias voltage applied between the gate and source of the transistor 31 can be reduced. Therefore, by using the circuit configuration of this embodiment, the gate of the first transistor 31 The negative bias voltage applied between the gate and source can also be reduced, reducing the first-order This makes it possible to suppress the deterioration of the transistor 31.

[0410] The ninth transistor 39 is provided at a position corresponding to the second gate of the first transistor 31. A terminal is connected between the terminal and the gate of the third transistor 33 via a first terminal and a second terminal. In addition, in the present embodiment, a system having a plurality of pulse output circuits may be provided. In the case of a soft register, the signal line driver circuit has more stages than the scan line driver circuit. The resistor 39 may be omitted, thereby reducing the number of transistors.

[0411] In addition, the semiconductor layers of the first transistor 31 to the thirteenth transistor 43 are made of an oxide By using a semiconductor, the off-current of the thin film transistor is reduced, and the on-current and The field effect mobility can be increased and the degree of degradation can be reduced. Therefore, malfunctions in the circuit can be reduced. Compared to transistors using amorphous silicon, a high potential is applied to the gate electrode. Therefore, the degree of deterioration of the transistor due to the second power supply potential VCC is small. The same operation can be obtained by supplying the first power supply potential VDD to the power supply line. Since the number of power lines to be routed can be reduced, the circuit can be made more compact.

[0412] The gate electrodes (first gate electrode and second gate electrode) of the seventh transistor 37 a clock signal provided by the third input terminal 23 to the gate of the eighth transistor 38; A second input terminal 22 supplies a potential to the first gate electrode and the second gate electrode. The clock signal is applied to the gate electrode of the seventh transistor 37 (the gate electrode of the first transistor and the gate electrode of the second transistor). A clock signal is supplied to the gate electrode of the eighth transistor by the second input terminal 22. The third input terminal 23 is connected to the gate electrodes (the first gate electrode and the second gate electrode) of the transistor 38. The same effect can be obtained by swapping the wiring so that the clock signal is supplied by At this time, in the shift register shown in FIG. The seventh transistor 37 is turned off, and the eighth transistor 38 is turned on. The first transistor 38 is on, then the seventh transistor 37 is off, and the eighth transistor By turning off the input terminal 38, the second input terminal 22 and the third input terminal 23 are The voltage drop at node B is generated by the gate of the seventh transistor 37. due to a drop in the potential of the gate electrode of the eighth transistor 38 and a drop in the potential of the gate electrode of the eighth transistor 39. On the other hand, in the shift register shown in FIG. The seventh transistor 37 and the eighth transistor 38 are both in an on state. 7 is on, the eighth transistor 38 is off, then the seventh transistor 37 is off. By turning off the eighth transistor 38, the second input terminal 22 and The voltage drop at the node B caused by the voltage drop at the input terminal 23 of the third transistor is The potential of the gate electrode of the transistor 38 can be reduced to one time. The gate electrodes (first gate electrode and second gate electrode) of the seventh transistor 37 are connected to the third A clock signal is supplied from the input terminal 23, and the gate electrode of the eighth transistor 38 (the first A clock signal is supplied to the first gate electrode and the second gate electrode from a second input terminal 22. This is because the number of times the potential of node B changes is reduced. This is because it is possible to further reduce noise.

[0413] In this manner, the potentials of the first output terminal 26 and the second output terminal 27 are maintained at the L level. By configuring the node B to periodically receive a high-level signal during the period, the pulse output This makes it possible to suppress malfunction of the power circuit.

[0414] (Embodiment 12) A thin film transistor is manufactured, and the thin film transistor is used in a pixel portion and further in a driver circuit. It is possible to manufacture a semiconductor device (also called a display device) having a display function. A part or the whole of a driver circuit having a transistor is integrally formed on the same substrate as the pixel portion, A system panel can be formed.

[0415] The display device includes a display element. The display element may be a liquid crystal element (also called a liquid crystal display element), a light-emitting A light-emitting element (also called a light-emitting display element) can be used. A light-emitting element emits light by applying a current or a voltage. This category includes elements whose brightness is controlled by a specific factor, such as inorganic EL (Electroluminescent) devices. Luminescence elements, organic electroluminescence elements, etc. Also, electronic ink, etc. A display medium in which the contrast changes due to electrical effects can also be used.

[0416] The display device includes a panel in which a display element is sealed, and a controller for the panel. and a module in which an IC or the like including the above is mounted. In the process, the element substrate corresponds to one form before the display element is completed, and the element substrate is The display substrate includes a plurality of pixels, each of which is provided with a means for supplying a current to the display element. Alternatively, only the pixel electrode (also called a pixel electrode layer) of the display element may be formed. After the conductive film that will become the pixel electrode is formed, but before the pixel electrode is formed by etching, It may be in one form or another, and any form is applicable.

[0417] In this specification, the term "display device" refers to an image display device, a display device, or an optical device. Also refers to connectors, such as FPC (Flexible Printed Circuit). inted circuit), TAB (Tape Automated Bondin) g) Tape or TCP (Tape Carrier Package) is attached Modules with printed wiring boards on the ends of TAB tape or TCP Or, the display element is equipped with an IC (integrated circuit) by the COG (Chip On Glass) method. All directly mounted modules are also included in the display device.

[0418] The appearance and cross section of a liquid crystal display panel, which is one embodiment of a semiconductor device, will be described with reference to FIG. FIG. 10(A1) and FIG. 10(A2) show thin film transistors 4010 and 4011. 4006 and a liquid crystal element 4013 are disposed between the first substrate 4001 and the second substrate 4006 by a sealant. FIG. 10(B) is a plan view of the panel sealed with 4005. A2) corresponds to the cross-sectional view at MN.

[0419] A pixel portion 4002 and a scanning line driver circuit 4004 are provided on a first substrate 4001. In this manner, a sealant 4005 is provided. A second substrate 4006 is provided on the path 4004. The line driver circuit 4004 is made up of a first substrate 4001, a sealant 4005, and a second substrate 4006. The liquid crystal layer 4008 is sealed together with the first substrate 4001. In a region different from the region surrounded by the material 4005, a single crystal is formed on a separately prepared substrate. A signal line driver circuit 4003 formed of a semiconductor film or a polycrystalline semiconductor film is mounted.

[0420] The method of connecting the separately formed drive circuit is not particularly limited, and may be a COG method, A wire bonding method, a TAB method, or the like can be used. FIG. 10A shows an example of mounting a signal line driver circuit 4003 by the COG method. This is an example in which a signal line driver circuit 4003 is mounted by the TAB method.

[0421] In addition, a pixel portion 4002 and a scanning line driver circuit 4004 are provided on a first substrate 4001. In FIG. 10B, the thin film transistor included in the pixel portion 4002 is A thin film transistor 4010 and a thin film transistor 401 included in a scanning line driver circuit 4004 1 is shown. An oxide insulating layer 404 is formed on the thin film transistors 4010 and 4011. 1, a protective insulating layer 4020, and an insulating layer 4021 are provided in this order.

[0422] The thin film transistors 4010 and 4011 each include the oxide semiconductor layer described in any of Embodiments 1 to 7. Thin film transistors with high reliability, including thin film transistors for driving circuits, can be used. The transistor 4011 may be, for example, the thin film transistor 410 or 411 shown in any one of the first to seventh embodiments. 40, 449, 460, 490, or 492 can be used, and thin film transistors for pixels can be used. The transistor 4010 may be, for example, the thin film transistor 420 or 410 shown in any one of the first to seventh embodiments. 51, 470, or 493 can be used. The transistors 4010 and 4011 are n-channel thin film transistors.

[0423] The oxide semiconductor layer of the thin film transistor 4011 for the driver circuit is A conductive layer 4040 is provided in a position overlapping with the channel formation region. By providing the gate insulating film at a position overlapping the channel formation region of the nitride semiconductor layer, In addition, the amount of change in the threshold voltage of the thin film transistor 4011 can be reduced. The conductive layer 4040 may have the same potential as the gate electrode layer of the thin film transistor 4011. The conductive layer may be different from the first gate electrode layer and may function as the second gate electrode layer. The 4040 is in the GND state, 0V potential is applied, or it is in the floating state. This is also fine.

[0424] In addition, a pixel electrode layer 4030 of the liquid crystal element 4013 is connected to the thin film transistor 4010. The counter electrode layer 4031 of the liquid crystal element 4013 is electrically connected to the second substrate 4 006. A pixel electrode layer 4030, a counter electrode layer 4031, and a liquid crystal layer 4008 The overlapping portion corresponds to a liquid crystal element 4013. The counter electrode layer 4031 is provided with oxide insulating layers 4032 and 4033 which function as alignment films. A liquid crystal layer 4008 is sandwiched between the oxide insulating layers 4032 and 4033.

[0425] The first substrate 4001 and the second substrate 4006 may be light-transmitting substrates. Glass, ceramics, and plastics can be used. , FRP (Fiberglass-Reinforced Plastics) board, PV F (polyvinyl fluoride) film, polyester film, or acrylic resin film Room can be used.

[0426] The spacer 4035 is a columnar spacer obtained by selectively etching an insulating film. The distance (cell gap) between the pixel electrode layer 4030 and the counter electrode layer 4031 is controlled. The spacer 4035 is provided to control the amount of light emitted from the spacer 4035. A spherical spacer may be used as the spacer 4035. In addition, the counter electrode layer 4031 is provided over the same substrate as the thin film transistor 4010. The common connection portion is electrically connected to the common potential line. The counter electrode layer 4031 and the common potential line can be electrically connected via the conductive particles. The conductive particles are contained in the sealing material 4005 .

[0427] Alternatively, a liquid crystal that exhibits a blue phase without using an alignment film may be used. The blue phase is one of the liquid crystal phases. When the temperature of cholesteric liquid crystal is increased, the phase immediately transitions from the cholesteric phase to the isotropic phase. The blue phase appears only in a narrow temperature range, so it is necessary to improve the temperature range. In order to achieve this, a liquid crystal composition containing 5% by weight or more of a chiral agent is used for the liquid crystal layer 4008. A liquid crystal composition containing a liquid crystal exhibiting a blue phase and a chiral agent has a response speed of 1 msec. Since the liquid crystal display is optically isotropic, no alignment treatment is required, and the viewing angle dependency is small.

[0428] The liquid crystal display device of the present embodiment is a transmissive liquid crystal display device or a semi-transmissive liquid crystal display device. It can also be applied.

[0429] In the liquid crystal display device of the present embodiment, a polarizing plate is provided on the outer side (the viewing side) of the substrate, and In this example, a colored layer (also called a color filter) and an electrode layer used for a display element are provided in this order. However, the polarizing plate may be provided on the inner side of the substrate. Also, the laminated structure of the polarizing plate and the colored layer is not limited to this embodiment. The present invention is not limited to a specific form, and may be appropriately set depending on the materials of the polarizing plate and the colored layer and the manufacturing process conditions.

[0430] The thin film transistor 4011 has an oxide insulating layer 4 in contact with a semiconductor layer including a channel formation region. The oxide insulating layer 4041 is formed using the oxide insulating film described in Embodiment 1, for example. The oxide insulating layer 4041 may be formed using a material and a method similar to those of the insulating layer 416. As the first embodiment, a silicon oxide film is formed by sputtering.

[0431] In addition, a protective insulating layer 4020 is formed over the oxide insulating layer 4041. The protective insulating layer 20 can be formed using a material and a method similar to those of the protective insulating layer 403 described in Embodiment 1. Here, a silicon nitride film is formed as the protective insulating layer 4020 by the PCVD method. .

[0432] In order to reduce the surface unevenness of the thin film transistor, a planarizing insulating film is formed on the protective insulating layer 4020. The insulating layer 4021 that functions as a film is formed. The planarization insulating layer 404 may be formed of the same material and by the same method as that of the planarization insulating layer 404 shown in FIG. Heat-resistant organic resins such as benzocyclobutene resins, polyamides, and epoxy resins In addition to the above organic materials, low-k materials can be used. , siloxane resin, PSG (phosphorus glass), BPSG (borophosphorus glass), etc. are used. In addition, by stacking a plurality of insulating films made of these materials, an insulating layer can be formed. 4021 may be formed.

[0433] The method for forming the insulating layer 4021 is not particularly limited, and may be a sputtering method, a S OG method, spin coating, dip, spray coating, droplet ejection method (inkjet method, screen lean printing, offset printing, etc.), doctor knife, roll coater, curtain coater The insulating layer 4021 is baked and the semiconductor layer is baked. By combining this with annealing of the layer, it becomes possible to efficiently manufacture a semiconductor device.

[0434] The pixel electrode layer 4030 and the counter electrode layer 4031 are made of indium oxide containing tungsten oxide. , indium zinc oxide with tungsten oxide, indium oxide with titanium oxide, Indium tin oxide containing titanium oxide, indium tin oxide (hereinafter referred to as ITO), Translucent materials such as indium zinc oxide and indium tin oxide doped with silicon oxide A conductive material may be used.

[0435] The pixel electrode layer 4030 and the counter electrode layer 4031 are made of a conductive polymer. The conductive composition may be used to form the conductive film. The pixel electrode thus fabricated has a sheet resistance of 10,000 Ω / □ or less and a light transmittance of 550 nm. It is preferable that the resistance of the conductive polymer contained in the conductive composition is 70% or more. It is preferable that the electrical conductivity be 0.1 Ω·cm or less.

[0436] As the conductive polymer, a so-called π-electron conjugated conductive polymer can be used. For example, polyaniline or its derivatives, polypyrrole or its derivatives, polythiophene or its derivatives, or a copolymer of two or more of these.

[0437] A signal line driver circuit 4003 and a scanning line driver circuit 4004 or a pixel section 40 Various signals and potentials are applied to the input 02 via the FPC4018.

[0438] The connection terminal electrode 4015 is made of the same conductive film as the pixel electrode layer 4030 of the liquid crystal element 4013. The terminal electrode 4016 is formed from the source electrode layer and the drain electrode layer of the thin film transistor 4011. The gate electrode layer is formed of the same conductive film.

[0439] The connection terminal electrode 4015 is connected to a terminal of the FPC 4018 via an anisotropic conductive film 4019. The electrodes are electrically connected to each other.

[0440] In FIG. 10, a signal line driver circuit 4003 is formed separately and mounted on a first substrate 4001. The present invention is not limited to this configuration. Alternatively, only a part of the signal line driver circuit or a part of the scanning line driver circuit may be separately formed. It may be disguised as

[0441] FIG. 19 shows a semiconductor device using a TFT substrate 2600 produced by the production method disclosed in this specification. 1 shows an example in which a liquid crystal display module is configured as a semiconductor device.

[0442] FIG. 19 shows an example of a liquid crystal display module, in which a TFT substrate 2600 and an opposing substrate 2601 are connected. The substrate 2602 is fixed to the substrate 2601 by a bonding material 2602, and a pixel portion 2603 including a TFT and the like and a liquid crystal layer are disposed between the substrate 2601 and the substrate 2602. A display element 2604 and a colored layer 2605 are provided to form a display area. 5 is necessary for color display, and in the case of the RGB method, it corresponds to each color of red, green, and blue. A colored layer corresponding to each pixel is provided. A polarizing plate 2606, a polarizing plate 2607, and a diffusion plate 2613 are disposed on the outer side of the light source 1. The display is composed of a cold cathode fluorescent lamp 2610 and a reflector 2611, and the circuit board 2612 is a flexible A wiring board 2609 is connected to the wiring circuit section 2608 of the TFT substrate 2600, and the control External circuits such as roll circuits and power circuits are built in. Also, between the polarizer and the liquid crystal layer The layers may be laminated together with a retardation plate therebetween.

[0443] The LCD module is available in TN (Twisted Nematic) mode, IPS (In-plane Switching) mode, n-Plane-Switching mode, FFS (Fringe Field Switching) switching mode, MVA (Multi-domain Vertical A alignment) mode, PVA(Patterned Vertical Alignment) mode nment) mode, ASM(Axially Symmetric aligned Micro-cell mode, OCB (Optically Compensated Birefringence mode, FLC (Ferroelectric Liquid uid Crystal) mode, AFLC(AntiFerroelectric L iquid Crystal mode etc. can be used.

[0444] By the above steps, a highly reliable liquid crystal display panel can be manufactured as a semiconductor device. do.

[0445] This embodiment mode can be implemented in appropriate combination with the configurations described in other embodiments. It is.

[0446] (Embodiment 13) An example of electronic paper will be shown as one mode of a semiconductor device.

[0447] The thin film transistors of the first to seventh embodiments include an element electrically connected to a switching element. The present invention may be used for electronic paper that uses electrophoresis to drive electronic ink. Also called electrophoretic display, it has the same readability as paper and is different from other displays. It has the advantage of being able to consume less power and be made thinner and lighter than conventional devices.

[0448] Electrophoretic displays can take a variety of forms, but the first particle has a positive charge. A microcapsule containing a negatively charged second particle and a negatively charged second particle is mixed with a solvent or solute. By applying an electric field to the microcapsules, By moving the particles in a capsule in opposite directions, only the color of the particles that have gathered on one side is displayed. The first particles or the second particles contain a dye and are not mobile in the absence of an electric field. In addition, the first particles and the second particles have different colors (including colorless).

[0449] Thus, electrophoretic displays operate in such a way that materials with high dielectric constants migrate to areas of high electric field. This is a display that utilizes the so-called dielectrophoretic effect. The polarizing plate and counter substrate required for the display device are not necessary, and the thickness and weight are reduced.

[0450] The microcapsules dispersed in a solvent are called electronic ink. The electronic ink can be printed on surfaces such as glass, plastic, fabric, and paper. In addition, a color display is possible by using a color filter or particles having a pigment.

[0451] In addition, the above microphone is appropriately placed on the active matrix substrate so as to be sandwiched between two electrodes. By arranging multiple microcapsules, an active matrix display device is completed. Display can be achieved by applying an electric field to the cell. An active matrix substrate obtained by using transistors can be used.

[0452] The first particles and the second particles in the microcapsules may be made of a conductive material, an insulating material, a semiconductor material, or a combination of both. Conductive materials, magnetic materials, liquid crystal materials, ferroelectric materials, electroluminescent materials, electro A material selected from magnetochromic materials, magnetophoretic materials, or a composite material of these materials is used. That's good.

[0453] FIG. 18 shows an active matrix type electronic paper as an example of a semiconductor device. The transistor 581 can be manufactured in a manner similar to that of the thin film transistor described in the embodiment mode 1. The thin film transistor includes a conductor layer and is highly reliable. A film transistor can also be applied as the thin film transistor 581 .

[0454] The electronic paper in FIG. 18 is an example that uses the twisting ball display method. The display method is a method in which the first electrode layer, which is an electrode layer that uses spherical particles painted in black and white as a display element, is used. a potential difference is generated between the first electrode layer and the second electrode layer; This method displays images by controlling the orientation of all spherical particles.

[0455] The thin film transistor 581 formed on the substrate 580 is a thin film transistor having a bottom gate structure. The thin film transistor is covered with an insulating layer 583 in contact with the semiconductor layer and an insulating layer 584. The source electrode layer or drain electrode layer of the transistor 581 is a first electrode layer 587 and an insulating layer 5 83, insulating layer 584, and insulating layer 585 are in contact with each other through openings formed therein, and are electrically connected to each other. Between the first electrode layer 587 and the second electrode layer 588 formed on the substrate 596, a black region is formed. 590a and white area 590b, and a cavity 594 surrounded by a liquid. The spherical particles 589 are surrounded by a filler 59 such as a resin. The first electrode layer 587 corresponds to a pixel electrode, and the second electrode layer 588 corresponds to a common electrode. The second electrode layer 588 corresponds to a current-carrying electrode. The common connection portion is electrically connected to a common potential line disposed between the pair of substrates. The second electrode layer 588 and the common potential line can be electrically connected via the conductive particles. do.

[0456] Also, instead of the twist ball, an electrophoretic element can be used. and a 10μm to 20μm diameter nanoparticle that contains positively charged white nanoparticles and negatively charged black nanoparticles. Microcapsules with a diameter of about 0 μm are used. When an electric field is applied to the microcapsules by the first and second electrode layers, the microcapsules emit white light. White particles and black particles move in opposite directions, allowing the display to be white or black. A display element that applies this principle is an electrophoretic display element, commonly known as electronic paper. Electrophoretic display elements have a higher reflectivity than liquid crystal display elements, so auxiliary lights are not required. It also consumes little power and the display can be seen even in dimly lit places. Even if power is not supplied to the display, the image once displayed can be retained. In order to prevent this, a semiconductor device with a display function (simply a display device, or a device equipped with a display device) is required to be connected to the radio wave source. The displayed image can be preserved even if the device (also called a semiconductor device) is moved away. It becomes possible.

[0457] Through the above steps, electronic paper having high reliability as a semiconductor device can be manufactured. .

[0458] This embodiment mode can be implemented in appropriate combination with the configurations described in other embodiments. It is.

[0459] (Embodiment 14) An example of a light-emitting display device is shown as a semiconductor device. is shown using a light-emitting element that uses electroluminescence. The light-emitting element that uses the light-emitting material is classified into two types according to whether the light-emitting material is an organic compound or an inorganic compound. Generally, the former is called an organic EL element and the latter an inorganic EL element.

[0460] In an organic EL element, electrons and holes are released from a pair of electrodes by applying a voltage to the light-emitting element. These are then injected into a layer containing a light-emitting organic compound, causing a current to flow. When the electrons and holes recombine, the light-emitting organic compound forms an excited state, When the excited state returns to the ground state, light is emitted. The optical element is called a current-excited light-emitting element.

[0461] Inorganic EL elements are divided into dispersion-type inorganic EL elements and thin-film-type inorganic EL elements according to their element structure. Dispersion-type inorganic EL elements have a light-emitting layer in which particles of a light-emitting material are dispersed in a binder. The emission mechanism is a donor-acceptor reaction that utilizes the donor and acceptor levels. Inorganic EL elements are made by sandwiching a light-emitting layer between dielectric layers, and The structure is sandwiched between electrodes, and the light emission mechanism utilizes the inner-shell electron transition of metal ions. This is a localized light emission. Note that, in this embodiment, an organic EL element will be used as the light emitting element for explanation.

[0462] FIG. 12 shows an example of a pixel configuration to which digital time gray scale driving can be applied as an example of a semiconductor device. This is a diagram.

[0463] The configuration of a pixel to which digital time gray scale driving can be applied and the operation of the pixel will be described. The figure shows an n-channel transistor that uses an oxide semiconductor layer as a channel formation region in one pixel. Here is an example of using two of them.

[0464] The pixel 6400 includes a switching transistor 6401, a driving transistor 6402, The switching transistor 6 401 has a gate electrode connected to a scanning line 6406 and a first electrode (a source electrode and a drain electrode). One of the electrodes) is connected to a signal line 6405, and the second electrode (the source electrode and the drain electrode) is connected to a signal line 6405. The other end (side) is connected to the gate electrode of the driving transistor 6402. The gate electrode of the capacitor 6402 is connected to a power supply line 6407 via a capacitor element 6403. The first electrode is connected to a power line 6407, and the second electrode is connected to a first electrode (pixel electrode) of the light-emitting element 6404. The second electrode of the light emitting element 6404 corresponds to a common electrode 6408. The electrode 6408 is electrically connected to a common potential line formed on the same substrate.

[0465] A low power supply potential is set to the second electrode (common electrode 6408) of the light emitting element 6404. Note that the low power supply potential is a low power supply potential with respect to the high power supply potential set to the power supply line 6407. Potential < High potential is a potential that satisfies the power supply potential. Examples of low power supply potential include GND and 0V. The potential difference between the high power supply potential and the low power supply potential is applied to the light emitting element 6404 to emit light. In order to make the light emitting element 6404 emit light by passing a current through the element 6404, a high power supply potential and a low power supply potential are The potential difference between the potentials is equal to or greater than the forward threshold voltage of the light emitting element 6404. Set.

[0466] The capacitor 6403 is omitted by substituting the gate capacitance of the driving transistor 6402. It is also possible to use a gate capacitance of the driving transistor 6402 according to the channel type. A capacitance may be formed between the composition region and the gate electrode.

[0467] In the case of a voltage input voltage driving method, the gate electrode of the driving transistor 6402 is The driving transistor 6402 is fully turned on or off. In other words, the driving transistor 6402 is operated in a linear region. The driving transistor 6402 is operated in a linear region, so the voltage of the power supply line 6407 is A voltage higher than the voltage applied to the gate electrode of the driving transistor 6402 is applied to the gate electrode of the driving transistor 6402. A voltage equal to or higher than (power supply line voltage + Vth of driving transistor 6402) is applied to 6405. do.

[0468] In addition, when analog gray scale driving is performed instead of digital time gray scale driving, the input of the signal is different. By doing so, the same pixel configuration as in FIG. 12 can be used.

[0469] When analog gradation driving is performed, the gate electrode of the driving transistor 6402 is connected to the light emitting element 64 A voltage equal to or higher than the forward voltage of 04 plus the Vth of the driving transistor 6402 is applied. The forward voltage of 6404 refers to the voltage required to achieve the desired brightness. Incidentally, the driving transistor 6402 is designed to operate in the saturation region. By inputting a video signal, a current can be passed through the light emitting element 6404. In order to operate the transistor 6402 in the saturation region, the potential of the power supply line 6407 is set to The gate potential of the transistor 6402 is set higher than that of the transistor 6403. Analog gray scale driving can be performed by passing a current according to a video signal through the element 6404 .

[0470] Note that the pixel configuration shown in FIG. 12 is not limited to this. For example, A switch, a resistive element, a capacitive element, a transistor, a logic circuit, or the like may be added.

[0471] Next, the configuration of the light emitting element will be described with reference to FIG. 13. Here, the driving TFT is The cross-sectional structure of a pixel will be described using the example of the type shown in Figure 13(A), (B), and (C). The driving TFTs used in the semiconductor device, TFTs 7001, 7011, and 7021, are The thin film transistor can be manufactured in a manner similar to that of any of the first to seventh embodiments. The present invention relates to a highly reliable thin film transistor including a

[0472] The thin film transistor and the light emitting element are formed on a substrate. For this purpose, at least one of the anode and cathode must be transparent. The light emitting element has a top emission structure that emits light from the side of the substrate, and the light emitting element has a bottom emission structure that emits light from the side of the substrate. Light emitting elements with a surface emission structure and dual emission structures that emit light from both the substrate side and the side opposite the substrate The pixel configuration shown in FIG. 12 can be applied to any light-emitting element of the emission structure. can be done.

[0473] A light emitting element having a bottom emission structure will be described with reference to FIG.

[0474] The TFT 7011 is an n-type, and the light emitted from the light-emitting element 7012 is emitted toward the cathode 7013. FIG. 13A shows a cross-sectional view of a pixel when the TFT 7011 is electrically connected to the pixel. A cathode 7013 of a light-emitting element 7012 is formed on a light-transmitting conductive film 7017. A light-emitting layer 7014 and an anode 7015 are laminated in this order on the cathode 7013. The conductive film 7017 having the insulating property is formed by the oxide insulating layer 7031, the protective insulating layer 7035, and the insulating layer 7036. The drain electrode layer of the TFT7011 is electrically connected to the contact hole formed in 032. is connected to

[0475] The light-transmitting conductive film 7017 can be formed of indium oxide containing tungsten oxide, oxide Indium zinc oxide with tungsten oxide, indium oxide with titanium oxide, Indium tin oxide containing titanium, indium tin oxide (hereinafter referred to as ITO), Conductive materials with optical transparency such as indium zinc oxide and indium tin oxide doped with silicon oxide A membrane may be used.

[0476] In addition, the cathode 7013 can be made of various materials. However, it is preferable to use a material having a small work function, e.g. Specifically, alkali metals such as Li and Cs, and alkaline earth metals such as Mg, Ca, and Sr. Metals and alloys containing these (Mg:Ag, Al:Li, etc.), as well as rare earth elements such as Yb and Er. In FIG. 13(A), the thickness of the cathode 7013 is such that it transmits light (preferably Preferably, the thickness is about 5 nm to 30 nm. For example, an aluminum film having a thickness of 20 nm is used. The membrane is used as the cathode 7013 .

[0477] After a light-transmitting conductive film and an aluminum film are laminated, the film is selectively etched. In this case, the conductive film 7017 and the cathode 7013 may be formed on the same substrate. It is preferable to use a etchant.

[0478] The periphery of the cathode 7013 is covered with a partition wall 7019. The partition wall 7019 is made of polyimide, alumina, Organic resin films such as acrylic resin, polyamide, and epoxy resin, inorganic insulating films, and organic polysiloxanes The partition wall 7019 is formed by using a photosensitive resin material. An opening is formed in the opening, and the side wall of the opening is an inclined surface formed with a continuous curvature. In the case where a photosensitive resin material is used for the partition wall 7019, The step of forming a stop mask can be omitted.

[0479] The light-emitting layer 7014 formed on the cathode 7013 and the partition wall 7019 is composed of a single layer. The light-emitting layer 70 may be formed by laminating a plurality of layers. When the cathode 7013 is composed of a plurality of layers, an electron injection layer, an electron transport layer, a light emitting layer, and a The layer, the hole transport layer, and the hole injection layer are laminated in this order. Note that it is not necessary to provide all of these layers. stomach.

[0480] The stacking order is not limited to the above, and may be a hole injection layer, a hole transport layer, a light emitting layer, etc., on the cathode 7013. However, when comparing power consumption, the cathode may be used in the same manner as the cathode. An electron injection layer, an electron transport layer, a light-emitting layer, a hole transport layer, and a hole injection layer are stacked on the electrode 7013 in this order. Layering is preferred because it consumes less power.

[0481] In addition, various materials can be used for the anode 7015 formed on the light-emitting layer 7014. However, materials with large work functions, such as titanium nitride, ZrN, Ti, W, Ni, Pt, Cr, etc., and transparent conductive materials such as ITO, IZO (indium zinc oxide), and ZnO. It is also preferable to provide a shielding film 7016 on the anode 7015, for example, a metal that blocks light or a light that reflects light. In this embodiment, an ITO film is used as the anode 7015. A Ti film is used as the shielding film 7016 .

[0482] The region where the light-emitting layer 7014 is sandwiched between the cathode 7013 and the anode 7015 is the light-emitting element 7012. In the case of the element structure shown in FIG. 13A, the light emitted from the light emitting element 7012 is is emitted toward the cathode 7013 as indicated by the arrow.

[0483] Note that FIG. 13A shows an example in which a light-transmitting conductive film is used as a gate electrode layer. The light emitted from the light emitting element 7012 passes through the color filter layer 7033 and is reflected by the TFT The light is emitted through the gate electrode layer and source electrode layer of the TFT7011. A light-transmitting conductive film is used as the electrode layer or the source electrode layer, and the aperture ratio can be improved. do.

[0484] The color filter layer 7033 is formed by a droplet discharge method such as an inkjet method, a printing method, a photolithography method, or the like. Each is formed by an etching method using graphic technology.

[0485] The color filter layer 7033 is covered with an overcoat layer 7034, which is a protective insulating layer. In FIG. 13A, the overcoat layer 7034 is thin. As shown in FIG. 7, the overcoat layer 7034 has irregularities caused by the color filter layer 7033. It has the function of flattening the surface.

[0486] In addition, the oxide insulating layer 7031, the protective insulating layer 7035, and the insulating layer 7032 are formed, and A contact hole reaching the drain electrode layer is disposed at a position overlapping with a partition wall 7019 . In FIG. 13A, a contact hole reaching the drain electrode layer and a partition wall 7019 are overlapped. By adopting this layout, the aperture ratio can be improved.

[0487] Next, a light emitting element having a dual emission structure will be described with reference to FIG.

[0488] In FIG. 13B, a light-transmitting conductive film 7027 electrically connected to a TFT 7021 is A cathode 7023 of the light-emitting element 7022 is formed on the cathode 7023. 24 and an anode 7025 are laminated in this order. A contact hole formed in the solid insulating layer 7041, the protective insulating layer 7045, and the insulating layer 7042. It is electrically connected to the drain electrode layer of the TFT 7021 via a via.

[0489] The light-transmitting conductive film 7027 can be formed using indium oxide containing tungsten oxide, Indium zinc oxide with tungsten oxide, indium oxide with titanium oxide, Indium tin oxide containing titanium, indium tin oxide (hereinafter referred to as ITO), Conductive materials with optical transparency such as indium zinc oxide and indium tin oxide doped with silicon oxide A membrane may be used.

[0490] In addition, the cathode 7023 can be made of various materials. However, it is preferable to use a material with a small work function, e.g. Specifically, alkali metals such as Li and Cs, and alkaline earth metals such as Mg, Ca, and Sr. Metals and alloys containing these (Mg:Ag, Al:Li, etc.), as well as rare earth elements such as Yb and Er. In this embodiment, the thickness of the cathode 7023 is set to a thickness that allows light to pass through (preferably Preferably, the thickness is about 5 nm to 30 nm. For example, an aluminum film having a thickness of 20 nm is used. The membrane is used as the cathode 7023 .

[0491] After a light-transmitting conductive film and an aluminum film are laminated, the film is selectively etched. In this case, the conductive film 7027 and the cathode 7023 may be formed on the same substrate. It is preferable to use a etchant.

[0492] The periphery of the cathode 7023 is covered with a partition 7029. The partition 7029 is made of polyimide, alumina, Organic resin films such as acrylic resin, polyamide, and epoxy resin, inorganic insulating films, and organic polysiloxanes The partition wall 7029 is formed by using a photosensitive resin material. An opening is formed in the opening, and the side wall of the opening is an inclined surface formed with a continuous curvature. In the case where a photosensitive resin material is used for the partition wall 7029, The step of forming a stop mask can be omitted.

[0493] The light-emitting layer 7024 formed on the cathode 7023 and the partition wall 7029 is composed of a single layer. The light-emitting layer 70 may be formed by laminating a plurality of layers. When the cathode 7023 is composed of a plurality of layers, an electron injection layer, an electron transport layer, a light emitting layer, and a The layer, the hole transport layer, and the hole injection layer are laminated in this order. Note that it is not necessary to provide all of these layers. stomach.

[0494] The stacking order is not limited to the above, and may be a hole injection layer, a hole transport layer, a light emitting layer, etc., on the cathode 7023. However, when comparing power consumption, the cathode may be used in the same manner as the cathode. An electron injection layer, an electron transport layer, a light-emitting layer, a hole transport layer, and a hole injection layer are stacked on the electrode 7023 in this order. Layering is preferred because it consumes less power.

[0495] In addition, various materials can be used for the anode 7025 formed on the light-emitting layer 7024. However, materials with large work functions, such as transparent conductive materials such as ITO, IZO, and ZnO, are In this embodiment, an ITO film containing silicon oxide is used as the anode 7026.

[0496] The region where the light-emitting layer 7024 is sandwiched between the cathode 7023 and the anode 7025 is the light-emitting element 7022. In the case of the element structure shown in FIG. 13B, the light emitted from the light emitting element 7022 is is emitted toward both the anode 7025 side and the cathode 7023 side as indicated by the arrows.

[0497] Note that FIG. 13B shows an example in which a light-transmitting conductive film is used as a gate electrode layer. The light emitted from the light emitting element 7022 to the cathode 7023 side is reflected by the color filter layer 7043. The light passes through the gate electrode layer and source electrode layer of the TFT7021 and is emitted. By using a conductive film having light-transmitting properties as the gate electrode layer and the source electrode layer of 7021, The aperture ratio on the electrode 7025 side and the aperture ratio on the cathode 7023 side can be made substantially the same.

[0498] The color filter layer 7043 is formed by a droplet discharge method such as an inkjet method, a printing method, a photolithography method, or the like. Each is formed by an etching method using graphic technology.

[0499] The color filter layer 7043 is covered with an overcoat layer 7044, which is a protective insulating layer. Covered by layer 7045 .

[0500] In addition, the oxide insulating layer 7041, the protective insulating layer 7045, and the insulating layer 7042 are formed, and A contact hole reaching the drain electrode layer is disposed at a position overlapping with a partition wall 7029 . The layout is such that the contact hole reaching the drain electrode layer and the partition wall 7029 overlap each other. This makes it possible to make the aperture ratio on the anode 7025 side and the aperture ratio on the cathode 7023 side almost the same. .

[0501] In addition, a light-transmitting conductive film formed over the protective insulating layer 7045 and the insulating layer 7042 The contact hole reaching 7027 is disposed at a position overlapping with the partition wall 7029 .

[0502] However, when using a light-emitting element with a dual-side emission structure and making both display surfaces full color display, Since the light from the anode 7025 side does not pass through the color filter layer 7043, a separate color filter is required. It is preferable to provide a sealing substrate having a filter layer above the anode 7025.

[0503] Next, a light emitting element having a top emission structure will be described with reference to FIG.

[0504] In FIG. 13C, a TFT 7001 which is a driving TFT is an n-type TFT, and a light emitting element 7002 emits light. FIG. 13C shows a cross-sectional view of a pixel in the case where the light emitted from the pixel is emitted to the anode 7005 side. A cathode 7003 of a light emitting element 7002 electrically connected to a TFT 7001 is formed. On the cathode 7003, a light-emitting layer 7004 and an anode 7005 are laminated in this order.

[0505] In addition, various materials can be used for the cathode 7003. For example, Materials, specifically, alkali metals such as Li and Cs, and arsenic such as Mg, Ca, and Sr. In addition to alkaline earth metals and alloys containing them (Mg:Ag, Al:Li, etc.), Yb and E Rare earth metals such as r are preferred.

[0506] The periphery of the cathode 7003 is covered with a partition wall 7009. The partition wall 7009 is made of polyimide, alumina, Organic resin films such as acrylic resin, polyamide, and epoxy resin, inorganic insulating films, and organic polysiloxanes The partition wall 7009 is formed by using a photosensitive resin material. An opening is formed in the opening, and the side wall of the opening is an inclined surface formed with a continuous curvature. In the case where a photosensitive resin material is used for the partition wall 7009, The step of forming a stop mask can be omitted.

[0507] The light-emitting layer 7004 formed on the cathode 7003 and the partition wall 7009 is composed of a single layer. The light-emitting layer 70 may be formed by laminating a plurality of layers. When the cathode 7003 is composed of multiple layers, an electron injection layer, an electron transport layer, a light emitting layer, and a The layer, the hole transport layer, and the hole injection layer are laminated in this order. Note that it is not necessary to provide all of these layers. stomach.

[0508] The stacking order is not limited to the above, and a hole injection layer, a hole transport layer, and a light emitting layer may be stacked on the cathode 7003. The cathode 700 may be laminated in this order, the electron transport layer, and the electron injection layer. 3 will function as the anode.

[0509] In FIG. 13(C), a hole injection was performed on a laminated film in which a Ti film, an aluminum film, and a Ti film were laminated in this order. The dopant layer, hole transport layer, light emitting layer, electron transport layer, and electron injection layer are laminated in that order, and Mg:A A laminate of a g-alloy thin film and ITO is formed.

[0510] However, when comparing power consumption, the cathode 7003 is provided with an electron injection layer, an electron transport layer, a light emitting layer, It is preferable to laminate the hole transport layer and the hole injection layer in this order, since this reduces power consumption.

[0511] The anode 7005 is formed using a conductive material having light transmitting properties, for example, tungsten oxide. Indium oxide containing tungsten oxide, indium zinc oxide containing titanium oxide Indium oxide, Indium tin oxide with titanium oxide, Indium tin oxide, Indium A light-transmitting conductive film such as indium zinc oxide or indium tin oxide with silicon oxide added may also be used.

[0512] The region where the light-emitting layer 7004 is sandwiched between the cathode 7003 and the anode 7005 constitutes the light-emitting element 7002. In the case of the element structure shown in FIG. 13C, the light emitted from the light emitting element 7002 is , and is ejected toward the anode 7005 as indicated by the arrow.

[0513] In addition, in FIG. 13C, a TFT 7001 is shown as an example using a thin film transistor 460. However, there is no particular limitation, and other thin film transistors can be used. When another thin film transistor is used as the thin film transistor 01, the cathode 7003 and the drain electrode layer are in contact with each other. The electrical connection is made so that

[0514] In FIG. 13C, the drain electrode layer of the TFT 7001 is oxidized with the cathode 7003. The planarizing insulating layer 7053 is made of polyimide, acrylic, etc. Resin materials such as styrene resin, benzocyclobutene resin, polyamide, and epoxy resin are used. In addition to the above resin materials, low-k materials and siloxane-based materials are also available. Resin, PSG (phosphorus glass), BPSG (borophosphorus glass), etc. can be used. Note that a planarization insulating layer 7053 is formed by stacking a plurality of insulating films formed from these materials. The method for forming the planarization insulating layer 7053 is not particularly limited and may be determined depending on the material. Sputtering method, SOG method, spin coating, dip, spray coating, droplet ejection method (Inkjet method, screen printing, offset printing, etc.), doctor knife, roll Tools such as a coater, curtain coater, knife coater, etc. can be used.

[0515] In addition, a partition wall 7009 is provided to insulate the cathode 7003 from the cathode of an adjacent pixel. The partition wall 7009 is made of an organic resin film such as polyimide, acrylic resin, polyamide, or epoxy resin. The partition wall 7009 is formed using an inorganic insulating film or an organic polysiloxane. An opening is formed on the cathode 7003 using a resin material, and the sidewall of the opening has a continuous curvature. It is preferable to form the partition wall 7009 so that the partition wall 7009 has an inclined surface. When a conductive resin material is used, the step of forming a resist mask can be omitted.

[0516] In the structure of FIG. 13C, when a full-color display is performed, for example, the light-emitting element 70 02 is a green light emitting element, one adjacent light emitting element is a red light emitting element, and the other The light-emitting element is a blue light-emitting element. In addition to the three types of light-emitting elements, a white light-emitting element is also added. A light-emitting display device capable of full-color display using four types of light-emitting elements may be manufactured.

[0517] In the structure of FIG. 13C, all the light emitting elements are white light emitting elements. A sealing substrate having a color filter or the like is disposed above the light emitting element 7002. A light-emitting display device capable of full color display may be manufactured. By forming a material and combining it with a color filter and a color conversion layer, a full color display is achieved. It is possible.

[0518] Of course, a single-color display may be used. For example, a lighting device may be formed using white light. Alternatively, monochromatic light may be used to form an area color type light emitting device.

[0519] If necessary, an optical film such as a polarizing film, eg, a circular polarizing plate, may be provided.

[0520] Although the organic EL element has been described as the light-emitting element here, inorganic EL elements can also be used as the light-emitting element. It is also possible to provide an L element.

[0521] In addition, the thin film transistor (driving TFT) that controls the driving of the light-emitting element and the light-emitting element are electrically However, a current control TFT is connected between the driving TFT and the light emitting element. The configuration may be such that the input / output terminals are connected to each other.

[0522] In addition, one embodiment of the present invention is also applicable to a liquid crystal display device as long as the light-emitting element and the partition wall are not provided. The case of a liquid crystal display device is shown in FIG.

[0523] This shows the case where the TFT7071 is an n-type. In Figure 47, the TFT7071 is electrically connected The light-transmitting conductive film 7067 is made of an oxide The TFT 7 is connected to the insulating layer 7061 through a contact hole formed in the protective insulating layer 7062. It is electrically connected to the drain electrode layer 071.

[0524] The...

Claims

1. A semiconductor device having a transistor and an insulating layer located above the transistor, The transistor is a channel formation region having an oxide semiconductor; a first conductive layer having a region located below the channel formation region and functioning as a first gate electrode; a second conductive layer having a region located above the channel formation region and functioning as a second gate electrode; a third conductive layer electrically connected to the channel formation region and functioning as one of a source electrode and a drain electrode; a fourth conductive layer electrically connected to the channel formation region and functioning as the other of the source electrode and drain electrode; a first oxide region having a region in contact with a lower surface of the third conductive layer and having a lower resistance than the channel formation region; a second oxide region having a region in contact with a lower surface of the fourth conductive layer and having a lower resistance than the channel formation region; the third conductive layer is electrically connected to the channel formation region via the first oxide region; the fourth conductive layer is electrically connected to the channel formation region via the second oxide region; the insulating layer has a region in contact with an upper surface of the second conductive layer, a region in contact with an upper surface of the third conductive layer, a region in contact with an upper surface of the fourth conductive layer, a region in contact with an upper surface of the first oxide region, and a region in contact with an upper surface of the second oxide region; the second conductive layer has the same material as the third conductive layer; the second conductive layer has the same material as the fourth conductive layer; The channel formation region comprises indium oxide.

2. A semiconductor device having a transistor and an insulating layer located above the transistor, The transistor is a channel formation region having an oxide semiconductor; a first conductive layer having a region located below the channel formation region and functioning as a first gate electrode; a second conductive layer having a region located above the channel formation region and functioning as a second gate electrode; a third conductive layer electrically connected to the channel formation region and functioning as one of a source electrode and a drain electrode; a fourth conductive layer electrically connected to the channel formation region and functioning as the other of the source electrode and drain electrode; a first oxide region having a region in contact with a lower surface of the third conductive layer and having a lower resistance than the channel formation region; a second oxide region having a region in contact with a lower surface of the fourth conductive layer and having a lower resistance than the channel formation region; a side surface of the first oxide region has a region in contact with an oxide insulating layer; a side surface of the second oxide region has a region in contact with the oxide insulating layer; the third conductive layer is electrically connected to the channel formation region via the first oxide region; the fourth conductive layer is electrically connected to the channel formation region via the second oxide region; the insulating layer has a region in contact with an upper surface of the second conductive layer, a region in contact with an upper surface of the third conductive layer, a region in contact with an upper surface of the fourth conductive layer, a region in contact with an upper surface of the first oxide region, and a region in contact with an upper surface of the second oxide region; the second conductive layer has the same material as the third conductive layer; the second conductive layer has the same material as the fourth conductive layer; The channel formation region comprises indium oxide.

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