Power Modules, Converters, and Inverters

Abstract

Provided is a power conversion circuit in which a switching transistor and a synchronous rectification transistor are connected in series to each other and the inductance of a source of the switching transistor is smaller than the inductance of a source of the synchronous rectification transistor.

Description

[Technical field]

[0001] The present embodiment relates to a power conversion circuit, a power module, a converter, and an inverter. [Background technology]

[0002] In a half-bridge circuit or full-bridge circuit in which two elements (a switching element and a synchronous rectifier element) are connected in series, when the two elements are turned on at the same time, a short circuit occurs between the power supply and ground, causing a large through-current to flow. A large through-current can cause losses in the switching element or even destroy the switching element itself.

[0003] In order to suppress shoot-through current, a pause period (dead time) in which all elements are turned off is required during the transition period between the on / off states of elements. However, when one element is turned on from the dead time state in which all elements are turned off, a phenomenon may occur in which the gate of the other element is turned on due to a change in the drain voltage (false isolation or false on). This is a problem that can occur, for example, in three-phase inverters for motor drive and DC / DC converters with synchronous rectification.

[0004] In recent years, many research institutes have been conducting research and development of silicon carbide (SiC) devices. SiC power devices have the advantages of lower on-resistance, faster switching speeds, and higher temperature operation than conventional Si power devices. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Application Publication No. 5-226994 Summary of the Invention [Problem to be solved by the invention]

[0006] Generally, when using a switching element that operates at high speed, a source sense signal line is connected to the switching element. Since the electromotive force of the source inductance of the switching element does not affect the gate circuit and a sufficient potential difference can be secured for charging the gate oxide film of the switching element, the current change speed can be increased, and as a result, the loss (switching loss) that occurs when the switching element is turned on and off is reduced.

[0007] On the other hand, since only the charge / discharge current contributes to the current change in the voltage change region, this contribution is relatively small, and the difference in voltage change of the switching element depending on whether the source sense signal line is connected or not is small and approximately equal.

[0008] In addition, the switching characteristics of the synchronous rectifier element are determined by the operation of the switching element. In a half-bridge circuit, a short circuit of the switching element and the synchronous rectifier element connected in series due to an erroneous ON of the synchronous rectifier element is a problem.

[0009] A short circuit occurs in the voltage change region, but the source inductance on the return side in the current change region that occurs before the voltage change region has a large effect on the short circuit. The direction of the source inductance of the synchronous rectifier element in the current change region is the same as the direction of the source inductance of the switching element, and the voltage of the gate oxide film of each element in the voltage change region rises in the positive direction.

[0010] In a synchronous rectifier element that is not connected to the source sense signal wiring, the source inductance is shared with the gate circuit, so the electromotive force negatively charges the gate oxide film. This makes the starting point of the voltage rise in the voltage change region lower, making it less likely to cause a short circuit.

[0011] In the case of elements connected to the source sense signal line, the source signal line is separated, so the source inductance does not affect the voltage of the gate oxide film, which makes the element susceptible to the rise in voltage in the voltage change region and prone to short circuits.

[0012] Such a short circuit increases the power loss of the element, and in a half-bridge circuit formed of elements connected to the source sense signal wiring, the advantage of low power loss obtained by improving the switching characteristics of the elements connected to the source sense signal wiring may be lost due to the short circuit.

[0013] In order to prevent such a short circuit, it is necessary to prevent the synchronous rectifier element from being erroneously turned on. However, the switching characteristics including the synchronous rectifier element are determined by the switching element.

[0014] One aspect of the present embodiment provides a power conversion circuit that suppresses short circuits of switching elements and synchronous rectification elements while reducing power loss. Another aspect of the present embodiment provides a power module including the power conversion circuit. Another aspect of the present embodiment provides a converter and an inverter including the power module. [Means for solving the problem]

[0015] In this embodiment, in a power conversion circuit, a switching element connected to the source sense signal wiring and a synchronous rectification element not connected to the source sense signal wiring are used in combination, thereby making use of the switching characteristics of the switching element connected to the source sense signal wiring while suppressing short circuits of the synchronous rectification element.

[0017] Another aspect of the present embodiment is a power module including the power conversion circuit.

[0018] Another aspect of this embodiment is 1. A power module comprising: a first transistor having a first source, a first gate, and a first drain; a second transistor having a second source, a second gate, and a second drain; a first source wiring connected to the first source via a first source pad; a first gate signal wiring connected to the first gate via a first gate pad; a first drain wiring connected to the first drain; a second gate signal wiring connected to the second gate via a second gate pad; a second drain wiring connected to the second drain; and a first source sense signal wiring electrically connected to the first source pad, wherein the second source is connected to the first drain wiring via a second source pad, the first transistor has a function of exciting a first inductor of a wiring connecting the first source pad and the first source wiring, the second transistor has a function of releasing power stored in the first inductor, and the second source pad outputs a signal to the second source signal wiring via the first drain wiring. It is. Another aspect of this embodiment is 1. A power module comprising: a first transistor having a first source, a first gate, and a first drain; a second transistor having a second source, a second gate, and a second drain; a first source sense signal wiring connected to the first source via a first source pad; a first gate signal wiring connected to the first gate via a first gate pad; a first drain wiring connected to the first drain; a second source wiring connected to the second source via a second source pad; a second source signal wiring connected to the second source pad via the second source wiring; a second gate signal wiring connected to the second gate via a second gate pad; a second drain wiring connected to the second drain; and a first source signal wiring connected to the first source pad via the second drain wiring, wherein the first transistor has a function of exciting a first inductor of a wiring connecting between the first source pad and the second drain wiring, and the second transistor has a function of releasing power stored in the first inductor. It is.

[0019] Another aspect of the present embodiment is a converter or inverter including the power module. Effect of the Invention

[0020] According to the present embodiment, it is possible to provide a power conversion circuit that suppresses short circuits of switching elements and synchronous rectification elements and reduces power loss. Another embodiment can provide a power module including the power conversion circuit. Another embodiment can provide a converter and an inverter including the power module. [Brief description of the drawings]

[0021] [Figure 1] FIG. 1 shows a power conversion circuit according to an embodiment of the present invention. [Diagram 2] FIG. 2 is a schematic circuit diagram of a half-bridge circuit, which is a power conversion circuit according to one aspect of the present embodiment. [Diagram 3] FIG. 3 is a schematic circuit configuration diagram of a half-bridge circuit, which is a power conversion circuit according to one aspect of the present embodiment. [Figure 4] FIG. 4 is a schematic cross-sectional structural diagram of a SiC DIMISFET, which is an example of a semiconductor device applicable to the power conversion circuit of one aspect of this embodiment. [Diagram 5] FIG. 5 is a schematic cross-sectional view of a SiC TMISFET, which is an example of a semiconductor device that can be applied to the power conversion circuit of one aspect of this embodiment. [Figure 6] FIG. 6 shows a power conversion circuit according to another aspect of the present embodiment. [Figure 7] FIG. 7 shows a power conversion circuit according to another aspect of the present embodiment. [Figure 8] FIG. 8 shows a power conversion circuit according to another aspect of the present embodiment. [Figure 9] FIG. 9 is a simplified schematic planar pattern configuration diagram of a power module according to this embodiment, that is, a half-bridge built-in module, before a resin layer is formed. [Figure 10] FIG. 10 is a simplified schematic planar pattern configuration diagram of a power module according to this embodiment, that is, a half-bridge built-in module, before a resin layer is formed. [Figure 11] FIG. 11 is a simplified schematic planar pattern configuration diagram of the power module according to this embodiment, that is, a half-bridge built-in module, before a resin layer is formed. [Figure 12] FIG. 12 is a circuit diagram including transistors: (a) circuit A including a transistor that is not connected to a signal wiring for source sensing, and (b) circuit B including a transistor that is connected to a signal wiring for source sensing. [Figure 13] FIG. 13 is a diagram showing the change in voltage of the gate oxide film in the non-driven element. [Figure 14] FIG. 14 is a circuit diagram of a current-mode synchronous rectification step-down DC / DC converter according to this embodiment. [Figure 15] FIG. 15 is a circuit diagram of a current-mode synchronous rectification step-up DC / DC converter according to this embodiment. [Figure 16] FIG. 16 is a circuit diagram of a circuit used in a double pulse test. [Figure 17] FIG. 17 is a circuit diagram showing combinations of circuits A′ and B′ shown in FIG. 16, including (a) a combination of a circuit A′ having a transistor that is not connected to the source sensing signal wiring, and a circuit B′ having a transistor that is connected to the source sensing signal wiring, (b) a combination of circuits A′ and B′ both having transistors that are not connected to the source sensing signal wiring, and (c) a combination of circuits A′ and B′ both having transistors that are connected to the source sensing signal wiring. [Figure 18] FIG. 18 is a diagram showing operational waveforms of a transistor included in circuit B', in which (a) gate voltage, (b) drain current, and (c) drain voltage are operational waveforms. [Figure 19] FIG. 19 is a diagram showing losses in the transistors included in circuit A' and circuit B', (a) synchronous rectification element losses in the transistors included in circuit A', and (b) switching element losses in the transistors included in circuit B'. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0022] Next, the present embodiment will be described with reference to the drawings. In the following description of the drawings, the same or similar parts are given the same or similar reference numerals. However, it should be noted that the drawings are schematic, and the relationship between the thickness and planar dimensions of each component is different from the actual relationship. Therefore, the specific thickness and dimensions should be determined with reference to the following description. In addition, it goes without saying that the drawings include parts with different dimensional relationships and ratios.

[0023] The following embodiments are merely examples of devices and methods for embodying the technical ideas, and do not specify the materials, shapes, structures, arrangements, etc. of the components. Various modifications can be made to the embodiments within the scope of the claims.

[0024] One aspect of this embodiment is as follows.

[0025] [1] A power conversion circuit in which a switching transistor and a synchronous rectification transistor are connected in series, and the source inductance of the switching transistor is smaller than the source inductance of the synchronous rectification transistor.

[0026] [2] The power conversion circuit according to [1], further comprising a capacitor electrically connected to the switching transistor and the synchronous rectification transistor.

[0027] [3] The power conversion circuit according to [2], further comprising an output terminal electrically connected to the capacitor.

[0028] [4] The power conversion circuit according to any one of [1] to [3], further comprising a power terminal electrically connected to the drain of the switching transistor.

[0029] [5] A power module comprising the power conversion circuit according to any one of [1] to [4].

[0030] [6] A power module comprising: a first transistor having a function of exciting a first inductor and connected to a first source sense signal wiring; a second transistor having a function of releasing power stored in the first inductor; a first gate signal wiring and the first source sense signal wiring electrically connected to a gate of the first transistor, and a second gate signal wiring and a first source signal wiring electrically connected to a gate of the second transistor, wherein the first transistor is connected in series with the second transistor, and the first inductor is connected to a connection point between the first transistor and the second transistor.

[0031] [7] The power module according to [6], wherein the source inductance of the first transistor is smaller than the source inductance of the second transistor.

[0032] [8] The power module according to [6] or [7], further comprising a capacitor electrically connected to the first transistor and the second transistor.

[0033] [9] The power module according to [8], further comprising an output terminal electrically connected to the capacitor.

[0034]

[10] The power module according to any one of [6] to [9], further comprising a power terminal electrically connected to the drain of the first transistor.

[0035]

[11] The power module according to any one of [6] to

[10] , wherein the first transistor functions as a switching element, and the second transistor functions as a synchronous rectifier element.

[0036]

[12] The power module according to any one of [6] to

[11] , wherein the second transistor outputs a signal to the first source signal wiring via a drain of the first transistor.

[0037]

[13] The power module according to any one of [6] to

[11] , wherein the second transistor outputs a signal to the first source signal wiring via a source of the second transistor.

[0038]

[14] The power module according to

[13] , further comprising a second source signal wiring electrically connected to the first transistor, and a second source sense signal wiring electrically connected to the second transistor, wherein the first transistor outputs a signal to the second source signal wiring via the drain of the second transistor.

[0039]

[15] The power module described in

[12] , wherein the second transistor and the drain of the first transistor are connected by a first wiring, and when a signal is output from the gate of the second transistor to the first source signal wiring, the allowable current value of the first wiring is greater than the allowable current value of a wiring directly connected to the second gate signal wiring.

[0040]

[16] The power module according to

[13] , wherein when a signal is output from the gate of the second transistor to the first source signal wiring, a current allowable value of the second wiring via the source of the second transistor is larger than a current allowable value of a wiring directly connected to the second gate signal wiring.

[0041]

[17] A converter comprising the power module according to any one of [5] to

[16] .

[0042]

[18] An inverter comprising the power module according to any one of items [5] to

[16] .

[0043] (Power conversion circuit) The power conversion circuit according to this embodiment will be described.

[0044] FIG. 1 shows a power conversion circuit according to an embodiment of the present invention, which includes a transistor U1 as a synchronous rectifier element, a transistor U4 as a switching element, and a gate resistor R g1 , R g4 , and the gate drive circuit V G1 , V G4 The power conversion circuit has a plurality of insulated gate field effect transistors (MISFETs: Metal-Insulator-Semiconductor Field Effect Transistors), and the transistor U1 has a MISFET chip Q1 that functions as a synchronous rectifier element, and the wiring of the transistor U1 has an inductance L1. The transistor U4 has a MISFET chip Q4 that functions as a switching element and a source sense signal wiring SS4, and the wiring of the transistor U4 has an inductance L4.

[0045] A first inductor (not shown) can be connected to the connection point (indicated by a black circle in FIG. 1) between the transistors U1 and U4. G1 monitors the source of the MISFET chip Q1 through the wiring inductance L1, and controls the gate resistance R g1 A drive signal is applied to the gate of the MISFET chip Q1 via the inductance L1. The inductance L1 is a current path through which a current flows between the source and drain of the MISFET chip Q1. The gate drive circuit V G4 monitors the source of the MISFET chip Q4 via the source sense signal wiring SS4, and adjusts the gate resistance R g4 A drive signal is applied to the gate of the MISFET chip Q4 via the inductor L4. Note that the inductor L4 is a current path through which a current flows between the source and drain of the MISFET chip Q4, and the source sense signal wiring SS4 is a signal path provided separately from the current path.

[0046] The MISFET chip Q4 has a function of exciting a first inductor (not shown), and the MISFET chip Q1 has a function of releasing the power stored in the first inductor. A smaller source inductance enables a high-speed switching operation, and a larger source inductance makes it less likely that a short circuit will occur due to the high-speed switching operation. Therefore, a power conversion circuit that is high-speed, has low loss, and is less likely to short circuit can be configured by using a transistor with a source signal wiring and a small source inductance as a switching element that excites the first inductor and determines the switching characteristics, and using a transistor with a large source inductance and no source signal wiring as a switch (synchronous rectification element) that releases the power stored in the inductor and determines the degree of short circuit occurrence.

[0047] The power conversion circuit shown in Fig. 1 will be described in more detail with reference to Fig. 2 and Fig. 3. The circuit shown in Fig. 2 and Fig. 3 is a power conversion circuit 1, which is an example of a schematic circuit configuration of a half-bridge circuit. Note that the power conversion circuit 1 according to this embodiment is not limited to a half-bridge circuit, and can also be applied to a full-bridge circuit, a three-phase bridge circuit, or the like.

[0048] As described above, the power conversion circuit 1 includes the transistor U1, which is a synchronous rectifier element, and the transistor U4, which is a switching element including the source sense signal wiring SS4. Here, the characteristics of the element (transistor) depending on whether or not it is connected to the source sense signal wiring will be described.

[0049] FIG. 12(a) shows a circuit A including a MISFET chip Q that is not connected to a source sense signal wiring, and FIG. 12(b) shows a circuit B including a MISFET chip Q that is connected to a source sense signal wiring SS.

[0050] FIG. 13 shows the change in gate voltage of a non-driven element that is not performing a switching operation, which is either a switching element or a synchronous rectifier element.

[0051] In the current change region (current change period) in the figure, in circuit A, the source inductance is shared with the gate circuit, so the electromotive force negatively charges the gate oxide film, whereas in circuit B, the element is connected to the source sense signal wiring and the source signal wiring is separated, so the electromotive force of the source inductance does not affect the voltage of the gate oxide film.

[0052] In the voltage change region (voltage change period) in the diagram, the starting point of the voltage rise is low in Circuit A, while the starting point of the voltage rise is high in Circuit B. Circuit B is prone to exceeding the threshold voltage of the element and prone to false turn-on, but since the starting point of the voltage rise in Circuit A is low, it is less likely to exceed the threshold voltage of the element and is more likely to operate normally.

[0053] Therefore, in order to operate the power conversion circuit at high speed and normally, it is effective to use both a switching element connected to the source sense signal wiring and a synchronous rectifier element not connected to the source sense signal wiring. With this configuration, it is possible to take advantage of the switching characteristics of the switching element connected to the source sense signal wiring, and also to suppress false turn-on by utilizing the fact that the voltage rise of the synchronous rectifier element not connected to the source sense signal wiring starts at a low point, thereby ensuring operational stability.

[0054] Furthermore, the transistor operating waveforms and losses in a double pulse test are compared between the power conversion circuit of this embodiment and the conventional power conversion circuit. Fig. 16 shows a circuit (DPT (Double Pulse Test) circuit) used in the double pulse test. Note that although the configurations of the circuit A' and the circuit B' are exemplified as the power conversion circuit of this embodiment, the transistor operating waveforms and losses due to the difference in the configuration of the circuit A' and the circuit B' are compared.

[0055] 16, in the configuration of the transistors included in the circuit A' and the transistors included in the circuit B', a power source E, a capacitor C, an inductor L, and a constant current source I are connected to the circuit A' and the circuit B'. The transistor included in the circuit A' functions as a synchronous rectifier element, and the transistor included in the circuit B' functions as a switching element.

[0056] Here, the power supply E of the DPT circuit is 800V, and the constant current source I is 16A. Also, a circuit diagram showing a combination of circuit A' and circuit B' of the DPT circuit is shown in Fig. 17. Fig. 17(a) shows a combination of a circuit A' including a transistor (SiC MOSFET S4108 manufactured by ROHM Co., Ltd.) that is not connected to the signal wiring for source sense, and a circuit B' including a transistor (SiC MOSFET S4108 manufactured by ROHM Co., Ltd.) that is connected to the signal wiring for source sense, Fig. 17(b) shows a combination of circuits A' and B' including transistors (SCT3080KL manufactured by ROHM Co., Ltd.) that are not connected to the signal wiring for source sense, and Fig. 17(c) shows a combination of circuits A' and B' including transistors (SiC MOSFET S4108 manufactured by ROHM Co., Ltd.) that are connected to the signal wiring for source sense.

[0057] In the above DPT circuit, the circuit shown in Fig. 17(a) is the configuration of Example 1 equipped with the power conversion circuit of this embodiment, the circuit shown in Fig. 17(b) is the configuration of Comparative Example 1 equipped with a conventional power conversion circuit, and the circuit shown in Fig. 17(c) is the configuration of Comparative Example 2 equipped with a conventional power conversion circuit. Note that the circuit symbols and the like shown in Figs. 17(a) to (c) are omitted because the circuit symbols and the like shown in Figs. 12(a) and 12(b) can be used.

[0058] In the above power conversion circuit, the operation waveforms and losses of the transistors in the double pulse test are shown in Figs. 18 and 19. Fig. 18(a) shows the gate voltage (V ox,L ) is a diagram showing the operation waveform of the transistor included in the circuit B′, and FIG. 18(b) shows the drain current (I d,L) is a diagram showing the operation waveform of the drain voltage (V ds,L ) are the operating waveforms. Figure 19(a) shows the synchronous rectification element loss (P H FIG. 19(b) shows the switching element loss (P L FIG. 13 is a diagram showing (W) of the configuration of the casing.

[0059] As shown in FIG. 18(a), there is little difference in the operational waveform of the gate voltage between Example 1 and Comparative Example 1 and Comparative Example 2. On the other hand, as shown in FIG. 18(b), the operational waveform of the drain current is changed significantly in Comparative Example 2, which is prone to erroneous turn-on, while the current in Example 1 changes gradually, similar to Comparative Example 1. Also, as shown in FIG. 18(c), the operational waveform of the drain voltage is changed later in Comparative Example 1 than in Comparative Example 2, but the starting point of the voltage change in Example 1 is faster than Comparative Example 1, similar to Comparative Example 2. Therefore, as shown in FIG. 19(a), Example 1 has smaller synchronous rectification element loss of the transistor than Comparative Example 1 and Comparative Example 2, and as shown in FIG. 19(b), Example 1 has smaller switching element loss of the transistor than Comparative Example 1 and Comparative Example 2.

[0060] As described above, by using in combination a transistor that functions as a switching element connected to the source sense signal wiring, and a transistor that functions as a synchronous rectifier element that is not connected to the source sense signal wiring, it is possible to reduce the synchronous rectifier element loss and the switching element loss compared to conventional power conversion circuits, and it is possible to obtain a power conversion circuit that operates at high speed and normally.

[0061] The power conversion circuit 1 may include a control circuit, which will be described later, and may include, for example, a gate diode as shown in FIG.

[0062] As shown in FIG. 3, between the external gate terminal GT1 and source terminal ST1 and the gate G1 and source S1 of the MISFET chip Q1, there is a parasitic inductance L GP1 and L SP1 Between the external gate terminal GT4 and source sense terminal SST4 and the gate G4 and source sense signal wiring SS4 of the MISFET chip Q4, there is a parasitic inductance L GP4 and L SP4 Such an inductance component exists in the gate closed circuit of the MISFET chip, and causes an operation delay in driving the gate of the MISFET chip and an increase in the voltage fluctuation between the gate and source sense when the voltage between the drain and source changes.

[0063] In order to suppress the parasitic effect due to such inductance components, the shorter the distance from the cathode and anode of the diode to the gate pad electrode and source pad electrode, the greater the effect. The gate pad electrode and source pad electrode of the MISFET are formed on the surface of the MISFET. Therefore, the gate diode may be fabricated in the same chip as the MISFET, or the anode of the gate diode chip may be directly soldered onto the source pad electrode of the MISFET.

[0064] Although the gate diodes may be arranged together for each MISFET arranged in parallel, it is more effective to connect the gate diodes individually to each of a plurality of MISFETs.

[0065] The MISFET may be a SiC MISFET. A schematic cross-sectional structure of a SiC DI (Double Implanted) MISFET, which is an example of a semiconductor device 100 applicable to the power conversion circuit 1, is shown in FIG.

[0066] As shown in Figure 4, the SiC DIMISFET has n- A semiconductor substrate 26 made of a high resistance layer, a p-body region 28 formed on the front side of the semiconductor substrate 26, and a n-type semiconductor layer 29 formed on the front side of the p-body region 28. + A source region 30, a gate insulating film 32 disposed on the surface of the semiconductor substrate 26 between the p-body regions 28, a gate electrode 38 disposed on the gate insulating film 32, a source electrode 34 connected to the source region 30 and the p-body regions 28, and a n-type gate insulating film 36 disposed on the back surface of the semiconductor substrate 26 opposite to the front surface. + A drain region 24 and a + and a drain electrode 36 connected to the drain region 24.

[0067] In FIG. 4, semiconductor device 100 includes p-body region 28 and n-type junctions formed on the surface of p-body region 28. + The source region 30 is formed by double ion implantation (DI), and the source pad electrode SP is connected to a source electrode 34 connected to the source region 30 and the p-body region 28. The gate pad electrode (not shown) is connected to a gate electrode 38 disposed on the gate insulating film 32. Moreover, the source pad electrode SP and the gate pad electrode (not shown) are disposed on an interlayer insulating film 44 for passivation that covers the surface of the semiconductor device 100, as shown in FIG.

[0068] As shown in FIG. 4, the SiC DIMISFET has an n-type semiconductor layer sandwiched between p-type body regions 28. - A depletion layer as shown by the dashed line is formed in the semiconductor substrate 26 made of a high resistance layer, so that the channel resistance R JFET In addition, a body diode BD is formed between the p-body region 28 and the semiconductor substrate 26.

[0069] Moreover, the MISFET can be configured by a SiC trench (T: Trench) MISFET. A schematic cross-sectional structure of a SiC TMISFET, which is an example of a semiconductor device 100 applicable to the power conversion circuit 1, is shown in FIG.

[0070] As shown in FIG. 5, the SiC TMISFET includes a semiconductor substrate 26N made of an n-layer, a p-body region 28 formed on the front surface side of the semiconductor substrate 26N, and an n-type semiconductor layer 29 formed on the front surface of the p-body region 28. + A source region 30, a trench gate electrode 38TG formed in a trench extending through the p-body region 28 to the semiconductor substrate 26N via a gate insulating film 32 and interlayer insulating films 44U and 44B, and an n + A source electrode 34 connected to the source region 30 and the p-body region 28 and a n-body region 36 disposed on the back surface of the semiconductor substrate 26N opposite to the front surface of the semiconductor substrate 26N + A drain region 24 and a + and a drain electrode 36 connected to the drain region 24.

[0071] 5, in the semiconductor device 100, a trench gate electrode 38TG is formed in a trench that penetrates the p body region 28 and reaches the semiconductor substrate 26N, via the gate insulating film 32 and the interlayer insulating films 44U and 44B, and a source pad electrode SP is connected to a source electrode 34 that is connected to the source region 30 and the p body region 28. A gate pad electrode (not shown) is connected to the gate electrode 38 that is arranged on the gate insulating film 32. Moreover, the source pad electrode SP and the gate pad electrode (not shown) are arranged on an interlayer insulating film 44U for passivation that covers the surface of the semiconductor device 100, as shown in FIG.

[0072] In the SiC TMISFET, the channel resistance R associated with the junction FET (JFET) effect like in the SiC DIMISFET JFET In addition, the p-body region 28, the semiconductor substrate 26, and the n + A body diode BD is formed between the drain regions 24 .

[0073] Moreover, for the semiconductor device 100 (MISFET chips Q1 and Q4) applicable to the power conversion circuit 1, a GaN-based FET or the like can be applied instead of a SiC-based MISFET.

[0074] Furthermore, for the semiconductor device 100 (MISFET chips Q1 and Q4) applicable to the power conversion circuit 1, a semiconductor having a band gap energy of, for example, 1.1 eV to 8 eV can be used.

[0075] (Modification) As shown in Fig. 6, the connection relationship between the switching element and the synchronous rectifier element of the power conversion circuit 1 may be such that the source S4 of the MISFET chip Q4 operating as the switching element is electrically connected to the drain D1 of the MISFET chip Q1 operating as the synchronous rectifier element via an inductance L4. Furthermore, as shown in Fig. 7 and Fig. 8, the power conversion circuit shown in Fig. 1 and Fig. 6 may further include a power source E, a capacitor C, and an inductor L.

[0076] (Power Module) As described above, the power module equipped with the power conversion circuit 1 can have a half-bridge built-in module configuration. In the power module, the MISFET chip Q1 and the MISFET chip Q4 are built into one module. In FIG. 3, an example is shown in which four MISFET chips Q1 and four MISFET chips Q4 are arranged in parallel.

[0077] An example of a simplified schematic planar pattern configuration of a power module is shown in FIGS.

[0078] As shown in FIG. 9, the transistor including the MISFET chip Q1 includes a source signal wiring pattern SL1 and a gate signal wiring pattern GL1, and the transistor including the MISFET chip Q4 includes a source sense signal wiring pattern SSL4 and a gate signal wiring pattern GL4. The gate of the MISFET chip Q1 is directly connected to the gate signal wiring pattern GL1 via the wiring W11. The gate of the MISFET chip Q1 is also electrically connected to the source signal wiring pattern SL1 via the wirings W1 and W2 and the transistor including the MISFET chip Q4 (specifically, the drain D4). The current path through the wirings W1 and W2 and the transistor including the MISFET chip Q4 has a larger current tolerance than the current path through the wiring W11, so a large current can flow. Furthermore, the gate of the MISFET chip Q4 is directly connected to the gate signal wiring pattern GL4 and the source sense signal wiring pattern SSL4 via wiring.

[0079] As shown in FIG. 10, the transistor including the MISFET chip Q1 includes a source signal wiring pattern SL1 and a gate signal wiring pattern GL1, and the transistor including the MISFET chip Q4 includes a source sense signal wiring pattern SSL4 and a gate signal wiring pattern GL4. The gate of the MISFET chip Q1 is directly connected to the gate signal wiring pattern GL1 via the wiring W12. The gate of the MISFET chip Q1 is also electrically connected to the source signal wiring pattern SL1 via the wirings W3 and W4 and the source S1 of the MISFET chip Q1. The current path via the wirings W3 and W4 and the source S1 of the MISFET chip Q1 has a larger current tolerance than the current path via the wiring W12, so a large current can flow. The gate of the MISFET chip Q4 is also directly connected to the gate signal wiring pattern GL4 and the source sense signal wiring pattern SSL4 via wiring.

[0080] As shown in FIG. 11, the transistor including the MISFET chip Q1 includes a source sense signal wiring pattern SSL1, a source signal wiring pattern SL1, and a gate signal wiring pattern GL1, and the transistor including the MISFET chip Q4 includes a source sense signal wiring pattern SSL4, a source signal wiring pattern SL4, and a gate signal wiring pattern GL4. The gate of the MISFET chip Q1 is directly connected to the gate signal wiring pattern GL1 via the wiring W12. The gate of the MISFET chip Q1 is also electrically connected to the source signal wiring pattern SL1 via the wirings W3 and W4 and the source S1 of the MISFET chip Q1. The current path via the wirings W3 and W4 and the source S1 of the MISFET chip Q1 has a larger current tolerance than the current path via the wiring W12, so a large current can flow. The gate of the MISFET chip Q4 is also directly connected to the gate signal wiring pattern GL4 and the source sense signal wiring pattern SSL4 via wiring. The gate of the MISFET chip Q4 is electrically connected to a source signal wiring pattern SL4 via the wirings W1 and W2 and a transistor including the MISFET chip Q1 (specifically, the drain D1). The current path via the wirings W1 and W2 and the transistor including the MISFET chip Q1 has a larger current tolerance than the current path via the wiring W11, and therefore can pass a large current.

[0081] 11, either the MISFET chip Q1 or the MISFET chip Q4 functions as a switching element. A source sense signal wiring of a transistor including the MISFET functioning as the switching element may be controlled to be connected to the MISFET.

[0082] Each signal wiring of the power module shown in FIGS. 9 to 11 is connected to an external output terminal (reference numbers omitted).

[0083] (converter) 14 is a circuit diagram showing a current-mode synchronous rectification step-down DC / DC converter including a power module according to this embodiment. The DC / DC converter 51 steps down an input voltage Vin supplied to an input terminal VIN to generate a desired output voltage Vout at an output terminal VOUT.

[0084] The DC / DC converter 51 includes a switching element T11, a rectifier element T12, a drive circuit 53, a feedback voltage generating circuit 56, an error amplifier 57, a phase compensation circuit 58, a PWM comparator 60, a slope voltage generating circuit 61, an inductor L11, and a smoothing capacitor C1.

[0085] The switching element T11 is an N-channel MOS (Metal Oxide Semiconductor) field effect transistor connected to the drive circuit 53, the output current detection unit 54, and the rectifier element T12, and functions as a switching transistor that repeatedly turns on and off to control the current flowing through the inductor L11. The drain D of the switching element T11 is connected to the input terminal VIN. The source S of the switching element T11 is connected to the drain D of the rectifier element T12. A gate signal GH is applied to the gate G of the switching element T11 from the drive circuit 53. In addition, the source voltage of the switching element T11 is fed back to the drive circuit 53 via a source sense signal wiring SS. The switching element T11 is turned off when the gate signal GH is at a low level, and turned on when the gate signal GH is at a high level. The rectifier element T12 supplies a current toward the inductor L11 when the switching element T11 is off.

[0086] The rectifier element T12 is an N-channel MOS field effect transistor connected to the switching element T11 and the drive circuit 53, and operates in synchronization with and complementarily to the switching element T11 as a synchronous rectifier transistor. The drain D of the rectifier element T12 is connected to the source S of the switching element T11. A common connection point between the rectifier element T12 and the switching element T11 is shown as a node N1. The rectifier element T12 is turned on when the switching element T11 is off, and is turned off when the switching element T11 is on. The source S of the rectifier element T12 is connected to the ground potential GND. A gate signal GL is applied to the gate G of the rectifier element T12 by the drive circuit 53. The rectifier element T12 is turned on when the gate signal GL is at a high level, and is turned off when the gate signal GL is at a low level.

[0087] By turning on / off the switching element T11 and the rectifier element T12 complementarily, a square-wave switching voltage Vsw appears at the node N1. This switching voltage Vsw is smoothed by the inductor L11 and the smoothing capacitor C1, and an output voltage Vout is taken out at the output terminal VOUT. The inductor L11 and the smoothing capacitor C1 are connected in series between the node N1 and the ground potential GND, and their common connection point is indicated by a node N2. The voltage generated in the smoothing capacitor C1, i.e., the output voltage Vout, appears at the node N2.

[0088] In the DC / DC converter 51, a step-down switch output stage is formed by using a switching element T11, a rectifying element T12, an inductor L11, and a smoothing capacitor C1, which steps down the input voltage Vin supplied to the input terminal VIN to generate a desired output voltage Vout at the output terminal VOUT.

[0089] When the components of the DC / DC converter 51 are integrated into an IC, the switching element T11 and the rectifying element T12 may be built into the IC or may be externally attached to the IC. When externally attached to the IC, external terminals are required for outputting the gate signal GH and the gate signal GL to the outside, respectively. An N-channel MOS field effect transistor may be used as the switching element T11. An IGBT or the like may be used as the switching element T11 and the rectifying element T12. The switching element T11 and the rectifying element T12 may be configured as bipolar transistors.

[0090] In order to prevent an excessively large through current from flowing from the switching element T11 to the rectifying element T12, the drive circuit 53 has a section (so-called dead time) during which the gate signal GH is at a high level and the gate signal GL is at a low level so that the gate signal GH is not at a high level and the gate signal GL is not at a high level.

[0091] Furthermore, the drive circuit 53 also has a function of forcibly stopping the switching operation of the switch output stage in response to an abnormality protection signal not shown (a function of setting the gate signal GH output to the switching element T11 to a low level and the gate signal GL output to the rectifier element T12 to a low level).

[0092] The feedback voltage generating circuit 56 is composed of resistors R1 and R2 connected in series between the output terminal VOUT and the ground potential GND, and outputs a feedback voltage Vfb from a node N3 which is a common connection point between them. The feedback voltage Vfb is a voltage proportional to the voltage generated in the smoothing capacitor C1, and is also a DC voltage proportional to the output voltage Vout generated at the output terminal VOUT.

[0093] The error amplifier 57 generates an error voltage Verr according to the difference between a reference voltage Vref input to the non-inverting input terminal (+) and a feedback voltage Vfb input to the inverting input terminal (-). The error voltage Verr rises when the feedback voltage Vfb is lower than the reference voltage Vref, and falls when the feedback voltage Vfb is higher than the reference voltage Vref. The error voltage Verr is output from the output side of the error amplifier 57. Note that the error voltage Verr can also be converted to a current rather than a voltage and output from the output side of the error amplifier 57. An error amplifier configured in this way is known as a transconductance error amplifier.

[0094] The phase compensation circuit 58 is composed of a series circuit of a resistor R3 and a capacitor C3 connected in series between the output terminal of the error amplifier 57 and the ground potential GND. It is well known that such a phase compensation circuit is used in a DC / DC converter. The phase compensation circuit 58 is used to increase the difference with respect to the phase delay of 180 degrees in the DC / DC converter 51, that is, the phase margin. For example, if the phase is 120 degrees when the loop gain of the DC / DC converter 51 is 0db (gain x1), the phase margin is 180 degrees - 120 degrees = 60 degrees. It is said that this phase margin is sufficient if it is, for example, 45 degrees or more.

[0095] The PWM comparator 60 compares the error voltage Verr applied to the inverting input terminal (-) with the slope signal Vsl applied to the non-inverting input terminal (+) to generate a pulse width modulation signal pwm. Based on the pulse width modulation signal pwm, the DC / DC converter 51 performs PWM control.

[0096] The pulse width modulation signal pwm output from the PWM comparator 60 is applied to the drive circuit 53 in the subsequent stage, and turns on and off the switching element T11 and the rectifier element T12 in a complementary manner. A sequential circuit (e.g., an RS flip-flop) (not shown) is provided inside the drive circuit 53. A clock signal is applied to the set terminal of this RS flip-flop, and the pulse width modulation signal pwm is applied to the reset terminal. In this case, the clock signal corresponds to the set signal of the RS flip-flop, and the pulse width modulation signal pwm corresponds to the reset signal of the RS flip-flop.

[0097] The slope voltage generating circuit 61 generates a slope signal Vsl in order to operate the PWM comparator 60 by pulse width modulation. The slope signal Vsl is a triangular wave signal generated based on a clock signal.

[0098] A converter equipped with the power module of this embodiment applies a power conversion circuit including a switching element connected to the source sense signal wiring and a rectifier element not connected to the source sense signal wiring, thereby making use of the switching characteristics of the switching element connected to the source sense signal wiring, and also taking advantage of the low starting point of the voltage rise of the rectifier element not connected to the source sense signal wiring to suppress false turn-on and ensure operational stability.

[0099] 15 is a circuit diagram showing a current-mode synchronous rectification step-up DC / DC converter including a power module according to this embodiment. The DC / DC converter 72 steps up an input voltage Vin supplied to an input terminal VIN to generate a desired output voltage Vout at an output terminal VOUT.

[0100] The DC / DC converter 72 includes a switching element T21, a rectifier element T22, a drive circuit 53, a feedback voltage generating circuit 56, an error amplifier 57, a phase compensation circuit 58, a PWM comparator 60, a slope voltage generating circuit 61, an inductor L12, and a smoothing capacitor C2.

[0101] DC / DC converter 72 differs from the step-down type shown in Fig. 14 in the circuit portion subsequent to drive circuit 53. The other circuit portions are the same. Here, the circuit portions that differ between the two will be described.

[0102] The switching element T21 is an N-channel MOS field effect transistor connected to the rectifier element T22, the drive circuit 53, and the inductor L12, and functions as a switching transistor that repeatedly turns on and off to control the current flowing through the inductor L12. The switching element T21 operates in a complementary manner in synchronization with the rectifier element T22. The source S of the switching element T21 is connected to the ground potential GND. The drain D of the switching element T21 is commonly connected to the source S of the rectifier element T22 and one end of the inductor L12. This common connection point is indicated by a node N1. A gate signal GL is applied to the gate G of the switching element T21 by the drive circuit 53. In addition, the source voltage of the switching element T21 is fed back to the drive circuit 53 via a source sense signal wiring SS. The switching element T21 is turned on when the gate signal GL is at a high level, and turned off when the gate signal GL is at a low level.

[0103] The other end of the inductor L12 is connected to an input terminal VIN to which an input voltage Vin is supplied. That is, the switching element T21 is coupled to the input voltage Vin via the inductor L12. The current flowing through the inductor L12 is controlled by the switching element T21.

[0104] The source S of the rectifier element T22 is connected to the drain D of the switching element T21 and one end of the inductor L12. The drain D of the rectifier element T22 is connected to the node N2, i.e., the output terminal VOUT. A gate signal GH is applied to the gate G of the rectifier element T22 by the drive circuit 53. The rectifier element T22 is turned off when the gate signal GH is at a low level, and turned on when the gate signal GH is at a high level.

[0105] A smoothing capacitor C2 is connected between the node N2, that is, the output terminal VOUT, and the ground potential GND. The smoothing capacitor C2 performs rectification and smoothing operations together with the inductor L12 and the rectifying element T22.

[0106] The differences between the synchronous rectification step-up DC / DC converter 72 and the synchronous rectification step-down DC / DC converter 51 shown in Fig. 14 have been described. Other circuit parts are the same as those in Fig. 14, and therefore will not be described. The DC / DC converter 72 also uses a switching element connected to the source sense signal wiring and a rectifying element not connected to the source sense signal wiring. Note that the DC / DC converter shown in Fig. 14 is a step-down type, and the DC / DC converter shown in Fig. 15 is a step-up type, but it goes without saying that the converters can be applied to so-called step-up / step-down DC / DC converters that switch between step-down and step-up types.

[0107] Although not shown, it is also possible to configure an inverter including the power conversion circuit of this embodiment. In order to make the inverter function as an inverter, it is sufficient to control the elements in the inverter to use the elements connected to the source sense signal wiring when the elements function as switching elements.

[0108] [Other embodiments] As described above, although several embodiments have been described, the descriptions and drawings forming a part of the disclosure are illustrative and should not be understood as limiting. From this disclosure, various alternative embodiments, examples and operating techniques will become apparent to those skilled in the art. Thus, the present embodiment includes various embodiments not described herein. [Explanation of symbols]

[0109] 10...Substrate 24...n + Drain Region 26, 26N...Semiconductor substrate (drift layer) 28…p body region 30…Source region 32...Gate insulating film 34...Source electrode 36...Drain electrode 38…Gate electrode 38TG…Trench gate electrode 44, 44U, 44B...Interlayer insulating film 51, 72...DC / DC converter 53...Drive circuit 56...Feedback voltage generation circuit 57...Error amplifier 58...Phase compensation circuit 60…PWM comparator 61...Slope voltage generating circuit 100...Semiconductor devices BD: Body diode C, C3…Capacitor C1, C2: Smoothing capacitors D, D1, D4...Drain D G1 , D G4 …Gated diode E…Power supply G, G1, G4...Gate GH, GL...Gate signal GL1, GL4...Gate signal wiring pattern GND…Ground potential GT1, GT4...Gate terminals I…constant current source IL…Load current L, L11, L12...Inductors L1, L2, L4, L GP1 , L SP1 , L GP4 , L SP4 …Inductance N: Negative power terminal N1, N2, N3...nodes O, VOUT: Output terminal P: Positive power terminal pwm...Pulse width modulation signal Q, Q1, Q4…MISFET chip R1, R2, R3…Resistance R g1 , R g4 …Gate resistor RJFET …Channel resistance Ron: ON resistance S, S1, S4…Source SL1, SL4...Source signal wiring patterns ST1: Source terminal SP: Source pad electrode SS, SS1, SS4...Source sense signal wiring SSL1, SSL4...Source sense signal wiring pattern SST4: Source sense terminal SSW4…Source sense wire T11, T21...Switching elements T12, T22...Rectifying element U1, U4...Transistors Verr: Error voltage Vfb: Feedback voltage V G1 , V G4 …Gate drive circuit Vin: Input voltage VIN: Input terminal Vout: Output voltage Vref: Reference voltage Vsl: Slope signal W1, W2, W3, W4, W11, W12…Wiring

Claims

1. A first transistor having a first source, a first gate, and a first drain; a second transistor having a second source, a second gate, and a second drain; a first source wiring connected to the first source via a first source pad; a first gate signal line connected to the first gate via a first gate pad; a first drain wiring connected to the first drain; a second gate signal line connected to the second gate via a second gate pad; a second drain wiring connected to the second drain; a first source sense signal line electrically connected to the first source pad; Equipped with the second source is connected to the first drain wiring via a second source pad; the first transistor has a function of exciting a first inductor of a wiring that connects the first source pad and the first source wiring; the second transistor has a function of releasing the power stored in the first inductor; the second source pad outputs a signal to a second source signal line via the first drain line; Power module.

2. A first transistor having a first source, a first gate, and a first drain; a second transistor having a second source, a second gate, and a second drain; a first source sense signal line connected to the first source via a first source pad; a first gate signal line connected to the first gate via a first gate pad; a first drain wiring connected to the first drain; a second source wiring connected to the second source via a second source pad; a second source signal line connected to the second source pad via the second source line; a second gate signal line connected to the second gate via a second gate pad; a second drain wiring connected to the second drain; a first source signal wiring connected to the first source pad via the second drain wiring; Equipped with the first transistor has a function of exciting a first inductor of a wiring that connects between the first source pad and the second drain wiring, The second transistor has a function of releasing the power stored in the first inductor. Power module.

3. 2. The power module according to claim 1, wherein an inductance of a wiring connecting between the first source pad and the first source wiring is smaller than an inductance of a wiring connecting between the second source pad and the second source signal wiring.

4. 3. The power module according to claim 2, wherein an inductance of a wiring connecting between the first source pad and the first source signal wiring is smaller than an inductance of a wiring connecting between the second source pad and the second source signal wiring.

5. 4. The power module according to claim 1, further comprising a first capacitor connected between the first source wiring and the second drain wiring.

6. The power module according to claim 5 , further comprising a first terminal electrically connected to the second drain wiring.

7. The power module according to any one of claims 1 and 3 to 5, further comprising a second terminal electrically connected to the first drain wiring.

8. The first transistor functions as a switching element, The power module according to any one of claims 1 to 7, wherein the second transistor functions as a synchronous rectifier element.

9. 3. The power module according to claim 2, wherein the first transistor outputs a signal to the first source signal wiring via a second drain wiring of the second transistor.

10. the second source pad and the first drain wiring are connected by a first wiring; 2 . The power module according to claim 1 , wherein a current allowable value of the first wiring is greater than a current allowable value of a wiring that connects the second gate pad and the second gate signal wiring.

11. 3. The power module according to claim 2, wherein a current allowable value of a second wiring electrically connecting the second source pad and the second source signal wiring via the second source wiring is larger than a current allowable value of a wiring connecting the second gate pad and the second gate signal wiring.

12. A converter comprising a power module according to any one of claims 1 to 11, and which outputs a voltage obtained by stepping down or stepping up an input voltage supplied to a first or second terminal to a second or first terminal.

13. An inverter comprising a power module according to any one of claims 1 to 11.

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