SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

Abstract

To provide a semiconductor device which has in a lower portion a transistor employing a material other than an oxide semiconductor and has in an upper portion a transistor employing an oxide semiconductor.SOLUTION: A semiconductor device comprises: a first transistor 160 comprising first to fourth lines, a first gate electrode, a first source electrode and a first drain electrode; and a second transistor 162 having a second gate electrode, a second source electrode and a second drain electrode. The first transistor is provided on a substrate including a semiconductor material. The second transistor includes an oxide semiconductor layer. The first gate electrode and one of the second source electrode and the second drain electrode are electrically connected to each other. The first line and the first source electrode are electrically connected to each other. The second line and the first drain electrode are electrically connected to each other. The third line and the other of the second source electrode and the second drain electrode are electrically connected to each other. The fourth line and the second gate electrode are electrically connected to each other.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The disclosed invention relates to a semiconductor device using a semiconductor element and a manufacturing method thereof. do. [Background technology]

[0002] Memory devices that use semiconductor elements are volatile memory devices that lose their contents when the power supply is cut off. They are broadly divided into two types: volatile memory devices, which retain their contents even when the power supply is cut off, and non-volatile memory devices, which retain their contents even when the power supply is cut off. can be.

[0003] A typical example of a volatile memory device is a DRAM (Dynamic Random Access Memory). DRAM is a memory element that can be selected from the transistors. By storing charge in the capacitor, information is stored.

[0004] From the above principle, in DRAM, when information is read, the charge in the capacitor is lost. Therefore, every time data is read, a write operation is required again. The transistors that make up the transistors have leakage currents, and when the transistors are not selected, Because electric charges flow in and out at the same time, the data retention period is short. A re-write operation (refresh operation) is required, and power consumption must be sufficiently reduced. In addition, if the power supply is cut off, the memory contents are lost, so long-term memory To hold the information, a separate storage device using magnetic or optical materials is required.

[0005] Another example of a volatile memory device is SRAM (Static Random Access Memory). SRAM uses circuits such as flip-flops to store data. No refresh operation is required to retain data, which is an advantage over DRAM. However, because it uses circuits such as flip-flops, the cost per unit of memory capacity is high. In addition, if the power supply is cut off, the memory contents are lost. In this regard, there is no difference with DRAM.

[0006] A typical example of a non-volatile memory device is a flash memory. A floating gate is provided between the gate electrode of the transistor and the channel forming region, Since memory is stored by holding an electric charge in the floating gate, the data is retained for an extremely long period of time. The advantage is that it lasts a very long time (semi-permanent) and does not require the refresh operations required for volatile storage devices. For example, see Patent Document 1.

[0007] However, the gate insulating layer that constitutes the memory element is damaged by the tunnel current that occurs during writing. The memory element deteriorates, and if it is written to repeatedly, it will no longer function. In order to avoid this problem, for example, the number of write operations to each memory element may be uniform. However, to achieve this, complex peripheral circuits are required. However, even if such a method is adopted, the fundamental problem of life span is not solved. Therefore, flash memory is not suitable for applications where information needs to be rewritten frequently.

[0008] In addition, to inject or remove charge from the floating gate, high Moreover, it takes a relatively long time to inject or remove the charge. However, there is also a problem in that it is not easy to increase the speed of writing and erasing. [Prior art documents] [Patent documents]

[0009] [Patent Document 1] Japanese Patent Publication No. 57-105889 Summary of the Invention [Problem to be solved by the invention]

[0010] In view of the above problems, one embodiment of the disclosed invention provides a method for storing stored contents even when power is not supplied. To provide a semiconductor device having a new structure capable of retaining data and having no limit on the number of times it can be written. One of the objectives of the organization is to [Means for solving the problem]

[0011] One embodiment of the present invention is a transistor formed using an oxide semiconductor and a transistor formed using another material. The present invention relates to a semiconductor device having a stacked structure with a transistor formed using the above-mentioned method. For example, Such a configuration can be adopted.

[0012] One embodiment of the present invention is a semiconductor device including a first wiring (source line), a second wiring (bit line), and a third wiring. (first signal line), a fourth wiring (second signal line), a first gate electrode, and a first source electrode a first transistor having a first drain electrode, a second gate electrode, and a second a second transistor having a source electrode and a second drain electrode; The first transistor is provided over a substrate including a semiconductor material, and the second transistor is provided over an oxide semiconductor A first gate electrode and a second source electrode or a second drain electrode The first wiring (source line) and the first source electrode are electrically connected to each other. The second wiring (bit line) and the first drain electrode are electrically connected to each other. The third wiring (first signal line) and the other of the second source electrode or the second drain electrode are electrically connected, and the fourth wiring (second signal line) and the second gate electrode are electrically It is a semiconductor device connected.

[0013] In the above, the first transistor is a channel forming transistor provided in a substrate including a semiconductor material. a region, impurity regions provided so as to sandwich the channel forming region, and a region A first gate insulating layer, a first gate electrode on the first gate insulating layer, and an impurity region and an electric and a first source electrode and a first drain electrode electrically connected to the first source electrode.

[0014] In the above, the second transistor has a second gate electrode on a substrate including a semiconductor material. a second gate insulating layer on the second gate electrode; and an oxide semiconductor layer on the second gate insulating layer. a second source electrode and a second drain electrode electrically connected to the oxide semiconductor layer; And, it has.

[0015] In the above, the substrate containing a semiconductor material is a single crystal semiconductor substrate or an SOI substrate. It is preferable to use a plate, and it is particularly preferable that the semiconductor material is silicon.

[0016] In the above, the oxide semiconductor layer is made of an In-Ga-Zn-O-based oxide semiconductor material. In particular, the oxide semiconductor layer preferably contains In2Ga2ZnO7 crystals. In addition, the hydrogen concentration in the oxide semiconductor layer is preferably 5×10 19 atoms / cm 3 In addition, the off-state current of the second transistor is preferably 1×10 -13 A In addition, the off-state current of the second transistor is preferably 1×10 -20 A It is more preferable to set it as follows.

[0017] In the above, the second transistor is provided in a region overlapping with the first transistor. The configuration can be as follows.

[0018] In this specification, the terms "above" and "below" refer to the positional relationship of a component. For example, the term "gate electrode on a gate insulating layer" does not necessarily mean "directly under" the gate insulating layer. If the expression "gate electrode" is used, it excludes those that include other components between the gate insulating layer and the gate electrode. In addition, the terms "upper" and "lower" are merely used for the convenience of explanation, and Unless otherwise stated, this also includes reversed versions.

[0019] In addition, the terms "electrode" and "wiring" used in this specification refer to these components functionally. This is not intended to be limiting. For example, an "electrode" may be used as a part of a "wire." , and vice versa. Furthermore, the terms "electrode" and "wiring" are used interchangeably to refer to the plural "electrodes". This also includes cases where the "wiring" is formed integrally.

[0020] In addition, the functions of the "source" and "drain" may differ depending on whether transistors of different polarities are used or not. However, they may be swapped when the direction of the current changes during circuit operation. In this specification, the terms "source" and "drain" are used interchangeably. It is assumed that this is possible.

[0021] In this specification, "electrically connected" means "something that has some electrical effect." This includes cases where the device is connected via a wire. is not subject to any particular restriction as long as it enables transmission and reception of electrical signals between connected objects.

[0022] For example, "something that has some kind of electrical effect" includes not only electrodes and wiring, but also transistors. Switching elements such as transistors, resistors, inductors, capacitors, and other various devices This includes elements having functions such as:

[0023] In general, an "SOI substrate" is a substrate that has a silicon semiconductor layer on an insulating surface. However, in this specification, a semiconductor layer made of a material other than silicon is provided on an insulating surface. In other words, the semiconductor layer of an "SOI substrate" is The substrate is not limited to a silicon semiconductor layer. Not only semiconductor substrates such as wafers, but also glass substrates, quartz substrates, sapphire substrates, metal substrates, etc. This includes any non-semiconductor substrate, i.e., a conductive substrate with an insulating surface or a semiconductor on an insulating substrate. The term "SOI substrate" broadly includes those having a layer of material. In this context, the term "semiconductor substrate" does not only refer to a substrate made of semiconductor material, but also to a substrate made of semiconductor material. In other words, in this specification, "SOI substrate" is also broadly defined as "semiconductor substrate". This is included in the "conductor substrate." Effect of the Invention

[0024] In one embodiment of the present invention, a transistor using a material other than an oxide semiconductor is provided in a lower portion, A semiconductor device including a transistor including an oxide semiconductor is provided.

[0025] Since a transistor using an oxide semiconductor has an extremely low off-state current, It is possible to retain the memory contents for a much longer period of time. This eliminates the need for refresh operations or makes it possible to reduce the frequency of refresh operations to an extremely low level. Therefore, power consumption can be sufficiently reduced. It is possible to retain the stored contents for a long period of time.

[0026] In addition, high voltage is not required to write information, and there is no problem of element deterioration. Information is written by switching the transistor between on and off, so Also, by controlling the potential input to the transistor, Since it is rewritable, there is also the advantage that there is no need to erase the information. do.

[0027] In addition, a transistor using a material other than an oxide semiconductor is Compared to the conventional EEPROM, it can operate at higher speeds, so by using this, the contents of the memory can be It is possible to perform reading at high speed.

[0028] In this way, transistors using materials other than oxide semiconductors and transistors using oxide semiconductors By integrating a transistor, a semiconductor device with unprecedented features can be realized. It is possible. [Brief description of the drawings]

[0029] [Figure 1] A circuit diagram for explaining a semiconductor device. [Diagram 2] 1A and 1B are cross-sectional and plan views for explaining a semiconductor device; [Diagram 3]1 is a cross-sectional view illustrating a manufacturing process of a semiconductor device; [Figure 4] 1 is a cross-sectional view illustrating a manufacturing process of a semiconductor device; [Diagram 5] 1 is a cross-sectional view illustrating a manufacturing process of a semiconductor device; [Figure 6] FIG. 1 is a cross-sectional view illustrating a semiconductor device. [Figure 7] FIG. 1 is a cross-sectional view illustrating a semiconductor device. [Figure 8] FIG. 1 is a cross-sectional view illustrating a semiconductor device. [Figure 9] FIG. 1 is a cross-sectional view illustrating a semiconductor device. [Figure 10] FIG. 1 is a diagram illustrating an electronic device using a semiconductor device. [Figure 11] Vertical cross-sectional view of an inverted staggered transistor using an oxide semiconductor [Figure 12] Energy band diagram (schematic diagram) at the A-A' cross section of Figure 11 [Figure 13] (A) A diagram showing the state when a positive potential (+VG) is applied to the gate (GE1), and (B) a diagram showing the state when a negative potential (-VG) is applied to the gate (GE1). [Figure 14] A diagram showing the relationship between the vacuum level, the work function of a metal (φM), and the electron affinity of an oxide semiconductor (χ) [Figure 15] A circuit diagram for explaining a semiconductor device. [Figure 16] A circuit diagram for explaining a semiconductor device. [Figure 17] A circuit diagram for explaining a semiconductor device. [Figure 18] A circuit diagram for explaining a semiconductor device. [Figure 19] A circuit diagram for explaining a semiconductor device. [Figure 20] Timing chart showing the relationship between potentials [Figure 21] A circuit diagram for explaining a semiconductor device. [Figure 22] 1A and 1B are cross-sectional and plan views for explaining a semiconductor device; [Figure 23] FIG. 1 is a cross-sectional view illustrating a semiconductor device. [Figure 24] FIG. 1 is a cross-sectional view illustrating a semiconductor device. [Diagram 25] FIG. 1 shows characteristics of a transistor including an oxide semiconductor. [Figure 26] Circuit diagram for evaluating the characteristics of a transistor using an oxide semiconductor [Figure 27] Timing chart for evaluating characteristics of a transistor using an oxide semiconductor [Figure 28] FIG. 1 shows characteristics of a transistor including an oxide semiconductor. [Figure 29] FIG. 1 shows characteristics of a transistor including an oxide semiconductor. [Diagram 30] FIG. 1 shows characteristics of a transistor including an oxide semiconductor. [Diagram 31] Figure showing the results of the memory window width survey DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0030] An embodiment of the present invention will be described below with reference to the drawings. The present invention is not limited to the above description, and may be modified in various forms and without departing from the spirit and scope of the present invention. It will be readily understood by those skilled in the art that various modifications may be made to the details. The present invention should not be construed as being limited to the description of the embodiment shown in the accompanying drawings.

[0031] In addition, the position, size, range, etc. of each component shown in the drawings are not necessarily shown in order to facilitate understanding. The actual position, size, range, etc. may not be shown. There is no limitation to the position, size, range, etc. shown.

[0032] In this specification, ordinal numbers such as "first," "second," and "third" are used to avoid confusion of components. It should be noted that the numbers are added to avoid any unnecessary errors and are not intended to limit the number of errors.

[0033] (Embodiment 1) In this embodiment, a structure and a manufacturing method of a semiconductor device according to one embodiment of the disclosed invention will be described. This will be described with reference to FIGS.

[0034] <Circuit configuration of semiconductor device> FIG. 1 shows an example of a circuit configuration of a semiconductor device. A transistor 160 using a material (e.g., silicon) and a transistor using an oxide semiconductor In the following description, the semiconductor device shown in FIG. It is sometimes called.

[0035] Here, the gate electrode of transistor 160 and the source electrode or drain of transistor 162 are The first line (1st Line) is electrically connected to one of the drain electrodes. The source line SL is electrically connected to the source electrode of the transistor 160. A second wiring (also called a bit line BL) and a drain of the transistor 160 The first signal electrode is electrically connected to the third wiring (3rd Line). The line S1 and the other of the source electrode or the drain electrode of the transistor 162 are connected to each other. A fourth line (also called a second signal line S2) and a transistor are electrically connected to each other. The gate electrode of the transistor 162 is electrically connected.

[0036] The transistor 160 using a material other than an oxide semiconductor is a transistor using an oxide semiconductor. Compared to the conventional EEPROM, it can operate at higher speeds, so by using this, the contents of the memory can be In addition, a transistor using an oxide semiconductor can be used. The off-state current of the transistor 162 is extremely small. By turning off the transistor 62, the potential of the gate electrode of the transistor 160 is maintained for a very long time. In addition, in the transistor 162 including an oxide semiconductor, Another advantage is that short channel effects are less likely to occur.

[0037] By taking advantage of the feature that the potential of the gate electrode can be maintained, It is possible to write, retain, and read.

[0038] First, the writing and holding of information will be explained. The transistor 162 is turned on by applying a potential that turns on the transistor 162 . As a result, the potential of the third wiring is applied to the gate electrode of the transistor 160 (write After that, the potential of the fourth wiring is set to a potential at which the transistor 162 is turned off. By turning off the transistor 162, the gate electrode of the transistor 160 The potential is maintained (retained).

[0039] Since the off-state current of the transistor 162 is extremely small, the gate electrode of the transistor 160 The potential is maintained for a long period of time. For example, if the potential of the gate electrode of transistor 160 is If the potential is such that the transistor 160 is turned on, the transistor 160 will remain on for a long time. The potential of the gate electrode of the transistor 160 is maintained for a certain period of time. If the potential is such that the transistor 160 is turned off, the transistor 160 will remain in the off state for a long time. is retained over time.

[0040] Next, the reading of information will be described. As described above, when the transistor 160 is in the on state, Alternatively, when the off state is maintained, a predetermined potential (low potential) is applied to the first wiring. When the transistor 160 is turned on, the potential of the second wiring changes depending on whether the transistor 160 is turned on or off. For example, when the transistor 160 is on, the potential of the first wiring As a result, the potential of the second wiring is lowered. In the off state, the potential of the second wiring does not change.

[0041] In this manner, while the information is being held, the potential of the second wiring is compared with a predetermined potential. This allows the information to be read out.

[0042] Next, the rewriting of information will be described. The rewriting of information includes the above-mentioned writing of information and That is, the potential of the fourth wiring is held in the same manner as when the transistor 162 is turned on. This causes the transistor 162 to be turned on. (a potential related to new information) is applied to the gate electrode of transistor 160. Then, The potential of the fourth wiring is set to a potential at which the transistor 162 is turned off. By turning off 62, the new information is held.

[0043] In this way, the semiconductor device according to the disclosed invention can directly read data by rewriting the data. It is possible to rewrite information. This is why it is necessary for flash memory etc. This eliminates the need for an erase operation, and makes it possible to suppress a decrease in operation speed caused by the erase operation. That is, high speed operation of the semiconductor device is achieved.

[0044] The off-state current of the writing transistor 162 using an oxide semiconductor is extremely small. The potential of the gate electrode of the transistor 160 is maintained for a long time. The refresh operation required for conventional DRAM is no longer necessary, or the refresh operation is It is possible to reduce the frequency of operations to an extremely low level (for example, once a month to once a year). As described above, the semiconductor device of the disclosed invention has a feature as a substantially non-volatile memory device. There are.

[0045] In addition, the semiconductor device of the disclosed invention differs from conventional DRAM in that information is read out. Since the information is not lost, there is no need to rewrite it every time it is read. Compared to DRAM, the frequency of writing information can be significantly reduced, resulting in lower power consumption. It is possible to sufficiently suppress the above.

[0046] In addition, the semiconductor device of the disclosed invention can directly write information to the semiconductor device again. This is necessary for flash memory and other devices. This eliminates the need for an erase operation, and thus makes it possible to suppress a decrease in operation speed caused by the erase operation. In other words, high speed operation of the semiconductor device is realized. Since it does not require the high voltages required for writing and erasing data using transistors, it is a semiconductor The power consumption of the device can be further reduced.

[0047] The semiconductor device according to the disclosed invention further includes a write transistor and a read transistor. Each memory cell needs to include at least six transistors. This makes it possible to reduce the area per memory cell significantly compared to SRAM, which requires a This allows semiconductor devices to be arranged at a high density.

[0048] In addition, in conventional floating gate transistors, the gate insulating film (TFT) The charge transfer in the gate insulating film (tunnel insulating film) causes deterioration of the gate insulating film (tunnel insulating film). However, in the memory cell according to one embodiment of the present invention, The information is written by the switching operation of the read transistor, which is a problem that has not been solved in the past. This can eliminate the degradation of the gate insulating film that was previously caused by the number of write operations. This means that there is no limit to the number of rewrites, and the rewrite resistance is extremely high. 10 9 No degradation of current-voltage characteristics observed even after more than 1 billion writes .

[0049] Note that the field-effect mobility of the writing transistor 162 using an oxide semiconductor is In this state, 3 cm 2 / Vs or more 250cm 2 / Vs or less, preferably 5cm 2 / Vs or later Upper 200cm 2 / Vs or less, preferably 10cm 2 / Vs or more 150cm 2 / Vs or later In addition, a transistor including an oxide semiconductor has a subthreshold swing value (S value) should be 0.1V / dec. or less. Use such a transistor. This makes it possible to sufficiently shorten the time required to write information.

[0050] The channel length L of the writing transistor 162 using an oxide semiconductor is 10 nm or more. It is preferable that the channel size is 400 nm or less. This provides various benefits, such as faster operation of the register, lower power consumption, and higher integration.

[0051] The read transistor 160 is a transistor using crystalline silicon. In particular, from the viewpoint of increasing the speed of the read operation, it is preferable to use single crystal silicon. It is preferable to use an n-channel transistor having such a single crystal silicon transistor. The capacitor can be formed, for example, using bulk silicon (so-called silicon wafer). do.

[0052] The above explanation applies to the case where an n-type transistor (n-channel transistor) is used. However, p-type transistors can be used instead of n-type transistors. It goes without saying.

[0053] <Plane and cross-sectional configurations of semiconductor device> FIG. 2 shows an example of the configuration of the semiconductor device. FIG. 2(A) shows a cross section of the semiconductor device. 2(B) shows a plan view of the semiconductor device. These correspond to the cross sections taken along lines A1-A2 and B1-B2 in FIG. 2(A) and FIG. 2(B). The semiconductor device shown in FIG. 1 has a transistor 160 using a material other than an oxide semiconductor in the lower portion. The transistor 162 includes an oxide semiconductor in the upper portion. Transistor 160 and transistor 162 are both described as n-type transistors. However, a p-type transistor may be used. In particular, the transistor 160 is preferably a p-type transistor. It is easy to do so.

[0054] The transistor 160 includes a channel forming region 11 provided in a substrate 100 including a semiconductor material. 6, and the impurity region 114 and the high concentration impurity region 115 are provided so as to sandwich the channel forming region 116. A pure region 120 (collectively referred to as an impurity region) and a channel forming region 11 6, and a gate electrode provided on the gate insulating layer 108. 110 and a source or drain electrode 130a electrically connected to the impurity region 114. , and a source or drain electrode 130b.

[0055] Here, a sidewall insulating layer 118 is provided on the side surface of the gate electrode 110. In addition, in the region of the substrate 100 that does not overlap with the sidewall insulating layer 118 as shown in the cross-sectional view, The semiconductor device has a high-concentration impurity region 120, and a metal compound region 1 24. Also, on the substrate 100, an element isolation insulating film is provided so as to surround the transistor 160. A layer 106 is provided, and an interlayer insulating layer 126 and a An interlayer insulating layer 128 is provided. A source or drain electrode 130b is formed on the interlayer insulating layer 126 and the interlayer insulating layer 128. Through the opening, the source electrode is electrically connected to the metal compound region 124. The drain electrode 130a and the source or drain electrode 130b are formed in a metal compound region. The high concentration impurity region 120 and the impurity region 114 are electrically connected through the region 124. The gate electrode 110 is provided with a source electrode or drain electrode 130a and a source electrode A similarly provided electrode 130c is electrically connected to the drain electrode 130b. do.

[0056] The transistor 162 includes a gate electrode 136d provided on the interlayer insulating layer 128 and a gate A gate insulating layer 138 is provided on the electrode 136d. An oxide semiconductor layer 140 and a second insulating film provided on the oxide semiconductor layer 140. A source electrode or drain electrode 142a, which is electrically connected to the source electrode or drain electrode 142b, and an in-electrode 142b.

[0057] Here, the gate electrode 136d is embedded in the insulating layer 132 formed on the interlayer insulating layer 128. Similarly to the gate electrode 136d, the source electrode An electrode 136a is in contact with the drain electrode 130a, and a source or drain electrode 130b is in contact with the drain electrode 130b. An electrode 136b is formed in contact with the electrode 130c, and an electrode 136c is formed in contact with the electrode 130c. do.

[0058] In addition, a protective layer is provided on the transistor 162 so as to be in contact with part of the oxide semiconductor layer 140. An insulating layer 144 is provided, and an interlayer insulating layer 146 is provided on the protective insulating layer 144. Here, the protective insulating layer 144 and the interlayer insulating layer 146 are provided with a source electrode or a drain electrode. The openings reach the source electrode 142a and the source or drain electrode 142b. Through the opening, the electrode 150d and the electrode 150e are connected to the source electrode or the drain electrode. The electrode 142a is formed in contact with the source electrode or the drain electrode 142b. As well as the electrode 150d and the electrode 150e, the gate insulating layer 138, the protective insulating layer 144, the interlayer insulating The layer 146 is provided with openings through which the electrodes 136a, 136b, and 136c are in contact. Electrodes 150a, 150b, and 150c are formed.

[0059] Here, impurities such as hydrogen are sufficiently removed from the oxide semiconductor layer 140, and the oxide semiconductor layer 140 is highly purified. Specifically, the hydrogen concentration in the oxide semiconductor layer 140 is preferably 5×10 19 atoms / cm 3 Less than 5×10 18 atoms / cm 3 More hopes below Preferably 5 x 10 17 atoms / cm 3 This is the same as the general silicon wafer. The carrier in the wafer (a silicon wafer with trace amounts of impurity elements such as phosphorus and boron added) Rear concentration (1×10 14 / cm 3 A sufficiently small value of carrier concentration (e.g. For example, 1×10 12 / cm 3 Less than or equal to 1.45×10 10 / cm 3 (less than) In this way, the hydrogen concentration is sufficiently reduced and the material is highly purified, becoming intrinsic (i-type) or essentially By using an oxide semiconductor that is essentially intrinsic (i-type), The transistor 162 can be obtained. For example, the transistor 162 at room temperature (25° C.) The off-state current (here, the value per unit channel width (1 μm)) at 1zA (zeptoampere) is 1 x 10 -21 A) or less, preferably 1zA / μm or less. At 85°C, the current is 100zA / μm (1×10 -19 A / μm or less, preferably is 10zA / μm (1×10 -20 In this way, the hydrogen concentration is sufficient. The oxide semiconductor layer 140 is reduced to an intrinsic state or substantially intrinsic state, and a transistor is formed. By reducing the off-current of the transistor 162, a semiconductor device with a new configuration can be realized. The hydrogen concentration in the oxide semiconductor layer 140 can be measured by secondary ion mass spectrometry ( Measured by SIMS (Secondary Ion Mass Spectroscopy) This is what was done.

[0060] An insulating layer 152 is provided on the interlayer insulating layer 146, and a buried insulating film is formed in the insulating layer 152. Electrodes 154a, 154b, 154c, and 154d are provided so that the electrodes 154a, 154b, 154c, and 154d are inserted into the Here, electrode 154a is in contact with electrode 150a, and electrode 154b is in contact with electrode 150. b, electrode 154c is in contact with electrode 150c and electrode 150d, and electrode 1 54d is in contact with electrode 150e.

[0061] That is, in the semiconductor device shown in FIG. 2, the gate electrode 110 of the transistor 160 and The source electrode or drain electrode 142a of the transistor 162 is connected to the electrode 130c and the electrode 1 36c, the electrodes 150c, 154c and 150d are electrically connected to each other. do.

[0062] <Method for manufacturing semiconductor device> Next, an example of a method for manufacturing the above semiconductor device will be described. A method for fabricating the transistor 160 will be described with reference to FIG. A method for producing the heater 162 will be described with reference to FIGS.

[0063] <How to make the lower transistor> First, a substrate 100 containing a semiconductor material is prepared (see FIG. 3(A)). The plate 100 may be a single crystal semiconductor substrate such as silicon or silicon carbide, or a polycrystalline semiconductor substrate. Compound semiconductor substrates such as silicon germanium, SOI substrates, etc. can be used. Here, a single crystal silicon substrate is used as the substrate 100 containing a semiconductor material. An example will be given.

[0064] A protective layer 102 is formed on the substrate 100 to serve as a mask for forming an element isolation insulating layer. (See FIG. 3(A)). The protective layer 102 is made of, for example, silicon oxide, silicon nitride, An insulating layer made of silicon oxynitride or the like can be used. In order to control the threshold voltage of a transistor, impurities that give n-type conductivity are used. The substrate 100 may be doped with an impurity element that imparts p-type conductivity or an impurity element that imparts p-type conductivity. In the case of silicon, impurities that give n-type conductivity are, for example, phosphorus or arsenic. In addition, examples of impurities that impart p-type conductivity include boron and aluminum. For example, nium, gallium, etc. can be used.

[0065] Next, etching is performed using the protective layer 102 as a mask, and the The part of the substrate 100 in the area where the semiconductor device is not attached (the exposed area) is removed. The conductor region 104 is formed (see FIG. 3(B)). It is preferable to use an etching gas or an etchant, but wet etching may also be used. The etching liquid can be appropriately selected depending on the material to be etched.

[0066] Next, an insulating layer is formed so as to cover the semiconductor region 104, and a region overlapping the semiconductor region 104 is The insulating layer is selectively removed to form an element isolation insulating layer 106 (see FIG. 3(B)). The insulating layer is formed using silicon oxide, silicon nitride, silicon nitride oxide, etc. Methods for removing the insulating layer include polishing such as CMP and etching. Either of them may be used. After the semiconductor region 104 is formed or after the element isolation insulation After the layer 106 is formed, the protective layer 102 is removed.

[0067] Next, an insulating layer is formed on the semiconductor region 104, and a layer containing a conductive material is formed on the insulating layer. do.

[0068] The insulating layer will later become the gate insulating layer and is obtained using a method such as CVD or sputtering. Silicon oxide, silicon nitride oxide, silicon nitride, hafnium oxide, aluminum oxide, etc. It is preferable to use a single layer or multilayer structure of a film containing aluminum, tantalum oxide, etc. The surface of the semiconductor region 104 is oxidized or nitrided by plasma treatment or thermal oxidation treatment. The insulating layer may be formed by the high density plasma treatment. Using a mixture of rare gases such as Xe and oxygen, nitrogen oxide, ammonia, nitrogen, hydrogen, etc. The thickness of the insulating layer is not particularly limited, but may be, for example, 1 nm or more and 10 nm or less. It can be made 0 nm or less.

[0069] The layer containing a conductive material is a metal material such as aluminum, copper, titanium, tantalum, or tungsten. Also, the insulating layer can be formed using a semiconductor material such as polycrystalline silicon containing a conductive material. The method of formation is not particularly limited, and examples of the method include deposition, C Various film formation methods such as the VD method, the sputtering method, and the spin coating method can be used. In this embodiment, the layer containing a conductive material is formed using a metal material. The following information will be provided.

[0070] Thereafter, the insulating layer and the layer containing the conductive material are selectively etched to form the gate insulating layer 108. Then, a gate electrode 110 is formed (see FIG. 3(C)).

[0071] Next, an insulating layer 112 is formed to cover the gate electrode 110 (see FIG. 3(C)). Phosphorus (P) or arsenic (As) is added to the conductive region 104 to form a shallow junction with the substrate 100. In this case, an impurity region 114 having a thickness of 100 nm is formed (see FIG. 3(C)). However, when forming a p-type transistor, Impurity elements such as boron (B) and aluminum (Al) can be added. By forming the region 114, a channel-forming region is formed below the gate insulating layer 108 of the semiconductor region 104. A region 116 is formed (see FIG. 3C). The concentration of the added impurity is appropriately set. However, when semiconductor elements are highly miniaturized, the concentration can be increased. In this embodiment, the impurity region 114 is formed after the insulating layer 112 is formed. However, the process of forming the insulating layer 112 after forming the impurity region 114 is adopted. It is also possible to say this.

[0072] Next, a sidewall insulating layer 118 is formed (see FIG. 3(D)). The layer 118 is formed by forming an insulating layer to cover the insulating layer 112 and then applying a highly anisotropic By applying a simple etching process, the film can be formed in a self-aligned manner. Then, the insulating layer 112 is partially etched to expose the upper surface of the gate electrode 110 and the impurity region 1 It is a good idea to expose the top surface of 14.

[0073] Next, a semiconductor device is formed so as to cover the gate electrode 110, the impurity region 114, the sidewall insulating layer 118, etc. Then, an insulating layer is formed in the region where the insulating layer contacts the impurity region 114. By doping the silicon substrate with ions such as phosphorus (P) or arsenic (As), a high-concentration impurity region 120 is formed (see FIG. 3(E)). After that, the insulating layer is removed, and the gate electrode 110, the sidewall insulating layer 118, A metal layer 122 is formed so as to cover the high concentration impurity region 120 and the like (see FIG. 3(E)). The metal layer 122 can be formed by a variety of film forming methods such as vacuum deposition, sputtering, and spin coating. The metal layer 122 can be formed using the semiconductor material that constitutes the semiconductor region 104. It is preferable to form the insulating layer using a metal material that reacts with the metal to form a low-resistance metal compound. Such metal materials include, for example, titanium, tantalum, tungsten, nickel, and cobalt. Examples include platinum and tungsten.

[0074] Next, a heat treatment is performed to react the metal layer 122 with the semiconductor material. A metal compound region 124 is formed in contact with the high concentration impurity region 120 (see FIG. 3(F)). When polycrystalline silicon or the like is used as the gate electrode 110, the gate electrode 110 A metal compound region is also formed in the portion in contact with the metal layer 122.

[0075] The heat treatment may be, for example, a heat treatment by irradiation with a flash lamp. Of course, other heat treatment methods may be used, but the chemical reaction involved in the formation of metal compounds is In order to improve the controllability of the heat treatment, it is desirable to use a method that can realize a very short heat treatment. The metal compound region is preferably formed by a reaction between a metal material and a semiconductor material. The metal compound region is formed in the region, and the conductivity is sufficiently increased. This sufficiently reduces the electrical resistance and improves the device characteristics. After forming region 124, metal layer 122 is removed.

[0076] Next, an interlayer insulating layer 126 and an interlayer insulating layer 127 are formed to cover the respective components formed by the above-mentioned steps. The interlayer insulating layer 126 and the interlayer insulating layer 128 are formed by using silicon oxide. Silicon, silicon oxide nitride, silicon nitride, hafnium oxide, aluminum oxide, tantalum oxide The insulating layer can be formed using a material containing an inorganic insulating material such as niobium. It is also possible to form the layer using an organic insulating material such as acrylic resin. The structure is a two-layer structure of an interlayer insulating layer 126 and an interlayer insulating layer 128. After the interlayer insulating layer 128 is formed, the surface of the interlayer insulating layer 128 may be subjected to a process such as CMP or etching. It is desirable to flatten the surface by using a method such as flattening.

[0077] Thereafter, openings are formed in the interlayer insulating layers 126 and 128, reaching the metal compound region 124. A source electrode or drain electrode 130a and a source electrode or drain electrode 130b are formed in the opening. The source electrode or drain electrode 130a or The source electrode or drain electrode 130b is formed by, for example, PVD or CVD in the area including the opening. After forming a conductive layer using a method such as a CMP method, the top is It can be formed by removing a portion of the conductive layer.

[0078] In addition, a part of the conductive layer is removed to form the source electrode or drain electrode 130a and the source electrode Alternatively, when forming the drain electrode 130b, the surface of the electrode is processed to be flat. For example, after forming a thin titanium film or titanium nitride film in the region including the opening, When a tungsten film is formed to fill the opening, the inclusions are removed by the subsequent CMP. The necessary tungsten film, titanium film, titanium nitride film, etc. are removed, and the flatness of the surface is improved. In this way, the source electrode or drain electrode 130a, By planarizing the surface including the source or drain electrode 130b, This makes it possible to form good electrodes, wiring, insulating layers, semiconductor layers, and the like.

[0079] In this case, the source electrode or drain electrode 130 in contact with the metal compound region 124 Although only the source electrode 130a or the drain electrode 130b is shown, in this process, The electrode in contact with the base electrode 110 (for example, the electrode 130c in FIG. 2) is also formed. A source electrode or drain electrode 130a, a source electrode or drain There is no particular limitation on the material that can be used for the electrode 130b, and various conductive materials can be used. For example, molybdenum, titanium, chromium, tantalum, tungsten, Conductive materials such as aluminum, copper, neodymium, and scandium can be used.

[0080] In this manner, a transistor 160 is formed using the substrate 100 containing a semiconductor material. After the above steps, electrodes, wiring, an insulating layer, etc. may be further formed. In addition, by adopting a multilayer wiring structure consisting of a laminated structure of interlayer insulating layers and conductive layers, Therefore, it is possible to provide a highly integrated semiconductor device.

[0081] <How to make the upper transistor> Next, referring to FIG. 4 and FIG. 5, a process for forming a transistor 162 on the interlayer insulating layer 128 will be described. 4 and 5 show various electrodes and transistors on the interlayer insulating layer 128. Since the figure shows the manufacturing process of the transistor 162, the The transistor 160 and other components that correspond to it are omitted.

[0082] First, an interlayer insulating layer 128, a source electrode or drain electrode 130a, An insulating layer 132 is formed on the drain electrode 130b and the electrode 130c (see FIG. 4(A)). The edge layer 132 can be formed by using a PVD method, a CVD method, or the like. Silicon oxide nitride, silicon nitride, hafnium oxide, aluminum oxide, tantalum oxide The insulating film 10 can be formed using a material containing an inorganic insulating material such as silica.

[0083] Next, the source or drain electrode 130a, the source or Openings are formed so as to reach the drain electrode 130b and the electrode 130c. An opening is also formed in the region where the gate electrode 136d is to be formed. A conductive layer 134 is formed so as to fill the opening (see FIG. 4B). The mask can be formed by a method such as etching using a photomask. It can be formed by a method such as exposure to light. As for etching, wet etching is used. Either etching or dry etching may be used, but from the viewpoint of fine processing, dry etching is preferred. The conductive layer 134 is preferably formed by a method such as PVD or CVD. The conductive layer 134 can be formed by a deposition method. are molybdenum, titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium Examples of conductive materials include aluminum, scandium, and their alloys and compounds (e.g., nitrides). Can be obtained.

[0084] More specifically, for example, a thin titanium film is formed by PVD in the area including the opening, and then CV After forming a thin titanium nitride film by the D method, a tungsten film is formed to fill the opening. Here, the titanium film formed by the PVD method is A bottom electrode (here, a source electrode or a drain electrode 130a, The oxide film on the surface of the electrode (130b, 130c, etc.) is reduced to reduce the contact resistance with the lower electrode. In addition, the titanium nitride film formed afterwards has the function of suppressing the diffusion of the conductive material. It also has a barrier function that suppresses the formation of a barrier film made of titanium or titanium nitride. After that, a copper film may be formed by plating.

[0085] After the conductive layer 134 is formed, the conductive layer 134 is etched or CMP is performed. 34 is removed to expose the insulating layer 132, and the electrodes 136a, 136b, and 136c are then 36c and a gate electrode 136d are formed (see FIG. 4(C)). Parts are removed to form electrodes 136a, 136b, 136c, and a gate electrode 136d. When doing so, it is desirable to process the insulating layer 13 so that the surface is flat. 2. Planarizing the surfaces of the electrodes 136a, 136b, 136c, and the gate electrode 136d This allows for the formation of good electrodes, wiring, insulating layers, semiconductor layers, etc. in subsequent processes. It becomes possible.

[0086] Next, the insulating layer 132, the electrode 136a, the electrode 136b, the electrode 136c, and the gate electrode 136d are The gate insulating layer 138 is formed so as to cover the gate insulating layer 138 (see FIG. 4(D)). The gate insulating layer can be formed by using a CVD method, a sputtering method, or the like. 138 is silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, aluminum oxide, oxide It is preferable to form the gate insulating film so as to contain hafnium, tantalum oxide, or the like. The layer 138 may have a single layer structure or a multilayer structure. Silicon oxynitride was produced by plasma CVD using silane (SiH4), oxygen, and nitrogen. The thickness of the gate insulating layer 138 is not particularly limited. However, for example, it can be set to 10 nm or more and 500 nm or less. For example, a first gate insulating layer having a thickness of 50 nm to 200 nm and a first gate insulating It is preferable to laminate a second gate insulating layer having a thickness of 5 nm to 300 nm on the layer.

[0087] Note that an oxide semiconductor (high-temperature oxide semiconductor) that has been made i-type or substantially i-type by removing impurities can be used. Since the purified oxide semiconductor is extremely sensitive to the interface states and the interface charges, When using such an oxide semiconductor for the oxide semiconductor layer, the interface with the gate insulating layer is important. That is, the gate insulating layer 138 in contact with the highly purified oxide semiconductor layer has a high quality There will be a demand for quality improvement.

[0088] For example, the high-density plasma CVD method using microwaves (2.45 GHz) produces dense, high-insulation-voltage This is advantageous in that a high quality gate insulating layer 138 can be formed. The contact between the conductor layer and the high-quality gate insulating layer reduces the interface state and improves the interface characteristics. This is because it can be made into something that is

[0089] Of course, if it can form a good insulating layer as a gate insulating layer, highly purified Even when an oxide semiconductor layer is used, other methods such as sputtering and plasma CVD are used. In addition, the film quality and the oxide semiconductor layer can be changed by heat treatment after the formation. Alternatively, an insulating layer may be applied to modify the interface characteristics of the gate insulating layer 138. In addition, the interface state density with the oxide semiconductor layer is reduced, and a good interface is obtained. All that is required is to form something that can form a surface.

[0090] When impurities are contained in an oxide semiconductor, stress such as a strong electric field or high temperature can cause The bond between the impurity and the main component of the oxide semiconductor is broken, and the resulting dangling bond is This induces a shift in Vth.

[0091] Impurities in the oxide semiconductor, particularly impurities such as hydrogen and water, are removed as much as possible, and the By improving the interface characteristics with the insulation layer, it is possible to withstand stresses such as strong electric fields and high temperatures. It is possible to obtain a more stable transistor.

[0092] Next, an oxide semiconductor layer is formed over the gate insulating layer 138 and etched using a mask. The oxide semiconductor layer is processed by the above method to form an island-shaped oxide semiconductor layer 140. (See Figure 4(E)).

[0093] The oxide semiconductor layer includes In-Ga-Zn-O, In-Sn-Zn-O, and In-A l-Zn-O series, Sn-Ga-Zn-O series, Al-Ga-Zn-O series, Sn-Al-Zn -O series, In-Zn-O series, Sn-Zn-O series, Al-Zn-O series, In-O series, Sn- It is preferable to use an O-based or Zn-O-based oxide semiconductor layer, and in particular an amorphous oxide semiconductor layer. In this embodiment, an In-Ga-Zn-O oxide semiconductor film is formed as the oxide semiconductor layer. The amorphous oxide semiconductor layer is formed by a sputtering method using a target for sputtering. Note that the addition of silicon to an amorphous oxide semiconductor layer suppresses the crystallization of the layer. Therefore, for example, a target containing SiO2 in an amount of 2% by weight or more and 10% by weight or less can be used. An oxide semiconductor layer may be formed using the above-mentioned method.

[0094] Examples of targets for forming an oxide semiconductor layer by a sputtering method include oxide A target for forming an oxide semiconductor film containing zinc as a main component can be used. A target for forming oxide semiconductor films containing Ga and Zn (composition ratio: In2O3:G A2O3:ZnO=1:1:1 [molar ratio]) can also be used. In, As a target for forming oxide semiconductor films containing Ga and Zn, In2O3:Ga2O3 :ZnO=1:1:2 [molar ratio], or In2O3:Ga2O3:ZnO=1:1: A target having a composition ratio of 4 [mol ratio] may be used. The target filling rate is 90% or more and 100% or less, preferably 95% or more (e.g., 99.9%). By using a target for oxide semiconductor deposition with a high filling rate, dense oxide A compound semiconductor layer is formed.

[0095] The oxide semiconductor layer is formed in a rare gas (typically, argon) atmosphere, an oxygen atmosphere, or a fluorine-containing gas atmosphere. Alternatively, it is preferable to use a mixed atmosphere of a rare gas (typically argon) and oxygen. Specifically, the concentration of impurities such as hydrogen, water, compounds having hydroxyl groups, or hydrides. It is preferable to use a high-purity gas in which the amount of ions is reduced to about several ppm (preferably about several ppb). It is appropriate.

[0096] When forming the oxide semiconductor layer, the substrate is held in a treatment chamber kept in a reduced pressure state. The temperature is set to 100°C or higher and 600°C or lower, preferably 200°C or higher and 400°C or lower. By forming the oxide semiconductor layer while performing the above-mentioned step, the impurity concentration in the oxide semiconductor layer can be reduced. In addition, damage to the oxide semiconductor layer caused by sputtering can be reduced. Then, the sputtering gas from which hydrogen and water have been removed is introduced while removing the residual moisture in the processing chamber. The oxide semiconductor layer is formed by using a metal oxide as a target. To remove the particles, it is preferable to use an adsorption type vacuum pump. For example, a cryopump A pump, an ion pump, or a titanium sublimation pump can be used. The stage may be a turbopump plus a cold trap. The deposition chamber evacuated using a pump contains, for example, hydrogen atoms, water ( Since compounds containing hydrogen atoms such as H2O are exhausted, the oxide semiconductor formed in the film formation chamber The concentration of impurities contained in the conductor layer can be reduced.

[0097] The formation conditions are, for example, a distance between the substrate and the target of 100 mm and a pressure of 0.6 Pa, DC power 0.5kW, oxygen atmosphere (oxygen flow rate 100%) The following conditions can be applied. When a pulsed direct current (DC) power supply is used, the deposition This reduces the amount of powdery material (also called particles or dust) that is generated during the coating process, and reduces the film thickness distribution. The thickness of the oxide semiconductor layer is preferably 2 nm to 200 nm, more preferably 5 The appropriate thickness varies depending on the oxide semiconductor material used. Therefore, the thickness may be appropriately selected depending on the material used.

[0098] Before forming the oxide semiconductor layer by sputtering, argon gas was introduced to the plasma A reverse sputtering process is performed to generate a smear, and dust adhering to the surface of the gate insulating layer 138 is removed. Here, the reverse sputtering is a method of removing the sputtering. Instead of bombarding the target with ions, the treatment surface is bombarded with ions. The method of modifying the surface by bombarding the surface with ions is as follows: A high-frequency voltage is applied to the processing surface side in an argon atmosphere to generate plasma near the substrate. In addition, the argon atmosphere can be replaced by a nitrogen atmosphere, a helium atmosphere, or an oxygen atmosphere. An atmosphere or the like may also be used.

[0099] The etching of the oxide semiconductor layer can be performed by either dry etching or wet etching. Of course, both can be used in combination. In order to match the etching conditions (etching gas, etching solution, etc.) to the material, The etching time, temperature, etc. should be set appropriately.

[0100] The etching gas used in dry etching is, for example, a gas containing chlorine (chlorine-based gas, For example, chlorine (Cl2), boron chloride (BCl3), silicon chloride (SiCl4), carbon tetrachloride ( CCl4) and others. In addition, gases containing fluorine (fluorine-based gases, such as carbon tetrafluoride) Fluorine (CF4), sulfur fluoride (SF6), nitrogen fluoride (NF3), trifluoromethane (CHF 3), hydrogen bromide (HBr), oxygen (O2), and the addition of helium (He) or ammonia to these gases. A gas containing an added rare gas such as argon (Ar) may also be used.

[0101] As a dry etching method, parallel plate type RIE (Reactive Ion Etch) ing method and ICP (Inductively Coupled Plasma) A method of etching a silicon wafer using a plasma-coupled plasma (PPS) can be used. As shown in the figure, the etching conditions (the amount of power applied to the coil-shaped electrode, the amount of power applied to the electrode on the substrate side) The power consumption, electrode temperature on the substrate side, etc. are set appropriately.

[0102] The etching solution used for wet etching is a mixture of phosphoric acid, acetic acid, and nitric acid. Alternatively, ITO07N (manufactured by Kanto Chemical Co., Ltd.) or the like may be used.

[0103] Next, the oxide semiconductor layer is preferably subjected to a first heat treatment. The temperature of the first heat treatment can be set to The temperature is set to 300° C. or higher and 750° C. or lower, preferably 400° C. or higher and lower than the distortion point of the substrate. For example, The substrate is placed in an electric furnace using a resistance heating element or the like, and the oxide semiconductor layer 140 is heated in a nitrogen atmosphere. Heat treatment is performed at 450° C. in air for 1 hour. During this time, the oxide semiconductor layer 140 is not exposed to the air. Avoid touching and recontamination with water or hydrogen.

[0104] The heat treatment device is not limited to an electric furnace, and may be any device that uses heat conduction from a medium such as a heated gas, or The apparatus may be a device that heats the object to be treated by thermal radiation. For example, a GRTA (Gas Rapid Thermal Anneal) equipment, LRTA (Lamp Rapid RTA (Rapid Thermal Anneal) equipment etc. The LRTA device can be equipped with halogen lamps, metal halide lamps, etc. Lamps, xenon arc lamps, carbon arc lamps, high pressure sodium lamps, high pressure water A device that heats the workpiece by radiating light (electromagnetic waves) emitted from a lamp such as a silver lamp. The GRTA device is a device that performs heat treatment using high-temperature gas. An inert gas that does not react with the workpiece during heat treatment, such as a rare gas such as argon or nitrogen. A gas is used.

[0105] For example, in the first heat treatment, the substrate is immersed in an inert gas heated to a high temperature of 650° C. to 700° C. After heating for a few minutes, the substrate is taken out of the inert gas (GRTA process). GRTA treatment allows high-temperature heat treatment in a short time. Because it is a heat treatment, it can be applied even under temperature conditions exceeding the distortion point of the substrate.

[0106] The first heat treatment is performed in a vacuum chamber mainly containing nitrogen or a rare gas (helium, neon, argon, etc.). It is preferable to carry out the process in an atmosphere that does not contain water, hydrogen, etc. The purity of nitrogen or rare gas such as helium, neon, or argon introduced into the heat treatment device is 6N (99.9999%) or more, preferably 7N (99.99999%) or more (i.e. , the impurity concentration is 1 ppm or less, preferably 0.1 ppm or less.

[0107] Depending on the conditions of the first heat treatment or the material of the oxide semiconductor layer, the oxide semiconductor layer may be crystallized. In some cases, the crystallinity is 90% or more, or 80% or less. % or more of the crystallinity of the oxide semiconductor layer. Depending on the material of the oxide semiconductor layer, the oxide semiconductor layer may be amorphous and not contain crystalline components. There are also cases where this is the case.

[0108] In addition, microcrystals (grain size of 1 nm or less) are formed in an amorphous oxide semiconductor (for example, on the surface of an oxide semiconductor layer). The oxide semiconductor layer is a mixture of 20 nm or less (typically 2 nm or more and 4 nm or less). There are cases like this.

[0109] In addition, the electrical characteristics of the oxide semiconductor layer can be changed by arranging microcrystals in the amorphous region. For example, it is possible to use an In-Ga-Zn-O oxide semiconductor film deposition target. When the oxide semiconductor layer is formed using a SiO2 oxide film, the In2Ga2Z oxide film has electrical anisotropy. By forming a microcrystalline part in which the crystal grains of nO7 are oriented, the electrical properties of the oxide semiconductor layer can be changed. It can be made into a.

[0110] More specifically, for example, the c-axis of In2Ga2ZnO7 is perpendicular to the surface of the oxide semiconductor layer. By orienting the oxide semiconductor layer in a direction parallel to the surface of the oxide semiconductor layer, the electrical conductivity in the direction parallel to the surface of the oxide semiconductor layer is improved. This can improve the insulating property in the direction perpendicular to the surface of the oxide semiconductor layer. The microcrystal parts have a function of suppressing the intrusion of impurities such as water and hydrogen into the oxide semiconductor layer. has.

[0111] Note that the oxide semiconductor layer having the above-described microcrystal portion is a GRTA-treated oxide semiconductor layer. It can be formed by heating. In addition, the Zn content is higher than the In or Ga content. By using a small sputtering target, it is possible to form the film more suitably.

[0112] The first heat treatment for the oxide semiconductor layer 140 is performed to process the oxide semiconductor layer 140 into an island-shaped oxide semiconductor layer 140. In that case, the first heat treatment is performed on the oxide semiconductor layer. The substrate is then removed and subjected to a photolithography process.

[0113] Note that the first heat treatment has an effect of dehydrating and dehydrogenating the oxide semiconductor layer 140. Therefore, it can also be called dehydration treatment, dehydrogenation treatment, etc. The hydrogenation process is carried out after forming the oxide semiconductor layer, by forming a source electrode or a drain electrode on the oxide semiconductor layer 140. After laminating the drain electrode, a protective insulating layer is formed on the source electrode or drain electrode. In addition, such dehydration treatment, dehydration The oxidation process may be carried out not only once but also multiple times.

[0114] Next, a source electrode or drain electrode 142a, The source or drain electrode 142b is formed (see FIG. 4(F)). The drain electrode 142a and the source or drain electrode 142b are formed on the oxide semiconductor layer 1 After forming a conductive layer so as to cover 40, the conductive layer is selectively etched. It can be formed.

[0115] The conductive layer is formed by using PVD methods such as sputtering and CVD methods such as plasma CVD. The conductive layer can be formed of a material such as aluminum, chromium, copper, Tantalum, titanium, molybdenum, tungsten, or any of the above elements. Manganese, magnesium, zirconium, beryllium, etc. can be used. Alternatively, one or more materials selected from the group consisting of aluminum, thorium, and aluminum alloy may be used. Titanium, tantalum, tungsten, molybdenum, chromium, neodymium, scandium Alternatively, a material containing a single element selected from the group consisting of aluminum and a combination of multiple elements may be used. It may be a single layer structure or a laminated structure of two or more layers. For example, Single-layer aluminum film structure, two-layer aluminum film with titanium film laminated on top, titanium and a three-layer structure in which a film, an aluminum film, and a titanium film are laminated.

[0116] Here, the exposure to light when forming the mask used for etching is ultraviolet light, KrF laser light, or ArF It is preferable to use laser light.

[0117] The channel length (L) of the transistor is defined as the distance between the bottom end of the source or drain electrode 142a and the is determined by the distance between the lower end of the source electrode or drain electrode 142b. When exposure is performed with a channel length (L) of less than 25 nm, the channel length is extremely small, ranging from a few nm to a few tens of nm. Extreme ultraviolet light with the shortest wavelength is used to create a mask. Exposure to extreme ultraviolet light provides high resolution and a large depth of focus. The channel length (L) of the formed transistor is set to 10 nm or more and 1000 nm or less. This allows for faster circuit operation. Furthermore, the off-state current is extremely small, This avoids a large power consumption.

[0118] In addition, when etching the conductive layer, the oxide semiconductor layer 140 is not removed. The materials and etching conditions are adjusted appropriately. In this step, a part of the oxide semiconductor layer 140 is etched to form a groove (a recess ) may be formed as an oxide semiconductor layer.

[0119] In addition, between the oxide semiconductor layer 140 and the source electrode or drain electrode 142a, An oxide conductive layer is formed between the conductor layer 140 and the source electrode or drain electrode 142b. The oxide conductive layer and the source or drain electrode 142a or The metal layer for forming the drain electrode 142b is formed continuously (continuous film formation). It is possible. The oxide conductive layer can function as a source region or a drain region. By providing such an oxide conductive layer, the resistance of the source region or the drain region can be reduced. This allows high speed operation of the transistor.

[0120] In order to reduce the number of masks used and the number of processes, an exposure method in which the transmitted light has multiple intensities is used. A resist mask is formed using a multi-tone mask, which is a mask, and the etching process is performed using this. The resist mask formed using the multi-tone mask has a plurality of thicknesses. The shape becomes stepped, and the shape can be further deformed by ashing. It can be used for multiple etching processes to process different patterns. A multi-tone mask is used to create resist masks that correspond to at least two different patterns. Therefore, the number of exposure masks can be reduced, and the corresponding photomasks can be formed. The lithography process can also be eliminated, simplifying the process.

[0121] After the above process, plasma treatment using gas such as N2O, N2, or Ar may be performed. It is preferable that the plasma treatment is performed on the exposed surface of the oxide semiconductor layer. Water and other adhering substances are removed. In addition, plasma treatment is performed using a mixture of oxygen and argon gas. You may go.

[0122] Next, the protective insulating layer 14 in contact with a part of the oxide semiconductor layer 140 is removed without exposing it to the air. Form 4 (see Figure 4(G)).

[0123] The protective insulating layer 144 is formed by mixing impurities such as water and hydrogen into the protective insulating layer 144 using a method such as sputtering. The thickness of the insulating film is 1 nm or more. Examples of materials that can be used for the protective insulating layer 144 include silicon oxide, silicon nitride, and silicon oxynitride. The structure may be a single layer structure or a multilayer structure. The substrate temperature when the protective insulating layer 144 is formed is set to be equal to or higher than room temperature and equal to or lower than 300° C. The atmosphere is preferably a rare gas (typically argon) atmosphere, an oxygen atmosphere, or a rare A mixture of gas (typically argon) and oxygen is preferred.

[0124] If hydrogen is contained in the protective insulating layer 144, the hydrogen may penetrate into the oxide semiconductor layer or may be oxidized by the hydrogen. As a result, oxygen is extracted from the oxide semiconductor layer, and the oxide semiconductor layer is Therefore, the resistance of the protective insulating layer 1 may become low, and a parasitic channel may be formed. It is important that 44 does not contain hydrogen as much as possible, and that hydrogen is not used in the formation method. It is.

[0125] In addition, it is preferable to form the protective insulating layer 144 while removing residual moisture in the processing chamber. The compound semiconductor layer 140 and the protective insulating layer 144 are preferably formed so as not to contain hydrogen, hydroxyl groups, or water. This is in order to do so.

[0126] In order to remove residual moisture from within the processing chamber, it is preferable to use an adsorption type vacuum pump. For example, cryopumps, ion pumps, and titanium sublimation pumps can be used. It is preferable that the exhaust means is a turbo pump with a cold trap added. The deposition chamber evacuated using a cryopump may be filled with hydrogen atoms, water (H2 O) and other compounds containing hydrogen atoms have been removed, The concentration of impurities contained in the layer 144 can be reduced.

[0127] The sputtering gas used in forming the protective insulating layer 144 contains hydrogen, water, and a hydroxyl group. The concentration of impurities such as compounds or hydrides is on the order of a few ppm (preferably on the order of a few ppb). It is preferable to use a high purity gas in which the concentration has been reduced to 100%.

[0128] Then, a second heat treatment (preferably for 20 It is preferable to carry out the heating at a temperature between 0°C and 400°C, for example between 250°C and 350°C. The second heat treatment is performed at 250° C. for 1 hour in a nitrogen atmosphere. This makes it possible to reduce the variation in the electrical characteristics of the transistors.

[0129] In addition, even if heat treatment is performed in air at 100°C to 200°C for 1 hour to 30 hours, This heat treatment may be performed by maintaining a constant heating temperature or by heating from room temperature to 100°C or higher. Repeat heating to a temperature of 200°C or less and then cooling from the heating temperature to room temperature several times. Moreover, this heat treatment may be carried out under reduced pressure before the formation of the protective insulating layer. When the heat treatment is performed under reduced pressure, the heating time can be shortened. The treatment may be performed in place of the second heat treatment, or may be performed before or after the second heat treatment. stomach.

[0130] Next, an interlayer insulating layer 146 is formed on the protective insulating layer 144 (see FIG. 5(A)). The edge layer 146 can be formed by using a PVD method, a CVD method, or the like. Silicon oxide nitride, silicon nitride, hafnium oxide, aluminum oxide, tantalum oxide The interlayer insulating layer 146 can be formed using a material containing an inorganic insulating material such as fluorine. After that, it is desirable to flatten the surface by a method such as CMP or etching. It is nice.

[0131] Next, an electrode 1 is formed on the interlayer insulating layer 146, the protective insulating layer 144, and the gate insulating layer 138. 36a, electrode 136b, electrode 136c, source or drain electrode 142a, source An opening is formed so as to reach the electrode or drain electrode 142b, and a conductive material is embedded in the opening. A conductive layer 148 is formed (see FIG. 5B). The opening is formed by etching using a mask or the like. The mask can be formed by a method such as exposure using a photomask. The etching method can be wet etching or dry etching. However, from the viewpoint of fine processing, it is preferable to use dry etching. The conductive layer 148 is preferably formed by a film forming method such as a PVD method or a CVD method. Materials that can be used to form the conductive layer 148 include molybdenum, titanium, and the like. Tantalum, chromium, tantalum, tungsten, aluminum, copper, neodymium, scandium, etc. Examples of the conductive materials include any of the conductive materials, their alloys, and compounds (e.g., nitrides).

[0132] Specifically, for example, a thin titanium film is formed in the area including the opening by the PVD method, and then the titanium film is removed by the CVD method. After forming a thin titanium nitride film by , a tungsten film is formed so as to fill the opening. Here, the titanium film formed by the PVD method is Electrodes (here, electrodes 136a, 136b, 136c, source electrodes or drain electrodes) The oxide film formed on the surface of the electrode 142a, the source electrode or the drain electrode 142b is reduced. This has the function of reducing the contact resistance with the lower electrode. The silicon film has a barrier function that suppresses the diffusion of conductive materials. After forming a barrier film such as a copper film, a copper plating method may be used to form the copper film.

[0133] After the conductive layer 148 is formed, the conductive layer 148 is etched or CMPed. Electrodes 150a, 150b, and 150c are then removed to expose the interlayer insulating layer 146. 50c, an electrode 150d, and an electrode 150e are formed (see FIG. 5(C)). A part of 148 is removed to form electrodes 150a, 150b, 150c, 150d, and When forming the pole 150e, it is desirable to process it so that the surface is flat. As shown in FIG. 1, the interlayer insulating layer 146, the electrode 150a, the electrode 150b, the electrode 150c, the electrode 150d, By planarizing the surface of the electrode 150e, it is possible to obtain good electrodes, wiring, and insulation in the subsequent steps. It is possible to form an edge layer, etc.

[0134] Further, an insulating layer 152 is formed, and the electrodes 150a, 150b, and 150c are attached to the insulating layer 152. 50c, the electrode 150d, and the electrode 150e are formed, and the After forming the conductive layer as described above, a part of the conductive layer is removed by a method such as etching or CMP. , the insulating layer 152 is exposed, and the electrodes 154a, 154b, 154c, and 154 This step is the same as that for forming the electrodes 150a, etc. Therefore, I will omit the details.

[0135] In the case where the transistor 162 is manufactured by the above-described method, the hydrogen concentration in the oxide semiconductor layer 140 is Degree is 5 x 10 19 atoms / cm 3 and the off-current of the transistor 162 is The hydrogen concentration is sufficiently reduced and the purity is increased. By using the oxide semiconductor layer 140, the transistor 162 with excellent characteristics can be obtained. In addition, a transistor 160 using a material other than an oxide semiconductor is provided in the lower portion, A semiconductor device having excellent characteristics and including a transistor 162 using an oxide semiconductor in a portion is manufactured. It is possible.

[0136] In addition, examples of semiconductor materials that can be compared to oxide semiconductors include silicon carbide (e.g., 4H Oxide semiconductors and 4H-SiC have several things in common. One example is the intrinsic carrier density of oxide semiconductors at room temperature. -7 / cm 3 Process This is estimated to be 6.7 × 10 -11 / cm 3 Similar to , which is an extremely low value. The intrinsic carrier density of silicon (1.4×10 10 / cm 3 degree) When compared to this, it is easy to see how extraordinary the situation is.

[0137] In addition, the energy band gap of oxide semiconductors is 3.0 to 3.5 eV, and The energy band gap of iC is 3.26 eV, so it is called a wide-gap semiconductor. In this respect, oxide semiconductors and silicon carbide have in common.

[0138] On the other hand, there is a very big difference between oxide semiconductors and silicon carbide. The process temperature is 1500℃ to 2000℃. However, it is difficult to form a laminated structure with semiconductor elements using other semiconductor materials. This is because the semiconductor substrate and semiconductor elements are destroyed. It is made by heat treatment at 300℃ to 500℃ (below the glass transition temperature, at most about 700℃). It is possible to form an integrated circuit using other semiconductor materials and then use an oxide semiconductor. This makes it possible to form a semiconductor element.

[0139] In addition, unlike silicon carbide, it is possible to use substrates with low heat resistance, such as glass substrates. Furthermore, compared to silicon carbide, it has the advantage that it does not require high-temperature heat treatment. This has the advantage that the energy cost can be sufficiently reduced.

[0140] Although there have been many studies on the physical properties of oxide semiconductors, In one embodiment of the disclosed invention, the localized level is not sufficiently reduced. By removing water and hydrogen, which can cause intrinsic levels, from the oxide semiconductor, a highly purified oxide semiconductor can be obtained. This is to create a semiconductor that sufficiently reduces the localized levels in the energy gap. This is the idea that allows us to manufacture extremely superior industrial products. This makes it possible.

[0141] In addition, oxygen is supplied to the dangling bonds of metals that are generated due to oxygen deficiency, and oxygen vacancies are formed. By reducing the localized levels, a more highly purified (i-type) oxide semiconductor can be obtained. For example, an oxide film containing excess oxygen is formed in contact with the channel formation region, By supplying oxygen from the oxide film, it is possible to reduce localized levels caused by oxygen defects. .

[0142] Defects in oxide semiconductors include shallow levels below the conduction band caused by excess hydrogen and deep levels caused by a lack of oxygen. In order to eliminate these defects, hydrogen is thoroughly Remove and provide sufficient oxygen.

[0143] Conduction mechanism of transistors using oxide semiconductors Next, the conduction mechanism of a transistor using an oxide semiconductor will be described with reference to FIGS. In the following description, an ideal situation is assumed for ease of understanding.

[0144] FIG. 11 is a cross-sectional view of an inverted staggered transistor using an oxide semiconductor. an oxide semiconductor layer (OS) is provided on a gate insulating layer (GI) on a pole layer (GE1); A source electrode (S) and a drain electrode (D) are provided thereon.

[0145] FIG. 12(A) and FIG. 12(B) show the energy band structure on the line A-A' in FIG. FIG. 12(A) shows the state when no voltage is applied to the gate electrode layer (V G =0), and No voltage is applied to either the drain electrode or the source electrode, or the same voltage is applied to both. This is the case (V S =V D = 0, or V S =V D ) Figure 12(B) shows the drain electrode Positive voltage (V D >0), the dashed line shows the case where no voltage is applied to the gate electrode layer (V G =0), the solid line indicates a positive voltage (V G >0) is applied. When no voltage is applied to the electrode layer, the high potential barrier prevents the oxide semiconductor from This indicates the off state where no carriers (electrons) are injected into the body and no current flows. When a positive voltage is applied to the electrode layer, the potential barrier is lowered, indicating an on-state in which current flows.

[0146] 13(A) and 13(B) show energy band diagrams in the cross section taken along line B-B' in FIG. FIG. 13(A) shows a gate electrode layer (GE1) with a positive potential (V G >0) In a given state, carriers (electrons) flow between the source and drain electrodes. FIG. 13B shows the gate electrode layer (GE1) in a negative potential (V G <0) is applied and the transistor is in the off state (no minority carriers flow). show.

[0147] Figure 14 shows the relationship between the vacuum level and the work function (φ M ) and the electron affinity (χ) of the oxide semiconductor Shows.

[0148] Metals are degenerate, with the Fermi level located within the conduction band. On the other hand, conventional oxide semiconductors n-type, and its Fermi level (E f ) is the intrinsic Fermi element located in the middle of the band gap. Level (E i ) and is located closer to the conduction band. It is known that some of the oxygen deficiencies act as donors and are one of the factors that cause n-type structures. It is known that loss is also a factor in the n-type conversion.

[0149] In contrast, an oxide semiconductor according to one embodiment of the disclosed invention can convert hydrogen, which is a factor in making the oxide semiconductor n-type, into an oxide. The oxide semiconductor is made of a material that is free from elements (impurity elements) other than the main components of the oxide semiconductor. By purifying the material so that it is not oxidized, and removing the oxygen vacancies, it is made into an intrinsic (i-type) material, or In other words, instead of adding impurity elements to make it i-type, By removing impurities such as hydrogen and water, and oxygen vacancies as much as possible, highly purified i-type (intrinsic This is characterized by the fact that the Fermi level (E f ) is the intrinsic Fermi level (E i ) can be considered to be equivalent to

[0150] The band gap of oxide semiconductors (E g ) is 3.15 eV, and the electron affinity (χ) is 4.3 e V. The work function of titanium (Ti), which constitutes the source and drain electrodes, is The electron affinity (χ) of the oxide semiconductor is approximately equal to that of the metal-oxide semiconductor interface. In this case, no Schottky barrier is formed for electrons.

[0151] Metal work function (φ M When the electron affinity (χ) of the oxide semiconductor is equal to that of the oxide semiconductor, As a result, an energy band diagram (schematic diagram) such as that shown in FIG. 12(A) is obtained.

[0152] In FIG. 12(B), black circles (●) represent electrons. When a positive potential is applied to the drain electrode, The electrons cross the barrier (h) and are injected into the oxide semiconductor, where they flow toward the drain electrode. The height of the barrier (h) depends on the gate voltage (V G ) but depends on the positive drain voltage When a voltage is applied to the drain electrode, the barrier height in FIG. 12(A) without voltage application, That is, the band gap (E g ) or lower.

[0153] At this time, the electrons pass through the gate insulating layer and the highly purified oxide semiconductor, as shown in FIG. The electrons move near the interface with the body (the most energetically stable part of the oxide semiconductor).

[0154] Also, as shown in FIG. 13(B), when a negative potential is applied to the gate electrode (GE1), Since the number of holes, which are minority carriers, is essentially zero, the current is close to zero. .

[0155] For example, the off-state current at room temperature (25°C) is 10zA / μm (1×10 -20 A / μm ) or less, or 1zA / μm(1×10 -21 A / μm) or less, and therefore A transistor with a threshold swing value (S value) of 0.1V / dec. is obtained.

[0156] In this way, the oxide semiconductor is prepared so that impurities other than the main component of the oxide semiconductor are not included as much as possible. High purification can improve the operation of the transistor.

[0157] <Modification> 6 to 9 show modified examples of the configuration of the semiconductor device. In the following, the following modified examples are A description will be given of a transistor 162 having a different configuration from that described above. The configuration of the controller 160 is the same as that described above.

[0158] In FIG. 6, a gate electrode 136d is provided under an oxide semiconductor layer 140, and a source electrode or drain electrode The drain electrode 142a and the source electrode or drain electrode 142b are formed on the oxide semiconductor layer 14. The lower surface of the transistor 162 is in contact with the oxide semiconductor layer 140. Here, an example is shown. The structure of the plane can be changed appropriately according to the cross section. Only the surface will be shown.

[0159] The major difference between the configuration shown in FIG. 6 and the configuration shown in FIG. 2 is that the source electrode or the drain electrode The connection between the oxide semiconductor layer 140 and the source or drain electrode 142a or 142b That is, in the configuration shown in FIG. 2, , the source electrode or drain electrode 142a, the source electrode or drain electrode 142b, 6, the oxide semiconductor layer 140 is in contact with the lower surface of the oxide semiconductor layer 140. The source electrode or drain electrode 142a and the source electrode or drain electrode 142b are in contact with each other. Due to this difference in contact, the arrangement of other electrodes, insulating layers, etc. may differ. The details of each component are the same as those in Figure 2.

[0160] Specifically, a gate electrode 136d provided on the interlayer insulating layer 128 and a gate electrode 136 d, and a source electrode 134 is provided on the gate insulating layer 138. a source or drain electrode 142a, a source or drain electrode 142b, and a source electrode or in contact with the upper surface of the drain electrode 142a, the source electrode or the drain electrode 142b. and an oxide semiconductor layer 140.

[0161] Here, the gate electrode 136d is embedded in the insulating layer 132 formed on the interlayer insulating layer 128. Similarly to the gate electrode 136d, the source electrode An electrode 136a is in contact with the drain electrode 130a, and a source or drain electrode 130b is in contact with the drain electrode 130b. An electrode 136b is formed in contact with the electrode 130c, and an electrode 136c is formed in contact with the electrode 130c. do.

[0162] In addition, a protective layer is provided on the transistor 162 so as to be in contact with part of the oxide semiconductor layer 140. An insulating layer 144 is provided, and an interlayer insulating layer 146 is provided on the protective insulating layer 144. Here, the protective insulating layer 144 and the interlayer insulating layer 146 are provided with a source electrode or a drain electrode. The openings reach the source electrode 142a and the source or drain electrode 142b. Through the opening, the electrode 150d and the electrode 150e are connected to the source electrode or the drain electrode. The electrode 142a is formed in contact with the source electrode or the drain electrode 142b. As well as the electrode 150d and the electrode 150e, the gate insulating layer 138, the protective insulating layer 144, the interlayer insulating The layer 146 is provided with openings through which the electrodes 136a, 136b, and 136c are in contact. Electrodes 150a, 150b, and 150c are formed.

[0163] An insulating layer 152 is provided on the interlayer insulating layer 146, and a buried insulating film is formed in the insulating layer 152. Electrodes 154a, 154b, 154c, and 154d are provided so that the electrodes 154a, 154b, 154c, and 154d are inserted into the Here, electrode 154a is in contact with electrode 150a, and electrode 154b is in contact with electrode 150. b, electrode 154c is in contact with electrode 150c and electrode 150d, and electrode 1 54d is in contact with electrode 150e.

[0164] FIG. 7 shows an example of a structure in which a gate electrode 136d is provided on an oxide semiconductor layer 140. FIG. 7A shows a source electrode or drain electrode 142a and a source electrode or drain The oxide semiconductor layer 140 is connected to the lower surface of the oxide semiconductor layer 140 by a contact electrode 142b. FIG. 7B shows a configuration example in which a source electrode or drain electrode 142a and a source The drain electrode 142b is formed on the upper surface of the oxide semiconductor layer 140. This is an example of a configuration in contact with the conductor layer 140.

[0165] The major difference between the configuration shown in FIG. 2 and FIG. 6 and the configuration shown in FIG. The difference is that the gate electrode 136d is provided. The major difference in the configuration is the source electrode or drain electrode 142a and The drain electrode 142b is disposed on either the lower surface or the upper surface of the oxide semiconductor layer 140. These differences lead to differences in other electrodes, insulation, and The arrangement of layers is different. The details of each component are the same as in Figure 2.

[0166] Specifically, in FIG. 7A, a source electrode or a drain electrode provided on an interlayer insulating layer 128 A source electrode 142a, a source or drain electrode 142b, and a source or drain electrode An oxide semiconductor in contact with the upper surface of the electrode 142a and the source or drain electrode 142b a gate insulating layer 138 provided on the oxide semiconductor layer 140; and a gate electrode 136 d in a region overlapping with the oxide semiconductor layer 140 on the gate electrode 138 .

[0167] In FIG. 7B, the oxide semiconductor layer 140 and the oxide A source electrode or drain electrode 1 is provided in contact with the upper surface of the semiconductor layer 140. 42a, a source electrode or drain electrode 142b, an oxide semiconductor layer 140, a source electrode or drain electrode 142a and a source or drain electrode 142b. The gate insulating layer 138 overlaps with the oxide semiconductor layer 140 on the gate insulating layer 138. and a gate electrode 136d in the region.

[0168] In addition, in the configuration shown in FIG. 7, compared with the configuration shown in FIG. 2, some components can be omitted. In this case, the manufacturing process can be simplified. Of course, this is not essential in the configuration shown in FIG. It goes without saying that components can be omitted.

[0169] FIG. 8 shows a case where the size of the element is relatively large, in which a gate electrode is provided under the oxide semiconductor layer 140. This is an example of a configuration having an electrode 136d. In this case, the requirements for surface flatness and coverage are satisfied. Since the requirements are relatively gentle, wiring, electrodes, etc. are formed by embedding them in the insulating layer. For example, the gate electrode 136 can be formed by patterning the conductive layer after it is formed. Although not shown here, it is possible to form the transistor 160 It is also possible to prepare the same.

[0170] The major difference between the configuration shown in FIG. 8(A) and the configuration shown in FIG. 8(B) is the source electrode or drain electrode. The source electrode 142a and the source or drain electrode 142b are formed on the oxide semiconductor layer 140. The question is whether the contact is made on the lower or upper surface of the Due to these differences, the arrangement of other electrodes, insulating layers, etc. is also different. The details of the components are the same as those in FIG.

[0171] Specifically, in FIG. 8A, a gate electrode 136d is provided on the interlayer insulating layer 128, A gate insulating layer 138 is provided on the gate electrode 136d. The source or drain electrode 142a, the source or drain electrode 142 b, and the source or drain electrode 142a, the source or drain electrode 142b and an oxide semiconductor layer 140 in contact with the upper surface of the substrate.

[0172] In FIG. 8B, a gate electrode 136d is provided on the interlayer insulating layer 128, and a gate A gate insulating layer 138 provided on the electrode 136d, and a gate electrode on the gate insulating layer 138 The oxide semiconductor layer 140 provided in a region overlapping with the oxide semiconductor layer 136d and the oxide semiconductor layer 140 A source electrode or drain electrode 142a provided in contact with the upper surface, a source electrode or a drain electrode 142b.

[0173] In addition, in the configuration shown in FIG. 8, components can be omitted compared to the configuration shown in FIG. In this case as well, the effect of simplifying the manufacturing process can be obtained.

[0174] FIG. 9 shows a case where the size of the element is relatively large, in which a gate is formed on the oxide semiconductor layer 140. This is an example of a configuration having an electrode 136d. In this case, too, the flatness of the surface and the coverage are important. Since the requirements for the insulation are relatively low, wiring and electrodes are embedded in the insulating layer. For example, the gate electrode 1 can be formed by patterning after the conductive layer is formed. Although not shown here, it is possible to form transistor 1 60 can be produced in the same manner.

[0175] The major difference between the configuration shown in FIG. 9(A) and the configuration shown in FIG. 9(B) is that the source electrode or the drain electrode The source electrode 142a and the source or drain electrode 142b are formed on the oxide semiconductor layer 140. The question is whether the contact is made on the lower or upper surface of the Due to these differences, the arrangement of other electrodes, insulating layers, etc. is also different. The details of the components are the same as those in FIG.

[0176] Specifically, in FIG. 9A, a source electrode or a drain electrode provided on an interlayer insulating layer 128 A source electrode 142a, a source or drain electrode 142b, and a source or drain electrode An oxide semiconductor in contact with the upper surface of the electrode 142a and the source or drain electrode 142b Layer 140, source or drain electrode 142a, source or drain electrode 1 42b, a gate insulating layer 138 provided on the oxide semiconductor layer 140, and a gate insulating layer 13 and a gate electrode 136d provided in a region overlapping with the oxide semiconductor layer 140 on the gate electrode 136. do.

[0177] In FIG. 9B, the oxide semiconductor layer 140 and the oxide A source electrode or drain electrode 1 is provided in contact with the upper surface of the semiconductor layer 140. 42a, source or drain electrode 142b, and source or drain electrode 14 2a, a source electrode or drain electrode 142b, and a gate electrode provided on the oxide semiconductor layer 140. The gate insulating layer 138 is provided in a region overlapping with the oxide semiconductor layer 140 on the gate insulating layer 138. and a gate electrode 136d.

[0178] In addition, in the configuration shown in FIG. 9, components can be omitted compared to the configuration shown in FIG. In this case as well, the effect of simplifying the manufacturing process can be obtained.

[0179] As described above, a semiconductor device having a novel structure can be realized according to one embodiment of the disclosed invention. In this embodiment, the transistor 160 and the transistor 162 are stacked. Although the above example has been described, the configuration of the semiconductor device is not limited to this example. In this embodiment, the channel lengths of the transistors 160 and 162 are perpendicular to each other. The positional relationship between the transistor 160 and the transistor 162 is the same as that in the above example. Furthermore, the transistor 160 and the transistor 162 may be overlapped. It may be provided.

[0180] For ease of understanding, the present embodiment will be described with reference to a semiconductor device having a minimum storage unit (1 bit). However, the configuration of the semiconductor device is not limited to this. By appropriately connecting the above semiconductor devices, more advanced semiconductor devices can be constructed. By using multiple devices, it is possible to configure a NAND type or NOR type semiconductor device. The configuration is not limited to that shown in FIG. 1 and can be modified as appropriate.

[0181] The semiconductor device according to this embodiment has a very low off-state current characteristic of the transistor 162. It is possible to retain information for a long period of time. In other words, it is the type of memory required for DRAM. No refresh operation is required, and power consumption can be reduced. It is possible to use the semiconductor device as a photo-emissive semiconductor device.

[0182] In addition, in order to write information by switching the transistor 162, It does not require high voltage and does not have the problem of element degradation. Furthermore, it is possible to turn the transistor on and off with a This allows information to be written and erased, and high-speed operation can be easily achieved. This is because it is possible to directly rewrite information by controlling the voltage applied to the transistor. Another advantage is that no action is required to erase the information.

[0183] In addition, a transistor using a material other than an oxide semiconductor is Compared to the conventional EEPROM, it can operate at higher speeds, so by using this, the contents of the memory can be It is possible to perform reading at high speed.

[0184] The structures, methods, and the like described in this embodiment may be combined as appropriate with the structures, methods, and the like described in other embodiments. They can be used in combination.

[0185] (Embodiment 2) In this embodiment, a structure and a manufacturing method of a semiconductor device according to another embodiment of the disclosed invention will be described. This will be described with reference to FIG.

[0186] 15A shows an example of a circuit configuration of a semiconductor device. The difference from FIG. 1 is that a capacitor 16 That is, in FIG. 15A, the source electrode of the transistor 162 One of the gate and drain electrodes of the capacitor 164 and the gate of the transistor 160 are connected to the gate electrode of the capacitor 164. The first wiring (1st Line: source line) is electrically connected to the source electrode. BL) and the source electrode of the transistor 160 are electrically connected to each other, and the second wiring (2nd Line: also called bit line BL) and the drain electrode of transistor 160 , electrically connected. In addition, a third wiring (3rd Line: the first signal line S1 The other of the source electrode and the drain electrode of the transistor 162 is electrically connected to A fourth line (also called a second signal line S2) and a transistor The gate electrode of the fifth wiring (5th Li ne: also referred to as a word line WL) and the other electrode of the capacitor element 164 are electrically connected. Note that in FIG. 15, in order to illustrate that the transistor is formed using an oxide semiconductor, The OS code is also included.

[0187] Here, the above-described transistor including an oxide semiconductor is used as the transistor 162. A transistor including an oxide semiconductor has a feature of having an extremely low off-state current. Therefore, by turning off the transistor 162, the gate of the transistor 160 is turned on. It is possible to hold the potential of the gate electrode for an extremely long period of time. 164, the charge applied to the gate electrode of the transistor 160 is retained. This makes it easier to read out the stored information.

[0188] The transistor 160 is not particularly limited. From the viewpoint of this, for example, transistors using single crystal silicon, etc. It is preferable to use high speed transistors.

[0189] In the semiconductor device shown in FIG. 15A, the potential of the gate electrode of the transistor 160 can be held. By taking advantage of this feature, it is possible to write, retain, and read information as follows: .

[0190] First, the writing and holding of information will be explained. The transistor 162 is turned on by applying a potential that turns the transistor 162 on. As a result, the potential of the third wiring is applied to the gate electrode of the transistor 160 and the That is, a predetermined charge is applied to the gate electrode of the transistor 160. Here, the charge that gives two different potentials (hereafter, the charge that gives the low potential) is Charge Q L , the charge that gives the high potential is charge Q H (called transistor 16) The gate electrode of the transistor is set to zero. The storage capacity may be improved by applying a charge to the fourth wiring. The transistor 162 is turned off by applying a potential to the transistor 162. As a result, the charge applied to the gate electrode of the transistor 160 is retained (retained).

[0191] Since the off-state current of the transistor 162 is extremely small, the gate electrode of the transistor 160 The charge is retained for a long period of time.

[0192] Next, the reading of information will be described. In this state, when an appropriate potential (read potential) is applied to the fifth wiring, the gate of the transistor 160 Depending on the amount of charge held in the transistor electrode, the second wiring has a different potential. If the transistor 160 is an n-channel type, then the gate electrode of the transistor 160 is connected to Q H is given The apparent threshold V th_H is connected to the gate electrode of transistor 160. L but Given the apparent threshold V th_L This is because the temperature is lower than that of the The threshold voltage of the transistor 160 is the fifth threshold voltage required to turn the transistor 160 "on". Therefore, the potential of the fifth wire is V th_H and V th_L By setting the potential V0 at the midpoint between For example, in writing, Q H If given, the fifth wire The potential of V0 (>V th_H ), transistor 160 is in the "on state." Q L is given, the potential of the fifth wire is V0( <V th_L ) even if The transistor 160 remains in the "off state." Therefore, the potential of the second wiring is not observed. The stored information can be read out.

[0193] When memory cells are arranged in an array, only the information of a desired memory cell is read. In this way, it is necessary to read the information of a specific memory cell and When the information of the other memory cells is not read, the first memory cell of the memory cell that is not the object of reading is For the wiring of 5, the transistor 160 is in the "off state" regardless of the state of the gate electrode. That is, V th_H Alternatively, a smaller potential can be applied to the gate. The potential at which transistor 160 is "on" regardless of its polarity, i.e., V th_L A larger potential may be applied to the fifth wiring.

[0194] Next, the rewriting of information will be described. The rewriting of information includes the above-mentioned writing of information and That is, the potential of the fourth wiring is held in the same manner as when the transistor 162 is turned on. This causes the transistor 162 to be turned on. (a potential related to new information) is applied to the gate electrode of the transistor 160 and the capacitor 164. After that, the potential of the fourth wiring is set to a potential at which the transistor 162 is turned off. By turning off the transistor 162, the gate voltage of the transistor 160 is The poles are now given a charge related to the new information.

[0195] In this way, the semiconductor device according to the disclosed invention can directly read data by rewriting the data. It is possible to rewrite information. This is why it is necessary for flash memory etc. This eliminates the need to extract charge from the floating gate using high voltages, and the erase operation In other words, it is possible to suppress the decrease in the operating speed caused by the above-mentioned problem. It will be revealed.

[0196] The source electrode or drain electrode of the transistor 162 is connected to the gate of the transistor 160. The flow cell is electrically connected to a gate electrode, and is used as a non-volatile memory element. This has the same effect as the floating gate of a floating gate type transistor. In the figure, the source electrode or drain electrode of the transistor 162 and the gate of the transistor 160 The portion to which the gate electrode is electrically connected is sometimes called the floating gate portion FG. When the transistor 162 is off, the floating gate portion FG is embedded in an insulator. It can be seen that the floating gate portion FG holds electric charge. The off-state current of the transistor 162 using Since the capacitance is less than 1 / 100,000 of that of the transistor 162, the floating It is possible to ignore the loss of charge stored in the gate FG. The transistor 162 using the semiconductor material enables non-volatile storage of data even without power supply. It is possible to realize a storage device having a high degree of reliability.

[0197] For example, the off-state current of the transistor 162 at room temperature (25° C.) is 10 zA (1 zA Ampere) is 1 x 10 -21 A) or less, and the capacitance value of the capacitance element 164 is about 10 fF. In some cases, at least 10 4 It is possible to hold data for more than 100 seconds. However, it goes without saying that this varies depending on the transistor characteristics and capacitance value.

[0198] In this case, the gate problem pointed out in the conventional floating gate type transistor is There is no problem of deterioration of the gate insulating film (tunnel insulating film). This solves the problem of deterioration of the gate insulating film when electrons are injected into the floating gate. This means that there is no theoretical limit to the number of times you can write to a file. In addition, the conventional floating gate transistor requires The high voltage that was previously required is no longer necessary.

[0199] The semiconductor device shown in FIG. 15A includes elements such as transistors constituting the semiconductor device. It can be considered as including resistance and capacitance as shown in FIG. In FIG. 15B, the transistor 160 and the capacitor 164 are respectively a resistor and a R1 and C1 are considered to be composed of a resistor and a capacitance. The resistance value R1 is the resistance and capacitance value of the capacitance element 164. R2 and C2 correspond to the resistance of the edge layer. The resistance and capacitance of the transistor 160 are the gate resistance and capacitance of the transistor 160 when the transistor 160 is in the on state. The capacitance C2 corresponds to the resistance of the insulating layer, and is the so-called gate capacitance (the capacitance between the gate electrode and the source A capacitance formed between the gate electrode or the drain electrode, and a gate electrode and a channel forming region This corresponds to the capacitance value of the capacitance formed between

[0200] The resistance between the source and drain electrodes of the transistor 162 when it is in the off state (actual If the gate leakage of transistor 162 is sufficiently small, then In the condition, if R1 and R2 satisfy R1 ≧ ROS and R2 ≧ ROS, the charge The retention period (or information retention period) of the current is mainly due to the on-state of the transistor 162. The input current is determined by the input current.

[0201] On the other hand, if this condition is not satisfied, the off-state current of the transistor 162 is not sufficiently small. In addition, it becomes difficult to secure a sufficient retention period. The leakage current (for example, the leakage current generated between the source electrode and the gate electrode) is large. For this reason, the semiconductor device disclosed in this embodiment has the above-mentioned characteristics. It is desirable that the above conditions be satisfied.

[0202] On the other hand, it is desirable that C1 and C2 satisfy the relationship C1 ≧ C2. When controlling the potential of the floating gate portion FG by the fifth wiring (for example, when reading This is because the fluctuation in the potential of the fifth wiring can be kept low when the fifth wiring is opened (when the fifth wiring is opened).

[0203] By satisfying the above-mentioned relationship, it is possible to realize a more suitable semiconductor device. R1 and R2 are formed by the gate insulating layer of the transistor 160 and the insulating layer of the capacitance element 164. The same applies to C1 and C2. Therefore, the material and thickness of the gate insulating layer are It is desirable to appropriately set the length and other factors so as to satisfy the above-mentioned relationship.

[0204] In the semiconductor device shown in this embodiment, the floating gate portion FG is a flash Same function as the floating gate of a floating gate type transistor such as memory However, the floating gate portion FG of this embodiment is a floating gate of a flash memory or the like. In flash memory, the control gate has fundamentally different characteristics. The voltage applied to the floating gate of the adjacent cell is high, so the effect of the potential on the floating gate of the adjacent cell is large. In order to prevent this from reaching the cell, it is necessary to maintain a certain amount of space between the cells. This is one of the factors that hinder the high integration of semiconductor devices. This is due to the fundamental principle of flash memory, which is to generate a tunnel current by applying a magnetic field. It is something.

[0205] In addition, due to the above-mentioned principle of flash memory, the deterioration of the insulating film progresses, limiting the number of times it can be rewritten. Kai (10 4 ~10 5 Another problem arises:

[0206] The semiconductor device according to the disclosed invention is a transistor including an oxide semiconductor. This operates in this way and does not use the principle of charge injection by tunnel current as described above. Unlike flash memory, high electric fields are not required to inject charges. Since there is no need to consider the effect of the high electric field caused by the control gate on adjacent cells, Integration becomes easier.

[0207] In addition, since it does not use charge injection by tunnel current, there is no cause for degradation of memory cells. This means that it has higher durability and reliability than flash memory. .

[0208] In addition, flash memory does not require a high electric field or large peripheral circuits (such as a boost circuit). This is an advantage over memory.

[0209] The dielectric constant of the insulating layer constituting C1 is εr1, and the dielectric constant of the insulating layer constituting C2 is εr If the area S1 of C1 and the area S2 of C2 are different, 2·S2 ≧ S1( It is preferable to easily realize C1 ≧ C2 while satisfying S2 ≧ S1. For example, in C1, a film made of a high-k material such as hafnium oxide is used. The layer structure is a laminated structure of a film made of a high-k material such as hafnium oxide and a film made of an oxide semiconductor. is adopted to set εr1 to 10 or more, preferably 15 or more, and in C2, silicon oxide By adopting this, εr2 can be set to 3 to 4. By using this configuration in combination, Thus, the semiconductor device according to the disclosed invention can be highly integrated.

[0210] The above explanation applies to the case where an n-type transistor (n-channel transistor) is used. However, p-type transistors can be used instead of n-type transistors. It goes without saying.

[0211] As described above, in the semiconductor device according to one embodiment of the disclosed invention, A write transistor with low leakage current (off-state current) between the write transistors, A non-volatile memory including a read transistor and a capacitance element using a semiconductor material different from that of a transistor. The memory cell has:

[0212] The off-state current of the write transistor is 100 zA (1×10 -19 A) or less, preferably 10zA (1×10 -20 A) or less, more preferably 1 zA(1×10 -21 A) or less. In ordinary silicon semiconductors, the low ohmic Although it is difficult to obtain a high current, transistors obtained by processing oxide semiconductors under appropriate conditions can be used. For this reason, the write transistor can be made of an oxide semiconductor. It is preferable to use a transistor including:

[0213] Furthermore, transistors using oxide semiconductors have a small subthreshold swing (S value). Therefore, even if the mobility is relatively low, the switching speed can be sufficiently high. Therefore, by using the transistor as a writing transistor, This makes it possible to make the rise of the write pulse applied to the write gate FG extremely steep. In addition, since the off-current is small, the amount of charge held in the floating gate FG can be reduced. In other words, it is possible to reduce the number of transistors using an oxide semiconductor for writing. By using it as a transistor, information can be rewritten at high speed.

[0214] As the readout transistor, a transistor that operates at high speed is used to increase the readout speed. For example, a switching transistor is used as the read transistor. It is preferable to use transistors with speeds of 1 nanosecond or less.

[0215] Data is written to the memory cell by turning on the write transistor. One of the source electrode or the drain electrode of the writing transistor and the electrode of the capacitor element A floating gate electrode electrically connected to the gate electrode of the read transistor A potential is supplied to the gate FG, and then the write transistor is turned off. This is done by holding a certain amount of charge in the floating gate portion FG. Since the off-current of the transistor for loading is extremely small, the floating gate FG is The charge stored in the transistor is retained for a long time. If the off-current is, for example, substantially zero, The refresh operation required for the DRAM of This makes it possible to reduce the frequency of such repairs extremely (for example, once a month or once a year). This can significantly reduce the power consumption of the device.

[0216] It is also possible to directly rewrite information by writing it again to the memory cell. This eliminates the need for the erase operation required in flash memories, etc. It is possible to suppress the decrease in the operation speed caused by the erase operation. In addition, writing and erasing can be performed with conventional floating gate transistors. Since the high voltage required for the semiconductor device is not required, the power consumption of the semiconductor device is further reduced. The voltage applied to the memory cell according to the present embodiment (each terminal of the memory cell) The maximum value of the difference between the maximum and minimum potentials applied simultaneously to the When writing data, the voltage in one memory cell must be 5V or less, or 3V or less. It is possible.

[0217] A memory cell arranged in a semiconductor device according to the disclosed invention includes a write transistor and Since it is sufficient to include at least a read transistor, for example, one memory cell Compared to SRAM, which requires six transistors per memory cell, In other words, it is possible to form memory cells in a semiconductor device with high density. can be placed.

[0218] In addition, in conventional floating gate transistors, the gate insulating film (TFT) The charge transfer in the gate insulating film (tunnel insulating film) causes deterioration of the gate insulating film (tunnel insulating film). However, in the memory cell according to one embodiment of the present invention, Since information is written by the switching operation of the read transistor, the gate insulation There is no problem with film deterioration. This is because there is no theoretical limit to the number of times that data can be written, and the rewrite resistance is high. For example, a memory cell according to one embodiment of the present invention has 1×10 9 Even after more than 1 billion writes, the current-voltage characteristics showed no degradation. do not have.

[0219] Furthermore, a transistor using an oxide semiconductor as a writing transistor in a memory cell In the case of using an oxide semiconductor, the energy gap is generally large (for example, In-Ga - Zn-O system: 3.0 to 3.5 eV) Thermally excited carriers are extremely few, e.g. For example, no degradation is observed in the current-voltage characteristics of the memory cell even in a high-temperature environment of 150°C.

[0220] The transistor having the above-mentioned excellent characteristics is used as a write transistor for a memory cell. By applying the above-mentioned method, a semiconductor device having unprecedented features can be provided.

[0221] As described above, the configurations, methods, etc. described in this embodiment may be used in conjunction with the configurations, methods, etc. described in other embodiments. They can be used in any suitable combination.

[0222] (Embodiment 3) In this embodiment, an application example of a semiconductor device according to one embodiment of the disclosed invention will be described with reference to FIGS. This will be explained with reference to FIG.

[0223] FIG. 16 shows an outline of a semiconductor device according to this embodiment.

[0224] FIG. 16 is a diagram illustrating the semiconductor device shown in FIG. 1 or FIG. 15(A) (hereinafter, also referred to as a memory cell 1200). 1 is an example of a circuit diagram of a semiconductor device formed using a plurality of

[0225] The semiconductor device shown in FIG. 16 is a memory device in which a plurality of memory cells 1200 are arranged in a matrix. A rechargeable cell array, a first driving circuit 1211, a second driving circuit 1212, and a third driving circuit A fourth driving circuit 1213 is electrically connected to the fourth driving circuit 1214 and the first driving circuit 1211. In addition, a plurality of wirings L1 and a plurality of wirings L2 electrically connected to the second driving circuit 1212 a plurality of wirings L3 electrically connected to the third driving circuit 1213; and a fourth driving circuit and a plurality of wirings L4 electrically connected to 1214.

[0226] As shown in FIG. 16, each memory cell 1200 includes a wiring L1, a wiring L2, a wiring L3, and The wiring L4 is electrically connected. This allows each memory cell 1200 to be connected to the first drive circuit 1 211, a second driving circuit 1212, a third driving circuit 1213 and a fourth driving circuit 121 4 can be used to control the operation of the memory cells. The wiring L1, L2, L3, and L4 are arranged in a matrix, with the wiring L1, L2, L3, and L4 arranged in a grid in the row or column direction. By providing the memory cell 120, the write operation and the read operation of the semiconductor device can be performed. It can also be done row by row or column by column of 0's.

[0227] The memory cell 1200 shown in FIG. 16 includes a first driver circuit 1211 to a fourth driver circuit 1212. 1214 are electrically connected to each other, but the disclosed invention is However, it is not limited to this. A plurality of wirings are connected from one or more driving circuits to the memory cell 120. 0. Also, any one or more of the memory cells 120 0, the wiring of one or more of the drive circuits is not electrically connected. That's fine.

[0228] In the semiconductor device shown in FIG. 16, a first driver circuit 1211 and a second driver circuit 1212 The third driver circuit 1213 and the fourth driver circuit 1214 are provided independently. The disclosed invention is not limited to this. A driving circuit having one or more functions In order to ensure sufficient operating speed, the driving circuit is made of a single crystal semiconductor. It is preferable that the material used is bulk silicon (so-called silicon wafer). It is recommended to use the word "eha".

[0229] Next, a more specific configuration example will be described.

[0230] 17(A) and 17(B) are diagrams illustrating the semiconductor device (hereinafter, memory cell) shown in FIG. 17 is an example of a circuit diagram of a semiconductor device formed using a plurality of 1A shows a circuit diagram of a so-called NAND type semiconductor device in which memory cells 400 are connected in series. FIG. 17B shows a so-called NOR type in which memory cells 400 are connected in parallel. FIG. 2 is a circuit diagram of the semiconductor device.

[0231] The semiconductor device shown in FIG. 17A includes a source line SL, a bit line BL, a first signal line S1, and a plurality of The memory cell 400 includes a second signal line S2, a plurality of word lines WL, and a plurality of memory cells 400. In (A), there is one source line SL and one bit line BL. However, the present invention is not limited to this, and may have a configuration having a plurality of source lines SL and bit lines BL. stomach.

[0232] In each memory cell 400, the gate electrode of transistor 160 and the gate electrode of transistor 162 One of the source electrode and the drain electrode of the capacitor 164 is electrically connected to Also, the first signal line S1 and the source electrode or the drain electrode of the transistor 162 are connected to each other. The other of the gate electrodes is electrically connected to the second signal line S2 and the gate of the transistor 162. The electrode of the capacitor 164 is electrically connected to the word line WL. The other is electrically connected.

[0233] The source electrode of the transistor 160 in the memory cell 400 is connected to the adjacent memory cell The drain electrode of the transistor 160 in the memory cell 400 is electrically connected to the drain electrode of the transistor 160 in the memory cell 400. The drain electrode of the transistor 160 is connected to the drain electrode of the transistor of the adjacent memory cell 400. 160 is electrically connected to the source electrode of the memory cell 160. The drain of the transistor 160 of the memory cell 400 provided at one end of the The electrode is electrically connected to a bit line BL. Also, a plurality of memory cells are connected in series. The source voltage of the transistor 160 of the memory cell 400 provided at the other end of the The pole is electrically connected to a source line SL.

[0234] In the semiconductor device shown in FIG. 17A, writing and reading operations are performed row by row. A write operation is performed as follows. A transistor is connected to the second signal line S2 of the row to be written. A potential is applied to turn on the transistor 162 of the row to be written. As a result, the first signal line S is connected to the gate electrodes of the transistors 160 in the specified row. A potential of 1 is applied, and a predetermined charge is applied to the gate electrode. Data can be written to the memory cells in the selected row.

[0235] The read operation is performed as follows: First, the word lines WL other than the row from which the read is to be performed are In addition, regardless of the charge applied to the gate electrode of the transistor 160, the transistor 160 A potential is applied to turn on the transistors 160 other than the row to be read out. Then, the gate of the transistor 160 is connected to the word line WL of the row to be read. The charge carried by the electrode selects the on or off state of the transistor 160. Then, a constant potential is applied to the source line SL, and a constant potential is applied to the bit line The read circuit (not shown) connected to the source line BL is set to an operating state. The transistors 160 between the bit line SL and the bit line BL are turned on except for the row to be read. Since the read operation is in the read state, the conductance between the source line SL and the bit line BL is The state of the transistor 160 in the row is determined by the state (on or off). The charge on the gate electrode of the transistor 160 in the row that is being read out causes the transistor Since the conductance is different, the potential of the bit line BL will be different accordingly. The potential of the bit line BL is read by the read circuit, and the memory of the specified row is Information can be read from the recell.

[0236] The semiconductor device shown in FIG. 17B includes a source line SL, a bit line BL, a first signal line S1, a second The memory cell 400 includes a plurality of signal lines S2 and word lines WL. The gate electrode of each transistor 160 and the source electrode or drain of each transistor 162 One of the in-electrodes and one of the electrodes of the capacitor 164 are electrically connected to each other. The source line SL and the source electrode of the transistor 160 are electrically connected to each other, and the bit line BL and the drain electrode of the transistor 160 are electrically connected. S1 and the other of the source electrode or the drain electrode of the transistor 162 are electrically connected. The second signal line S2 and the gate electrode of the transistor 162 are electrically connected. The word line WL and the other electrode of the capacitor 164 are electrically connected to each other.

[0237] In the semiconductor device shown in FIG. 17B, writing and reading operations are performed row by row. The write operation is performed in the same manner as in the semiconductor device shown in FIG. The read operation is performed as follows. First, a transistor is connected to the word line WL other than the row to be read. The transistor 160 is turned off regardless of the charge applied to the gate electrode of the transistor 160. A potential such as this is applied to turn off the transistors 160 in the row other than the row to be read out. Then, the gate electrode of the transistor 160 is connected to the word line WL of the row to be read. The charge determines the potential ( A constant potential is applied to the source line SL, and a constant potential is applied to the bit line BL. A read circuit (not shown) connected to the source line SL is set to an operating state. The conductance between the lines BL is determined by the state (on state) of the transistor 160 of the row to be read. In other words, the transistors 160 of the row to be read out are determined by the The potential of the bit line BL will take on different values ​​depending on the charge carried by the gate electrode. The potential of the bit line BL is read by the read circuit, and the memory cells in the specified row are Information can be read out from the

[0238] In the above description, the amount of information stored in each memory cell 400 is 1 bit. The structure of the memory device described in the embodiment is not limited to this. Three or more potentials may be provided to increase the amount of information stored in each memory cell 400. For example, when four types of potentials are applied to the gate electrode of the transistor 160, Each memory cell can hold two bits of information.

[0239] Next, an example of a read circuit that can be used in the semiconductor device shown in FIG. This will be explained using 18.

[0240] FIG. 18A shows a schematic diagram of a read circuit. The read circuit is made up of a transistor and a The amplifier has a sense amplifier circuit.

[0241] When reading, terminal A is connected to the bit line BL to which the memory cell to be read is connected. A bias potential Vbias is applied to the gate electrode of the transistor, and The potential of the electrode is controlled.

[0242] The memory cell 400 exhibits different resistance values ​​depending on the data stored therein. When the transistor 160 of the selected memory cell 400 is in an on state, the memory cell 400 is in a low resistance state. When the transistor 160 of the selected memory cell 400 is in an off state, the memory cell 400 is in a high resistance state. .

[0243] When the memory cell is in a high resistance state, the potential of terminal A becomes higher than the reference potential Vref, and the sense The amplifier outputs a voltage corresponding to the voltage at terminal A. On the other hand, when the memory cell is in a low resistance state, Then, the potential of terminal A becomes lower than the reference potential Vref, and the sense amplifier circuit The corresponding potential is output.

[0244] In this way, by using the read circuit, data can be read from the memory cell. Note that the read circuit in this embodiment is just an example. Other circuits may be used. The read circuit may include a precharge circuit. The bit lines BL may be connected to each other.

[0245] FIG. 18B shows a differential sense amplifier, which is an example of a sense amplifier circuit. The amplifier has input terminals Vin(+) and Vin(-) and an output terminal Vout. The difference between the potentials of Vin(+) and Vin(-) is amplified. If the potential of Vin(+) is higher than Vin(-), Vout outputs a High signal. If the differential sense amplifier is connected to the read circuit, the Vout output is set to Low. When used in a circuit, one of Vin(+) and Vin(-) is connected to terminal A, and Vin(+) and A reference potential Vref is applied to the other terminal of Vin(-).

[0246] FIG. 18C shows a latch-type sense amplifier, which is an example of a sense amplifier circuit. The sense amplifier has input / output terminals V1 and V2, and input terminals for control signals Sp and Sn. First, set signal Sp to High and signal Sn to Low to cut off the power supply potential (Vdd). Then, apply potential V1in and V2in for comparison to V1 and V2 respectively. After that, when signal Sp is set to Low and signal Sn is set to High to supply the power supply potential (Vdd), if the potentials V1in and V2in for comparison are in the relationship V1in > V2in, the output of V1 will be High, the output of V2 will be Low, and if they are in the relationship V1in < V2in, the output of V1 will be Low and the output of V2 will be High. Utilizing such a relationship, the difference between V1in and V2in can be amplified. When using the latch-type sense amplifier in a read circuit, one of V1 and V2 is connected to terminal A and the output terminal via a switch, and a reference potential Vref is applied to the other of V1 and V2.

[0247] FIG. 19 is an example of a circuit diagram of a semiconductor device formed using a plurality of the semiconductor devices shown in FIG. 15(A). The semiconductor device shown in FIG. 19 has a storage capacity of m × n bits.

[0248] The semiconductor device according to FIG. 19 includes m word lines WL, m second signal lines S2, n bit lines BL, n source lines SL, n first signal lines S1, and a plurality of memory cells 1100 arranged in a matrix of m (rows) × n (columns) (m and n are natural numbers), and peripheral circuits such as a first drive circuit 1111, a second drive circuit 1112, a third drive circuit 1113, and a fourth drive circuit 1114. Here, as the memory cell 1100, the configuration described in the previous embodiment (for example, the configuration shown in FIG. 15(A)) is applied. ​

[0249] That is, each memory cell 1100 includes a first transistor 160, a second transistor 16 2 and a capacitor 164. One of a source electrode and a drain electrode of the second transistor 162 and a One of the electrodes is connected to the source line SL and the source electrode of the first transistor 160. is connected, and the bit line BL and the drain electrode of the first transistor 160 are connected. The first signal line S1 and the source electrode or the drain electrode of the second transistor 162 are connected to each other. The other is connected to the second signal line S2 and the gate electrode of the second transistor 162. , and the word line WL and the other electrode of the capacitor 164 are connected.

[0250] The memory cells 1100 are connected in parallel between a source line SL and a bit line BL. For example, a memory cell 1100(i,j) in row i and column j (i is an integer between 1 and m, j is an integer between 1 and m) is where n is an integer between 1 and n) represents the source line SL(j), the bit line BL(j), the first signal line S 1(j), a word line WL(i), and a second signal line S2(i), respectively.

[0251] The source line SL and the bit line BL are connected to a first driving circuit 1111. The signal line S1 is connected to the second driving circuit 1112, and the signal line S2 is connected to the third driving circuit 1113. The word line WL is connected to a fourth drive circuit 1113, and the word line WL is connected to a fourth drive circuit 1114. In this example, a first driver circuit 1111, a second driver circuit 1112, a third driver circuit The fourth driver circuit 1113 and the fourth driver circuit 1114 are provided independently. The present invention is not limited to this. A decoder having one or more of the above functions may be used. stomach.

[0252] Next, the write operation of the semiconductor device shown in FIG. 19 will be described with reference to the timing chart shown in FIG. The write and read operations will now be described.

[0253] For simplicity, the operation of a 2-row x 2-column semiconductor device will be described here. The disclosed invention is not limited thereto.

[0254] 20 is a diagram for explaining the operation of the semiconductor device shown in FIG. 19. In FIG. S1(1) and S1(2) are the potentials of the first signal line S1, S2(1) and S 2(2) is the potential of the second signal line S2, BL(1) and BL(2) are the potentials of the second signal line S2, The potentials of the bit lines BL, WL(1) and WL(2), are the potential of the word line WL, SL(1 ) and SL(2) correspond to the potentials of the source line SL, respectively.

[0255] First, write to memory cell (1,1) and memory cell (1,2) in the first row, When reading from the first memory cell (1,1) and the second memory cell (1,2), In the following, the data to be written to the memory cell (1,1) is assumed to be "1". A case where the data to be written to the memory cell (1,2) is "0" will be described.

[0256] First, the write operation will be described. In the first row write period, the second signal of the first row is A potential VH is applied to the line S2(1) to turn on the second transistor 162 in the first row. In addition, 0V is applied to the second signal line S2(2) in the second row, and the second transistor 1 62 is turned off.

[0257] Next, a potential V2 is applied to the first signal line S1(1) in the first column, and a potential V3 is applied to the first signal line S1(2) in the second column. Apply a potential of 0V.

[0258] As a result, the potential V2 is applied to the floating gate portion FG of the memory cell (1,1), The floating gate portion FG of the cell (1,2) is given 0V. Here, the potential V The potential of the second transistor is higher than the threshold voltage of the first transistor 160. The potential of the second signal line S2(1) in the first row is set to 0 V, and the second transistor 162 in the first row is turned off. By setting the write state to "ON", the writing is terminated.

[0259] The word lines WL(1) and WL(2) are set to 0V. The first signal line in the first column Before changing the potential of S1(1), the second signal line S2(1) in the first row is set to 0V. After the write operation, the terminal connected to the word line WL is the control gate electrode, and the first transistor 160 is the the source electrode of the first transistor 161 as a source electrode, the drain electrode of the second transistor 162 as a drain electrode, The threshold value of the memory element is Vw0 for data "0" and Vw1 for data "1". Here, the threshold voltage of the memory cell is Vw1. The voltage at the terminal connected to the word line WL changes the resistance between the drain electrode and the drain electrode. In addition, Vw0>0>Vw1.

[0260] Next, the read operation will be described. During the read operation of the first row, the word line W 0V is applied to L(1), and a potential VL is applied to the word line WL(2) of the second row. If WL(1) is set to 0V, the data in the first row will The first transistor 160 of the memory cell (1,2) in which the data "0" is stored is in the off state. The first transistor 160 of the memory cell (1,1) in which data "1" is stored is turned on. If WL(2) is at potential VL, then data "0" and "1" are written to the second row. Regardless of which of the two memory cells holds the first transistor 160, the first transistor 160 is in an off state. It becomes.

[0261] Next, a potential of 0 V is applied to the source line SL(1) in the first column and the source line SL(2) in the second column.

[0262] As a result, the first potential of the memory cell (1,1) is applied between the bit line BL(1) and the source line SL(1). Since the transistor is on, the resistance is low, and the bit line BL(2)-source line SL( During the period 2), the first transistor 160 of the memory cell (1, 2) is in an off state, and therefore the resistance is high. The read circuit connected to the bit line BL(1) and the bit line BL(2) The data can be read from the difference in resistance of the lines.

[0263] In addition, 0V is applied to the second signal line S2(1), and a potential VL is applied to the second signal line S2(2). , all the second transistors 162 are kept in an off state. Since the potential of the part FG is 0V or V2, by setting the second signal line S2(1) to 0V, All the second transistors 162 in the first row can be turned off. When a potential VL is applied to the word line WL(2), the potential of the floating gate portion FG becomes The potential becomes lower than the potential immediately after writing. In order to prevent the word line WL(2) from being turned on, the second signal line S2(2) is connected to the word line WL(2 As a result, all of the second transistors 162 are turned off. This can be done.

[0264] Next, the output potential when the circuit shown in FIG. 21 is used as the read circuit will be described. Since the resistance between the bit line BL(1) and the source line SL(1) is low, A low potential is input to the bit line BL(2) and the output D(1) is high. Since the resistance between the lines SL(2) is high, a high potential is input to the clocked inverter, and the output D(2) will be Low.

[0265] The operating voltages are, for example, VDD=2V, V2=1.5V, VH=2V, and VL=-2V. It is possible.

[0266] As described above, by providing a plurality of memory cells, a semiconductor device The memory capacity can be increased. The number and arrangement of memory cells, the number and arrangement of wiring, The number and arrangement of the operating circuits can be appropriately designed, and are not limited to the above configuration. isn't it.

[0267] As described above, the configurations, methods, etc. described in this embodiment may be used in conjunction with the configurations, methods, etc. described in other embodiments. They can be used in any suitable combination.

[0268] (Embodiment 4) In this embodiment, an embodiment of the disclosed invention different from that in the first and second embodiments is described. The structure of the semiconductor device and a manufacturing method thereof will be described with reference to FIGS. The transistor 260 described in this embodiment is the same as that described in the previous embodiment. As the transistor 160 in the circuit diagram, the transistor 262 is the same as that in the previous embodiment. In the circuit diagram, the transistor 162 is replaced with a capacitor 264 as in the previous embodiment. It can be used as the capacitive element 164 in the circuit diagram.

[0269] <Cross-sectional and planar configurations of semiconductor device> FIG. 22 shows an example of the configuration of the semiconductor device. FIG. 22(A) shows a cross section of the semiconductor device. 22(A) and 22(B) show a plan view of the semiconductor device. 22(B) along the lines C1-C2 and D1-D2. In the figure, in order to avoid complication, the source electrode or drain electrode 254, Some of the components, such as the wiring 256, are omitted. The semiconductor device to be described has a transistor 260 using a semiconductor material other than an oxide semiconductor in a lower portion. and a transistor 262 using an oxide semiconductor in the upper portion. Transistors using semiconductor materials other than conductors can easily operate at high speeds. A transistor using a semiconductor is capable of holding charge for a long period of time due to its characteristics.

[0270] It should be noted that the above transistors are all n-channel transistors. However, it goes without saying that a p-channel transistor can be used. The technical essence of the present invention is to use an oxide semiconductor as the transistor 262 to store data. Since the purpose is to use the semiconductor device, it is not necessary to limit the specific configuration of the semiconductor device to that shown here. .

[0271] In the semiconductor device shown in FIG. 22, a transistor 262 and a capacitance element 264 are The planar layout shown in FIG. For example, if the minimum processing dimension is F, then Moricell's area is 15F 2 ~25F 2 It is possible to make the following:

[0272] One of the differences between the semiconductor device shown in FIG. 22 and the semiconductor device shown in the previous embodiment is that The presence or absence of a sidewall insulating layer in the transistor 260. The semiconductor device does not have a sidewall insulating layer. As a result, the impurity region 114 (see, for example, FIG. 2) is not formed. As shown in the figure, when the sidewall insulating layer is not provided, the In addition, compared to the case where a sidewall insulating layer is provided, the fabrication is quicker. The process can be simplified.

[0273] Another difference between the semiconductor device shown in FIG. 22 and the semiconductor device shown in the previous embodiment is that , which are the interlayer insulating layers in the transistor 260. That is, the semiconductor device shown in FIG. In this example, the hydrogen-containing interlayer insulating layer 225 contacts the metal compound region 224 of the transistor 260. By providing the interlayer insulating layer 225 containing hydrogen in contact with the metal compound region 224, Hydrogen is supplied to the transistor 260 to improve the characteristics of the transistor 260. Such an interlayer insulating layer 225 can be formed by, for example, a plasma CVD method. Further, the interlayer insulating layer 226 may include a silicon nitride layer containing hydrogen. The use of a low-concentration insulating layer may deteriorate the characteristics of the transistor 262. It is possible to prevent hydrogen from entering the transistor 262. 226 is, for example, silicon nitride formed by sputtering in the absence of hydrogen. By adopting such a configuration, the transistor 260 and the transistor In addition, in FIG. 22, the substrate 200 is The element isolation insulating layer 206 is formed on the substrate 100 of the first embodiment. 06, the gate insulating layer 208 is the gate insulating layer 108 of the first embodiment, and the gate electrode 210 The gate electrode 110 of the first embodiment corresponds to the channel forming region 216 of the first embodiment. In the hole formation region 116, the high concentration impurity region 220 is the high concentration impurity region 120 of the first embodiment. The metal compound region 224 corresponds to the metal compound region 124 of the first embodiment. .

[0274] Another difference between the semiconductor device shown in FIG. 22 and the semiconductor device shown in the previous embodiment is that In the transistor 262, the insulating layer 243a and the insulating layer 243b are oxide semiconductor layers. Between the oxide semiconductor layer 244 and the source or drain electrode 242a, and between the oxide semiconductor layer 244 and the The point is provided between the source electrode or the drain electrode 242b. By providing the layer 243a and the insulating layer 243b, the gate electrode 248a and the source A source or drain electrode 242a (or a gate electrode 248a) and a source or drain electrode The gate capacitance formed by the gate electrode 242b is reduced, and the operation of the transistor 262 is The speed can be improved.

[0275] As in the first embodiment, the lower transistor 260 and the upper transistor 262 are The source electrode or drain electrode 242a is formed directly on the gate electrode 210. This configuration is more efficient than when electrodes and wiring are provided separately. In comparison, the integration density is improved and the manufacturing process is simplified.

[0276] In this embodiment, a configuration having the above-mentioned differences is shown. A configuration having only one of the above may be adopted.

[0277] <Method for Manufacturing Semiconductor Device> Next, an example of a method for manufacturing the above semiconductor device will be described. The process after forming the capacitor 260 and the method of manufacturing the upper transistor 262 are shown in FIG. 24. The lower transistor 260 is the same as that shown in the first embodiment. The method for producing the same can be used as that described above. For details, see the description of the first embodiment. Note that in this embodiment, a capacitor 264 is provided. In this embodiment, an interlayer insulating layer 225 and an interlayer insulating film 226 are formed to cover the transistor 260. Three types of interlayer insulating layers are formed: layer 226, interlayer insulating layer 228, and the like. In the embodiment, in the manufacturing process of the transistor 260, The source or drain electrode 130a and the source or drain electrode 130b are not formed. However, the source electrode or drain electrode 130a and the source electrode or drain electrode 130 For convenience, the transistor will be called transistor 260 even if "b" is not formed.

[0278] First, the lower transistor 260 is formed by the method shown in the first embodiment, and then the transistor The upper part of the gate electrode 210 of 260 is removed. The removal process includes a chemical mechanical polishing (CMP) process. By this, the upper surface of the gate electrode 210 may be polished by a polishing process such as a static mechanical polishing process. The upper interlayer insulating layers 225, 226, and 228 are removed. By sufficiently flattening the surface by the polishing process, it is possible to obtain good electrodes and wiring in the subsequent process. It is possible to form lines, insulating layers, semiconducting layers, etc.

[0279] Next, on the gate electrode 210, the interlayer insulating layer 225, the interlayer insulating layer 226, and the interlayer insulating layer 228, A conductive layer is formed, and the conductive layer is selectively etched to form a source electrode or a drain electrode. 242a and a source or drain electrode 242b are formed (see FIG. 23(A)). Here, the source electrode or drain electrode 242a is directly connected to the gate electrode 210. It is formed like this.

[0280] Forming a source or drain electrode 242a and a source or drain electrode 242b The conductive layer for this purpose is the source or drain electrode 142a, The source electrode or drain electrode 142b may be formed using a material similar to that of the source electrode or drain electrode 142b. The conductive layer is also etched in the same manner as in the first embodiment. For details, the description in embodiment 1 can be referred to.

[0281] Next, the source or drain electrode 242a, the source or drain electrode 242b and forming an insulating layer to cover the source electrode or the An insulating layer 243a is formed on the drain electrode 242a, and a source or drain electrode 242b is formed on the drain electrode 242b. Then, an insulating layer 243b is formed on each of the first and second electrodes 243a and 243b (see FIG. 23B).

[0282] By providing the insulating layers 243a and 243b, the gate electrode 2 48a, a source electrode or drain electrode 242a, and a source electrode or drain It is possible to reduce the parasitic capacitance between the electrode 242b.

[0283] Next, the source or drain electrode 242a, the source or drain electrode 242b An oxide semiconductor layer 244 is formed to cover the gate insulating layer 2 46 is formed (see FIG. 23(C)).

[0284] The oxide semiconductor layer 244 can be formed using the material and the method for the oxide semiconductor layer 140 described in Embodiment 1. In addition, the oxide semiconductor layer 244 can be formed by performing heat treatment (first heat treatment For details, please refer to the description of the first embodiment. do.

[0285] The gate insulating layer 246 is formed by the material and method of the gate insulating layer 138 shown in the first embodiment. After the gate insulating layer 246 is formed, the insulating layer 246 can be formed in an inert gas atmosphere or It is preferable to perform the heat treatment in an oxygen atmosphere (second heat treatment). The description of form 1 may be taken into consideration.

[0286] Next, a region to be a channel formation region of the transistor 262 is formed on the gate insulating layer 246. A gate electrode 248a is formed in a region overlapping the source electrode or drain electrode 242. An electrode 248b is formed in a region overlapping with a (see FIG. 23(D)).

[0287] The gate electrode 248a and the electrode 248b are formed after forming a conductive layer on the gate insulating layer 246. The gate electrode can be formed by selectively etching the conductive layer. The conductive layer that becomes the electrode 248a and the electrode 248b can be formed by a PVD method such as a sputtering method, The source electrode can be formed by using a CVD method such as a plasma CVD method. or the drain electrode 242a, etc., and the descriptions therefor can be taken into consideration.

[0288] Next, an interlayer insulating layer is formed on the gate insulating layer 246, the gate electrode 248a, and the electrode 248b. 250 and an interlayer insulating layer 252 are formed (see FIG. 24(A)). The protective insulating layer 144 and the interlayer insulating layer 252 are the same as the protective insulating layer 144 and the interlayer insulating layer 146 shown in the first embodiment. For details, the description of Embodiment 1 can be referred to. It is possible.

[0289] It is preferable that the interlayer insulating layer 252 is formed so that its surface is flat. By forming the interlayer insulating layer 252 so as to have a flat surface, when the semiconductor device is miniaturized, Even in such a case, electrodes, wiring, and the like can be suitably formed on the interlayer insulating layer 252. The interlayer insulating layer 252 is planarized by a method such as CMP (chemical mechanical polishing). This can be done using the method.

[0290] Next, the interlayer insulating layer 225, the interlayer insulating layer 226, the interlayer insulating layer 228, and the oxide semiconductor layer 244 are , the gate insulating layer 246, the interlayer insulating layer 250, and the interlayer insulating layer 252 are selectively etched. 2, an opening is formed down to the metal compound region 224 of the transistor 260 (FIG. 24(B) ) For etching, either dry etching or wet etching can be used. However, from the viewpoint of miniaturization, it is preferable to use dry etching.

[0291] Then, a source electrode or drain electrode 254 is formed so as to be embedded in the opening. Then, a wiring 256 that is connected to the source electrode or drain electrode 254 is formed (FIG. 24 (See (C)).

[0292] The source electrode or drain electrode 254 is formed, for example, by a PVD method or a CVD method in the region including the opening. After forming a conductive layer using a method such as etching or CMP, The conductive layer can be formed by removing a part of the conductive layer. A thin titanium film is formed on the area including the mouth by the PVD method, and a thin titanium nitride film is formed on the area by the CVD method. A method of forming a tungsten film so as to fill the opening after forming a tungsten film in the opening can be applied. Here, the titanium film formed by the PVD method is a film that does not adhere to the oxide film (natural oxide film) on the surface on which it is formed. etc.) to reduce the contact resistance with the lower electrode etc. (here, the metal compound region 224). In addition, the titanium nitride film formed afterwards suppresses the diffusion of the conductive material. In addition, after forming a barrier film made of titanium or titanium nitride, A copper film may be formed on the conductive layer by plating.

[0293] The wiring 256 is formed after forming a conductive layer in contact with the source electrode or drain electrode 254. The conductive layer can be formed by selectively etching the conductive layer. It is formed using PVD methods such as sputtering and CVD methods such as plasma CVD. The details are the same as those of the source electrode or drain electrode 242a. do.

[0294] As a result of the above, a semiconductor device including the transistor 260, the transistor 262, and the capacitor element 264 is The conductor device is completed.

[0295] In the semiconductor device described in this embodiment, a transistor 262 and a capacitor 264 are The transistor 260 has a sidewall insulation. The gate electrode 210 does not have an insulating layer, and the source electrode or drain electrode 242a is directly formed on the gate electrode 210. High integration is possible due to the fact that the semiconductor device is formed in a contact-type semiconductor device. In addition, the manufacturing process is simplified. It has been done.

[0296] In addition, in the semiconductor device described in this embodiment, an insulating layer containing hydrogen is used as the interlayer insulating layer 225. By applying an insulating layer having a low hydrogen concentration as the interlayer insulating layer 226, The characteristics of the capacitor 260 and the transistor 262 are improved. By providing the insulating layer 243b, the so-called gate capacitance is reduced, and the transistor 262 The operating speed has been improved.

[0297] The above-mentioned features of the present embodiment provide a semiconductor device with extremely excellent characteristics. is possible.

[0298] As described above, the configurations, methods, etc. described in this embodiment may be used in conjunction with the configurations, methods, etc. described in other embodiments. They can be used in any suitable combination.

[0299] (Embodiment 5) In this embodiment, an example of an electronic device equipped with the semiconductor device obtained in the above embodiment will be described. The semiconductor device obtained in the above embodiment does not require power supply. In addition, the data can be retained even if the data is written or erased. Furthermore, the operation is also fast. Therefore, the semiconductor device can be used to realize a new configuration of a power supply. It is possible to provide a child device. The semiconductor device is then mounted on a circuit board or the like and installed inside each electronic device.

[0300] FIG. 10A shows a notebook personal computer including the semiconductor device according to the above embodiment. The computer is composed of a main body 301, a housing 302, a display unit 303, a keyboard 304, etc. It has been made.

[0301] FIG. 10B shows a personal digital assistant (PDA) including the semiconductor device according to the above embodiment. The main body 311 includes a display unit 313, an external interface 315, and operation buttons 314. Also, a stylus 312 is provided as an accessory for operation.

[0302] FIG. 10C shows an example of electronic paper including the semiconductor device according to the above embodiment. The electronic book 320 is shown. The electronic book 320 is made up of two housings, a housing 321 and a housing 323. The housing 321 and the housing 323 are integrated with each other by a shaft portion 337. The opening and closing operation can be performed around the axis 337. The book 320 can be used like a paper book.

[0303] A display unit 325 is incorporated in the housing 321, and a display unit 327 is incorporated in the housing 323. The display unit 325 and the display unit 327 may be configured to display a continuous screen, or may be configured to display different images. By configuring to display different screens, for example, A text is displayed on the right display unit (display unit 325 in FIG. 10C) and a text is displayed on the left display unit ( In (C), an image can be displayed on the display unit 327).

[0304] FIG. 10C shows an example in which an operation unit and the like are provided on the housing 321. The body 321 includes a power source 331, operation keys 333, a speaker 335, etc. The page can be turned by pressing the arrow 333. In addition, a keyboard and a pointer are installed on the same surface as the display unit of the housing. The housing may be provided with an external display device or the like. Connection terminals (earphone terminal, USB terminal, AC adapter and USB cable, etc.) A configuration including a terminal that can be connected to various cables, a recording medium insertion portion, etc. Furthermore, the electronic book 320 may be configured to have the functionality of an electronic dictionary.

[0305] The electronic book 320 may be configured to transmit and receive information wirelessly. It is also possible to purchase and download desired book data from the child book server. It is possible.

[0306] Electronic paper can be applied to any field that displays information. For example, in addition to e-books, posters, in-car advertisements on trains and other vehicles, credit cards, etc. The present invention can be applied to displays on various cards such as gift cards.

[0307] FIG. 10D illustrates a mobile phone including the semiconductor device according to the above embodiment. The phone is made up of two housings, housing 340 and housing 341. Housing 341 has a front display panel 342, speaker 343, microphone 344, pointing device 3 46, a camera lens 347, and an external connection terminal 348. The mobile phone includes a solar cell 349 for charging the mobile phone, an external memory slot 350, etc. The antenna is also built into the housing 341.

[0308] The display panel 342 has a touch panel function, and in FIG. The mobile phone has a solar cell 34 A boost circuit is implemented to boost the voltage output by 9 to the voltage required by each circuit. In addition to the above configuration, the device may be configured to incorporate a non-contact IC chip, a small recording device, etc. It is also possible.

[0309] The display direction of the display panel 342 changes appropriately depending on the usage mode. A camera lens 347 is provided on the same surface as the camera 42, making video calling possible. The speaker 343 and microphone 344 are not limited to voice calls, but also video calls, recording, playback, etc. Furthermore, the housing 340 and the housing 341 can be slid, and as shown in FIG. It can be folded from the unfolded state to the overlapping state, making it compact and suitable for carrying. It is Noh.

[0310] The external connection terminal 348 can be connected to various cables such as an AC adapter or a USB cable. The external memory slot 350 can store a recording medium. It can store and move larger amounts of data. In addition to the above features, It may also be equipped with an infrared communication function, a television receiving function, etc.

[0311] FIG. 10E shows a digital camera including the semiconductor device according to the above embodiment. The digital camera is comprised of a main body 361, a display unit (A) 367, an eyepiece 363, and an operation switch 364. , a display unit (B) 365, a battery 366, etc.

[0312] FIG. 10F illustrates a television set including the semiconductor device according to the above embodiment. In the vision device 370, a display unit 373 is built into a housing 371. In this case, the stand 375 is used to hold the case in place. This shows the configuration that supported 371.

[0313] The television device 370 can be operated using an operation switch provided on the housing 371 or a separate remote control. This can be done by the operation device 380. The remote control operation device 380 has an operation key 379. This allows you to control the channel and volume, and to operate the image displayed on the display unit 373. In addition, the remote control operation device 380 can receive the output from the remote control operation device 380. A display unit 377 for displaying the information to be displayed may be provided.

[0314] It is preferable that the television device 370 is configured to include a receiver, a modem, etc. The receiver can receive general television broadcasts. By connecting to a wired or wireless communication network, The communication of information between a single person (e.g., a sender and a receiver, or between receivers themselves) or between two people (e.g., a sender and a receiver, or a receiver and another receiver) It is possible.

[0315] The structures, methods, and the like described in this embodiment may be combined as appropriate with the structures, methods, and the like described in other embodiments. Can be used in combination EXAMPLES

[0316] In this example, the off-state current of a transistor including a highly purified oxide semiconductor was measured. The results will be explained.

[0317] First, the off-state current of a transistor using a highly purified oxide semiconductor is sufficiently small. Considering this, we prepared a transistor with a sufficiently large channel width W of 1 m and measured the off-state current. The off-current of a transistor with a channel width W of 1 m was measured. In FIG. 25, the horizontal axis represents the gate voltage VG, and the vertical axis represents the drain current ID. When the voltage VD is +1V or +10V, the gate voltage VG is in the range of -5V to -20V. The off-current of the thin-film transistor is 1×10, which is the detection limit. -13 It is found that the In addition, the off-state current of the transistor (here, the current per unit channel width (1 μm)) value) is 1aA / μm (1×10 -18 It was found that the maximum capacitance was less than 1.5 A / μm.

[0318] Next, we aimed to measure the off-state current of a thin-film transistor using a highly purified oxide semiconductor more accurately. The results are described below. The off-state current of the transistor is 1×10 -13 It is found that the Therefore, we fabricated a device for characteristic evaluation to obtain a more accurate off-state current value ( The results of the determination of the concentration of 100 ppm or less (values ​​below the detection limit of the measuring instrument) are explained below.

[0319] First, the characteristic evaluation element used in the current measurement method will be described with reference to FIG.

[0320] The characteristic evaluation element shown in FIG. 26 has three measurement systems 800 connected in parallel. 0 is a capacitor element 802, a transistor 804, a transistor 805, and a transistor 806 , and a transistor 808. A transistor including a highly purified oxide semiconductor was used for the capacitor 806.

[0321] In the measurement system 800, one of the source terminal and the drain terminal of a transistor 804, One of the terminals of the capacitor 802 and the source and drain terminals of the transistor 805 One side is connected to a power supply (the power supply that provides V2). the other of the source and drain terminals of the transistor 808 One of the terminals of the capacitor 802, the other terminal of the capacitor 802, and the gate terminal of the transistor 805 are connected to each other. The other of the source terminal and the drain terminal of the transistor 808 is connected to One of the source terminal and the drain terminal of the transistor 806 and the gate of the transistor 806 The output terminal of the transistor 805 is connected to a power supply (the power supply that provides V1). the other of the source and drain terminals of the transistor 806 The other terminal is connected and serves as an output terminal.

[0322] The gate terminal of the transistor 804 is connected to a resistor R1, R2, and R3. A potential Vext_b2 for controlling the state of the transistor 808 is supplied to the gate terminal of the transistor 808. A potential Vext_b1 is supplied to control the on and off states of the transistor 808. Moreover, the potential Vout is output from the output terminal.

[0323] Next, a current measuring method using the above-mentioned characteristic evaluation element will be described.

[0324] First, an outline of the initial period during which a potential difference is applied to measure the off-state current will be described. During the period, a gate terminal of the transistor 808 is connected to the transistor 808 to turn the transistor 808 on. A potential Vext_b1 is input to the source terminal or drain terminal of the transistor 804. A node connected to the other of the terminals (i.e., the source terminal and drain terminal of the transistor 808) One of the terminals of the capacitor 802 and the gate terminal of the transistor 805 A potential V1 is applied to node A, which is a node connected to the The transistor 804 is kept in an off state.

[0325] Then, a potential that turns off the transistor 808 is applied to the gate terminal of the transistor 808. Vext_b1 is input to turn off the transistor 808. After turning off the transistor 804, the potential V1 is set to a low potential. The potential V2 is set to the same potential as the potential V1. When the initial period ends, the node A and the source terminal of the transistor 804 and A potential difference is generated between the drain terminal of the transistor 808 and the node A. Since a potential difference occurs between the other of the source terminal and the drain terminal, A small amount of charge flows through the transistor 804 and the transistor 808. In other words, an off-current occurs. .

[0326] Next, an outline of the measurement period of the off-state current will be described. The potential of one of the source terminal or drain terminal of 804 (i.e., V2) and The potential of the other terminal of the source terminal or the drain terminal of the transistor 808 (i.e., V1) is During the measurement period, the potential of the node A is not fixed (flow This causes a charge to flow through the transistor 804, and over time The amount of charge held at node A fluctuates. In other words, the output potential Vout of the output terminal also changes. .

[0327] Details of the relationship between the potentials during the initial period in which the potential difference is applied and the subsequent measurement period The timing chart is shown in FIG.

[0328] In the initial period, first, the potential Vext_b2 is applied when the transistor 804 is turned on. This makes the potential of node A V2, that is, the low potential (V After that, the potential Vext_b2 is set to a value so that the transistor 804 is turned off. Then, the transistor 804 is turned off by setting the potential at a low level. Vext_b1 is set to a potential (high potential) that turns on the transistor 808. This causes the potential of node A to become V1, i.e., the high potential (VDD). xt_b1 is set to a potential at which the transistor 808 is turned off. Node A goes into a floating state and the initial period ends.

[0329] In the subsequent measurement period, electric charges flow into node A at potentials V1 and V2. Or, the potential is set so that charge flows out from node A. Here, the potential V1 and the potential V 2 is the low potential (VSS). However, at the timing when the output potential Vout is measured In this case, it is necessary to operate the output circuit, so V1 is temporarily set to a high potential (VDD). Note that the period when V1 is at a high potential (VDD) should be short enough so as not to affect the measurement. The period.

[0330] When a potential difference is applied as described above and the measurement period starts, the voltage at node A increases over time. The amount of charge held by the transistor fluctuates, and the potential at node A fluctuates accordingly. This means that the potential of the gate terminal of the transistor 805 fluctuates over time. The potential of the output potential Vout of the terminal also changes.

[0331] A method for calculating the off-state current from the obtained output potential Vout will be described below.

[0332] Before calculating the off-state current, the potential V A and the output potential Vout. This causes the output potential Vout to change to the potential V A You can ask for the above. From the above relationship, the potential of node A, V A is expressed as a function of the output potential Vout as follows: It is possible.

[0333]

number

[0334] Also, the charge Q at node A A is the potential V of node A. A , capacitance C connected to node A A , fixed Using the constant (const), it is expressed as follows: CA is the sum of the capacitance of the capacitive element 802 and other capacitances.

[0335]

number

[0336] Current I at node A A is the charge flowing into (or out of) node A. Since it is a time derivative, the current I A is expressed as follows:

[0337]

number

[0338] In this way, the capacitance C connected to node A A The output potential Vout of the output terminal is Current I A can be sought.

[0339] By using the method described above, the leakage current flowing between the source and drain of the transistor in the off state is The off-state current (off-state current) can be measured.

[0340] In this embodiment, a highly purified oxide having a channel length L of 10 μm and a channel width W of 50 μm is used. Using semiconductors, a transistor 804, a transistor 805, a transistor 806, In each of the parallel measurement systems 800, a capacitance element 802a The capacitance values ​​of the capacitive elements 802a to 802c are set to 100 fF, and the capacitance values ​​of the capacitive elements 802b to 1 and the capacitance element 802c is set to 3 pF.

[0341] In the measurement according to this embodiment, VDD=5V and VSS=0V. In this test, the potential V1 is set to VSS as a rule, and the potential is increased by 100 msec every 10 to 300 sec. Vout was measured as VDD for the period c. The time Δt was set to approximately 30,000 sec.

[0342] FIG. 28 shows the relationship between the elapsed time Time in the current measurement and the output potential Vout. From FIG. 28, it can be seen that the potential changes over time.

[0343] FIG. 29 shows the off-state current at room temperature (25° C.) calculated from the above current measurement. FIG. 29 shows the relationship between the source-drain voltage V and the off-current I. 29, when the source-drain voltage is 4 V, the off-current is about 40 zA / μm. In addition, under the condition of a source-drain voltage of 3.1 V, the off-current It was found that the current density was 10zA / μm or less. Note that 1zA is 10 -21 Represents A.

[0344] Furthermore, the off-state current calculated from the above current measurement in a temperature environment of 85°C is FIG. 30 shows the relationship between the source-drain voltage V and the off-state current V under a temperature environment of 85° C. The relationship between the current I and the source-drain voltage is 3.1 V. It was found that the off-state current was 100 zA / μm or less.

[0345] As described above, in the transistor including a highly purified oxide semiconductor, It was confirmed that the flow was sufficiently small. EXAMPLES

[0346] The number of times that the semiconductor device according to one embodiment of the disclosed invention can be rewritten was investigated. The survey results will now be explained with reference to FIG.

[0347] The semiconductor device used in the investigation has a circuit configuration shown in FIG. An oxide semiconductor is used for a transistor corresponding to the transistor 162, and a capacitor 164 is used for the transistor 162. The corresponding capacitance element had a capacitance of 0.33 pF.

[0348] The investigation involves setting the initial memory window width and repeating the holding and writing of information a set number of times. The memory window width after the data is returned is compared with the memory window width after the data is returned. The write is performed by applying either 0V or 5V to the wiring corresponding to the third wiring in FIG. Either of these two wires should be applied, and either 0V or 5V should be applied to the wire corresponding to the fourth wire. When the potential of the wiring corresponding to the fourth wiring is 0 V, the transistor 162 The corresponding transistor (write transistor) is in the off state, so The applied potential is maintained. If the potential of the wiring corresponding to the fourth wiring is 5V, Since the transistor corresponding to the transistor 162 is in the on state, the wiring corresponding to the third wiring The line potential is applied to node FG.

[0349] The memory window width is one of the indices that indicate the characteristics of a memory device. The potential Vcg of the wiring corresponding to the fifth wiring and the potential Vcg of the wiring corresponding to the transistor 160 during the memory state The curve ( The difference between the Vcg and Id curves is called the shift amount ΔVcg. The state where 0V is applied to node FG (hereafter referred to as the low state) and the state where 5V is applied to node FG are In other words, the memory window width is the Lo This can be confirmed by sweeping the potential Vcg in the w state and the high state.

[0350] Figure 31 shows the memory window width in the initial state and the 1×10 9 After writing The results of the investigation of the memory window width are shown in Fig. 31. In Fig. 31, the horizontal axis is Vcg (V). The vertical axis indicates Id(A). From FIG. 9 Before and after writing, It can be seen that the memory window width has not changed. 9 Before and after writing The fact that the memory window width does not change during this period means that the semiconductor device This indicates that there is no deterioration.

[0351] As described above, the semiconductor device according to one embodiment of the disclosed invention performs storage and writing in a 1×1 0 9 Even if it is repeatedly written many times, the characteristics do not change, and it has extremely high rewrite resistance. According to one embodiment of the present invention, a highly reliable semiconductor device can be realized. [Explanation of symbols]

[0352] 100 Substrates 102 Protective layer 104 Semiconductor area 106 Element isolation insulating layer 108 Gate Insulation Layer 110 Gate electrode 112 Insulating layer 114 Impurity region 116 Channel formation region 118 Sidewall insulating layer 120 High concentration impurity region 122 Metal layer 124 Metal compound area 126 Interlayer Insulation Layer 128 Interlayer Insulation Layer 130a source electrode or drain electrode 130b Source electrode or drain electrode 130c electrode 132 Insulating Layer 134 Conductive Layer 136a electrode 136b Electrode 136c electrode 136d Gate electrode 138 Gate Insulation Layer 140 Oxide semiconductor layer 142a Source electrode or drain electrode 142b Source or drain electrode 144 Protective Insulation Layer 146 Interlayer Insulation Layer 148 Conductive Layer 150a electrode 150b electrode 150c electrode 150d electrode 150e electrode 152 Insulating layer 154a electrode 154b electrode 154c electrode 154d electrode 160 Transistors 162 Transistor 164 Capacitive element 200 boards 206 Element isolation insulating layer 208 Gate Insulation Layer 210 Gate electrode 216 Channel formation region 220 High concentration impurity region 224 Metal compound area 225 Interlayer Insulation Layer 226 Interlayer Insulation Layer 228 Interlayer Insulation Layer 242a Source or drain electrode 242b Source or drain electrode 243a Insulating layer 243b Insulating layer 244 Oxide semiconductor layer 246 Gate Insulation Layer 248a Gate electrode 248b Electrode 250 Interlayer Insulation Layer 252 Interlayer insulation layer 254 Source or drain electrode 256 Wiring 260 Transistors 262 Transistor 264 Capacitive element 301 Main unit 302 Case 303 Display section 304 Keyboard 311 Main unit 312 Stylus 313 Display section 314 Operation button 315 External Interface 320 e-books 321 Case 323 Case 325 Display section 327 Display section 331 Power supply 333 Operation Key 335 Speaker 337 Shaft 340 Case 341 Case 342 Display Panel 343 Speakers 344 Microphone 345 Operation Key 346 Pointing Device 347 Camera Lenses 348 External connection terminal 349 Solar Cells 350 external memory slot 361 Main unit 363 Eyepiece 364 Operation Switch 365 Display section (B) 366 Battery 367 Display section (A) 370 Television Equipment 371 Case 373 Display section 375 Stand 377 Display section 379 Operation Key 380 Remote Controlled Device 400 memory cells 800 Measurement System 802 Capacitive element 802a Capacitive element 802b Capacitive element 802c Capacitive Element 804 Transistor 805 Transistor 806 Transistor 808 Transistor 1100 memory cells 1111 Drive circuit 1112 Drive circuit 1113 Drive circuit 1114 Drive circuit 1200 memory cells 1211 Drive circuit 1212 Drive circuit 1213 Drive circuit 1214 Drive circuit

Claims

1. A first transistor and a second transistor are included. the first transistor has a channel formation region in an oxide semiconductor layer, the oxide semiconductor layer is disposed above a layer including silicon having a channel formation region of the second transistor, with an insulating layer being disposed above a gate electrode of the second transistor therebetween; a source electrode or a drain electrode of the first transistor disposed above the oxide semiconductor layer is electrically connected to a gate electrode of the second transistor; the oxide semiconductor layer does not overlap with a gate electrode of the second transistor in a plan view; Semiconductor device.

2. In claim 1, the oxide semiconductor layer has a hydrogen concentration of 5×10 19 atoms / cm 3 or less as measured by secondary ion mass spectrometry; The off-state current of the first transistor is 1×10 when the drain voltage is +1 V or +10 V and the gate voltage is in the range of −5 V to −20 V. －１３ A or lower, Semiconductor device.

3. A first transistor and a second transistor are included. the first transistor has a channel formation region in an oxide semiconductor layer, the oxide semiconductor layer is disposed above a layer including silicon having a channel formation region of the second transistor, with an insulating layer being disposed above a gate electrode of the second transistor therebetween; a source electrode or a drain electrode of the first transistor disposed above the oxide semiconductor layer is electrically connected to a gate electrode of the second transistor; the oxide semiconductor layer does not overlap with a gate electrode of the second transistor in a plan view; the oxide semiconductor layer has a hydrogen concentration of 5×10 19 atoms / cm 3 or less as measured by secondary ion mass spectrometry; the first transistor has an off-state current per unit channel width of 10 zA / μm or less at 25° C.; Semiconductor device.

4. In claim 3, the first transistor has an off-state current per unit channel width of 1 zA / μm or less at 25° C.; Semiconductor device.

5. A first transistor and a second transistor are included. the first transistor has a channel formation region in an oxide semiconductor layer, the oxide semiconductor layer is disposed above a layer including silicon having a channel formation region of the second transistor, with an insulating layer being disposed above a gate electrode of the second transistor therebetween; a source electrode or a drain electrode of the first transistor disposed above the oxide semiconductor layer is electrically connected to a gate electrode of the second transistor; the oxide semiconductor layer does not overlap with a gate electrode of the second transistor in a plan view; the oxide semiconductor layer has a hydrogen concentration of 5×10 19 atoms / cm 3 or less as measured by secondary ion mass spectrometry; the first transistor has an off-state current per unit channel width at 85° C. of 100 zA / μm or less; Semiconductor device.

6. In claim 5, the first transistor has an off-state current per unit channel width of 10 zA / μm or less at 85° C.; Semiconductor device.

7. A first transistor and a second transistor are included. a capacitance element electrically connected to a gate electrode of the second transistor is not provided; the first transistor has a channel formation region in an oxide semiconductor layer, the oxide semiconductor layer is disposed above a layer including silicon having a channel formation region of the second transistor, with an insulating layer being disposed above a gate electrode of the second transistor therebetween; a source electrode or a drain electrode of the first transistor disposed above the oxide semiconductor layer is electrically connected to a gate electrode of the second transistor; the oxide semiconductor layer does not overlap with a gate electrode of the second transistor in a plan view; Semiconductor device.

8. In claim 7, the oxide semiconductor layer has a hydrogen concentration of 5×10 19 atoms / cm 3 or less as measured by secondary ion mass spectrometry; The off-state current of the first transistor is 1×10 when the drain voltage is +1 V or +10 V and the gate voltage is in the range of −5 V to −20 V. －１３ A or lower, Semiconductor device.

9. In any one of claims 1 to 8, the oxide semiconductor layer is an In—Ga—Zn—O-based, In—Sn—Zn—O-based, In—Al—Zn—O-based, Sn—Ga—Zn—O-based, Al—Ga—Zn—O-based, Sn—Al—Zn—O-based, In—Zn—O-based, Sn—Zn—O-based, Al—Zn—O-based, In—O-based, Sn—O-based, or Zn—O-based; Semiconductor device.

10. A method for manufacturing a semiconductor device according to any one of claims 1 to 9, comprising the steps of: The oxide semiconductor layer is subjected to a heat treatment at 300° C. or more and 750° C. or less in a nitrogen atmosphere. A method for manufacturing a semiconductor device.

11. A method for manufacturing a semiconductor device according to any one of claims 1 to 9, comprising the steps of: The oxide semiconductor layer is formed by a sputtering method. A method for manufacturing a semiconductor device.

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