Avalanche Photodiode Array

Abstract

To provide an APD (avalanche photodiode) array capable of reducing a dead area by a simple configuration and of achieving detection of a desired electromagnetic wave or a particle beam.SOLUTION: In an APD array 1, a plurality of APDs 15 include a first semiconductor layer 21, a plurality of second semiconductor layers 22, and a multiplication layer 40. The first semiconductor layer 21 is provided at a second surface 12 side from a semiconductor region 20. The plurality of second semiconductor layers 22 are arranged along a first surface 11. The multiplication layer 40 is provided in the semiconductor region 20, between the plurality of second semiconductor layers 22 and the first semiconductor layer 21 in a direction orthogonal to the first surface 11. Each of a third semiconductor layer 23 and a fourth semiconductor layer 24 of the multiplication layer 40 are provided continuously so as to be overlapped with the plurality of second semiconductor layers 22 when seen from the direction orthogonal to the first surface 11. The third semiconductor layer 23 is provided at the first surface 11 side from the fourth semiconductor layer 24.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present invention relates to an avalanche photodiode array. [Background technology]

[0002] An avalanche photodiode array having a plurality of avalanche photodiodes is known (for example, see Patent Document 1). In the avalanche photodiode array described in Patent Document 1, a plurality of avalanche photodiodes are arranged on a semiconductor substrate. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Special Publication No. 2019-530215 Summary of the Invention [Problem to be solved by the invention]

[0004] In a photodetector using an avalanche photodiode array, there exists a dead area between adjacent avalanche photodiodes where light cannot be detected. The photodetector of Patent Document 1 is equipped with a microlens array, and is configured to refract light that would otherwise enter the dead area by the microlens and guide it to a detectable area. This can effectively expand the light receiving range.

[0005] However, in a configuration using a microlens array, the cost is high and the number of steps in the manufacturing process is large due to the microlens array. Therefore, in such a configuration, it is difficult to reduce the cost and the number of steps in the manufacturing process. Furthermore, in a configuration using a microlens array, it is not possible to expect a reduction effect of the dead area for electromagnetic waves and particle beams such as electron beams that pass through the microlens. For this reason, an avalanche photodiode array that can reduce the dead area and realize the detection of the desired electromagnetic waves or particle beams while having a simple configuration with fewer components such as a microlens array is expected.

[0006] An object of one aspect of the present invention is to provide an avalanche photodiode array that can reduce dead areas and achieve desired detection of electromagnetic waves or particle beams with a simple configuration. [Means for solving the problem]

[0007] An avalanche photodiode array according to one aspect of the present invention includes a semiconductor substrate. The semiconductor substrate has a first surface and a second surface opposed to each other. The semiconductor substrate includes a semiconductor region of a first conductivity type provided on the first surface side. The semiconductor substrate includes a plurality of avalanche photodiodes. The plurality of avalanche photodiodes are arranged along the first surface. The plurality of avalanche photodiodes include a first semiconductor layer of a first conductivity type, a plurality of second semiconductor layers of a second conductivity type, and a multiplication layer. The first semiconductor layer is provided on the second surface side of the semiconductor region. The plurality of second semiconductor layers are arranged along the first surface. Each of the second semiconductor layers is surrounded by the semiconductor region when viewed from a direction perpendicular to the first surface. The multiplication layer is provided within the semiconductor region and is provided between the plurality of second semiconductor layers and the first semiconductor layer in a direction perpendicular to the first surface. When viewed from a direction perpendicular to the first surface, the plurality of second semiconductor layers and the multiplication layer are provided within a range in which the first semiconductor layer is located. The multiplication layer includes a third semiconductor layer of a second conductivity type and a fourth semiconductor layer of the second conductivity type that face each other. The third semiconductor layer is provided closer to the first surface than the fourth semiconductor layer. Each of the third semiconductor layer and the fourth semiconductor layer is provided continuously so as to overlap a plurality of the second semiconductor layers when viewed from a direction perpendicular to the first surface.

[0008] In one aspect, the multiple avalanche photodiodes include a first semiconductor layer of a first conductivity type, multiple second semiconductor layers of a second conductivity type, and a multiplication layer. Each of the third and fourth semiconductor layers of the multiplication layer is continuously provided so as to overlap with the multiple second semiconductor layers when viewed from a direction perpendicular to the first surface. In this case, carriers generated by the incidence of the electromagnetic wave or particle beam to be detected are multiplied by the multiplication layer continuously provided so as to overlap with the multiple second semiconductor layers. The carriers multiplied in the multiplication layer are output from each second semiconductor layer. According to this configuration, the dead area can be reduced. Since the multiplication layer is provided separately from the multiple second semiconductor layers, the concentration of the electric field in each second semiconductor layer is suppressed. Therefore, edge breakdown is also suppressed in each second semiconductor layer. Therefore, in a simple configuration without a microlens array or the like, the dead area is reduced and the desired electromagnetic wave or particle beam can be detected. According to this configuration, the sensitivity layer can be configured relatively wide. Therefore, in particular, detection of the electromagnetic wave or particle beam requiring a relatively wide sensitivity layer can be realized.

[0009] In the above aspect, the impurity concentration of the first semiconductor layer and the impurity concentration of the fourth semiconductor layer may be higher than the impurity concentration of the semiconductor region. The impurity concentration of the first semiconductor layer may be higher than the impurity concentration of the fourth semiconductor layer. The impurity concentration of each of the second semiconductor layers may be higher than the impurity concentration of the third semiconductor layer.

[0010] In the above-mentioned embodiment, the shortest distance between the first semiconductor layer and the fourth semiconductor layer in the direction perpendicular to the first surface may be greater than the shortest distance between the second semiconductor layers and the third semiconductor layer. In this case, a relatively wide sensitivity layer is ensured between the first semiconductor layer and the fourth semiconductor layer. Therefore, the detection accuracy of the electromagnetic wave or particle beam that requires a relatively wide sensitivity layer can be improved.

[0011] In one of the above embodiments, the impurity concentration of the third semiconductor layer is higher than the impurity concentration of the fourth semiconductor layer. In this case, during operation, the electric field strength between the first semiconductor layer and the fourth semiconductor layer is higher than the electric field strength between the first surface and the third semiconductor layer. Therefore, the movement speed of the generated carriers between the first semiconductor layer and the fourth semiconductor layer is ensured, and high-speed response can be realized. Edge breakdown between the multiple second semiconductor layers and the multiplication layer can be further suppressed.

[0012] In one of the above embodiments, an arbitrary position from the first surface in a direction perpendicular to the first surface is defined as "x", the impurity concentration of the third semiconductor layer at the arbitrary position "x" is defined as "f(x)", the impurity concentration of the fourth semiconductor layer at the arbitrary position "x" is defined as "g(x)", and the thickness of the third semiconductor layer in the direction perpendicular to the first surface is defined as "L α " and the thickness of the fourth semiconductor layer in a direction perpendicular to the first surface is "L β ", the shortest distance between the first surface and the third semiconductor layer in a direction perpendicular to the first surface is "A", and the shortest distance between the first surface and the fourth semiconductor layer in a direction perpendicular to the first surface is "B", then formula (1) may be satisfied.

number

[0013] In one of the above embodiments, the semiconductor substrate may include a fifth semiconductor layer of a second conductivity type that surrounds the entire region in which the second semiconductor layers are arranged when viewed from a direction perpendicular to the first surface. When viewed from a direction perpendicular to the first surface, the third semiconductor layer and the fifth semiconductor layer may overlap each other at least in part. In this case, the variation in gain in each second semiconductor layer can be further reduced. Furthermore, the movement of carriers generated outside the detection range to the second semiconductor layer can be suppressed.

[0014] In one embodiment, the edge of each second semiconductor layer may be covered by a junction termination extension region when viewed from a direction perpendicular to the first surface. The junction termination extension region covering each second semiconductor layer may be a semiconductor region of a second conductivity type having an impurity concentration lower than the impurity concentration of the second semiconductor layer. In this case, edge breakdown in each second semiconductor layer may be further suppressed.

[0015] In the above embodiment, a portion of each of the second semiconductor layers facing the semiconductor region may be covered with a junction termination extension region, which can further suppress edge breakdown in each of the second semiconductor layers.

[0016] In one embodiment, the junction termination extension region covering each second semiconductor layer may be spaced apart from the multiplication layer, whereby the electric field strength between each second semiconductor layer and the multiplication layer may become more uniform.

[0017] In the above-mentioned one embodiment, when viewed from a direction perpendicular to the first surface, an edge of the fifth semiconductor layer may be covered by a junction termination extension region. The junction termination extension region covering the fifth semiconductor layer may be a semiconductor region of the second conductivity type having an impurity concentration lower than the impurity concentration of the fifth semiconductor layer. In this case, edge breakdown in the fifth semiconductor layer may be suppressed.

[0018] In one of the above embodiments, the semiconductor substrate may include a sixth semiconductor layer of the first conductivity type. The sixth semiconductor layer may be provided between adjacent second semiconductor layers among the plurality of second semiconductor layers when viewed from a direction perpendicular to the first surface. The impurity concentration of the sixth semiconductor layer may be higher than the impurity concentration of the semiconductor region. In this case, the movement of carriers between the adjacent second semiconductor layers may be suppressed.

[0019] In the above embodiment, the sixth semiconductor layer may have a thickness smaller than a thickness of each of the second semiconductor layers in a direction perpendicular to the first surface, whereby edge breakdown between the sixth semiconductor layer and the third semiconductor layer can be suppressed.

[0020] In the above embodiment, the semiconductor substrate may include silicon, and the second conductivity type may be N-type.

[0021] In the above embodiment, the semiconductor substrate may include indium phosphide, and the second conductivity type may be P-type.

[0022] In the above-mentioned embodiment, the multiplication layer may be provided within a range of 10 μm or less from the first surface in a direction perpendicular to the first surface. In this case, the multiplication layer has a structure that is relatively easy to form.

[0023] In the above embodiment, the width of each second semiconductor layer in the direction along the first surface may be greater than 10 μm. In this case, the size of each pixel that performs detection can be ensured.

[0024] In the above embodiment, when viewed from a direction perpendicular to the first surface, the multiplication layer may include a pair of edges facing each other. Three or more of the second semiconductor layers may be arranged in the opposing direction of the pair of edges. When viewed from a direction perpendicular to the first surface, the second semiconductor layers may be located between the pair of edges in the opposing direction. In this case, the variation in gain in each second semiconductor layer can be further suppressed.

[0025] In the above-mentioned embodiment, when viewed from a direction perpendicular to the first surface, the areas of the regions where the second semiconductor layers and the multiplication layer overlap each other may be equal to each other. In this case, the variation in gain in each second semiconductor layer can be further suppressed.

[0026] In the above-mentioned one embodiment, an edge of the multiplication layer may overlap with the shielding member when viewed from a direction perpendicular to the first surface, in which case generation of carriers outside the detection target region can be suppressed.

[0027] In the above aspect, each avalanche photodiode may be a front-illuminated type in which detection light is incident from a first surface, or a back-illuminated type in which detection light is incident from a second surface.

[0028] In one of the above embodiments, when viewed from a direction perpendicular to the first surface, a portion of each second semiconductor layer that overlaps with the multiplication layer may have a rectangular shape extending in a direction along the first surface.

[0029] In the above embodiment, when viewed from a direction perpendicular to the first surface, the width of each second semiconductor layer may be greater than the shortest distance between adjacent second semiconductor layers, in which case the directions of electric field lines from the second semiconductor layers are unified, and generated carriers are easily guided to the second semiconductor layers. Effect of the Invention

[0030] One aspect of the present invention provides an avalanche photodiode array that can reduce dead areas and achieve desired detection of electromagnetic waves or particle beams with a simple configuration. [Brief description of the drawings]

[0031] [Figure 1] 1 is a schematic plan view of an avalanche photodiode array according to an embodiment of the present invention. [Diagram 2] FIG. 2 is a cross-sectional view of an avalanche photodiode array. [Diagram 3] FIG. 2 is a plan view of an avalanche photodiode array. [Figure 4] FIG. 2 is a partially enlarged view of an avalanche photodiode array. [Diagram 5] FIG. 11 is a cross-sectional view of an avalanche photodiode array in a modified example of the present embodiment. [Figure 6]FIG. 11 is a cross-sectional view of an avalanche photodiode array in a modified example of the present embodiment. [Figure 7] 1 is a schematic plan view of an avalanche photodiode array which is a modified example of the present embodiment. [Figure 8] 1A and 1B are schematic plan views of an avalanche photodiode array which is a modified example of this embodiment. [Figure 9] FIG. 11 is a cross-sectional view of an avalanche photodiode array in a modified example of the present embodiment. [Figure 10] 1 is a schematic plan view of an avalanche photodiode array which is a modified example of the present embodiment. [Figure 11] 5(a) and 5(b) are schematic diagrams showing the configuration of a semiconductor layer in a comparative example. [Figure 12] FIG. 13 is a diagram showing the evaluation results of an APD array. [Figure 13] FIG. 13 is a diagram showing the evaluation results of an APD array. [Figure 14] FIG. 2 is a schematic diagram showing an electric field between semiconductor layers. [Figure 15] 1 is a schematic diagram showing an electric field intensity in a semiconductor substrate; DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0032] Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings. In the description, the same elements or elements having the same functions will be denoted by the same reference numerals, and duplicated descriptions will be omitted.

[0033] First, the configuration of the avalanche photodiode array in this embodiment will be described with reference to Figs. 1 to 4. Hereinafter, "avalanche photodiode" will be referred to as "APD". Fig. 1 is a schematic plan view of the APD array in this embodiment. Fig. 2 is a cross-sectional view of the APD array. Fig. 3 is a plan view of the APD array. Fig. 4 is a partially enlarged view of the APD array. The X-axis, Y-axis, and Z-axis are mutually orthogonal. Direction D1 coincides with the Z-axis direction. Direction D2 is orthogonal to direction D1 and parallel to the XY-axis plane. Hereinafter, direction D1 will also be referred to as the "Z-axis direction".

[0034] The APD array 1 is used for detecting electromagnetic waves or particle beams. The APD array 1 can be used, for example, as a light detector for LiDAR (Light Detection and Ranging). The APD array 1 can also be used, for example, as a detector for high-energy particles. The APD array 1 is particularly used for detecting electromagnetic waves or particle beams that require a relatively wide sensitivity layer. For example, the electromagnetic waves detected by the APD array 1 include electromagnetic waves having a wavelength of 600 nm to 1200 nm, or X-rays. The particle beams detected by the APD array 1 include high-energy particle beams such as electron beams. Hereinafter, X-rays and high-energy particle beams are collectively referred to as "high-energy beams". In this embodiment, the APD array 1 is of a surface incidence type.

[0035] 1 and 2, the APD array 1 includes a semiconductor substrate 10. As shown in Fig. 2, the semiconductor substrate 10 has a first surface 11 and a second surface 12 facing each other.

[0036] The semiconductor substrate 10 has a plurality of APDs 15. The plurality of APDs 15 are arranged along a first surface 11. As shown in Fig. 3, the APD array 1 includes a detection target area DA. The APD array 1 outputs a detection signal according to an electromagnetic wave or particle incident on the detection target area DA. Each APD 15 operates in a linear mode.

[0037] In this embodiment, each APD 15 is a front-incident type in which detection light is incident from the first surface 11. That is, in this embodiment, the first surface 11 corresponds to an incident surface. The Z axis is perpendicular to the first surface 11. The X axis and the Y axis extend along the first surface 11.

[0038] As shown in FIG. 2, the semiconductor substrate 10 includes a semiconductor region 20 provided on the first surface 11 side. The semiconductor region 20 is of a first conductivity type. In this embodiment, the semiconductor region 20 forms a part of the first surface 11. The semiconductor substrate 10 further includes a first semiconductor layer 21, a plurality of second semiconductor layers 22, and a multiplication layer 40. The plurality of APDs 15 include the first semiconductor layer 21, the plurality of second semiconductor layers 22, and the multiplication layer 40 provided in the semiconductor substrate 10. The first semiconductor layer 21 is of a first conductivity type. The plurality of second semiconductor layers 22 are of a second conductivity type.

[0039] The first semiconductor layer 21 is provided closer to the second surface 12 than the semiconductor region 20. The first semiconductor layer 21 is provided along the second surface 12. In this embodiment, the first semiconductor layer 21 forms the second surface 12. The first semiconductor layer 21 is in contact with the semiconductor region 20 in the semiconductor substrate 10. When viewed from the Z-axis direction, the multiple second semiconductor layers 22 and the multiplication layer 40 are provided within the range in which the first semiconductor layer 21 is located. In this embodiment, the first semiconductor layer 21 corresponds to an anode.

[0040] The multiple second semiconductor layers 22 are arranged along the first surface 11. Each second semiconductor layer 22 forms a part of the first surface 11. Each second semiconductor layer 22 is surrounded by a semiconductor region 20 when viewed from the Z-axis direction. In this embodiment, each second semiconductor layer 22 contacts the semiconductor region 20 on a surface other than the surface that forms the first surface 11. When viewed from the Z-axis direction, the semiconductor region 20 is provided between the adjacent second semiconductor layers 22. Each second semiconductor layer 22 corresponds to a channel layer that outputs a detection signal of each APD 15.

[0041] As shown in FIG. 1, when viewed from the Z-axis direction, the portion of each second semiconductor layer 22 overlapping with the multiplication layer 40 has, for example, a rectangular shape extending in the X-axis direction. In this specification, "overlap" is not limited to the case where the contours of the layers match, but includes the case where they overlap at least partially. When viewed from the Z-axis direction, the portion of each second semiconductor layer 22 overlapping with the detection target area DA has, for example, a rectangular shape extending in the X-axis direction. In this specification, the "rectangular shape" also includes a shape with rounded corners. When viewed from the Z-axis direction, the width W1 of each second semiconductor layer 22 is greater than the shortest distance L1 between the second semiconductor layers 22 adjacent to each other. When viewed from the Z-axis direction, the width W1 of each second semiconductor layer 22 is, for example, greater than 10 μm. The width W1 of the second semiconductor layer 22 is, for example, the length in the direction along the X-axis direction.

[0042] The multiplication layer 40 multiplies carriers. The multiplication layer 40 is provided in the semiconductor region 20. The multiplication layer 40 is provided between a plurality of second semiconductor layers 22 and the first semiconductor layer 21 in the Z-axis direction. The multiplication layer 40 is provided, for example, in a range of 10 μm or less from the first surface 11 in the Z-axis direction. The multiplication layer 40 may be provided in a range of 1 μm or more and 10 μm or less from the first surface 11 in the Z-axis direction.

[0043] The multiplication layer 40 has, for example, a rectangular shape. The multiplication layer 40 extends, for example, in the X-axis direction. When viewed from the Z-axis direction, the multiplication layer 40 includes a pair of edges 41a and 41b facing each other in the X-axis direction and edges 41c and 41d facing each other in the Y-axis direction.

[0044] In the front-illuminated APD array 1, when the multiple second semiconductor layers 22 are two-dimensionally arranged in a matrix, the multiple second semiconductor layers 22 are arranged in two or less columns in the row or column direction. In this embodiment, as shown in Fig. 1, the multiple second semiconductor layers 22 are arranged in two or less rows in the Y-axis direction. The multiple second semiconductor layers 22 are arranged in three or more rows in the X-axis direction. The multiple second semiconductor layers 22 are arranged in two or less rows and three or more columns. In the configuration shown in Fig. 1, the multiple second semiconductor layers 22 are arranged in two rows and four columns.

[0045] When viewed from the Z-axis direction, the multiple second semiconductor layers 22 are located between a pair of edges 41a, 41b in the X-axis direction. In other words, when viewed from the Z-axis direction, the pair of edges 41a, 41b of the multiplication layer 40 are located outside the edge 44a of the second semiconductor layer 44 that is located outermost in the X-axis direction among the multiple second semiconductor layers 22. When the multiple second semiconductor layers 22 are arranged in two rows or less and three columns or more, the multiplication layer 40 is disposed so as to straddle the multiple second semiconductor layers 22 when viewed from the Z-axis direction.

[0046] In this case, in the multiple second semiconductor layers 22, the areas where each second semiconductor layer 22 overlaps with the multiplication layer 40 are equal to each other when viewed from the Z-axis direction. "Equal" includes manufacturing tolerances. The detection target area DA is located within the range in which the multiplication layer 40 is located. When viewed from the Z-axis direction, each second semiconductor layer 22 extends in the Y-axis direction beyond the edges 41c, 41d of the multiplication layer 40.

[0047] 2, the multiplication layer 40 includes a third semiconductor layer 23 and a fourth semiconductor layer 24 facing each other. The third semiconductor layer 23 is provided closer to the first surface 11 than the fourth semiconductor layer 24. The fourth semiconductor layer 24 is provided closer to the second surface 12 than the third semiconductor layer 23. The third semiconductor layer 23 is of the second conductivity type. The fourth semiconductor layer 24 is of the first conductivity type.

[0048] In this embodiment, the multiplication layer 40 further includes a semiconductor region 20 located between the third semiconductor layer 23 and the fourth semiconductor layer 24. The third semiconductor layer 23 and the fourth semiconductor layer 24 face each other with the semiconductor region 20 therebetween and are spaced apart from each other. As a modification of this embodiment, the multiplication layer 40 may not include the semiconductor region 20. In this modification, the third semiconductor layer 23 and the fourth semiconductor layer 24 are connected to each other.

[0049] The multiplication layer 40 is provided continuously so as to overlap with the plurality of second semiconductor layers 22 when viewed from the Z-axis direction. In other words, when viewed from the Z-axis direction, a single region surrounded by the edges 41a, 41b, 41c, and 41d of the multiplication layer 40 overlaps with the plurality of second semiconductor layers 22. Each of the third semiconductor layer 23 and the fourth semiconductor layer 24 included in the multiplication layer 40 is provided continuously so as to overlap with the plurality of second semiconductor layers 22 when viewed from the Z-axis direction. The third semiconductor layer 23 and the fourth semiconductor layer 24 are provided so as to overlap with each other when viewed from the Z-axis direction. Both one third semiconductor layer 23 and one fourth semiconductor layer 24 face the plurality of second semiconductor layers 22 in the Z-axis direction.

[0050] In this embodiment, when viewed from the Z-axis direction, edges 41a, 41b, 41c, and 41d of the multiplication layer 40 coincide with edges of the third semiconductor layer 23. When viewed from the Z-axis direction, edges 41a, 41b, 41c, and 41d of the multiplication layer 40 coincide with edges of the fourth semiconductor layer 24. In this embodiment, each second semiconductor layer 22 includes a portion that does not overlap with the multiplication layer 40 when viewed from the Z-axis direction. For example, when viewed from the Z-axis direction, the area of ​​the region where the multiplication layer 40 and the multiple second semiconductor layers 22 overlap is 80% or more of the area of ​​the region where the multiplication layer 40 is located.

[0051] The semiconductor substrate 10 further includes a fifth semiconductor layer 25. When viewed from the Z-axis direction, the fifth semiconductor layer 25 surrounds the entire region in which the multiple second semiconductor layers 22 are arranged. The fifth semiconductor layer 25 forms a part of the first surface 11. The fifth semiconductor layer 25 is surrounded by the semiconductor region 20. The fifth semiconductor layer 25 is in contact with the semiconductor region 20 on a surface other than the surface that forms the first surface 11. The fifth semiconductor layer 25 is of the second conductivity type.

[0052] When viewed in the Z-axis direction, the multiplication layer 40 and the fifth semiconductor layer 25 at least partially overlap each other. When viewed in the Z-axis direction, the third semiconductor layer 23 and the fifth semiconductor layer 25 at least partially overlap each other. The fifth semiconductor layer 25 corresponds to an absorption layer that absorbs carriers generated outside the detection target area DA.

[0053] The semiconductor substrate 10 further includes a plurality of sixth semiconductor layers 26. Each sixth semiconductor layer 26 is of a first conductivity type. The plurality of sixth semiconductor layers 26 are arranged on the first surface 11. Each sixth semiconductor layer 26 forms a part of the first surface 11. Each sixth semiconductor layer 26 is surrounded by the semiconductor region 20. In this embodiment, each sixth semiconductor layer 26 is in contact with the semiconductor region 20 on a surface other than the surface forming the first surface 11. Each sixth semiconductor layer 26 is provided between a plurality of second semiconductor layers 22 adjacent to each other when viewed from the Z-axis direction. Each sixth semiconductor layer 26 corresponds to a separator that separates the second semiconductor layers 22 adjacent to each other and suppresses the movement of carriers.

[0054] Each sixth semiconductor layer 26 overlaps with the third semiconductor layer 23 when viewed from the Z-axis direction. In the Z-axis direction, the thickness of each sixth semiconductor layer 26 is smaller than the thickness of each second semiconductor layer 22. Each sixth semiconductor layer 26 and the third semiconductor layer 23 are spaced apart from each other. For example, in the Z-axis direction, the shortest distance between each sixth semiconductor layer 26 and the third semiconductor layer 23 is, for example, 1 μm or more. A semiconductor region 20 is provided between each sixth semiconductor layer 26 and the third semiconductor layer 23. In the direction along the first surface 11, the width of each sixth semiconductor layer is, for example, 8 μm or less.

[0055] The semiconductor substrate 10 further includes a semiconductor electrode layer 45. When viewed from the Z-axis direction, the semiconductor electrode layer 45 surrounds the entire region in which the plurality of second semiconductor layers 22 are arranged and the entire fifth semiconductor layer 25. The semiconductor electrode layer 45 forms a part of the first surface 11. The semiconductor electrode layer 45 is surrounded by the semiconductor region 20. The semiconductor electrode layer 45 contacts the semiconductor region 20 on a surface other than the surface that forms the first surface 11. The semiconductor electrode layer 45 is of a first conductivity type. When viewed from the Z-axis direction, the multiplication layer 40 and the semiconductor electrode layer 45 do not overlap. The semiconductor electrode layer 45 is electrically connected to the first semiconductor layer 21.

[0056] The semiconductor substrate 10 is made of, for example, a silicon semiconductor. In this case, the semiconductor substrate 10 contains silicon. In this case, the first conductive type is P type, and the second conductive type is N type. In the semiconductor substrate 10, the first semiconductor layer 21 and the fourth semiconductor layer 24, which are P type semiconductor layers, are doped with, for example, a Group III element as an impurity. The P type impurity includes, for example, at least one selected from boron, gallium, and indium. The second semiconductor layer 22 and the third semiconductor layer 23, which are N type semiconductor layers, are doped with, for example, a Group V element as an impurity. The N type impurity includes, for example, at least one selected from phosphorus, arsenic, and antimony.

[0057] The doping of the impurities is performed by, for example, ion implantation or thermal diffusion. In this embodiment, the second semiconductor layer 22, the third semiconductor layer 23, the fourth semiconductor layer 24, the fifth semiconductor layer 25, and the semiconductor electrode layer 45 are formed by doping the impurities by ion implantation.

[0058] As a modification of this embodiment, the semiconductor substrate 10 may be made of, for example, a compound semiconductor. In this case, the semiconductor substrate 10 may contain indium phosphide. The first conductivity type is N-type, and the second conductivity type is P-type. In the semiconductor substrate 10, the N-type semiconductor layer is doped with, for example, a Group IV or Group VI element as an impurity. The N-type impurity includes, for example, at least one selected from silicon, tin, sulfur, selenium, and tellurium. The P-type semiconductor layer is doped with, for example, a Group II element as an impurity. The P-type impurity includes, for example, at least one selected from beryllium and zinc.

[0059] The amount of impurity doped in each of the semiconductor region 20, the first semiconductor layer 21, the second semiconductor layer 22, the third semiconductor layer 23, the fourth semiconductor layer 24, the fifth semiconductor layer 25, and the semiconductor electrode layer 45 satisfies the following relationship indicated by the impurity concentration, for example. The impurity concentration of the first semiconductor layer 21 and the impurity concentration of the fourth semiconductor layer 24 are, for example, equal to or higher than the impurity concentration of the semiconductor region 20, and more preferably, higher than the impurity concentration of the semiconductor region 20. The impurity concentration of the first semiconductor layer 21 is, for example, equal to or higher than the impurity concentration of the fourth semiconductor layer 24, and more preferably, higher than the impurity concentration of the fourth semiconductor layer 24. The impurity concentration of each second semiconductor layer 22 is, for example, equal to or higher than the impurity concentration of the third semiconductor layer 23, and more preferably, higher than the impurity concentration of the third semiconductor layer 23. The impurity concentration of the third semiconductor layer 23 is, for example, equal to or higher than the impurity concentration of the fourth semiconductor layer 24, and more preferably, higher than the impurity concentration of the fourth semiconductor layer 24. The impurity concentration of the sixth semiconductor layer 26 is equal to or higher than the impurity concentration of the semiconductor region 20, and more preferably higher than the impurity concentration of the semiconductor region 20. The impurity concentration of the fifth semiconductor layer 25 is, for example, equal to that of each second semiconductor layer 22. The impurity concentration of the semiconductor electrode layer 45 is, for example, equal to that of the first semiconductor layer 21. "Impurity concentration" means the amount of doped impurity per unit volume. The impurity concentration is also called the charge carrier concentration or the majority carrier concentration.

[0060] As a modification of this embodiment, the amount of impurity doped in each of the semiconductor region 20, the first semiconductor layer 21, the second semiconductor layer 22, the third semiconductor layer 23, the fourth semiconductor layer 24, the fifth semiconductor layer 25, and the semiconductor electrode layer 45 may be compared by the sum of the amount of impurity in the Z-axis direction, instead of the impurity concentration. The sum of the amount of impurity in the Z-axis direction can be obtained, for example, by performing a line integration in the Z-axis direction of the impurity concentration at an arbitrary position from the first surface 11 in the Z-axis direction. The section length for performing the line integration is, for example, the thickness in the Z-axis direction of the target region. Hereinafter, the value obtained by this line integration is referred to as the "integral amount of impurity."

[0061] For example, an arbitrary position from first surface 11 in the Z-axis direction is defined as “x”, the impurity concentration of third semiconductor layer 23 at arbitrary position “x” is defined as “f(x)”, the impurity concentration of fourth semiconductor layer 24 at arbitrary position “x” is defined as “g(x)”, and the thickness of third semiconductor layer 23 in the Z-axis direction is defined as “L α " and the thickness of the fourth semiconductor layer 24 in the Z-axis direction is "L β ", the shortest distance between the first surface 11 and the third semiconductor layer 23 in the Z-axis direction is "A", and the shortest distance between the first surface 11 and the fourth semiconductor layer 24 in the Z-axis direction is "B", then the following formula (2) is satisfied.

number

[0062] That is, the integral amount of impurities in the third semiconductor layer 23 is, for example, equal to or greater than the integral amount of impurities in the fourth semiconductor layer 24. More preferably, the integral amount of impurities in the third semiconductor layer 23 is greater than the integral amount of impurities in the fourth semiconductor layer 24, for example.

[0063] The amount of impurity doped in each of the semiconductor region 20, the first semiconductor layer 21, the second semiconductor layer 22, the third semiconductor layer 23, the fourth semiconductor layer 24, the fifth semiconductor layer 25, and the semiconductor electrode layer 45 satisfies the following relationship in the above-mentioned impurity integral amount. The impurity integral amount of the first semiconductor layer 21 and the impurity integral amount of the fourth semiconductor layer 24 are, for example, equal to or greater than the impurity integral amount of the semiconductor region 20, and more preferably, greater than the impurity integral amount of the semiconductor region 20. The impurity integral amount of the first semiconductor layer 21 is, for example, equal to or greater than the impurity integral amount of the fourth semiconductor layer 24, and more preferably, greater than the impurity integral amount of the fourth semiconductor layer 24. The impurity integral amount of each second semiconductor layer 22 is, for example, equal to or greater than the impurity integral amount of the third semiconductor layer 23, and more preferably, greater than the impurity integral amount of the third semiconductor layer 23. The impurity integral amount of the sixth semiconductor layer 26 is, for example, equal to or greater than the impurity integral amount of the semiconductor region 20, and more preferably, greater than the impurity integral amount of the semiconductor region 20. The impurity integral amount of the fifth semiconductor layer 25 is, for example, equal to that of each second semiconductor layer 22. The impurity integral amount of the semiconductor electrode layer 45 is, for example, greater than that of the first semiconductor layer .

[0064] 1 and 3, the APD array 1 further includes a plurality of metal layers 30, 31, and 32, and a plurality of pad electrodes 33, 34, and 35. The plurality of metal layers 30, 31, and 32, and the plurality of pad electrodes 33, 34, and 35 are all provided on the first surface 11.

[0065] When viewed from the Z-axis direction, the multiple metal layers 30 cover parts of the multiple second semiconductor layers 22. The multiple metal layers 30 are spaced apart from one another. The multiple metal layers 30 are in contact with different second semiconductor layers 22. Each metal layer 30 applies a potential to the second semiconductor layer 22 it is in contact with.

[0066] The metal layer 31 surrounds the plurality of second semiconductor layers 22 when viewed from the Z-axis direction. As shown in Fig. 2, the metal layer 31 overlaps with the fifth semiconductor layer 25 when viewed from the Z-axis direction. The metal layer 31 is provided continuously along the fifth semiconductor layer 25. The metal layer 31 is in contact with the fifth semiconductor layer 25, for example. For example, a potential may be applied to the fifth semiconductor layer 25 via the metal layer 31. In this case, the fifth semiconductor layer 25 can further absorb carriers generated in the detection target area DA.

[0067] 1, the metal layer 31 overlaps with edges 41a, 41b of the multiplication layer 40 when viewed from the Z-axis direction. The edges 41a, 41b of the multiplication layer 40 are shielded from light by the metal layer 31. The metal layer 31 corresponds to a shielding member that prevents the electromagnetic wave to be detected from being incident on the edges 41a, 41b, 41c, and 41d of the multiplication layer 40.

[0068] When viewed from the Z-axis direction, the metal layer 32 surrounds the metal layer 31 and the multiple second semiconductor layers 22. When viewed from the Z-axis direction, the metal layer 32 overlaps with the semiconductor electrode layer 45. The metal layer 32 is provided continuously along the semiconductor electrode layer 45. The metal layer 32 is in contact with the semiconductor electrode layer 45. An electric potential is applied to the semiconductor electrode layer 45 via the metal layer 32.

[0069] Each of the pad electrodes 33 is connected to the metal layer 30. Each of the pad electrodes 33 is electrically connected to each of the second semiconductor layers 22 via the metal layer 30. As shown in FIG. 3, each of the pad electrodes 33 is provided on the first surface 11 and contacts a corresponding one of the second semiconductor layers 22 via a corresponding one of the metal layers 30. Each of the pad electrodes 33 corresponds to an output terminal that outputs a detection signal from each of the second semiconductor layers 22. When viewed from the Z-axis direction, each of the pad electrodes 33 is provided in a range that does not overlap with the multiplication layer 40. The pad electrodes 33 are arranged in the X-axis direction and are connected to different second semiconductor layers 22 from each other. In this embodiment, each of the pad electrodes 33 corresponds to a cathode of the APD array 1.

[0070] The multiple pad electrodes 34 are connected to the metal layer 31. In this embodiment, each pad electrode 34 corresponds to a cathode of the APD array 1. The multiple pad electrodes 35 are connected to the metal layer 32. In this embodiment, the pad electrode 35, the metal layer 32, the semiconductor electrode layer 45, and the first semiconductor layer 21 correspond to an anode of the APD array 1.

[0071] 2, each APD 15 includes a branching layer 51, an electric field relaxation layer 52, a high electric field layer 53, an electric field control layer 54, and a sensitivity layer 55 formed in the semiconductor substrate 10. The branching layer 51, the electric field relaxation layer 52, the high electric field layer 53, the electric field control layer 54, and the sensitivity layer 55 are arranged in order from the first surface 11 to the second surface 12.

[0072] The branching layer 51 is made of the second semiconductor layer 22 and the semiconductor region 20. The branching layer 51 is located in a region from the first surface 11 to a boundary B1 between the semiconductor region 20 on the first surface 11 side and the third semiconductor layer 23. As a modification of the present embodiment, the second semiconductor layer 22 may be in contact with the third semiconductor layer 23. In this case, the branching layer 51 is made of the second semiconductor layer 22, and the boundary B1 is the boundary between the second semiconductor layer 22 and the third semiconductor layer 23.

[0073] The electric field relaxation layer 52, the high electric field layer 53, and the electric field control layer 54 correspond to the multiplication layer 40. In other words, in this embodiment, the multiplication layer 40 includes the electric field relaxation layer 52, the high electric field layer 53, and the electric field control layer 54. The electric field relaxation layer 52 relaxes the electric field intensity in the branching layer 51. The electric field relaxation layer 52 is made of the third semiconductor layer 23. The electric field relaxation layer 52 is located in a region from the boundary B1 to a boundary B2 between the semiconductor region 20 and the third semiconductor layer 23 on the second surface 12 side.

[0074] The high electric field layer 53 is a layer to which a higher electric field strength is applied during operation than the other semiconductor layers. The high electric field layer 53 corresponds to a carrier multiplication layer that multiplies carriers at an electric field strength higher than the other semiconductor layers. The high electric field layer 53 is made of the semiconductor region 20. The high electric field layer 53 is located in a region from the boundary B2 to the boundary B3 between the semiconductor region 20 and the fourth semiconductor layer 24.

[0075] The electric field control layer 54 controls the electric field intensity in the high electric field layer 53. The electric field control layer 54 is made of the fourth semiconductor layer 24. The electric field control layer 54 is located in a region from the boundary B3 to a boundary B4 between the semiconductor region 20 and the fourth semiconductor layer 24 on the second surface 12 side.

[0076] The multiplication layer 40 is located in the region from the boundary B1 to the boundary B4. In a modification of the present embodiment, when the semiconductor region 20 is not provided between the third semiconductor layer 23 and the fourth semiconductor layer 24, the multiplication layer 40 does not include the semiconductor region 20. In this case, the high electric field layer 53 corresponds to the boundary between the third semiconductor layer 23 and the fourth semiconductor layer 24.

[0077] The sensitive layer 55 is made of the semiconductor region 20. The sensitive layer 55 is located in a region from the boundary B4 to the boundary B5 between the semiconductor region 20 and the first semiconductor layer 21. In the Z-axis direction, the shortest distance L11 between the first semiconductor layer 21 and the fourth semiconductor layer 24 is greater than the shortest distance L12 between the plurality of second semiconductor layers 22 and the third semiconductor layer 23. Therefore, in the Z-axis direction, the thickness of the sensitive layer 55 is greater than the shortest distance L12 between the plurality of second semiconductor layers 22 and the third semiconductor layer 23. In the Z-axis direction, the thickness of the sensitive layer 55 may be greater than the thickness of the branching layer 51. In the Z-axis direction, the thickness of the sensitive layer 55 may be greater than the sum of the thickness of the branching layer 51 and the thickness of the multiplication layer 40. The thickness of the sensitive layer 55 is, for example, 10 μm or more and 1000 μm or less. The thickness of the sensitive layer 55 may be 20 μm or more and 80 μm or less.

[0078] When electrons or particles are incident on the sensitivity layer 55, carriers are generated in the sensitivity layer 55. The carriers generated in the sensitivity layer 55 move to the multiplication layer 40. The movement speed of the carriers generated in the sensitivity layer 55 depends on the electric field strength in the sensitivity layer 55. The carriers are multiplied in the multiplication layer 40. The carriers multiplied in the multiplication layer 40 move to the branching layer 51. The carriers that have moved to the branching layer 51 are output from each second semiconductor layer 22.

[0079] Next, an APD array according to a modification of this embodiment will be described with reference to Fig. 5. Fig. 5 is a cross-sectional view of an APD array 1A according to a modification of this embodiment. This modification is generally similar to or the same as the above-described embodiment and modifications. The APD array 1A differs from the above-described embodiment in that it includes a semiconductor substrate 10A instead of the semiconductor substrate 10. The following mainly describes the differences from the above-described embodiment.

[0080] As shown in FIG. 5, the semiconductor substrate 10A includes a plurality of junction termination extension regions (JTE) 27. Each second semiconductor layer 22 is covered by the junction termination extension region 27. When viewed from the Z-axis direction, the edge 22b of each second semiconductor layer 22 is covered by the junction termination extension region 27. In this modification, each second semiconductor layer 22 and the semiconductor region 20 are spaced apart from each other. The junction termination extension region 27 is provided between each second semiconductor layer 22 and the semiconductor region 20. Each second semiconductor layer 22 is in contact with the junction termination extension region 27 on a surface other than the surface that forms the first surface 11. In other words, a portion of each second semiconductor layer 22 facing the semiconductor region 20 is in contact with the junction termination extension region 27.

[0081] The fifth semiconductor layer 25 is covered by the junction termination extension region 27. When viewed from the Z-axis direction, the edge 25b of the fifth semiconductor layer 25 is covered by the junction termination extension region 27. In this modification, the fifth semiconductor layer 25 and the semiconductor region 20 are spaced apart from each other. The junction termination extension region 27 is provided between the fifth semiconductor layer 25 and the semiconductor region 20. The fifth semiconductor layer 25 is in contact with the junction termination extension region 27 on a surface other than the surface that forms the first surface 11. In other words, a portion of the fifth semiconductor layer 25 that faces the semiconductor region 20 is in contact with the junction termination extension region 27.

[0082] In this modification, each junction termination extension region 27 is spaced apart from the third semiconductor layer 23. A semiconductor region 20 is provided between each junction termination extension region 27 and the third semiconductor layer 23. As a further modification of this modification, each junction termination extension region 27 and the third semiconductor layer 23 may be in contact with each other.

[0083] As a further modification of this modification, the multiple junction termination extension regions 27 may be one continuous region. In this case, for example, the multiple second semiconductor layers 22 and the fifth semiconductor layers 25 are covered by one junction termination extension region 27.

[0084] Each junction termination extension region 27 is a semiconductor region of the second conductivity type. The impurity concentration of the junction termination extension region 27 is lower than the impurity concentration of the second semiconductor layer 22. The impurity integral amount of the junction termination extension region 27 is, for example, smaller than the impurity integral amount of the second semiconductor layer 22.

[0085] Next, an APD array according to a modification of this embodiment will be described with reference to Fig. 6. Fig. 6 is a cross-sectional view of an APD array 1B according to a modification of this embodiment. This modification is generally similar to or the same as the above-described embodiment and modifications. The APD array 1B differs from the configuration shown in Fig. 5 in that it includes a semiconductor substrate 10B instead of the semiconductor substrate 10A. Below, the differences from the configuration shown in Fig. 5 will be mainly described.

[0086] As shown in FIG. 6, the semiconductor substrate 10B differs from the semiconductor substrate 10A in that it includes a plurality of junction termination extension regions 27C instead of the plurality of junction termination extension regions 27. When viewed from the Z-axis direction, the edge 22b of each second semiconductor layer 22 is covered by the junction termination extension region 27C. The junction termination extension region 27C is provided between the edge 22b of each second semiconductor layer 22 and the semiconductor region 20. Each second semiconductor layer 22 contacts the semiconductor region 20 at a portion other than the edge 22b. For example, at least a portion of the surface 22a of each second semiconductor layer 22 that faces the first surface 11 contacts the semiconductor region 20. The edge 22b of each second semiconductor layer 22 includes the edge of the surface 22a of each second semiconductor layer 22 that faces the first surface 11.

[0087] When viewed from the Z-axis direction, the edge 25b of the fifth semiconductor layer 25 is covered by the junction termination extension region 27C. The junction termination extension region 27C is provided between the edge 25b of the fifth semiconductor layer 25 and the semiconductor region 20. A portion of the fifth semiconductor layer 25 other than the edge 25b is in contact with the semiconductor region 20. For example, at least a part of a surface 25a of the fifth semiconductor layer 25 that faces the first surface 11 is in contact with the semiconductor region 20. The edge 25b of the fifth semiconductor layer 25 includes an edge of the surface 25a of the fifth semiconductor layer 25 that faces the first surface 11.

[0088] In this modification, of the edge 25b of the fifth semiconductor layer 25, the junction termination extension region 27C is provided at the edge 25b on the second semiconductor layer 22 side, and the junction termination extension region 27C is not provided at the edge 25b on the semiconductor electrode layer 45 side. In a modification of this modification, the junction termination extension region 27C may be provided at both the edge 25b on the second semiconductor layer 22 side and the edge 25b on the semiconductor electrode layer 45 side of the fifth semiconductor layer 25.

[0089] In this modification, each junction termination extension region 27C is spaced apart from the third semiconductor layer 23. A semiconductor region 20 is provided between each junction termination extension region 27C and the third semiconductor layer 23. As a further modification of this modification, each junction termination extension region 27C and the third semiconductor layer 23 may be in contact with each other.

[0090] Each junction termination extension region 27C is a semiconductor region of the second conductivity type. The impurity concentration of the junction termination extension region 27C is lower than the impurity concentration of the second semiconductor layer 22. The impurity integral amount of the junction termination extension region 27C is smaller than the impurity integral amount of the second semiconductor layer 22, for example.

[0091] Next, an APD array according to a modification of this embodiment will be described with reference to Fig. 7. Fig. 7 is a schematic plan view of an APD array 1C according to a modification of this embodiment. This modification is generally similar to or the same as the above-described embodiment and modifications. This modification differs from the above-described embodiment in the positional relationship between the multiple second semiconductor layers 22 and the multiplication layer 40. Below, the differences from the above-described embodiment will be mainly described.

[0092] In the semiconductor substrate 10C of the APD array 1C, the second semiconductor layers 22 are arranged in one row, with three or more arranged in the X-axis direction. In other words, in the APD array 1C, the second semiconductor layers 22 are arranged in two rows or less and three columns or more. In the APD array 1C, the second semiconductor layers 22 are arranged in one row and eight columns.

[0093] In the APD array 1C, the multiplication layer 40 also has a rectangular shape. The multiplication layer 40 extends in the X-axis direction. When viewed from the Z-axis direction, the second semiconductor layers 22 are located between a pair of edges 41a, 41b in the X-axis direction. In other words, when viewed from the Z-axis direction, the pair of edges 41a, 41b of the multiplication layer 40 are located outside the edge 44a of the second semiconductor layer 44 that is located outermost in the X-axis direction among the second semiconductor layers 22. In other words, when viewed from the Z-axis direction, the multiplication layer 40 is disposed so as to straddle the second semiconductor layers 22. In this case, when viewed from the Z-axis direction, the areas of the regions where the second semiconductor layers 22 and the multiplication layer 40 overlap are equal to each other in the second semiconductor layers 22. When viewed from the Z-axis direction, each second semiconductor layer 22 extends in the Y-axis direction beyond the edges 41c, 41d of the multiplication layer 40. When viewed in the Z-axis direction, the multiplication layer 40 and the fifth semiconductor layer 25 at least partially overlap each other.

[0094] Next, an APD array according to a modification of this embodiment will be described with reference to Fig. 8(a) and Fig. 8(b). Fig. 8(a) is a schematic plan view of an APD array 1D according to a modification of this embodiment. Fig. 8(b) is a schematic plan view of an APD array 1E according to a modification of this embodiment. This modification is generally similar or the same as the above-described embodiment and modifications. This modification differs from the above-described embodiment in the positional relationship between the multiple second semiconductor layers 22 and the multiplication layer 40. Below, differences from the configuration shown in Fig. 8(a) and Fig. 8(b) will be mainly described.

[0095] In the APD array 1D, the second semiconductor layers 22 are arranged in one row and two columns. In other words, in the APD array 1D, the second semiconductor layers 22 are arranged in two rows or less and less than three columns.

[0096] In the APD array 1D, the multiplication layer 40 has a rectangular shape. The multiplication layer 40 extends in the X-axis direction. In the APD array 1D, when viewed from the Z-axis direction, the multiplication layer 40 is surrounded by the fifth semiconductor layer 25. When viewed from the Z-axis direction, the multiplication layer 40 and the fifth semiconductor layer 25 do not overlap. In this case, when viewed from the Z-axis direction, the areas of the regions where each second semiconductor layer 22 and the multiplication layer 40 overlap are equal to each other in the multiple second semiconductor layers 22. When viewed from the Z-axis direction, each second semiconductor layer 22 extends in the X-axis direction and the Y-axis direction beyond the edges 41a, 41b, 41c, and 41d of the multiplication layer 40.

[0097] In the APD array 1E, the second semiconductor layers 22 are arranged in two rows and two columns. In other words, in the APD array 1E, the second semiconductor layers 22 are arranged in two rows or less and less than three columns.

[0098] In the APD array 1E, the multiplication layer 40 has a rectangular shape. The multiplication layer 40 extends in the X-axis direction. In the APD array 1E, when viewed from the Z-axis direction, the multiplication layer 40 is surrounded by the fifth semiconductor layer 25. When viewed from the Z-axis direction, the multiplication layer 40 and the fifth semiconductor layer 25 do not overlap. In this case, when viewed from the Z-axis direction, the areas of the regions where each second semiconductor layer 22 and the multiplication layer 40 overlap are equal to each other in the multiple second semiconductor layers 22. When viewed from the Z-axis direction, each second semiconductor layer 22 extends in the X-axis direction and the Y-axis direction beyond the edges 41a, 41b, 41c, and 41d of the multiplication layer 40.

[0099] Next, an APD array in a modified example of this embodiment will be described with reference to Fig. 9. Fig. 9 is a cross-sectional view of an APD array 1F in a modified example of this embodiment. This modified example is generally similar to or the same as the above-described embodiment and modified examples. This modified example differs from the above-described embodiment in that the APD array is a back-illuminated type. Below, differences from the configuration shown in the above-described embodiment will be mainly described.

[0100] In the APD array 1F, each APD 15 is a back-illuminated type in which detection light is incident from the second surface 12. In this modification, the second surface 12 corresponds to the incident surface. The Z axis is perpendicular to the first surface 11. The APD array 1F includes a semiconductor substrate 10F. The semiconductor substrate 10F has a configuration in which the semiconductor substrate 10 of the APD array 1 shown in FIG. 5 is inverted upside down. The APD array 1F may have a configuration in which the semiconductor substrates 10A, 10B, 10C, 10D, and 10E are inverted upside down as the semiconductor substrate 10F.

[0101] In the Z-axis direction, the thickness of the first semiconductor layer 21 of the semiconductor substrate 10F is smaller than the thickness of the first semiconductor layer 21 of the semiconductor substrate 10. Only in this respect, the semiconductor substrate 10F differs from the semiconductor substrate 10. For example, the semiconductor substrate 10F is formed by removing a part of the first semiconductor layer 21 of the semiconductor substrate 10. For example, the semiconductor substrate 10F is formed by grinding the first semiconductor layer 21 of the semiconductor substrate 10A in the Z-axis direction.

[0102] The APD array 1F includes, in addition to the semiconductor substrate 10F, for example, a silicon oxide film 91, a light shielding film 92, a plurality of pad electrodes 93, a plurality of bump electrodes 94, a passivation layer 95, a resin layer 96, solder 97, and a control substrate 98. The second surface 12 of the semiconductor substrate 10F is covered with the silicon oxide film 91. The second surface 12 of the semiconductor substrate 10F may be covered with a silicon nitride film instead of the silicon oxide film 91.

[0103] In this modified example, the silicon oxide film 91 is covered with a light-shielding film 92. The light-shielding film 92 blocks electromagnetic waves and the like other than the electromagnetic waves or particle beams to be detected. The material of the light-shielding film 92 may be selected according to the electromagnetic waves or particle beams to be detected. The material of the light-shielding film 92 contains, for example, aluminum. The light-shielding film 92 transmits the high-energy beams to be detected and blocks visible light. As a result, the detection accuracy of the high-energy beam is improved. When the detection target is visible light, the APD array 1F does not need to include the light-shielding film 92.

[0104] The multiple pad electrodes 93 are provided on the first surface 11 of the semiconductor substrate 10F. Each pad electrode 93 is in contact with the first surface 11 of the semiconductor substrate 10F. The multiple pad electrodes 93 are arranged so as to be in contact with any one of the semiconductor electrode layer 45, the second semiconductor layer 22, and the fifth semiconductor layer 25.

[0105] A plurality of bump electrodes 94 are provided on the corresponding pad electrodes 93. The material of the bump electrodes 94 is, for example, nickel or gold. The APD array 1F may have a direct bond instead of the bump electrodes 94. The direct bond is, for example, a Cu-Cu direct bond.

[0106] The passivation layer 95 covers the first surface 11 of the semiconductor substrate 10F and the pad electrodes 93, except for the portions where each pad electrode 93 contacts the bump electrode 94. The material of the passivation layer 95 contains, for example, silicon nitride. The solder 97 electrically connects the control substrate 98 and the bump electrodes 94. The resin layer 96 is provided on the control substrate 98 so as to cover the bump electrodes 94 and the solder 97.

[0107] The control board 98 is electrically connected to the semiconductor substrate 10F through the solder 97, the bump electrodes 94, and the pad electrodes 93. The control board 98 applies a potential to the semiconductor electrode layer 45, the second semiconductor layer 22, and the fifth semiconductor layer 25 via the pad electrodes 93. The control board 98 acquires and processes detection signals from each APD 15 of the APD array 1F. The control board 98 includes a readout circuit that reads out the detection signals from each APD 15. The control board 98 includes, for example, an ASIC (Application Specific Integrated Circuit) or a PCB (Printed Circuit Board) board.

[0108] Next, an APD array according to a modification of this embodiment will be described with reference to Fig. 10. Fig. 10 is a schematic plan view of an APD array 1G according to a modification of this embodiment. This modification is generally similar to or the same as the above-described embodiment and modifications. This modification differs from the APD array 1F in the positional relationship between the multiple second semiconductor layers 22 and the multiplication layer 40. Below, the differences from the APD array 1F will be mainly described.

[0109] When the APD array is a back-illuminated type, the second semiconductor layers 22 may be two-dimensionally arranged in a matrix shape with three or more columns in the row and column directions. The configuration of the APD array in this case will be described with reference to FIG.

[0110] In the APD array 1G, the second semiconductor layers 22 are arranged in 9 rows and 7 columns. Therefore, in the APD array 1G, the second semiconductor layers 22 are two-dimensionally arranged in a matrix shape with three or more columns in the row and column directions.

[0111] In the APD array 1G, the multiplication layer 40 also has a rectangular shape. When viewed from the Z-axis direction, edges 41a, 41b, 41c, and 41d of the multiplication layer 40 include a pair of edges 41a, 41b that face each other in the X-axis direction and edges 41c, 41d that face each other in the Y-axis direction.

[0112] In the APD array 1G, when viewed from the Z-axis direction, the second semiconductor layers 22 are located between a pair of edges 41a, 41b in the X-axis direction. The second semiconductor layers 22 are located between a pair of edges 41c, 41d in the Y-axis direction. In other words, the second semiconductor layers 22 are arranged within the range in which the multiplication layer 40 is located when viewed from the Z-axis direction. In other words, all of the edges 41a, 41b, 41c, and 41d of the multiplication layer 40 are located outside the edge 44a of the second semiconductor layer 44 that is located at the outermost position among the second semiconductor layers 22 when viewed from the Z-axis direction. In other words, the multiplication layer 40 is arranged to straddle the second semiconductor layers 22 when viewed from the Z-axis direction. In this case, too, the areas of the regions in which the second semiconductor layers 22 and the multiplication layers 40 overlap are equal to each other when viewed from the Z-axis direction. When viewed in the Z-axis direction, the multiplication layer 40 and the fifth semiconductor layer 25 at least partially overlap each other. When viewed in the Z-axis direction, edges 41a, 41b, 41c, and 41d of the multiplication layer 40 of the APD array 1G overlap with the fifth semiconductor layer 25 along the entire periphery.

[0113] As described above, in the APD arrays 1, 1A, 1B, 1C, 1D, 1E, 1F, and 1G, the multiple APDs 15 include a first semiconductor layer 21 of a first conductivity type, multiple second semiconductor layers 22 of a second conductivity type, and a multiplication layer 40. When viewed from the Z-axis direction, each of the third semiconductor layer 23 and the fourth semiconductor layer 24 of the multiplication layer 40 is continuously provided so as to overlap with the multiple second semiconductor layers 22. In this case, carriers generated by the incidence of the electromagnetic wave or particle beam to be detected are multiplied by the multiplication layer 40 continuously provided so as to overlap with the multiple second semiconductor layers 22. The carriers multiplied in the multiplication layer 40 are output from each second semiconductor layer 22. With this configuration, the dead area can be reduced. Therefore, in a simple configuration without a microlens array or the like, the dead area is reduced and the desired electromagnetic wave or particle beam can be detected. With this configuration, the sensitivity layer can be configured relatively wide. Therefore, in particular, detection of electromagnetic waves or high-energy beams that require a relatively wide sensitivity layer can be realized.

[0114] 11(a) and 11(b) are schematic diagrams showing the configuration of the semiconductor layer in the comparative example. As shown in FIG. 11(a), when a multiplication layer is formed by the second semiconductor layer 22 of the second conductivity type and the semiconductor layer 140 of the first conductivity type for each APD 115, the gain varies between the APDs 115. As shown in FIG. 11(b), when one semiconductor layer 140 of the first conductivity type is formed for the second semiconductor layers 22 of different second conductivity types, the gain seems to be uniform between the APDs 115 including the different second semiconductor layers 22. However, in the configuration shown in FIG. 11(b), a high electric field layer 53 is formed between the second semiconductor layer 22 and the semiconductor layer 140, so that the electric field is concentrated at the edge 22b of each second semiconductor layer 22, and an edge breakdown occurs between each second semiconductor layer 22 and the semiconductor layer 140.

[0115] In the APD arrays 1, 1A, 1B, 1C, 1D, 1E, 1F, and 1G, the multiplication layer 40 is provided in addition to the second semiconductor layers 22, so that the high electric field layer 53 and the second semiconductor layers 22 are spaced apart from each other. Therefore, concentration of the electric field in each second semiconductor layer 22 is suppressed, and edge breakdown in each second semiconductor layer 22 is also suppressed.

[0116] In the APD arrays 1, 1A, 1B, 1C, 1D, 1E, 1F, and 1G, the multiplication layer 40 is provided continuously so as to overlap with a plurality of second semiconductor layers 22. This configuration can also suppress the variation in gain in each APD 15. Figures 12 and 13 show the evaluation results of the APD array 1. In this evaluation, a laser light was swept in the X-axis direction so as to pass through four second semiconductor layers 22 arranged in the X-axis direction.

[0117] Fig. 12 shows the output of the APD 15 corresponding to each second semiconductor layer 22 according to the irradiation position of the laser light. In Fig. 12, the horizontal axis shows the irradiation position of the laser, and the vertical axis shows the output current value. Signals S1 to S2 respectively show the output from the APD 15 corresponding to each second semiconductor layer 22.

[0118] Fig. 13 shows the overall output of the APD array 1 according to the irradiation position of the laser light. In Fig. 13, the horizontal axis shows the irradiation position of the laser, and the vertical axis shows the output current value. Signal S5 shows the sum of the outputs from each APD 15. In this way, it was confirmed that the APD array 1 suppresses the variation in gain between the APDs 15 and operates with a uniform gain.

[0119] In the APD arrays 1, 1A, 1B, 1C, 1D, 1E, 1F, and 1G, the shortest distance L11 between the first semiconductor layer 21 and the fourth semiconductor layer 24 in the Z-axis direction is greater than the shortest distance L12 between the second semiconductor layers 22 and the third semiconductor layer 23. In this case, a relatively wide sensitivity layer 55 is secured between the first semiconductor layer 21 and the fourth semiconductor layer 24. Therefore, the detection accuracy of electromagnetic waves or particle beams that require a relatively wide sensitivity layer 55 can be improved. For example, near-infrared rays having a wavelength longer than 6000 nm, X-rays having a wavelength shorter than ultraviolet rays, and high-energy particle beams can easily pass through a semiconductor substrate. If a relatively wide sensitivity layer 55 is secured, the detection accuracy of electromagnetic waves having a wavelength of 600 nm to 1200 nm and high-energy beams such as X-rays can also be improved.

[0120] 14 is a schematic diagram showing the electric field between each semiconductor layer. Each arrow indicates an electric field line. The electric field strength of the electric field E1 between the surface 22a of each second semiconductor layer 22 and the boundary B1 may be such that the carriers multiplied in the multiplication layer 40 are branched and guided. The electric field strength of the electric field E1, i.e., the electric field strength of the branching layer 51, may be, for example, 10 1 ~10 2 V / cm. The electric field strength of the electric field E1 is 10 3 If the electric field strength exceeds 10 V / cm, edge breakdown may occur. The electric field strength of the electric field E2 between the boundary B5 and the boundary B2 may be such that the generated carriers are sufficiently accelerated (drifted). In order to ensure responsiveness, the electric field strength of the electric field E2, i.e., the electric field strength of the sensitive layer 55, is set to, for example, 10 2 ~10 4The electric field strength of the electric field E3 between the boundary B3 and the boundary B4 may be an electric field strength that multiplies the carriers that flow in. The electric field strength of the electric field E3, that is, the electric field strength of the high electric field layer 53, is, for example, 10 5 ~10 6 It is about V / cm.

[0121] In the APD arrays 1, 1A, 1B, 1C, 1D, 1E, 1F, and 1G, the impurity concentration of the third semiconductor layer 23 is higher than the impurity concentration of the fourth semiconductor layer. In this case, during operation, the electric field strength of the electric field E3 between the first semiconductor layer 21 and the fourth semiconductor layer 24 is higher than the electric field strength of the electric field E1 between the first surface 11 and the third semiconductor layer 23. FIG. 15 is a schematic diagram showing the electric field strength in the semiconductor substrate. The relationship between the electric fields E1, E2, and E3 described above depends on the impurity concentration of the third semiconductor layer 23 and the impurity concentration of the fourth semiconductor layer. If the impurity concentration of the third semiconductor layer 23 is higher than the impurity concentration of the fourth semiconductor layer, the relationship of electric field E3>electric field E2>electric field E1 can be established. Therefore, the movement speed of the generated carriers between the first semiconductor layer 21 and the fourth semiconductor layer 24 is ensured, and a high-speed response can be realized. The edge breakdown between the plurality of second semiconductor layers 22 and the multiplication layer 40 can be further suppressed.

[0122] In the APD arrays 1, 1A, 1B, 1C, 1D, 1E, 1F, and 1G, formula (3) is satisfied.

number

[0123] "x" is an arbitrary position from the first surface 11 in the Z-axis direction. "f(x)" is the impurity concentration of the third semiconductor layer 23 at the arbitrary position "x". "g(x)" is the impurity concentration of the fourth semiconductor layer 24 at the arbitrary position "x". "L α " is the thickness of the third semiconductor layer 23 in the Z-axis direction. β" is the thickness of the fourth semiconductor layer 24 in the Z-axis direction. "A" is the shortest distance between the first surface 11 and the third semiconductor layer 23 in the Z-axis direction. "B" is the shortest distance between the first surface 11 and the fourth semiconductor layer 24 in the Z-axis direction. The relationship between the above-mentioned electric fields E1, E2, and E3 depends on the integral amount of impurity of the third semiconductor layer 23 and the integral amount of impurity of the fourth semiconductor layer. If the integral amount of impurity of the third semiconductor layer 23 is higher than the integral amount of impurity of the fourth semiconductor layer, the relationship electric field E3 > electric field E2 > electric field E1 can be established. In this case, the movement speed of the generated carriers between the first semiconductor layer 21 and the fourth semiconductor layer 24 is ensured, and high-speed response can be realized. Edge breakdown can be further suppressed between the multiple second semiconductor layers 22 and the multiplication layer 40.

[0124] When viewed from the Z-axis direction, the semiconductor substrates 10, 10A, 10B, 10C, 10D, 10E, 10F, and 10G each include a fifth semiconductor layer 25 of a second conductivity type that surrounds the entire region in which the second semiconductor layers 22 are arranged. When viewed from the Z-axis direction, the third semiconductor layer 23 and the fifth semiconductor layer 25 at least partially overlap each other. In this case, the variation in gain in each second semiconductor layer 22 can be further reduced. Furthermore, the movement of carriers generated outside the detection target region DA to the second semiconductor layer 22 can be suppressed.

[0125] In the APD arrays 1A and 1B, when viewed from the Z-axis direction, the edge 22b of each second semiconductor layer 22 is covered by the junction termination extension region 27, 27C. The junction termination extension region 27, 27C covering each second semiconductor layer 22 is a semiconductor region 20 of the second conductivity type having an impurity concentration lower than the impurity concentration of the second semiconductor layer 22. In this case, edge breakdown in each second semiconductor layer 22 can be further suppressed.

[0126] In the APD array 1A, the portion of each second semiconductor layer 22 that faces the semiconductor region 20 is covered with the junction termination extension region 27. In this case, edge breakdown in each second semiconductor layer 22 can be further suppressed.

[0127] In the APD arrays 1A and 1B, the junction termination extension region 27 covering each second semiconductor layer 22 is separated from the multiplication layer 40. In this case, the electric field strength between each second semiconductor layer 22 and the multiplication layer 40 can become more uniform.

[0128] In the APD arrays 1A and 1B, when viewed from the Z-axis direction, the edge 25b of the fifth semiconductor layer 25 is covered by the junction termination extension region 27, 27C. The junction termination extension region 27, 27C covering the fifth semiconductor layer 25 is a semiconductor region of the second conductivity type having an impurity concentration lower than the impurity concentration of the fifth semiconductor layer 25. In this case, edge breakdown in the fifth semiconductor layer 25 can be suppressed.

[0129] The semiconductor substrates 10, 10A, 10B, 10C, 10D, 10E, 10F, and 10G each include a sixth semiconductor layer 26 of a first conductivity type. When viewed from the Z-axis direction, the sixth semiconductor layer 26 is provided between adjacent second semiconductor layers 22 out of the multiple second semiconductor layers 22. The impurity concentration of the sixth semiconductor layer 26 is higher than the impurity concentration of the semiconductor region 20. In this case, the movement of carriers between adjacent second semiconductor layers 22 can be suppressed.

[0130] In the Z-axis direction, the thickness of the sixth semiconductor layer 26 may be smaller than the thickness of each of the second semiconductor layers 22. In this case, edge breakdown between the sixth semiconductor layer 26 and the third semiconductor layer 23 can be suppressed.

[0131] The semiconductor substrates 10, 10A, 10B, 10C, 10D, 10E, 10F, and 10G contain silicon. The second conductivity type is N-type. In a semiconductor substrate containing silicon, electrons are more likely to be multiplied by about 20 times than holes. Therefore, by providing the multiplication layer 40 to the N-type second semiconductor layer 22, the multiplication factor can be improved.

[0132] The semiconductor substrates 10, 10A, 10B, 10C, 10D, 10E, 10F, and 10G may contain indium phosphide. In this case, the second conductivity type may be P-type. In a semiconductor substrate containing indium phosphide, holes are more easily multiplied than electrons. Therefore, by providing the multiplication layer 40 to the P-type second semiconductor layer 22, the multiplication factor can be improved.

[0133] In the APD arrays 1, 1A, 1B, 1C, 1D, 1E, 1F, and 1G, the multiplication layer 40 is provided within a range of 10 μm or less from the first surface 11 in the Z-axis direction. In this case, the multiplication layer 40 has a configuration that is relatively easy to form. In particular, the multiplication layer 40 can be formed relatively easily when it is formed by ion implantation.

[0134] In the APD arrays 1, 1A, 1B, 1C, 1D, 1E, 1F, and 1G, the width W1 of each second semiconductor layer 22 is greater than 10 μm in the direction along the first surface 11. In this case, the size of each pixel that performs detection can be ensured.

[0135] In the APD arrays 1, 1A, 1B, and 1C, when viewed from the Z-axis direction, the multiplication layer 40 includes a pair of edges 41a, 41b facing each other. Three or more second semiconductor layers 22 are arranged in the opposing direction of the pair of edges 41a, 41b. When viewed from the Z-axis direction, the second semiconductor layers 22 are located between the pair of edges 41a, 41b in the opposing direction. In this case, the variation in gain in each second semiconductor layer 22 can be further suppressed.

[0136] In the APD arrays 1, 1A, 1B, 1C, 1D, 1E, 1F, and 1G, when viewed from the Z-axis direction, the areas of the regions where each second semiconductor layer 22 overlaps with the multiplication layer 40 are equal to each other in the multiple second semiconductor layers 22. In this case, the variation in gain in each second semiconductor layer 22 can be further suppressed.

[0137] In the APD arrays 1, 1A, 1B, 1C, 1D, and 1E, when viewed from the Z-axis direction, the edges 41a, 41b, 41c, and 41d of the multiplication layer 40 overlap with the metal layer 31 serving as a shielding member. In this case, generation of carriers outside the detection target area DA can be suppressed.

[0138] In the APD arrays 1, 1A, 1B, 1C, 1D, 1E, 1F, and 1G, when viewed from the Z-axis direction, the width W1 of each second semiconductor layer 22 is larger than the shortest distance L1 between adjacent second semiconductor layers 22. In this case, the directions of the electric field lines from the second semiconductor layers 22 are unified, and the generated carriers are easily guided to the second semiconductor layers 22.

[0139] Although the embodiments and modifications of the present invention have been described above, the present invention is not necessarily limited to the above-described embodiments, and various modifications are possible without departing from the spirit of the present invention.

[0140] For example, the semiconductor substrates 10, 10A, 10B, 10C, 10D, 10E, 10F, and 10G may include another separator instead of the plurality of sixth semiconductor layers 26. For example, a shallow trench isolation (STI) or LOCOS (LOCal Oxidation of Silicon) structure may be formed. In this case, the STI or LOCOS structure is formed at the position of each sixth semiconductor layer 26. However, in this case, the surface of the semiconductor substrate becomes uneven. When a structure in which a plurality of sixth semiconductor layers 26 are formed is used, the uniformity of the electric field strength in the multiplication layer 40 can be improved more than when the STI or LOCOS structure is used. When the STI or LOCOS structure is formed after the multiplication layer 40 is formed, the uniformity of the electric field strength in the multiplication layer 40 is improved more than when the STI or LOCOS structure is formed before the multiplication layer 40 is formed. [Explanation of symbols]

[0141] 1, 1A, 1B, 1C, 1D, 1E, 1F, 1G...APD array, 10, 10A, 10B, 10C, 10D, 10E, 10F, 10G...semiconductor substrate, 11...first surface, 12...second surface, 20...semiconductor region, 21...first semiconductor layer, 22...second semiconductor layer, 22b, 25b, 41a, 41b, 41c, 41d...edge, 23...third semiconductor layer, 24...fourth semiconductor layer, 25...fifth semiconductor layer, 26...sixth semiconductor layer, 27, 27C...junction termination extension region, 40...multiplication layer, 15...APD, L1, L11, L12...shortest distance, W1...width.

Claims

1. a semiconductor substrate having a first surface and a second surface opposed to each other and including a semiconductor region of a first conductivity type provided on the first surface side; the semiconductor substrate has a plurality of avalanche photodiodes arranged along the first surface; The plurality of avalanche photodiodes include a first semiconductor layer of a first conductivity type provided on the second surface side of the semiconductor region; a plurality of second semiconductor layers of a second conductivity type arranged along the first surface and each surrounded by the semiconductor region when viewed in a direction perpendicular to the first surface; a multiplication layer provided in the semiconductor region and between the second semiconductor layers and the first semiconductor layer in a direction perpendicular to the first surface, When viewed from a direction perpendicular to the first surface, the second semiconductor layers and the multiplication layer are provided within a range in which the first semiconductor layer is located, the multiplication layer includes a third semiconductor layer of a second conductivity type and a fourth semiconductor layer of a first conductivity type facing each other, the third semiconductor layer is provided closer to the first surface than the fourth semiconductor layer, An avalanche photodiode array, wherein each of the third semiconductor layer and the fourth semiconductor layer is provided continuously so as to overlap with the plurality of second semiconductor layers when viewed from a direction perpendicular to the first surface.

2. an impurity concentration of the first semiconductor layer and an impurity concentration of the fourth semiconductor layer are higher than an impurity concentration of the semiconductor region; an impurity concentration of the first semiconductor layer is higher than an impurity concentration of the fourth semiconductor layer; 2. The avalanche photodiode array according to claim 1, wherein the impurity concentration of each of the second semiconductor layers is higher than the impurity concentration of the third semiconductor layer.

3. 3. The avalanche photodiode array according to claim 1, wherein in a direction perpendicular to the first surface, a shortest distance between the first semiconductor layer and the fourth semiconductor layer is greater than a shortest distance between the plurality of second semiconductor layers and the third semiconductor layer.

4. 4. The avalanche photodiode array according to claim 1, wherein an impurity concentration of the third semiconductor layer is higher than an impurity concentration of the fourth semiconductor layer.

5. An arbitrary position from the first surface in a direction perpendicular to the first surface is defined as "x", an impurity concentration of the third semiconductor layer at the arbitrary position "x" is defined as "f(x)", an impurity concentration of the fourth semiconductor layer at the arbitrary position "x" is defined as "g(x)", and a thickness of the third semiconductor layer in a direction perpendicular to the first surface is defined as "L α " and the thickness of the fourth semiconductor layer in a direction perpendicular to the first surface is "L β ", the shortest distance between the first surface and the third semiconductor layer in a direction perpendicular to the first surface is "A", and the shortest distance between the first surface and the fourth semiconductor layer in a direction perpendicular to the first surface is "B", [0010] 5. The avalanche photodiode array according to claim 1, wherein:

6. the semiconductor substrate includes a fifth semiconductor layer of a second conductivity type surrounding an entire region in which the plurality of second semiconductor layers are arranged when viewed from a direction perpendicular to the first surface, The avalanche photodiode array according to claim 1 , wherein the third semiconductor layer and the fifth semiconductor layer at least partially overlap each other when viewed from a direction perpendicular to the first surface.

7. an edge of each of the second semiconductor layers is covered by a junction termination extension region when viewed perpendicular to the first surface; 7. The avalanche photodiode array according to claim 1, wherein the junction termination extension region covering each of the second semiconductor layers is a semiconductor region of a second conductivity type having an impurity concentration lower than an impurity concentration of the second semiconductor layer.

8. 8. The avalanche photodiode array of claim 7, wherein a portion of each of the second semiconductor layers facing the semiconductor region is covered by the junction termination extension region.

9. 9. The avalanche photodiode array of claim 7, wherein the junction termination extension region covering each of the second semiconductor layers is spaced apart from the multiplication layer.

10. When viewed in a direction perpendicular to the first surface, an edge of the fifth semiconductor layer is covered by a junction termination extension region; 7. The avalanche photodiode array of claim 6, wherein the junction termination extension region covering the fifth semiconductor layer is a semiconductor region of a second conductivity type having an impurity concentration lower than an impurity concentration of the fifth semiconductor layer.

11. the semiconductor substrate includes a sixth semiconductor layer of a first conductivity type provided between adjacent ones of the second semiconductor layers when viewed from a direction perpendicular to the first surface, The avalanche photodiode array according to claim 1 , wherein an impurity concentration of the sixth semiconductor layer is higher than an impurity concentration of the semiconductor region.

12. 12. The avalanche photodiode array of claim 11, wherein a thickness of the sixth semiconductor layer is smaller than a thickness of each of the second semiconductor layers in a direction perpendicular to the first surface.

13. the semiconductor substrate comprises silicon; 13. The avalanche photodiode array according to claim 1, wherein the second conductivity type is N-type.

14. the semiconductor substrate includes indium phosphide; 13. The avalanche photodiode array according to claim 1, wherein the second conductivity type is a P type.

15. 15. The avalanche photodiode array according to claim 1, wherein the multiplication layer is provided within a range of 10 μm or less from the first surface in a direction perpendicular to the first surface.

16. 16. The avalanche photodiode array according to claim 1, wherein a width of each of the second semiconductor layers in a direction along the first surface is greater than 10 μm.

17. When viewed in a direction perpendicular to the first surface, the multiplication layer includes a pair of edges opposed to each other, The plurality of second semiconductor layers are arranged in a direction in which the pair of edges face each other, and three or more of the second semiconductor layers are arranged in the direction in which the pair of edges face each other.

17. The avalanche photodiode array according to claim 1, wherein, when viewed from a direction perpendicular to the first surface, the plurality of second semiconductor layers are located between the pair of edges in the opposing direction.

18. 18. The avalanche photodiode array according to claim 1, wherein, when viewed from a direction perpendicular to the first surface, the areas of the regions where the second semiconductor layer and the multiplication layer overlap in the plurality of second semiconductor layers are equal to each other.

19. The avalanche photodiode array according to claim 1 , wherein an edge of the multiplication layer overlaps with a shielding member when viewed from a direction perpendicular to the first surface.

20. 20. The avalanche photodiode array according to claim 1, wherein each of the avalanche photodiodes is a front-illuminated type in which detection light is incident from the first surface, or a back-illuminated type in which detection light is incident from the second surface.

21. 21. The avalanche photodiode array according to claim 1, wherein, when viewed from a direction perpendicular to the first surface, a portion of each of the second semiconductor layers that overlaps with the multiplication layer has a rectangular shape extending in a direction along the first surface.

22. 22. The avalanche photodiode array according to claim 1, wherein, when viewed in a direction perpendicular to the first surface, a width of each of the second semiconductor layers is greater than a shortest distance between adjacent second semiconductor layers.

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