Power Conversion Equipment

Abstract

To provide a highly reliable power conversion device improving performance in operation continuation, with the suppression of a converter overcurrent and a converter overvoltage which occur in the event of a system accident.SOLUTION: A power conversion device which can convert between AC and DC includes a power converter and a converter control unit. The power converter includes a switching element which can switch AC terminal voltages on the AC side. The converter control unit gives an operation command to the switching element. Upon detection of an absolute value of the AC voltage decreased from a predetermined range, the converter control unit limits active power output by the power converter to a range which is smaller than a rated active power before an abnormality causing the decrease of the AC voltage absolute value is removed, and continues the restriction of the active power until at least the abnormality is removed.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] FIELD An embodiment of the present invention relates to a power conversion device. [Background technology]

[0002] In recent years, modular multilevel converters (MMCs) have been put to practical use as power converters. MMCs are power converters that have arm units that contain multiple unit converters (cells) connected in series, and can handle high voltages and large capacity by adding up the output voltages of each cell. Power converters are connected, for example, between AC and DC systems to convert power between them. When an abnormality such as an accident occurs in an AC or DC system to which a power converter is connected, the power converter is required to continue operation or to restart quickly after the abnormality is resolved so as not to impair the stability of the voltage and frequency of the AC system. However, for example, an accident occurs in the AC system, or the fluctuation in the AC system voltage immediately after the accident is cleared may cause an overshoot in the converter current, causing the converter to stop operation due to overcurrent protection. In addition, the excessive current may overcharge the cell capacitor, causing the converter to stop operation due to overvoltage protection. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2017-143624 A [Patent Document 2] JP 2017-143626 A Summary of the Invention [Problem to be solved by the invention]

[0004] An object of the present invention is to provide a highly reliable power conversion device that suppresses converter overcurrents and converter overvoltages that occur during a grid fault and has improved operation continuity performance. [Means for solving the problem]

[0005] A power conversion device according to an embodiment is a power conversion device capable of converting AC and DC. The power conversion device has a power converter and a converter control unit. The power converter includes a switching element capable of switching an AC terminal voltage on the AC side. The converter control unit issues an operation command to the switching element. When the converter control unit detects that the absolute value of the AC voltage has dropped below a predetermined range, the converter control unit limits an active power output by the power converter to a range smaller than a rated active power before an abnormality that has caused the drop in the absolute value of the AC voltage is eliminated, and continues to limit the active power at least until the abnormality is eliminated. [Brief description of the drawings]

[0006] [Figure 1] 1 is a diagram showing an example of the configuration of a power conversion device 100 according to an embodiment. [Diagram 2] FIG. 2 is a diagram showing an example of the configuration of a cell CL according to the embodiment. [Diagram 3] FIG. 13 is a diagram showing another example of the configuration of the cell CL according to the embodiment. [Figure 4] FIG. 2 is a diagram showing an example of the configuration of a converter control unit 20 of the embodiment. [Diagram 5] FIG. 2 is a diagram showing an example of the configuration of an AC information calculation unit 21 according to the embodiment. [Figure 6] FIG. 2 is a diagram showing an example of the configuration of a system fault detection unit 22 according to the embodiment. [Figure 7] 1 is a schematic diagram showing an example of a grid-connected converter system including an AC system and a power converter 10 connected to the AC system; [Figure 8] Phasor diagram of the grid-tied converter system. [Figure 9] 3 is a diagram showing an example of an operation of the power conversion device 100 according to the embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0007] Hereinafter, a power conversion device according to an embodiment will be described with reference to the drawings.

[0008] 1 is a diagram showing an example of a configuration of a power conversion device 100 according to an embodiment. The power conversion device 100 is provided at an interconnection point between an AC system and a DC system, and converts AC power supplied by the AC system into DC power supplied by the DC system. The AC system may be an AC power source or an AC load, and the DC system may be a DC power source or a DC load.

[0009] The power conversion device 100 includes a power converter 10 and a converter control unit 20. The power converter 10 is, for example, a double star-connected modular multilevel converter (hereinafter, MMC: Modular Multilevel Converter) that converts AC power and DC power mutually based on the control of the converter control unit 20. The power converter 10 includes a plurality of legs LG between a positive pole of a DC system (a positive pole terminal P shown in the figure) and a negative pole of the DC system (a negative pole terminal N shown in the figure).

[0010] The number of legs LG corresponds to, for example, the number of phases of AC power supplied by the AC system. In the embodiment, the AC system supplies three-phase AC power, namely, a first phase (R phase shown in the figure), a second phase (S phase shown in the figure), and a third phase (T phase shown in the figure). For this reason, the power converter 10 includes a leg LGr corresponding to the R phase, a leg LGs corresponding to the S phase, and a leg LGt corresponding to the T phase, as shown in FIG. 1. The legs LG have the same configuration as each other. In the following description, the configuration related to leg LGr is designated by the suffix "r", the configuration related to leg LGs is designated by the suffix "s", and the configuration related to leg LGt is designated by the suffix "t". In addition, when leg LGr, leg LGs, and leg LGt are not to be distinguished from one another, they are collectively referred to as "leg LG".

[0011] A certain phase of the three phases of AC power supplied by the AC system is connected to the leg LG. In the embodiment, the leg LG is connected to the AC system via a transformer TR. Specifically, the R phase is connected to the leg LGr, the S phase is connected to the leg LGs, and the T phase is connected to the leg LGt. In the following description, the connection point between the leg LGr and the R phase is referred to as the connection point CPr, the connection point between the leg LGs and the S phase is referred to as the connection point CPs, and the connection point between the leg LGt and the T phase is referred to as the connection point CPt. In the following description, when the connection points CPr, CPs, and CPt are not distinguished from each other, they are simply referred to as the connection point CP. In the following description, a portion having the same potential as the positive terminal P of the DC voltage output by the power converter 10 is also referred to as the positive terminal P of the leg LG, and a portion having the same potential as the negative terminal N of the DC voltage is also referred to as the negative terminal N of the leg LG.

[0012] Below, leg LGr will be described as a representative of each leg LG. Leg LGr includes two groups of n cells CL (cells CL1-1r to CL1-nr and cells CL2-1r to CL2-nr shown in the figure) and a plurality of reactors RT (reactors RT1r and RT2r shown in the figure). n is a natural number. Here, the group of cells CL between the positive terminal P of leg LG and the connection point of each phase is also referred to as a positive arm unit. In addition, the group of cells CL between the connection point of each phase and the negative terminal N of leg LG is also referred to as a negative arm unit.

[0013] In the positive arm unit of leg LGr, cells CL1-1r to CL1-nr are connected in series in the order shown from the positive terminal P side to the connection point CPr side, and these are connected to the connection point CPr via a reactor RT1r. In addition, in the negative arm unit of leg LGr, cells CL2-1r to CL2-nr are connected in series in the order shown from the connection point CPr side to the negative terminal N side, and these are connected to the connection point CPr via a reactor RT2r. The reactor RT may be connected to either the high potential side or the low potential side of the arm unit, or between the cells CL. The reactor RT may be replaced with a transformer having a special winding structure that has a leakage reactance sufficient to replace the function of the reactor, and may be integrated with the transformer TR.

[0014] Note that leg LGr may be provided with a current detector that detects a positive arm current (R-phase positive current Ipr shown in the figure) flowing from the positive terminal P to the connection point CP, and a current detector that detects a negative arm current (R-phase negative current Inr shown in the figure) flowing from the connection point CP to the negative terminal N. The AC current Isr may be directly detected by providing a separate current detector at the AC terminal, or may be indirectly detected by calculation from the difference Inr-Ipr between the detected positive arm current and negative arm current.

[0015] The converter control unit 20 controls the power converter 10 by, for example, a hardware processor such as a CPU executing a program (software) stored in a storage unit (not shown). Some or all of the components of the converter control unit 20 may be realized by hardware such as an LSI, ASIC, FPGA, or GPU, or may be realized by a combination of software and hardware. The processing of the converter control unit 20 will be described later.

[0016] FIG. 2 is a diagram showing an example of the configuration of a cell CL of the embodiment. The cell CL is, for example, a half-bridge circuit. As shown in FIG. 2, the cell CL includes, for example, a plurality of switching elements Q (switching elements Q1 to Q2 shown in the figure), a number of diodes D (diodes D1 to D2 shown in the figure) corresponding to the switching elements Q, and a capacitor C. The switching element Q is, for example, an insulated gate bipolar transistor (hereinafter, IGBT). However, the switching element Q is not limited to an IGBT. The switching element Q may be any element as long as it is a self-extinguishing switching element capable of realizing a converter or an inverter. In the embodiment, a case where the switching element Q is an IGBT will be described.

[0017] The switching element Q1 and the switching element Q2 are connected in series to each other. The switching element Q1, the switching element Q2, and the capacitor C are connected in parallel to each other. Each switching element Q and its paired diode D are connected in parallel to each other. Specifically, the switching element Q1 and the diode D1 are connected in parallel to each other, and the switching element Q2 and the diode D2 are connected in parallel to each other.

[0018] The cell CL has a positive terminal connected to the positive terminal P side of the leg LG and a negative terminal connected to the negative terminal N side. The positive terminal of the cell CL is connected to the connection point between the switching element Q1 and the switching element Q2, and the negative terminal of the cell CL is connected to the emitter terminal of the switching element Q2. In the following description, the voltage generated between the positive terminal and the negative terminal of the cell CL is referred to as the cell voltage Vo.

[0019] Each switching element Q has a switching terminal (not shown) for switching the switching element Q on and off, and the switching terminal is connected to the converter control unit 20, and a control signal is input from the converter control unit 20. Specifically, a first gate signal gtp is input as a control signal to the switching element Q1, and a second gate signal gtn is input as a control signal to the switching element Q2. The capacitor C included in the cell CL is charged or discharged by switching each switching element Q on or off based on the control signal. In addition, the cell CL is provided with a voltage detector (not shown) for detecting a capacitor voltage Vc, which is the voltage of the capacitor C.

[0020] If the control signal that turns on the switching element Q is expressed as "1" and the control signal that turns it off is expressed as "0", the cell voltage Vo coincides with the capacitor voltage Vc when (gtp, gtn) = (1, 0). Setting the control signal to (gtp, gtn) = (1, 0) is called insert, and this state is called the insert state. Also, the cell voltage Vo is 0 [V] when (gtp, gtn) = (0, 1). Setting the control signal to (gtp, gtn) = (0, 1) is called bypass, and this state is called the bypass state. In this way, the switching element Q provided in each arm unit is switched, and each cell is placed in the insert state or bypass state, thereby generating a multi-level waveform.

[0021] Setting the switching element Q to (gtp, gtn)=(1, 1) should be prohibited because it would short-circuit the capacitor C. Also, in order to prevent the state of the switching element Q from transiently becoming (gtp, gtn)=(1, 1) during switching, the switching element Q is usually controlled to a transient state (gtp, gtn)=(0, 0) for a very short time (dead time). Also, stopping the switching control of the switching element Q is achieved by fixing the state to (gtp, gtn)=(0, 0). Stopping the switching control of all switching elements Q of the power converter 10 is called gate blocking, and this state is called the gate blocked state.

[0022] Fig. 3 is a diagram showing another example of the configuration of a cell CL of the embodiment. The cell CL is, for example, a full bridge circuit. As shown in Fig. 3, the cell CL includes, for example, a plurality of switching elements Q (switching elements Q1 to Q4 shown in the figure), a number of diodes D (diodes D1 to D4 shown in the figure) corresponding to the number of switching elements Q, and a capacitor C. The switching element Q1 and the switching element Q2 are connected in series to each other. The switching element Q3 and the switching element Q4 are connected in series to each other. The switching elements Q1 and Q2, the switching elements Q3 and Q4, and the capacitor C are connected in parallel to each other.

[0023] Each switching element Q and its paired diode D are connected in parallel to each other. Specifically, the switching element Q1 and the diode D1 are connected in parallel to each other, the switching element Q2 and the diode D2 are connected in parallel to each other, the switching element Q3 and the diode D3 are connected in parallel to each other, and the switching element Q4 and the diode D4 are connected in parallel to each other.

[0024] The cell CL has a positive terminal connected to the connection point CPr side of the leg LGrs and a negative terminal connected to the connection point CPs side. The positive terminal of the cell CL is connected to the connection point between the switching element Q1 and the switching element Q2, and the negative terminal of the cell CL is connected to the connection point between the switching element Q3 and the switching element Q4. In the following description, the voltage generated between the positive terminal and the negative terminal of the cell CL is referred to as the cell voltage Vo.

[0025] Each switching element Q has a switching terminal (not shown) for switching the switching element Q on and off, and the switching terminal is connected to the converter control unit 20, and a control signal is input from the converter control unit 20. Specifically, a first gate signal gta is input as a control signal to the switching element Q1, a second gate signal gtb is input as a control signal to the switching element Q2, a third gate signal gtc is input as a control signal to the switching element Q3, and a fourth gate signal gtd is input as a control signal to the switching element Q4. The capacitor C included in the cell CL is charged or discharged by switching each switching element Q on or off based on the control signal. In addition, the cell CL is provided with a voltage detector (not shown) for detecting a capacitor voltage Vc, which is the voltage of the capacitor C.

[0026] If the control signal that turns on the switching element Q is expressed as "1" and the control signal that turns it off is expressed as "0", the cell voltage Vo will match the capacitor voltage Vc when (gta, gtb, gtc, gtd) = (1, 0, 0, 1). Setting the control signal to (gta, gtb, gtc, gtd) = (1, 0, 0, 1) is called positive voltage insertion, and this state is called the positive voltage insertion state. Also, the cell voltage Vo will match the inverse of the capacitor voltage -Vc when (gta, gtb, gtc, gtd) = (0, 1, 1, 0). Setting the control signal to (gta, gtb, gtc, gtd) = (0, 1, 1, 0) is called negative voltage insertion, and this state is called the negative voltage insertion state. Furthermore, the cell voltage Vo is 0 [V] when (gta, gtb, gtc, gtd) = (1, 0, 1, 0) or (0, 1, 0, 1). Setting the control signals to (gta, gtb, gtc, gtd) = (1, 0, 1, 0) or (0, 1, 0, 1) is called bypass, and this state is called the bypass state. In this way, the switching element Q of each arm unit is switched, and each cell is placed in a positive voltage insert state, a negative voltage insert state, or a bypass state, thereby generating a multi-level waveform.

[0027] In addition, setting the switching element Q to (gta, gtb)=(1, 1) or (gtc, gtd)=(1, 1) should be prohibited because it shorts the capacitor C. In addition, in order to prevent the state of the switching element Q from transiently becoming (gta, gtb)=(1, 1) or (gtc, gtd)=(1, 1) during switching, the switching element Q is usually controlled to a state (gta, gtb)=(0, 0) or (gtc, gtd)=(0, 0) for a very short time (dead time). In addition, when the switching control of the switching element Q is stopped, it is realized by fixing the state to (gta, gtb, gtc, gtd)=(0, 0, 0, 0). Stopping the switching control of all the switching elements Q of the power converter 10 is called gate block, and this state is called a gate block state.

[0028] Fig. 4 is a diagram showing an example of the configuration of the converter control unit 20 of the embodiment. The converter control unit 20 includes, as functional units, an AC information calculation unit 21, a grid fault detection unit 22, a command value limiting unit 23, a capacitor voltage collective control unit 24, a DC current control unit 25, and an AC current control unit 26. Note that Fig. 4 omits some of the control functional units included in the converter control unit 20. For example, in addition to the functional units shown as an example, the converter control unit 20 includes, although not shown in the figure, a gate signal generation unit that converts a voltage command value into a gate signal, a capacitor voltage balance control unit that equalizes the capacitor voltage, and a circulating current control unit that controls the circulating current circulating through each phase leg.

[0029] The AC information calculation unit 21 receives, for example, AC system voltages Vsr, Vss, and Vst of the AC system detected by the voltage detector shown in FIG. 1 as input, and calculates and outputs an AC system effective voltage Vsd, an AC system reactive voltage Vsq, and an AC system phase theta synchronized with the input AC system voltages.

[0030] The system fault detection unit 22 receives the AC system effective voltage Vsd as input, and outputs a system overvoltage fault detection signal OVFLT indicating whether or not an occurrence of an overvoltage due to an AC system fault has been detected, and a system undervoltage fault detection signal UVFLT indicating whether or not an occurrence of an undervoltage due to an AC system fault has been detected.

[0031] The command value limiting unit 23 includes, as functional units, a 1 / Vdc calculation unit 23A, a 1 / Vs calculation unit 23B, a limiter 23C, and a limiter 23D. The command value limiting unit 23 receives an active power command value P*, a reactive power command value Q*, a grid overvoltage fault detection signal OVFLT, and a grid undervoltage fault detection signal UVFLT as inputs, and outputs a limited DC current command value Idc*_lim and a limited reactive current command value Isq*_lim.

[0032] The 1 / Vdc calculation unit 23A converts the active power command value P* input to the command value limiting unit 23 into a DC current command value Idc* by multiplying it by 1 / Vdc. Here, Vdc is the rated DC voltage or the DC voltage detection value. The DC current command value Idc* is limited by the processing of the limiter 23C set based on the system overvoltage fault detection signal OVFLT and the system undervoltage fault detection signal UVFLT, and obtains a limited DC current command value Idc*_lim. The specific settings of the limiter 23C will be described later.

[0033] The 1 / Vs calculation unit 23B converts the reactive power command value Q* input to the command value limiting unit 23 into a reactive current command value Isq* by multiplying it by 1 / Vs. Here, Vs is a detection value of the rated AC system voltage or the AC system voltage amplitude. The reactive current command value Isq* is limited by the processing of the limiter 23C set based on the system overvoltage accident detection signal OVFLT and the system undervoltage accident detection signal UVFLT, and obtains a limited reactive current command value Isq*_lim. The specific settings of the limiter 23D will be described later.

[0034] In the example of FIG. 4, the DC current command value Idc* and the reactive current command value Isq* are subjected to the processing by the limiters 23C and 23D, but the active power command value P* and the reactive power command value Q* may be subjected to the processing by the limiters 23C and 23D and then converted to each current command value in the subsequent stages.

[0035] The capacitor voltage general control unit 24 receives the capacitor voltage command value Vc* and the average value Vc of the capacitor voltage inside the power converter 10 as input, and outputs an active current command value Isd* adjusted so that Vc coincides with Vc*.

[0036] The DC current control unit 25 includes, as functional units, a subtraction unit 25A, a PI calculation unit 25B, a limiter 25C, and an addition unit 25D. The DC current control unit 25 receives the limited DC current command value Idc*_lim, the DC current Idc, the grid overvoltage fault detection signal OVFLT, the grid undervoltage fault detection signal UVFLT, and the operation mode command MODE as inputs, and outputs a DC voltage command value Vdc*.

[0037] The subtraction unit 25A calculates the deviation between the limited DC current command value Idc*_lim and the DC current Idc by subtracting the DC current Idc from the limited DC current command value Idc*_lim, and outputs the deviation to the PI calculation unit 25B. The PI calculation unit 25B performs proportional-integral calculation processing on the calculated deviation, and outputs the result to the limiter 25C. The limiter 25C performs limiter processing on the output result, and outputs the DC voltage control amount ΔVdc. The addition unit 25D adds the DC voltage control amount ΔVdc and the rated DC voltage command value Vdc_ref, and outputs the DC voltage command value Vdc*.

[0038] The operation mode command MODE is a command signal that distinguishes between the DC voltage control mode and the DC current control mode. During normal operation when no abnormality occurs, in the DC voltage control mode, the upper and lower limits of the limiter 25C are both set to zero. Since the DC voltage control amount ΔVdc is zero, the DC voltage command value Vdc* coincides with the rated DC voltage command value Vdc_ref, and the terminal in the DC voltage control mode maintains the DC voltage of the DC system constant.

[0039] On the other hand, in the case of the DC current control mode, the limiter 25C is set so that both or either one of the upper and lower limits are set to a non-zero value. The DC voltage command value Vdc* is manipulated by the effective output of the DC voltage control amount ΔVdc, and the DC current Idc is controlled so as to coincide with the limited DC current command value Idc*_lim. For example, in a two-terminal DC current system, one end is set to the DC voltage control mode and the other end is set to the DC current control mode, thereby controlling the DC voltage and DC current of the DC system, respectively, to transmit active power. The specific settings of the limiter 23C according to the system overvoltage fault detection signal OVFLT and the system undervoltage fault detection signal UVFLT will be described later.

[0040] The AC current control unit 26 receives the active current command value Isd*, the limited reactive current command value Isq*_lim, the AC currents Isr, Iss, Ist, the AC system active voltage Vsd, the AC system reactive voltage Vsq, and the AC system phase theta, and outputs the converter AC terminal voltage command values ​​Vr*, Vs*, and Vt*. For example, the AC current control unit 26 applies non-interfering current control based on variables on a general rotating coordinate system, and manipulates the converter AC terminal voltage command values ​​Vr*, Vs*, and Vt* so that the active current Isd matches the active current command value Isd* and the reactive current Isq matches the limited reactive current command value Isq*_lim.

[0041] Although not shown, the converter control unit 20 further determines a voltage command value for each arm unit from the DC voltage command value Vdc* output by the DC current control unit 25 and the converter AC terminal voltage command values ​​Vr*, Vs*, and Vt* output by the AC current control unit 26. For the R-phase positive side arm unit, it calculates the arm voltage command value Varmpr* corresponding to the arm voltage Varmpr, and determines the gate signals gtp1-1r, gtn1-1r to gtp1-nr, and gtn1-nr of each cell and outputs them to the power converter 10. The same applies to the other arm units.

[0042] In the embodiment, the active power is controlled by adjusting the DC current Idc. When an active current flows in or out from the DC terminal side, the average value Vc of the capacitor voltage changes, and the capacitor voltage collective control unit 24 regulates the active current Isd on the AC terminal side to compensate for the change. The active power and the active power command value on the DC terminal side may be fed forward to the capacitor voltage collective control unit 24, and the active power required to maintain the capacitor voltage may be further adjusted by feedback control to obtain it. However, in order to limit the active power, it is necessary to first limit the DC current Idc. If the active power flowing in or out from the DC terminal side is reduced by limiting the DC current Idc, the active current command value Isd* will also decrease as a result, and the active power on the AC terminal side will also decrease.

[0043] FIG. 5 is a diagram showing an example of the configuration of the AC information calculation unit 21 of the embodiment. The AC information calculation unit 21 includes, for example, a conversion unit 21A, a PI calculation unit 21B, an addition unit 21C, and an oscillator 21D as functional units. The conversion unit 21A acquires information indicating the AC system voltages (R-phase voltage Vsr, S-phase voltage Vss, and T-phase voltage Vst) detected by the voltage detector shown in FIG. 1. The conversion unit 21A converts (calculates) the acquired R-phase voltage Vsr, S-phase voltage Vss, and T-phase voltage Vst into an AC system effective voltage Vsd and an AC system reactive voltage Vsq using the following formula (1). The AC system voltage phase theta is a value output by an oscillator 21D described later, and is a value indicating the voltage phase of a certain reference phase (in this example, the R phase) of the AC system.

[0044]

number

[0045] The PI calculation unit 21B calculates a frequency difference (hereinafter, frequency difference Δfpll) between the frequency of the AC system voltage to which the power converter 10 is connected and a reference AC system frequency fs0 based on the AC system reactive voltage Vsq converted by the conversion unit 21A, and performs proportional integral calculation processing. The frequency difference Δfpll takes a positive value when the frequency of the AC system voltage is higher than the reference AC system frequency fs0, and takes a negative value when the frequency is lower than the reference AC system frequency fs0. The reference AC system frequency fs0 is the rated frequency of the AC system to be connected, and is a constant of, for example, 50 [Hz] or 60 [Hz]. The frequency difference Δfpll continues to increase or decrease until the calculated value of the AC system reactive voltage Vsq input to the PI calculation unit 21B becomes zero, and converges to the value of the difference between the actual AC system frequency and the reference AC system frequency fs0.

[0046] The adder 21C adds the frequency difference Δfpll calculated by the PI calculator 21B to the reference AC system frequency fs0. In the following description, the frequency obtained by adding the frequency difference Δfpll to the reference AC system frequency fs0 is referred to as an AC frequency fpll.

[0047] The oscillator 21D outputs an AC system voltage phase theta that repeatedly and monotonically increases from a minimum value of 0 to a maximum value of 2π according to the frequency of the AC frequency fpll calculated by the adder 21C. As described above, the AC system voltage phase theta is used for the conversion of the AC system effective voltage Vsd and the AC system reactive voltage Vsq of the conversion unit 21A and for AC current control. In AC current control, when non-interfering current control based on variables on a general rotating coordinate system is applied, the AC system voltage phase theta is used for the rotating coordinate conversion or inverse conversion (fixed coordinate conversion) of voltage and current values.

[0048] Through the above-mentioned processing, the AC information calculation unit 21 obtains the AC system voltage phase theta by repeating the calculation of the AC system voltage phase theta so that the calculated value of the AC system reactive voltage Vsq in the conversion unit 21A becomes zero.

[0049] 6 is a diagram illustrating an example of the configuration of the system accident detection unit 22 according to the embodiment. The system accident detection unit 22 includes a comparator 22A and a state holder 22B as functional units. The comparator 22A compares the AC system effective voltage Vsd calculated by the AC information calculation unit with a preset AC system voltage upper limit value Vth_H and an AC system voltage lower limit value Vth_L. When the AC system effective voltage Vsd is greater than the AC system voltage upper limit value Vth_H, the comparator 22A outputs a system voltage upper limit over signal OV to the state holder 22B.

[0050] Furthermore, when the AC system effective voltage Vsd is smaller than the AC system voltage lower limit Vth_L, the comparator 22A outputs a system voltage lower limit over signal UV to the state holder 22B. A state in which the AC system effective voltage Vsd is larger than the AC system voltage upper limit Vth_H or smaller than the AC system voltage lower limit Vth_L is, for example, a state in which a system accident has occurred in the AC system, the amplitude of each phase voltage of the AC system indicates an abnormal value, or there is an imbalance between the phases. The range indicated by the AC system voltage upper limit Vth_H to the AC system voltage lower limit Vth_L is an example of a "predetermined range" that the absolute value of the AC voltage can take.

[0051] In addition, the comparator 22A may be configured to compare the composite voltage vector Vsdq obtained by equation (2) with a predetermined threshold value, and output a system voltage upper limit exceedance signal OV or a system voltage lower limit exceedance signal UV if the value of the composite voltage vector Vsdq is greater than a predetermined upper threshold value or less than a predetermined lower threshold value.

[0052]

number

[0053] When the comparator 22A outputs the system voltage upper limit over signal OV, the state holder 22B continues to output a valid system overvoltage accident detection signal OVFLT for the holding time period. On the other hand, when the comparator 22A outputs the system voltage lower limit over signal UV, the state holder 22B continues to output a valid system undervoltage accident detection signal UVFLT for the holding time period. The holding time is, for example, a period of 1 / 2 the voltage period of the AC system. By providing a holding time, even if the AC system effective voltage Vsd becomes oscillatory and repeatedly exceeds the AC system voltage upper limit value Vth_H or the AC system voltage lower limit value Vth_L, the valid state of the system overvoltage accident detection signal OVFLT or the system undervoltage accident detection signal UVFLT is maintained without interruption.

[0054] 7 is a schematic diagram showing an example of a grid-connected converter system including an AC system and a power converter 10 connected to the AC system. The power converter 10 is connected to an AC system voltage Vs via a grid-connection reactance Xs, and controls the incoming AC current Is by adjusting the AC terminal voltage V.

[0055] The interconnection reactance Xs is an equivalent interconnection impedance that collectively represents the effective reactance for the AC currents Isr, Iss, and Ist of each phase, and in FIG. 1, for example, it is the sum of 0.5 times the reactance value of the reactor RT for each arm and the reactance value of the transformer TR. In other words, if the reactance value of the reactor RT is X and the reactance value of the transformer TR is X', then Xs = X' + X / 2 [H]. If the power converter 10 is not an MMC but has a configuration like a general two-level converter that does not have a reactor in the arm, then the reactor connected to the AC side terminal or the transformer leakage reactance simply matches Xs.

[0056] Fig. 8 is a phasor diagram of the grid-connected converter system. Fig. 8(a) shows a situation in which active power and capacitive reactive power are controlled simultaneously. In this situation, the phase of the AC grid voltage Vs and the phase of the active current Isd match, so rectifier operation is performed (active power flows into the power converter 10), and the phase of the reactive current Isq leads the phase of the AC grid voltage Vs by 90 degrees, so capacitive reactive power operation is performed (leading reactive power operation). The converter AC terminal voltage V becomes larger than the AC grid voltage Vs.

[0057] Fig. 8(b) shows a situation in which active power and inductive reactive power are controlled simultaneously. In this situation, the phase of the AC system voltage Vs and the phase of the active current Isd match, so rectifier operation is performed (active power flows into the power converter 10), and the phase of the reactive current Isq lags the phase of the AC system voltage Vs by 90 degrees, so inductive reactive power operation is performed (lagging reactive power operation). The converter AC terminal voltage V can be made smaller than the AC system voltage Vs.

[0058] Fig. 8(c) shows a state where only the capacitive reactive power is controlled. In this state, the active current Isd is zero, so the active power is also zero, and the phase of the reactive current Isq leads the phase of the AC system voltage Vs by 90 degrees, so this is capacitive reactive power operation (leading reactive power operation). The converter AC terminal voltage V becomes larger than the AC system voltage Vs.

[0059] Fig. 8(d) shows a state in which only the inductive reactive power is controlled. In this state, the active current Isd is zero, so the active power is also zero, and the phase of the reactive current Isq lags behind the phase of the AC system voltage Vs by 90 degrees, so this is inductive reactive power operation (lagging reactive power operation). The converter AC terminal voltage V becomes smaller than the AC system voltage Vs.

[0060] Since the square of the amplitude of the AC current Is is the sum of the square of the amplitude of the active current Isd and the square of the amplitude of the reactive current Isq, it is effective to reduce the amplitude of the AC current Is by reducing both the active power and the reactive power. Also, it is effective to limit the capacitive reactive power, and in particular to output the inductive reactive power, in order to reduce the amplitude of the converter AC terminal voltage.

[0061] Fig. 9 is a diagram illustrating an example of the operation of the power conversion device 100 of the embodiment. In Fig. 9, time T0 indicates a time point when an AC system fault occurs. Before the AC system fault occurs at time T0, the AC system voltages Vsr, Vss, and Vst are three-phase balanced, have normal amplitudes, and have frequencies approximately equal to the reference AC system frequency fs0.

[0062] At this time, the AC system effective voltage Vsd becomes a constant value representing the absolute amplitude value. Since this value is not lower than the AC system voltage lower threshold Vth_L and is not higher than the AC system voltage upper threshold Vth_H, the system overvoltage fault detection signal OVFLT and the system undervoltage fault detection signal UVFLT are invalid.

[0063] When the grid overvoltage fault detection signal OVFLT and the grid undervoltage fault detection signal UVFLT are invalid, the limit value LM1 of the limiter 23C for the DC current command value is set so that the absolute values ​​of both the upper and lower limits are equivalent to the rated DC current or a current larger than the rated DC current, such as 1.1 times the rated DC current. The limit value LM2 of the limiter 23D for the reactive current command value is set so that the absolute values ​​of both the upper and lower limits are equivalent to the rated reactive current or a current larger than the rated reactive current, such as 1.1 times the rated reactive current. The limit value LM3 of the limiter 25C for the DC voltage margin is set so that the upper and / or lower limits are zero when the operation mode command MODE is the DC voltage control mode, and is set to a non-zero value when the operation mode command MODE is the DC current control mode.

[0064] During normal operation, the power converter 10 in the DC current control mode controls the DC current Idc to match the limit DC current command value Idc*_lim, thereby controlling the active power so that it does not exceed the rated active power corresponding to the active power command value P*. The active power of the power converter 10 in the DC voltage control mode connected to the power converter 10 in the DC current control mode via a DC system also becomes an active power that does not exceed the rated active power corresponding to the active power command value P*. Furthermore, each power converter 10 controls the reactive current Isq to match the limit reactive current command value Isq*_lim, thereby controlling the reactive power so that it does not exceed the rated reactive power corresponding to the reactive power command value Q*.

[0065] Next, assume that an AC system accident occurs at time T0, in which one phase of the AC system is grounded. As shown in the top row of FIG. 9, one of the AC system voltages Vsr, Vss, and Vst is at almost zero voltage. At this time, the voltages of the remaining two phases are healthy, so the AC system effective voltage Vsd oscillates at twice the AC system frequency. Since the minimum value of the AC system effective voltage Vsd is below the AC system voltage lower threshold Vth_L, the system undervoltage accident detection signal UVFLT becomes valid. During the period in which the one-phase ground fault continues, the valid state of the system undervoltage accident detection signal UVFLT is maintained by the effect of the state holder 22B of the system accident detection unit 22. In a typical AC system protection system, this period is about several times the AC system voltage period.

[0066] As shown in the bottom row of FIG. 9, due to the fluctuation of the AC system voltage when a fault occurs, an overshoot occurs in the AC current, and the maximum AC current amplitude Ismax increases. The maximum AC current amplitude Ismax is a quantity that represents the three-phase maximum value of the three-phase AC current. When the system undervoltage fault detection signal UVFLT is valid, the limit value LM1 of the limiter 23C for the DC current command value is set so that the absolute values ​​of both the upper and lower limits correspond to a current smaller than the rated DC current. In FIG. 9, for example, both the upper and lower limits of LM1 are set to zero.

[0067] The upper limit of the limit value LM2 of the limiter 23D for the reactive current command value may be set to a current equivalent to a current smaller than the rated capacitive reactive current. The lower limit of the limit value LM2 does not need to be changed from the normal operation. In FIG. 9, for example, the upper limit of LM2 is set to a current equivalent to a current smaller than the rated capacitive reactive current, and the lower limit of LM2 is set to a value equal to that during normal operation. Furthermore, the upper and / or lower limit of the limit value LM3 of the limiter 25C for the DC voltage margin is set to an absolute value larger than the set value during normal operation in the DC current control mode (the allowable fluctuation width of the DC voltage of another power converter 10 connected via the DC system), regardless of the operation mode command MODE.

[0068] When the system is undervoltage, the power converter 10 connected to the target AC system controls the DC current Idc to coincide with the limit DC current command value Idc*_lim, thereby limiting the active power to a value smaller than the rated active power. The limit DC current command value Idc*_lim input to the DC current control unit 25 is not limited in the power converter 10 on the AC side of the DC system where no system accident has occurred, but is limited in the power converter 10 on the AC side where the system accident has occurred. As a result, the power converters 10 try to control the DC current of the DC system to different values, but the DC current control of the power converter 10 with a small DC voltage margin (allowable fluctuation range of the DC voltage) is saturated, so that the DC current is finally controlled to a value according to the DC current control of the power converter 10 with a large DC voltage margin (allowable fluctuation range of the DC voltage).

[0069] When the power converter 10 on the AC side where the system fault has occurred is in the DC current control mode, the other power converter 10 in the DC system is in the DC voltage control mode, so the DC voltage margin is set to zero and the DC voltage is controlled to a constant value Vdc_ref. Therefore, by forming a difference voltage with respect to the constant DC voltage Vdc_ref of the other power converter 10 by the DC voltage control margin expanded when the system undervoltage fault detection signal UVFLT is valid, the voltage applied to the impedance of the DC system is adjusted and the DC current Idc is controlled to the limited value Idc*_lim.

[0070] On the other hand, when the power converter 10 on the AC side where the system fault has occurred is in the DC voltage control mode, the other power converter 10 in the DC system is in the DC current control mode, so the DC voltage margin is set to a non-zero value, and the DC voltage is controlled to a value obtained by adding the non-zero DC voltage control amount ΔVdc to the rated DC voltage Vdc_ref. When the system undervoltage fault detection signal UVFLT is valid, the DC voltage control margin is expanded more than the DC voltage margin in the other DC current control mode (during normal operation), so the DC current control of the other power converter 10 is saturated first (the DC voltage control amount ΔVdc becomes a fixed value when it reaches the limit value LM3 of the limiter 25C). The power converter 10 on the AC side where the system fault has occurred further forms a difference voltage with respect to the saturated DC voltage Vdc of the other power converter 10, thereby adjusting the voltage applied to the impedance of the DC system and controlling the DC current Idc to the limited Idc*_lim value.

[0071] When the system is undervoltage, the power converter 10 connected to the target AC system limits the DC current Idc regardless of the operation mode command MODE, and the active power flowing in and out of the DC terminal side is limited to a value smaller than the rated active power. As described above, if the active power flowing in and out of the DC terminal side is reduced by limiting the DC current Idc, the active current command value Isd* is reduced as a result, and the active power on the AC terminal side is also reduced to a value smaller than the rated active power. In addition, by controlling the reactive current Isq to match the limited reactive current command value Isq*_lim, for example, when the reactive power command value Q* is equivalent to the rated capacitive reactive power, the amount of capacitive reactive power is limited. The AC current amplitude maximum value Ismax is reduced at least by the amount of the active power limit. In addition, as the active power and the capacitive reactive power are reduced, the amplitude of the power converter AC terminal voltage is also reduced.

[0072] Time T1 in FIG. 9 indicates the time when the earth fault phase of the AC system is disconnected and the system fault is cleared. When the earth fault phase of the AC system is disconnected and the fault is cleared at time T1, the AC system voltage may temporarily rise to a voltage higher than the normal voltage during the recovery process as shown in the figure. This AC system transient overvoltage also appears as an increase in the AC system effective voltage Vsd. The AC system effective voltage Vsd exceeds the AC system voltage upper threshold Vth_H, and the system overvoltage fault detection signal OVFLT becomes effective. When the system overvoltage fault detection signal OVFLT is effective, the limit value LM1 of the limiter 23C for the DC current command value is set so that the absolute values ​​of both the upper and lower limits are equivalent to a current smaller than the rated DC current. In FIG. 9, for example, both the upper and lower limits of LM1 are set to zero, similarly to when the system undervoltage fault detection signal UVFLT is effective.

[0073] The limit value LM2 of the limiter 23D for the reactive current command value may be set to a smaller upper limit or to zero, and the lower limit may not be changed from that during normal operation. In Fig. 9, for example, the upper limit of LM2 is set to zero, and the lower limit of LM2 is set to a value equal to that during normal operation. Furthermore, the limit value LM3 of the limiter 25C for the DC voltage margin is set so that the upper limit and / or lower limit are greater than the absolute value set during normal operation in the DC current control mode (the allowable fluctuation width of the DC voltage of another power converter connected via the DC system) regardless of the operation mode command MODE, as in the case where the system undervoltage fault detection signal UVFLT is valid.

[0074] In the case of a system overvoltage, similarly to the case of a system undervoltage, the power converter 10 connected to the target AC system limits the DC current Idc regardless of the operation mode command MODE, and the active power flowing in and out of the DC terminal side is limited to a value smaller than the rated active power. As described above, if the active power flowing in and out of the DC terminal side is reduced by limiting the DC current Idc, the active current command value Isd* is reduced as a result, and the active power on the AC terminal side is also reduced to a value smaller than the rated active power. In addition, by controlling the reactive current Isq to match the limited reactive current command value Isq*_lim, for example, the capacitive reactive power becomes zero. The maximum AC current amplitude Ismax is reduced at least by the amount of the active power limit. In addition, with the reduction in the active power and the capacitive reactive power, the amplitude of the AC terminal voltage of the power converter can be reduced.

[0075] In the case of a system overvoltage, the converter AC terminal voltage becomes higher because it faces a larger amplitude AC system voltage than in the case of a system undervoltage. The power converter 10 has an upper limit of the converter AC terminal voltage that can be output. For example, in the case of an MMC, the peak-to-peak maximum value of the outputtable phase voltage is about the value obtained by multiplying the rated capacitor voltage of the cell by the number of cells in series for each arm unit. When the maximum command value of the converter AC terminal voltage exceeds the upper limit of the outputtable voltage, a control saturation state called overmodulation occurs, and for example, the control of the AC current temporarily does not function, and a large current overshoot occurs. In FIG. 9, the maximum AC current amplitude Ismax also increases significantly immediately after time T1. This overshoot amount can be larger than the overshoot amount immediately after the occurrence of a system undervoltage accident T0, in which no overmodulation occurs.

[0076] In the embodiment, the peak value of the maximum AC current amplitude Ismax considering the current overshoot in FIG. 9 is suppressed by the following effects (a) to (c). (a) At the time of system undervoltage before the system overvoltage occurs immediately after the system fault recovery T1, at least the active power is limited in advance, so that the current value before the overshoot amount is added is small. (b) At the time of system undervoltage before the system overvoltage occurs immediately after the system fault recovery T1, the maximum values ​​of the active power and the capacitive reactive power are limited in advance, so that the amplitude of the converter AC terminal voltage before the control follows immediately after the system fault recovery T1 is also suppressed, and overmodulation is reduced. (c) When a system overvoltage occurs immediately after the system fault recovery T1, the maximum values ​​of the active power and the capacitive reactive power are limited, so that the amplitude of the converter AC terminal voltage is suppressed even after the control follows, and overmodulation is reduced.

[0077] In FIG. 9, the peak value of the maximum AC current amplitude Ismax does not exceed the overcurrent protection threshold Ioc, and the power converter 10 continues to operate. In addition, at this time, the risk of the cell capacitor being overcharged by an excessive current and operation being stopped due to overvoltage protection is also reduced. In this way, if a transient overvoltage occurs in the system when the system accident is recovered from, the power converter 10 may become uncontrollable (overmodulation), which has a more serious impact on the continuation of operation than when the system accident occurs (when there is an undervoltage). Therefore, by limiting the active power and reactive power in advance when the system accident occurs (when there is an undervoltage), it is possible to prevent operation from being stopped after the system accident is recovered from and after the system transient overvoltage is converged, and to quickly restore the operating state before the accident occurred.

[0078] 9 indicates the time point when the system overvoltage converges. At time T2, when the system overvoltage converges, the AC system effective voltage Vsd returns to the normal range, and the retention time of the state holder 22B of the system fault detection unit 22 has elapsed, the limit values ​​of the limiters are restored to the settings before the occurrence of the system fault, and the active power and reactive power are again controlled according to the control during normal operation.

[0079] According to at least one of the embodiments described above, even if the current increases due to a system transient overvoltage when the system is restored from a fault, the current absolute value is reduced in advance, so that the maximum current value can be suppressed. This makes it possible to prevent overcurrent protection stop or overvoltage protection stop due to the cell capacitor being charged with an excessive current.

[0080] Furthermore, according to the embodiment, the risk of overmodulation (uncontrollable) due to a system transient overvoltage can be reduced by limiting the capacitive reactive power that increases the amplitude of the converter AC terminal voltage. Appropriate control can be performed when the system is restored from a fault, thereby reducing the risk of protection shutdown.

[0081] Furthermore, according to the embodiment, by expanding the DC voltage margin, it is possible to limit the active power (DC current) regardless of the operation mode, that is, the DC voltage control mode or the DC current control mode. Furthermore, the power converter in the DC voltage control mode can limit the active power without communication, without giving a command to the power converter in the DC current control mode connected via the DC system.

[0082] Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included in the scope of the invention and its equivalents described in the claims, as well as in the scope and spirit of the invention. [Explanation of symbols]

[0083] 10...power converter, 20...converter control unit, 21...AC information calculation unit, 21A...conversion unit, 21B...PI calculation unit, 21C...addition unit, 21D...oscillator, 22...system fault detection unit, 22A...comparator, 22B...state holder, 23...command value limiting unit, 23A...1 / Vdc calculation unit, 23B...1 / Vs calculation unit, 23C, 23D...limiter, 24...capacitor voltage collective control unit, 25...DC current control unit, 26...AC current control unit, 100...power conversion device

Claims

1. A power conversion device capable of converting AC and DC, a power converter including a switching element capable of switching an AC terminal voltage on the AC side; A converter control unit that issues an operation command to the switching element, when detecting that the absolute value of the AC voltage has fallen below a predetermined range, the converter control unit limits the active power output by the power converter to a range smaller than a rated active power before an abnormality that has caused the fall in the absolute value of the AC voltage is eliminated, and continues to limit the active power at least until the abnormality is eliminated; the converter control unit includes a DC voltage margin setting unit that limits a manipulated variable based on a difference between a DC current at a DC terminal of the power converter and a DC current command value to be equal to or lower than an upper limit and / or equal to or higher than a lower limit of an allowable fluctuation range of a DC voltage, a command value of the DC voltage of the DC terminal includes the limited manipulated variable, During the limiting of the active power, the absolute value of the upper limit and / or the lower limit of the allowable fluctuation range of the DC voltage is changed to a value larger than that in the case where the absolute value of the AC voltage is within a predetermined range. Power conversion equipment.

2. A power conversion device capable of converting AC and DC, a power converter including a switching element capable of switching an AC terminal voltage on the AC side; A converter control unit that issues an operation command to the switching element, when detecting that the absolute value of the AC voltage has fallen below a predetermined range, the converter control unit limits the active power output by the power converter to a range smaller than a rated active power before an abnormality that has caused the fall in the absolute value of the AC voltage is eliminated, and continues to limit the active power at least until the abnormality is eliminated; the converter control unit includes a DC voltage margin setting unit that limits a manipulated variable based on a difference between a DC current at a DC terminal of the power converter and a DC current command value to be equal to or lower than an upper limit and / or equal to or higher than a lower limit of an allowable fluctuation range of a DC voltage, a command value of the DC voltage of the DC terminal includes the limited manipulated variable, during the limiting of the active power, changing the absolute value of the upper limit and / or the lower limit of the allowable fluctuation range of the DC voltage to a value larger than the absolute value of the upper limit and / or the lower limit of the allowable fluctuation range of the DC voltage of another power converter connected via the DC terminal; Power conversion equipment.

3. The converter control unit includes: when detecting that the absolute value of the AC voltage has risen above the predetermined range, limiting the active power output by the power converter to a range smaller than a rated active power; the limiting of the active power is continued until the abnormality is removed and the absolute value of the AC voltage falls within the predetermined range. The power conversion device according to claim 1 or 2.

4. when detecting that the absolute value of the AC voltage has dropped below the predetermined range, the converter control unit limits the capacitive reactive power output by the power converter to a range smaller than a rated capacitive reactive power before the abnormality that caused the drop in the absolute value of the AC voltage is eliminated, and continues to limit the capacitive reactive power at least until the abnormality is eliminated. The power conversion device according to claim 1 .

5. when detecting that an absolute value of the AC voltage has risen above the predetermined range, the converter control unit limits the capacitive reactive power output by the power converter to a range smaller than a rated capacitive reactive power; The limitation of the capacitive reactive power is continued until the abnormality is removed and the absolute value of the AC voltage falls within the predetermined range. The power conversion device according to claim 4.

6. when detecting that an absolute value of the AC voltage has increased above the predetermined range, the converter control unit limits the capacitive reactive power output by the power converter to zero; The limitation of the capacitive reactive power is continued until the abnormality is removed and the absolute value of the AC voltage falls within the predetermined range. The power conversion device according to claim 4.

7. The power converter has an arm unit in which a plurality of unit converters are connected in series, and includes a phase unit in which a first arm unit and a second arm unit are connected in series for each phase of an AC current; a connection point between the first arm unit and the second arm unit is a terminal that is connected to a phase of the AC; an inductance element is inserted at one end of each of the first arm unit and the second arm unit, or at an arbitrary position between the unit converters; Both ends of the phase unit are DC terminals, and the unit converter includes a plurality of switching elements and an energy storage element. The power conversion device according to any one of claims 1 to 6.

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