Fault detection circuit and inverter system

Abstract

A fault detection circuit (103) for detecting an abnormality in an inrush current prevention circuit (102) including an inrush resistor (200) and an inrush relay (201) arranged in parallel, the fault detection circuit (103) includes a resistive voltage divider circuit (301) for dividing a voltage across both ends of the inrush current prevention circuit (102), an amplifier circuit (302) for amplifying a difference in the voltage divided by the resistive voltage divider circuit (301), a peak hold circuit (303) for temporarily holding a peak of the voltage divided by the resistive voltage divider circuit (301), and a control unit (304) for detecting a break fault in the inrush resistor (200), a short fault in the inrush relay (201), and an open fault in the inrush relay (201) based on signals output from the amplifier circuit (302) and the peak hold circuit (303), respectively. The amplifier circuit (302) and the peak hold circuit (303) are connected in parallel between the resistive voltage divider circuit (301) and the control unit (304).

Description

[Technical field]

[0001] The present disclosure relates to a fault detection circuit for preventing inrush current in a power supply that is smoothed by a capacitor, and an inverter system. [Background technology]

[0002] Generally, electrical equipment that receives power from a commercial power source is equipped with an inrush current prevention circuit that prevents large currents from flowing through electronic components due to inrush current. When charging a capacitor inside the electrical equipment, the inrush current prevention circuit prevents excessive charging current from flowing through the capacitor by initially charging it through a resistor. However, if charging continues through the resistor, the resistor's temperature will exceed the allowable temperature, so after the capacitor has been charged to a certain extent, a relay that bypasses both ends of the resistor is turned on to charge the capacitor without passing through the resistor.

[0003] If an electrical device is used while a relay or resistor that constitutes an inrush current prevention circuit is faulty, an excessive inrush current may occur or components may overheat, causing the electrical device to fail.

[0004] Patent Document 1 discloses a fault detection circuit that includes a peak hold circuit between an inrush resistor and a comparator, and detects open circuit faults in the inrush resistor and short circuit faults in the inrush relay by monitoring the voltage across both ends of the inrush resistor and inrush relay that are connected in parallel. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] JP 2022-59371 A Summary of the Invention [Problem to be solved by the invention]

[0006] However, the fault detection circuit disclosed in the above Patent Document 1 cannot detect an open fault in an inrush relay, and therefore when an open fault occurs in an inrush relay in an electric device such as a power converter, the reliability of the entire system decreases and the downtime at the time of the fault increases. For this reason, there has been a demand for a fault detection circuit that can detect an open fault in an inrush relay.

[0007] The present disclosure has been made in consideration of the above, and has an object to provide a fault detection circuit that can detect an open fault in an inrush relay. [Means for solving the problem]

[0008] In order to solve the above-mentioned problems and achieve the object, a fault detection circuit according to the present disclosure detects an abnormality in an inrush current prevention circuit including an inrush resistor and an inrush relay arranged in parallel. The fault detection circuit includes a resistive voltage divider circuit that divides a voltage across both ends of the inrush current prevention circuit, an amplifier circuit that amplifies a difference in the voltage divided by the resistive voltage divider circuit, a peak hold circuit that performs temporary peak holding of the voltage divided by the resistive voltage divider circuit, and a control unit that detects an open circuit fault in the inrush resistor, a short circuit fault in the inrush relay, and an open circuit fault in the inrush relay based on signals output from the amplifier circuit and the peak hold circuit. The amplifier circuit and the peak hold circuit are connected in parallel between the resistive voltage divider circuit and the control unit. Effect of the Invention

[0009] The fault detection circuit according to the present disclosure has an effect of being able to detect an open fault in an inrush relay. [Brief description of the drawings]

[0010] [Figure 1] A functional block diagram of a drive circuit including a fault detection circuit according to a first embodiment. [Diagram 2] FIG. 1 is a diagram showing an example of an amplifier circuit of a failure detection circuit according to a first embodiment; [Diagram 3] FIG. 1 is a diagram showing an example of a peak hold circuit according to a first embodiment; [Figure 4] FIG. 1 is a diagram showing output voltages of an amplifier circuit and a peak hold circuit of a fault detection circuit according to a first embodiment in a normal state; [Diagram 5] FIG. 13 is a diagram showing voltage waveforms when an open fault occurs in an inrush relay of an amplifier circuit and a peak hold circuit of the fault detection circuit according to the first embodiment; [Figure 6] FIG. 13 is a diagram showing voltage waveforms when an inrush resistor in an amplifier circuit and a peak hold circuit in the fault detection circuit according to the first embodiment has a breakage fault; [Figure 7] FIG. 13 is a diagram showing voltage waveforms when an inrush relay of an amplifier circuit and a peak hold circuit of the fault detection circuit according to the first embodiment has a short circuit fault; [Figure 8] FIG. 1 is a diagram showing a modification of the amplifier circuit of the failure detection circuit according to the first embodiment; [Figure 9] FIG. 1 is a diagram showing a modified example of a peak hold circuit of the failure detection circuit according to the first embodiment. [Figure 10] FIG. 13 is a diagram showing output voltages of an amplifier circuit and a peak hold circuit in a fault detection circuit according to a first modification of the first embodiment under normal conditions. [Figure 11] FIG. 13 is a diagram showing voltage waveforms when an open fault occurs in an inrush relay of an amplifier circuit and a peak hold circuit of a fault detection circuit according to a first modification of the first embodiment; [Figure 12] FIG. 13 is a diagram showing voltage waveforms when an inrush relay of an amplifier circuit and a peak hold circuit of a fault detection circuit according to a first modification of the first embodiment has a short circuit fault; [Figure 13] FIG. 13 is a diagram showing voltage waveforms in a normal state when a three-phase AC ramp is input to an amplifier circuit and a peak hold circuit of a fault detection circuit according to a first modification of the first embodiment; [Figure 14] FIG. 13 is a diagram showing voltage waveforms of an amplifier circuit and a peak hold circuit of a fault detection circuit according to a first modification of the first embodiment when an open fault occurs in an inrush relay during a ramp input of a three-phase AC current. [Figure 15] FIG. 13 is a diagram showing voltage waveforms at the time of a breakage fault in an inrush resistor when a three-phase AC lamp is input to an amplifier circuit and a peak hold circuit of a fault detection circuit according to a first modification of the first embodiment; [Figure 16]FIG. 13 is a diagram showing voltage waveforms of an amplifier circuit and a peak hold circuit of a fault detection circuit according to a first modification of the first embodiment when a short fault occurs in an inrush relay during a three-phase AC ramp input. [Figure 17] FIG. 13 is a diagram showing power waveforms in a normal state when a direct current step is input to an amplifier circuit and a peak hold circuit of a fault detection circuit according to a first modification of the first embodiment; [Figure 18] FIG. 13 is a diagram showing a voltage waveform when an open fault occurs in an inrush relay when a DC step input is applied to the fault detection circuit according to the first modification of the first embodiment. [Figure 19] FIG. 13 is a diagram showing a voltage waveform when a breakage fault occurs in an inrush resistor when a direct current step is input to the fault detection circuit according to the first modification of the first embodiment; [Figure 20] FIG. 13 is a diagram showing a voltage waveform when a short fault occurs in an inrush relay when a DC step is input to the fault detection circuit according to the first modification of the first embodiment. [Figure 21] FIG. 13 is a diagram showing a voltage waveform during normal operation of the fault detection circuit according to the first modification of the first embodiment when a direct lamp current is input; [Figure 22] FIG. 13 is a diagram showing a voltage waveform when an open fault occurs in an inrush relay when a DC lamp is input to a fault detection circuit according to a first modification of the first embodiment. [Diagram 23] FIG. 13 is a diagram showing a voltage waveform when an inrush resistor has a breakage fault when a direct current is input to a lamp in the fault detection circuit according to the first modification of the first embodiment; [Figure 24] FIG. 13 is a diagram showing a voltage waveform when an inrush relay is short-circuited when a direct current lamp is input to the fault detection circuit according to the first modification of the first embodiment; [Diagram 25] FIG. 13 is a diagram showing a voltage waveform when a breakage fault occurs in an inrush resistor when a single-phase AC is input to the fault detection circuit according to the first modification of the first embodiment. [Figure 26] FIG. 13 is a diagram showing a configuration of a drive circuit including a failure detection circuit according to a second embodiment. [Figure 27] FIG. 13 is a diagram showing a drive circuit including a failure detection circuit according to a first modification of the second embodiment. [Figure 28] FIG. 13 is a diagram showing an example of a temperature simulation result using the fault detection circuit according to the second embodiment; [Figure 29]FIG. 13 is a diagram showing an example of a temperature simulation result using the fault detection circuit according to the first modification of the second embodiment; [Diagram 30] FIG. 1 is a diagram showing an example of a hardware configuration for implementing a control unit of a fault detection circuit according to the first and second embodiments; DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] A fault detection circuit and an inverter system according to an embodiment will be described in detail below with reference to the drawings.

[0012] Embodiment 1 1 is a functional block diagram of a drive circuit including a fault detection circuit according to a first embodiment. The drive circuit 800 includes a rectifier circuit 100 that rectifies an AC power supply 10, a smoothing capacitor 101 that smoothes a pulsating current, an inrush current prevention circuit 102 that prevents a large current from flowing through the smoothing capacitor 101 due to an inrush current, and a fault detection circuit 103 that detects an abnormality in the inrush current prevention circuit 102. The drive circuit 800 is connected to an inverter 400. The drive circuit 800 and the inverter 400 form a part of an inverter system 700 that supplies power to a load (not shown). The inverter 400 is supplied with power whose voltage has been smoothed by the smoothing capacitor 101.

[0013] The inrush current prevention circuit 102 includes an inrush resistor 200 and an inrush relay 201 connected in parallel. The inrush current prevention circuit 102 prevents an excessive current from flowing when the power is turned on in a state where the smoothing capacitor 101 has no charge.

[0014] The fault detection circuit 103 includes a resistive voltage divider circuit 301 that divides the voltage across both ends of the inrush current prevention circuit 102, an amplifier circuit 302 that amplifies the output divided by the resistive voltage divider circuit 301, a peak hold circuit 303 that performs signal processing on the voltage of the inrush current prevention circuit 102, and a control unit 304 that determines a fault in the inrush current prevention circuit 102.

[0015] The resistive voltage divider circuit 301 divides the voltage applied to both ends of the inrush current prevention circuit 102. Since a voltage of the order of 100V is applied to the busbar of the main circuit that supplies power to the inverter 400, if this voltage is directly input to the control unit 304, the control unit 304 will be damaged. Therefore, the resistive voltage divider circuit 301 divides the voltage so that a voltage of the order of 1V is input to the control unit 304.

[0016] Fig. 2 is a diagram showing an example of an amplifier circuit of the fault detection circuit according to embodiment 1. Amplifier circuit 302 shown in Fig. 2 amplifies the output divided by resistive voltage divider circuit 301 shown in Fig. 1 using amplifier 401, and outputs the amplified output to control unit 304 shown in Fig. 1. Hereinafter, the output voltage of amplifier circuit 302 is referred to as Vr.

[0017] Fig. 3 is a diagram showing an example of a peak hold circuit according to embodiment 1. Peak hold circuit 303 shown in Fig. 3 temporarily holds the peak of the output divided by resistive voltage divider circuit 301 shown in Fig. 1 in peak hold section 501, and outputs the output to control section 304 shown in Fig. 1. Hereinafter, the output voltage of peak hold circuit 303 is referred to as Vcg.

[0018] The control unit 304 detects whether the inrush resistor 200 and the inrush relay 201 are normal or in an abnormal state, based on the state of the voltage Vr output by the amplifier circuit 302 and the voltage Vcg output by the peak hold circuit 303. The control unit 304 detects the abnormal state by distinguishing between a break in the inrush resistor 200, an open fault in the inrush relay 201, and a short fault in the inrush relay 201.

[0019] FIG. 4 is a diagram showing the output voltage of the amplifier circuit and the peak hold circuit of the fault detection circuit according to the first embodiment in a normal state. In FIG. 4, the vertical axis indicates voltage, and the horizontal axis indicates time. In FIG. 4, time t0 is the time when the AC power supply 10 is turned on, time t1 is the time when the control unit 304 is started, time t2 is the time when the control of turning on the inrush relay 201 is completed, and time t3 is the time when the inverter 400 starts outputting. In FIG. 4, the dashed line indicates the voltage Vr, and the solid line indicates the voltage Vcg. During normal operation, when the AC power supply 10 is turned on at time t0, a transformer that generates a voltage to be supplied to each circuit (not shown) including the fault detection circuit 103 is started, and generation of a control power supply in which the voltage is controlled for each circuit is started. At time t1, the control unit 304 is started, and the bus voltage becomes constant. Since there is no charge in the smoothing capacitor 101 between time t0 and time t1, a large charging current flows through the inrush resistor 200. After time t1, due to the load of control unit 304, a charging current having a component six times the AC power supply frequency flows through inrush resistor 200 due to AC full-wave rectification via smoothing capacitor 101. When the bus voltage exceeds a preset threshold, control is performed to turn on inrush relay 201, and at time t2, inrush relay 201 is turned on. When inrush relay 201 is turned on, a charging current begins to flow through inrush relay 201, and no charging current flows through inrush resistor 200. When inverter output begins at time t3, more charging current begins to flow through inrush relay 201.

[0020] The output voltage Vr of the amplifier circuit 302 and the output voltage Vcg of the peak hold circuit 303 behave normally as follows. After time t1, a charging current having a component six times the AC power supply frequency flows through the inrush resistor 200 due to AC full-wave rectification, and therefore the output voltage Vr of the amplifier circuit 302 appears with a magnitude corresponding to the charging current. When the inrush relay 201 is turned on at time t2, no discharge current flows through the inrush resistor 200, and the output voltage Vr of the amplifier circuit 302 becomes 0V.

[0021] Furthermore, between time t0 and time t1, a large charging current flows through inrush resistor 200, and capacitor 503 is charged according to the voltage obtained by subtracting forward voltage VF of diode 502 of peak hold unit 501 from the voltage division value of resistor voltage divider circuit 301 at that time. At time t1, voltage Vcg that exceeds judgment reference value Vlevel1 appears. After time t1, the charge of capacitor 503 is discharged via resistor 504, and voltage Vcg decreases over time until it becomes equal to or lower than judgment reference value Vlevel1.

[0022] FIG. 5 is a diagram showing voltage waveforms at the time of an open fault of the inrush relay of the amplifier circuit and the peak hold circuit of the fault detection circuit according to the first embodiment. In FIG. 5, the vertical axis indicates voltage, and the horizontal axis indicates time. As in FIG. 4, time t0 in FIG. 5 is the time when the AC power supply 10 is turned on, time t1 is the time when the control unit 304 is started, time t2 is the time when the control to turn on the inrush relay 201 is completed, and time t3 is the time when the inverter 400 starts outputting. In FIG. 5, the dashed line indicates the voltage Vr, and the solid line indicates the voltage Vcg. At the time of an open fault of the inrush relay 201, even if the bus voltage exceeds a preset threshold and the control to turn on the inrush relay 201 is performed, the inrush relay 201 is not turned on at time t2, so that the charging current continues to flow through the inrush resistor 200 even after time t2. Therefore, at the time of an open fault of the inrush relay 201, the voltage Vr continues to appear at a constant value even after time t2. When the output of the inverter 400 is turned on at time t3, a larger charging current flows through the inrush resistor 200, causing the voltage Vr to further increase. When the voltage Vr exceeds the judgment reference value Vlevel1, the control unit 304 detects an open fault in the inrush relay 201.

[0023] FIG. 6 is a diagram showing voltage waveforms when an inrush resistor of the amplifier circuit and the peak hold circuit of the fault detection circuit according to the first embodiment has a disconnection fault. In FIG. 6, the vertical axis indicates voltage, and the horizontal axis indicates time. As in FIG. 4, time t0 in FIG. 6 is the time when the AC power supply 10 is turned on, time t1 is the time when the control unit 304 is started, time t2 is the time when the control for turning on the inrush relay 201 is completed, and time t3 is the time when the inverter 400 starts outputting. In FIG. 6, the dashed line indicates voltage Vr, and the solid line indicates voltage Vcg. When an inrush resistor 200 has a disconnection fault, the charging path to the smoothing capacitor 101 is only the high-resistance resistor voltage divider circuit 301 from time t0 when the AC power supply 10 is turned on, so that the voltage across the inrush current prevention circuit 102 is high at least from time t1 to time t3. That is, when an open circuit fault occurs in the inrush resistor 200, the voltage Vr becomes a constant value exceeding the judgment reference value Vlevel1 at least from time t1 to time t3. The control unit 304 detects an open circuit fault in the inrush resistor 200 when the voltage Vr continues to have a constant value exceeding the judgment reference value Vlevel1 after time t1. Note that if the inrush relay 201 is turned on while the inrush resistor 200 has an open circuit fault, a large current flows through the smoothing capacitor 101. Therefore, the control unit 304 detects an open circuit fault in the inrush resistor 200 before the control to turn on the inrush relay 201 is completed at time t2. For this reason, in actual control, the inrush relay 201 is not turned on even at time t2 when the control to turn on the inrush relay 201 is completed.

[0024] FIG. 7 is a diagram showing voltage waveforms when the inrush relay of the amplifier circuit and the peak hold circuit of the fault detection circuit according to the first embodiment has a short circuit fault. In FIG. 7, the vertical axis indicates voltage, and the horizontal axis indicates time. As in FIG. 4, time t0 in FIG. 7 is the time when the AC power source 10 is turned on, time t1 is the time when the control unit 304 is started, time t2 is the time when the control for turning on the inrush relay 201 is completed, and time t3 is the time when the inverter 400 starts outputting. In FIG. 7, the dashed line indicates the voltage Vr, and the solid line indicates the voltage Vcg. When the inrush relay 201 has a short circuit fault, no charge / discharge current flows through the inrush resistor 200 from time t0 when the AC power source 10 is turned on to time t2 when the inrush relay 201 is turned on, so that the voltage Vcg does not exceed the judgment reference value Vlevel1 even after time t1 when the control unit 304 is started. The control unit 304 detects a short circuit failure of the inrush relay 201 if the voltage Vcg does not exceed the determination reference value Vlevel1 from time t1 to time t2 when the control to turn on the inrush relay 201 is completed.

[0025] 8 is a diagram showing a modified example of the amplifier circuit of the fault detection circuit according to the first embodiment. The amplifier circuit 302 according to the modified example includes a resistor 402 installed on the positive electrode line 405, a resistor 403 installed between the positive electrode line 405 and the negative electrode line 406, and a diode 404 installed in parallel with the resistor 403 between the positive electrode line 405 and the negative electrode line 406. Between time t1 and time t2, a current also flows in the discharging direction, but in the amplifier circuit 302 according to the modified example, the resistors 402 and 403 and the diode 404 are added, so that the voltage Vr becomes less than −0.3 V, and the control unit 304 is protected. The protection of the control unit 304 is not limited to the circuit configuration shown as an example, and any circuit configuration may be used as long as the same effect can be obtained.

[0026] FIG. 9 is a diagram showing a modified example of the peak hold circuit of the fault detection circuit according to the first embodiment. The peak hold circuit 303 according to the modified example includes an overvoltage protection circuit 900. The overvoltage protection circuit 900 includes a first bipolar transistor 901, a second bipolar transistor 902, and a plurality of resistors 903, 904, 905, and 906. Since the withstand voltage before the start of the control unit 304 is about 0.3 V, if the control unit 304 is not started before the capacitor 503 is charged with a voltage, the control unit 304 may be damaged. However, when the control power is supplied, the second bipolar transistor 902 is turned on, and then the first bipolar transistor 901 is also turned on, so that the voltage Vcg is input to the control unit 304 and the control unit 304 is started. The protection of the control unit 304 is not limited to the circuit configuration shown as an example, and any circuit configuration may be used as long as it provides a similar effect.

[0027] Next, a method for further improving the accuracy of the abnormality detection of the inrush relay 201 will be described. FIG. 10 is a diagram showing the output voltage of the amplifier circuit and the peak hold circuit of the fault detection circuit according to the first modification of the embodiment 1 in a normal state. In FIG. 10, the vertical axis indicates voltage, and the horizontal axis indicates time. As in FIG. 4, time t0 in FIG. 10 is the time when the AC power supply 10 is turned on, time t1 is the time when the control unit 304 is started, time t2 is the time when the control for turning on the inrush relay 201 is completed, and time t3 is the time when the inverter 400 starts outputting. In FIG. 10, the dashed line indicates the voltage Vr, and the solid line indicates the voltage Vcg. In the fault detection circuit 103 according to the first modification of the embodiment 1, a second judgment reference value Vlevel2 that is a value smaller than the first judgment reference value Vlevel1 is set. In addition, the control unit 304 judges each failure mode based on both the voltage Vr and the voltage Vcg. The behavior of the voltages Vr and Vcg is similar to that of the amplifier circuit 302 and the peak hold circuit 303 of the fault detection circuit 103 according to the first embodiment shown in Fig. 4. Immediately after the control unit 304 is started up at time t1, the voltage Vcg exceeds the second judgment reference value Vlevel2, and then the voltage Vcg gradually decreases to below the second judgment reference value Vlevel2.

[0028] FIG. 11 is a diagram showing voltage waveforms when an open fault occurs in the inrush relay of the amplifier circuit and the peak hold circuit of the fault detection circuit according to the first modified example of the first embodiment. In FIG. 11, the vertical axis indicates voltage, and the horizontal axis indicates time. As in FIG. 4, time t0 in FIG. 11 is the time when the AC power supply 10 is turned on, time t1 is the time when the control unit 304 is started, time t2 is the time when the control for turning on the inrush relay 201 is completed, and time t3 is the time when the inverter 400 starts outputting. In FIG. 11, the dashed line indicates the voltage Vr, and the solid line indicates the voltage Vcg. When an open fault occurs in the inrush relay 201, a large charging current flows through the inrush resistor 200 between time t0 and time t1, and the capacitor 503 is charged according to the voltage obtained by subtracting the forward voltage VF of the diode 502 of the peak hold unit 501 from the voltage division value of the resistive voltage division circuit 301 at that time. At time t1, a voltage Vcg that exceeds the first reference value Vlevel1 appears. After time t1, the charge of the capacitor 503 is discharged through the resistor 504, and the voltage Vcg drops over time to the first judgment reference value Vlevel1 or less. When an open fault occurs in the inrush relay 201, even if control is performed to turn on the inrush relay 201, the inrush relay 201 is not turned on at time t2, so the charging current continues to flow to the inrush resistor 200. Therefore, when an open fault occurs in the inrush relay 201, the voltage Vr continues to appear at a constant value even after time t2. Therefore, the control unit 304 detects an open fault in the inrush relay 201 when the voltage Vcg drops to the second judgment reference value Vlevel2 or less and the voltage Vr exceeds the second judgment reference value Vlevel2 for a certain period of time or more after time t2. This makes it possible to detect an open fault in the inrush relay 201 at an earlier stage than the method shown in FIG. 5.

[0029] Depending on the load of the control unit 304, the voltage Vr may not exceed the second judgment reference value Vlevel2 even if the charging current continues to flow to the inrush resistor 200. To avoid being unable to detect an open fault in the inrush relay 201 in such a case, the control unit 304 detects an open fault in the inrush relay 201 even when the voltage Vr exceeds the first judgment reference value Vlevel1 after the output of the inverter 400 is turned on, in the same manner as in the method shown in Fig. 5.

[0030] FIG. 12 is a diagram showing voltage waveforms when the inrush relay of the amplifier circuit and the peak hold circuit of the fault detection circuit according to the first modified example of the first embodiment has a short circuit fault. In FIG. 12, the vertical axis indicates voltage, and the horizontal axis indicates time. As in FIG. 4, time t0 in FIG. 12 is the time when the AC power source 10 is turned on, time t1 is the time when the control unit 304 is started, time t2 is the time when the control for turning on the inrush relay 201 is completed, and time t3 is the time when the inverter 400 starts outputting. In FIG. 12, the dashed line indicates the voltage Vr, and the solid line indicates the voltage Vcg. When the inrush relay 201 has a short circuit fault, no charge / discharge current flows through the inrush resistor 200 from time t0 when the AC power source 10 is turned on to time t2 when the inrush relay 201 is turned on, so that the voltages Vcg and Vr remain below the second judgment reference value Vlevel2 even after the time t1 when the control unit 304 is started. The control unit 304 detects a short circuit failure of the inrush relay 201 based on the fact that the voltage Vcg and the voltage Vr are equal to or lower than the second judgment reference value Vlevel2 for a certain period of time or more between time t1 and time t2. The set value for the certain period of time or more may be preset according to the device and system used by the user.

[0031] In this way, by setting a certain time period that is shorter than the time from time t1 to time t3, which is the timing when the inverter 400 starts operating, in addition to the first judgment reference value Vlevel1 and the second judgment reference value Vlevel2, detection of a short circuit fault in the inrush relay 201 can be achieved without any problems.

[0032] It is expected that erroneous detection of a short circuit fault in the inrush relay 201 can be prevented by detecting a short circuit fault in the inrush relay 201 under the condition that the voltages Vcg and Vr are equal to or lower than the second judgment reference value Vlevel2 for a certain period of time or more after the time t2. Specifically, it is possible to prevent erroneous detection of a short circuit fault in the inrush relay 201 even in a case where a certain amount of charge has accumulated in the smoothing capacitor 101, the inrush current is suppressed, and the voltage Vcg does not rise to the first judgment reference value Vlevel1.

[0033] Furthermore, the method of determining when the inrush resistor 200 has a breakage fault is the same as when only the first determination reference value Vlevel1 is used, and the addition of the second determination reference value Vlevel2 does not affect the determination.

[0034] In the above explanation, the power supply is a three-phase AC step input, but the fault detection circuit 103 also operates without problems with lamp input, single-phase AC, or DC input. The operation in various modes when the power supply is changed will be explained below.

[0035] FIG. 13 is a diagram showing voltage waveforms in a normal state when a three-phase AC lamp is input to the amplifier circuit and the peak hold circuit of the fault detection circuit according to the first modified example of the first embodiment. In FIG. 13, the vertical axis indicates voltage, and the horizontal axis indicates time. In FIG. 13, time t0 is the time when the AC power source 10 is turned on, time t1 is the time when the control unit 304 is started, time t2 is the time when the control to turn on the inrush relay 201 is started, time t3 is the time when the control to turn on the inrush relay 201 is completed, time t4 is the time when the bus voltage becomes a constant value, and time t5 is the time when the inverter 400 starts outputting. In FIG. 13, the dashed line indicates the voltage Vr, and the solid line indicates the voltage Vcg. In normal operation, when the AC power source 10 is turned on at time t0, a transformer that generates a voltage to be supplied to each circuit including the fault detection circuit 103 is started, and each control power source is generated.

[0036] At time t1, the control unit 304 is started. Since the power supply is a lamp input, a large inrush current does not flow. Also, since there is a load of the control unit 304 after time t1, a charging current having a component six times the AC power supply frequency flows through the inrush resistor 200 by AC full-wave rectification via the smoothing capacitor 101. When the bus voltage exceeds the threshold at time t2, the inrush relay 201 is controlled to be turned on. At time t3, the inrush relay 201 is turned on. When the inrush relay 201 is turned on, a charging current flows through the inrush relay 201, and no charging current flows through the inrush resistor 200. When the inverter 400 starts outputting at time t5, a larger charging current flows through the inrush relay 201. Since a charging current having a component six times the AC power supply frequency flows through the inrush resistor 200 by AC full-wave rectification after time t1, a voltage Vr having a magnitude according to the charging current appears. When the inrush relay 201 is turned on at time t3, no charge / discharge current flows through the inrush resistor 200, and the voltage Vr becomes 0 V. Since the power supply is a lamp input, no large charge current flows, and therefore the voltage Vcg hardly appears after time t0.

[0037] Fig. 14 is a diagram showing voltage waveforms at the time of an open fault of the inrush relay when a three-phase AC lamp is input to the amplifier circuit and the peak hold circuit of the fault detection circuit according to the first modified example of the first embodiment. In Fig. 14, the vertical axis indicates voltage, and the horizontal axis indicates time. As in Fig. 13, time t0 in Fig. 14 is the time when the AC power supply 10 is turned on, time t1 is the time when the control unit 304 is started, time t2 is the time when the control to turn on the inrush relay 201 is started, time t3 is the time when the control to turn on the inrush relay 201 is completed, time t4 is the time when the bus voltage becomes a constant value, and time t5 is the time when the inverter 400 starts outputting. In Fig. 14, the dashed line indicates the voltage Vr, and the solid line indicates the voltage Vcg. When the inrush relay 201 has an open fault, the inrush relay 201 does not turn on at time t3, so that the charging current continues to flow through the inrush resistor 200 even after time t3, and the voltage Vr continues to appear at a value equal to or greater than a certain magnitude. When the inverter output turns on at time t5, more charging current flows through the inrush resistor 200, so that the value of the voltage Vr becomes even larger. When the value of the voltage Vr exceeds the first judgment reference value Vlevel1, the control unit 304 detects the open fault of the inrush relay 201.

[0038] In the case of an open fault in the inrush relay 201 during a three-phase AC ramp input, the voltage Vcg hardly appears after time t0, and therefore the method utilizing the fact that the voltage Vcg has dropped to or below the second judgment reference value Vlevel2 as shown in Fig. 11 cannot be used. Therefore, during a three-phase AC ramp input, the voltage Vr is used to detect an open fault in the inrush relay 201.

[0039] Fig. 15 is a diagram showing voltage waveforms at the time of a breakage fault in an inrush resistor when a three-phase AC lamp is input to the amplifier circuit and the peak hold circuit of the fault detection circuit according to the first modified example of the first embodiment. In Fig. 15, the vertical axis indicates voltage, and the horizontal axis indicates time. As in Fig. 13, time t0 in Fig. 15 is the time when the AC power supply 10 is turned on, time t1 is the time when the control unit 304 is started, time t2 is the time when the control to turn on the inrush relay 201 is started, time t3 is the time when the control to turn on the inrush relay 201 is completed, time t4 is the time when the bus voltage becomes a constant value, and time t5 is the time when the inverter 400 starts outputting. In Fig. 15, the dashed line indicates the voltage Vr, and the solid line indicates the voltage Vcg. When the inrush resistor 200 has a disconnection fault, the charging path to the smoothing capacitor 101 is only the high-resistance resistor voltage divider circuit 301 from time t0 when the lamp input AC power supply 10 is turned on, and the voltage across the inrush current prevention circuit 102 becomes high at least from time t1 to time t5. In other words, when the inrush resistor 200 has a disconnection fault, the voltages Vr and Vcg exceed the judgment reference value Vlevel1 from time t1 to at least time t5. The control unit 304 detects the disconnection fault of the inrush resistor 200 when the voltages Vr and Vcg continue to exceed the judgment reference value Vlevel1 for a first time period determined in advance after time t1. The set value of the first time period may be preset according to the device and system used by the user. If the inrush relay 201 is turned on while the inrush resistor 200 has an open circuit fault, a large current flows through the smoothing capacitor 101, so the control unit 304 detects the open circuit fault of the inrush resistor 200 before the control of turning on the inrush relay 201 is completed at time t3. For this reason, in actual control, the inrush relay 201 is not turned on even at time t3 when the control of turning on the inrush relay 201 is completed.

[0040] FIG. 16 is a diagram showing voltage waveforms at the time of a short circuit fault of the inrush relay at the time of lamp input of three-phase AC of the amplifier circuit and the peak hold circuit of the fault detection circuit according to the first modified example of the first embodiment. In FIG. 16, the vertical axis indicates voltage, and the horizontal axis indicates time. As in FIG. 13, time t0 in FIG. 16 is the time when the AC power source 10 is turned on, time t1 is the time when the control unit 304 is started, time t2 is the time when the control to turn on the inrush relay 201 is started, time t3 is the time when the control to turn on the inrush relay 201 is completed, time t4 is the time when the bus voltage becomes a constant value, and time t5 is the time when the inverter 400 starts outputting. In FIG. 16, the dashed line indicates the voltage Vr, and the solid line indicates the voltage Vcg. At the time of a short circuit fault of the inrush relay 201, no charging / discharging current flows through the inrush resistor 200 from time t0 when the lamp input AC power source 10 is turned on to time t3 when the inrush relay 201 is turned on. That is, even after time t1 when the control unit 304 is started, the voltages Vcg and Vr continue to be below the second judgment reference value Vlevel2 without exceeding it. After the control unit 304 is started, the control unit 304 detects a short circuit fault in the inrush relay 201 based on the fact that the voltages Vcg and Vr are equal to or less than the second judgment reference value Vlevel2 for a predetermined second time or more. Furthermore, by setting the second time in the same manner as in FIG. 12 described above, it becomes possible to detect a short circuit fault in the inrush relay 201 without any problems. The set value of the second time may be set in advance according to the device and system used by the user.

[0041] FIG. 17 is a diagram showing power waveforms in a normal state when a step of DC is input to the amplifier circuit and the peak hold circuit of the fault detection circuit according to the first modified example of the first embodiment. In FIG. 17, the vertical axis indicates voltage, and the horizontal axis indicates time. In FIG. 17, time t0 is the time when the DC power supply is turned on, time t1 is the time when the control unit 304 is started, time t2 is the time when the control of turning on the inrush relay 201 is completed, and time t3 is the time when the inverter 400 starts outputting. In FIG. 17, the dashed line indicates voltage Vr, and the solid line indicates voltage Vcg. In normal operation, when the DC power supply is turned on at time t0, a transformer that generates a voltage to be supplied to each circuit including the fault detection circuit 103 is started, and each control power supply is generated. Then, at time t1, the control unit 304 is started, and the bus voltage becomes constant. Since there is no charge in the smoothing capacitor 101 between time t0 and time t1, a large charging current flows through the inrush resistor 200. After time t1, although there is a load from the control unit 304, unlike AC power supply, the smoothing capacitor 101 is fully charged, so no charging current flows through the inrush resistor 200. At time t2, the inrush relay 201 turns on, clamping the potential of the inrush resistor 200 to 0 V. At time t3, the inverter 400 starts outputting, and a charging current due to the output of the inverter 400 starts to flow through the inrush relay 201.

[0042] Unlike AC input, power is supplied from the power supply to the control load without passing through the smoothing capacitor 101 even after time t1, so no charging current with a frequency six times that of the AC power supply flows. Therefore, the voltage Vr does not appear in the period from time t0 to time t2. After time t2, the inrush relay 201 turns on, so the voltage Vr does not appear even if the inverter 400 starts outputting.

[0043] Between time t0 and time t1, a large charging current flows through inrush resistor 200, and capacitor 503 is charged according to the voltage obtained by subtracting forward voltage VF of diode 502 of peak hold circuit 303 from the voltage division value of resistor voltage divider circuit 301 at that time. Therefore, at time t1, voltage Vcg that exceeds first judgment reference value Vlevel1 appears. After time t1, the charge of capacitor 503 is discharged via resistor 504, and voltage Vcg decreases over time to become equal to or less than first judgment reference value Vlevel1.

[0044] FIG. 18 is a diagram showing a voltage waveform when an open fault occurs in the inrush relay when a direct current step input occurs in the fault detection circuit according to the first modified example of the first embodiment. In FIG. 18, the vertical axis indicates voltage, and the horizontal axis indicates time. As in FIG. 17, time t0 in FIG. 18 is the time when the direct current power supply is turned on, time t1 is the time when the control unit 304 is started, time t2 is the time when the control to turn on the inrush relay 201 is completed, and time t3 is the time when the inverter 400 starts outputting. In FIG. 18, the dashed line indicates the voltage Vr, and the solid line indicates the voltage Vcg. When an open fault occurs in the inrush relay 201, even if the control to turn on the inrush relay 201 is performed, the inrush relay 201 is not turned on at time t2, but the charging current does not flow to the inrush resistor 200, so the voltage Vr does not appear. When the output of the inverter 400 is turned on at time t3, the charging current during operation flows to the inrush resistor 200, so the value of the voltage Vr increases. When the voltage Vr exceeds the first judgment reference value Vlevel1, the control unit 304 detects an open fault in the inrush relay 201. In this way, in the case of a DC step input, the voltage Vr hardly appears, so the method of detecting an open fault in the inrush relay 201 before the start of operation as shown in Fig. 11 cannot be used.

[0045] FIG. 19 is a diagram showing a voltage waveform when an inrush resistor breaks a fault when a DC step input of the fault detection circuit according to the first modified example of the first embodiment occurs. In FIG. 19, the vertical axis indicates voltage, and the horizontal axis indicates time. As in FIG. 17, time t0 in FIG. 19 is the time when the DC power supply is turned on, time t1 is the time when the control unit 304 is started, time t2 is the time when the control of turning on the inrush relay 201 is completed, and time t3 is the time when the inverter 400 starts outputting. In FIG. 19, the dashed line indicates the voltage Vr, and the solid line indicates the voltage Vcg. When the inrush resistor 200 breaks a fault, the charging path to the smoothing capacitor 101 is only the high-resistance resistor voltage divider circuit 301 from time t0 when the step-input DC power supply is turned on, so that the voltage across the inrush current prevention circuit 102 is high at least from time t1 to time 3. That is, when the inrush resistor 200 has an open circuit fault, the voltage Vr exceeds the first judgment reference value Vlevel1 from time t1 to at least time t3. The control unit 304 detects the open circuit fault of the inrush resistor 200 when the voltage Vr continues to have a constant value exceeding the first judgment reference value Vlevel1 for a first time period determined in advance from time t1. The set value of the first time period may be set in advance according to the device and system used by the user. Note that, when the inrush relay 201 is turned on while the inrush resistor 200 has an open circuit fault, a large current flows through the smoothing capacitor 101. Therefore, the control unit 304 detects the open circuit fault of the inrush resistor 200 before the control to turn on the inrush relay 201 is completed at time t2. Therefore, in actual control, the inrush relay 201 is not turned on even at time t2 when the control to turn on the inrush relay 201 is completed.

[0046] FIG. 20 is a diagram showing a voltage waveform when a short circuit occurs in the inrush relay when a DC step input is input to the fault detection circuit according to the first modified example of the first embodiment. In FIG. 20, the vertical axis indicates voltage, and the horizontal axis indicates time. As in FIG. 17, time t0 in FIG. 20 is the time when the DC power supply is turned on, time t1 is the time when the control unit 304 is started, time t2 is the time when the control for turning on the inrush relay 201 is completed, and time t3 is the time when the inverter 400 starts outputting. In FIG. 20, the dashed line indicates the voltage Vr, and the solid line indicates the voltage Vcg. When a short circuit occurs in the inrush relay 201, no charge / discharge current flows through the inrush resistor 200 from time t0 when the step input DC power supply is turned on to time t2 when the inrush relay 201 is turned on. That is, even at time t1 when the control unit 304 is started, the voltage Vcg and the voltage Vr are equal to or lower than the second judgment reference value Vlevel2. The control unit 304 detects a short circuit failure of the inrush relay 201 when the voltage Vcg and the voltage Vr are equal to or lower than the second judgment reference value Vlevel2 for a predetermined second time or more from the time t1. The set value of the second time may be preset according to the device and system used by the user.

[0047] FIG. 21 is a diagram showing a voltage waveform during normal operation of the fault detection circuit according to the first modified example of the first embodiment when a DC lamp input is applied. In FIG. 21, the vertical axis indicates voltage, and the horizontal axis indicates time. In FIG. 21, time t0 is the time when the DC power supply is turned on, time t1 is the time when the control unit 304 is started, time t2 is the time when the control for turning on the inrush relay 201 is started, time t3 is the time when the control for turning on the inrush relay 201 is completed, time t4 is the time when the bus voltage becomes a constant value, and time t5 is the time when the inverter 400 starts outputting. In FIG. 21, the dashed line indicates the voltage Vr, and the solid line indicates the voltage Vcg. During normal operation, when the DC lamp input is started at time t0, a transformer that generates a voltage to be supplied to each circuit including the fault detection circuit 103 is started, and each control power supply is generated. Thereafter, the control unit 304 is started at time t1. Since the DC input from the DC power supply is a lamp input, no large inrush current flows through the inrush resistor 200. Furthermore, after time t1, a charging current flows through the inrush resistor 200 via the smoothing capacitor 101. Thereafter, when the inrush relay 201 is turned on at time t3, the charging current stops flowing through the inrush resistor 200. When the inverter output starts at time t5, a charging current due to the output of the inverter 400 starts flowing through the inrush relay 201.

[0048] FIG. 22 is a diagram showing a voltage waveform when an open fault occurs in the inrush relay when a direct current lamp is input to the fault detection circuit according to the first modified example of the first embodiment. In FIG. 22, the vertical axis indicates voltage, and the horizontal axis indicates time. As in FIG. 21, time t0 in FIG. 22 is the time when the DC power supply is turned on, time t1 is the time when the control unit 304 is started, time t2 is the time when the control to turn on the inrush relay 201 is started, time t3 is the time when the control to turn on the inrush relay 201 is completed, time t4 is the time when the bus voltage becomes a constant value, and time t5 is the time when the inverter 400 starts outputting. In FIG. 22, the dashed line indicates the voltage Vr, and the solid line indicates the voltage Vcg. When an open fault occurs in the inrush relay 201, the inrush relay 201 is not turned on at time t3, so the charging current continues to flow through the inrush resistor 200 until the bus voltage becomes a constant value at time t4. Therefore, during the period from time t1 to time t4, a constant voltage Vr continues to appear. After time t4, the charging current stops flowing through the inrush resistor 200, so the voltage Vr gradually drops and disappears. When the inverter output is turned on at time t5, the charging current during operation flows through the inrush resistor 200, so the voltage Vr increases. When the voltage Vr exceeds the first judgment reference value Vlevel1, the control unit 304 detects an open fault in the inrush relay 201. In the case of an open fault in the inrush relay 201, the voltage Vcg hardly appears after time t0, so the method of detecting an open fault in the inrush relay 201 before the start of operation as shown in FIG. 11 cannot be used.

[0049] Fig. 23 is a diagram showing a voltage waveform at the time of a breakage fault in an inrush resistor when a direct current lamp is input to the fault detection circuit according to the first modified example of the first embodiment. In Fig. 23, the vertical axis indicates voltage, and the horizontal axis indicates time. As in Fig. 21, time t0 in Fig. 23 is the time when the direct current power supply is turned on, time t1 is the time when the control unit 304 is started, time t2 is the time when the control to turn on the inrush relay 201 is started, time t3 is the time when the control to turn on the inrush relay 201 is completed, time t4 is the time when the bus voltage becomes a constant value, and time t5 is the time when the inverter 400 starts outputting. In Fig. 23, the dashed line indicates the voltage Vr, and the solid line indicates the voltage Vcg. When the inrush resistor 200 has a disconnection fault, the charging path to the smoothing capacitor 101 is only the high-resistance resistor voltage divider circuit 301 from time t0 when the DC lamp input from the DC power source starts, so the voltage across the inrush current prevention circuit 102 becomes high at least from time 1 to time t5. In other words, when the inrush resistor 200 has a disconnection fault, the voltages Vr and Vcg exceed the first judgment reference value Vlevel1 from time t1 to at least time t5. The control unit 304 detects the disconnection fault of the inrush resistor 200 when the voltages Vr and Vcg continue to exceed the judgment reference value Vlevel1 for a first time period determined in advance from time t1. The set value of the first time period may be preset according to the device and system used by the user. If the inrush relay 201 is turned on while the inrush resistor 200 has an open circuit fault, a large current flows through the smoothing capacitor 101, so the control unit 304 detects the open circuit fault of the inrush resistor 200 before the control of turning on the inrush relay 201 is completed at time t3. Therefore, in actual control, the inrush relay 201 is not turned on even at time t3 when the control of turning on the inrush relay 201 is completed. Furthermore, the voltage Vcg continues to rise until the bus voltage reaches a constant value at time t4.

[0050] FIG. 24 is a diagram showing a voltage waveform when a short circuit occurs in the inrush relay when a DC ramp input of the fault detection circuit according to the first modified example of the first embodiment occurs. In FIG. 24, the vertical axis indicates voltage, and the horizontal axis indicates time. As in FIG. 21, time t0 in FIG. 24 is the time when the DC power supply is turned on, time t1 is the time when the control unit 304 is started, time t2 is the time when the control to turn on the inrush relay 201 is started, time t3 is the time when the control to turn on the inrush relay 201 is completed, time t4 is the time when the bus voltage becomes a constant value, and time t5 is the time when the inverter 400 starts outputting. In FIG. 24, the dashed line indicates the voltage Vr, and the solid line indicates the voltage Vcg. When a short circuit occurs in the inrush relay 201, no charge / discharge current flows through the inrush resistor 200 from time t0 when the DC ramp input from the DC power supply starts to time t3 when the inrush relay 201 turns on. That is, the voltages Vcg and Vr become equal to or lower than the second judgment reference value Vlevel2 at the timing of time t1 when the control unit 304 is started up. The control unit 304 detects a short circuit fault of the inrush relay 201 when the voltages Vcg and Vr are equal to or lower than the second judgment reference value Vlevel2 for a predetermined second time or more from time t1. Furthermore, by setting the second time in the same manner as in FIG. 12 described above, detection of a short circuit fault of the inrush relay 201 can be realized without any problem. Note that the set value of the second time may be set in advance according to the device and system used by the user.

[0051] With single-phase AC, the operation is the same as with three-phase AC except when the inrush resistor 200 has a breakage fault, so only the operation when the inrush resistor 200 has a breakage fault will be described here.

[0052] FIG. 25 is a diagram showing a voltage waveform when a breakage fault occurs in the inrush resistor when a single-phase AC is input to the fault detection circuit according to the first modified example of the first embodiment. In FIG. 25, the vertical axis indicates voltage, and the horizontal axis indicates time. In FIG. 25, time t0 is the time when the single-phase AC power supply is turned on, time t1 is the time when the control unit 304 is started, time t2 is the time when the control to turn on the inrush relay 201 is completed, and time t3 is the time when the inverter 400 starts outputting. In FIG. 25, the dashed line indicates voltage Vr, and the solid line indicates voltage Vcg. When a breakage fault occurs in the inrush resistor 200 of the three-phase AC, the charging path to the smoothing capacitor 101 is only the high-resistance resistor voltage dividing circuit 301 after the time t0 when the power is turned on, so that the voltage across the inrush current prevention circuit 102 is high at least from time t1 to time t3. Therefore, when the inrush resistor 200 has an open circuit fault, the voltage Vr exceeds the first judgment reference value Vlevel1 after time t1. However, in the case of single-phase AC, the voltage Vr also drops when the power supply voltage drops to near 0V. Therefore, there is a time when the voltage Vr is equal to or lower than the first judgment reference value Vlevel1, and there is a risk that the open circuit fault of the inrush resistor 200 cannot be detected. If the open circuit fault of the inrush resistor 200 cannot be detected and the inrush relay 201 is turned on, the charging path will be in a state where only the inrush relay 201 and the smoothing capacitor 101, which is hardly charged, exist, and an excessive charging current will flow. Therefore, if the ratio of the time during which the voltage Vr exceeds the first judgment reference value Vlevel1 until the inrush relay 201 is turned on is equal to or higher than a preset value, the control unit 304 detects the open circuit fault of the inrush resistor 200. If the inrush relay 201 is turned on while the inrush resistor 200 has an open circuit fault, a large current flows through the smoothing capacitor 101, so the control unit 304 detects the open circuit fault of the inrush resistor 200 before the control to turn on the inrush relay 201 is completed at time t2. For this reason, in actual control, the inrush relay 201 is not turned on even at time t2 when the control to turn on the inrush relay 201 is completed.

[0053] The operation of the inrush resistor 200 at the time of a breakage fault is the same whether the single-phase AC is step-input or ramp-input. Therefore, the input method of the single-phase AC may be either step-input or ramp-input.

[0054] The set value of the percentage of time during which the voltage Vr exceeds the first judgment reference value Vlevel1 may be set according to the environmental conditions of the device and system used by the user. If the input section of the inverter 400 has a general circuit configuration, the set value of the percentage of time during which the voltage Vr exceeds the first judgment reference value Vlevel1 can be uniquely determined mainly according to the input frequency of the single-phase AC power source. In this way, by setting a set value for the percentage of time during which the voltage Vr exceeds the first judgment reference value Vlevel1 in addition to the first judgment reference value Vlevel1, it becomes possible to detect an open circuit fault in the inrush resistor 200 without any problems.

[0055] As described above, the detection of a short circuit fault of the inrush relay 201 and the detection of an open circuit fault of the inrush relay 201 are similar to those in the case of three-phase AC. That is, the control unit 304 detects an open circuit fault of the inrush relay 201 when the voltage Vr exceeds the second judgment reference value Vlevel2 for a predetermined first time or more after the voltage Vcg drops to or below the second judgment reference value Vlevel2. The control unit 304 also detects a short circuit fault of the inrush relay 201 when the voltage Vr and the voltage Vcg are equal to or lower than the second judgment reference value Vlevel2 for a predetermined second time or more after the control unit 304 is started up.

[0056] In this way, the fault detection circuit 103 according to the first embodiment uses two voltage signals, namely, the voltage Vr output by the amplifier circuit 302 and the voltage Vcg output by the peak hold circuit 303, to detect three abnormality modes, namely, an open fault in the inrush resistor 200 of the inrush current prevention circuit 102, an open fault in the inrush relay 201, and a short fault in the inrush relay 201. Moreover, the fault detection circuit 103 according to the modification of the first embodiment can detect the above-mentioned three abnormality modes with high accuracy by setting two determination reference values ​​that are thresholds for determining an abnormality.

[0057] Embodiment 2 FIG. 26 is a diagram showing the configuration of a drive circuit including a fault detection circuit according to the second embodiment. In the drive circuit 800 according to the second embodiment, an inrush current prevention circuit 102 has two inrush relays 2011, 2012 connected in parallel. The fault detection circuit 103 includes a plurality of thermistors 6001, 6002 each installed around the inrush relays 2011, 2012 connected in parallel, a differential amplifier 601 that amplifies a voltage corresponding to a temperature detection value output by the thermistors 6001, 6002, and a diode 602 that couples the output voltage amplified by the differential amplifier 601. Hereinafter, all the thermistors 6001, 6002 are collectively referred to as the thermistor 600. Also, all the inrush relays 2011, 2012 are collectively referred to as the inrush relay 201. The thermistor 600 detects the temperature of the inrush relays 2011, 2012. In order to avoid adverse effects on the temperature detection accuracy of the inrush relays 2011 and 2012, heat generating components that generate a large amount of heat are not placed around the thermistor 600.

[0058] Next, we will explain the signal processing of the temperature detected by thermistor 600. First, the output voltage corresponding to the temperature detection value of thermistor 600 is amplified by differential amplifier 601. The amplified output voltage is coupled via diode 602. This makes it possible to extract the difference voltage of the temperature detection voltage of thermistor 600 as an output.

[0059] The value of the differential voltage output by the diode 602 indicates the temperature difference between thermistors 6001 and 6002. By inputting this output to the control unit 304 in parallel with the voltage Vr of the amplifier circuit 302 of the first embodiment, it is possible to detect that an open fault has occurred in either of the inrush relays 2011 and 2012 connected in parallel when the voltage Vr reaches a certain level or higher.

[0060] During normal operation, the magnitude of the current flowing through each thermistor 600 installed around the inrush relay 201 is approximately the same, so the temperatures of the thermistors 600 are approximately the same. Therefore, the change in resistance value due to temperature change of the thermistors 600 is also approximately the same, and the output voltage is also the same. Then, the difference is output as voltage Vr by the differential amplifier 601 and diode 602, so that during normal operation when there is no temperature difference between the thermistors 600, the output of the differential amplifier 601 is approximately 0V.

[0061] When any of the inrush relays 201 has an open fault, current is concentrated in the normally operating inrush relay 201, causing the temperature around the normally operating inrush relay 201 to rise. Since no current flows through the faulty inrush relay 201, there is almost no change in temperature around the faulty inrush relay 201. This causes a difference in the change in resistance value of the thermistor 600, which changes the output voltage, and this can be output as voltage Vr by the differential amplifier 601 and diode 602. When the voltage Vr exceeds a certain value during inverter operation, the control unit 304 detects that any of the parallel-connected inrush relays 201 has an open fault.

[0062] The reference value for the voltage Vr indicating an open fault may be determined according to a user's desired degree of tolerance for deterioration of the inrush relay 201. The degree of tolerance for deterioration of the inrush relay 201 corresponds to the temperature difference between the inrush relays 201 connected in parallel.

[0063] As an example, if the allowable temperature difference of the inrush relays 201 in the inverter 400 system is set to 15° C. between parallel connections, and the variations in the constants of the thermistor 600, the diode 602, and the step-down resistors (not shown) mounted in the circuit are taken into consideration, the reference value for the voltage Vr is Vr=1.0 V. In other words, in the above case, if Vr exceeds 1.0 V, it indicates that one of the parallel-connected inrush relays 201 is in an open-circuit fault state.

[0064] 26, only the maximum combination of differential voltages is output according to the temperature difference, so it is not possible to identify which inrush relay 201 has an open fault. For this reason, if multiple terminals are provided in the control unit 304 and multiple voltages Vr can be output from the differential amplifier 601, it is possible to detect the temperature difference of each inrush relay 201. With such a configuration, it is possible to identify the inrush relay 201 that has an open fault. In other words, by providing the control unit 304 with multiple terminals for detecting open faults in the inrush relays 201, it is possible to improve the efficiency of work, for example, when replacing a faulty part during maintenance.

[0065] 27 is a diagram showing a drive circuit including a fault detection circuit according to a first modification of the second embodiment. Only the inrush current prevention circuit 102 and the fault detection circuit 103 are shown, and the other parts are omitted. Also, of the fault detection circuit 103, the resistive voltage dividing circuit 301, the amplifier circuit 302, and the control unit 304 are omitted. In the inrush current prevention circuit 102 according to the first modification of the second embodiment, the number of parallel connections of the inrush relays 201 is n, and the inrush relays 2011 to 201 n The fault detection circuit 103 differs from the inrush current prevention circuit 102 according to the second embodiment in that it includes a thermistor 6001 to a thermistor 600. n By increasing the number of parallel connections, it is possible to realize a configuration of the inrush relay 201 that can be mounted on a large-capacity inverter 400. Therefore, it is possible to detect open faults in the inrush relays 201 connected in parallel in a wide range of inverter 400 capacity classes, and it is possible to achieve both functional safety on the user side and cost reduction on the side of the manufacturer of the inverter 400, etc. Also, even if the number of parallel connections of the inrush relays 201 is increased to three or more, the above-mentioned improvement effect on maintainability can be obtained by adding a terminal for detecting open faults in the control unit 304.

[0066] FIG. 28 is a diagram showing an example of a temperature simulation result using the fault detection circuit according to the second embodiment. The temperature simulation result shown in FIG. 28 is a result of a temperature simulation performed using Femtet (registered trademark) manufactured by Murata Software Co., Ltd. Panasonic relays with model number ALFG2PF18 C01L were used as the inrush relays 2011 and 2012. The thermistors 6001 and 6002 were placed at a position 5 mm away from the large current plate metal portion of each of the inrush relays 2011 and 2012 that generates the most heat. The temperature simulation conditions were that the contact resistance of the inrush relays 2011 and 2012 was 2 mΩ, and a current of 33 A was passed through the inrush relays 2011 and 2012 on one side. As a result, the temperature of the thermistor 6001 around the normal inrush relay 2011 rose by 18.3° C., and the temperature of the thermistor 6002 around the inrush relay 2012 that had an open fault rose by 3.2° C. The temperature difference between the two thermistors 6001, 6002 is 15.1° C., and the voltage Vr exceeds 1.0 V, making it possible to detect that one of the inrush relays 2011, 2012 has an open fault.

[0067] FIG. 29 is a diagram showing an example of a temperature simulation result using a fault detection circuit according to a first modified example of the second embodiment. In this example, a fault detection circuit 103 is used to detect a fault in an inrush current prevention circuit 102 having three inrush relays 2011, 2012, and 2013. The temperature simulation result shown in FIG. 29 is a temperature simulation result performed using Femtet (registered trademark) manufactured by Murata Software Co., Ltd. The inrush relays 2011, 2012, and 2013 were Panasonic relays with model number ALFG2PF18 C01L. The thermistors 6001, 6002, and 6003 were placed at a position 5 mm away from the large current sheet metal portion that generates the most heat in each of the inrush relays 2011, 2012, and 2013. The temperature simulation conditions were that the contact resistance of the inrush relays 2011, 2012, and 2013 was 2 mΩ, and a current of 33 A was passed through the inrush relays 2011, 2012, and 2013 on one side. As a result, the thermistor 6002 around the normal inrush relay 2012 rose by 18.2°C, the thermistor 6001 around the inrush relay 2011 that had an open fault rose by 3.0°C, and the thermistor 6003 around the inrush relay 2013 that had also had an open fault rose by 3.5°C. The maximum temperature difference of the three thermistors 6001, 6002, and 6003 is the temperature difference between the thermistor 6002 installed around the inrush relay 2012 and the thermistor 6001 installed around the inrush relay 2011, and the temperature difference between these two thermistors 6001 and 6002 is 15.2°C, and the voltage Vr exceeds 1.0V. Therefore, the control unit 304 can detect that any one of the inrush relays 2011, 2012, and 2013 has an open fault.

[0068] An example of a temperature simulation result using the fault detection circuit 103 of the second embodiment and an example of a temperature simulation result using the fault detection circuit 103 according to the first modified example of the second embodiment have been described above. However, if the positional relationship between the thermistor 600 and the inrush relay 201 is changed, it affects the heat transfer of the inrush relay 201. When the positional relationship between the thermistor 600 and the inrush relay 201 is changed due to design constraints, the allowable temperature difference between parallel inrush relays (=15° C.) can be maintained by suppressing the constant variation by changing the components or by changing the reference value of the voltage Vr. In addition, if the inrush relays 2011, 2012, and 2013 are changed to different components, the structure of the internal wiring changes, and therefore the heat transfer to the thermistor 600 also changes. The change of the inrush relays 2011, 2012, and 2013 is also adjusted by suppressing the constant variation by changing the components described above or by changing the reference value of the voltage Vr.

[0069] As described above, a thermistor 600 is installed around the inrush relay 201, the signal is amplified by a differential amplifier 601, and coupled via a diode 602 to output a differential voltage that serves as the temperature detection voltage for the inrush relay 201. By inputting this output voltage in parallel to the voltage Vr output by the amplifier circuit 302, the control unit 304 receives a signal, making it possible to detect that any of the inrush relays 201 is abnormal.

[0070] Next, a hardware configuration of the control unit 304 will be described. Fig. 30 is a diagram showing an example of a hardware configuration realizing the control unit of the fault detection circuit according to the first and second embodiments. The control unit 304 is realized as a computer system by a processing circuit including a processor 91 that executes various processes, a memory 92 that is a main memory, and a storage device 93 that stores information.

[0071] The processor 91 may be a calculation means such as an arithmetic device, a microprocessor, a microcomputer, a CPU (Central Processing Unit), or a DSP (Digital Signal Processor). The memory 92 may be a non-volatile or volatile semiconductor memory such as a RAM (Random Access Memory), a ROM (Read Only Memory), a flash memory, an EPROM (Erasable Programmable Read Only Memory), or an EEPROM (Electrically Erasable Programmable Read Only Memory). The storage device 93 stores a program for executing a process for detecting a fault in the inrush resistor 200 and the inrush relay 201. The processor 91 reads the program stored in the storage device 93 into the memory 92 and executes it. The processor 91 reads the program stored in the storage device 93 into the memory 92 and executes it, thereby realizing the function of the control unit 304.

[0072] The configurations shown in the above embodiments are merely examples of the contents, and may be combined with other known technologies. Parts of the configurations may be omitted or modified without departing from the spirit of the invention. [Explanation of symbols]

[0073] 10 AC power supply, 91 processor, 92 memory, 93 storage device, 100 rectifier circuit, 101 smoothing capacitor, 102 inrush current prevention circuit, 103 fault detection circuit, 200 inrush resistor, 201, 2011, 2012, 2013, 201 n Inrush relay, 301, resistive voltage divider circuit, 302, amplifier circuit, 303, peak hold circuit, 304, control unit, 400, inverter, 401, amplifier, 402, 403, 504, 903, 904, 905, 906, resistor, 404, 502, 602, diode, 405, positive electrode line, 406, negative electrode line, 501, peak hold unit, 503, capacitor, 600, 6001, 6002, 6003, 600 nThermistor, 601 differential amplifier, 700 inverter system, 800 drive circuit, 900 overvoltage protection circuit, 901 first bipolar transistor, 902 second bipolar transistor.

Claims

1. A fault detection circuit for detecting an abnormality in an inrush current prevention circuit including an inrush resistor and an inrush relay arranged in parallel, a resistor voltage divider circuit that divides a voltage across the inrush current prevention circuit; an amplifier circuit that amplifies a difference between the voltages divided by the resistive voltage divider circuit; a peak hold circuit for temporarily holding a peak of the voltage divided by the resistive voltage divider circuit; a control unit that detects an open circuit fault of the inrush resistor, a short circuit fault of the inrush relay, and an open circuit fault of the inrush relay based on a comparison result between the voltage output by the amplifier circuit and the voltage output by the peak hold circuit and a preset reference value for the voltage output by the amplifier circuit and the voltage output by the peak hold circuit; Equipped with The fault detection circuit, wherein the amplifier circuit and the peak hold circuit are connected in parallel between the resistive voltage divider circuit and the control unit.

2. The voltage applied to the resistor voltage divider circuit is a voltage obtained by rectifying a three-phase AC voltage input in a stepwise manner, The judgment reference value is preset, The control unit is After the control unit is started, when the voltage output by the amplifier circuit continues to have a constant value exceeding the judgment reference value, an open circuit fault of the inrush resistor is detected; detecting an open fault in the inrush relay when a voltage output from the amplifier circuit exceeds the judgment reference value after the control for turning on the inrush relay is completed; 2. The fault detection circuit according to claim 1, wherein a short fault of the inrush relay is detected when the voltage output by the peak hold circuit does not exceed the judgment reference value until the control of turning on the inrush relay is completed after the control unit is started.

3. The voltage applied to the resistor voltage divider circuit is a voltage obtained by rectifying a three-phase AC voltage input in a stepwise manner, a first judgment reference value and a second judgment reference value smaller than the first judgment reference value are preset for the voltage output by the amplifier circuit and the voltage output by the peak hold circuit; The control unit is After the control unit is started, when the voltage output by the amplifier circuit continues to have a constant value exceeding the first judgment reference value, an open circuit fault of the inrush resistor is detected; detecting an open fault of the inrush relay when a voltage output by the amplifier circuit exceeds the second judgment reference value for a predetermined period of time or more after the voltage output by the peak hold circuit falls below the second judgment reference value; 2. The fault detection circuit according to claim 1, further comprising: a detection circuit for detecting a short circuit fault in the inrush relay when the voltage output from the amplifier circuit and the voltage output from the peak hold circuit do not exceed the second judgment reference value until the time when the control for turning on the inrush relay is completed after the control unit is started.

4. The voltage applied to the resistor voltage divider circuit is a voltage obtained by rectifying a three-phase AC voltage input to the lamp, a first judgment reference value and a second judgment reference value smaller than the first judgment reference value are preset for the voltage output by the amplifier circuit and the voltage output by the peak hold circuit; The control unit is detects an open circuit failure of the inrush resistor when a voltage output from the amplifier circuit and a voltage output from the peak hold circuit continue to have values ​​exceeding the first judgment reference value for a predetermined first time period after startup of the control unit, detecting an open fault in the inrush relay when a voltage output from the amplifier circuit exceeds the first determination reference value after control for turning on the inrush relay is completed; 2. The fault detection circuit according to claim 1, characterized in that a short circuit fault in the inrush relay is detected when the voltage output by the amplifier circuit and the voltage output by the peak hold circuit are equal to or lower than the second judgment reference value for a predetermined second time or more after startup of the control unit.

5. the voltage applied to the resistor voltage divider circuit is a step-input DC voltage, a first judgment reference value and a second judgment reference value smaller than the first judgment reference value are preset for the voltage output by the amplifier circuit and the voltage output by the peak hold circuit, The control unit is detects an open circuit failure of the inrush resistor when a voltage output by the amplifier circuit continues to have a constant value exceeding the first judgment reference value for a predetermined first time period after the control unit is started, detecting an open fault in the inrush relay when a voltage output from the amplifier circuit exceeds the first determination reference value after control for turning on the inrush relay is completed; 2. The fault detection circuit according to claim 1, characterized in that a short circuit fault in the inrush relay is detected when the voltage output by the amplifier circuit and the voltage output by the peak hold circuit are equal to or lower than the second judgment reference value for a predetermined second time or more after startup of the control unit.

6. The voltage applied to the resistor voltage divider circuit is a DC voltage input to the lamp, a first judgment reference value and a second judgment reference value smaller than the first judgment reference value are preset for the voltage output by the amplifier circuit and the voltage output by the peak hold circuit, The control unit is detects an open circuit failure of the inrush resistor when a voltage output from the amplifier circuit and a voltage output from the peak hold circuit maintain a constant value exceeding the first judgment reference value for a first period of time that is preset after the control unit is started, detecting an open fault in the inrush relay when a voltage output from the amplifier circuit exceeds the first determination reference value after control for turning on the inrush relay is completed; 2. The fault detection circuit according to claim 1, characterized in that a short circuit fault in the inrush relay is detected when the voltage output by the amplifier circuit and the voltage output by the peak hold circuit are equal to or lower than the second judgment reference value for a predetermined second time or more after startup of the control unit.

7. The voltage applied to the resistive voltage divider circuit is a voltage obtained by rectifying a single-phase AC voltage, a first judgment reference value and a second judgment reference value smaller than the first judgment reference value are preset for the voltage output by the amplifier circuit and the voltage output by the peak hold circuit, The control unit is detects an open circuit failure of the inrush resistor when a rate at which the voltage output by the amplifier circuit exceeds the first judgment reference value is equal to or greater than a preset value during a period from when the control unit is started until when control for turning on the inrush relay is completed; detecting an open fault of the inrush relay when a voltage output from the amplifier circuit exceeds the second judgment reference value for a predetermined first time or more after the voltage output from the peak hold circuit falls to or below the second judgment reference value; 2. The fault detection circuit according to claim 1, characterized in that a short fault of the inrush relay is detected when the voltage output by the amplifier circuit and the voltage output by the peak hold circuit are equal to or lower than the second judgment reference value for a predetermined second time or more after startup of the control unit.

8. A fault detection circuit for detecting an abnormality in an inrush current prevention circuit including an inrush relay arranged in parallel, a resistor voltage divider circuit that divides a voltage across the inrush current prevention circuit; an amplifier circuit that amplifies a difference between the voltages divided by the resistive voltage divider circuit; a thermistor disposed around each of the inrush relays to detect a temperature of each of the inrush relays; a differential amplifier connected in series to each of the thermistors and configured to output the largest difference among a plurality of pairs of differences based on the detection results of the thermistors; and a control unit that detects an open fault in the inrush relay whose temperature is highest when the voltage output by the amplifier circuit after control to turn on the inrush relay is completed exceeds a preset reference value for the voltage output by the amplifier circuit.

9. A drive circuit including a smoothing capacitor for smoothing a pulsating current, an inrush current prevention circuit for preventing a large current from flowing through the smoothing capacitor due to an inrush current, and the fault detection circuit according to any one of claims 1 to 8; an inverter that operates by being supplied with power whose voltage has been smoothed by the smoothing capacitor.

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