Method for manufacturing a semiconductor device, method for manufacturing a device equipped with a semiconductor device, semiconductor device, and device equipped with a semiconductor device

Abstract

Provided are: a method for manufacturing a semiconductor device which prevents die shift in semiconductor packaging; a method for manufacturing a device provided with a semiconductor device; a semiconductor device; and a device provided with a semiconductor device. The method for manufacturing a semiconductor device provided with a semiconductor chip includes: a step for disposing a semiconductor chip in a peeled section provided on a substrate, so that an electrode of the semiconductor chip comes into contact with the peeled section; a step for forming an anchor section that defines the position of the semiconductor chip and that is flexible and freely bendable so as to cover the peeled section and the semiconductor chip; a step for forming a sealing part that comes into contact with the anchor section and that is flexible and freely bendable; and a step for separating the peeled section and the substrate from the semiconductor chip and the anchor section, to expose the electrode of the semiconductor chip. The anchor section is formed by, at least, any one of a vapor phase deposition method, a spray coating method, and an inkjet method.

Description

[Technical field]

[0001] The present invention relates to a method for manufacturing a semiconductor device, a method for manufacturing a device equipped with a semiconductor device, a semiconductor device, and a device equipped with a semiconductor device. [Background technology]

[0002] In recent years, in the field of semiconductor packaging, FOWLP (Fan Out Wafer Level Packaging) is known as a technology that has become mainstream in mobile applications such as portable electronic devices such as smartphones (see, for example, Patent Document 1). In addition, technology that employs flexible displays is also known as a technology for mobile applications (see, for example, Patent Document 2), and among these, there are displays that can be freely bent. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] International Publication No. 2018 / 081705 [Patent Document 2] Patent Publication No. 2019-211778 Summary of the Invention [Problem to be solved by the invention]

[0004] However, in the method of embedding a semiconductor chip in a sealing resin in semiconductor packaging, there is a risk of a problem called die shift, in which the semiconductor chip moves due to the flow of the sealing resin, and the sealing resin hardens in a state where the semiconductor chip is displaced from the specified position, resulting in problems such as defective wiring to the semiconductor chip. Furthermore, in a product that can be bent such as a flexible display, there is a risk that the deviation from the specified position will be further increased by bending the display. [Means for solving the problem]

[0005] A method for manufacturing a semiconductor device according to the present invention comprises at least the following steps. A method for manufacturing a semiconductor device including a semiconductor chip, comprising: a step of placing a semiconductor chip such that electrodes of the semiconductor chip abut on a peeling portion provided on a substrate; forming an anchor portion that defines a position of the semiconductor chip and has flexibility so as to cover the peeling portion and the semiconductor chip; forming a sealing portion that is in contact with the anchor portion and has flexibility and can be bent; and separating the peeling portion and the substrate from the semiconductor chip and the anchor portion to expose the electrodes of the semiconductor chip. fruit, The anchor portion is any one of a combination of 4,4'-diaminodiphenylmethane and 4,4'-diphenylmethane diisocyanate, a combination of 1,9-diaminononane and 1,9-diisocyanatenonane, and a combination of 1,5-diaminopentane and 1,5-diisocyanatepentane. It is characterized by:

[0006] The method for manufacturing a device including a semiconductor device of the present invention includes the steps of: The method is characterized by including a step of fabricating a device by combining the semiconductor device fabricated by the above-mentioned method with other components.

[0007] The semiconductor device of the present invention has at least the following configuration. A semiconductor device including a semiconductor chip, A semiconductor chip having an electrode formed on one surface thereof; an anchor portion that covers a surface of the semiconductor chip other than the surface on which the electrodes are formed and has flexibility such that the anchor portion is freely bendable; a sealing portion that abuts against the anchor portion and has flexibility that allows the sealing portion to bend freely; and wiring connected to the electrodes of the semiconductor chip.

[0008] The present invention also provides an apparatus including the semiconductor device described above. [Brief description of the drawings]

[0009] [Figure 1]1 is a cross-sectional view showing an example of a semiconductor device including a semiconductor chip according to an embodiment of the present invention. [Diagram 2] 1 is a flowchart for explaining an example of a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Diagram 3] 1A and 1B are diagrams for explaining an example of a method for manufacturing a semiconductor device. (a) is a schematic cross-sectional view showing an example of a state in which a surface on which electrodes of a semiconductor chip are formed is placed so as to abut against a first peeling portion (Tape A) provided on a wafer (first substrate). (b) is a perspective view of (a). (c) is a schematic cross-sectional view showing an example of a state in which an anchor portion (anchor layer) has been formed. (d) is a perspective view of (c). [Figure 4] 1A and 1B are diagrams for explaining an example of a method for manufacturing a semiconductor device. (a) is a diagram showing an example of a state in which PDMS is formed on the anchor part (anchor layer) and a second release part (Tape B) and a second substrate are provided. (b) is a perspective view of (a). (c) is a diagram showing an example of a state in which the first release part and the first substrate are separated from the semiconductor chip and the anchor part (anchor layer) to expose the electrodes of the semiconductor chip. (d) is a perspective view of (c). [Diagram 5] 1A and 1B are diagrams for explaining an example of a method for manufacturing a semiconductor device, where (a) is a diagram showing an example of a state in which an SBL (buffer layer) is formed, (b) is a perspective view of (a), (c) is a diagram showing an example of a state in which a redistribution layer is formed, and (d) is a perspective view of (c). [Figure 6] 1A is a schematic cross-sectional view showing an example of a semiconductor device in which a second substrate and a second release portion are separated from PDMS, FIG. 1B is a perspective view of FIG. 1A, and FIG. 1C is a schematic view showing an example of a semiconductor device in a curved state. [Figure 7] Photographs for explaining the effect of the manufacturing method of the semiconductor device according to the embodiment of the present invention. (a) is a photograph showing an example of the position of the semiconductor chip when an anchor part (anchor layer) is provided in the semiconductor device according to the embodiment of the present invention. (b) is a photograph showing an example of die shift when no anchor part is used as a comparative example. [Figure 8] 1A is a schematic cross-sectional view illustrating an example of a mechanism for preventing misalignment of a semiconductor chip when an anchor portion is provided. FIG. 1A is a schematic cross-sectional view illustrating a state in which a semiconductor chip is placed on a first release portion, an anchor portion is formed, and PDMS is injected. FIG. 1B is a schematic cross-sectional view illustrating an example of gas removal and hardening of PDMS. FIG. 1C is a schematic cross-sectional view illustrating an example of thermal peeling. FIG. 1D is a schematic cross-sectional view illustrating an example of a state in which the first release portion and the like are separated from the semiconductor chip and the anchor layer. [Figure 9] 1A and 1B are diagrams showing an example of the mechanism of die shift when no anchor layer (anchor portion) is used as a comparative example. (a) is a schematic cross-sectional view of a state in which a semiconductor chip is placed on a first peeling portion and PDMS is injected. (b) is a schematic cross-sectional view for explaining an example of gas removal and hardening of PDMS. (c) is a schematic cross-sectional view for explaining an example of thermal peeling. (d) is a schematic cross-sectional view showing an example of a state in which the first peeling portion and the like are separated from the semiconductor chip and PDMS (sealing portion). [Figure 10] FIG. 1 is a diagram illustrating an example of an apparatus including a semiconductor device. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] A manufacturing method for a semiconductor device according to an embodiment of the present invention enables the production of highly integrated semiconductor packaging by forming an anchor portion (anchor layer, etc.) that suppresses the movement of a semiconductor chip in semiconductor packaging. In detail, the method for manufacturing a semiconductor device includes the steps of: positioning a semiconductor chip so that electrodes of the semiconductor chip abut against a peel-off portion provided on a substrate; forming an anchor portion that defines the position of the semiconductor chip and has flexibility and bends freely so as to cover the peel-off portion and the semiconductor chip; forming a sealing portion that abuts against the anchor portion and has flexibility and bends freely; and separating the peel-off portion and the substrate from the semiconductor chip and the anchor portion to expose the electrodes of the semiconductor chip.

[0011] A method for manufacturing a device including the semiconductor device of the present invention includes a step of combining the semiconductor device manufactured by the above-mentioned method for manufacturing a semiconductor device with other components to manufacture a device.

[0012] In addition, a semiconductor device according to an embodiment of the present invention has a semiconductor chip having an electrode formed on one surface, an anchor portion that covers all surfaces of the semiconductor chip except the surface on which the electrode is formed and has flexibility and can be bent freely, a sealing portion that abuts the anchor portion and has flexibility and can be bent freely, and wiring connected to the electrode of the semiconductor chip. Moreover, the device according to the embodiment of the present invention includes a semiconductor device including a semiconductor chip.

[0013] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. The embodiment of the present invention includes the contents shown in the drawings, but is not limited thereto. In the following description of each drawing, parts common to parts already described will be given the same reference numerals, and some duplicated description will be omitted. In addition, the drawings are schematic, and the relationship between thickness and planar dimensions, the thickness ratio of each layer, etc. may differ from the actual ones. Furthermore, the drawings may include parts in which the relationship and ratio of dimensions differ from each other. In addition, the embodiments shown below are merely examples of methods for realizing the technical idea of ​​the present invention, and the technical idea of ​​the present invention does not limit the materials, shapes, structures, arrangements, etc. of the components to those described below. The technical idea of ​​the present invention can be modified in various ways within the technical scope described in the claims.

[0014] FIG. 1 is a cross-sectional view showing an example of a semiconductor device according to an embodiment of the present invention. The semiconductor device 100 includes a semiconductor chip 1, an anchor portion 14 (also called an anchor layer), a sealing portion 15, wiring 17, etc. In the example shown in Fig. 1, the semiconductor device 100 also includes a buffer layer 16 (also called a buffer portion).

[0015] The semiconductor chip 1 is an LED, a micro LED (for example, a substantially rectangular parallelepiped shape with a side length of about 1 μm to 200 μm), an integrated circuit, a semiconductor sensor, a capacitor, a transistor, a semiconductor sensor, or the like, and is formed in a chip shape. In the example shown in FIG. 1, the semiconductor chip 1 is formed in a substantially rectangular parallelepiped shape, and electrodes 12 are formed on one surface.

[0016] The anchor portion 14 is formed so as to cover the surface of the semiconductor chip 1 other than the surface on which the electrodes 12 are formed.

[0017] In the example shown in FIG. 1, the sealing portion 15 is formed so as to abut against the anchor portion 14.

[0018] In the example shown in FIG. 1, a buffer layer 16 is formed on the upper part of the sealing portion 15 and on a part of the semiconductor chip 1. In addition, in the example shown in Figure 1, wiring 17 (rewiring layer) is formed on top of the buffer layer 16, and the wiring 17 is electrically connected to the electrode 12 of the semiconductor chip 1 through a via hole 16h formed in the buffer layer 16.

[0019] FIG. 2 is a flowchart for explaining an example of a method for manufacturing the semiconductor device 100 according to the embodiment of the present invention. An example of a method for manufacturing the semiconductor device 100 will be described with reference to the flowchart shown in Fig. 2 and Figs. 3 to 6. Hereinafter, a method for manufacturing a semiconductor device employing die-first / face-down FOWLP (Fan Out Wafer Level Packaging) as a mounting method for the semiconductor chip 1 will be described, but the present invention is not limited to this embodiment as long as die shift can be suppressed by forming an anchor part having flexibility that can be freely bent.

[0020] The manufacturing method of the semiconductor device 100 includes a step (ST1) of placing a semiconductor chip on a first peel-off portion provided on a first substrate, an anchor portion forming step (ST2), a sealing portion forming step, and a step (ST3) of placing the second peel-off portion and the second substrate, a step (ST4) of separating the first peel-off portion and the first substrate, a buffer layer forming step (ST5), a wiring forming step (ST6), and a step (ST7) of separating the second peel-off portion and the second substrate.

[0021] Specifically, in step ST1, as shown in Figures 3(a) and 3(b), a peeling portion 22 (first peeling portion) is formed on a substrate 21 (also called a first substrate or a first carrier) such as a silicon wafer. The peeling portion 22 is made of, for example, a functional adhesive member. The functional adhesive member is formed of a weakly adhesive adhesive (such as an adhesive tape that can be peeled off at high temperatures). Weak adhesion means that the peel strength decreases at a predetermined temperature or higher (for example, about 130°C (set temperature)). In this embodiment, a thermal peeling tape (Tape A) is used as the peeling portion 22. It is also possible to prepare a substrate 21 on which the peeling portion 22 is provided in advance. Next, the semiconductor chip 1 is placed at a predetermined position on the peeling portion 22. In detail, the semiconductor chip 1 is placed on the peeling portion 22 so that the electrodes 12 formed on one surface of the semiconductor chip 1 abut against the peeling portion 22. Examples of materials for forming the peeling portion 22 include photo-peeling materials such as UV peeling tape that can be peeled off by irradiation with UV light, peeling materials that can be peeled off using laser ablation such as an excimer laser below deep ultraviolet light, and peeling materials that can be peeled off by irradiation with laser light such as ultraviolet, visible, or near-infrared light. Also, the release portion 22 may not be of the tape type, but may be, for example, a spin-coated type thermal release material. The release portion 22 may also be a material that can be mechanically released using a tool such as a wedge. Moreover, the peelable portion 22 may be formed from a material that can be peeled off with a solvent. That is, the peeling portion 22 is formed from a material that can be peeled off by at least one of the following methods: thermal peeling, optical peeling (including laser), mechanical peeling (including peeling methods using a high-pressure jet, etc.), and solvent peeling.

[0022] In step ST2, as shown in Figures 3(c) and 3(d), anchor parts 14 are formed so as to cover the peeling portion 22 and the upper and side surfaces of the semiconductor chip 1. In detail, anchor parts 14 are formed so as to cover the portions of the semiconductor chip 1 other than the surface on which the electrodes 12 are formed. These anchor parts 14 determine the position of the semiconductor chip 1 so that the position of the semiconductor chip 1 does not shift. In this embodiment, even if the size of the semiconductor chip 1 is less than 1 mm, the provision of anchor parts 14 can suppress die shift.

[0023] The anchor portion 14 can be formed by, for example, either a vapor phase deposition method or a spray coating method, but any method may be used as long as it can be finished with flexibility.

[0024] Examples of materials for forming the anchor portion 14 include polyureas such as a combination of 4,4'-diaminodiphenylmethane and 4,4'-diphenylmethane diisocyanate, a combination of 1,9-diaminononane and 1,9-diisocyanatenonane, and a combination of 1,5-diaminopentane and 1,5-diisocyanatepentane. Parylene can also be used. The plasticity of these materials gives the anchor portion flexibility so that it can be bent freely.

[0025] The thickness of the anchor portion 14 may be any thickness that can suppress misalignment of the semiconductor chip 1 during the subsequent process of forming the sealing portion, and is, for example, 0.1 μm to 100 μm, preferably 0.5 μm to 10 μm, and optimally 1 μm to 3 μm. In this embodiment, an aromatic polyurea of ​​a combination of 4,4'-diaminodiphenylmethane and 4,4'-diphenylmethane diisocyanate is uniformly formed by deposition polymerization to cover the peeling portion 22 and the upper and side surfaces of the semiconductor chip 1, thereby forming an anchor portion 14 having a thickness of 1 μm. In another embodiment, an aliphatic polyurea such as a combination of 1,9-diaminononane and 1,9-diisocyanatenonane or a combination of 1,5-diaminopentane and 1,5-diisocyanatepentane can be obtained by deposition polymerization. In the case of aliphatic polyurea, if the substrate temperature is high, the residence time of the aliphatic monomer on the substrate is too short to cause a polymerization reaction, but if the substrate temperature is set to -20°C or lower, sufficient deposition is possible.

[0026] In step ST3, as shown in Figures 4(a) and 4(b), the process of forming the sealing portion 15 and arranging the peeling portion 23 (second peeling portion) and the substrate 24 (also called the second substrate or second carrier) is performed. In this embodiment, a liquid or semi-liquid resin (e.g., silicone rubber (PDMS: polydimethylsiloxane)) is applied onto the anchor portion 14 as a material for forming the sealing portion 15, and then a substrate 24 (second substrate) such as a silicon wafer having a peel-off portion 23 provided on its underside is placed on the sealing portion 15. For example, a thermal peeling tape (Tape B) was used as the peeling portion 23. This thermal peeling tape (Tape B) is one whose peel strength decreases at a predetermined temperature or higher (for example, about 150° C. (a set temperature higher than that of the peeling portion 22)).

[0027] Then, with the material (such as PDMS) for forming sealing portion 15 placed between substrate 21 and substrate 24, a vacuum device is used to degas (remove gas) PDMS at a predetermined vacuum level (e.g., 10 kPa) for a predetermined time (e.g., 30 minutes), and sealing portion 15 is formed by compression molding at a predetermined pressure (e.g., 0.7 MPa).

[0028] Next, in step ST4, the substrate 21 (first substrate) and the peeling portion 22 (first peeling portion) are separated from the semiconductor chip 1 and the anchor portion 14 to expose the electrodes 12 of the semiconductor chip 1, and then the substrate is inverted upside down as shown in Figures 4(c) and 4(d). In detail, the substrate 21 (first substrate) and the peeling portion 22 (first peeling portion) are heated at a predetermined temperature (about 130° C.) (for example, for two minutes) to separate them from the semiconductor chip 1 and the anchor portion 14.

[0029] 5(a) and 5(b), a thin buffer layer 16 (SBL: Stress Buffer Layer) is formed on the semiconductor chip 1 and the anchor portion 14. The buffer layer 16 can be formed by, for example, a vapor phase deposition method, a spin coating method, a spray coating method, or the like. An insulating material such as parylene can be used as a material for forming the buffer layer 16. Next, via holes 16h are formed in the buffer layer 16 by etching technology, laser processing technology, etc. The via holes 16h are formed above the electrodes 12 of the semiconductor chip 1.

[0030] In step ST6, as shown in Fig. 5(c) and Fig. 5(d), wiring 17 of a predetermined pattern is formed in the buffer layer 16. The wiring 17 is electrically connected to the electrodes 12 of the semiconductor chip 1 through via holes 16h. In detail, in this embodiment, the wiring 17 is formed into a predetermined wiring pattern from a metal material such as titanium or gold by physical vapor deposition technology, a photolithography process, wet etching, or the like.

[0031] Next, in step ST7, the peel-off portion 23 (second peel-off portion) and the substrate 24 (second substrate) shown in FIG. 5(c) are separated from the sealing portion 15 to produce the semiconductor device 100 as shown in FIG. 6(a) and FIG. 6(b). In detail, the substrate 24 (second substrate) and the peeling portion 23 (second peeling portion) are peeled off from the sealing portion 15 by heating them at a predetermined temperature (about 150° C.) (for example, for two minutes).

[0032] As shown in FIG. 6(a), the sealing portion 15 and the like are formed to have flexibility, so that the semiconductor device 100 is configured to be freely bendable.

[0033] Next, in step ST8, the above-mentioned semiconductor device 100 is combined with other components, such as various sensors, a drive unit, and a housing unit, to manufacture a device including the semiconductor device 100.

[0034] The inventors of the present application have actually fabricated a semiconductor device and confirmed the effect of the method for manufacturing a semiconductor device according to the embodiment of the present invention.

[0035] Fig. 7 is a photograph for explaining the effect of the manufacturing method of the semiconductor device according to the embodiment of the present invention. The manufacturing method used was die-first / face-down FOWLP. In detail, Fig. 7(a) is a photograph showing an example of the position of the semiconductor chip when an anchor portion (anchor layer) of the semiconductor device according to the embodiment of the present invention is provided. Fig. 7(b) is a photograph for explaining an example of die shift when no anchor portion is used as a comparative example. The die shift value was measured using a digital microscope after forming sealing portion 15 by compression molding PDMS, as shown in FIG. 7(a) and FIG. 7(b).

[0036] The viscosity of the PDMS precursor (liquid or semi-liquid material for the sealing portion 15) was 60 Pa·s, which is about 2 to 3 orders of magnitude lower than that of a typical rigid epoxy molding compound (EMC). The die shift value was measured at a distance of about 20 mm from the center of the wafer.

[0037] As shown in FIG. 7(a), on a peel-off portion (second peel-off portion) provided on a substrate (first substrate), an integrated circuit (size 2.5 mm / 2.5 mm / 400 μm: width / length / height) is arranged as semiconductor chip 1S, a capacitor (size 1000 μm / 500 μm / 500 μm: W / L / H) is arranged as semiconductor chip 1A, a near-infrared micro LED (size 340 μm / 340 μm / 270 μm: W / L / H) is arranged as semiconductor chip 1B, and a red micro LED (size 270 μm / 270 μm / 270 μm: W / L / H) is arranged as semiconductor chip 1C. In this embodiment, the semiconductor chip 1S is an integrated circuit (LSI) of a PPG sensor (optical heart rate sensor) including an LED driver, a photodiode, a memory circuit, and the like.

[0038] As shown in Figure 7(a), when an anchor portion (anchor layer) is provided, it was confirmed that the semiconductor chips 1S, 1A, 1B, and 1C are positioned in specified positions and that deviation from the specified positions is suppressed.

[0039] As shown in Fig. 7(b), in the comparative example where no anchor portion (anchor layer) was provided, the die shifts in the x-axis direction (left-right direction in Fig. 7(b)) and y-axis direction (up-down direction in Fig. 7(b)) of the semiconductor chip 1A (capacitor) were 125 μm and 930 μm, respectively. The die shifts of the semiconductor chip 1B (near-infrared micro LED) were 890 μm, and the die shifts of the semiconductor chip 1C (red micro LED) were 825 μm. This is because the adhesive strength (adhesive force: 0.215 N / mm) between the small-sized semiconductor chips 1A, 1B, and 1C and the peeled portion is very low. There are two reasons why a large die shift occurs. The first reason is that the flow of the resin, which is the material that forms the sealing part, is large, and a large shear force is applied to the side wall of the semiconductor chip. In particular, the semiconductor chip 1A (capacitor) does not have a protective wall surrounding it, and a large force acts on the thick die. Moreover, the semiconductor chips 1B and 1C (micro LEDs) are moved along the sidewall of the large-sized semiconductor chip 1S (LSI chip) by the flow of the resin fluid.

[0040] The second reason is due to bubbling during outgassing from the viscous PDMS (the material that forms the seal) and the interface between the die and the tape in vacuum.

[0041] 8(a) to 8(d) are diagrams for explaining an example of a mechanism for preventing misalignment of a semiconductor chip when anchor portions are provided (embodiment of the present invention). In detail, as shown in Fig. 8(a), a semiconductor chip 1 (such as a micro LED) is placed on a peeling portion 22 provided on a substrate (not shown), and an anchor portion 14 is formed. Then, liquid or semi-liquid PDMS is injected as a material for forming the sealing portion 15. Expandable particles 22p are contained in the peeling portion 22. Small bubbles 15b (gas) are contained in the PDMS of the sealing portion 15. Next, as shown in Fig. 8(b), a vacuum is created using a vacuum device, and the PDMS bubbles 15b (gas) expand and move upward. After the gas is removed, high pressure is applied to harden the PDMS in the sealing portion 15. As shown in Fig. 8(b), since anchor portions 14 are provided, the force of the PDMS fluid does not act on the semiconductor chip 1. Furthermore, even if the PDMS bubbles 15b (gas) expand, the force of the PDMS bubbles 15b (gas) does not act on the semiconductor chip 1 because anchor portions 14 are provided.

[0042] Next, as shown in Fig. 8(c), the substrate and the peeling portion 22 are heated to a predetermined temperature to expand the expandable particles 22p of the peeling portion 22, and as shown in Fig. 8(d), the peeling portion 22 (first peeling portion) and the like are separated (thermally peeled) from the semiconductor chip 1 and the anchor portion 14. Even if a force is applied to the semiconductor chip 1 from the expandable particles 22p of the peeling portion 22, the anchor portion 14 suppresses the semiconductor chip 1 from shifting from its specified position. By providing the anchor portion 14, the die shift is significantly improved to within 5 μm, so that, for example, a highly accurate mask alignment process becomes possible in wiring formation (RDL formation) by a post-process photolithography step.

[0043] As a comparative example, an example of the mechanism of die shift when no anchor layer (anchor portion) is used will be described with reference to FIGS. 9(a) to 9(d). As shown in FIG. 9(a), a semiconductor chip 1 (such as a micro LED) is placed on a peelable portion 22 provided on a substrate (not shown), and liquid or semi-liquid PDMS is injected as a material for forming a sealing portion 15.

[0044] As shown in Figure 9(b), a force F due to the flow of the PDMS fluid acts on the semiconductor chip 1, and when a vacuum is created using a vacuum device to remove the PDMS gas from the sealing portion 15, an upward force due to the expanded bubble 15b (gas) acts on the semiconductor chip 1, causing the semiconductor chip to shift from its specified position.

[0045] As shown in FIG. 9(c), when the substrate and the peeling portion 22 are heated to a predetermined temperature and the expandable particles 22p of the peeling portion 22 are expanded, a force is applied to the semiconductor chip 1 from the expandable particles 22p. Then, as shown in FIG. 9(d), when the peeled portion 22 (first peeled portion) and the like are separated from the semiconductor chip 1 and the sealing portion 15, the semiconductor chip 1 becomes displaced from the specified position.

[0046] FIG. 10 is a diagram for explaining an example of an apparatus including a semiconductor device. The inventor of the present application applied the semiconductor device according to the present invention to an optical heart rate measuring device (biometric measuring device) that can be attached to a nail. The optical heart rate measuring device shown in FIG. 10 includes a red micro LED, a near-infrared micro LED, a capacitor, and a PPG (Photoplethysmography) sensor chip. The PPG sensor chip is electrically connected to components of the optical heart rate measuring device, such as the red micro LED, the near-infrared micro LED, and the capacitor, via wiring (Fan-out RDL). The PPG sensor chip includes an LED driver, a light receiving unit (PD: Photodiode), and a PPG memory circuit that records a photoelectric volume pulse wave signal. The upper right part of FIG. 10 is a photograph showing an example of an optical heart rate measuring device (biometric measuring device) in a state where it is detachably attached to a nail with an adhesive or the like, and the left part of FIG. 10 is a photograph showing an enlarged view of the red micro LED and the near-infrared micro LED. This optical heart rate measuring device is attached to the nail and emits red and near-infrared light from a micro LED. The light reflected by the capillaries in the finger is received by the light receiving unit, and pulse waves and transcutaneous oxygen saturation (SpO2) can be monitored in real time through signal processing.

[0047] That is, according to the method for manufacturing a semiconductor device of the present invention, it is possible to fabricate a highly integrated, thin and freely bendable semiconductor device or bioinstrumentation device.

[0048] As described above, the manufacturing method of the semiconductor device 100 according to an embodiment of the present invention includes steps (ST1, ST2) of positioning the semiconductor chip 1 so that the electrodes 12 of the semiconductor chip 1 abut against the peel-off portion 22 (also referred to as the first peel-off portion or the first thermal peel-off portion) provided on the substrate 21 (also referred to as the first substrate), a step (ST3) of forming an anchor portion 14 (anchor layer) that determines the position of the semiconductor chip 1 so as to cover the peel-off portion 22 (first thermal peel-off portion) and the semiconductor chip 1, a step (ST4) of forming a sealing portion 15 (PDMS, etc.) that abuts against the anchor portion 14, and a step (ST6) of separating the peel-off portion 22 (first thermal peel-off portion) and the substrate 21 (first substrate) from the semiconductor chip 1 and the anchor portion 14 to expose the electrodes 12 of the semiconductor chip 1. Specifically, in step ST3, the anchor portions 14 are formed so as to cover the surfaces of the semiconductor chip 1 other than the surface on which the electrodes 12 are formed. Moreover, the manufacturing method of the semiconductor device 100 employs die-first / face-down FOWLP as the mounting method for the semiconductor chip 1. That is, in semiconductor packaging, by forming anchor portion 14 that determines the position of semiconductor chip 1 as described above, anchor portion 14 can suppress deviation of semiconductor chip 1 from the specified position, and a method for manufacturing a semiconductor device can be provided that produces a highly integrated semiconductor device 100 in which semiconductor chip 1 is positioned at the specified position with high precision. In other words, it is possible to provide a method for manufacturing a semiconductor device that prevents die shift during semiconductor packaging. It is also preferable that the peeling portion 22 and the anchor portion 14 have a certain degree of bonding strength at the interface so as not to shift in the in-plane direction. When a thermal peeling material is used as the peeling portion 22, the peeling portion 22 is configured so as to be easily thermally peeled from the anchor portion 14 when heated to a temperature that causes thermal peeling or a temperature slightly higher than that.

[0049] Furthermore, even if the semiconductor chip 1 deviates from the specified position by approximately 0.1 μm to 5 μm, for example, when forming the anchor portion 14 or the sealing portion 15, this is within the range of error and is included in the prevention of deviation of the semiconductor chip 1 from the specified position by the anchor portion 14.

[0050] Furthermore, it is preferable that anchor part 14 and sealing part 15 (PDMS or the like) have a certain degree of bonding strength so as not to be displaced in the in-plane direction at the interface. When a thermal peeling material is used for peeling part 22 or 23, even if anchor part 14 or sealing part 15 is heated to a temperature that causes thermal peeling in the thermal peeling step or to a temperature slightly higher than that, the bonding force acts effectively at the interface between anchor part 14 and sealing part 15 (PDMS or the like) and they are configured not to be separated.

[0051] Furthermore, when multiple semiconductor chips 1 are arranged on a peel-off portion 22 (first peel-off portion) provided on a substrate 21 (first substrate), even if there is variation in the thickness (height) of the semiconductor chips 1, the semiconductor chips 1 are arranged so that the electrodes 12 of the semiconductor chips 1 abut against the peel-off portion 22 provided on the substrate 21, anchor portions 14 are formed to determine the position of the semiconductor chip 1 (ST3), a sealing portion 15 (PDMS, etc.) is formed (ST4), and the peel-off portion 22 and the substrate 21 are separated, thereby providing a method for manufacturing a semiconductor device in which the electrodes 12 of each semiconductor chip 1 can be positioned at a specified position in the same plane with high precision.

[0052] In addition, the manufacturing method of a semiconductor device according to an embodiment of the present invention includes a step (ST7) of forming wiring 17 connected to electrodes 12 of semiconductor chip 1 after the step (ST6) of exposing electrodes 12 of semiconductor chip 1. That is, it is possible to provide a manufacturing method for a semiconductor device in which wiring 17 is formed with high precision on electrodes 12 of semiconductor chip 1 that are arranged at specified positions with high precision.

[0053] In the method for manufacturing a semiconductor device according to the embodiment of the present invention, anchor portion 14 is formed by at least any one of a vapor phase deposition method, a spin coating method, a spray coating method, and an inkjet method. That is, the anchor portion 14 (anchor layer) can be easily formed by any of a vapor phase deposition method, a spin coating method, a spray coating method, etc. By forming the anchor portion 14, the semiconductor chip 1 is prevented from shifting from a specified position, and is placed in a previously specified position with high accuracy.

[0054] Furthermore, even if the sealing portion 15 (PDMS, etc.) is formed to abut against the anchor portion 14, no force is applied directly to the semiconductor chip 1 when the sealing material of the sealing portion 15 is injected, and it is possible to prevent the semiconductor chip 1 from shifting from the specified position. In particular, by forming the above-mentioned anchor portion 14 by vapor phase deposition, the position of the semiconductor chip 1 can be defined, and deviation from the defined position can be easily prevented.

[0055] Furthermore, the semiconductor device 100 according to an embodiment of the present invention is a semiconductor device 100 manufactured by the above-mentioned semiconductor device manufacturing method, and specifically includes a semiconductor chip 1 having an electrode 12 formed on one surface, an anchor portion 14 covering all surfaces of the semiconductor chip 1 except the surface on which the electrode 12 is formed, a sealing portion 15 (PDMS, etc.) abutting the anchor portion 14, and wiring 17 connected to the electrode 12 of the semiconductor chip 1. That is, in the semiconductor device 100 manufactured by the above-mentioned semiconductor device manufacturing method, the anchor portion 14 covers all surfaces of the semiconductor chip 1 except for the surface on which the electrodes 12 are formed, and the sealing portion 15 (PDMS, etc.) is formed so as to abut against the anchor portion 14, so that a highly integrated semiconductor device 100 can be provided with high precision without deviation from the specified position. Furthermore, when the sealing portion 15 and the like of the semiconductor device 100 are formed from a flexible material, the semiconductor device 100 can be flexibly bent, and since the anchor portion 14 is provided even in a bent state, the positional deviation of the semiconductor chip 1 is small.

[0056] Moreover, the manufacturing method of a device including the semiconductor device according to the embodiment of the present invention includes a step of combining the semiconductor device 100 manufactured by the above-mentioned manufacturing method of the semiconductor device with other components to manufacture a device. In other words, it is possible to easily provide a manufacturing method of a device including the semiconductor device 100. Moreover, a device according to an embodiment of the present invention includes the semiconductor device 100. The device including the semiconductor device 100 may be an electronic device, for example, a portable information processing device such as a smartphone or a mobile phone, a medical device, or a device other than an electronic device, and any device including the semiconductor device 100 is included in the scope of the invention.

[0057] Although the embodiments of the present invention have been described in detail above with reference to the drawings, the specific configurations are not limited to these embodiments, and the present invention also includes design changes and the like that do not deviate from the gist of the present invention. In addition, the embodiments shown in the above-mentioned drawings can be combined with each other as long as there is no particular contradiction or problem in the purpose, configuration, etc. Furthermore, the contents of each drawing may be independent embodiments, and the embodiment of the present invention is not limited to one embodiment obtained by combining the drawings.

[0058] For example, the manufacturing method of a semiconductor device according to an embodiment of the present invention may include a step of forming an insulating layer (buffer portion) made of an insulating material between either or both of the anchor portion 14 and the semiconductor chip 1, or between the anchor portion 14 and the sealing portion 15. This insulating layer (buffer portion) can increase the bonding strength between the anchor portion 14 and the semiconductor chip 1 or the sealing portion 15 by providing an insulating layer made of a material that increases the bonding strength at the boundary portion when the bonding strength between the anchor portion 14 and the semiconductor chip 1 or the sealing portion 15 is weak. In addition, when the anchor portion 14 is made of a conductive material, for example, an insulating layer (buffer portion) can be formed between the anchor portion 14 and the semiconductor chip 1, or between the anchor portion 14 and the sealing portion 15, or both, to prevent leakage current from the anchor portion 14. [Explanation of symbols]

[0059] 1. Semiconductor chip 12...Electrode (electrode of semiconductor chip) 14...Anchor section (anchor layer, etc.) 15...Sealing part (PDMS etc.) 16...Buffer layer 17...Wiring (rewiring layer, etc.) 21...Substrate (first substrate) 22...Removal portion (first removal portion) 23... Peeling portion (second peeling portion) 24...Substrate (second substrate) 100...Semiconductor device

Claims

1. A method for manufacturing a semiconductor device including a semiconductor chip, comprising: a step of placing a semiconductor chip such that electrodes of the semiconductor chip abut on a peeling portion provided on a substrate; forming an anchor portion that defines a position of the semiconductor chip and has flexibility so as to cover the peeling portion and the semiconductor chip; forming a sealing portion that is in contact with the anchor portion and has flexibility and can be bent; and separating the peeling portion and the substrate from the semiconductor chip and the anchor portion to expose the electrodes of the semiconductor chip. The anchor portion is any one of a combination of 4,4'-diaminodiphenylmethane and 4,4'-diphenylmethane diisocyanate, a combination of 1,9-diaminononane and 1,9-diisocyanatenonane, and a combination of 1,5-diaminopentane and 1,5-diisocyanatepentane.

4. A method for manufacturing a semiconductor device comprising the steps of:

2. After exposing the electrodes of the semiconductor chip, a step of forming wiring to be connected to the electrodes is included.

2. The method for manufacturing a semiconductor device according to claim 1.

3. The anchor portion is formed by a vapor deposition method, a spray coating method, or an inkjet method.

3. The method for manufacturing a semiconductor device according to claim 1, wherein the semiconductor device is a semiconductor device having a first insulating layer.

4. The anchor portion is formed so as to cover a portion of the semiconductor chip other than the surface on which the electrodes are formed.

4. The method for manufacturing a semiconductor device according to claim 1, wherein the semiconductor device is a semiconductor substrate.

5. forming an insulating layer between the anchor portion and the semiconductor chip, or between the anchor portion and the sealing portion, or both of them; 5. The method for manufacturing a semiconductor device according to claim 1,

6. The method includes a step of assembling a semiconductor device manufactured by the method for manufacturing a semiconductor device according to any one of claims 1 to 5 with other components to manufacture a device.

4. A method for manufacturing a device including a semiconductor device.

7. A semiconductor chip having an electrode formed on one surface thereof; an anchor portion that covers a surface of the semiconductor chip other than the surface on which the electrodes are formed and has flexibility such that the anchor portion is freely bendable; a sealing portion that abuts against the anchor portion and has flexibility that allows the sealing portion to bend freely; and wiring connected to the electrodes of the semiconductor chip. A semiconductor device comprising:

8. The anchor portion is any one of a combination of 4,4'-diaminodiphenylmethane and 4,4'-diphenylmethane diisocyanate, a combination of 1,9-diaminononane and 1,9-diisocyanatenonane, a combination of 1,5-diaminopentane and 1,5-diisocyanatepentane, and parylene.

8. The semiconductor device according to claim 7,

9. An apparatus comprising the semiconductor device according to claim 7 or 8.

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