POWER CONVERSION DEVICE AND METHOD FOR CONTROLLING POWER CONVERSION DEVICE

Abstract

The control device (4) outputs first and second drive signals (Vin1, Vin2) so as to provide a dead time during which both the first and second semiconductor switching elements (Q1, Q2) are in an off state. The drive device (3) includes a first drive unit (311) configured to be able to adjust the drive capacity of the first semiconductor switching element (Q1), and a first adjustment unit (312) that adjusts the drive capacity of the first semiconductor switching element (Q1) by the first drive unit (311) in response to a first adjustment signal (Vref1) so as to change the switching speed of the first semiconductor switching element (Q1). The control device (4) includes a setting unit (402) that sets the active level time of the first drive signal (Vin1) in response to the first adjustment signal (Vref1).

Description

[Technical field]

[0001] The present disclosure relates to a power conversion device, and more particularly to a power conversion device including a plurality of semiconductor switching elements. [Background technology]

[0002] 2. Description of the Related Art In recent years, semiconductor switching elements such as metal-oxide-semiconductor field-effect transistors (MOSFETs) and insulated gate bipolar transistors (IGBTs) have become widespread. These semiconductor switching elements are used, for example, as power semiconductor elements in power conversion devices.

[0003] Japanese Patent Application Laid-Open No. 2019-22253 (Patent Document 1) discloses a semiconductor drive device. As shown in FIG. 10 and FIG. 11 of Patent Document 1, the short circuit protection board of the semiconductor drive device includes an overcurrent detection circuit and a short circuit detection circuit. When the overcurrent detection circuit detects an overcurrent flowing through the IGBT, the short circuit detection circuit determines that the IGBT is short-circuited. Then, the short circuit detection circuit reduces the gate voltage of the IGBT to shut off the IGBT (see

[0055] to

[0058] ). [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2019-22253 A [Patent Document 2] JP 2012-129973 A [Patent Document 3] Patent Publication No. 2022-46153 [Patent Document 4] JP 2017-212870 A [Patent Document 5] Patent Publication No. 2022-48884 Summary of the Invention [Problem to be solved by the invention]

[0005] In a power conversion device including a plurality of semiconductor switching elements, there is a demand for appropriately controlling the switching timing of each semiconductor switching element. For example, assume a situation in which two semiconductor switching elements connected in series with each other are alternately turned on. In order to avoid a situation in which both of the two semiconductor switching elements are turned on even temporarily, it is conceivable to provide a "dead time" in which both of the two semiconductor switching elements are turned off. In switching control in which such a dead time is provided, it is desirable to appropriately control the switching timing.

[0006] The present disclosure has been made in consideration of the above problems, and one of the objects of the present disclosure is to appropriately control switching timing in switching control in which a dead time is provided. [Means for solving the problem]

[0007] A power conversion device according to an embodiment of the present disclosure includes a first semiconductor switching element, a second semiconductor switching element, a control device, and a drive device. The control device outputs first and second drive signals, each of which is switched between an active level and an inactive level, such that the first semiconductor switching element and the second semiconductor switching element are alternately turned on and a dead time is provided in which both the first and second semiconductor switching elements are in an off state. The drive device drives the first and second semiconductor switching elements according to the first and second drive signals. The drive device includes a first drive unit configured to be able to adjust the drive capability of the first semiconductor switching element, and a first adjustment unit that adjusts the drive capability of the first semiconductor switching element by the first drive unit according to a first adjustment signal so that a switching speed of the first semiconductor switching element changes. The control device includes a setting unit that sets an active level time of the first drive signal according to the first adjustment signal.

[0008] In a control method for a power conversion device according to another aspect of the present disclosure, the power conversion device includes first and second semiconductor switching elements and a drive device that drives the first and second semiconductor switching elements according to first and second drive signals, respectively. Each of the first and second drive signals is switched between an active level and an inactive level. The drive device is configured to adjust the drive capability of the first semiconductor switching element according to the first adjustment signal so that a switching speed of the first semiconductor switching element is changed. The control method for the power conversion device includes a step of outputting the first and second drive signals so that the first semiconductor switching element and the second semiconductor switching element are alternately turned on and a dead time is provided in which both the first and second semiconductor switching elements are in an off state. The step of outputting includes a step of setting an active level time of the first drive signal according to the first adjustment signal. Effect of the Invention

[0009] While the on-time of the first semiconductor switching element can be changed depending on the driving capability of the first driving unit, in the above aspect, the active level time of the first driving signal is set depending on the adjustment signal. The active level time of the first driving signal is lengthened depending on the adjustment signal, and when the active level time of the first driving signal is lengthened, the on-time of the first semiconductor switching element is lengthened. This makes it possible to ensure the necessary on-time of the first semiconductor switching element. Therefore, according to the above aspect, it is possible to appropriately control the switching timing in switching control in which a dead time is provided. [Brief description of the drawings]

[0010] [Figure 1] 1 is a block diagram showing an example of a configuration of a power conversion system according to an embodiment. [Diagram 2] FIG. 1 is a diagram illustrating an example of a configuration of a power conversion device. [Diagram 3] FIG. 2 is a diagram illustrating an example of a hardware configuration of a control device. [Figure 4] FIG. 2 is a diagram illustrating a first example of the configuration of a drive device and a control device. [Diagram 5] FIG. 2 is a diagram showing a first example of the configuration of a drive unit. [Figure 6] FIG. 13 is a diagram showing a second example of the configuration of the drive unit. [Figure 7] FIG. 13 is a diagram illustrating a third example of the configuration of the drive unit. [Figure 8] 11 is a diagram illustrating an example of a relationship between an adjustment signal and a drive capability signal. [Figure 9] 13 is a diagram illustrating another example of the relationship between the adjustment signal and the drive capability signal. [Figure 10] 4 is a time chart for explaining the operation of the drive device. [Figure 11] 4 is a time chart for explaining a dead time. [Figure 12] 4 is a time chart for explaining an actual on-time of a switching element. [Figure 13] 5 is a time chart for explaining the influence of the driving capability of a switching element by a driving device on the ON time of the switching element. [Figure 14] 5 is a time chart for explaining a process for generating a drive signal in the present embodiment. [Figure 15] 11 is a diagram illustrating an example of a correspondence relationship between an adjustment signal and a high-level time of a drive signal. FIG. [Figure 16] 13 is a diagram illustrating another example of the correspondence relationship between the adjustment signal and the high-level time of the drive signal. FIG. [Figure 17] 11 is a diagram illustrating an example of a correspondence relationship between an adjustment signal and a correction time of a drive signal. FIG. [Figure 18] 13 is a diagram illustrating another example of the correspondence relationship between the adjustment signal and the correction time of the drive signal. FIG. [Figure 19] 10 is a flowchart showing an example of a processing procedure for generating a drive signal according to the embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference characters, and the description thereof will not be repeated.

[0012] Embodiment <System configuration> 1 is a block diagram showing an example of a configuration of a power conversion system according to an embodiment. The power conversion system 100 includes a power conversion device 1, a power source 8, and a load 9.

[0013] The power supply 8 supplies power to the power conversion device 1. The power supply 8 is, for example, an AC power supply (AC system), typically a commercial power supply. The power supply 8 may be a DC power supply (DC system) such as a storage battery or a solar cell. The power supply 8 may include an AC / DC converter connected to the AC power supply. The power supply 8 may include a DC / DC converter that boosts or lowers the DC power output from the DC power supply.

[0014] The load 9 is a device driven by power supplied from the power conversion device 1. The load 9 is, for example, an AC load. Specifically, the load 9 may be a three-phase motor for a hybrid car, an electric car, a railroad car, an elevator, or an air conditioner. The load 9 may be, for example, an electric discharge machine, a laser processing machine, an induction heating cooker, or a non-contact power supply system. The load 9 may be, for example, a DC load (for example, a storage battery).

[0015] The power conversion device 1 is electrically connected between a power source 8 and a load 9. The power conversion device 1 converts power supplied from the power source 8 into power suitable for use by the load 9, and supplies the converted power to the load 9. The power conversion device 1 includes a main conversion device 2, a main drive device 3, and a control device 4.

[0016] The main converter 2 includes a semiconductor module 201 for performing the above-mentioned power conversion operation. The semiconductor module 201 includes, for example, switching elements Q1 to Q6 (see FIG. 2). Each of the switching elements Q1 to Q6 is a MOSFET, an IGBT, a MESFET (Metal-Semiconductor Field-Effect Transistor), a bipolar transistor, or the like. The material of the switching elements Q1 to Q6 is typically Si, but other materials (SiC, GaN ... a 2O 3 , diamond, etc.

[0017] The main driving device 3 drives the semiconductor module 201 in the main conversion device 2. The control device 4 controls the main driving device 3.

[0018] 2 is a diagram showing an example of the configuration of the power conversion device 1. In this example, the power source 8 is a three-phase AC power source 81, and supplies AC power to the main conversion device 2 via three AC input terminals Ta, Tb, and Tc. The load 9 is a three-phase electric motor 91, and receives AC power from the main conversion device 2 via three AC output terminals Tu, Tv, and Tw. The main conversion device 2 includes a rectifier circuit 21 and an inverter circuit 22.

[0019] The rectifier circuit 21 is, for example, a full-wave rectifier circuit, and includes six diodes 211 to 216. The diode 211 has a cathode connected to the high-potential DC power line PL and an anode connected to the AC input terminal Ta. The diode 212 has a cathode connected to the AC input terminal Ta and an anode connected to the low-potential DC power line NL. The diode 213 has a cathode connected to the high-potential DC power line PL and an anode connected to the AC input terminal Tb. The diode 214 has a cathode connected to the AC input terminal Tb and an anode connected to the low-potential DC power line NL. The diode 215 has a cathode connected to the high-potential DC power line PL and an anode connected to the AC input terminal Tc. The diode 216 has a cathode connected to the AC input terminal Tc and an anode connected to the low-potential DC power line NL.

[0020] The inverter circuit 22 is, for example, a two-level three-phase full-bridge circuit, and includes six switching elements Q1 to Q6 and six freewheel diodes D1 to D6. The freewheel diodes D1 to D6 are connected in anti-parallel to the switching elements Q1 to Q6, respectively. The switching elements Q1 and Q2 are connected in series to each other to form a U-phase arm 22U of the full-bridge circuit. The switching elements Q3 and Q4 are connected in series to each other to form a V-phase arm 22V of the full-bridge circuit. The switching elements Q5 and Q6 are connected in series to each other to form a W-phase arm 22W of the full-bridge circuit. Each phase arm is connected between a high-potential DC power line PL and a low-potential DC power line NL. The U-phase arm, the V-phase arm, and the W-phase arm are connected to AC output terminals Tu, Tv, and Tw, respectively.

[0021] The main driving device 3 includes six driving devices 31 to 36. The driving devices 31 to 36 drive the switching elements Q1 to Q6, respectively. The configuration of each of the driving devices 31 to 36 will be described with reference to FIG. 4 and subsequent figures.

[0022] The control device 4 outputs a drive signal Vinj (j=1 to 6) to each of the six driving devices 31 to .

[0023] 3 is a diagram showing an example of a hardware configuration of the control device 4. The control device 4 includes, for example, a processor 41, a memory 42, a receiver 43, and a display 44.

[0024] The processor 41 is an arithmetic processing device such as a central processing unit (CPU) or a micro processing unit (MPU). The memory 42 includes a volatile storage device such as a dynamic random access memory (DRAM) or a static random access memory (SRAM), and a non-volatile storage device such as a hard disk drive (HDD), a solid state drive (SSD), or a flash memory. The memory 42 stores a system program including an operating system (OS), a control program including computer-readable code, and various parameters for controlling the power conversion operation. The processor 41 realizes various arithmetic processing by reading the system program, the control program, and the parameters, expanding them in the memory 42, and executing them.

[0025] The control device 4 may be realized by a processing circuit (not shown) such as an Application Specific Integrated Circuit (ASIC) or a Field Programmable Gate Array (FPGA). The control device 4 may include a processing circuit instead of or in addition to the processor 41 and the memory 42.

[0026] The receiving device 43 is a touch panel, an operation button, etc., and receives operations by a user. The display 44 is a monitor, etc., and displays to the user the progress and results of the arithmetic processing by the processor 41. Instead of or in addition to the display 44, the control device 4 may include a communication module (not shown) for transmitting the progress and results of the arithmetic processing by the processor 41 to the outside.

[0027] <Configuration of the drive unit and control unit> ≪Basic configuration≫ FIG. 4 is a diagram showing the basic configuration of the main driving device 3 and the control device 4. Each of the driving devices 31-36 shown in FIG. 3 executes the same process for the corresponding switching element among the switching elements Q1-Q6. To avoid cluttering the page, FIG. 4 shows only two switching elements Q1 and Q2 and driving devices 31 and 32 that drive the switching elements Q1 and Q2, respectively. The following describes the configuration of the switching element Q1 and the driving device 31 as a representative example, but the switching element Q2 and the driving device 32 are also configured in the same way, except for the difference in the power supply voltage and reference potential.

[0028] The switching element Q1 is a power semiconductor switching element. In this example, the switching element Q1 is a power MOSFET and includes a drain D, a source S, and a gate G. However, the switching element Q1 may be an IGBT (Insulated Gate Bipolar Transistor), a MESFET, or a bipolar power transistor.

[0029] The control device 4 generates a drive signal Vin1 for controlling the switching timing of the switching element Q1. For example, the control device 4 generates the drive signal Vin1 by PWM (Pulse Width Modulation) control based on a comparison between a triangular wave carrier signal and a voltage command value. The control device 4 may generate the drive signal Vin1 by using another method such as a space vector method instead of a triangular wave carrier signal. The control device 4 outputs the generated drive signal Vin1 to the drive device 31.

[0030] The control device 4 includes a storage unit 401 and a setting unit 402. The storage unit 401 stores a map used for setting the on-time of the drive signal Vin1. The setting unit 402 sets the on-time of the drive signal Vin1 by referring to the map. The setting of the on-time of the drive signal Vin1 will be described in detail later with reference to Figs. 11 to 19.

[0031] The driving device 31 is connected to a power supply voltage Vcc1 and a reference potential (ground GND1). The power supply voltage and the reference potential are different between the driving device 31 that drives the upper arm and the driving device 32 that drives the lower arm. The driving device 31 includes a driving unit 311, an adjustment unit 312, and terminals T11 to T13. The terminal T11 is electrically connected to the control device 4. Since the reference potential may be different between the driving device 31 that drives the upper arm and the control device 4, an interface (such as a level shift circuit or an isolator) (not shown) is provided between the terminal T1 of the driving device 31 and the control device 4. The terminal T12 is connected to the control device 4. The terminal T13 is electrically connected to the switching element Q1.

[0032] The adjustment unit 312 adjusts the driving ability of the switching element Q1 by the driving unit 311. The driving ability of the switching element Q1 by the driving unit 311 determines the switching speed of the switching element Q1. The higher the driving ability of the switching element Q1 by the driving unit 311, the faster the switching speed of the switching element Q1.

[0033] More specifically, the adjustment unit 312 receives an adjustment signal Vref1 via a terminal T12 from the control device 4. The adjustment unit 312 generates a drive capability signal Vcap1 for adjusting the drive capability of the switching element Q by the drive unit 311 based on the adjustment signal Vref1, and outputs the generated drive capability signal Vcap1 to the drive unit 311.

[0034] The driving unit 311 receives the driving signal Vin1 from the control device 4 via a terminal T11, and also receives the driving capability signal Vcap1 from the adjustment unit 312. The driving unit 311 generates a gate signal Sg1 based on the driving signal Vin and the driving capability signal Vcap1. More specifically, the driving unit 311 is configured to adjust the driving capability of the switching element Q1 according to the driving capability signal Vcap1, and generates the gate signal Sg1 from the driving signal Vin1 according to the adjusted driving capability. The driving unit 311 outputs the generated gate signal Sg1 to the gate G of the switching element Q1 via a terminal T13. This allows the waveform (gate waveform) of the gate signal Sg1 provided to the gate G of the switching element Q1 to be changed according to the driving capability signal Vcap1.

[0035] <Drive unit configuration> The following describes three typical configuration examples of the driver 311. However, the configuration of the driver 311 is not limited to these as long as it is possible to change the switching speed of the switching element Q1.

[0036] 5 is a diagram showing a first example of the configuration of the driver 311A. The driver 311A ​​is configured so that the gate resistor included in the driver 311A ​​is variable. The driver 311A ​​includes a control circuit 51 and a resistance adjustment circuit 52.

[0037] The control circuit 51 generates the gate signal Sg1 by driving the resistance adjustment circuit 52 based on the drive signal Vin1 and the drive capability signal Vcap1. The resistance adjustment circuit 52 includes, for example, a plurality of series circuits. Each of the plurality of series circuits includes a resistance element 521 and a switch 522 connected in series with each other. Each switch 522 is controlled to be turned on and off in response to a control signal from the control circuit 51. The control circuit 51 selects a resistance element to be controlled (which resistance element is to be connected and which resistance element is to be disconnected) among the plurality of resistance elements 521 included in the resistance adjustment circuit 52 based on the drive capability signal Vcap1, and switches on and off the switch corresponding to the selected resistance element. This allows the gate resistance of the switching element Q1 to be adjusted to a desired value.

[0038] 6 is a diagram showing a second example of the configuration of the drive unit. The drive unit 311B is configured to vary the gate current to the switching element Q1. The drive unit 311B includes a control circuit 53 and a current adjustment circuit .

[0039] The current adjustment circuit 54 includes, for example, a switch 541 connected to the gate of the switching element Q1, and an operational amplifier 542. The operational amplifier 542 changes the current (gate current) flowing through the switch 541 so as to follow the drive capability signal Vcap1 provided from the adjustment unit 312. The control circuit 53 controls the on / off of the current flowing through the switch 541 by switching the switch 541 in response to the drive signal Vin1.

[0040] FIG. 7 is a diagram showing a third example of the configuration of the driving unit. The driving unit 311C is configured to vary the gate voltage of the switching element Q1. The driving unit 311C includes a voltage adjustment circuit 55 and a driving circuit 56. The driving circuit 56 includes, for example, an NPN bipolar transistor 561 and a PNP bipolar transistor 562 connected in series between a power supply voltage Vcc and a ground GND. The voltage adjustment circuit 55 includes a voltage amplifier 551 (for example, an operational amplifier circuit). The amplification factor of the voltage amplifier 551 is adjusted by a driving capability signal Vcap1. A common gate of the bipolar transistors 561 and 562 receives the driving signal Vin1 amplified by the voltage amplifier 551. A common output node of the bipolar transistors 561 and 562 is connected to the gate of the switching element Q1. This allows the gate voltage of the switching element Q1 to be adjusted according to the driving capability signal Vcap1.

[0041] <Driving capability signal> Fig. 8 is a diagram showing an example of the relationship between the adjustment signal Vref1 and the drive capability signal Vcap1. Fig. 9 is a diagram showing another example of the relationship between the adjustment signal Vref1 and the drive capability signal Vcap1. The horizontal axis represents the voltage value of the adjustment signal Vref1. The vertical axis represents the voltage value of the drive capability signal Vcap1.

[0042] The higher the adjustment signal Vref1, the higher the drive capability signal Vcap1. As the adjustment signal Vref1 increases, the drive capability signal Vcap1 may increase linearly as shown in Figure 8, or may increase in steps as shown in Figure 9. Although not shown, the drive capability signal Vcap1 may increase nonlinearly (curvilinearly) as the adjustment signal Vref1 increases.

[0043] In general, switching loss and conduction loss occur with the switching operation of a switching element. The switching loss depends on the area of ​​the region where the voltage waveform and the current waveform overlap. Therefore, the switching loss decreases when the switching waveform exhibits a steep change, whereas it increases when the switching waveform exhibits a gradual change. In addition, high-frequency switching noise occurs with the switching operation of a switching element and is superimposed on the switching waveform. The switching noise increases when the switching waveform exhibits a steep change, whereas it decreases when the switching waveform exhibits a gradual change. Thus, there is a trade-off between switching loss and switching noise depending on whether the switching waveform exhibits a steep or gradual change.

[0044] When the driving capability signal Vcap1 is set so that the driving capability of the switching element Q1 by the driving unit 311 increases, the switching waveform exhibits a steep change, so that the switching noise increases while the switching loss decreases. This improves the energy saving performance of the power conversion device 1 and reduces the energy consumption.

[0045] On the other hand, when the driving capability signal Vcap1 is set so that the driving capability of the switching element Q1 by the driving unit 311 is reduced, the switching waveform exhibits a gradual change, so that the switching loss increases while the switching noise decreases. This makes it easy to make the power conversion device 1 comply with the EMC (Electromagnetic Compatibility) standard. In addition, since EMC countermeasure parts are not required, the material cost can be reduced.

[0046] <Operation of the drive unit> 10 is a time chart for explaining the operation of the driving device 31. The horizontal axis represents elapsed time, and the vertical axis represents, from the top, the adjustment signal Vref1, the driving capability signal Vcap1, the driving signal Vin1, and the gate signal Sg1.

[0047] At initial time t0, the adjustment signal Vref1 is 0 V. The adjustment signal Vref1 rises at time t1 and further rises at time t4. The drive signal Vin1 repeats periodic changes (rising and falling) between a high level (H) and a low level (L).

[0048] In this example, the rising edge of the drive signal Vin1 is the timing for generating (updating) the drive capability signal Vcap1. Therefore, at times t2, t5, and 17 when the drive signal Vin1 rises, the drive capability signal Vcap1 is generated based on the adjustment signal Vref1.

[0049] During turn-on switching of the switching element Q1, the voltage applied between the drain D (positive electrode) and source S (negative electrode) of the switching element Q1 decreases, and the current flowing between the drain D and source S increases. During turn-off switching of the switching element Q1, the voltage applied between the drain D and source S increases, and the current flowing between the drain D and source S decreases. A waveform that indicates at least one change in the voltage (voltage between the drain D and source S) and the current (current flowing between the drain D and source S) during these switching events is called a "switching waveform."

[0050] In general, switching loss and conduction loss occur with the switching operation of a switching element. The switching loss depends on the area of ​​the region where the voltage waveform and the current waveform overlap. Therefore, the switching loss decreases when the switching waveform exhibits a steep change, whereas it increases when the switching waveform exhibits a gradual change. In addition, high-frequency switching noise occurs with the switching operation of a switching element and is superimposed on the switching waveform. The switching noise increases when the switching waveform exhibits a steep change, whereas it decreases when the switching waveform exhibits a gradual change. Thus, there is a trade-off between switching loss and switching noise depending on whether the switching waveform exhibits a steep or gradual change.

[0051] When the driving capability signal Vcap1 is set so that the driving capability of the switching element Q1 by the driving unit 311 increases, the switching speed of the switching element Q1 increases and the switching waveform exhibits a steep change. Therefore, while the switching noise increases, the switching loss decreases. This improves the energy saving performance of the power conversion device 1 and reduces the energy consumption.

[0052] Conversely, when the driving capability signal Vcap1 is set so that the driving capability of the driving unit 311 for the switching element Q1 is reduced, the switching speed of the switching element Q1 is reduced and the switching waveform exhibits a gradual change. As a result, the switching loss increases while the switching noise is reduced. This makes it easier to make the power conversion device 1 compliant with EMC (Electromagnetic Compatibility) standards. In addition, since EMC countermeasure components are no longer necessary, the material costs can be reduced.

[0053] The timing of generating the drive capability signal Vcap1 is not limited to the rising edge of the drive signal Vin1. The timing of generating the drive capability signal Vcap1 may be set to the falling edge of the drive signal Vin1, or may be set to the rising edge (or falling edge) of a delayed drive signal Vin1. The drive capability signal Vcap1 may be generated in synchronization with the rising edge (or falling edge) of a signal other than the drive signal Vin1 (such as a timer signal, a clock signal, an enable signal, or power-on).

[0054] <Dead time> 2, the switching element Q1 and the switching element Q2 are connected in series. Therefore, for example, if the timing at which the switching element Q1 is switched from on to off by the drive signal Vin1 and the timing at which the switching element Q2 is switched from off to on by the drive signal Vin2 are simultaneous, the switching element Q2 may turn on before the switching element Q1 is completely off, causing the capacitor C to be short-circuited. To avoid such a situation, a "dead time" during which both the switching elements Q1 and Q2 are off is provided between the timing at which the switching element Q1 is switched from on to off and the timing at which the switching element Q2 is switched from off to on.

[0055] FIG. 11 is a time chart for explaining the dead time. The horizontal axis represents elapsed time. The vertical axis represents, from the top, the drive signal Vin1 output from the control device 4 to the drive unit 311, the drive signal Vin2 output from the control device 4 to the drive unit 321, the drain-source voltage (hereinafter sometimes abbreviated as "voltage") Vds1 of the switching element Q1, and the drain-source voltage Vds2 of the switching element Q2. The same applies to FIGS. 12 to 14 described later. For ease of understanding, the delay times (turn-on delay time and turn-off delay time) of the drain-source voltage with respect to the drive signal are omitted from the illustration.

[0056] The driving signal Vin1 changes from a low level to a high level at time t11, and from a high level to a low level at time t12. The driving signal Vin2 changes from a low level to a high level at time t13, and from a high level to a low level at time t14. Furthermore, the driving signal Vin1 changes from a low level to a high level at time t15, and from a high level to a low level at time t16. In this case, the time from time t12 to time t13 and the time from time t14 to time t15 are dead times (represented by DT). Note that since both switching elements Q1 and Q2 are off during the dead times, the direction through which the current flows among the switching elements Q1 and Q2 and the freewheel diodes D1 and D2 is determined by the direction of the current flowing through the load (the electric motor 91 in this example) (see FIG. 2).

[0057] The sum of the drain-source voltage (hereinafter sometimes abbreviated as "voltage") Vds1 of the switching element Q1 and the voltage Vds2 of the switching element Q2 is always equal to the terminal voltage of the capacitor C (see FIG. 2) connected between the DC power lines PL and NL. Ideally, as shown in FIG. 11, the voltage Vds1 of the switching element Q1 changes in a square wave shape in synchronization with the drive signal Vin1. This provides an on-time Ton1 of the switching element Q1 from time t11 to time t12. The on-time Ton1 is equal to the time Th1 during which the drive signal Vin1 is at a high level (hereinafter referred to as the "high level time").

[0058] However, in reality, the on-time Ton1 of the switching element Q1 is not completely equal to the high-level time Th1.

[0059] The on-time Ton2 of the switching element Q1 is longer than the high-level time T2 during which the drive signal Vin2 is at a high level by the dead time provided before and after the high-level time T2 (in FIG. 11, this is the sum of the time from time t12 to time t13 and the time from time t14 to time t15).

[0060] FIG. 12 is a time chart for explaining the actual on-time of the switching element Q1. The voltage Vds1 of the actual switching element Q1 does not change like a square wave, and a turn-on time and a turn-off time occur. The on-time Ton1 of the switching element Q1 is shorter than the high-level time Th1 of the drive signal Vin1 by the turn-on time ton of the switching element Q1 (more specifically, the rise time, where the turn-on time ton=the turn-on delay time+the rise time). In the example of FIG. 12, the turn-on time ton of the switching element Q1 is shorter than the high-level time Th1 of the drive signal Vin1 by the time from time t21 to time t21′.

[0061] A short on-time Ton1 of the switching element Q1 means a short time during which the switching element Q1 can be used for the power conversion operation in the power conversion device 1. Therefore, depending on the operating conditions of the power conversion device 1 (for example, when the power conversion device 1 converts large power), it may not be possible to ensure the on-time Ton1 that is essentially required for the switching element Q1.

[0062] In addition, the driving capability of the driving device 31 for the switching element Q1 can affect the on-time Ton1.

[0063] In addition, the voltage Vds2 of the actual switching element Q2 does not change like a square wave. The on-time Ton2 of the actual switching element Q2 becomes shorter than the on-time Ton2 shown in FIG. 11 and approaches the high-level time T2 by the amount that the dead time provided before the high-level time T2 becomes shorter (see the change from time t22 to time t22').

[0064] Fig. 13 is a time chart for explaining the influence of the driving ability of the driving device 31 on the on-time Ton1 of the switching element Q1. In Fig. 13, a thin dashed dotted line indicates the time change in the voltage Vds1 of the switching element Q1 when the driving ability of the driving device 31 for the switching element Q1 is high. On the other hand, a thick solid line indicates the time change in the voltage Vds1 of the switching element Q1 when the driving ability of the driving device 31 for the switching element Q1 is low. The same applies to the switching element Q2.

[0065] When the driving capability of the driving device 31 for the switching element Q1 is high, the switching speed of the switching element Q1 is fast and the turn-on time ton is short. Then, the difference between the on-time Ton1 of the switching element Q1 and the high-level time Th1 of the driving signal Vin1 is relatively short. On the other hand, when the driving capability of the driving device 31 for the switching element Q1 is low, the switching speed of the switching element Q1 is slow and the turn-on time ton is long. Then, the difference between the on-time Ton1 of the switching element Q1 and the high-level time Th1 of the driving signal Vin1 is relatively long.

[0066] In this way, when the driving capability of the switching element Q1 by the driving device 31 is adjusted, the on-time Ton1 of the switching element Q1 is affected. Therefore, even if a normal "dead time correction" for simply setting the on-time Ton1 is performed in consideration of the dead time, when the driving capability of the switching element Q1 is changed (particularly when the driving capability of the switching element Q1 by the driving device 31 is set low), there is a possibility that the time length required for the on-time Ton1 of the switching element Q1 cannot be secured. Therefore, in this embodiment, the control device 4 generates the driving signal Vin1 in consideration of the difference in the driving capability of the switching element Q1 by the driving device 31. Hereinafter, this process is referred to as a driving signal generation process, and will be described in detail.

[0067] <Generation process of drive signals> 14 is a time chart for explaining the generation process of the drive signal in this embodiment. As described above, the drive capacity of the switching element Q1 by the drive device 31 is determined according to the adjustment signal Vref1 provided to the drive device 31 by the control device 4. Therefore, the control device 4 sets the high level time Th1 of the drive signal Vin1 according to the adjustment signal Vref1.

[0068] 14, the high-level time Th1 of the drive signal Vin1 (see thick solid line) for the switching element Q1 when the driving ability of the driving device 31 for the switching element Q1 is low is longer than the high-level time Th1 of the drive signal Vin1 (see thin dashed dotted line) for the switching element Q1 when the driving ability of the driving device 31 for the switching element Q1 is high (see times t42, t42'). In this way, the lower the driving ability of the switching element Q1, the longer the high-level time Th1 of the drive signal Vin1 is set.

[0069] As an example, the control device 4 sets the high level time Th1 of the drive signal Vin1 as the sum of a reference time Th0 and a correction time ΔTh1 (Vref1) (see the following formula (1)). Th1=Th0+ΔTh1(Vref1) ···(1)

[0070] The reference time Th0 has a fixed length and is determined in advance so that the high-level time Th1 is the minimum necessary time length even if the correction time ΔTh1=0. The reference time Th0 may be, for example, a high-level time under ideal conditions when no turn-on time or turn-off time occurs as described in Fig. 11. On the other hand, the correction time ΔTh1 has a variable length and changes according to the adjustment signal Vref1.

[0071] By setting the high-level time Th1 of the drive signal Vin1 in this manner, the high-level time Th1 becomes longer as the correction time ΔTh1 becomes longer according to the adjustment signal Vref1, and therefore the on-time Ton1 of the switching element Q1 becomes longer. In other words, the lower the driving capability of the switching element Q1 by the drive device 31 is set by the adjustment signal Vref1, the longer the on-time Ton1 of the switching element Q1 is set. This makes it possible to ensure the necessary on-time Ton1 even when the driving capability of the switching element Q1 by the drive device 31 is low.

[0072] Fig. 15 is a diagram showing an example of the correspondence relationship between the adjustment signal Vref1 and the high-level time Th1 of the drive signal Vin1. Fig. 16 is a diagram showing another example of the correspondence relationship between the adjustment signal Vref1 and the high-level time Th1 of the drive signal Vin1. The horizontal axis represents the level of the adjustment signal Vref1. The vertical axis represents the high-level time Th1 of the drive signal Vin1.

[0073] 15, when the adjustment signal Vref1 is at the lowest level (Vref1=0 in this example), the high level time Th1 of the drive signal Vin1 is the longest Th(max). As the level of the adjustment signal Vref1 increases, the high level time Th1 of the drive signal Vin1 decreases monotonically. When the adjustment signal Vref1 is at the highest level (Vref1=Vmax in this example), the high level time Th1 of the drive signal Vin1 is the shortest reference time Th0.

[0074] 16, there may be a range of the adjusted signal Vref1 in which the high-level time Th1 of the drive signal Vin1 is maintained at the longest, or there may be a range of the adjusted signal Vref1 in which the high-level time Th1 of the drive signal Vin1 is maintained at the shortest. Although not shown, the high-level time Th1 of the drive signal Vin1 is not limited to decreasing linearly from the longest to the shortest, and may decrease in a curved manner or in a stepwise manner.

[0075] 15 or 16, the correspondence relationship between the adjustment signal Vref1 and the high level time Th1 of the drive signal Vin1 is prepared as a map and stored in the storage unit 401 (see FIG. 4) of the control device 4. The control device 4 sets the high level time Th1 of the drive signal Vin1 from the adjustment signal Vref1 by referring to the map.

[0076] Instead of the relationship between the adjustment signal Vref1 and the high level time Th1 of the drive signal Vin1, the relationship between the adjustment signal Vref1 and the correction time ΔTh1 of the drive signal Vin1 may be used as a map.

[0077] Fig. 17 is a diagram showing an example of the correspondence relationship between the adjustment signal Vref1 and the correction time ΔTh1 of the drive signal Vin1. Fig. 18 is a diagram showing another example of the correspondence relationship between the adjustment signal Vref1 and the correction time ΔTh1 of the drive signal Vin1. The horizontal axis represents the level of the adjustment signal Vref1. The vertical axis represents the correction time ΔTh1 of the drive signal Vin1. As shown in Figs. 17 and 18, a map may be prepared that specifies the correspondence relationship between the correction time ΔTh1, which is obtained by subtracting a reference time Th0 from the high level time Th1 of the drive signal Vin1, and the adjustment signal Vref1.

[0078] These maps may include the driving conditions (voltage, current, temperature, etc.) of the switching element Q1. That is, the maps may define the correspondence between the adjustment signal Vref1, the high level time Th1 (or the correction time ΔTh1) of the driving signal Vin1, and the driving conditions of the switching element Q1. The correspondence may be defined by a data format other than the map (table, relational expression, function, etc.).

[0079] In the example of FIG. 14, the on-time Ton2 of the switching element Q2 is also set to be variable according to the adjustment signal Vref2, like the on-time Ton1 of the switching element Q1. However, the on-time Ton2 of the switching element Q2 may be the same time length regardless of the adjustment signal Vref2. In other words, the on-time Ton2 of the switching element Q2 may be subjected to normal dead time correction that does not depend on the driving capability of the switching element Q2. Alternatively, the on-time Ton2 of the switching element Q2 may not be subjected to dead time correction at all.

[0080] <Processing flow> 19 is a flowchart showing an example of a processing procedure for generating the drive signal Vin1 in the embodiment. The processing shown in this flowchart is executed, for example, at every predetermined control period. Each step is realized by software processing by the control device 4, but may also be realized by hardware (electrical circuitry) arranged in the control device 4. Hereinafter, step is abbreviated as S.

[0081] 4 and 19, in S101, the control device 4 generates the adjustment signal Vref1. The control device 4 outputs the adjustment signal Vref1 to the drive device 31.

[0082] In S102, the control device 4 acquires the drive condition of the switching element Q1. More specifically, the control device 4 may acquire the applied voltage to the switching element Q1 from a voltage sensor (not shown), or may acquire the current flowing through the switching element Q1 from a current sensor (not shown). The control device 4 may acquire the temperature of the power conversion device 1 (which may be the temperature inside the device or may be the environmental temperature) from a temperature sensor (not shown).

[0083] In S103, the control device 4 refers to the map and sets the high level time Th1 of the switching element Q1 corresponding to the adjustment signal Vref1 and the driving conditions of the switching element Q1.

[0084] It is not essential that the map includes the drive conditions. The control device 4 may refer to a map that does not include the drive conditions and simply set the high level time Th1 of the switching element Q1 corresponding to the adjustment signal Vref1.

[0085] In S104, the control device 4 generates the drive signal Vin1 so that the high level time Th1 is set as described above. Here, the drive signal Vin1 of the switching element Q1 has been described, but the control device 4 also performs similar processing on the drive signal Vin2 of the switching element Q2. However, it is not necessary to perform dead time correction on the drive signal Vin2 of the switching element Q2.

[0086] As described above, in this embodiment, the high level time Th1 of the drive signal Vin1 is set according to the adjustment signal Vref1. When the level of the adjustment signal Vref1 is low, the high level time Th1 of the drive signal Vin1 becomes longer, and when the high level time Th1 of the drive signal Vin1 becomes longer, the on time Ton1 of the switching element Q1 becomes longer. This makes it possible to secure the on time Ton1 required according to the switching speed of the switching element Q1 (the driving ability of the switching element Q1 by the driving unit 311). The same applies to the switching element Q2. Therefore, according to this embodiment, in switching control in which a dead time is provided, the switching timing of the switching elements Q1 and Q2 can be appropriately controlled.

[0087] In this embodiment, the high level of the drive signal Vin1 corresponds to the "active level" according to the present disclosure, and the low level of the drive signal Vin1 corresponds to the "inactive level" according to the present disclosure. However, depending on the circuit configuration of the power conversion device, the polarity of the high level and the low level may be reversed. In other words, the high level may correspond to the "inactive level" and the low level may correspond to the "active level."

[0088] It is not essential to perform the same process on both the drive signal Vin1 of the switching element Q1 and the drive signal Vin2 of the switching element Q2. The control device 4 may perform the above process on only one of the drive signal Vin1 and the drive signal Vin2. For example, the control device 4 may generate the drive signal Vin1 of the switching element Q1 so that a dead time according to the adjustment signal Vref1 is provided, while the dead time of the drive signal Vin2 of the switching element Q2 may be fixed regardless of the adjustment signal Vref2. In this way, the control device 4 sets the high level time of the drive signal for at least one switching element among the multiple switching elements Q1 to Q6 according to the adjustment signal.

[0089] The embodiments disclosed herein should be considered to be illustrative and not restrictive in all respects. The scope of this application is defined by the claims, not the description of the embodiments above, and is intended to include all modifications within the meaning and scope of the claims. [Explanation of symbols]

[0090] 1 power conversion device, 2 main conversion device, 21 rectifier circuit, 22 inverter circuit, 22U, 22V, 22W arm, 3 main drive device, 31-36 drive device, 4 control device, 41 processor, 42 memory, 43 receiving device, 44 display, 51 control circuit, 52 resistance adjustment circuit, 521 resistance element, 522 switch, 53 control circuit, 54 current adjustment circuit, 541 switch, 542 operational amplifier, 55 voltage adjustment circuit, 551 voltage amplifier, 56 drive circuit, 561, 562 bipolar transistor, 8 power supply, 81 AC power supply, 9 load, 91 electric motor, 100 power conversion system, 201 semiconductor module, 211-216 diode, 311, 311A-311C, 321 drive unit, 312 adjustment unit, 401 memory unit, 402 Setting section, C capacitor, D1, D6 freewheeling diodes, NL, PL DC power lines, Q, Q1 to Q6 switching elements.

Claims

1. A first semiconductor switching element; A second semiconductor switching element; a control device that outputs first and second drive signals that are switched between an active level and an inactive level so that the first semiconductor switching element and the second semiconductor switching element are alternately turned on and a dead time is provided during which both the first and second semiconductor switching elements are turned off; a drive device that drives the first and second semiconductor switching elements in accordance with the first and second drive signals, respectively; The drive device is a first drive unit configured to be able to adjust the drive capability of the first semiconductor switching element; a first adjustment unit that adjusts a drive capability of the first semiconductor switching element by the first drive unit in response to a first adjustment signal so that a switching speed of the first semiconductor switching element is changed; the control device includes a setting unit that sets an active level time of the first drive signal in response to the first adjustment signal; a switching speed of the first semiconductor switching element determined in response to the first adjustment signal being slow, the setting unit sets an active level time of the first drive signal to be longer than a switching speed of the first semiconductor switching element determined in response to the first adjustment signal being fast.

2. The drive device is a second drive unit configured to be able to adjust the drive capability of the second semiconductor switching element; a second adjustment unit that adjusts a drive capability of the second semiconductor switching element by the second drive unit in response to a second adjustment signal so that a switching speed of the second semiconductor switching element is changed; The power conversion device according to claim 1 , wherein the setting unit sets an active level time of the second drive signal in accordance with the second adjustment signal.

3. 3. The power conversion device according to claim 2, wherein the first semiconductor switching element and the second semiconductor switching element are connected in series to each other to form an arm of the power conversion device.

4. the control device outputs the first adjustment signal to the first adjustment unit and outputs the second adjustment signal to the second adjustment unit; the first adjustment unit generates a first drive capability signal for adjusting a drive capability of the first semiconductor switching element by the first drive unit based on the first adjustment signal, and outputs the first drive capability signal to the first drive unit; 4. The power conversion device according to claim 3, wherein the second adjustment unit generates a second drive capability signal for adjusting a drive capability of the second semiconductor switching element by the second drive unit based on the second adjustment signal, and outputs the second drive capability signal to the second drive unit.

5. the control device further includes a storage unit configured to store a correspondence relationship between a level of the first adjustment signal and an active level time of the first drive signal; The power conversion device according to any one of claims 1 to 4, wherein the setting unit sets the active level time of the first drive signal from the level of the first adjustment signal by referring to the correspondence relationship.

6. the active level time of the first drive signal is represented by the sum of a constant reference time regardless of the level of the first adjustment signal and a correction time according to the level of the first adjustment signal, the control device further includes a storage unit that stores a correspondence relationship between a level of the first adjustment signal and the correction time, The power conversion device according to any one of claims 1 to 4, wherein the setting unit calculates a correction time corresponding to the first adjustment signal by referring to the correspondence relationship, and sets the active level time of the first drive signal based on the calculated correction time.

7. A method for controlling a power conversion device, comprising: The power conversion device is first and second semiconductor switching elements; a drive device that drives the first and second semiconductor switching elements in accordance with first and second drive signals, respectively; each of the first and second drive signals being switched between an active level and an inactive level; the drive device is configured to adjust a drive capability of the first semiconductor switching element in response to a first adjustment signal so that a switching speed of the first semiconductor switching element is changed; The method for controlling a power conversion device includes: outputting the first and second drive signals so that the first semiconductor switching element and the second semiconductor switching element are alternately turned on and a dead time is provided during which both the first and second semiconductor switching elements are in an off state; the outputting step includes a step of setting an active level time of the first drive signal in response to the first adjustment signal; A control method for a power conversion device, wherein the setting step includes a step of setting an active level time of the first drive signal longer when a switching speed of the first semiconductor switching element determined in response to the first adjustment signal is slow than when a switching speed of the first semiconductor switching element determined in response to the first adjustment signal is fast.

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