Memory System

Abstract

To provide a memory system capable of efficiently transmitting data to a host.SOLUTION: According to an embodiment, a memory system includes a non-volatile memory, and a controller. The controller can communicate with a host, and controls the non-volatile memory. The host includes a host memory, and a control circuit that accesses the host memory in a first size unit. When an address specified by the host as a storage position of read data read from the non-volatile memory to the host memory is not aligned with a boundary of the host memory defined for each first size, the controller transmits to the host a first packet including the read data that has a size to the boundary from the position indicated by the address and is to be stored from the position indicated by the address of the host memory, and thereafter transmits to the host a second packet that has the first size and includes the read data to be stored from the position of the boundary.SELECTED DRAWING: Figure 9

Description

Technical Field

[0001] Embodiments of the present invention relate to a memory system.

Background Art

[0002] In recent years, memory systems equipped with non-volatile memories have become widespread. For example, an SSD (solid state drive) equipped with a NAND type flash memory (NAND memory) is used as storage for information processing devices such as servers and personal computers.

[0003] NVM Express (NVMe) TM An SSD that communicates with an information processing device (host) according to a protocol compliant with the NVMe specification can perform data transmission for storing data read from the NAND memory at a position in the host memory specified by the host.

[0004] NVMe TM PCI Express (PCIe) used for transmission and reception of commands and data defined in the NVMe specification TM In an interface compliant with the specification, data is transmitted and received in units of TLP (transaction-layer packet). The TLP has a maximum length defined as MPS (max payload size). The MPS can be defined to match, for example, the unit of access by the host to the host memory. On the other hand, there is no regulation regarding the address alignment for the position in the host memory of the data transmitted by the TLP.

[0005] Therefore, the data transmitted by the TLP is not always stored in accordance with the boundary determined for each unit of access by the host to the host memory. When they do not match, much of the data transmitted by the TLP crosses the boundary of the host's access to the host memory. In this case, for example, an overhead is generated to obtain data stored across the access boundary.

Prior Art Documents

Patent Documents

[0006]

Patent Document 1

Patent Document 2

Patent Document 3

Summary of the Invention

Problems to be Solved by the Invention

[0007] One embodiment of the present invention provides a memory system capable of efficiently transmitting data to a host.

Means for Solving the Problems

[0008] According to the embodiment, the memory system includes a non-volatile memory and a controller. The controller is communicable with a host and controls the non-volatile memory. The host includes a host memory and a control circuit that accesses the host memory in units of a first size. When the address designated by the host as the storage position of the read data read from the non-volatile memory does not align with the boundary of the host memory determined for each first size, a first packet having a size from the position indicated by the address to the boundary and including the read data to be stored from the position indicated by the address of the host memory is transmitted to the host, and then a second packet having the first size and including the read data to be stored from the boundary position is transmitted to the host. In the read command After transmitting to the host, a second packet having the first size and including the read data to be stored from the boundary position is transmitted to the host. , it is generated as the first packet to be sent to the host in response to the read command among the packets containing read data, and the first packet is After transmitting the first packet including the read data to be stored from the position indicated by the address of the host memory to the host, a second packet having the first size and including the read data to be stored from the boundary position is transmitted to the host.

Brief Description of the Drawings

[0009]

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Mode for Carrying Out the Invention

[0010] Hereinafter, embodiments will be described with reference to the drawings. FIG. 1 is a diagram showing a configuration example of a memory system 1 of an embodiment. FIG. 1 also shows a configuration example of an information processing system including the memory system 1 and a host 2 connected to the memory system 1.

[0011] Memory system 1 is a storage device. Here, an example where memory system 1 is realized as an SSD is shown. Host 2 is an information processing device. Host 2 is, for example, a server or a personal computer. Memory system 1 and host 2 are connected by an interface conforming to, for example, PCIe TM specifications. Also, memory system 1 and host 2 communicate using a protocol conforming to, for example, NVMe TM specifications. In PCIe TM data is transmitted and received in units of TLPs. That is, data transmission and reception between memory system 1 and host 2 are performed in units of these TLPs.

[0012] Host 2 includes a CPU (central processing unit) 21, a host memory 22, and a memory controller 23. CPU 21 is a processing device that executes various programs. The various programs are, for example, an operating system, utility software, application software, and a driver. For example, CPU 21 executing an operating system issues a write command requesting data writing or a read command requesting data reading to memory system 1.

[0013] Host memory 22 is the main memory device of host 2. Host memory 22 is, for example, DRAM (dynamic random access memory). In host memory 22, a data buffer 22A for temporarily storing data read from memory system 1 is provided. Note that a data buffer for temporarily storing data to be written to memory system 1 may be further provided in host memory 22.

[0014] The memory controller 23 is a control device that controls access to the host memory 22. The memory controller 23 is configured, for example, as a hardware circuit. The memory controller 23 and the CPU 21 may be configured as integrated hardware.

[0015] The memory system 1 includes a controller 11 and a non-volatile memory (here, a NAND memory) 12. The controller 11 is configured, for example, as a SoC (system-on-a-chip). The functions of each part of the controller 11 can be realized by dedicated hardware, a processor that executes a program (firmware), or a combination thereof.

[0016] The controller 11 is a control device that controls the NAND memory 12 in response to commands from the host 2. For example, when the controller 11 receives a write command from the host 2, it controls the writing of data (write data) specified by the host 2 to the NAND memory 12. Also, when the controller 11 receives a read command from the host 2, it controls the reading of data (read data) specified by the host 2 from the NAND memory 12.

[0017] The controller 11 includes a PHY (physical layer) 31, a host interface control unit (host IF control unit) 32, and a NAND control unit 33.

[0018] The PHY 31 is a processing device for realizing the functions of the physical layer in the OSI (Open Systems Interconnection) layer model. The PHY 31 controls the input of serial signals from a connector connecting the controller 11 and the host 2 and the output of serial signals to the connector.

[0019] The host interface control unit 32 controls the transmission and reception of data with the host 2. For example, the host interface control unit 32 receives a plurality of TLPs containing write data from the host 2 and extracts the write data from each TLP. Further, the host interface control unit 32 includes the read data read from the NAND memory 12 in a plurality of TLPs and transmits each TLP to the host 2.

[0020] The NAND control unit 33 controls the writing of data to the NAND memory 12 and the reading of data from the NAND memory 12.

[0021] Reference numerals a1 to a4 in FIG. 1 indicate the flow from when the host 2 issues a read command until the data (read data) specified by the read command is transmitted from the memory system 1 to the host 2.

[0022] The host 2 issues a read command to the memory system 1, specifying the logical address associated with the read data and the size of the read data (a1). The logical address is, for example, a logical block address (LBA). The size of the read data is represented in units called sectors, for example. The size of a sector is, for example, 520 bytes. The read command also specifies an address indicating the position on the host memory 22 (data buffer 22A) where the read data should be stored.

[0023] The host 2 can specify a plurality of addresses as the positions in the host memory 22 where the read data should be stored. For example, even when there is no continuous free area in the data buffer 22A that is larger than the size of the read data, the host 2 can combine a plurality of free areas that are smaller than the size of the read data to secure a free area of the size of the read data in the data buffer 22A and issue a read command. Hereinafter, the address indicating the position on the host memory 22 may be referred to as the host memory address.

[0024] As a format of an address list for specifying a host memory address, PRP (physical region page entry / list) and SGL (scatter gather list) are known. PRP / SGL stores a plurality of host memory addresses each indicating the head position of a region of a certain size. The number of host memory addresses stored in PRP / SGL varies according to the size of the read data. When combining a plurality of non - contiguous free regions in the data buffer 22A as a storage destination of the read data, a plurality of PRP / SGLs can be used.

[0025] When the controller 11 of the memory system 1 receives a read command, it controls the NAND memory 12 to output read data based on a physical address indicating a position in the NAND memory 12 corresponding to the logical address specified by the read command and the size of the read data (a2). Under the control of the controller 11, the NAND memory 12 performs an output operation, and thus read data is read from the NAND memory 12 (a3).

[0026] The controller 11 transmits the read data read from the NAND memory 12 to the host 2 included in a plurality of TLPs as described above (a4). Each TLP transmitted from the memory system 1 to the host 2 also includes a host memory address. The read data transmitted from the memory system 1 to the host 2 by the TLP is stored at a position in the host memory 22 (data buffer 22A) indicated by the host memory address.

[0027] For example, a CPU 21 executing an operating system manages the data stored in the host memory 22 in units of sectors, for example. As described above, the size of a sector is, for example, 520 bytes. In other words, the host memory 22 includes a plurality of first sections each having a capacity of 520 bytes. That is, on the host memory 22, a first boundary is defined every 520 bytes.

[0028] On the one hand, the memory controller 23 accesses the data stored in the host memory 22, for example, in units of 512 bytes. The memory controller 23 generates ECC (error correction code) parity for the data stored in the host memory 22, for example, for every 512 bytes. Accordingly, in addition to the first section, the host memory 22 includes a plurality of second sections (also referred to as memory blocks), each having a capacity of 512 bytes. That is, on the host memory 22, a second boundary is defined for every 512 bytes. Hereinafter, the second boundary is referred to as the host access boundary.

[0029] For the TLP for transmitting and receiving data between the host 2 and the memory system 1, the maximum length MPS is defined in the PCIe TM specification. It is defined that MPS is a size of a power of 2 bytes. MPS can be defined to match, for example, the size of the memory block of the host memory 22. MPS is, for example, 512 (2 to the 9th power) bytes. On the other hand, the data transmitted by the TLP is not necessarily stored in the host memory 22 in accordance with the host access boundary

[0030] For example, assume a case where the data transmitted by the TLP is stored in the host memory 22 across the boundaries of two memory blocks (referred to as the first memory block and the second memory block). In this case, when the memory controller 23 stores the newly transmitted data by the TLP in the host memory 22, it has to perform two writes, namely, a write to the first memory block and a write to the second memory block. Further, the memory controller 23 has to read out the data already stored in the first memory block and regenerate the ECC parity for the first memory block in combination with the newly transmitted data by the TLP. Therefore, when the memory controller 23 writes the newly transmitted data by the TLP to the host memory 22, an overhead is generated.

[0031] When the host memory address specified by the host 2 is different from the host access boundary, the memory system 1 of the embodiment efficiently transmits read data to the host 2 by TLP. More specifically, the memory system 1 is provided with a mechanism for ensuring address alignment to the host access boundary for the read data transmitted to the host 2 by TLP. This will be described in detail below.

[0032] FIG. 2 is a diagram showing a configuration example of the host interface control unit 32 in the memory system 1 of the embodiment.

[0033] As shown in FIG. 2, the host interface control unit 32 includes a data buffer 41, a read controller 42, an address management table 43, a protocol conversion unit 44, and a pool buffer 45.

[0034] The address management table 43 is a table that manages the host memory address specified by the read command issued from the host 2. The address management table 43 has a plurality of entries. Each entry holds a list (PRP / SGL) of host memory addresses specified by one read command. A plurality of PRP / SGLs may be held in each entry. The maximum number of entries in the address management table 43 is the number of read commands that the memory system 1 can queue.

[0035] The data buffer 41 is a buffer that temporarily stores the read data (b1) sent from the NAND control unit 33. The data buffer 41 is provided, for example, in an SRAM (not shown) in the controller 11. When the data buffer 41 stores the read data, it notifies the read controller 42 to that effect (b2). Also, the data buffer 41 transmits the read data to the protocol conversion unit 44 (b3).

[0036] The read controller 42 is a control device that controls the transmission of read data to the host 2. When notified by the data buffer 41, the read controller 42 starts a process to transmit the read data stored in the data buffer 41 to the host 2. The read controller 42 acquires the host memory address specified by the host 2 as the storage destination of the read data from the address management table 43 (b4). The read controller 42 transmits a request for transmitting the read data to the host 2 to the protocol conversion unit 44 (b5). This request designates the host memory address acquired from the address management table 43 as the storage destination of the read data.

[0037] More specifically, the read controller 42 sequentially transmits a plurality of requests (b5) to the protocol conversion unit 44. Each of the plurality of requests designates a host memory address and a data size, and requests to transmit the read data (b3) sent from the data buffer 41 to the host 2 for the data size. The data size specified here is equal to or less than the MPS. Thereby, it becomes possible to transmit the read data to the host 2 in a TLP having a length equal to or less than the MPS.

[0038] The protocol conversion unit 44 is a processing device that converts the request sent from the read controller 42 into a protocol that can be received by the PHY 31. The symbol b7A indicates a command corresponding to the request (b5) sent from the read controller 42. The symbol b7B corresponds to the read data (b3) sent from the data buffer 41 and indicates the read data that is the processing target of the command indicated by the symbol b7A.

[0039] The command (b7A) and data (b7B) output from the protocol conversion unit 44 are generated based on the host memory address and data size specified by the request (b5) sent from the read controller 42. That is, the host memory address specified in the request (b5) is specified in the command (b7A), and the data (b7B) has the data size specified in the request (b5).

[0040] The read controller 42 determines the host memory address and data size specified in the request (b5) to be sent to the protocol conversion unit 44 based on the host memory address acquired from the address management table 43. The host memory address acquired from the address management table 43 is the host memory address stored in the host 2 in PRP / SGL. The host 2 (more specifically, the CPU 21) determines the host memory address according to, for example, the free status of the host memory 22 (data buffer 22A). On the other hand, the first host memory address stored in the host 2 in PRP / SGL, that is, the host memory address indicating the start position of the free area in the host memory 22 that will store the read data, does not necessarily match the host access boundary (that is, the unit of access by the memory controller 23).

[0041] When the host memory address specified by the command (b7A) sent from the protocol conversion unit 44, for example, is different from the host access boundary, the pool buffer 45 reorganizes the command (b7A) and the read data (b7B) so as to ensure the address alignment with the host access boundary. The pool buffer 45 has a control circuit 45A that controls the reorganization of these command (b7A) and read data (b7B). The symbol b7A´ indicates the command reorganized by the control circuit 45A. The symbol b7B´ indicates the read data reorganized by the control circuit 45A.

[0042] FIG. 3 is a diagram showing the processing units related to the reading of data from the memory system 1. Reference signs a1 and a4 correspond to reference signs a1 and a4 in FIG. 1.

[0043] For example, the CPU 21 that is executing the operating system issues a command to the memory system 1 to read data in a size that is an integer multiple of the sector size (a1). As described above, the sector size is, for example, 520 bytes. On the other hand, the memory system 1 transmits the data read from the NAND memory 12 in response to a command from the host 2 to the host 2 in TLP units defined by the MPS (a4). As described above, the MPS is defined to match, for example, the size of the memory block of the host memory 22. The size of the memory block is, for example, 512 bytes.

[0044] The data transmitted from the memory system 1 to the host 2 in TLP is stored at the position of the host memory 22 (data buffer 22A) indicated by the host memory address included in the TLP. The memory controller 23 accesses the data buffer 22A in which the data from the memory system 1 is stored in memory block units (c1).

[0045] Subsequently, with reference to FIG. 4, an example in which the host 2 reads 16 sectors of data from the memory system 1 will be described. Reference sign c11 indicates the first section (sector) of the host memory 22. Reference sign 12 indicates the second section (memory block) of the host memory 22.

[0046] In the example shown in FIG. 4, when issuing a read command, since there was no continuous free area for 16 sectors in the host memory 22 (data buffer 22A), the CPU 21 is assumed to have combined two free areas for 8 sectors (d1, d2) and specified them as the storage destination for the read data. Area d1 has a size of 8 sectors (520 × 8 = 4160 bytes) from the host memory address "0x1040" to the host memory address "0x2080". "0xNNNN" indicates a hexadecimal number. Also, hereinafter, unless otherwise specified, an address represented in hexadecimal is a byte address. That is, 1 byte of data is stored between the position indicated by address 0x0 and the position indicated by address 0x1. Area d2 has a size of 8 sectors (520 × 8 = 4160 bytes) from the host memory address "0x30C0" to the host memory address "0x4100". The storage destination for the first half 8 sectors of the read data is area d1, and the storage destination for the second half 8 sectors is area d2. In this case, two PRP / SGLs are created, one for area d1 and one for area d2. Each PRP / SGL stores a plurality of host memory addresses including the host memory address indicating the start of each area.

[0047] The host memory address "0x1040" indicating the start position of the area d1 is not aligned with the second boundary (host access boundary) every 512 bytes (0x0200). Therefore, a plurality of first partitions (sectors) arranged from the host memory address "0x1040" straddle the host access boundary. In FIG. 4, an example is shown in which three first partitions (sectors) arranged from the host memory address "0x1040" straddle the host access boundaries (0x1200, 0x1400, 0x1600). Similarly, the host memory address "0x30C0" indicating the start position of the area d2 is not aligned with the second boundary (host access boundary) every 512 bytes (0x0200). Therefore, a plurality of first partitions (sectors) arranged from the host memory address "0x30C0" straddle the host access boundary. In FIG. 4, an example is shown in which three first partitions (sectors) arranged from the host memory address "0x30C0" straddle the host access boundaries (0x3200, 0x3400, 0x3600).

[0048] Here, a comparative example regarding the transmission of read data to Host 2 will be described. The host interface control unit of the memory system according to the comparative example does not have a pool buffer.

[0049] FIG. 5 is a diagram showing an example in which the memory system of the comparative example transmits read data to Host 2 in a TLP. Note that FIG. 5 shows an example of one transmission of a TLP having the area d1 as a storage destination. (A) shows a memory block group arranged from the host memory address "0x1000" on the host memory 22. The first memory block [0] in the memory block group is arranged from the host memory address "0x1000". The second memory block [1] in the memory block group is arranged from the host memory address "0x1200". The third memory block [2] in the memory block group is arranged from the host memory address "0x1400". The fourth memory block [3] in the memory block group is arranged from the host memory address "0x1600". For data protection, ECC parity may be generated in units of memory blocks indicated by the symbol f1.

[0050] Here, it is assumed that the MPS is defined as 512 bytes, which is the size of the second section (memory block). The host interface control unit of the comparative example always includes the 4160-byte read data stored in the area d1 in TLPs by MPS and transmits them to Host 2 when the remaining amount of the untransmitted data is equal to or greater than the MPS (512 bytes). Therefore, the host interface control unit of the comparative example first transmits TLP#0 including 512 bytes of read data including the host memory address "0x1040" at the head of the area d1 (B1).

[0051] (As shown in (B1), the first TLP#0 includes a total of 512 bytes of read data, 448 bytes from the position of "0x1040" in memory block [0] and 64 bytes from the position of "0x1200" at the head of memory block [1]. When ECC parity is generated in units of memory blocks, the memory controller 23 of Host 2 acquires 64 bytes of already stored data from the position of "0x1000" at the head of memory block [0], combines the acquired 64 bytes of data with the 448 bytes of read data received in TLP#0, and generates ECC parity for the 512 bytes of data stored in memory block [0].

[0052] Subsequently, the host interface control unit of the comparative example transmits TLP#1 including read data of 512 bytes from the 513th byte, including the host memory address "0x1240" of the storage destination (B2). As shown in (B2), TLP#1 includes a total of 512 bytes of data, 448 bytes from the position of "0x1240" in memory block [1] and 64 bytes from the position of "0x1400" which is the start of memory block [2]. Similar to the case of memory block [0], the memory controller 23 of host 2 acquires 64 bytes of already stored data from the position of "0x1200" which is the start of memory block [1], combines the acquired 64 bytes of data with the 448 bytes of data received in TLP#1, and generates ECC parity for the 512 bytes of data to be stored in memory block [1].

[0053] Subsequently, the host interface control unit of the comparative example further transmits TLP#2 including read data of 512 bytes from the 1025th byte, including the host memory address "0x1440" of the storage destination (B3). As shown in (B3), TLP#2 includes a total of 512 bytes of data, 448 bytes from the position of "0x1440" in memory block [2] and 64 bytes from the position of "0x1600" which is the start of memory block [3]. Similar to the cases of memory block [0] and memory block [1], the memory controller 23 of host 2 acquires 64 bytes of already stored data from the position of "0x1400" which is the start of memory block [2], combines the acquired 64 bytes of data with the 448 bytes of data received in TLP#2, and generates ECC parity for the 512 bytes of data to be stored in memory block [2].

[0054] Similarly, the host interface control unit of the comparative example transmits TLP#3 to TLP#8 to host 2. The size of the read data included in TLP#8 is 64 (520×8 - 512×8) bytes.

[0055] FIG. 5(C) shows a list of TLPs transmitted to host 2 to store read data for eight sectors in area d1 (see FIG. 4) by the host interface control unit of the comparative example. Since the second boundary (host access boundary) of host memory 22 is provided every 512 (0x0200) bytes, the 512-byte read data sent by each of TLPs #0 to #7 and the 64-byte read data sent by TLP #8 cross the second boundary.

[0056] As described above, in the host interface control unit of the comparative example, when the host memory address specified by host 2 using PRP / SGL is not aligned with the second boundary (host access boundary) of host memory 22, data sent in many TLPs crosses the second boundary. When data sent in many TLPs crosses the second boundary, for example, it may cause a large amount of overhead during the generation of ECC parity.

[0057] Next, with reference to FIG. 6, an example in which the host interface control unit 32 of the embodiment transmits read data to host 2 in a TLP will be described. Note that FIG. 6 also shows an example of one transmission of a TLP having area d1 (see FIG. 4) as a storage destination. Also, similar to the above-described comparative example, (A) shows a memory block group arranged from the host memory address "0x1000" on host memory 22.

[0058] The host interface control unit 32 of the embodiment first transmits TLP #0 including 448 bytes of read data corresponding to the size from the host memory address "0x1040" at the head of area d1 to the second boundary, including the host memory address "0x1040" (B1). The host interface control unit 32 sets the size of the read data included in the TLP #0 to 448 bytes instead of 512 bytes, for example. Details will be described later.

[0059] As shown in (B1), the first TLP #0 contains read data of 448 bytes starting from the position of "0x1040" in memory block [0]. For memory block [0], similar to the comparative example, the memory controller 23 of host 2 acquires the already stored data of 64 bytes starting from the position of "0x1000" which is the start of memory block [0], combines the acquired 64-byte data with the 448-byte read data received in TLP #0, and generates ECC parity for the 512-byte data to be stored in memory block [0].

[0060] Subsequently, the host interface control unit 32 transmits TLP #1 containing read data of 512 bytes from the 449th byte to the 512th byte, including the destination host memory address "0x1200" (B2). As shown in (B2), TLP #1 contains data of 512 bytes starting from the position of "0x1200" which is the start of memory block [1]. For memory block [1], the memory controller 23 of host 2 can generate ECC parity only with the data received in TLP #1.

[0061] Subsequently, the host interface control unit 32 further transmits TLP #2 containing read data of 512 bytes from the 961st byte to the 512th byte, including the destination host memory address "0x1400" (B3). As shown in (B3), TLP #2 contains data of 512 bytes starting from the position of "0x1400" which is the start of memory block [2]. Similarly for memory block [2], the memory controller 23 of host 2 can generate ECC parity only with the data received in TLP #2.

[0062] Similarly, the host interface control unit 32 of the embodiment transmits TLP #3 to TLP #8 to host 2. The size of the read data included in TLP #8 is 128 (520×8 - 448 - 512×7) bytes.

[0063] FIG. 6(C) shows a list of TLPs transmitted to host 2 to store read data for eight sectors in area d1 (see FIG. 4) by host interface control unit 32 of the embodiment. The 448-byte read data sent in TLP#0 is stored from the host memory address “0x1040” specified by host 2. Therefore, although the start does not align with the second boundary (host access boundary) of host memory 22 (symbol f2), the end aligns with the second boundary. The 512-byte read data sent in each of TLP#1 to TLP#7 aligns with the second boundary at both the start and the end. The 128-byte read data sent in TLP#8 aligns with the second boundary at the start.

[0064] As described above, in host interface control unit 32 of the embodiment, even when the host memory address specified by host 2 using PRP / SGL does not align with the second boundary (host access boundary) of host memory 22, address alignment with the host access boundary is guaranteed for the read data transmitted to host 2 in the TLP.

[0065] FIG. 7 is a diagram showing a configuration example of pool buffer 45. Pool buffer 45 has buffer unit 52 in addition to control circuit 45A shown in FIG. 2. Control circuit 45A includes pool input control unit 51 and pool output control unit 53.

[0066] Pool input control unit 51 is a control device that controls the input of commands (b7A) and data (b7B) sent from protocol conversion unit 44. The command (b7A) includes, in addition to the host memory address, identification information that can identify the data length and the read command that requests the read data (b7B). Pool input control unit 51 stores the read data (b7B) in buffer unit 52 based on the identification information of the read command, the host memory address, and the data length indicated by the command (b7A).

[0067] The buffer unit 52 is a buffer having a plurality of entries (pool buffer entries). The buffer unit 52 is provided, for example, in an SRAM (not shown) within the controller 11. The number of pool buffer entries is equal to or greater than the number of read commands that the memory system 1 can queue at one time. The size of each pool buffer entry is equal to the MPS. The SRAM constituting the buffer unit 52 has a capacity capable of storing the entries of the pool buffer corresponding to the maximum MPS supported by the memory system 1. Each read command is associated with one of the entries. The read data read from the NAND memory 12 in response to the read command and transmitted to the host 2 by the TLP is aligned to a size that guarantees the address alignment with the host access boundary via the pool buffer entry.

[0068] The boolean input control unit 51 that stores the read data (b7B) in the buffer unit 52 first identifies the pool buffer entry of the buffer unit 52 based on the identification information of the read command indicated by the command (b7A). Next, the boolean input control unit 51 determines the storage position of the read data (b7B) in the identified pool buffer entry based on the host memory address indicated by the command (b7A). The boolean input control unit 51 determines, for example, the address indicated by the lower 9 bits of the host memory address where the read data to be transmitted by the TLP should be stored as the storage position of the read data in the pool buffer entry. That is, the pool input control unit 51 stores the read data at a position offset by the address indicated by the lower 9 bits of the host memory address from the head of the pool buffer entry. For example, when the host memory address is "0x1040", the boolean input control unit 51 stores the data (b7B) from the position offset by "0x0040" bytes from the head of the pool buffer entry.

[0069] In FIG. 7, data [N-M] indicates that the read data (b7B) requested by the M-th command (b7A) for a read command with identification information N is being referred to. For a certain read command N, a plurality of commands (b7A) can be transmitted from the protocol conversion unit 44. In this case, the value of M is incremented by 1 from 0. Also, last indicates that it is the last command (b7A) sent from the protocol conversion unit 44 for a certain read command N. That is, the command (b7A) further includes information indicating whether it is the last command. Hereinafter, last = 0 may indicate that it is not the last command (b7A), and last = 1 may indicate that it is the last command (b7A).

[0070] In the example shown in FIG. 7, in pool buffer entry 0, data [0-1], which is the read data (b7B) requested by the first command (b7A) for read command 0, and data [0-2], which is the read data (b7B) requested by the second command (b7A), are stored. Both data [0-1] and [0-2] have last = 0. Also, in pool buffer entry 1, data [1-1], which is the read data (b7B) requested by the first command (b7A) for read command 1, is stored. Data [1-1] has last = 0. Furthermore, in pool buffer entry 2, data [2-1], which is the read data (b7B) requested by the first command (b7A) for read command 2, is stored. Data [2-1] has last = 1.

[0071] The pool output control unit 53 transmits the data (b7B) stored in each pool buffer entry of the buffer unit 52 to the PHY 31 as a transmission target to the host 2 under certain conditions. At that time, the pool output control unit 53 reconstructs the command (b7A) and the data (b7B) to generate a command (b7A') and a data (b7B').

[0072] Next, the basic operation of the pool buffer 45 will be described. FIG. 8 is a diagram showing a first example of the basic operation of the pool buffer 45.

[0073] The first example is a case where the host memory address designated from the host 2 is aligned with the host access boundary.

[0074] First, a command and data [0-1] are input to the pool buffer 45. The address of the host memory where the data [0-1] specified by this command is to be stored is aligned with the host access boundary. The command input to the pool buffer 45 includes identification information (here 0) of the read command. When the read data corresponding to a certain read command is first input, the control circuit 45A allocates any pool buffer entry to the read command (A). Specifically, if there is no pool buffer entry to which the identification information of the read command included in the command is allocated, the control circuit 45A allocates a pool buffer entry that is not allocated to any read command. The control circuit 45A stores the read data in the allocated pool buffer entry based on the host memory address specified by the command (B). Note that, as described above, the command input to the pool buffer 45 also includes information indicating whether it is the last command for the read command. When the processing for the read data of the last command is completed, the control circuit 45A releases the corresponding pool buffer entry.

[0075] As described above, the control circuit 45A determines the address indicated by the lower 9 bits of the host memory address as the storage position of the read data in the pool buffer entry. Here, assume that the host memory address where the data [0-1] is to be stored is, for example, 0x1000. In this case, the data [0-1] is stored from the head of the pool buffer entry.

[0076] The commands input to the pool buffer 45 also include the size of the read data. Therefore, when there is subsequent read data following this read data, the control circuit 45A can also calculate the host memory address indicating the storage position of the subsequent read data.

[0077] When the second command and data [0-2] are input, the control circuit 45A identifies the pool buffer entry for storing this data [0-2] based on the identification information (here 0) of the read command included in the command. When the pool buffer entry is identified, the pool buffer 45 compares the host memory address indicating the storage position of the subsequent read data calculated when storing data [0-1] with the host memory address where data [0-2] should be stored. If both match, the control circuit 45A determines that data [0-2] is read data consecutive to data [0-1]. If data [0-2] is read data consecutive to data [0-1], the control circuit 45A stores data [0-2] in the pool buffer entry so as to connect it to data [0-1] (C). Similar to when storing data [0-1], the control circuit 45A calculates the host memory address indicating the storage position of the subsequent read data.

[0078] Even when the third command and data [0-3] are input, the control circuit 45A identifies the pool buffer entry for storing the read data based on the identification information (here 0) of the read command included in the command. Also, the control circuit 45A compares the host memory address indicating the storage position of the subsequent read data calculated when storing data [0-2] with the host memory address where data [0-3] should be stored. If both match, the control circuit 45A determines that data [0-3] is read data consecutive to data [0-2]. If data [0-3] is data consecutive to data [0-2], the control circuit 45A stores data [0-3] in the pool buffer entry so as to connect it to data [0-2] based on the host memory address where data [0-3] should be stored (D).

[0079] As described above, the commands input to the pool buffer 45 also include the size of the read data. Therefore, when the control circuit 45A attempts to store the read data in a pool buffer entry based on the host memory address, it can determine whether the read data fits into the pool buffer entry. Here, assume that data [0-3] does not fit into the pool buffer entry. When data [0-3] does not fit into the pool buffer entry, the control circuit 45A first stores a part of data [0-3] that fits into the pool buffer entry. At this point, the pool buffer entry contains read data for MPS from the start of data [0-1] to the middle of data [0-3]. The control circuit 45A generates a command for transmitting this MPS portion of the read data in a batch, and outputs the command and the read data to the PHY 31.

[0080] Next, the control circuit 45A calculates the host memory address corresponding to the start of the remaining part of data [0-3] that did not fit into the pool buffer entry. Based on the calculated host memory address, the control circuit 45A stores the remaining part of data [0-3] in the pool buffer entry. The remaining part of data [0-3] is stored from the start of the pool buffer entry (E).

[0081] Thereafter, until the last command is input, the operation of collecting the read data in units of MPS and generating and outputting a command for transmitting this MPS portion of the read data in a batch is repeated. When the last command is input, even if the total size of the read data corresponding to that command and the read data stored in the pool buffer entry does not reach the MPS, the control circuit 45A generates a command for transmitting these read data in a batch and outputs it to the PHY 31.

[0082] In this way, the pool buffer 45 combines, for example, read data with consecutive host memory addresses input by a plurality of commands into MPS units by storing them in pool buffer entries, and outputs the read data of the MPS units to the PHY 31 with one command.

[0083] FIG. 9 is a diagram showing a second example of the basic operation of the pool buffer 45. The second example is a case where the host memory address specified from the host 2 is not aligned with the host access boundary.

[0084] In the second example, a command and data [1-1] with a host memory address not aligned with the host access boundary are input. The control circuit 45A first allocates pool buffer entries (A). The control circuit 45A stores the data [1-1] in the allocated pool buffer entry based on the host memory address where the data [1-1] should be stored (B).

[0085] The control circuit 45A does not simply store data from the beginning of the pool buffer entry, but stores the read data from the position in the pool buffer entry corresponding to the position in the memory block based on the host memory address. Here, assume that the host memory address where the data [1-1] should be stored is 0x1040. In this case, the data [1-1] is stored from the position (g1) offset by 0x040 bytes from the beginning of the pool buffer entry. In this way, when the host memory address specified from the host 2 is not aligned with the host access boundary, the control circuit 45A stores the read data from the middle of the pool buffer entry.

[0086] When the second command and data [1-2] are input, the control circuit 45A identifies a pool buffer entry for storing this data [1-2]. Further, the control circuit 45A determines whether this data [1-2] is consecutive read data to data [1-1]. If it is consecutive read data, the control circuit 45A stores the data [1-2] in the pool buffer entry so as to connect it to the data [1-1] (C).

[0087] Even when the third command and data [1-3] are input, the control circuit 45A identifies a pool buffer entry for storing this data [1-3]. Further, the control circuit 45A determines whether this data [1-3] is consecutive read data to data [1-2]. If it is consecutive read data, the control circuit 45A stores the data [1-3] in the pool buffer entry so as to connect it to the data [1-2] (D).

[0088] Here, when the control circuit 45A attempts to store the data [1-3] in the pool buffer entry based on the host memory address, assume that the data [1-3] does not fit into the pool buffer entry. The control circuit 45A first stores a part of the data [1-3] that fits into the pool buffer entry in the pool buffer entry, generates a command for collectively transmitting the read data stored in the pool buffer entry at that time, and outputs the command and the read data to the PHY31.

[0089] The size of the read data output at this time is less than the MPS, and the host memory address corresponding to the head of this data is the host memory address specified from host 2. This host memory address is not aligned with the host access boundary. However, the host memory address corresponding to the end of this read data is aligned with the host access boundary.

[0090] Also, the remaining part of the data [1-3] that did not fit into the pool buffer entry is stored from the beginning of the pool buffer entry (E). Then, subsequent read data is output in chunks of MPS via the pool buffer entry. That is, hereafter, commands and read data are generated while ensuring alignment with the host access boundary.

[0091] In this way, the memory system 1 of the embodiment can ensure alignment with the host access boundary even when the host memory address specified from the host 2 is not aligned with the host access boundary.

[0092] FIG. 10 is a diagram showing a third example of the basic operation of the pool buffer 45. The third example is the case where discontinuous read data is detected. Discontinuous read data is read data in which the host memory address specified by the command does not match the host memory address indicating the storage position of the subsequent read data calculated at the time of storing the previous read data.

[0093] In FIG. 10, after the data [2-1] of the first command and the data [2-2] of the second command are stored in the pool buffer entry ((A) to (C)), the host memory address where the data [2-3] specified by the third command should be stored does not match the host memory address indicating the storage position of the subsequent read data calculated at the time of storing the data [2-2] (D). The symbol g2 indicates the position within the pool buffer entry where the data [2-3] should be stored, calculated from the host memory address where the data [2-3] should be stored.

[0094] When non - consecutive read data is detected, even if the size of the read data stored in the pool buffer entry is less than the MPS, the control circuit 45A generates a command for collectively transmitting the read data stored in the pool buffer entry at that time and outputs it to the PHY31. In the case of the example shown in FIG. 10, the control circuit 45A generates a command for collectively transmitting data [2 - 1] and data [2 - 2] and outputs it to the PHY31. Thereafter, data [2 - 3] is stored at the position indicated by the code g2 in the pool buffer entry.

[0095] As a result, for the read data stored in a plurality of non - consecutive regions on the host memory 22, even if the pool buffer entry is used to group the data in units of MPS, data having different regions on the host memory 22 as storage destinations will not be grouped into one TLP.

[0096] As an example in which non - consecutive read data is input, for example, as shown in FIG. 4, it is a case where host 2 sets a plurality of non - consecutive regions on the host memory 22 as storage destinations for the read data. For example, non - consecutive read data is input at the timing when the host memory address acquired by the read controller 42 from the address management table 43 switches from the host memory address stored in a certain PRP / SGL to the host memory address stored in another PRP / SGL.

[0097] FIG. 11 is a diagram showing a fourth example of the basic operation of the pool buffer 45. The fourth example is the case where the last command is detected. The last command is a command in which the information included in the command indicating whether it is the last command indicates that it is the last command.

[0098] In FIG. 11, after the data [3-1] of the first command and the data [3-2] of the second command are stored in the pool buffer entry ((A) to (C)), the case where the third command is the last command is shown (D). The last=1 indicated by the symbol h1 indicates that the third command is the last command.

[0099] When the last command is detected, even if the size of the read data stored in the pool buffer entry is less than the MPS, the control circuit 45A generates a command for collectively transmitting the read data stored in the pool buffer entry at that time and outputs it to the PHY31. In the case of the example shown in FIG. 11, the control circuit 45A generates a command for collectively transmitting the data [3-1], the data [3-2], and the data [3-3] of the third command (the last command) and outputs it to the PHY31.

[0100] Thereby, for example, due to the size of the read data stored in the pool buffer entry not reaching the MPS, the last part of the read data will not stay in the pool buffer entry forever.

[0101] Next, the exception operation of the pool buffer 45 will be described. FIGS. 12 and 13 are diagrams showing a first example of the exception operation of the pool buffer 45.

[0102] Among the commands input to the pool buffer 45, there are those having attributes such as the SGL Bit Bucket attribute, the Verify attribute, and the Error attribute.

[0103] The SGL Bit Bucket attribute is an attribute of a command corresponding to data that is specified as unnecessary from host 2 among the read data read from NAND memory 12 by a read command from host 2. For example, when host 2 reads data stored in a plurality of non - consecutive regions on NAND memory 12, host 2 can issue a plurality of read commands each targeting one of the plurality of regions. On the other hand, host 2 can also issue one read command targeting one region that includes the plurality of regions and specify that the data in the regions between the plurality of regions is unnecessary. The SGL Bit Bucket attribute is an attribute of a command corresponding to the read data specified as an unnecessary part among the read data related to the region specified in one read command. The read data of a command having the SGL Bit Bucket attribute is not transmitted to host 2.

[0104] The Verify attribute is an attribute of a command corresponding to the read data read from NAND memory 12 by a command issued by host 2 to check the validity of the data. The read data of a command having the Verify attribute is checked for validity by ECC parity but is not transmitted to host 2.

[0105] The Error attribute is an attribute of a command corresponding to the read data including an error that could not be corrected by ECC parity among the read data read from NAND memory 12 by a read command from host 2. The read data of a command having the Error attribute is not transmitted to host 2.

[0106] The read data of commands having the SGL Bit Bucket attribute, the Verify attribute, or the Error attribute are all unnecessary to be transmitted to host 2. The host interface control unit 32 has a selector 46 for discarding commands and read data having these attributes among the commands and read data output from the pool buffer 45.

[0107] Commands with SGL Bit Bucket attributes, Verify attributes, or Error attributes and their read data are discarded by selector 46. Therefore, the control circuit 45A does not perform processes such as storing in the pool buffer entry to collect MPS for the read data of commands with these attributes, and immediately outputs from the pool buffer entry.

[0108] Figures 12 and 13 show cases where commands with Verify attributes are input. Figure 12 shows an example where a command with a Verify attribute and data [4-1] longer than MPS are input. On the other hand, Figure 13 shows an example where a command with a Verify attribute and data [5-1] shorter than MPS are input. When a command with a Verify attribute is input, the control circuit 45A passes the pool buffer entry without performing the above-described processes on the data [4-1] (Figure 12), [5-1] (Figure 13) of this command, and immediately outputs the data [4-1], [5-1] from the pool buffer entry. The data [4-1], [5-1] output from the pool buffer entry are not output to PHY31 by selector 46. That is, the data [4-1], [5-1] are discarded. The same applies when commands with SGL Bit Bucket attributes or commands with Error attributes are input.

[0109] That is, in the case of read data of commands with Verify attributes, SGL Bit Bucket attributes, or Error attributes, the control circuit 45A does not perform processes such as separating with MPS for data longer than MPS, and does not perform processes such as collecting MPS for data shorter than MPS.

[0110] As a result, for data not transmitted to host 2, the control circuit 45A does not perform unnecessary processes as described above.

[0111] Figure 14 is a diagram showing a second example of the exception operation of pool buffer 45.

[0112] In the second example, normal commands and read data that do not have attributes such as the SGL Bit Bucket attribute, Verify attribute, and Error attribute are input, and in a state where this read data is stored in a pool buffer entry (FIGS. 14(A) and (B)), a command having the Verify attribute is input.

[0113] In this case, the control circuit 45A first generates and outputs a command for collectively transmitting the read data stored in the pool buffer entry even if the size of the read data stored in the pool buffer entry is less than the MPS at that time (C). After this output, the control circuit 45A outputs a command having the Verify attribute and read data. The same applies when a command having the SGL Bit Bucket attribute or a command having the Error attribute is input.

[0114] In the example shown in FIG. 14, the data [6-1] of a normal command is stored in a pool buffer entry. The size of the data [6-1] is less than the MPS. In this state, when a command having the Verify attribute is input, the control circuit 45A generates a command for transmitting the data [6-1], and outputs the command and the read data including the data [6-1] from the pool buffer entry. The data [6-1] output from the pool buffer entry is output to the PHY31 by the selector 46. Regarding the data [6-2] of the command having the Verify attribute, as described with reference to FIGS. 12 and 13, it is not output to the PHY31 by the selector 46.

[0115] As a result, for example, the read data that already needs to be transmitted to host 2 and the read data that does not need to be transmitted to host 2, which are already stored in the pool buffer entry, are not grouped together in one TLP.

[0116] As described above, even when the host memory address specified by the host 2 as the storage destination of the read data is not aligned with the host access boundary, the memory system 1 of the embodiment can ensure the address alignment with the host access boundary for the read data transmitted to the host 2. That is, the memory system 1 of the embodiment can perform efficient data transmission to the host 2.

[0117] Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the gist of the invention. These embodiments and their modifications are included in the scope and gist of the invention, and are included in the invention described in the claims and its equivalent scope.

Description of Reference Numerals

[0118] 1... Memory system, 2... Host, 11... Controller, 12... Non-volatile memory (NAND memory), 21... CPU, 22... Host memory, 22A... Data buffer, 23... Memory controller, 31... PHY, 32... Host interface control unit, 33... NAND control unit, 41... Data buffer, 42... Read controller, 43... Address management table, 44... Protocol conversion unit, 45... Pool buffer, 45A... Control circuit, 46... Selector, 51... Pool input control unit, 52... Buffer unit, 53... Pool output control unit.

Claims

1. A non-volatile memory; A controller capable of communicating with a host and controlling the non-volatile memory; Equipped with The host is A host memory; a control circuit for accessing the host memory in units of a first size; The controller: When an address specified in a read command from the host as a storage location in the host memory of the read data read from the nonvolatile memory is not aligned with a boundary of the host memory defined for each of the first sizes, generating a first packet having a size from the position indicated by the address to the boundary and including the read data to be stored from the position indicated by the address in the host memory as a first packet to be transmitted to the host in response to the read command among packets including the read data, and transmitting the first packet to the host; sending a second packet to the host having the first size and including the read data to be stored starting at the boundary; Memory system.

2. further comprising a buffer capable of storing data of the first size; the controller calculates a position in the buffer where the read data is to be stored based on the address, stores the read data in the calculated position in the buffer, and generates the first packet based on the read data stored in the position in the buffer.

2. The memory system of claim 1.

3. the controller stores the read data at a position offset from the beginning of the buffer by an amount equivalent to the lower bits of the address; 3. The memory system of claim 2.

4. the controller sequentially stores the plurality of read data in the buffer, and when the read data is stored up to the end of the buffer, outputs the plurality of read data stored in the buffer from the buffer.

3. The memory system of claim 2.

5. A non-volatile memory; A controller capable of communicating with a host and controlling the non-volatile memory; a buffer capable of storing data of a first size; Equipped with The host is A host memory; a control circuit for accessing the host memory in units of the first size; When an address specified by the host as a storage location in the host memory of the read data read from the nonvolatile memory is not aligned with a boundary of the host memory defined for each of the first sizes, after transmitting a first packet to the host, the first packet having a size from the location indicated by the address to the boundary and including the read data to be stored from the location indicated by the address in the host memory; sending a second packet to the host having the first size and including the read data to be stored starting at the boundary; calculating a position of the buffer for storing the read data based on the address, storing the read data at the calculated position in the buffer, and generating the first packet based on the read data stored at the position in the buffer; When the read data stored in the buffer is stored halfway in the buffer, and the read data stored in the buffer is to be stored in discontinuous positions in the host memory, the read data stored in the buffer is read from the non-volatile memory, and the read data stored in the buffer is output from the buffer. Memory system.

6. A non-volatile memory; A controller capable of communicating with a host and controlling the non-volatile memory; a buffer capable of storing data of a first size; Equipped with The host is A host memory; a control circuit for accessing the host memory in units of the first size; When an address specified by the host as a storage location in the host memory of the read data read from the nonvolatile memory is not aligned with a boundary of the host memory defined for each of the first sizes, after transmitting a first packet to the host, the first packet having a size from the location indicated by the address to the boundary and including the read data to be stored from the location indicated by the address in the host memory; sending a second packet to the host having the first size and including the read data to be stored starting at the boundary; calculating a position of the buffer for storing the read data based on the address, storing the read data at the calculated position in the buffer, and generating the first packet based on the read data stored at the position in the buffer; when the last read data read from the non-volatile memory in response to a read command from the host requesting transmission of the read data is stored in the buffer, outputting the read data stored in the buffer from the buffer. Memory system.

7. when the read data having a first attribute is read from the non-volatile memory in a state in which the read data is stored halfway in the buffer, the controller outputs the read data stored in the buffer from the buffer and then discards the read data having the first attribute.

7. The memory system of claim 6.

8. the read data having the first attribute is a portion of the read data read from the non-volatile memory that is designated by the host as an unnecessary portion; 8. The memory system of claim 7.

9. the read data having the first attribute is the read data read from the non-volatile memory for the purpose of checking validity; 8. The memory system of claim 7.

10. the read data having the first attribute is the read data that is read from the non-volatile memory and includes an uncorrectable error; 8. The memory system of claim 7.

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