Multi-chip stacked devices

Abstract

Examples described herein generally relate to multi-chip devices having stacked chips. In one example, the multi-chip device includes a chip stack including chips. One or more chips each include a selection circuit and a broken via pillar including a first continuous portion and a second continuous portion. The first continuous portion includes a through-substrate via and a first metal line. The second continuous portion includes a second metal line. The first metal line and the second metal line are disposed in a dielectric layer disposed on a surface of a semiconductor substrate of each chip. The first continuous portion and the second continuous portion are aligned in a direction perpendicular to the surface of the semiconductor substrate. An input node of the selection circuit is connected to one of the first metal line or the second metal line. An output node of the selection circuit is connected to the other of the first metal line or the second metal line.

Description

Technical Field

[0001] Examples of the present disclosure generally relate to multi-chip devices including stacked chips.

Background Art

[0002] Devices including modules and / or packages containing multiple integrated circuit chips have been developed. The form of such devices varies. By forming such devices, electronic devices can integrate multiple chips to form the device, and each chip can be manufactured using standard semiconductor processes and then assembled and packaged to form a larger multifunctional device. By having different chips, in some cases, semiconductor processes that are difficult to integrate can be separated, such as when a part of one chip requires a different process from another chip.

[0003] Another aspect is the ability to construct a device having chips with different functionalities (e.g., some are field programmable gate array (FPGA) chips and some are memory chips) in the same device with a smaller device size, more functionality, and lower power. The semiconductor process for chips can be more focused on giving the device a greater edge in areas such as increased chip performance, cost reduction, and increased yield in manufacturing. Other benefits can be realized by such devices.

Summary of the Invention

[0004] The examples described in this specification generally relate to multi-chip devices having chips stacked vertically. More particularly, some of the examples described in this specification relate to the structure and circuitry within a chip of a chip stack for inputting and outputting signals between chips. Some examples can, in particular, reduce the number of through substrate vias (TSVs) in a chip, reduce routing bottlenecking in a metal layer in a chip, enable flexibility in signal communication, and enable different chips in a chip stack to have the same integrated circuit and hardware.

[0005] One example described in this specification is a multi-chip device. The multi-chip device includes a chip stack. The chip stack includes a plurality of chips. Adjacent pairs of chips in the chip stack are attached to each other. One or more of the chips each include a first broken via pillar and a first selection circuit. The first broken via pillar includes a first continuous portion and a second continuous portion. The first continuous portion includes a first TSV and a first metal line. The first TSV passes through the semiconductor substrate of each chip. The first metal line is disposed within a group of dielectric layers disposed on the surface of the semiconductor substrate of each chip. The second continuous portion includes a second metal line. The second metal line is disposed within the group of dielectric layers. The first continuous portion and the second continuous portion are aligned in a direction perpendicular to the surface of the semiconductor substrate. The first continuous portion is not connected to the second continuous portion. A first input node of the first selection circuit is connected to one of the first metal line or the second metal line. An output node of the first selection circuit is connected to the other of the first metal line or the second metal line.

[0006] Another example described herein is a method of operating a multi-chip device. A first signal is received in a first selection circuit from a first continuous portion of a first broken via pillar. The first broken via pillar is in a first chip of a plurality of chips in a chip stack. Adjacent pairs of chips in the chip stack are attached to each other. A second signal is transmitted from the first selection circuit through a second continuous portion of the first broken via pillar. One of the first continuous portion and the second continuous portion includes a first TSV passing through a semiconductor substrate of the first chip. The first continuous portion and the second continuous portion are aligned in a direction perpendicular to the surface of the semiconductor substrate. The first continuous portion is not connected to the second continuous portion.

[0007] Another example described herein is a multi-chip device. The multi-chip device includes a first chip and a second chip attached to the first chip. The first chip includes a first selection circuit, a first broken via pillar, a second selection circuit, and a second broken via pillar. The first broken via pillar extends through a first semiconductor substrate of the first chip and a first group of dielectric layers on a first surface of the first semiconductor substrate. The first broken via pillar includes a first continuous portion and a second continuous portion. The first continuous portion includes a first TSV passing through the first semiconductor substrate. An output node of the first selection circuit is connected to the first continuous portion. The second continuous portion is aligned with the first continuous portion in a direction perpendicular to the first surface of the first semiconductor substrate. The second continuous portion is connected to a first input node of the first selection circuit. The second broken via pillar extends through the first semiconductor substrate and the first group of dielectric layers. The second broken via pillar includes a third continuous portion and a fourth continuous portion. The third continuous portion includes a second TSV passing through the first semiconductor substrate. The third continuous portion is connected to a first input node of the second selection circuit. The fourth continuous portion is aligned with the third continuous portion in a direction perpendicular to the first surface of the first semiconductor substrate. An output node of the second selection circuit is connected to the fourth continuous portion.

[0008] Some additional non-limiting examples of the present disclosure may be expressed as follows.

[0009] Example 1. A multi-chip device, A chip stack comprising a plurality of chips, wherein adjacent pairs of chips in the chip stack are attached to each other, and one or more of the chips each comprise a first broken via pillar and a first selection circuit, the first broken via pillar being A first continuous portion comprising a first through-substrate via (TSV) and a first metal wire, the first TSV passing through the semiconductor substrate of each chip, and the first metal wire being disposed within a group of dielectric layers disposed on the surface of the semiconductor substrate of each chip, the first continuous portion; A second continuous portion comprising a second metal wire, the second metal wire being disposed within the group of dielectric layers, the first continuous portion and the second continuous portion being aligned in a direction perpendicular to the surface of the semiconductor substrate, the first continuous portion not being connected to the second continuous portion, a first input node of the first selection circuit being connected to one of the first metal wire or the second metal wire, and an output node of the first selection circuit being connected to the other of the first metal wire or the second metal wire, the second continuous portion Comprising a chip stack Comprising a multi-chip device.

[0010] Example 2. The multi-chip device according to Example 1, wherein one or more of the chips each further comprise other circuits, and a second input node of the first selection circuit is connected to an output node of the other circuits.

[0011] Example 3. The multi-chip device according to Example 2, wherein the first metal wire or the second metal wire connected to the first input node of the first selection circuit is also connected to an input node of other circuits.

[0012] Example 4. The multi-chip device according to Example 2, wherein the first selection circuit is configured to selectively output, at the output node of the first selection circuit, a signal received from the first input node of the first selection circuit or the second input node of the first selection circuit.

[0013] Example 5. The multi-chip device according to Example 2, wherein the other circuit includes a programmable logic circuit.

[0014] Example 6. The multi-chip device according to Example 1, wherein the first input node of the first selection circuit is connected to the first metal wire, and the output node of the first selection circuit is connected to the second metal wire.

[0015] Example 7. The multi-chip device according to Example 1, wherein the first input node of the first selection circuit is connected to the second metal wire, and the output node of the first selection circuit is connected to the first metal wire.

[0016] Example 8. One or more of the chips each include a second broken via pillar and a second selection circuit, the second broken via pillar including a third continuous portion including a second TSV and a third metal wire, the second TSV passing through the semiconductor substrate of each chip and the third metal wire being disposed within a group of dielectric layers; and a fourth continuous portion including a fourth metal wire, the fourth metal wire being disposed within a group of dielectric layers, the third continuous portion and the fourth continuous portion being aligned in a direction perpendicular to the plane of the semiconductor substrate, the third continuous portion not being connected to the fourth continuous portion, an input node of the second selection circuit being connected to the third metal wire, an output node of the second selection circuit being connected to the fourth metal wire, a first input node of the first selection circuit being connected to the second metal wire, and an output node of the first selection circuit being connected to the first metal wire. The multi-chip device according to Example 1.

[0017] Example 9. The multi-chip device according to Example 1, wherein the first selection circuit includes a multiplexer, the first input node of the first selection circuit is the first input node of the multiplexer, and the output node of the first selection circuit is the output node of the multiplexer.

[0018] Example 10. A method for operating a multi-chip device, the method comprising: receiving a first signal in a first selection circuit from a first continuous portion of a first broken via pillar, the first broken via pillar being in a first chip of a plurality of chips in a chip stack, and adjacent pairs of chips in the chip stack being attached to each other; transmitting a second signal from the first selection circuit through a second continuous portion of the first broken via pillar, wherein one of the first continuous portion and the second continuous portion includes a first through-substrate via (TSV) passing through a semiconductor substrate of the first chip, the first continuous portion and the second continuous portion are aligned in a direction perpendicular to the surface of the semiconductor substrate, and the first continuous portion is not connected to the second continuous portion; and the method includes the above steps.

[0019] Example 11. The method according to Example 10, further comprising receiving the first signal in another circuit of the first chip.

[0020] Example 12. The method according to Example 10, further comprising receiving a third signal in the first selection circuit from another circuit of the first chip, and the first selection circuit selectively transmits the first signal or the third signal as the second signal.

[0021] Example 13. The method according to Example 12, further comprising configuring the first selection circuit to transmit the first signal or the third signal as the second signal.

[0022] Example 14. The method according to Example 10, wherein the first continuous portion includes the first TSV.

[0023] Example 15. The method according to Example 10, wherein the second continuous portion includes the first TSV.

[0024] Example 16. Receiving a third signal in a second selection circuit from a third continuous portion of a second broken via pillar, wherein the second broken via pillar is in a first chip, the third continuous portion includes a second TSV passing through a semiconductor substrate, the second continuous portion includes the first TSV, and receiving the third signal; Transmitting a fourth signal from the second selection circuit through a fourth continuous portion of the second broken via pillar, wherein the third continuous portion and the fourth continuous portion are aligned in a direction perpendicular to a plane of the semiconductor substrate, and the third continuous portion is not connected to the fourth continuous portion, and transmitting the fourth signal; The method according to Example 10, further comprising the above.

[0025] Example 17. A first signal is received from a second chip among a plurality of chips in a chip stack through a first continuous portion; A second signal is transmitted to a third chip among a plurality of chips in the chip stack through a second continuous portion, and the first chip is disposed between the second chip and the third chip in the chip stack; The method according to Example 10.

[0026] Example 18. A multi-chip device, A first chip, A first selection circuit; A first broken via pillar extending through a first semiconductor substrate of the first chip and a first group of dielectric layers on a first surface of the first semiconductor substrate, the first broken via pillar includes: A first continuous portion including a first through-substrate via (TSV) passing through the first semiconductor substrate, and an output node of the first selection circuit is connected to the first continuous portion; A second continuous portion aligned with the first continuous portion in a direction perpendicular to the first surface of the first semiconductor substrate, the second continuous portion being connected to the first input node of the first selection circuit comprising a first broken via pillar a second selection circuit a second broken via pillar extending through the first semiconductor substrate and a first group of dielectric layers, the second broken via pillar comprising a third continuous portion comprising a second TSV passing through the first semiconductor substrate, the third continuous portion being connected to the first input node of the second selection circuit a fourth continuous portion aligned with the third continuous portion in a direction perpendicular to the first surface of the first semiconductor substrate, the output node of the second selection circuit being connected to the fourth continuous portion comprising a second broken via pillar comprising a first chip a second chip attached to the first chip comprising a multi-chip device

[0027] Example 19. The first chip further comprises a first other circuit having an input node connected to the second continuous portion and an output node connected to the second input node of the first selection circuit a second other circuit having an input node connected to the third continuous portion and an output node connected to the second input node of the second selection circuit The multi-chip device according to Example 18

[0028] Example 20. The second chip comprises a third selection circuit a third broken via pillar extending through the second semiconductor substrate of the second chip and a second group of dielectric layers on the second surface of the second semiconductor substrate, the third broken via pillar comprising A fifth continuous portion including a third TSV passing through the second semiconductor substrate, wherein an output node of the third selection circuit is connected to the fifth continuous portion; A sixth continuous portion aligned with the fifth continuous portion in a direction perpendicular to the second surface of the second semiconductor substrate, wherein the sixth continuous portion is connected to a first input node of the third selection circuit, and the first continuous portion is connected to the sixth continuous portion; A third broken via pillar including; A fourth selection circuit; A fourth broken via pillar extending through the second semiconductor substrate and a second group of dielectric layers, the fourth broken via pillar including: A seventh continuous portion including a fourth TSV passing through the second semiconductor substrate, wherein the seventh continuous portion is connected to a first input node of the fourth selection circuit; An eighth continuous portion aligned with the seventh continuous portion in a direction perpendicular to the second surface of the second semiconductor substrate, wherein an output node of the fourth selection circuit is connected to the eighth continuous portion, and the third continuous portion is connected to the eighth continuous portion; A fourth broken via pillar including; The multi-chip device according to Example 18, including;

[0029] These and other aspects can be understood with reference to the following embodiments for carrying out the invention.

[0030] To enable a more detailed understanding of the features set forth above, a more detailed description briefly summarized above may be made with reference to the exemplary implementations shown in part in the accompanying drawings. However, it should be noted that the accompanying drawings merely illustrate typical exemplary implementations and should not be regarded as limiting the scope thereof.

Brief Description of the Drawings

[0031]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

DETAILED DESCRIPTION OF THE INVENTION

[0032] For ease of understanding, where possible, the same reference numbers are used to designate the same elements common to the figures. It is contemplated that elements of one example may be beneficially incorporated into other examples.

[0033] The examples described in this specification generally relate to multi-chip devices having chips stacked vertically. More particularly, some of the examples described in this specification relate to the structure and circuitry within a chip stack for inputting and outputting signals between chips. One or more of the chips in the chip stack can include one or more broken via pillars and respective selection circuits. A broken via pillar can include a first continuous portion and a second continuous portion aligned in a direction perpendicular to the surface of the semiconductor substrate of the chip. The first continuous portion can include, for example, (one or more) metal lines and / or (one or more) vias in (one or more) back dielectric layers on the back surface of the semiconductor substrate, through-substrate vias (TSVs) through the semiconductor substrate, and (one or more) metal lines and / or (one or more) vias in (one or more) front dielectric layers on the front surface of the semiconductor substrate. The second continuous portion can include, for example, (one or more) metal lines and / or (one or more) vias in (one or more) front dielectric layers on the front surface of the semiconductor substrate. The first continuous portion is not connected to the second continuous portion.

[0034] The selection circuit is connected between the first continuous portion and the second continuous portion. One of the first continuous portion and the second continuous portion can be connected to a first input node of the selection circuit and further to an input node of some other circuit of the chip. A second input node of the selection circuit can be connected to an output node of another circuit of the chip. The other of the first continuous portion and the second continuous portion is connected to an output node of the selection circuit.

[0035] The broken via pillar and the selection circuit can enable signals to be received, for example, from a chip above or below in a chip stack, and to be output, for example, to a chip below or above in the chip stack respectively, by the same broken via pillar. In some cases, for example, a signal received from a chip above or below can be passed through the broken via pillar and output, for example, to a chip below or above respectively. Such a structure and selection circuit can reduce the number of TSVs in a chip, for example, by half. Previously, via pillars including TSVs were dedicated to input signals or output signals. Some examples described herein enable input signals and output signals to share a broken via pillar (e.g., within the same area of a chip), which can reduce the total number of TSVs for input and output signals by half. This can reduce routing bottlenecking in the metal layers of a chip. Further, the broken via pillar can enable flexibility in signal communication and can enable different chips in a chip stack to have the same integrated circuit (IC) and hardware, which can reduce the number of variants of chips to be designed and taped out. Still further, the control of the configurability of the broken via pillar in some examples can be simplified, for example, compared to a tri-state buffer solution. Aspects of these and other examples are described below. As will be readily understood by those skilled in the art upon reading this disclosure, additional or other benefits can be achieved by various examples.

[0036] Various features are described below with reference to the figures. Note that the figures may or may not be drawn to scale, and that elements of similar structure or function are represented throughout the figures by like reference numerals. Note that the figures are only intended to facilitate the description of the features. The figures are not intended as an exhaustive description of the claimed invention or as a limitation on the scope of the claimed invention. Further, the examples shown need not show all aspects or advantages. An aspect or advantage described with respect to a particular example is not necessarily limited to that example and may be implemented in any other example, even if not so shown or explicitly described as such. Further, the methods described herein may be described in a particular order of operation, but other methods according to other examples may be implemented in various other orders, with more or fewer operations (e.g., including different serial or parallel implementations of various operations).

[0037] FIG. 1 is a structure of a multi-chip device according to some examples. The multi-chip device of FIG. 1 includes a chip stack including a base chip 102 and fabric chips 104, 106, 108. The base chip 102 and the fabric chips 104-108 are described herein as examples. Different chips are described herein as being or including various ICs or components (e.g., fabric, base, programmable logic, etc.), but the aspects described herein may generally be applicable to chips of multi-chip devices having any type of IC or component.

[0038] In the multi-chip device of FIG. 1, the fabric chips 104-108 are arranged downward with their active side or front side facing the base chip 102, and the base chip 102 is arranged upward with its active side or front side facing the fabric chips 104-108. In other multi-chip devices, an intermediate fabric chip is arranged upward with its active side or front side away from the base chip 102, a distal fabric chip is arranged downward with its active side or front side facing the base chip 102, and the base chip 102 is arranged upward with its active side or front side facing the fabric chips 104-108. Various other multi-chip devices can have different structures, different numbers of chips, additional components, and so on.

[0039] Generally, the chips 102-108 are stacked to form a chip stack in the multi-chip device. In some examples, the chips 102-108 are stacked to form an active die-on-active die (AoA) device. In some examples, more or fewer chips can be included in the chip stack. For example, the multi-chip device can have two chips, such as a base chip and a fabric chip, or two fabric chips. In other examples, the multi-chip device can have three chips, four chips, five chips, and so on.

[0040] Each of chips 102 - 108 includes respective semiconductor substrates 112, 114, 116, 118 and respective (one or more) front dielectric layers 122, 124, 126, 128 on the front surfaces of the respective semiconductor substrates 112 - 118. The (one or more) front dielectric layers 122 - 128 include metallization (e.g., metal lines and / or vias) (shown but not specifically numbered) formed therein that can electrically connect various components in the IC. Each of chips 102 - 106 includes respective (one or more) back dielectric layers 132, 134, 136 on the back surfaces of the respective semiconductor substrates 112 - 116. The (one or more) back dielectric layers 132 - 136 include metallization (e.g., metal lines and / or vias) (shown but not specifically numbered) formed therein that can electrically connect various components in the IC. As shown, the metallization in the (one or more) front dielectric layers 124, 126 of fabric chips 104, 106 connects to respective circuit regions 143, 145 of fabric chips 104, 106, which will be described in more detail below in the context of subsequent figures.

[0041] Each of the semiconductor substrates 112-118 of chips 102-108 includes transistors 142, 144, 146, 148 formed, for example, on and / or in the front surfaces of the respective semiconductor substrates 112-118. Transistors 142-148 and any other components can be connected to the metallization in the (one or more) front dielectric layers 122-128. Transistors 144, 146 are shown in the respective circuit regions 143, 145 of fabric chips 104, 106, but transistors 144, 146 and / or other transistors can be outside the circuit regions 143, 145. Each of the semiconductor substrates 112-116 of the respective chips 102-106 has (one or more) backside through-substrate vias (TSVs) 162, 164, 166 therethrough, which can electrically connect the metallization in the (one or more) front dielectric layers 122-126 to the metallization in the (one or more) back dielectric layers 132-136 of the respective chips 102-106.

[0042] Front bond pads 152, 154, 156, 158 (e.g., metal (e.g., Cu) bond pads) are formed in the respective (one or more) front dielectric layers 122-128 at the outer surfaces distal from the respective semiconductor substrates 112-118. The front bond pads 152-158 can be arranged to form a respective chip-to-chip interface. The front bond pads 152-158 are connected to the metallization in the respective (one or more) front dielectric layers 122-128. Back bond pads 174, 176 (e.g., metal (e.g., Cu) bond pads) are formed in the respective (one or more) back dielectric layers 134, 136 of fabric chips 104, 106 at the outer surfaces distal from the respective semiconductor substrates 114, 116. The back bond pads 174, 176 can be arranged to form a respective chip-to-chip interface. The back bond pads 174, 176 are connected to the metallization in the respective (one or more) back dielectric layers 134, 136.

[0043] External connector backside pads 172 (e.g., metal (e.g., aluminum) pads) are formed in the (one or more) backside dielectric layers 132 of the base chip 102 at an outer surface distal from the semiconductor substrate 112 of the base chip 102. The external connector backside pads 172 are connected to metallization in the (one or more) backside dielectric layers 132 of the base chip 102. A passivation layer 180 is formed on the outer surface distal from the semiconductor substrate 112 of the base chip 102, and each opening therethrough exposes the external connector backside pads 172. External connectors 182 (e.g., controlled collapse chip connection (C4), microbump, etc.) are formed on respective external connector backside pads 172 through the openings in the passivation layer 180.

[0044] The external connectors 182 can be attached to a package substrate. The package substrate can further be attached to, for example, a printed circuit board (PCB) to attach the package substrate (and thus the multi-chip device) to the PCB. Various other components can be included in the multi-chip device. For example, an interposer, a sealing material (such as a molded underfill (MUF)), etc. can be included in the multi-chip device. Those skilled in the art will readily envision various modifications that can be made to the multi-chip device.

[0045] Chips 102-108 are joined together (e.g., by a hybrid bond using metal-to-metal and oxide-to-oxide bonding) to form a chip stack. The base chip 102 is joined to the fabric chip 104 front side to front side, and thus the front bond pads 152 and the outer surface of one or more front dielectric layers 122 of the base chip 102 are joined to the front bond pads 154 and the outer surface of one or more front dielectric layers 124 of the fabric chip 104. The fabric chip 104 is joined to the fabric chip 106 backside to front side, and thus the back bond pads 174 and the outer surface of one or more back dielectric layers 134 of the fabric chip 104 are joined to the front bond pads 156 and the outer surface of one or more front dielectric layers 126 of the fabric chip 106. The fabric chip 106 is joined to the fabric chip 108 backside to front side, and thus the back bond pads 176 and the outer surface of one or more back dielectric layers 136 of the fabric chip 106 are joined to the front bond pads 158 and the outer surface of one or more front dielectric layers 128 of the fabric chip 108.

[0046] Other arrangements of the junctions may be implemented. For example, the base chip 102 may be joined to the fabric chip 104 front side to backside, and thus, the front bond pads 152 and the outer surface of the (one or more) front dielectric layers 122 of the base chip 102 are joined to the back bond pads 174 and the outer surface of the (one or more) back dielectric layers 134 of the fabric chip 104. The fabric chip 104 may be joined to the fabric chip 106 front side to backside, and thus, the front bond pads 154 and the outer surface of the (one or more) front dielectric layers 124 of the fabric chip 104 are joined to the back bond pads 176 and the outer surface of the (one or more) back dielectric layers 136 of the fabric chip 106. The fabric chip 106 may be joined to the fabric chip 108 front side to front side, and thus, the front bond pads 156 and the outer surface of the (one or more) front dielectric layers 126 of the fabric chip 106 are joined to the front bond pads 158 and the outer surface of the (one or more) front dielectric layers 128 of the fabric chip 108.

[0047] In other examples, the chips 102 - 108 may be attached to each other using external connectors (such as micro - bumps, solder, etc.). In some examples, some of the chips 102 - 108 may be attached to each other by external connectors, and others of the chips may be joined to each other without the use of external connectors. Any substitution of joining and use of external connectors may be implemented.

[0048] Any of the chips in the chip stack can include a Z-interface circuit. The Z-interface circuit can be configurable and can enable communication of signals between the chips in the chip stack. The Z-interface circuit can include a selection circuit and a broken via pillar including a TSV. The broken via pillar is connected from the selection circuit to transmit a signal to an upper chip or a lower chip. The signal from the selection circuit can be selectively (i) a signal transmitted from the broken via pillar and received by the selection circuit, or (ii) a signal transmitted from another circuit on the chip and received by the selection circuit. In some examples, the broken via pillar is broken in the sense that the broken via pillar may not be continuously connected through the metallization of each (one or more) front dielectric layer of the chip, and in the sense that the continuous portion of the broken via pillar is connected to the intervening selection circuit. Additional details of the Z-interface circuit are described below. Any of chips 102-108 can include a Z-interface circuit, but in some examples, the distal fabric chip 108 can omit the TSV and / or the metallization in the back dielectric layer since the distal fabric chip 108 may not receive backside processing.

[0049] In some examples, each of the fabric chips 104-108 can include a processing IC. The processing ICs of the fabric chips 104-108 can generally be the same IC. The hardware topology, architecture, and layout of the fabric chips 104-108 can be the same among the fabric chips 104 in some examples, except that the distal fabric chip 108 can omit components formed by backside processing such as backside TSVs, (one or more) backside dielectric layers, and / or metallization in the (one or more) backside dielectric layers. In some examples, the processing ICs of the fabric chips 104-108 can include one or more programmable logic regions (e.g., the fabric of an FPGA), which can have the same hardware topology, architecture, and layout among the fabric chips 104-108. Having a Z interface in the fabric chips 104-108 can enable chips that receive the same frontside processing to be integrated in a multi-chip device while allowing flexibility in how the fabric chips 104-108 are interconnected.

[0050] In other examples, the chips 102-108 can each be a different IC or can include different ICs, or can have any combination of including the same IC and / or different ICs. For example, any of the fabric chips 104-108 can be a processing IC or memory, or can include a processing IC or memory. In some examples, chip 108 is an ASIC. Any of the chips 102-108 can generally be referred to as an active chip.

[0051] FIG. 2 is a block diagram of a circuit diagram showing the ICs of the chip stack of the multi-chip device of FIG. 1 according to some examples. In the illustrated example, the multi-chip device is a multi-chip programmable device. The circuit diagram can be implemented in the multi-chip device of FIG. 1, for example, regardless of the orientation of the fabric chips 104, 106.

[0052] In the illustrated example, the base chip 102 includes a base IC on the base chip 102, which can be a System-on-Chip (SoC). The fabric chips 104, 106, 108 each include a respective programmable logic (PL) IC 224, 226, 228, which in some examples can be the same IC and have the same hardware layout and topology. These ICs are provided as an exemplary implementation. (For example, other ICs with other hard IP blocks) can be implemented on the chip. The fabric chips 104, 106, 108 further include respective Z interfaces 234, 236, 238.

[0053] The base IC on the base chip 102 includes a processing system 202, an input / output circuit (IO) 204, an IP core circuit 206, a network-on-chip (NoC) 210, and a Z interface 232. The processing system 202 can be or include any of a variety of different processor types and numbers of processor cores. For example, the processing system 202 can be implemented as an individual processor, for example, as a single core capable of executing program instruction code. In another example, the processing system 202 can be implemented as a multi-core processor. The processing system 202 can be implemented using any of a variety of different types of architectures. Exemplary architectures that can be used to implement the processing system 202 can include the ARM processor architecture, the x86 processor architecture, the graphics processing unit (GPU) architecture, the mobile processor architecture, the reduced instruction set computer (RISC) architecture (e.g., RISC-V), or other suitable architectures capable of executing computer-readable program instruction code.

[0054] The input / output circuit 204 can include an Extreme Performance Input / Output (XPIO), a multi-gigabit transceiver (MGT), a high-bandwidth memory (HBM) interface, an analog-to-digital converter (ADC), a digital-to-analog converter (DAC), or any other input / output block. The input / output circuit 204 can be configured to receive and / or transmit signals from and / or to circuits outside the multi-chip device. The IP core circuit 206 can include a memory controller (such as a double data rate (DDR) memory controller, a high-bandwidth memory (HBM) memory controller, etc.), a peripheral component interconnect express (PCIe) interface, a cache coherent interconnect for accelerators (CCIX) interface, an Ethernet core (such as a media access controller (MAC)), a forward error correction (FEC) block, and / or any other hardened circuit. Either the input / output circuit 204 and / or the IP core circuit 206 can be programmable.

[0055] The NoC 210 includes a programmable network 212 and a NoC Peripheral Interconnect (NPI) 214. The programmable network 212 communicatively couples a subsystem of the base IC on the base chip 102 and any other circuits to each other. The programmable network 212 includes NoC packet switches and interconnecting lines that connect the NoC packet switches. Each NoC packet switch performs switching of NoC packets in the programmable network 212. The programmable network 212 has interface circuits at the edges of the programmable network 212. The interface circuits include a NoC Master Unit (NMU) and a NoC Slave Unit (NSU). Each NMU is an ingress circuit that connects a master circuit to the programmable network 212, and each NSU is an egress circuit that connects the programmable network 212 to a slave endpoint circuit. The NMU is communicatively coupled to the NSU via the NoC packet switches and interconnecting lines of the programmable network 212. The NoC packet switches are connected to each other and are connected to the NMU and the NSU through the interconnecting lines to implement a plurality of physical channels in the programmable network 212. The NoC packet switches, the NMU, and the NSU each include a register block that determines the operation of the respective NoC packet switch, NMU, or NSU.

[0056] NPI214 includes circuit elements for writing to register blocks that determine the functionality of the NMU, NSU, and NoC packet switches. NPI214 includes a peripheral interconnect coupled to the register blocks for programming it to set the functionality. The register blocks in the NMU, NSU, and NoC packet switches of programmable network 212 support interrupts, quality of service (QoS), error handling and reporting, transaction control, power management, and address mapping control. NPI214 can include an NPI root node (e.g., a platform management controller (PMC) of processing system 202) that exists on processing system 202, an interconnected NPI switch connected to the NPI root node, and a protocol block connected to the interconnected NPI switch and the corresponding register block. NPI214 can be used to program any programmable circuit of the base IC on base chip 102. For example, NPI214 can be used to program any programmable input / output circuit 204 and / or IP core circuit 206.

[0057] The Z interface 232 can include active circuitry such as buffers and / or selection circuitry for driving signals. The Z interface 232 provides an interface that includes via metal lines and vias in a metallization layer to a chip on top of base chip 102 and / or a substrate (e.g., a package substrate) under base chip 102 for processing system 202, input / output circuit 204, IP core circuit 206, and programmable network 212 of NoC 210. Additionally, the Z interface 232 can provide a pass-through interface through base chip 102.

[0058] The various subsystems and circuits of the base IC on the base chip 102 can be communicatively coupled. As shown, the processing system 202, the input / output circuit 204, and the IP core circuit 206 are connected to the NoC 210 (e.g., to the programmable network 212) and are thus communicatively coupled to each other. The processing system 202 is further connected to the NPI 214 to communicate configuration data to the various programmable components on the base chip 102. The processing system 202 is further connected to the programmable network 212 of the NoC 210 to communicate configuration data to the chips on top of the base chip 102. The programmable network 212 of the NoC 210 is connected to the Z interface 232 such that data such as transaction data and configuration data can be communicated to another chip through the Z interface 232. Each of the processing system 202, the input / output circuit 204, and the IP core circuit 206 is connected to the Z interface 232 for communication with the programmable logic in the PL ICs 224, 226, 228 in the fabric chips 104, 106 on top, for example. Other communication mechanisms such as direct connections can be implemented between the various subsystems and circuits.

[0059] Each of the PL ICs 224 - 228 on each of the fabric chips 104 - 108 includes one or more programmable logic regions. A programmable logic region is a logic circuit element that can be programmed to perform a specified function. The programmable logic region can include any number or arrangement of programmable tiles. As an example, the programmable logic region can be implemented as the fabric of an FPGA. For example, the programmable logic region can include any number of configurable logic blocks (CLBs), look-up tables (LUTs), digital signal processing blocks (DSPs), random access memory blocks (BRAMs), and the like. Each of the programmable tiles (e.g., CLB, LUT, DSP, BRAM, etc.) can include one or more programmable interconnect elements. The various respective types of programmable tiles can be arranged in rows and / or columns, and the associated programmable interconnect elements can be connected to adjacent programmable logic elements in the same column and row, for example. The programmable interconnect elements can form an interconnect network of the programmable logic region. Any logic and connections can be implemented by the programmable logic region by programming or configuring any of the programmable tiles of the programmable logic region.

[0060] Each of the Z interfaces 234 - 238 on each of the fabric chips 104 - 108 can include active circuitry such as buffers and / or selection circuitry for driving signals. The Z interfaces 234 - 238 provide an interface including via metal lines and vias in a metallization layer for each of the PL ICs 224 - 228 to communicate with chips above and / or below each of the fabric chips 104 - 108. Further, the Z interfaces 234 - 238 can provide a pass-through interface through each of the fabric chips 104 - 108. Configuration data for the PL ICs 224 - 228 can be transmitted through a passive connection, for example, through the Z interfaces 234 - 238.

[0061] Each of the PL ICs 224-228 can include a configuration interconnect, including a configuration frame (CFRAME) driver. The CFRAME driver can be, or can include, control logic for communicating configuration data (such as a bitstream) for configuring programmable logic. Each programmable logic region can be configured or programmed by configuration data received via the Z interface 232, the corresponding Z interfaces 234-238 of the respective fabric chips 104-108, and any intervening Z interfaces 234, 236. For example, the processing system 202 (e.g., the PMC of the processing system 202) can send configuration data to the respective PL ICs 224-228 via the programmable network 212 and the Z interface 232 of the NoC 210. In some examples, the configuration interconnect (e.g., including the CFRAME driver) can direct configuration data to appropriate programmable tiles and can control configuring such programmable tiles.

[0062] FIG. 3 shows a simplified structure of at least respective portions of the Z interfaces 234, 236 of the fabric chips 104, 106, according to some examples. Although described with respect to the fabric chips 104, 106, the aspects of the Z interfaces described are applicable to the Z interface 232 of the base chip 102 and / or the Z interface 238 of the fabric chip 108 (e.g., without components formed by backside processing). Note that FIG. 3 does not show passive pass-through connections that may be present in the Z interfaces. FIG. 3 shows exemplary broken via pillars and selection circuits that may be present in the Z interfaces.

[0063] The Z interface 234 includes a broken via pillar 302, a selection circuit 312, a broken via pillar 304, and a selection circuit 314. The Z interface 236 includes a broken via pillar 306, a selection circuit 316, a broken via pillar 308, and a selection circuit 318.

[0064] Each of the broken via pillars generally includes a first continuous portion and a second continuous portion. The first continuous portion and the second continuous portion are aligned in a direction normal (e.g., vertical) to the surface (e.g., front or back surface) of the semiconductor substrate of the chip on which the respective broken via pillar is disposed. The first continuous portion generally includes a backside bond pad, one or more metal lines and / or one or more vias in one or more backside dielectric layers, a TSV, and one or more metal lines and / or one or more vias in one or more front side dielectric layers, which are continuously connected to each other. The second continuous portion generally includes one or more metal lines and / or one or more vias in one or more front side dielectric layers and a front side bond pad, which are continuously connected to each other.

[0065] As shown in the figure, the broken via pillar 302 in the fabric chip 104 includes a first continuous portion 302-1 and a second continuous portion 302-2. The first continuous portion 302-1 includes a backside bond pad 174-1, metal lines and vias (shown but not particularly identified) in the (one or more) backside dielectric layers 134, a backside TSV 164-1, metal lines 302x in the (one or more) frontside dielectric layers 124, and metal lines and vias (shown but not particularly identified) in the (one or more) frontside dielectric layers 124 between the backside TSV 164-1 and the metal lines 302x, which are continuously connected to each other. The second continuous portion 302-2 includes metal lines 302y in the (one or more) frontside dielectric layers 124, a frontside bond pad 154-1, and metal lines and vias (shown but not particularly identified) in the (one or more) frontside dielectric layers 124 between the frontside bond pad 154-1 and the metal lines 302y.

[0066] As shown in the figure, the broken via pillar 304 in the fabric chip 104 includes a first continuous portion 304-1 and a second continuous portion 304-2. The first continuous portion 304-1 includes a backside bond pad 174-2, metal lines and vias (shown but not particularly identified) in the (one or more) backside dielectric layers 134, a backside TSV 164-2, metal lines 304x in the (one or more) frontside dielectric layers 124, and metal lines and vias (shown but not particularly identified) in the (one or more) frontside dielectric layers 124 between the backside TSV 164-2 and the metal lines 304x, which are continuously connected to each other. The second continuous portion 304-2 includes metal lines 304y in the (one or more) frontside dielectric layers 124, a frontside bond pad 154-2, and metal lines and vias (shown but not particularly identified) in the (one or more) frontside dielectric layers 124 between the frontside bond pad 154-2 and the metal lines 304y.

[0067] As shown in the figure, the broken via pillar 306 in the fabric chip 106 includes a first continuous portion 306-1 and a second continuous portion 306-2. The first continuous portion 306-1 includes the backside bond pad 176-1, metal lines and vias (shown but not particularly identified) in the (one or more) backside dielectric layers 136, the backside TSV 166-1, the metal line 306x in the (one or more) frontside dielectric layers 126, and metal lines and vias (shown but not particularly identified) in the (one or more) frontside dielectric layers 126 between the backside TSV 166-1 and the metal line 306x, and these are continuously connected to each other. The second continuous portion 306-2 includes the metal line 306y in the (one or more) frontside dielectric layers 126, the frontside bond pad 156-1, and metal lines and vias (shown but not particularly identified) in the (one or more) frontside dielectric layers 126 between the frontside bond pad 156-1 and the metal line 306y.

[0068] As shown in the figure, the broken via pillar 308 in the fabric chip 106 includes a first continuous portion 308-1 and a second continuous portion 308-2. The first continuous portion 308-1 includes the backside bond pad 176-2, metal lines and vias (shown but not particularly identified) in the (one or more) backside dielectric layers 136, the backside TSV 166-2, the metal line 308x in the (one or more) frontside dielectric layers 126, and metal lines and vias (shown but not particularly identified) in the (one or more) frontside dielectric layers 126 between the backside TSV 166-2 and the metal line 308x, and these are continuously connected to each other. The second continuous portion 308-2 includes the metal line 308y in the (one or more) frontside dielectric layers 126, the frontside bond pad 156-2, and metal lines and vias (shown but not particularly identified) in the (one or more) frontside dielectric layers 126 between the frontside bond pad 156-2 and the metal line 308y.

[0069] Generally, a broken via pillar on a chip can be connected to a broken via pillar on another chip. As shown, the broken via pillar 302 is connected to the broken via pillar 306 by bonding and connecting the backside bond pad 174-1 of the fabric chip 104 to the front side bond pad 156-1 of the fabric chip 106. Similarly, the broken via pillar 304 is connected to the broken via pillar 308 by bonding and connecting the backside bond pad 174-2 of the fabric chip 104 to the front side bond pad 156-2 of the fabric chip 106. The broken via pillars 302, 304 can similarly be connected to the respective broken via pillars of the base chip 102 (e.g., by the front side bond pads 154-1, 154-2), and the broken via pillars 306, 308 can be connected to the respective broken via pillars of the fabric chip 108 (e.g., by the backside bond pads 176-1, 176-2).

[0070] Generally, each of the broken via pillars 302, 304, 306, 308 is not continuously connected through the metallization of the respective (one or more) front dielectric layers 124, 126 of the fabric chips 104, 106. More specifically, the respective first continuous portions 302-1, 304-1, 306-1, 308-1 of the broken via pillars 302, 304, 306, 308 are not connected to the respective second continuous portions 302-2, 304-2, 306-2, 308-2 of the broken via pillars 302, 304, 306, 308. For example, there are no metal lines 302x, 302y in the broken via pillar 302 and no vias directly connecting them, no metal lines 304x, 304y in the broken via pillar 304 and no vias directly connecting them, no metal lines 306x, 306y in the broken via pillar 306 and no vias directly connecting them, and no metal lines 308x, 308y in the broken via pillar 308 and no vias directly connecting them.

[0071] The selection circuit is connected between the first continuous portion and the second continuous portion of the broken via pillar. Each of the selection circuits 312, 314, 316, 318 can include any logic circuit. As shown in the figure, each of the selection circuits 312, 314, 316, 318 includes its respective multiplexer 312a, 314a, 316a, 318a. As shown in the figure, the metal line 302y of the second continuous portion 302-2 is connected to the input node of the multiplexer 312a, and the output node of the multiplexer 312a is connected to the metal line 302x of the first continuous portion 302-1. The metal line 304x of the first continuous portion 304-1 is connected to the input node of the multiplexer 314a, and the output node of the multiplexer 314a is connected to the metal line 304y of the second continuous portion 304-2. The metal line 306y of the second continuous portion 306-2 is connected to the input node of the multiplexer 316a, and the output node of the multiplexer 316a is connected to the metal line 306x of the first continuous portion 306-1. The metal line 308x of the first continuous portion 308-1 is connected to the input node of the multiplexer 318a, and the output node of the multiplexer 318a is connected to the metal line 308y of the second continuous portion 308-2. In some examples, the selection circuits can be connected between different portions of the broken via pillar by the metal lines of the broken via pillar in each of the respective metal layers having two or more metal layers disposed therebetween.

[0072] The metal line of the first continuous portion or the second continuous portion of the broken via pillar is connected to the input node of another circuit (e.g., PL IC) of the chip. As shown in the figure, the metal line 302y of the second continuous portion 302-2 is further connected to the input node of the PL IC 224, the metal line 304x of the first continuous portion 304-1 is further connected to the input node of the PL IC 224, the metal line 306y of the second continuous portion 306-2 is further connected to the input node of the PL IC 226, and the metal line 308x of the first continuous portion 308-1 is further connected to the input node of the PL IC 226.

[0073] The output nodes of other circuits (e.g., PLICs) are connected to the input nodes of the selection circuit. As shown, the output node of PLIC 224 is connected to the input node of multiplexer 312a, and another output node of PLIC 224 is connected to the input node of multiplexer 314a. The output node of PLIC 226 is connected to the input node of multiplexer 316a, and another output node of PLIC 226 is connected to the input node of multiplexer 318a.

[0074] Although not shown, the selection circuit can include a configuration memory (e.g., a static random access memory (SRAM)) for configuring the selection circuit. For example, a logic high or logic low value can be written to a configuration memory cell (e.g., via a passive Z interface connection to the processing system 202), and the configuration memory cell is connected to a control input node of the selection circuit (e.g., a multiplexer) to selectively configure the selection circuit based on the logic high or logic low value written to the configuration memory cell. In some examples, the control input node of the selection circuit can be connected to other circuit elements that can dynamically control the configuration of the selection circuit during operation of the multi-chip device.

[0075] During operation, a signal can be received by the fabric chip 104 at the front bond pad 154-1 and transmitted to the metal line 302y through the second continuous portion 302-2 of the broken via pillar 302. The signal is then transmitted to both the input node of the multiplexer 312a and the input node of the PL IC 224. The PL IC 224 can process the received signal or another signal, and can output a signal, which may or may not be based on the received signal, to the other input nodes of the multiplexer 312a. The multiplexer 312a selectively outputs the signal received from the metal line 302y or the signal received from the PL IC 224 based on the signal received at the control input node of the multiplexer 312a. The signal output by the multiplexer 312a is transmitted to the metal line 302x and further transmitted to the back bond pad 174-1 through the first continuous portion 302-1 of the broken via pillar 302. In some scenarios, for example, a signal received from the base chip 102 can be transmitted to the fabric chip 106 through the broken via pillar 302 and the selection circuit 312, and can be transmitted to the PL IC 224 through the second continuous portion 302-2 of the broken via pillar 302. In some scenarios, for example, a signal received from the base chip 102 can be transmitted to the PL IC 224 through the second continuous portion 302-2 of the broken via pillar 302, can be processed by the PL IC 224, and a response signal based on the received signal can be output by the PL IC 224 and transmitted to the fabric chip 106 through the selection circuit 312 and the first continuous portion 302-1 of the broken via pillar 302. In some scenarios, for example, a signal received from the base chip 102 can be transmitted to the PL IC 224 through the second continuous portion 302-2 of the broken via pillar 302, and a signal that may be unrelated to the received signal can be output by the PL IC 224 and transmitted to the fabric chip 106 through the selection circuit 312 and the first continuous portion 302-1 of the broken via pillar 302.

[0076] During operation, a signal can be received by the fabric chip 104 at the backside bond pad 174-1 and transmitted through the first continuous portion 304-1 of the broken via pillar 304 to the metal wire 304x. The signal is then transmitted to both the input node of the multiplexer 314a and the input node of the PL IC 224. The PL IC 224 can process the received signal or another signal, and can output a signal, which may or may not be based on the received signal, to the other input node of the multiplexer 314a. The multiplexer 314a selectively outputs the signal received from the metal wire 304x or the signal received from the PL IC 224 based on the signal received at the control input node of the multiplexer 314a. The signal output by the multiplexer 314a is transmitted to the metal wire 304y and further transmitted to the front side bond pad 154-2 through the second continuous portion 304-2 of the broken via pillar 304. In some scenarios, for example, a signal received from the fabric chip 106 can be transmitted to the base chip 102 through the broken via pillar 304 and the selection circuit 314, and can be transmitted to the PL IC 224 through the first continuous portion 304-1 of the broken via pillar 304. In some scenarios, for example, a signal received from the fabric chip 106 can be transmitted to the PL IC 224 through the first continuous portion 304-1 of the broken via pillar 304, can be processed by the PL IC 224, and a response signal based on the received signal can be output by the PL IC 224 and transmitted to the base chip 102 through the selection circuit 314 and the second continuous portion 304-2 of the broken via pillar 304. In some scenarios, for example, a signal received from the fabric chip 106 can be transmitted to the PL IC 224 through the first continuous portion 304-1 of the broken via pillar 304, and a signal that may be unrelated to the received signal can be output by the PL IC 224 and transmitted to the base chip 102 through the selection circuit 314 and the second continuous portion 304-2 of the broken via pillar 304.

[0077] The broken via pillars 306, 308, and the selection circuits 316, 318 can each operate in the same manner as the broken via pillars 302, 304, and the selection circuits 312, 314. Those skilled in the art can easily understand such operations, and thus the description of such operations is omitted here for the sake of brevity.

[0078] Those skilled in the art will readily understand that the illustration of FIG. 3 is simplified. In some examples, the (one or more) front dielectric layers 122-128 of each chip 102-108 are each a group of dielectric layers, or include a group of dielectric layers, such as 18 or more dielectric layers, for example, depending on the technology node of the chips 102-108. Further, the (one or more) front dielectric layers 122-128 can each have, or include, 18 metal layers (e.g., M0 layer to M17 layer) in some examples, although the number of metal layers can vary, such as depending on the technology node of the chip. In some examples where each chip has 18 metal layers in the (one or more) front dielectric layers, the metal lines 302x, 304x, 306x, 308x are in the M5 layer and the metal lines 302y, 304y, 306y, 308y are in the M7 layer. The various metal lines can be in different metal layers in other examples.

[0079] A broken via pillar can enable, within the same area of a chip (e.g., parallel to the front or back surface), for example, an input from a chip below to a chip and an output from that chip to a chip above, for example. For example, a broken via pillar can be used to receive an input signal and transmit an output signal. This can eliminate the use of two via pillars, each having a TSV, where one via pillar is for the input signal and another via pillar is for the output signal. Thus, some examples can implement a reduced area usage for Z - direction communication. The reduced area usage can also reduce bottlenecks for routing in the metal layers around the via pillars on the chip. Further, a broken via pillar can enable signal communication flexibility and can enable different chips in a chip stack to have the same IC and hardware, which can reduce the number of variants of chips to be designed and taped out. Still further, the controllability of the configurability of a broken via pillar in some examples can be simplified compared to, for example, a tri - state buffer solution.

[0080] Figure 4 is a flowchart of a method 400 for forming the multi - chip device of FIG. 1 according to some examples. The processing of the method 400 of FIG. 4 is generally described, and one of ordinary skill in the art will readily understand more specific processing that can be implemented. The more specific processing can follow any semiconductor processing for forming an IC on a substrate, which will be singulated into chips. For ease of explanation herein, the wafer on which one or more base chips 102 are formed is referred to as a base wafer, and the wafer on which one or more fabric chips 104, 106, 108 are formed is referred to as a fabric wafer. The wafers can be of any shape and / or size.

[0081] In block 402, front - side processing for the chips on each wafer is performed. For example, the front - side processing of each semiconductor substrate 112, 114, 116, 118 (e.g., wafers) can include forming devices (e.g., transistors 142, 144, 146, 148) in and / or on the front side of the semiconductor substrates 112, 114, 116, 118, and forming (one or more) front - side dielectric layers 122, 124, 126, 128 having metallization and front - side bond pads 152, 154, 156, 158 on the front side of the semiconductor substrates 112, 114, 116, 118. A plurality of base chips 102 can be formed on a base wafer. A plurality of fabric chips 104, 106, or 108 can be formed on a plurality of fabric wafers. The front - side processing can include forming, for example, a Z - interface selection circuit and broken via pillars on and / or in each semiconductor substrate and the (one or more) front - side dielectric layers.

[0082] In block 404, the base wafer is bonded to a first fabric wafer, such as a front - to - front bond shown in FIG. 1. As a result of the bonding, the front side of the base chip 102 is bonded to the front side of the fabric chip 104, as shown in FIG. 1. The bonding can be a hybrid bonding, such as bonding the front - side bond pad 152 on the base wafer to the front - side bond pad 154 on the first fabric wafer, and bonding the outer surface of the (one or more) front - side dielectric layers 122 on the base wafer to the outer surface of the (one or more) front - side dielectric layers 124 on the first fabric wafer.

[0083] In block 406, the semiconductor substrate of the first fabric wafer is thinned from the back surface of the first fabric wafer. As shown in FIG. 1, the semiconductor substrate 114 of the fabric chip 104 is thinned from the back surface. Thinning can be by chemical mechanical polishing (CMP) or other suitable processes. In block 408, backside processing for the fabric chips on the first fabric wafer is performed. As shown by FIG. 1, the backside processing can include forming backside TSVs 164 that pass through the semiconductor substrate 114 of the first fabric wafer and connecting to the metallization in the (one or more) front dielectric layers 124 on the first fabric wafer. The backside processing can further include forming (one or more) back dielectric layers 134 having metallization and back bond pads 174 on the back surface of the semiconductor substrate 114. The metallization in the (one or more) back dielectric layers 134 can be connected to the metallization in the (one or more) front dielectric layers 124 through the backside TSVs 164. Generally, the formation of the backside TSVs and the metallization in the (one or more) back dielectric layers can form broken via pillars of the Z interface on and / or in the respective semiconductor substrates and the (one or more) back dielectric layers.

[0084] In block 410, the first fabric wafer is bonded to a second fabric wafer, such as the back-to-front bonding shown in FIG. 1. As a result of the bonding, the back surface of the fabric chip 104 is bonded to the front surface of the fabric chip 106, as shown in FIG. 1. The bonding can be a hybrid bonding, such as bonding the back bond pads 174 on the first fabric wafer to the front bond pads 156 on the second fabric wafer and bonding the outer surface of the (one or more) back dielectric layers 134 on the first fabric wafer to the outer surface of the (one or more) front dielectric layers 126 on the second fabric wafer.

[0085] In block 412, as described with respect to block 406, the semiconductor substrate of the second fabric wafer is thinned from the back surface of the second fabric wafer. As shown in FIG. 1, the semiconductor substrate 116 of the fabric chip 106 is thinned from the back surface.

[0086] In block 414, as described with respect to block 408, backside processing for the fabric chips on the second fabric wafer is performed. As shown by FIG. 1, the backside processing can include forming backside TSVs 166 that pass through the semiconductor substrate 116 of the second fabric wafer and connecting to the metallization in the (one or more) front dielectric layers 126 on the second fabric wafer. The backside processing can further include forming (one or more) back dielectric layers 136 having metallization and back bond pads 176 on the back surface of the semiconductor substrate 116. The metallization in the (one or more) back dielectric layers 136 can be connected to the metallization in the (one or more) front dielectric layers 126 through the backside TSVs 166.

[0087] In block 416, the second fabric wafer is bonded to a third fabric wafer, such as the backside-to-frontside bonding shown in FIG. 1. As a result of the bonding, the back surface of the fabric chip 106 is bonded to the front surface of the fabric chip 108, as shown in FIG. 1. The bonding can be a hybrid bonding, such as bonding the back bond pads 176 on the second fabric wafer to the front bond pads 158 on the third fabric wafer and bonding the outer surface of the (one or more) back dielectric layers 136 on the second fabric wafer to the outer surface of the (one or more) front dielectric layers 128 on the third fabric wafer.

[0088] In block 418, as described with respect to block 406, the semiconductor substrate of the base wafer is thinned from the back surface of the base wafer. As shown in FIG. 1, the semiconductor substrate 112 of the base chip 102 is thinned from the back surface.

[0089] In block 420, as described with respect to block 408, backside processing for the base chips on the base wafer is performed. As shown by FIG. 1, the backside processing can include forming backside TSVs 162 that pass through the semiconductor substrate 112 of the base wafer and connecting to the metallization in the (one or more) front dielectric layers 122 on the base wafer. The backside processing can further include forming (one or more) back dielectric layers 132 having metallization and external connector backside pads 172 on the back surface of the semiconductor substrate 112. The metallization in the (one or more) back dielectric layers 132 can be connected to the metallization in the (one or more) front dielectric layers 122 through the backside TSVs 162. The backside processing for the base chips 102 can further include forming a passivation layer 180 and an external connector 182. In block 422, the bonded wafers are singulated (e.g., by sawing) to separate the formed individual multi-chip devices. Each of the multi-chip devices can be as shown in FIG. 1.

[0090] The various operations of the blocks of method 400 can be repeated and / or omitted to form various multi-chip devices. Method 400 is provided as an example of how some multi-chip devices can be formed. In other examples, some operations can be performed in parallel. For example, multiple different wafer stacks can be formed in parallel (e.g., by bonding and processing each wafer), and then the multiple different wafer stacks can then be bonded to each other and further processed to form a multi-chip device. One of ordinary skill in the art will readily understand how to form other multi-chip devices based on the above description of method 400.

[0091] FIG. 5 is a flowchart of a method 500 for operating a multi-chip device according to several examples. The multi-chip device can be, for example, such as those shown in FIGS. 1-3. Various operations of method 500 are described in the context of fabric chip 104 for purposes of explanation. One of ordinary skill in the art will readily understand that such operations can be similarly implemented or replicated on other chips such as fabric chip 106.

[0092] In block 502, a chip selection circuit is configured to selectively output and transmit received signals from a plurality of received signals. For example, the processing system 202 of base chip 102 can transmit configuration data to each of fabric chips 104-108 through passive connections of Z interfaces 232-238, and the selection circuits of Z interfaces 234-238 are configured, such as by writing configuration data to the configuration memory of the selection circuit. Any selection circuit of base chip 102 can be directly configured by processing system 202 without communicating corresponding configuration data through the Z interface. As further details of the example, the selection circuits 312, 314 of fabric chip 104 can be configured, such as by writing configuration data to the configuration memory. Selection circuit 312 can be configured to selectively output a signal received from metal line 302y or a signal received from PL IC 224. Selection circuit 314 can be configured to selectively output a signal received from metal line 304x or a signal received from PL IC 224.

[0093] In block 504, a first signal is received in a selection circuit from each continuous portion of the broken via pillar. The first signal can be received from a chip above or below in the chip stack. For example, the first signal can be received from the base chip 102 (e.g., the lower chip) at the front bond pad 154-1, transmitted through the second continuous portion 302-2 of the broken via pillar 302, and received in the selection circuit 312. Another first signal can be received from the fabric chip 104 (e.g., the upper chip) at the back bond pad 174-2, transmitted through the first continuous portion 304-1 of the broken via pillar 304, and received in the selection circuit 314.

[0094] In block 506, the first signal received in block 504 is further received in respective other circuits (e.g., PL IC). Continuing with the above example, the first signal can be received from the second continuous portion 302-2 of the broken via pillar 302 in the PL IC 224, and another first signal can be received from the first continuous portion 304-1 of the broken via pillar 304 in the PL IC 224.

[0095] In block 508, a second signal is received in a selection circuit from respective other circuits (e.g., PL IC). For example, the second signal can be received from the PL IC 224 in the selection circuit 312, and another second signal can be received from the PL IC 224 in the selection circuit 314. These second signals can be based on respective first signals (e.g., signals resulting from processing respective first signals), or can be independent of the respective first signals.

[0096] In block 510, a third signal is selectively output from each selection circuit and transmitted through the continuous portion of the broken via pillar. Which signal is selectively output from the selection circuit can be based on the configuration of the selection circuit provided in block 502. For example, selection circuit 312 can output a first signal or a second signal, which is further transmitted through the first continuous portion 302-1 of the broken via pillar 302 and output at the backside bond pad 174-1 to the fabric chip 106 (e.g., the upper chip). When the first signal is output from the selection circuit 312, the first signal can be passed through the broken via pillar 302 and the selection circuit 312 and through the fabric chip 104. In some cases, the broken via pillar 302 can serve as an input for the first signal and an output for a different second signal. Selection circuit 314 can output another first signal or a second signal, which is further transmitted through the second continuous portion 304-2 of the broken via pillar 304 and output at the front side bond pad 154-2 to the base chip 102 (e.g., the lower chip). When another first signal is output from the selection circuit 314, the another first signal can be passed through the broken via pillar 304 and the selection circuit 314 and through the fabric chip 104. In some cases, the broken via pillar 304 can serve as an input for the another first signal and an output for a different second signal.

[0097] The foregoing is directed to particular examples, but other and further examples may be devised without departing from its basic scope, which is determined by the following claims.

Claims

1. 1. A multi-chip device, comprising: A chip stack comprising a plurality of chips, wherein adjacent pairs of chips in the chip stack are attached to one another, one or more of the chips each comprising a first broken via pillar and a first selection circuit, the first broken via pillar comprising: a first continuous portion comprising a first through substrate via (TSV) and a first metal line, the first TSV passing through a semiconductor substrate of each chip and the first metal line being disposed within a group of dielectric layers disposed on a surface of the semiconductor substrate of each chip; a second continuous portion comprising a second metal line, the second metal line being disposed within the group of dielectric layers, the first continuous portion and the second continuous portion being aligned in a direction perpendicular to the surface of the semiconductor substrate, the first continuous portion being unconnected to the second continuous portion, a first input node of the first selection circuit being connected to one of the first metal line or the second metal line, and an output node of the first selection circuit being connected to the other of the first metal line or the second metal line; A chip stack comprising: Equipped with A multi-chip device, wherein each of the one or more of the chips further includes other circuitry, and a second input node of the first selection circuit is connected to an output node of the other circuitry.

2. 2. The multichip device of claim 1, wherein the first metal line or the second metal line connected to the first input node of the first selection circuit is also connected to an input node of the other circuit.

3. 2. The multichip device of claim 1 , wherein the first selection circuit is configured to selectively output at the output node of the first selection circuit a signal received from the first input node of the first selection circuit or the second input node of the first selection circuit.

4. The multi-chip device of claim 1 , wherein the other circuitry comprises a programmable logic circuit.

5. 2. The multichip device of claim 1, wherein the first input node of the first selection circuit is connected to the first metal line and the output node of the first selection circuit is connected to the second metal line.

6. 2. The multichip device of claim 1, wherein the first input node of the first selection circuit is connected to the second metal line and the output node of the first selection circuit is connected to the first metal line.

7. The one or more of the chips each further comprises a second broken via pillar and a second selection circuit, the second broken via pillar comprising: a third continuous portion comprising a second TSV and a third metal line, the second TSV passing through the semiconductor substrate of the respective chip and the third metal line disposed within the group of dielectric layers; a fourth continuous portion comprising a fourth metal line, the fourth metal line being disposed within the group of dielectric layers, the third continuous portion and the fourth continuous portion being aligned in a direction perpendicular to the surface of the semiconductor substrate, the third continuous portion being unconnected to the fourth continuous portion, an input node of the second selection circuit being connected to the third metal line, an output node of the second selection circuit being connected to the fourth metal line, the first input node of the first selection circuit being connected to the second metal line, and the output node of the first selection circuit being connected to the first metal line; The multi-chip device of claim 1 , comprising:

8. 2. The multichip device of claim 1 , wherein the first selection circuit includes a multiplexer, the first input node of the first selection circuit being a first input node of the multiplexer, and the output node of the first selection circuit being an output node of the multiplexer.

9. 1. A method of operating a multi-chip device, the method comprising: receiving a first signal at a first selection circuit from a first continuous portion of a first broken via pillar, the first broken via pillar being in a first chip of a plurality of chips in a chip stack, an adjacent pair of chips in the chip stack being attached to one another; transmitting a second signal from the first selection circuit through a second continuous portion of the first broken via pillar, where one of the first continuous portion and the second continuous portion includes a first through-substrate via (TSV) through a semiconductor substrate of the first chip, the first continuous portion and the second continuous portion are aligned in a direction perpendicular to a surface of the semiconductor substrate, and the first continuous portion is not connected to the second continuous portion; receiving a third signal in the first selection circuit from another circuit of the first chip; The method, wherein the first selection circuit selectively transmits either the first signal or the third signal as the second signal.

10. The method of claim 9 , wherein one of the first contiguous portion and the second contiguous portion includes the first TSV.

11. receiving a third signal at a second selection circuit from a third continuous portion of a second broken via pillar, the second broken via pillar being in the first chip, the third continuous portion including a second TSV through the semiconductor substrate, and the second continuous portion including the first TSV; transmitting a fourth signal from the second selection circuit through a fourth continuous portion of the second broken via pillar, the third continuous portion and the fourth continuous portion being aligned in a direction perpendicular to the surface of the semiconductor substrate, and the third continuous portion not being connected to the fourth continuous portion; The method of claim 9 further comprising:

12. the first signal is received from a second chip of the plurality of chips in the chip stack through the first contiguous portion; the second signal is transmitted through the second continuous portion to a third chip of the plurality of chips in the chip stack, the first chip being disposed between the second chip and the third chip in the chip stack; 10. The method of claim 9.

13. 1. A multi-chip device, comprising: A first chip, A first selection circuit; a first broken via pillar extending through a first semiconductor substrate of the first chip and through a first group of dielectric layers on a first surface of the first semiconductor substrate, the first broken via pillar comprising: a first continuous portion comprising a first through substrate via (TSV) through the first semiconductor substrate, an output node of the first selection circuit being connected to the first continuous portion; a second continuous portion aligned with the first continuous portion in a direction perpendicular to the first surface of the first semiconductor substrate, the second continuous portion being connected to a first input node of the first selection circuit; an integrated circuit, wherein a second input node of the first selection circuit is connected to an output node of the integrated circuit; A first broken beer pillar comprising: A second selection circuit; a second broken via pillar extending through the first semiconductor substrate and the first group of dielectric layers, the second broken via pillar comprising: a third continuous portion comprising a second TSV through the first semiconductor substrate, the third continuous portion being coupled to a first input node of the second selection circuit; and a fourth continuous portion aligned with the third continuous portion in a direction perpendicular to the first surface of the first semiconductor substrate, the fourth continuous portion being connected to an output node of the second selection circuit; and A second broken beer pillar comprising: A first chip comprising: a second chip attached to the first chip; A multi-chip device comprising:

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