NOR type flash memory and its operating method

Abstract

A NOR type flash memory suitable for protecting data that requires high reliability and an operating method thereof are provided. [Solution] A NOR type flash memory 100 of the present invention includes a memory cell array 110 including a plurality of memory cells, an ECC circuit 130 that performs error detection and correction of data read from a boot storage area 112 of the memory cell array 110, a means for storing in a boot management area 210 identification information that identifies the error mode of a fail cell whose error has been detected and corrected by the ECC circuit 130, and a recovery means for recovering the fail cell so that the error in the fail cell is eliminated based on the identified error mode.

Description

Technical Field

[0001] The present invention relates to a NOR-type flash memory and an operation method thereof, and particularly to a NOR-type flash memory equipped with an ECC function.

Background Art

[0002] In a NAND-type flash memory, repeated read / program / erase operations may cause threshold voltage variations due to deterioration of the tunnel insulating film or deterioration of Gm (transconductance), etc., which may lead to bit errors. As a countermeasure against such bit errors, an error detection and correction function (hereinafter referred to as an ECC function) is used (for example, Patent Document 1).

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In a NOR-type flash memory, since memory cells are connected in parallel and access to the memory cells is possible in bit units, the influence of disturbance, etc. is small, and the probability of bit errors occurring is also small compared to a NAND-type flash memory. Therefore, it is suitable for storing data that requires high reliability, such as boot data for operating a system or program codes.

[0005] In recent years, the data capacity of boot data and program codes has increased. On the other hand, even in NOR-type flash memories, the increase in memory capacity has been promoted by miniaturization of the memory size. Due to the miniaturization of memory cells, bit errors cannot be ignored even in NOR-type flash memories, and the combined use of an ECC function is being considered.

[0006] However, simply correcting errors by the ECC function is not sufficient to protect data that requires high reliability. For example, boot data is read from the NOR type flash memory when the system or software is started up. However, the read frequency of the boot data is higher than that of other data. Therefore, the probability of an error occurring in the boot data is higher than that of other data. If an error exceeding the number of bits that can be corrected by the ECC function occurs, the error in the boot data cannot be corrected, which is fatal to the system started by the boot data.

[0007] An object of the present invention is to solve such a conventional problem and provide a NOR type flash memory suitable for protecting data that requires high reliability and an operation method thereof.

Means for Solving the Problem

[0008] The NOR type flash memory according to the present invention includes a memory cell array including a plurality of memory cells, an ECC means for detecting and correcting an error in data read from the memory cell array, an error identification means for identifying an error mode of a fail cell error-detected and corrected by the ECC means, and a recovery means for recovering the fail cell so that the error of the fail cell is eliminated based on the identified error mode.

[0009] In one aspect, when the error mode represents a decrease in the threshold value of the memory cell, the recovery means programs the fail cell so that the threshold value increases. In one aspect, the error identification means holds the address of the fail cell, and the recovery means programs the fail cell based on the address. In one aspect, when the error mode represents an increase in the threshold value of the memory cell, the recovery means increases the read verification voltage of the fail cell. In one aspect, the error identification means holds the address of the fail cell, and the recovery means increases the read verification voltage when reading the fail cell based on the address. In one aspect, the NOR type flash memory further includes management means for managing the occurrence of fail cells in a sector of the memory cell array, and transfer means for transferring data of the sector including the fail cell to a redundant area of the memory cell array based on the management result of the management means. In one aspect, the memory cell array includes a boot data storage area for storing boot data, and the recovery means performs recovery of a fail cell storing boot data.

[0010] The operation method executed by the NOR type flash memory according to the present invention includes steps of performing error correction of data read from a memory cell array by ECC means, identifying an error mode of a fail cell error-detected and corrected by the ECC means, and recovering the fail cell so that the error of the fail cell is eliminated based on the identified error mode.

[0011] In one aspect, when the error mode represents a decrease in the threshold value of the memory cell, the step of recovering programs the fail cell so that the threshold value increases. In one aspect, when the error mode represents an increase in the threshold value of the memory cell, the step of recovering increases the read verification voltage of the fail cell.

Advantages of the Invention

[0012] According to the present invention, since the failed cells are recovered so that the errors of the error-detected and corrected failed cells are eliminated, the error detection and correction function of the ECC means can be provided with a margin, and as a result, high reliability of data can be maintained.

Brief Description of the Drawings

[0013]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Mode for Carrying Out the Invention

[0014] The NOR type flash memory according to the present invention has a memory management scheme suitable for protecting data that requires high reliability, such as boot data and program codes read at the time of system startup or software startup, and minimizes the occurrence of errors in the stored data to provide highly reliable data.

Example

[0015] Next, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram showing the configuration of a NOR-type flash memory according to an embodiment of the present invention. As shown in the figure, the NOR-type flash memory 100 of this embodiment includes a memory cell array 110 in which a plurality of memory cells are formed, an input / output circuit 120 that outputs read data to the outside in synchronization with a clock signal ExCLK or takes in data input from the outside, an ECC circuit 130 that generates codes for data to be programmed and performs error detection / correction on the read data, an address register 140 that receives address data via the input / output circuit 120, a controller 150 that controls operations based on command data received via the input / output circuit 120 and control signals applied to external terminals, a row selection circuit 160 that receives row address information Ax from the address register 140, decodes the row address information Ax, and performs selection of word lines, selection of sectors, etc. based on the decoding result, a sense / write circuit 170 that senses data read from the memory cells selected by the row selection circuit 160 or writes data to be programmed to the selected memory cells, a column selection circuit 180 that receives column address information Ay from the address register 140, decodes the column address information Ay, and performs selection of bit lines / source lines, etc. based on the decoding result, and an internal voltage generation circuit 190 that generates various voltages (program voltage Vpgm, read voltage Vread, erase voltage Vers, etc.) necessary for data reading, programming, erasing, etc.

[0016] The memory cell array 110 includes a plurality of memory cells arranged in a matrix, and each of the plurality of memory cells is connected in parallel between a bit line and a source line. That is, it has a NOR structure. The memory cell may be a two-dimensional structure formed on the surface of a substrate such as silicon, or a three-dimensional structure formed in a direction perpendicular to the substrate surface. Further, the memory cell may be a single-level cell (SLC) that stores binary data, or a multi-level cell (MLC) that stores multi-valued data.

[0017] The input / output circuit 120 receives commands, addresses, data, etc. from the host system in synchronization with the clock signal ExCLK, and provides the received commands, addresses, and data to the controller 150, the address register 140, the column selection circuit 180, and the sense / write circuit 170. Also, the input / output circuit 120 receives the data read from the memory cell array 110 from the sense / write circuit 170 and provides this to the host system.

[0018] The ECC circuit 130 includes an encoder that encodes data to generate an ECC code, and a decoder that decodes data based on the ECC code. During the program operation, the ECC circuit 130 calculates the bit string of the data input via the input / output circuit 120 to generate an ECC code necessary for error detection and correction of the input data, and during the read operation, performs error detection and correction of the data read from the memory cell array 110 based on the ECC code.

[0019] The number of bits that can be error-detected and corrected by the ECC circuit 130 is not particularly limited. The ECC circuit 130 performs error detection and correction, for example, using a Hamming code, Reed-Solomon, or BCH code. In the case of the BCH code, it is possible to detect and correct errors in multiple bits (e.g., 2 bits, 4 bits, 8 bits, etc.). Also, the ECC circuit 130 may correct (bit inversion) the error bits of the read data held in the sense / write circuit 170, or alternatively, the ECC circuit 130 may receive the read data, perform error correction there, and output the error-corrected data to the sense / write circuit 170.

[0020] The controller 150 is composed of hardware and / or software resources, and is, for example, composed of a microcontroller or a state machine including ROM / RAM. The controller 150 receives a command from the host system and controls the overall operations such as read, program, and erase based on the command.

[0021] When a memory cell is read, a positive voltage is applied to the selected word line by the row selection circuit 160, and the current or voltage flowing between the selected bit line and the selected source line is sensed by the sense / write circuit 170. When programming (writing) to the memory cell, a program voltage is applied to the selected word line by the row selection circuit 160, and a voltage corresponding to the data to be programmed is applied to the selected bit line by the sense / write circuit 170, and hot electrons flowing from the selected bit line to the selected source line are accumulated in the charge storage layer. However, the writing method may be other than this, and charges may be trapped in the charge storage layer by FN tunneling. To erase the memory cell, a certain voltage is applied to the selected word line. For example, hot holes are injected into the charge storage layer, or an erase voltage is applied to the substrate to discharge the charges accumulated in the charge storage layer by FN tunneling. The erasure of the memory cell is performed in units of sectors including a plurality of memory cells, but it is also possible to perform it in units of memory cells.

[0022] In the memory management scheme of this embodiment, when a fail cell (error bit) is detected by the ECC circuit 130, the error mode is identified, and the recovery of the fail cell is performed so that the error of the fail cell is eliminated according to the identified error mode. By recovering the fail cell, it is guaranteed that error correction can be performed within the range where error detection and correction by the ECC circuit 130 are possible, and the reliability of the data can be improved.

[0023] In another aspect, the recovery of the fail cell is performed during the replacement period of the data of the fail cell. That is, in parallel with the recovery of the fail cell, the data stored in the fail cell or the sector including the fail cell is transferred to a fresh redundant area, and the recovery of the fail cell is completed. The occurrence of a fail cell is a precursor to a failure, and by avoiding the memory area where the fail cell has occurred, the occurrence of further fail cells can be suppressed.

[0024] The memory management scheme of this embodiment is implemented for data that requires high reliability. Here, boot data is used as an example of such data. Boot data (boot code) is data necessary for system operation and is data that is protected separately from the normal data used by the user. Boot data is read from the memory cell array during system operation or when the flash memory is powered off and provided to an external host system. If part of the boot data is lost or part of it is rewritten, it will cause an obstacle to system operation. Therefore, high reliability is required for boot data.

[0025] Figure 2 shows a schematic example of the data stored in the memory cell array and the RAM. The memory cell array 110 includes a boot storage area 112 and a redundant area 114 for storing boot data in addition to the area used by the user to store normal data. On the other hand, the RAM 200 is a volatile memory such as SRAM and is provided, for example, in the controller 150. The RAM 200 includes a boot management area 210 for storing management information of the boot data. The boot storage area 112 and the redundant area 114 can be set in any address space of the memory cell array 110, and information regarding the set address space is stored, for example, in the fuse ROM of the memory cell array 110. Various information regarding the operation of the NOR type flash memory 100 is stored in the fuse ROM, and when the NOR type flash memory 100 is activated, the data stored in the fuse ROM is loaded into a configuration register or the like and referred to by the controller 150.

[0026] The boot data is input via the input / output circuit 120, and the controller 150 writes the input boot data to the main area of the boot storage area 112. Also, the ECC circuit 130 performs arithmetic processing on the input boot data, generates an ECC code necessary for error detection and correction, and the generated ECC code is written to the spare area of the boot storage area 112.

[0027] The boot storage area 112 has a plurality of sectors #1 to #n (or a plurality of blocks) as shown in FIG. 2. A memory cell connected to one word line can be called one page, and one sector is configured to include a plurality of pages. A sector includes a main area that can be accessed by a user and a spare area that cannot be accessed by the user. Boot data is stored in the main area, and in the spare area, as attribute information of the data written in the main area, for example, an ECC code of the boot data generated by the ECC circuit 130 is stored. Note that the ECC code of the boot data may be managed in units of sectors or in units of pages.

[0028] On the other hand, the boot management area 210 of the RAM 200 stores an ECC flag indicating that a fail cell (error bit) has been detected by the ECC circuit 130 or that a fail cell has been corrected during the read operation of the boot data, the address of the fail cell, identification information for identifying the error mode of the fail cell, and information regarding the recovery of the fail cell according to the error mode. Further, although not shown here, the boot management area 210 can include a look-up table LUT that defines the correspondence relationship of addresses between the boot storage area 112 and the redundant area 114.

[0029] The boot management area 210 is not particularly limited, but for example, manages the boot data of the boot storage area 112 in units of sectors. FIG. 2 exemplifies a management area_sector #1 for storing management information of sector #1 of the boot storage area 112. The management area_sector #1 includes a fail cell, an ECC flag, the address of the fail cell, identification of the error mode of the fail cell, and recovery information according to the error mode.

[0030] For example, when a fail cell FC1 is detected during the reading of the boot data of sector #1, the fail cell FC1 is registered in the management area_sector #1, an ECC flag indicating that the fail cell FC1 has an error bit or has been error-corrected is set, and the address of the fail cell FC1 is stored. Further, the identification of the error mode of the fail cell FC1 is stored. In this example, data "0", which represents that the fail cell FC1 has transitioned from data "1" to data "0", is exemplified as the identification information. In other words, the fail cell FC1 means that it has been corrected from data "0" to data "1" by the ECC circuit 130.

[0031] Also, when another fail cell FC2 is detected during the reading of sector #1, the fail cell FC2 is registered, the ECC flag of the fail cell FC2 is set, and the address of the fail cell FC2 is stored. As the identification of the error mode of the fail cell FC2, here, data "1", which represents that the fail cell FC2 has transitioned from data "0" to "1", is exemplified as the identification information. In other words, the fail cell FC2 means that it has been corrected from data "1" to data "0" by the ECC circuit 130.

[0032] Next, the relationship between the error mode and recovery will be described. FIG. 3(A) shows an error when the data of the memory cell transitions from "0" to "1" (that is, the threshold value of the fail cell decreases from □ to ■). The threshold value of the memory cell programmed with data "0" must be greater than the read verification voltage V WL However, in a fail cell whose threshold value has transitioned in a direction smaller than the read verification voltage V WL even though data "0" has been programmed, data "1" will be read out. This is an error caused by the loss of the charge accumulated in the memory cell and the deterioration of the retention characteristics, where the threshold value gradually decreases.

[0033] In this embodiment, as recovery from an error due to such retention characteristics, the address of the fail cell is stored in the memory management area 210, and then, at any timing, the threshold value of the fail cell is made to exceed the read verification voltage V WL by over-programming the fail cell, and the fail cell is refreshed. This is shown in FIG. 3(B) (the threshold value of the fail cell increases from □ to ■). For example, when the program voltage at the previous programming is known, a program larger than the previous program voltage may be applied to the fail cell to increase the threshold value of the memory cell in the positive direction, or if it is not known, the ISPP (Incremental Step Pulse Program) method may be used as in the case of a normal memory cell to perform over-programming. Finally, the over-programming ends when the program verification is successful. For the recovery regarding the fail cell FC1 in the boot management area, a flag indicating whether the over-programming has ended is set.

[0034] Different from the NAND type flash memory, in the NOR type flash memory, since the memory cells are connected in parallel, it is easy to program only the fail cell, and it is possible to suppress the program disturbance to the non-selected memory cells as in the case of the NAND type memory cell. By recovering the fail cell by over-programming the fail cell, at the time of reading the next boot data, the bit error of the recovered fail cell is not detected. As a result, a margin can be provided for the number of bits that can be error-detected and corrected by the ECC circuit 130 so that the number of error bits in the boot data does not exceed the number of bits that can be error-detected and corrected by the ECC circuit 130, and the reliability of the boot data can be improved.

[0035] FIG. 4(A) shows an error when the data of the memory cell transitions from "1" to "0" (the threshold value of the fail cell increases from □ to ■). The data "1", that is, the threshold value of the erased memory cell, is the read verification voltage V WLmust be smaller than, but the threshold voltage transitions in the direction of becoming larger than the read verification voltage V WL In a fail cell that has transitioned in the direction of becoming larger than WL , although the data has been erased to "1", the data "0" is read out. This is an error caused by the fact that the read frequency of the boot data is higher than that of other data, and when the memory cell of the data "1" is read out many times, the Gm (transconductance) deteriorates compared to the current flowing through the memory cell, and the threshold voltage gradually increases.

[0036] As a recovery for the error in which the threshold voltage increases, when reading the fail cell, the read verification voltage V WL is increased by ΔV to a new read verification voltage V WL _R is set. ΔV can be a predetermined value (for example, 0.2V), and this value is determined, for example, by an empirical rule. FIG. 4(B) shows the state of the recovery. The threshold voltage of the recovered fail cell becomes smaller than the new read verification voltage V WL _R, and during the read operation, the read data of the recovered fail cell becomes "1". For the recovery of the fail cell FC2 in the boot management area 210, the newly set read verification voltage V WL _R is stored. In this way, at the next read, the recovered fail cell is not detected as an error bit, the number of correctable bits by the ECC circuit 130 is given a margin, and the reliability of the boot data can be improved.

[0037] In addition, when the recovered fail cell is detected again as an error bit by the ECC circuit 130, it is also possible to further increase the read verification voltage V WL _R in the boot management area 210 by ΔV.

[0038] Next, the operation of the NOR type flash memory of this embodiment will be described. FIG. 5 is an operation flow when programming boot data into the boot storage area. In the NOR type flash memory 100, when a command, address, and boot data for programming the boot data are received from the host system via the input / output circuit 120 (S100), the ECC circuit 130 performs arithmetic processing on the received boot data and generates an ECC code (S110).

[0039] The controller 150 controls the programming of the boot data based on the received command, and programs the boot data and the ECC code into the selected sector in the boot storage area 112 by the row selection circuit 160 and the column selection circuit 180 based on the address held in the address register 140 (S120). The boot data is written into the main area, and the ECC code is written into the spare area. When the position for storing the boot data is predetermined, it is not always necessary to receive an address from the host system. For example, the address for storing the boot data may be stored in the fuse ROM, and the controller 150 may refer to the address stored in the fuse ROM and program the boot data into the boot storage area 112.

[0040] Next, the boot data read operation will be described. When reading the boot data, the controller 150 refers to the information stored in the boot management area 210, controls the reading of the boot data, and updates the management information of the boot data.

[0041] FIG. 6 is a flow showing the boot data read operation. When receiving a command or the like for reading the boot data from the host system (S200), the controller 150 reads the management information corresponding to the selected sector of the boot storage area 112 from the boot management area 210, and detects the failed cells in which the ECC flag is set in the sector (S210). For example, when the boot data of sector #1 shown in FIG. 2 is read, the controller 150 detects the failed cells FC1 and FC2 in which the ECC flag is set.

[0042] When the controller 150 detects a fail cell with the ECC flag set, it performs read control according to the error mode (S220). Specifically, for a fail cell corresponding to the identification of "1" in the error mode, based on the address of the fail cell stored in the boot management area 210, the read verification voltage when reading the fail cell is set to the verification read V WL _R for read control to change. On the other hand, for a fail cell corresponding to the identification of "0" in the error mode, at an appropriate timing after error detection, the over-programming of the fail cell has already been completed and the recovery flag is set.

[0043] Next, when the controller 150 reads the selected memory cell, it applies the verification read V WL to the word line, and when reading the fail cell, it applies the verification read V WL _R to the word line and reads the boot data from the boot storage area (S230). In this reading of the boot data, the ECC circuit 130 detects whether a fail cell (error bit) has occurred in the boot data based on the ECC code (S240). As described above, the recovered fail cell is not detected as an error bit, but if a new error has occurred in a memory cell other than the recovered fail cell, that fail cell is detected.

[0044] When an error is detected, the ECC circuit 130 corrects the error of the new fail cell (S250), and the controller 150 updates the data regarding the newly detected fail cell in the boot management area (S260). For example, when a new fail cell FC3 is detected during the reading of sector #1, as shown in FIG. 7, the fail cell FC3 is registered in the management area_sector #1, its ECC flag is set, the address is stored, and the identification of the error mode is stored. Also, the ECC flags of the fail cells FC1 and FC2 are rewritten to reset. Then, the read boot data is output to the host system via the input / output circuit 120 (S270).

[0045] As described above, according to this embodiment, the error mode of the fail cell detected and corrected by the ECC circuit 130 is identified, and the fail cell is recovered based on the error mode. Therefore, the error detection and correction function of the ECC circuit 130 is guaranteed, and thereby the reliability of the boot data can be maintained.

[0046] In the above embodiment, the boot management area 210 is set in the RAM 200 of the controller 150. However, when the NOR flash memory 100 is powered down, the data held in the RAM 200 is volatile. For this reason, during the power-down sequence of the NOR flash memory 100, it is desirable to back up the data in the boot management area 210 to a non-volatile memory, for example, the memory cell array 110, and when the NOR flash memory 100 is restarted, load the backed-up data into the boot management area 210 to prevent the loss of the data in the boot management area.

[0047] Next, another embodiment of this embodiment will be described. In the above embodiment, an example was shown in which the error correction function of the ECC circuit 130 was maximized by recovering the fail cell to maintain the reliability of the boot data. However, in this embodiment, the recovery period is restricted to further improve the reliability of the boot data.

[0048] The occurrence of a fail cell means a precursor of a sector failure due to repeated readings, and performing recovery (increasing the read verify voltage) as shown in Fig. 4(B) makes it easier to cause an error (the memory threshold value transitions in a direction smaller than the read verify voltage) as shown in Fig. 3(A). Therefore, continuously performing recovery of a fail cell may, as a result, increase the occurrence probability of a fail cell and reduce the reliability of boot data.

[0049] Therefore, in this embodiment, a sector in which a certain number of fail cells have occurred (for convenience, referred to as a fail sector) is determined to be inappropriate for protecting highly reliable data, and the data stored in the fail sector is replaced with a fresh sector in the redundant area 114. After replacement, the data in the fail sector is erased, and the fail sector is reused as an area for storing normal data. Such replacement of a fail sector also leads to wear leveling that equalizes the usage frequency of the memory cell array.

[0050] Fig. 8 shows the operation flow when replacing boot data. The controller 150 refers to the boot management area 210 and determines whether a certain number of fail cells have occurred in the sector (S300). The boot management area 210 manages fail cells in units of sectors, and the history of fail cells that have occurred in the sector is stored therein. The certain number can be arbitrarily determined. For example, it may be one fail cell or a plurality of fail cells.

[0051] When the controller 150 determines that a certain number of fail cells have occurred in the sector, it transfers the data of the sector to a fresh sector in the redundant area 114 (S310). When replacing data between sectors, the controller 150 registers the relationship between the address of the source sector and the address of the destination sector in the boot management area 210 in a lookup table or the like to associate the two (S320). After the transfer is completed, the controller 150 erases the data in the source fail sector (S330).

[0052] In this way, when a certain number of fail cells occur within a sector, by replacing the boot data with a fresh sector, the boot data can be protected so that errors in the boot data are minimized, and its reliability can be improved. Also, by replacing the boot data, the usage frequency of sectors within the memory cell array can be equalized.

[0053] Next, a modified example will be described. In the above embodiment, the boot data is replaced when a certain number of fail cells occur within a sector. However, in this modified example, the controller 150 may refer to the ECC flag in the boot management area and transfer the boot data of the sector to a sector in the redundant area when at least one set of ECC flags is detected within the sector. After the transfer of the data is completed, the controller 150 erases the data of the source sector.

[0054] In the description of the above embodiment, the boot data (boot code) is shown as data that requires high reliability. However, such data is not limited to the boot data, and may be other specific data to be protected equivalent to the boot data, which can be arbitrarily defined by the user. Also, in the above embodiment, an example of storing the ECC flag in the boot management area is shown, but this is just an example, and the ECC flag may be stored in the spare area within the sector.

[0055] Although the preferred embodiments of the present invention have been described in detail, the present invention is not limited to specific embodiments, and various modifications and changes are possible within the scope of the gist of the invention described in the claims.

Explanation of Reference Numerals

[0056] 100: NOR type flash memory 110: Memory cell array 120: Input / output circuit 130: ECC circuit 140: Address register 150: Controller 160: Row selection circuit 170: Sense / write circuit 180: Column selection circuit 190: Internal voltage generation circuit

Claims

1. a memory cell array including a plurality of memory cells; an ECC means for detecting and correcting errors in data read from the memory cell array; an error identification means for identifying an error type of a fail cell which has been detected and corrected by the ECC means; recovery means for recovering the fail cell so that the error of the fail cell is eliminated based on the identified error mode; A NOR type flash memory comprising:

2. 2. The NOR type flash memory according to claim 1, wherein when the error mode indicates a decrease in a threshold value of a memory cell, the recovery means programs the fail cell so that the threshold value increases.

3. The error identifying means holds an address of the fail cell, 3. The NOR type flash memory according to claim 2, wherein said recovery means programs said fail cell based on said address.

4. 2. The NOR type flash memory according to claim 1, wherein said recovery means increases a read verify voltage of said fail cell when said error mode indicates an increase in a threshold voltage of said memory cell.

5. The error identifying means holds an address of the fail cell, 5. The NOR type flash memory according to claim 4, wherein said recovery means increases a read verify voltage when reading said fail cell based on said address.

6. The NOR type flash memory further includes: a management means for managing occurrence of fail cells in a sector of the memory cell array; 2. The NOR type flash memory according to claim 1, further comprising transfer means for transferring data of the sector including said fail cell to a redundant area of ​​said memory cell array based on a management result of said management means.

7. the memory cell array includes a boot data storage area for storing boot data; 2. The NOR type flash memory according to claim 1, wherein said recovery means recovers a fail cell storing boot data.

8. An operating method performed by a NOR type flash memory, comprising: correcting errors in data read from the memory cell array by an ECC means; a step of identifying an error type of a fail cell whose error has been detected and corrected by the ECC means; recovering the failed cell so that the error of the failed cell is eliminated based on the identified error mode; The method of operation includes:

9. 9. The method of claim 8, wherein when the error mode represents a decrease in a threshold of a memory cell, the recovering step includes programming the failing cell to increase its threshold.

10. 9. The method of claim 8, wherein when the error mode represents an increase in a threshold voltage of a memory cell, the recovering step increases a read verify voltage of the failing cell.

Images