Multilayer wiring board, composite wiring board, packaged device, and method for manufacturing multilayer wiring board

Abstract

To provide a multilayer wiring board having high insulation reliability, a composite wiring board, a packaged device, and a method for manufacturing a multilayer wiring board.SOLUTION: Laminated layers 70 and 80 of a multilayer wiring board 12 include: insulating resin layers 71 and 81 which are provided with recesses 75 and 85 for lands opened in first surfaces 71a and 81a, groove parts 74 and 84 opened in the first surfaces, and recesses 76 and 86 for vias that are opened in second surfaces 71b and 81b, in which the one or more recesses communicate with the recesses 75 and 85 for the lands; inorganic insulating layers 160 and 170 including parts covering bottom surfaces 74b and 84b of the groove parts 74 and 84, and parts covering bottom surfaces 75b and 85b of the recesses 75 and 85 for the lands; and a conductor layer 77 in which the recesses 75 and 85 for the lands and the groove parts 74 and 84, and the recesses 63 and 76 included in the adjacent insulating resin layers 61 and 71 are embedded, and that constitutes land parts 72a and 82a, via parts 62 and 73, and wiring parts 72b and 82b.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present invention relates to a multilayer wiring board, a composite wiring board, a packaged device, and a method for manufacturing a multilayer wiring board. [Background technology]

[0002] In recent years, as semiconductor devices become faster and more highly integrated, there is a demand for narrower pitches of bonding terminals used for bonding to semiconductor chips and finer wiring within the substrate for wiring substrates for flip chip ball grid arrays (FC-BGA substrates) on which semiconductor chips are mounted. On the other hand, bonding between FC-BGA substrates and motherboards is required to be performed using bonding terminals arranged at almost the same pitch as before. In response to these demands, a technology has been adopted in which a multilayer wiring substrate including fine wiring, also called an interposer, is provided between the FC-BGA substrate and the semiconductor chip.

[0003] One of these is silicon interposer technology, which manufactures interposers by forming a multilayer wiring structure, each layer of which contains fine wiring, on a silicon wafer using semiconductor circuit manufacturing technology.

[0004] Also, a method has been developed in which the above multi-layer wiring structure is directly fabricated on an FC-BGA substrate, rather than being formed on a silicon wafer. This method involves forming the above multi-layer wiring structure by using chemical mechanical polishing (CMP) or the like in the manufacture of an FC-BGA substrate, the core layer of which is made of, for example, a glass epoxy substrate. This method is disclosed in Patent Document 1.

[0005] Furthermore, there is also a method in which an interposer is formed on a support such as a glass substrate, the interposer is bonded to an FC-BGA substrate, and then the support is peeled off from the interposer, thereby providing the above-mentioned multilayer wiring structure on the FC-BGA substrate. This method is disclosed in Patent Document 2. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] JP 2014-225671 A [Patent Document 2] International Publication No. 2018 / 047861 Summary of the Invention [Problem to be solved by the invention]

[0007] An object of the present invention is to provide a multilayer wiring board, a composite wiring board, a packaged device, and a method for manufacturing the multilayer wiring board, which have high insulation reliability. [Means for solving the problem]

[0008] According to one aspect of the present invention, there is provided a multilayer wiring board comprising: an insulating resin layer having two or more stacked layers, each of the two or more layers having a first surface and a second surface which is the back surface of the first surface, the insulating resin layer being provided with a first recess opening on the first surface, a groove opening on the first surface, and a second recess opening on the second surface and communicating with one or more of the first recesses, the insulating resin layer being integrally formed in the thickness direction; an inorganic insulating layer including a portion covering a bottom surface of the groove portion and a portion covering a bottom surface of the first recess; a land portion and a wiring portion respectively filling the first recess and the groove portion of the insulating resin layer; and a via portion protruding from the first surface at the position of the land portion, the via portion including a conductor layer filling a recess of another insulating resin layer adjacent on the first surface side.

[0009] Here, the insulating resin layer being "integrally formed in the thickness direction" means that there is no interface intersecting the thickness direction inside the insulating resin layer, that is, the insulating resin layer has a single-layer structure. Even if multiple insulating layers stacked on top of each other are made of the same material, their interfaces can be confirmed by observing the cross section with an electron microscope such as a scanning electron microscope.

[0010] According to another aspect of the present invention, there is provided a multilayer wiring board according to the above aspect, wherein the inorganic insulating layer further includes a portion covering a side wall of the first recess and a portion covering a side wall of the groove portion.

[0011] According to yet another aspect of the present invention, there is provided the multilayer wiring board according to the above aspect, wherein the inorganic insulating layer further includes a portion covering the first surface.

[0012] According to yet another aspect of the present invention, there is provided a multilayer wiring board according to the above aspect, wherein the material of the inorganic insulating layer includes one or more insulators selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride, silicon oxide doped with fluorine, and silicon oxide doped with carbon.

[0013] According to yet another aspect of the present invention, there is provided a multilayer wiring board according to the above aspect, wherein each of the two or more layers further includes a first metal-containing layer covering the peripheral edges of the land portion, the side surfaces of the via portion and the wiring portion, the surface of the wiring portion facing the opening of the groove portion, and the surface of the land portion facing the first surface.

[0014] According to yet another aspect of the present invention, there is provided a multilayer wiring board according to the above aspect, wherein each of the two or more layers further includes a second metal-containing layer interposed between the first metal-containing layer and the conductor layer and made of the same material as the conductor layer or made of a metal material having a smaller ionization tendency than the material of the conductor layer.

[0015] According to yet another aspect of the present invention, there is provided a multilayer wiring board according to any one of the above aspects, wherein the first metal-containing layer contains titanium.

[0016] According to yet another aspect of the present invention, there is provided a composite wiring board comprising a first wiring board and a second wiring board joined to the first wiring board, the first and second wiring boards being electrically connected to each other via a joining electrode interposed therebetween, and the second wiring board being a multilayer wiring board according to any of the aspects described above.

[0017] According to yet another aspect of the present invention, there is provided a composite wiring board according to the above aspect, wherein the first wiring board is a wiring board for a flip chip ball grid array, and the second wiring board is an interposer.

[0018] According to yet another aspect of the present invention, there is provided a packaged device comprising a composite wiring board according to any of the above aspects and a functional device mounted on a surface of the second wiring board opposite the first wiring board.

[0019] Here, the term "functional device" refers to a device that operates when at least one of power and an electric signal is supplied, a device that outputs at least one of power and an electric signal when stimulated from the outside, or a device that operates when at least one of power and an electric signal is supplied and outputs at least one of power and an electric signal when stimulated from the outside. The functional device is in the form of a chip, such as a semiconductor chip or a chip in which circuits and elements are formed on a substrate made of a material other than a semiconductor, such as a glass substrate. The functional device may include, for example, one or more of a large scale integrated circuit (LSI), a memory, an imaging element, a light-emitting element, and a MEMS (Micro Electro Mechanical Systems). The MEMS may be, for example, one or more of a pressure sensor, an acceleration sensor, a gyro sensor, a tilt sensor, a microphone, and an acoustic sensor. According to one example, the functional device is a semiconductor chip including an LSI.

[0020] According to yet another aspect of the present invention, a method includes forming two or more stacked layers, and forming each of the two or more layers includes forming a dummy layer having a groove and at least one through hole communicating with the recess on a base layer having a recess; forming a conductor layer on the dummy layer so as to fill the recess, the groove, and the through hole; polishing the conductor layer so as to remove a portion of the conductor layer outside the recess, the groove, or the through hole, thereby forming a portion of the conductor layer that fills the recess, the portion that fills the through hole, and the groove. as a via portion, a land portion and a wiring portion, respectively; thereafter, removing the dummy layer; forming an inorganic insulating layer so as to cover at least an upper surface of the land portion and an upper surface of the wiring portion; forming an insulating resin layer that covers the inorganic insulating layer, fills the gap between the land portion and the wiring portion, and has a recess provided at one or more positions of the land portion; and removing a portion of the inorganic insulating layer that is exposed at the position of the recess provided in the insulating resin layer.

[0021] According to yet another aspect of the present invention, there is provided the method for manufacturing a multilayer wiring board according to the above aspect, wherein the inorganic insulating layer is formed so as to further cover a side surface of the land portion and a side surface of the wiring portion.

[0022] According to yet another aspect of the present invention, there is provided a method for manufacturing a multilayer wiring board according to the above aspect, wherein the inorganic insulating layer is formed so as to further cover the base layer.

[0023] According to yet another aspect of the present invention, there is provided a method for manufacturing a multilayer wiring board according to the above aspect, wherein a material of the inorganic insulating layer includes one or more insulators selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride, silicon oxide doped with fluorine, and silicon oxide doped with carbon.

[0024] According to yet another aspect of the present invention, there is provided a method for manufacturing a multilayer wiring board according to the above aspect, wherein forming each of the two or more layers further includes forming a first metal-containing layer covering an upper surface of the dummy layer, an inner surface of the recess of the base layer, and an inner surface of the groove and the through hole of the dummy layer before forming the conductor layer.

[0025] According to yet another aspect of the present invention, there is provided a method for manufacturing a multilayer wiring board of the above aspect, wherein forming each of the two or more layers further includes forming a second metal-containing layer on the first metal-containing layer before forming the conductor layer, the second metal-containing layer being made of the same material as the conductor layer or made of a metal material having a smaller ionization tendency than the material of the conductor layer.

[0026] According to yet another aspect of the present invention, there is provided the method for producing a multilayer wiring board according to any one of the above aspects, wherein the first metal-containing layer contains titanium. [Brief description of the drawings]

[0027] [Figure 1] 1 is a schematic cross-sectional view of a packaged device according to an embodiment of the present invention; [Diagram 2] 2 is a cross-sectional view showing a schematic view of a portion of a multilayer wiring substrate used in the packaged device shown in FIG. 1. [Diagram 3] 3 is an enlarged schematic cross-sectional view of a portion of the multilayer wiring board shown in FIG. 2. [Figure 4] 1 is a cross-sectional view illustrating a process of a method for manufacturing a multilayer wiring board according to an embodiment of the present invention. [Diagram 5] 6 is a cross-sectional view illustrating another step in the method for manufacturing a multilayer wiring board according to an embodiment of the present invention. [Figure 6] 11 is a cross-sectional view illustrating a process for producing a multilayer wiring board according to an embodiment of the present invention. FIG. [Figure 7] 11 is a cross-sectional view illustrating a process for producing a multilayer wiring board according to an embodiment of the present invention. FIG. [Figure 8]11 is a cross-sectional view illustrating a process for producing a multilayer wiring board according to an embodiment of the present invention. FIG. [Figure 9] 11 is a cross-sectional view illustrating a process for producing a multilayer wiring board according to an embodiment of the present invention. FIG. [Figure 10] 11 is a cross-sectional view illustrating a process for producing a multilayer wiring board according to an embodiment of the present invention. FIG. [Figure 11] 11 is a cross-sectional view illustrating a process for producing a multilayer wiring board according to an embodiment of the present invention. FIG. [Figure 12] 11 is a cross-sectional view illustrating a process for producing a multilayer wiring board according to an embodiment of the present invention. FIG. [Figure 13] 11 is a cross-sectional view illustrating a process for producing a multilayer wiring board according to an embodiment of the present invention. FIG. [Figure 14] 11 is a cross-sectional view illustrating a process for producing a multilayer wiring board according to an embodiment of the present invention. FIG. [Figure 15] 11 is a cross-sectional view illustrating a process for producing a multilayer wiring board according to an embodiment of the present invention. FIG. [Figure 16] 11 is a cross-sectional view illustrating a process for producing a multilayer wiring board according to an embodiment of the present invention. FIG. [Figure 17] 11 is a cross-sectional view illustrating a process for producing a multilayer wiring board according to an embodiment of the present invention. FIG. [Figure 18] 11 is a cross-sectional view illustrating a process for producing a multilayer wiring board according to an embodiment of the present invention. FIG. [Figure 19] 11 is a cross-sectional view illustrating a process for producing a multilayer wiring board according to an embodiment of the present invention. FIG. [Figure 20] 11 is a cross-sectional view illustrating a process for producing a multilayer wiring board according to an embodiment of the present invention. FIG. [Figure 21] 11 is a cross-sectional view illustrating a process for producing a multilayer wiring board according to an embodiment of the present invention. FIG. [Figure 22]11 is a cross-sectional view illustrating a process for producing a multilayer wiring board according to an embodiment of the present invention. FIG. [Diagram 23] 11 is a cross-sectional view illustrating a process for producing a multilayer wiring board according to an embodiment of the present invention. FIG. [Figure 24] 11 is a cross-sectional view illustrating a process for producing a multilayer wiring board according to an embodiment of the present invention. FIG. [Diagram 25] 11 is a cross-sectional view illustrating a process for producing a multilayer wiring board according to an embodiment of the present invention. FIG. [Figure 26] 11 is a cross-sectional view illustrating a process for producing a multilayer wiring board according to an embodiment of the present invention. FIG. [Figure 27] 11 is a cross-sectional view illustrating a process for producing a multilayer wiring board according to an embodiment of the present invention. FIG. [Figure 28] 1A-1D are cross-sectional views illustrating schematic steps of a method for manufacturing a packaged device according to an embodiment of the present invention. [Figure 29] 5A-5C are cross-sectional views each showing a schematic diagram of another process for manufacturing a packaged device according to an embodiment of the present invention. [Diagram 30] 5A-5C are cross-sectional views illustrating schematic steps of a method for manufacturing a packaged device in accordance with an embodiment of the present invention. [Diagram 31] 5A-5C are cross-sectional views illustrating schematic steps of a method for manufacturing a packaged device in accordance with an embodiment of the present invention. [Diagram 32] FIG. 11 is a cross-sectional view illustrating a multilayer wiring board according to a comparative example. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0028] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. The embodiment described below is a more specific embodiment of any of the above aspects. The embodiment described below shows an example of the technical idea of ​​the present invention, and does not limit the technical idea of ​​the present invention to the material, shape, structure, arrangement, etc. of the components described below. Various modifications can be made to the technical idea of ​​the present invention within the technical scope defined by the claims described in the claims.

[0029] In the drawings referred to in the following description, components having the same or similar functions are given the same reference numerals. It should be noted that the drawings are schematic, and the relationship between the dimension in the thickness direction and the dimension in the direction perpendicular to the thickness direction, i.e., the in-plane direction, and the relationship between the dimensions in the thickness direction of multiple layers, etc., may differ from the actual ones. Therefore, the specific dimensions should be determined with reference to the following description. It should also be noted that the dimensional relationship between two or more components may differ between multiple drawings. It should also be noted that the same structure is drawn upside down in some drawings compared to other drawings.

[0030] In this disclosure, the terms "upper surface" and "lower surface" refer to surfaces of a plate-like member or a layer contained therein that are perpendicular to the thickness direction, and refer to the surfaces facing upward and downward in the drawings, respectively. Also, the term "side surface" refers to a surface that is parallel to or inclined with respect to the thickness direction.

[0031] 1 is a cross-sectional view showing a schematic diagram of a packaged device 1 according to an embodiment of the present invention. As shown in FIG. 1, the packaged device 1 includes a composite wiring substrate 10, a functional device 20, a first underfill layer 30, and a first bonding electrode 40.

[0032] The functional device 20 is, for example, a semiconductor chip, or a chip in which circuits and elements are formed on a substrate made of a material other than a semiconductor, such as a glass substrate. Here, as an example, the functional device 20 is a semiconductor chip. That is, here, the packaged device 1 is a semiconductor package.

[0033] The packaged device 1 includes a plurality of functional devices 20. The packaged device 1 may include only one functional device as the functional device 20.

[0034] The functional devices 20 are bonded to the composite wiring board 10 via first bonding electrodes 40. Here, the multiple functional devices 20 are bonded to the composite wiring board 10 by flip chip bonding. One or more of the functional devices 20 may be bonded to the composite wiring board 10 by other bonding methods such as wire bonding.

[0035] The first bonding electrodes 40 bond the multiple functional devices 20 to the composite wiring board 10. A plurality of first bonding electrodes 40 are provided for each functional device 20. The multiple first bonding electrodes 40 that bond one functional device 20 to the composite wiring board 10 are arranged at a narrow pitch between the functional device 20 and the composite wiring board 10. The narrow pitch here means a pitch narrower than the pitch of multiple second bonding electrodes 14 of the composite wiring board 10, which will be described later.

[0036] The first bonding electrode 40 is made of, for example, solder. When the functional device 20 is bonded to the composite wiring board 10 by wire bonding, for example, a gold wire can be used to electrically connect the functional device 20 and the composite wiring board.

[0037] The first underfill layer 30 fixes the multiple functional devices 20 to the composite wiring board 10. When the packaged device 1 is configured to include only one functional device 20, the first underfill layer 30 fixes the single functional device 20 to the composite wiring board 10. In this embodiment, the first underfill layer 30 is provided between the functional device 20 and the composite wiring board 10. The first underfill layer 30 includes a portion interposed between the functional device 20 and the composite wiring board 10 and a portion at least partially covering the side surface of the functional device 20.

[0038] Composite wiring board 10 includes a first wiring board and a second wiring board joined thereto. Here, composite wiring board 10 includes FC-BGA substrate 11, multilayer wiring board 12, second underfill layer 13, and second bonding electrode 14.

[0039] The FC-BGA substrate 11 is an example of a first wiring substrate. The FC-BGA substrate 11 is joined to, for example, a motherboard (not shown).

[0040] The FC-BGA substrate 11 includes a core layer 111 , a resin layer 112 , a conductor layer 113 , a resin layer 114 , and a bonding conductor 115 .

[0041] The core layer 111 is a resin layer. The core layer 111 is, for example, a fiber-reinforced substrate in which a woven or nonwoven fabric is impregnated with a thermosetting insulating resin. For example, glass fiber, carbon fiber, or aramid fiber can be used as the woven or nonwoven fabric. For example, epoxy resin can be used as the insulating resin.

[0042] Through holes are formed in the core layer 111. Part of the conductor layer 113 covers the side walls of the through holes. Here, part of the conductor layer 113 covers the side walls of the through holes provided in the core layer 111 so as to generate through holes whose side walls are made of a conductor. These through holes whose side walls are made of a conductor may be filled with an insulator.

[0043] The remainder of the conductor layers 113 and the resin layers 112 form a multi-layer wiring structure on both major surfaces of the core layer 111. Each multi-layer wiring structure includes conductor layers 113 and resin layers 112 that are alternately stacked.

[0044] The resin layer 112 is, for example, an insulating resin layer, and has a through hole.

[0045] The conductor layer 113 is made of a metal such as copper or an alloy, and may have a single-layer structure or a multi-layer structure.

[0046] The conductor layer 113 includes a wiring portion and a land portion. The conductor layer 113 facing the core layer 111 with the resin layer 112 sandwiched therebetween further includes a via portion covering the side wall of a through hole provided in the resin layer 112.

[0047] The resin layer 114 is provided on the multilayer wiring structure. The resin layer 114 is, for example, an insulating resin layer such as a solder resist. The resin layer 114 is provided with a through hole communicating with the conductor layer 113 located on the outermost surface of the multilayer wiring structure.

[0048] The bonding conductor 115 is formed so as to be capable of electrically bonding the packaged device 1 to another component such as a substrate. The bonding conductor 115 is, for example, a metal bump provided on a portion of the conductor layer 113 that is exposed at the position of the through hole of the resin layer 114. The bonding conductor is also called a bonding terminal. The bonding conductor 115 is, for example, made of solder.

[0049] The multilayer wiring board 12 is an example of a second wiring board. The multilayer wiring board 12 is bonded to the functional device 20 via a first bonding electrode 40. The multilayer wiring board 12 is bonded to the FC-BGA board 11 via a second bonding electrode 14. That is, in this embodiment, the multilayer wiring board 12 is an interposer that mediates the bonding between the functional device 20 and the FC-BGA board 11. The thickness of the multilayer wiring board 12 is, for example, in the range of 10 μm to 300 μm. The multilayer wiring board 12 will be described in detail later.

[0050] The second bonding electrodes 14 are arranged between the multilayer wiring substrate 12 and the functional device 20. The pitch of the second bonding electrodes 14 is wider than the pitch of the first bonding electrodes 40 and narrower than the pitch of the bonding conductors 115 located on the lower surface of the FC-BGA substrate 11. The second bonding electrodes 14 are made of, for example, solder.

[0051] The second underfill layer 13 includes a portion interposed between the FC-BGA substrate 11 and the multilayer wiring substrate 12. The underfill layer is also called a sealing resin layer. The second underfill layer 13 fixes the multilayer wiring substrate 12 to the FC-BGA substrate 11.

[0052] The multilayer wiring board 12 will be described in more detail with reference to FIGS. Fig. 2 is a cross-sectional view that diagrammatically illustrates a portion of the multilayer wiring board 12. Fig. 3 is a cross-sectional view that diagrammatically illustrates an enlarged portion of the multilayer wiring board 12 shown in Fig. 2. Fig. 3 specifically illustrates a portion of a first layer 70, a portion of a second layer 80, and their vicinities, which will be described later.

[0053] As shown in Figures 2 and 3, the multilayer wiring board 12 includes two or more stacked layers 50, an insulating resin layer 61, a seed adhesion layer 101, a seed layer 102, a conductor layer 103, a solder resist layer 104, a surface treatment layer 105, an insulating resin layer 107, and a conductor layer 108.

[0054] Here, two layers 50 are provided. The number of layers 50 may be three or more. Hereinafter, the two layers 50 will be referred to as a first layer 70 and a second layer 80. The first layer 70 is provided on an insulating resin layer 61. The first layer 70 includes a first insulating resin layer 71, a first inorganic insulating layer 160, and a first wiring layer 72.

[0055] The first insulating resin layer 71 has insulating properties. The first insulating resin layer 71 is provided on the insulating resin layer 61. The first insulating resin layer 71 has a first surface 71a and a second surface 71b which is the reverse surface of the first surface 71a. In this embodiment, the first surface 71a is the surface on the insulating resin layer 61 side. The second surface 71b is the surface on the second layer 80 side. The first insulating resin layer 71 is also formed with a groove 74, a land recess 75 which is a first recess, and a via recess 76 which is a second recess.

[0056] The groove portion 74 is formed on the first surface 71a of the first insulating resin layer 71 and opens at the first surface 71a. The groove portion 74 is a groove for forming a wiring portion 72b described later. A plurality of groove portions 74 are provided. The groove portions 74 have a depth that does not reach the second surface 71b of the first insulating resin layer 71.

[0057] The groove 74 is formed in a shape that gradually narrows toward the first surface 71a. The groove 74 has an inner surface 74a that is a side wall, and a bottom surface 74b.

[0058] In this embodiment, as shown in Fig. 2, the groove 74 is formed in a trapezoidal shape when cut along a cut surface perpendicular to the extension direction of the groove 74. That is, the cross section of the groove 74 in the cut surface is inverted tapered. The cross section of the groove 74 in this cut surface may be rectangular.

[0059] The land recess 75 is formed on the first surface 71a of the first insulating resin layer 71 and opens at the first surface 71a. The land recess 75 is a recess for forming a land portion 72a described later. A plurality of land recesses 75 are formed. Each of the plurality of land recesses 75 communicates with one of the groove portions 74. In addition, one or more of the land recesses 75 communicates with a via recess 76 included in the first insulating resin layer 71 in which the land recess 75 is provided.

[0060] The land recess 75 has an inner surface 75a which is a side wall, and a bottom surface 75b. Here, the land recess 75 is formed in a shape in which the dimension in a direction perpendicular to the thickness direction gradually decreases from the second surface 71b toward the first surface 71a. That is, the land recess 75 has a cross section perpendicular to the thickness direction in an inverse tapered shape. The land recess 75 is formed in, for example, a truncated cone shape. The land recess 75 may have a cross section parallel to the thickness direction in a rectangular shape.

[0061] The via recesses 76 are formed on the second surface 71b of the first insulating resin layer 71 and open at the second surface 71b. The via recesses 76 are recesses for forming the via portions 73. A plurality of via recesses 76 are formed. Each of the via recesses 76 communicates with one of the land recesses 75.

[0062] The via recess 76 has an inner surface 76a which is a side wall. The via recess 76 is formed in a shape in which the dimension in a direction perpendicular to the thickness direction gradually decreases from the second surface 71b toward the first surface 71a. That is, the via recess 76 has a cross section perpendicular to the thickness direction in an inverse tapered shape. The via recess 76 is formed in, for example, a truncated cone shape. The via recess 76 may have a cross section parallel to the thickness direction in a rectangular shape.

[0063] The edge of the inner side surface 76a on the first surface 71a side is surrounded by the edge of the land recess 75 on the second surface 71b side. When observed in the thickness direction of the first insulating resin layer 71, the position of the center of each via recess 76 approximately coincides with the position of the center of the land recess 75 connected to that via recess 76.

[0064] The first insulating resin layer 71 thus configured is integrally formed in the thickness direction.

[0065] The first inorganic insulating layer 160 includes a portion covering the inner side surface 74a and the bottom surface 74b, a portion covering the inner side surface 75a and the bottom surface 75b, and a portion covering the first surface 71a. That is, the first inorganic insulating layer 160 covers the inner surfaces of the grooves 74, the inner surfaces of the land recesses 75, and the first surface 71a.

[0066] The first inorganic insulating layer 160 is conformal to the surface on the first surface 71a side of the first insulating resin layer 71. The first inorganic insulating layer 160 has an opening 161 at the position of the opening 74c of the groove portion 74, and an opening 162 at the position of the opening 75c of the land recess 75. The land recess 75 communicates with the via recess 76 at the position of its bottom surface 75b, and therefore the bottom surface 75b is configured in an annular shape. Therefore, the portion of the first inorganic insulating layer 160 covering the bottom surface 75b is also configured in an annular shape.

[0067] The first wiring layer 72 fills the groove portion 74, the land recess 75, and the recess of the insulating resin layer adjacent to the first layer 70. Here, in this embodiment, the recess of the resin layer adjacent to the first layer 70 is a via hole 63, which will be described later, formed in the insulating resin layer 61.

[0068] As described above, in this embodiment, the first inorganic insulating layer 160 is provided on the inner surface of the groove portion 74 and the inner surface of the land recess portion 75. Therefore, the first inorganic insulating layer 160 is interposed between the first wiring layer 72 and the first insulating resin layer 71.

[0069] The first wiring layer 72 includes a seed adhesion layer 78 , a seed layer 79 , and a conductor layer 77 .

[0070] The conductor layer 77 fills the grooves 74 and the land recesses 75 of the first insulating resin layer 71, and the via holes 63 of the insulating resin layer 61. The portion of the conductor layer 77 into which the grooves 74 are filled constitutes the wiring portion 72b. The portion of the conductor layer 77 into which the land recesses 75 are filled constitutes the land portion 72a. The portion of the conductor layer 77 into which the via holes 63 are filled constitutes the via portion 62. The via portion 62 protrudes from the first surface 71a at the position of the land portion 72a. The conductor layer 77 is made of, for example, copper.

[0071] The seed adhesion layer 78 is a first metal-containing layer. The seed adhesion layer 78 is a layer containing titanium. The seed adhesion layer 78 covers the lower surface and side surface of each of the wiring portion 72b and the via portion 62. The seed adhesion layer 78 also covers the peripheral portion of the side surface and lower surface of the land portion 72a. The seed layer 79 is a second metal-containing layer. The seed layer 79 is a metal layer interposed between the seed adhesion layer 78 and the conductor layer 77. The seed layer 79 is made of the same material as the conductor layer 77 or a metal material having a smaller ionization tendency than the material of the conductor layer 77. The seed layer 79 is made of, for example, copper.

[0072] 2, the second layer 80 is provided on the first layer 70. The second layer 80 has a similar structure to the first layer 70.

[0073] Specifically, the second layer 80 includes a second insulating resin layer 81, a second inorganic insulating layer 170, and a second wiring layer 82. The second insulating resin layer 81, the second inorganic insulating layer 170, and the second wiring layer 82 correspond to the first insulating resin layer 71, the first inorganic insulating layer 160, and the first wiring layer 72, respectively.

[0074] The second insulating resin layer 81 has a first surface 81a and a second surface 81b. A groove 84, a land recess 85 as a first recess, and a via recess 86 as a second recess are formed in the second insulating resin layer 81. The first surface 81a, the second surface 81b, the groove 84, the land recess 85, and the via recess 86 of the second insulating resin layer 81 correspond to the first surface 71a, the second surface 71b, the groove 74, the land recess 75, and the via recess 76 of the first insulating resin layer 71, respectively.

[0075] The inner side surface 84a, bottom surface 84b, and opening 84c of the groove 84 correspond to the inner side surface 74a, bottom surface 74b, and opening 74c of the groove 74. The inner side surface 85a, bottom surface 85b, and opening 85c of the land recess 85 correspond to the inner side surface 75a, bottom surface 75b, and opening 75c of the land recess 75. The inner side surface 86a and opening 86c of the via recess 86 correspond to the inner side surface 76a and opening 76c of the via recess 76, respectively.

[0076] The second inorganic insulating layer 170 has openings 171 and 172. These openings 171 and 172 correspond to the openings 161 and 162 formed in the first inorganic insulating layer 160, respectively.

[0077] The second wiring layer 82 includes a seed adhesion layer 88, a seed layer 89, and a conductor layer 87. The seed adhesion layer 88, the seed layer 89, and the conductor layer 87 correspond to the seed adhesion layer 78, the seed layer 79, and the conductor layer 77, respectively.

[0078] The conductor layer 87 fills the grooves 84 and the land recesses 85 of the second insulating resin layer 81 and the via recesses 76 of the first insulating resin layer 71. The portion of the conductor layer 87 into which the grooves 84 are filled constitutes the wiring portion 82b. The portion of the conductor layer 87 into which the land recesses 85 are filled constitutes the land portion 82a. The portion of the conductor layer 87 into which the via recesses 76 are filled constitutes the via portion 73. The wiring portion 82b, the land portion 82a, and the via portion 73 correspond to the wiring portion 72b, the land portion 72a, and the via portion 62, respectively.

[0079] The insulating resin layer 61 is provided on the first surface 71a side. The insulating resin layer 61 has the first surface 61a and a second surface 61b. The first surface 61a is the surface opposite to the first layer 70. The second surface 61b is the surface on the first layer 70 side.

[0080] A via hole 63 is formed in the insulating resin layer 61. The via hole 63 is a hole penetrating the insulating resin layer 61 in the thickness direction, and opens at the first surface 61a and the second surface 61b. The via hole 63 has an inner side surface 64. The via hole 63 is formed in a shape such that the dimension in a direction perpendicular to the thickness direction gradually decreases from the second surface 61b toward the first surface 61a. The via hole 63 is formed in, for example, a truncated cone shape. As described above, the via hole 63 is filled with a part of the first wiring layer 72.

[0081] The seed adhesion layer 101 is, for example, a first metal-containing layer. The seed adhesion layer 101 is, for example, a layer containing titanium. The seed adhesion layer 101 includes a portion covering a part of the second surface 81b and a portion covering the inner surface of the via recess 86.

[0082] The seed layer 102 is, for example, a second metal-containing layer. The seed layer 102 is a metal layer provided on the seed adhesion layer 101. The seed layer 102 is made of the same material as the conductor layer 103 or a metal material having a smaller ionization tendency than the material of the conductor layer 103. The seed layer 102 is made of, for example, copper.

[0083] The conductor layer 103 is provided on the seed adhesion layer 101. The conductor layer 103 fills the via recess 86. The portion of the conductor layer 103 that fills the via recess 86 is the via portion 83. The conductor layer 103 is electrically connected to an interlayer connection conductor layer 90 composed of a conductor layer 77 and a conductor layer 87 through the seed adhesion layer 101 and the seed layer 102. The conductor layer 103 is made of, for example, copper.

[0084] The solder resist layer 104 is provided on the second layer 80 and the conductor layer 103. The solder resist layer 104 has through holes 104a that expose parts of the conductor layer 103. These through holes 104a enable electrical connection between the multilayer wiring board 12 and the FC-BGA board 11 via the second bonding electrodes 14.

[0085] The surface treatment layer 105 is provided on a portion of the conductor layer 103 that is exposed in the through-hole 104a of the solder resist layer 104. The surface treatment layer 105 prevents oxidation of the surface of the conductor layer 103 and improves wettability with solder.

[0086] The insulating resin layer 107 is provided on the first surface 61a of the insulating resin layer 61 and a part of the first wiring layer 72. The insulating resin layer 107 has a through hole at the position of the via portion 62.

[0087] The conductor layer 108 is formed in the through hole of the insulating resin layer 107. The conductor layer 108 is made of, for example, copper. The first bonding electrode 40 shown in FIG.

[0088] Next, a description will be given of an example of a method for manufacturing the multilayer wiring board 12. Figures 4 to 23 are cross-sectional views that roughly show an example of a method for manufacturing the multilayer wiring board 12.

[0089] In one example of this manufacturing method, first, a structure shown in Fig. 5 is obtained. Below, the steps for obtaining the structure in Fig. 5 will be described in order.

[0090] First, as shown in FIG. 4, a release layer 3 is provided on one surface of a support 2 . The support 2 is preferably transparent since light may be irradiated onto the peeling layer 3 through the support 2. The support 2 may be, for example, a glass plate. Since a glass plate has excellent flatness and high rigidity, it is suitable for forming a fine pattern of the multilayer wiring board 12 on the support 2. Furthermore, since a glass plate has a small CTE (coefficient of thermal expansion) and is not easily distorted, it is excellent in ensuring pattern arrangement accuracy and flatness.

[0091] When a glass plate is used as the support 2, the thickness of the glass plate is preferably thicker from the viewpoint of preventing warping during the manufacturing process, and is, for example, 0.5 mm or more, preferably 1.2 mm or more. The CTE of the glass plate is preferably 3 ppm or more and 16 ppm or less, and more preferably about 10 ppm from the viewpoint of the CTE of the FC-BGA substrate 11 and the functional device 20.

[0092] Examples of glass used as a material for forming the support 2 include quartz glass, borosilicate glass, alkali-free glass, soda glass, and sapphire glass. In cases where the support 2 does not need to be transparent when peeling the support 2, such as when a resin that foams when heated is used for the peeling layer 3, a material with little distortion, such as metal or ceramics, can be used for the support 2. In the example of this embodiment, glass is used for the support 2.

[0093] The release layer 3 may be, for example, a resin that absorbs light such as UV light, generates heat or changes in quality, and becomes peelable, or may be a resin that foams when heated and becomes peelable. When a resin that becomes peelable when exposed to light such as UV light, for example, laser light, is used, the support 2 is irradiated with light from the side opposite to the side where the release layer 3 is provided, and the support 2 is removed from the bonded body of the multilayer wiring board 12 and the FC-BGA board 11 on the support 2.

[0094] The release layer 3 can be selected from organic resins such as epoxy resin, polyimide resin, polyurethane resin, silicone resin, polyester resin, oxetane resin, maleimide resin, and acrylic resin, and inorganic layers such as amorphous silicon, gallium nitride, and metal oxide layers. The release layer 3 may further contain additives such as a photodecomposition accelerator, a light absorber, a sensitizer, and a filler.

[0095] Furthermore, the peeling layer 3 may have a single-layer structure or a multi-layer structure. For example, a protective layer may be provided on the peeling layer 3 for the purpose of protecting the multilayer wiring board 12 formed on the support 2, and a layer for improving the adhesion between the support 2 and the peeling layer 3 may be provided between the support 2 and the peeling layer 3. Furthermore, a laser light reflecting layer or a metal layer may be provided between the peeling layer 3 and the multilayer wiring board 12. The configuration of the peeling layer 3 is not limited to this embodiment. In the example of this embodiment, the peeling layer 3 is made of a resin that absorbs UV light and becomes peelable.

[0096] 5, a seed adhesion layer 5 and a seed layer 6 are provided on the release layer 3, for example, in a vacuum. The seed adhesion layer 5 is a layer that improves the adhesion of the seed layer 6 to the release layer 3 and prevents peeling of the seed layer 6. The seed layer 6 also acts as a power supply layer for electrolytic plating in forming wiring.

[0097] The seed adhesion layer 5 and the seed layer 6 can be formed by, for example, a sputtering method or a vapor deposition method. Examples of materials for the seed adhesion layer 5 and the seed layer 6 include Cu, Ni, Al, Ti, Cr, Mo, W, Ta, Au, Ir, Ru, Pd, Pt, AlSi, AlSiCu, AlCu, NiFe, ITO (Indium Tin Oxide), IZO (Indium Zinc Oxide), AZO (Aluminum-doped Zinc Oxide), ZnO, PZT (Lead Zirconate Titanate), TiN, Cu 3 N 4 , a Cu alloy, or a combination of a plurality of these may be used. In the example of the present embodiment, in consideration of electrical characteristics, ease of manufacture, and cost, a titanium layer is formed as the seed adhesion layer 5 and a copper layer is formed as the seed layer 6 in this order by a sputtering method.

[0098] The total thickness of the seed adhesion layer 5 and the seed layer 6 is preferably 1 μm or less. In this example, a titanium layer having a thickness of 50 nm is formed as the seed adhesion layer 5, and a copper layer having a thickness of 300 nm is formed as the seed layer 6.

[0099] Next, as shown in Fig. 6, a resist layer 140 is provided on the seed layer 6. When a liquid resist is used as the material of the resist layer 140, the resist layer 140 can be formed by any of the following methods: slit coating, curtain coating, die coating, spray coating, electrostatic coating, inkjet coating, gravure coating, screen printing, gravure offset printing, spin coating, and doctor coating. When a film-like resist is used for the resist layer 140, the resist layer 140 can be provided on the seed layer 6 by any of the following methods: lamination, vacuum lamination, vacuum pressing, and the like.

[0100] Next, through holes 141 are formed in the resist layer 140 by, for example, photolithography. Plasma treatment may be performed on the through holes 141 to remove residues from development. The thickness of the resist layer 140 is set according to the thickness of the conductor layer 108 to be provided in the through holes 141. In this embodiment, the thickness of the resist layer 140 is, for example, 8 μm.

[0101] The shape of the through holes 141 in a plan view is set according to the pitch of the bonding electrodes of the functional device 20 and the shape of the bonding electrodes. In this embodiment, the through holes 141 are circular, have an opening shape of φ25 μm, and have a pitch of 55 μm. Note that the plan view here refers to the shape seen in the thickness direction of the resist layer 140.

[0102] 7, a conductor layer 108 is formed on the seed layer 6 by electrolytic plating. The conductor layer 108 constitutes an electrode for bonding with the functional device 20. Examples of electrolytic plating for forming the conductor layer 108 include electrolytic nickel plating, electrolytic copper plating, electrolytic chromium plating, electrolytic Pd plating, electrolytic gold plating, electrolytic rhodium plating, and electrolytic iridium plating, among which electrolytic copper plating is preferable because it is simple, inexpensive, and has good electrical conductivity.

[0103] Since the conductor layer 108 serves as an electrode for bonding to the functional device 20, it is desirable that the thickness of the conductor layer 108 be 1 μm or more from the viewpoint of solder bonding, and 30 μm or less from the viewpoint of productivity.

[0104] 8, the resist layer 140 is removed. The resist layer 140 can be dissolved or peeled off by dry etching or by immersion in an alkaline solution or solvent.

[0105] 9, an insulating resin layer 107 is provided so as to embed the conductor layer 108. The insulating resin layer 107 may be photosensitive or non-photosensitive, and further, it does not have to be made of the same material as the insulating resin layers 61, 71, and 81 described below.

[0106] 10, the upper surface of the conductor layer 108 is exposed by physical polishing, or by physical polishing and surface polishing such as CMP processing. The conductor layer 108 may be formed by a semi-additive process.

[0107] 11, an insulating resin layer 61 is provided on the conductor layer 108 and the insulating resin layer 107. The insulating resin layer 61 is formed of, for example, a photosensitive resin.

[0108] As the photosensitive resin, for example, a photosensitive polyimide resin, a photosensitive benzocyclobutene resin, a photosensitive epoxy resin, or a modified product thereof can be used. As an example, a photosensitive epoxy resin is used as the photosensitive resin.

[0109] The photosensitive resin may be in the form of a liquid or a film.

[0110] When a liquid photosensitive resin is used, the insulating resin layer 61 can be formed by a method selected from, for example, slit coating, curtain coating, die coating, spray coating, electrostatic coating, inkjet coating, gravure coating, screen printing, gravure offset printing, spin coating, and doctor coating. According to one example, the insulating resin layer 61 is formed by a spin coating method using a photosensitive resin. Photosensitive epoxy resin can be cured at a relatively low temperature and shrinks little when cured, which is advantageous for the subsequent formation of fine patterns.

[0111] When a film-like photosensitive resin is provided as the insulating resin layer 61, lamination, vacuum lamination, vacuum pressing, or the like can be applied. The insulating resin layer 61 is formed so as to have a thickness of, for example, 2 μm on the conductor layer 108 .

[0112] Next, via holes 63 are formed in the insulating resin layer 61 at the positions of the conductor layer 108, for example, by photolithography. When a non-photosensitive resin is used, the via holes 63 can be formed, for example, by laser light irradiation. In this manner, a base layer whose surface is constituted by the exposed surface of the insulating resin layer 61 and the exposed surface of the conductor layer 108 is obtained.

[0113] Next, as shown in FIG. 12, a resist layer 143 is formed on the underlayer consisting of the insulating resin layer 61 and the conductor layer 108. The resist layer 143 can be formed by applying a photosensitive resin to the underlayer. As the photosensitive resin, for example, the resin exemplified for the insulating resin layer 61 can be used. Similarly to the insulating resin layer 61, the resist layer 143 can be formed by any of the following methods: slit coating, curtain coating, die coating, spray coating, electrostatic coating, inkjet coating, gravure coating, screen printing, gravure offset printing, spin coating, and doctor coating. Here, as an example, a photosensitive epoxy resin is used to form the resist layer 143 by spin coating.

[0114] Next, a groove 144 corresponding to the groove portion 74 and a through hole 145 corresponding to the land recess 75 are formed in the resist layer 143 by photolithography. Here, as an example, the groove 144 is formed so that a cross section perpendicular to the length direction has a forward tapered shape. The through hole 145 is also formed in a forward tapered shape. The groove 144 and the through hole 145 may be formed so that their cross sections have a rectangular shape, but forming them in a forward tapered shape makes it easier to form the seed adhesion layer 78 without generating discontinuous parts in the groove 144 and the through hole 145.

[0115] Furthermore, when the groove 144 and the through hole 145 are formed so that their cross sections have a forward tapered shape, the contact area between the first insulating resin layer 71 and the first inorganic insulating layer 160 increases compared to when their cross sections are rectangular. This makes it possible to improve the adhesion between the first insulating resin layer 71 and the first inorganic insulating layer 160. Similarly, it is possible to improve the adhesion between the first inorganic insulating layer 160 and the seed adhesion layer 78, the adhesion between the seed adhesion layer 78 and the seed layer 79, and the adhesion between the seed layer 79 and the conductor layer 77.

[0116] The resist layer 143 in which the grooves 144 and the through holes 145 are formed as described above is an example of a dummy layer. One or more of the through holes 145 communicate with the via holes 63. The opening of the through hole 145 on the via hole 63 side is larger than the opening of the via hole 63 on the through hole 145 side. The opening of the via hole 63 on the through hole 145 side is disposed within the opening of the through hole 145.

[0117] 13, a seed adhesion layer 78 is formed, for example, in a vacuum, on the resist layer 143, the insulating resin layer 61, and the conductor layer 108. Then, a seed layer 79 is formed, for example, in a vacuum, on the seed adhesion layer 78.

[0118] In this embodiment, the seed adhesion layer 78 is formed of titanium from the viewpoints of electrical properties, ease of manufacture, and cost, and also to function as a copper diffusion prevention layer. Also, the seed layer 79 is formed of copper, taking into consideration electrical properties, ease of manufacture, and cost. The seed adhesion layer 78 and the seed layer 79 are formed in sequence by a sputtering method. If a vapor phase deposition method is used for forming these films, the seed adhesion layer 78 and the seed layer 79 are provided on the entire exposed surfaces of the resist layer 143, the insulating resin layer 61, and the conductor layer 108, as shown in FIG. 13.

[0119] The total thickness of the seed adhesion layer 78 and the seed layer 79 is preferably 1 μm or less. Note that materials other than titanium may be used for the seed adhesion layer 78 as long as they have a copper diffusion prevention function. The material of the seed layer 79 may be the same as that of the conductor layer 77 or may be a metal material having a smaller ionization tendency than that of the conductor layer 77.

[0120] In this embodiment example, the seed adhesion layer 78 has a thickness of 50 nm, and the seed layer 79 has a thickness of 300 nm.

[0121] One or more other layers made of a metal material may be provided between the seed adhesion layer 78 and the seed layer 79. The layer provided between the seed adhesion layer 78 and the seed layer 79 is made of the same material as the conductor layer 77 or is made of a metal material having a smaller ionization tendency than the material of the conductor layer 77.

[0122] 14, a conductor layer 77 is formed on the seed layer 79 by, for example, electrolytic plating. The electrolytic plating for forming the conductor layer 77 is, for example, electrolytic copper plating. This electrolytic plating is performed so that the via holes 63, the through holes 145, and the grooves 144 are completely filled with the conductor layer 77, as shown in FIG.

[0123] 15, the conductor layer 77 and the seed layer 79 are subjected to polishing such as physical polishing and CMP (chemical mechanical polishing) to remove the portions of the conductor layer 77 and the seed layer 79 that are located outside the via hole 63, the through hole 145, and the groove 144. The seed adhesion layer 78 is also subjected to the same polishing to remove the portions of the seed adhesion layer 78 that are located outside the via hole 63, the through hole 145, and the groove 144. Note that with this polishing, a portion near the upper surface of the resist layer 143 may also be removed.

[0124] In this manner, the via portion 62, the land portion 72a, and the wiring portion 72b are obtained by respectively filling the via hole 63, the through hole 145, and the groove 144. In this method, unlike the conventional semi-additive method, a smooth conductor surface can be obtained because no etching process is performed.

[0125] 16, the resist layer 143 is removed. The resist layer 143 can be removed by dry etching or by immersion in an alkaline solution or solvent.

[0126] Next, as shown in Fig. 17, a first inorganic insulating layer 160 is formed on the surface on the conductor layer 77 side of the structure shown in Fig. 16. The material of the first inorganic insulating layer 160 includes, for example, one or more insulators selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride, silicon oxide doped with fluorine, and silicon oxide doped with carbon.

[0127] The first inorganic insulating layer 160 can be formed by, for example, plasma CVD (Chemical Vapor Deposition). The land portion 72a and the wiring portion 72b have an inversely tapered cross-sectional shape, and by using plasma CVD, the first inorganic insulating layer 160 can be formed not only on the upper surfaces of the conductor layer 77 and the insulating resin layer 61, but also on the portions of the seed adhesion layer 78 that cover the side surfaces of the land portion 72a and the wiring portion 72b.

[0128] In addition, a layer made of a silane coupling agent may be provided between the first inorganic insulating layer 160 and the wiring portion 72b and between the first inorganic insulating layer 160 and the land portion 72a. By providing a layer made of a silane coupling agent, it is possible to improve the adhesion between the first inorganic insulating layer 160 and the seed adhesion layer 78, the adhesion between the first inorganic insulating layer 160 and the seed layer 79, and the adhesion between the first inorganic insulating layer 160 and the conductor layer 77. When these adhesions are improved, even if the multilayer wiring board 12 is warped due to, for example, heat, peeling of the first inorganic insulating layer 160 and the seed adhesion layer 78, peeling of the first inorganic insulating layer 160 and the seed layer 79, and peeling of the first inorganic insulating layer 160 and the conductor layer 77 are unlikely to occur.

[0129] Moreover, the multilayer wiring board 12 of the present embodiment exhibits higher insulation reliability than a configuration in which an inorganic insulating layer is formed on a wiring portion formed by a conventional semi-additive process. When the semi-additive process is used, the wiring portion is formed by etching, so that the surface of the wiring portion is roughened.

[0130] Since the surface of the wiring is roughened, the conformability of the inorganic insulating film is reduced, which may result in the formation of pinholes in the inorganic insulating film. Copper diffuses through these pinholes, reducing the insulation reliability. Furthermore, if the inorganic insulating film is made thicker to eliminate the pinholes, the effect of the difference in linear expansion coefficient between copper and the inorganic insulating film becomes stronger, which may cause peeling at the copper / inorganic insulating film interface.

[0131] Next, as shown in FIG. 18, a first insulating resin layer 71 having a via recess 76 is formed on the first inorganic insulating layer 160, for example, by the same method as that described above for the insulating resin layer 61. For example, the first insulating resin layer 71 having the via recess 76 at one or more positions of the land portion 72a is obtained by spin-coating a photosensitive epoxy resin on the first inorganic insulating layer 160 and photolithography. Since the photosensitive resin can be cured at a relatively low temperature, there is little shrinkage associated with curing. This is therefore advantageous for the subsequent formation of a fine pattern.

[0132] The first insulating resin layer 71 can also be formed of a non-photosensitive resin such as a non-photosensitive polyimide insulating resin. For example, the first inorganic insulating layer 160 is spin-coated with a non-photosensitive resin, and the resin layer is irradiated with laser light to obtain the first insulating resin layer 71 having via recesses 76 at one or more positions of the land portion 72a. A non-photosensitive resin such as polyimide has excellent insulating properties and mechanical properties, and can also achieve high heat resistance.

[0133] In this manner, the first layer 70 including the first insulating resin layer 71, the conductor layer 77, the seed adhesion layer 78, the seed layer 79, and the first inorganic insulating layer 160 is obtained.

[0134] Next, the second layer 80 is formed on the base layer consisting of the first insulating resin layer 71 and the first inorganic insulating layer 160 in substantially the same manner as described above for the first layer 70.

[0135] That is, first, by a method similar to that described above for the resist layer 143, a resist layer 180 having grooves 181 and through holes 182 corresponding to the grooves 84 and the land recesses 85, respectively, is formed on the underlayer of the first inorganic insulating layer 160 made of the first insulating resin layer 71, as shown in Fig. 19. The resist layer 180 is an example of a dummy layer.

[0136] 20, the portion of the first inorganic insulating layer 160 exposed in the via recess 76 is removed by dry etching or the like. Next, the seed adhesion layer 88 and the seed layer 89 are sequentially formed by the same methods as those described above for the seed adhesion layer 78 and the seed layer 79, respectively.

[0137] This enables electrical connection between the land portion 72a and the via portion 73 formed thereon. Note that the removal of the portion exposed in the via recess 76 of the first inorganic insulating layer 160 may be performed after the via recess 76 is formed in the first insulating resin layer 71 and before the resist layer 180 is formed.

[0138] Next, by sequentially performing steps similar to those described with reference to Figures 14 to 18, a seed adhesion layer 88, a seed layer 89, a conductor layer 87 including a land portion 82a, a wiring portion 82b and a via portion 73, a second inorganic insulating layer 170, and a second insulating resin layer 81 are formed.

[0139] In this manner, the second layer 80 including the second insulating resin layer 81, the conductor layer 87, the seed adhesion layer 88, the seed layer 89, and the second inorganic insulating layer 170 is obtained.

[0140] Next, as shown in FIG. 22, the portion of the second inorganic insulating layer 170 exposed within the via recess 86 is removed by, for example, dry etching.

[0141] Next, for example, by a method similar to that described above for the seed adhesion layer 78 and the seed layer 79, the seed adhesion layer 101 and the seed layer 102 are successively formed on the second insulating resin layer 81 and the land portion 82a as shown in FIG. Next, for example, by the same method as that described above for the insulating resin layer 107, a resist layer 146 having through holes 147 is formed on the seed layer 102 as shown in FIG.

[0142] 25, a conductor layer 103 is formed on the seed layer 102. The conductor layer 103 is preferably formed by electrolytic copper plating.

[0143] Next, as shown in FIG. 26, the resist layer 146 is removed.

[0144] Next, as shown in FIG. 27, the exposed portion of the seed adhesion layer 101 is removed, and then the exposed portion of the seed layer 102 is removed. The resist layer 146 is removed, for example, by a solution or a solvent. The seed adhesion layer 101 and the seed layer 102 can be removed, for example, by immersing them in a chemical solution. The chemical solution for removing the seed adhesion layer 101 is, for example, an alkaline etching agent. The chemical solution for removing the seed layer 102 is, for example, an acidic etching agent.

[0145] 28, a solder resist layer 104 is provided on the second insulating resin layer 81 and the conductor layer 103. Next, through holes 104a are formed in the solder resist layer 104. The material for the solder resist layer 104 may be an insulating resin such as an epoxy resin or an acrylic resin. In the embodiment of the present invention, a photosensitive epoxy resin containing a filler is used as the solder resist layer 104.

[0146] Next, the surface treatment layer 105 is formed on the portion of the conductor layer 103 exposed in the through hole 104a. In this embodiment, the surface treatment layer 105 is formed by electroless Ni / Pd / Au plating. The surface treatment layer 105 may be an OSP (Organic Solderability Preservative) film, that is, a surface treatment layer made of a water-soluble preflux. Alternatively, the surface treatment layer 105 may be an electroless tin plating or an electroless Ni / Au plating layer. This completes the multilayer wiring board 12 supported on the support 2, that is, the multilayer wiring board with a support.

[0147] Next, a solder material is placed on the surface treatment layer 105, and then melted, cooled, and fixed to obtain the second bonding electrode 14.

[0148] 29, the multilayer wiring board 12 on the support 2 and the FC-BGA board 11 are joined together, and then a second underfill layer 13 is formed therebetween. The material for the second underfill layer 13 is, for example, a material in which one of epoxy resin, urethane resin, silicone resin, polyester resin, oxetane resin, and maleimide resin, or a mixture of two or more of these resins, to which silica, titanium, aluminum oxide, magnesium oxide, zinc oxide, or the like is added as a filler, is used. The second underfill layer 13 is formed by filling with a liquid resin.

[0149] Next, the support 2 is removed as shown in Fig. 30 and Fig. 31. One example of the removal is peeling. For example, as shown in Fig. 30, a laser beam 23 is irradiated from the rear surface of the support 2, i.e., the surface of the support 2 opposite to the FC-BGA substrate 11, to the peeling layer 3 formed at the interface with the support 2. By irradiating the laser beam 23, it becomes possible to remove the support 2 from the multilayer wiring substrate 12 as shown in Fig. 31.

[0150] Next, the release layer 3, the seed adhesion layer 5 and the seed layer 6 are sequentially removed to obtain the composite wiring board 10.

[0151] 1, a functional device 20 is mounted to complete the packaged device 1. Prior to mounting the functional device 20, the conductor layer exposed on the surface may be subjected to a surface treatment such as electroless Ni / Pd / Au plating, OSP, electroless tin plating, or electroless Ni / Au plating to prevent oxidation and improve the wettability of the solder bumps.

[0152] The joints are then sealed with a first underfill layer 30 . The material of the first underfill layer 30 may be, for example, the material exemplified for the second underfill layer 13. The first underfill layer 30 may be formed, for example, by the same method as that described above for the second underfill layer 13.

[0153] In this manner, the packaged device 1 shown in FIG. 1 is completed.

[0154] In the above method, the multilayer wiring board 12 is bonded to the FC-BGA substrate 11, and then the functional device 20 is bonded to the multilayer wiring board 12. Alternatively, the functional device 20 may be bonded to the multilayer wiring board 12, and then the multilayer wiring board 12 may be bonded to the FC-BGA substrate 11.

[0155] In the packaged device 1 configured in this manner, in the first layer 70, a first inorganic insulating layer 160 is interposed between the bottom surface 74b of the groove portion 74 and the first insulating resin layer 71, and between the bottom surface 75b of the land recess 75 and the first insulating resin layer 71. Of the first inorganic insulating layer 160, a portion interposed between the bottom surface 74b and the first insulating resin layer 71 and a portion interposed between the bottom surface 75b and the first insulating resin layer 71 serve as a barrier layer that makes it difficult for metal to diffuse from the upper surfaces of the land portion 72a and the wiring portion 72b into the first insulating resin layer 71.

[0156] Similarly, in the second layer 80, a second inorganic insulating layer 170 is interposed between a bottom surface 84b of the groove portion 84 and the second insulating resin layer 81, and between a bottom surface 85b of the land recess 85 and the second insulating resin layer 81. Of the second insulating resin layer 81, a portion interposed between the bottom surface 84b and the second insulating resin layer 81 and a portion interposed between the bottom surface 85b and the second insulating resin layer 81 serve as a barrier layer that makes it difficult for metal to diffuse from the upper surfaces of the land portion 82a and the wiring portion 82b to the second insulating resin layer 81.

[0157] Therefore, the above-described multilayer wiring board 12 achieves excellent insulation reliability, and therefore the composite wiring board 10 and packaged device 1 including the multilayer wiring board 12 also achieve excellent insulation reliability.

[0158] The seed adhesion layers 78 and 88 also function as barrier layers that make it difficult for metal to diffuse from the conductor layers 77 and 87 to the first insulating resin layer 71 and the second insulating resin layer 81. When the seed layers 79 and 89 are made of metal materials that have a smaller ionization tendency than the materials of the conductor layers 77 and 87, respectively, they also function as barrier layers that make it difficult for metal to diffuse from the conductor layers 77 and 87 to the first insulating resin layer 71 and the second insulating resin layer 81.

[0159] However, the portions of the seed adhesion layer 78 and the seed layer 79 covering the side surfaces of the land portion 72a and the wiring portion 72b tend to become thinner as the distance from the top surface of the conductor layer 77 increases. Similarly, the portions of the seed adhesion layer 88 and the seed layer 89 covering the side surfaces of the land portion 82a and the wiring portion 82b tend to become thinner as the distance from the top surface of the conductor layer 87 increases. When the thickness of the barrier layer decreases, its ability to prevent metal diffusion decreases.

[0160] The first inorganic insulating layer 160 further includes a portion covering the sidewall of the land recess 75 and a portion covering the sidewall of the groove 74. Therefore, in this structure, metal is less likely to diffuse from the side surfaces of the land 72a and the wiring portion 72b to the first insulating resin layer 71, compared to a structure in which the first inorganic insulating layer 160 does not include portions covering the sidewalls of the land recess 75 and the groove 74.

[0161] The first inorganic insulating layer 160 further includes a portion covering the first surface 71a of the first insulating resin layer 71. Similarly, the second inorganic insulating layer 170 further includes a portion covering the first surface 81a of the second insulating resin layer 81. This makes it difficult for metal to diffuse from one of the adjacent insulating resin layers to the other. In addition, the portion of the first inorganic insulating layer 160 covering the first surface 71a and the portion of the second inorganic insulating layer 170 covering the first surface 81a can make it difficult for the multilayer wiring substrate 12 to warp or bend.

[0162] In the above method, the resist layer 143 is removed after the conductor layer 77 is formed and polished, and the first insulating resin layer 71 is provided instead of the resist layer 143 being a component of the multilayer wiring board 12. Similarly, the resist layer 180 is removed after the conductor layer 87 is formed and polished, and the second insulating resin layer 81 is provided instead of the resist layer 180 being a component of the multilayer wiring board 12.

[0163] In the deposition and polishing processes of the conductor layers 77 and 87, etc., there is a risk of metal diffusing into the resist layers 143 and 180. The above-described multilayer wiring board 12 does not include the resist layers 143 and 180 into which metal may have diffused, and is therefore advantageous in terms of achieving high insulation reliability in this respect as well.

[0164] Next, the effects of using the configuration of multilayer wiring board 12 of the present embodiment and the manufacturing method thereof will be described with reference to a multilayer wiring board 150 shown in FIG. 32 as a comparative example.

[0165] 2 and 3, in this embodiment, the gap between the land portion 72a and the wiring portion 72b is filled with a first insulating resin layer 71. A first inorganic insulating layer 160 is provided on the upper surface and side surface of the land portion 72a and the upper surface and side surface of the wiring portion 72b.

[0166] In this way, the upper surface and side surfaces of the land portion 72a are covered with the first inorganic insulating layer 160, and the upper surface and side surfaces of the wiring portion 72b are covered with the first inorganic insulating layer 160, thereby making it difficult for metal to diffuse from the conductor layer 77 to the first insulating resin layer 71.

[0167] This effect is similarly achieved in the second layer 80. As a result, it is possible to improve the insulation between the multiple wiring portions 72b, and the insulation reliability between the land portion 72a and the wiring portion 72b.

[0168] The comparative example is a multilayer wiring board 150 in which inner conductor layers and interlayer connection conductor layers are fabricated by a semi-additive method, which is a known technique, as shown in Fig. 32. The multilayer wiring board 150 has a similar configuration to the multilayer wiring board 12 of the present embodiment, but differs in the following points. Components in the multilayer wiring board 150 that have the same functions as the multilayer wiring board 12 of the present embodiment will be described with the same reference numerals as those in the multilayer wiring board 12. Fig. 32 is a cross-sectional view showing the wiring portion 72b of the first layer 70, the wiring portion 82b of the second layer 80, and their vicinity of the multilayer wiring board 150.

[0169] 32, the multilayer wiring board 150 of the comparative example differs from the multilayer wiring board 12 of the present embodiment in that it does not have a first inorganic insulating layer 160 and a second inorganic insulating layer 170. Furthermore, the multilayer wiring board 150 of the comparative example differs from the multilayer wiring board 12 of the present embodiment in that the seed adhesion layer 78 and the seed layer 79 of the first wiring layer 72 do not cover the side surfaces of the conductor layer 77. Furthermore, the multilayer wiring board 150 of the comparative example differs from the multilayer wiring board 12 of the present embodiment in that the seed adhesion layer 88 and the seed layer 89 of the second wiring layer 82 do not cover the side surfaces of the conductor layer 87.

[0170] The structure of the multilayer wiring board 150 of the comparative example will be described with reference to the first layer 70. As shown in FIG. 32, in the multilayer wiring board 150 of the comparative example, the side surface of the conductor layer 77 of the first wiring layer 72 contacts the first insulating resin layer 71. That is, the contact area of ​​the conductor layer 77 with the first insulating resin layer 71 is larger than that of the multilayer wiring board 12 of the present embodiment. Therefore, copper of the conductor layer 77 is likely to diffuse into the first insulating resin layer 71. As a result, the insulation reliability of the first insulating resin layer 71 is likely to decrease. In the multilayer wiring board 150 of the comparative example, the second layer 80 is similar to the first layer 70, that is, the insulation reliability of the second insulating resin layer 81 is likely to decrease.

[0171] Furthermore, since the multilayer wiring board 150 of the comparative example does not have the first inorganic insulating layer 160 and the second inorganic insulating layer 170, the insulation reliability between the first insulating resin layer 71 and the second insulating resin layer 81 is also likely to decrease. <Confirmation of action and effect> To confirm the effects of this embodiment, the following evaluations were carried out on the multilayer wiring board 12 of this embodiment and the multilayer wiring board 150 of the comparative example. <Evaluation method> Insulation reliability evaluation The evaluation was performed under a bias of 3.3 V and an environment of 130°C / 85% RH. The wiring rule was L / S=2 / 2 μm. In both the multilayer wiring board 12 and the multilayer wiring board 150, the thicknesses of the insulating resin layers were set to 1 μm, 1.5 μm, 2 μm, and 2.5 μm.

[0172] In the multilayer wiring board 12, the thickness of the first inorganic insulating layer 160 and the second inorganic insulating layer 170 was set to 50 nm. After 192 hours under the above bias and environment, the resistance value was 10 6 The pass condition was a resistance of Ω or more. The number of evaluations for each resin thickness was N=10. <Evaluation Results> In the multilayer wiring board 150 of Comparative Example 1, all of the insulating resin layers had insulation defects at the time of 96 hours, regardless of the thickness of the insulating resin layer. On the other hand, in the multilayer wiring board 12 of the present embodiment, the resistance value after 192 hours was 10 6 As shown above, good insulation reliability was demonstrated.

[0173] The above-described embodiment is merely an example, and it goes without saying that other specific details such as structure can be modified as appropriate.

[0174] In the above example, the first inorganic insulating layer 160 covers the bottom surface 74b and the sidewalls in the groove 74, and covers the bottom surface 75b and the sidewalls in the land recess 75, but is not limited thereto. In another example, the first inorganic insulating layer 160 may cover only the bottom surface 74b in the groove 74, and cover only the bottom surface 75b in the land recess 75. Furthermore, the first inorganic insulating layer 160 covers the first surface 71a of the first insulating resin layer 71, but is not limited thereto. In another example, the first inorganic insulating layer 160 may not be provided on the first surface 71a.

[0175] Similarly, the second inorganic insulating layer 170 has been described as covering the bottom surface 84b and the sidewalls in the groove 84, and as covering the bottom surface 85b and the sidewalls in the land recess 85, but is not limited thereto. In another example, the second inorganic insulating layer 170 may be configured to cover only the bottom surface 84b in the groove 84, and as covering only the bottom surface 85b in the land recess 85. Furthermore, the second inorganic insulating layer 170 has been described as covering the first surface 81a of the second insulating resin layer 81, but is not limited thereto. In another example, the second inorganic insulating layer 170 may not be provided on the first surface 81a.

[0176] Furthermore, in the above example, the first layer 70 has been described as having a configuration including the seed adhesion layer 78 made of titanium that covers the side surface of the conductor layer 77. The seed adhesion layer 78 made of titanium constitutes an inorganic insulating layer. In the case of a configuration including the seed adhesion layer 78 as in the present embodiment, even if the first inorganic insulating layer 160 does not cover the side walls of the groove portion 74 and the side walls of the land recess portion 75, the seed adhesion layer 78 can prevent diffusion of metal from the conductor layer 77 to the first insulating resin layer 71.

[0177] Similarly, in the second layer 80, even if the second inorganic insulating layer 170 does not cover the side walls of the groove portion 84 and the side walls of the land recess 75, the seed adhesion layer 88 can prevent diffusion of metal from the conductor layer 87 to the second insulating resin layer 81.

[0178] In addition, in the above example, the multilayer wiring board 12 includes the first layer 70 and the second layer 80, but the multilayer wiring board 12 may further include one or more layers similar to the first layer 70 and the second layer 80.

[0179] The present invention can be used in a semiconductor device having a wiring board equipped with an interposer or the like interposed between a main board and an IC chip. The invention as originally claimed is set forth below. [1] The laminated structure includes two or more layers, each of which comprises: an insulating resin layer having a first surface and a second surface which is the reverse surface of the first surface, the insulating resin layer being integrally formed in a thickness direction with a first recess opening on the first surface, a groove opening on the first surface, and a second recess opening on the second surface and communicating with at least one of the first recesses; an inorganic insulating layer including a portion covering the bottom surface of the groove and a portion covering the bottom surface of the first recess; A multilayer wiring board including a land portion and a wiring portion that respectively fill the first recess and the groove portion of the insulating resin layer, and a via portion that protrudes from the first surface at the position of the land portion, the via portion including a conductor layer that fills a recess of another insulating resin layer adjacent on the first surface side. [2] 2. The multilayer wiring board according to item 1, wherein the inorganic insulating layer further includes a portion covering a side wall of the first recess and a portion covering a side wall of the groove. [3] 3. The multilayer wiring board according to item 2, wherein the inorganic insulating layer further includes a portion covering the first surface. [4] Item 2. The multilayer wiring board according to item 1, wherein the material of the inorganic insulating layer contains one or more insulators selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride, silicon oxide doped with fluorine, and silicon oxide doped with carbon. [5] 2. The multilayer wiring board according to item 1, wherein each of the two or more layers further includes a first metal-containing layer that covers the peripheral edges of the land portion, the side surfaces of the via portion and the wiring portion, the surface of the wiring portion facing the opening of the groove portion, and the surface of the land portion facing the first surface. [6] 6. The multilayer wiring board according to item 5, wherein each of the two or more layers further includes a second metal-containing layer interposed between the first metal-containing layer and the conductor layer and made of the same material as the conductor layer or made of a metal material having a smaller ionization tendency than the material of the conductor layer. [7] 7. The multilayer wiring board according to item 5 or 6, wherein the first metal-containing layer contains titanium. [8] A composite wiring board comprising a first wiring board and a second wiring board bonded to the first wiring board, the first and second wiring boards being electrically connected to each other via a bonding electrode interposed therebetween, and the second wiring board being a multilayer wiring board as described in any one of items 1 to 7. [9] 9. The composite wiring board according to item 8, wherein the first wiring board is a wiring board for a flip chip ball grid array, and the second wiring board is an interposer.

[10] Item 8 or 9, and the composite wiring board according to item 8 or 9; a functional device mounted on a surface of the second wiring substrate opposite to the surface of the first wiring substrate; A packaged device comprising:

[11] forming two or more layers in a laminate, each of the two or more layers comprising: forming a dummy layer on a base layer having a recess, the dummy layer having a groove and at least one through hole communicating with the recess; forming a conductor layer on the dummy layer so as to fill the recess, the groove, and the through hole; polishing the conductor layer so as to remove a portion located outside the recess, the groove, or the through hole, thereby obtaining a portion of the conductor layer in which the recess is filled, a portion in which the through hole is filled, and a portion in which the groove is filled as a via portion, a land portion, and a wiring portion, respectively; Thereafter, removing the dummy layer; forming an inorganic insulating layer so as to cover at least an upper surface of the land portion and an upper surface of the wiring portion; forming an insulating resin layer that covers the inorganic insulating layer, fills gaps between the land portion and the wiring portion, and has a recess at one or more positions of the land portion; removing a portion of the inorganic insulating layer that is exposed at the position of the recess provided in the insulating resin layer; A method for manufacturing a multilayer wiring board comprising the steps of:

[12] 12. The method for manufacturing a multilayer wiring board according to item 11, wherein the inorganic insulating layer is formed so as to further cover a side surface of the land portion and a side surface of the wiring portion.

[13] Item 13. The method for manufacturing a multilayer wiring board according to item 12, wherein the inorganic insulating layer is formed so as to further cover the underlayer.

[14] Item 12. The method for manufacturing a multilayer wiring board according to item 11, wherein the material of the inorganic insulating layer contains one or more insulators selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride, silicon oxide doped with fluorine, and silicon oxide doped with carbon.

[15] 15. The method for manufacturing a multilayer wiring board according to any one of claims 11 to 14, wherein the formation of each of the two or more layers further includes forming a first metal-containing layer that covers an upper surface of the dummy layer, an inner surface of the recess of the base layer, and an inner surface of the groove and the through hole of the dummy layer before forming the conductor layer.

[16] Item 16. The method for manufacturing a multilayer wiring board according to item 15, wherein the formation of each of the two or more layers further comprises forming a second metal-containing layer on the first metal-containing layer before forming the conductor layer, the second metal-containing layer being made of the same material as the conductor layer or made of a metal material having a smaller ionization tendency than the material of the conductor layer.

[17] Item 17. The method for manufacturing a multilayer wiring board according to item 15 or 16, wherein the first metal-containing layer contains titanium. [Explanation of symbols]

[0180] 1...packaged device, 2...support, 3...peeling layer, 5...seed adhesion layer, 6...seed layer, 10...composite wiring board, 11...FC-BGA board, 12...multilayer wiring board, 13...second underfill layer, 14...second bonding electrode, 20...functional device, 23...laser light, 30...first underfill layer, 40...first bonding electrode, 50...layer, 61...insulating resin layer, 62...via portion, 63... Via hole, 64...inner surface, 70...first layer, 71...first insulating resin layer, 72...first wiring layer, 72a...land portion, 72b...wiring portion, 73...via portion, 74...groove portion, 74a...inner surface, 74b...bottom surface, 74c...opening, 75...land recess, 75a...inner surface, 75c...opening, 77...conductor layer, 78...seed adhesion layer, 79...seed layer, 80...second layer, 81...second insulating resin layer, 82...second 2 wiring layer, 82a...land portion, 82b...wiring portion, 83...via portion, 84...groove portion, 84a...inner surface, 84b...bottom surface, 84c...opening, 85a...inner surface, 87...conductor layer, 88...seed adhesion layer, 89...seed layer, 90...interlayer connection conductor layer, 101...seed adhesion layer, 102...seed layer, 103...conductor layer, 104...solder resist layer, 104a...through hole, 105...surface treatment layer, 1 07...insulating resin layer, 108...conductor layer, 111...core layer, 112...resin layer, 113...conductor layer, 114...resin layer, 115...joint conductor, 134...solder resist layer, 140...resist layer, 141...through hole, 143...resist layer, 144...groove, 146...resist layer, 147...through hole, 150...comparative multilayer wiring board, 160...first inorganic insulating layer, 170...second inorganic insulating layer.

Claims

1. The laminated structure includes two or more layers, each of which comprises: an insulating resin layer having a first surface and a second surface which is the reverse side of the first surface, the insulating resin layer being integrally formed in a thickness direction, the insulating resin layer being provided with a first recess opening on the first surface, a groove opening on the first surface, and a second recess opening on the second surface and communicating with one or more of the first recesses; an inorganic insulating layer including a portion covering a bottom surface of the groove and a portion covering a bottom surface of the first recess; a land portion and a wiring portion in which the first recess and the groove of the insulating resin layer are filled, respectively, and a via portion protruding from the first surface at the position of the land portion, the via portion including a conductor layer in which a recess of another insulating resin layer adjacent to the first surface is filled, A multilayer wiring board, wherein each of the two or more layers further includes a first metal-containing layer that covers the side surfaces of the land portion, the via portion, and the wiring portion, the surface of the wiring portion facing the opening of the groove portion, and the peripheral portion of the surface of the land portion facing the first surface.

2. The multilayer wiring board according to claim 1 , wherein the inorganic insulating layer further includes a portion covering a side wall of the first recess and a portion covering a side wall of the groove.

3. The multilayer wiring board according to claim 2 , wherein the inorganic insulating layer further includes a portion covering the first surface.

4. 2. The multilayer wiring board according to claim 1, wherein the material of the inorganic insulating layer contains one or more insulators selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride, silicon oxide doped with fluorine, and silicon oxide doped with carbon.

5. 5. The multilayer wiring board according to claim 1, wherein each of the two or more layers further includes a second metal-containing layer interposed between the first metal-containing layer and the conductor layer and made of the same material as the conductor layer or made of a metal material having a smaller ionization tendency than the material of the conductor layer.

6. 6. The multilayer wiring board according to claim 1, wherein the first metal-containing layer contains titanium.

7. A composite wiring board comprising a first wiring board and a second wiring board joined to the first wiring board, the first and second wiring boards being electrically connected to each other via a joining electrode interposed between them, and the second wiring board being a multilayer wiring board as defined in any one of claims 1 to 6.

8. 8. The composite wiring board according to claim 7, wherein the first wiring board is a wiring board for a flip chip ball grid array, and the second wiring board is an interposer.

9. The composite wiring board according to claim 7 or 8, a functional device mounted on a surface of the second wiring substrate opposite to the surface of the first wiring substrate; A packaged device comprising:

10. forming two or more layers in a laminate, the forming of each of the two or more layers comprising: forming a dummy layer on a base layer having a recessed portion, the dummy layer having a groove and at least one through hole communicating with the recessed portion; forming a conductor layer on the dummy layer so as to fill the recess, the groove, and the through hole; polishing the conductor layer so as to remove a portion located outside the recess, the groove, or the through hole, thereby obtaining a portion of the conductor layer in which the recess is filled, a portion in which the through hole is filled, and a portion in which the groove is filled as a via portion, a land portion, and a wiring portion, respectively; Thereafter, removing the dummy layer; forming an inorganic insulating layer so as to cover at least an upper surface of the land portion and an upper surface of the wiring portion; forming an insulating resin layer that covers the inorganic insulating layer, fills gaps between the land portion and the wiring portion, and has recesses at one or more positions of the land portion; removing a portion of the inorganic insulating layer that is exposed at the position of the recess provided in the insulating resin layer; Including, The method for manufacturing a multilayer wiring board, wherein forming each of the two or more layers further includes forming a first metal-containing layer covering an upper surface of the dummy layer, an inner surface of the recess of the base layer, and an inner surface of the groove and the through hole of the dummy layer before forming the conductor layer.

11. The method for manufacturing a multilayer wiring board according to claim 10 , wherein the inorganic insulating layer is formed so as to further cover a side surface of the land portion and a side surface of the wiring portion.

12. The method for manufacturing a multilayer wiring board according to claim 11, wherein the inorganic insulating layer is formed so as to further cover the base layer.

13. 11. The method for manufacturing a multilayer wiring board according to claim 10, wherein the material of the inorganic insulating layer contains one or more insulators selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride, silicon oxide doped with fluorine, and silicon oxide doped with carbon.

14. 14. The method for manufacturing a multilayer wiring board according to claim 10, wherein the formation of each of the two or more layers further includes forming a second metal-containing layer on the first metal-containing layer before forming the conductor layer, the second metal-containing layer being made of the same material as the conductor layer or made of a metal material having a smaller ionization tendency than the material of the conductor layer.

15. 15. The method for manufacturing a multilayer wiring board according to claim 10, wherein the first metal-containing layer contains titanium.

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