Multilayer wiring board, composite wiring board, packaged device, and method for manufacturing multilayer wiring board

Abstract

To provide a multilayer wiring board having high insulation reliability, a composite wiring board, a packaged device, and a method for manufacturing a multilayer wiring board.SOLUTION: A first layer 70 and a second layer 80 of a multilayer wiring board 12 include: insulating resin layers 71 and 81 which are provided with recesses 75 and 85 for lands opened in first surfaces 71a and 81a, groove parts 74 and 84, and recesses 76 and 86 for vias that are opened in second surfaces 71b and 81b, and communicate with the one or more recesses 75 and 85 for the lands; first inorganic resin layers 160 and 170 including first parts 163 and 173 covering the first surfaces 71a and 81a, second parts 164 and 174 covering the openings of the groove parts 74 and 84, and third parts 165 and 175 covering peripheral edge parts on the side of the first surfaces 71a and 81a of the land parts 72a and 82a; and second inorganic insulating layers 200 and 210 including fourth parts 201 and 211 covering bottom surfaces 74b and 84b of the groove parts 74 and 84, and a sixth part 213 covering the bottom surfaces 75b and 85b of the recesses 75 and 85 for the lands.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present invention relates to a multilayer wiring board, a composite wiring board, a packaged device, and a method for manufacturing a multilayer wiring board. [Background technology]

[0002] In recent years, as semiconductor devices become faster and more highly integrated, there is a demand for narrower pitches of bonding terminals used for bonding to semiconductor chips and finer wiring within the substrate for wiring substrates for flip chip ball grid arrays (FC-BGA substrates) on which semiconductor chips are mounted. On the other hand, bonding between FC-BGA substrates and motherboards is required to be performed using bonding terminals arranged at almost the same pitch as before. In response to these demands, a technology has been adopted in which a multilayer wiring substrate including fine wiring, also called an interposer, is provided between the FC-BGA substrate and the semiconductor chip.

[0003] One of these is silicon interposer technology, which manufactures interposers by forming a multilayer wiring structure, each layer of which contains fine wiring, on a silicon wafer using semiconductor circuit manufacturing technology.

[0004] Also, a method has been developed in which the above multi-layer wiring structure is directly fabricated on an FC-BGA substrate, rather than being formed on a silicon wafer. This method involves forming the above multi-layer wiring structure by using chemical mechanical polishing (CMP) or the like in the manufacture of an FC-BGA substrate, the core layer of which is made of, for example, a glass epoxy substrate. This method is disclosed in Patent Document 1.

[0005] Furthermore, there is also a method in which an interposer is formed on a support such as a glass substrate, the interposer is bonded to an FC-BGA substrate, and then the support is peeled off from the interposer, thereby providing the above-mentioned multilayer wiring structure on the FC-BGA substrate. This method is disclosed in Patent Document 2. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] JP 2014-225671 A [Patent Document 2] International Publication No. 2018 / 047861 Summary of the Invention [Problem to be solved by the invention]

[0007] An object of the present invention is to provide a multilayer wiring board, a composite wiring board, a packaged device, and a method for manufacturing the multilayer wiring board, which have high insulation reliability. [Means for solving the problem]

[0008] According to one aspect of the present invention, there is provided a multilayer wiring board comprising: an insulating resin layer having two or more laminated layers, each of the two or more layers having a first surface and a second surface which is an opposite surface of the first surface, the insulating resin layer being provided with a first recess opening in the first surface, a groove opening in the first surface, and a second recess opening in the second surface and communicating with one or more of the first recesses, the insulating resin layer being integrally formed in a thickness direction; a land portion and a wiring portion respectively filling the first recess and the groove portion of the insulating resin layer, and a via portion protruding from the first surface at a position of the land portion, the via portion being a conductor layer filling a recess of another insulating resin layer adjacent on the first surface side; a first inorganic insulating layer including a first portion covering the first surface, a second portion closing the opening of the groove portion, and a third portion covering a peripheral portion of a surface of the land portion on the first surface side; and a second inorganic insulating layer including a portion covering a bottom surface of the groove portion and a portion covering a bottom surface of the first recess.

[0009] Here, the insulating resin layer being "integrally formed in the thickness direction" means that there is no interface intersecting the thickness direction inside the insulating resin layer, that is, the insulating resin layer has a single-layer structure. Even if multiple insulating layers stacked on top of each other are made of the same material, their interfaces can be confirmed by observing the cross section with an electron microscope such as a scanning electron microscope.

[0010] According to another aspect of the present invention, there is provided a multilayer wiring board relating to the above aspect, wherein the second inorganic insulating layer further includes a portion covering the side wall of the first recess, a portion covering the side wall of the groove portion, and a portion interposed between the first surface and the first portion covering it.

[0011] According to yet another aspect of the present invention, there is provided a multilayer wiring board according to any of the above aspects, wherein the material of each of the first inorganic insulating layer and the second inorganic insulating layer contains one or more insulators selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride, silicon oxide doped with fluorine, and silicon oxide doped with carbon.

[0012] According to yet another aspect of the present invention, there is provided the multilayer wiring board according to any one of the above aspects, wherein the insulating resin layer is made of a non-photosensitive resin.

[0013] According to yet another aspect of the present invention, there is provided a multilayer wiring board according to any of the above aspects, wherein each of the two or more layers further includes a first metal-containing layer covering the peripheral edges of the land portion, the side surfaces of the via portion and the wiring portion, the surface of the wiring portion facing the opening of the groove portion, and the surface of the land portion facing the first surface.

[0014] According to yet another aspect of the present invention, there is provided a multilayer wiring board according to the above aspect, wherein each of the two or more layers further includes a second metal-containing layer interposed between the first metal-containing layer and the conductor layer and made of the same material as the conductor layer or made of a metal material having a smaller ionization tendency than the material of the conductor layer.

[0015] According to yet another aspect of the present invention, there is provided a multilayer wiring board according to any one of the above aspects, wherein the first metal-containing layer contains titanium.

[0016] According to yet another aspect of the present invention, there is provided a composite wiring board comprising a first wiring board and a second wiring board joined to the first wiring board, the first and second wiring boards being electrically connected to each other via a joining electrode interposed therebetween, and the second wiring board being a multilayer wiring board according to any of the aspects described above.

[0017] According to yet another aspect of the present invention, there is provided a composite wiring board according to the above aspect, wherein the first wiring board is a wiring board for a flip chip ball grid array, and the second wiring board is an interposer.

[0018] According to yet another aspect of the present invention, there is provided a packaged device comprising a composite wiring board according to any of the above aspects and a functional device mounted on a surface of the second wiring board opposite the first wiring board.

[0019] Here, the term "functional device" refers to a device that operates when at least one of power and an electric signal is supplied, a device that outputs at least one of power and an electric signal when stimulated from the outside, or a device that operates when at least one of power and an electric signal is supplied and outputs at least one of power and an electric signal when stimulated from the outside. The functional device is in the form of a chip, such as a semiconductor chip or a chip in which circuits and elements are formed on a substrate made of a material other than a semiconductor, such as a glass substrate. The functional device may include, for example, one or more of a large scale integrated circuit (LSI), a memory, an imaging element, a light-emitting element, and a MEMS (Micro Electro Mechanical Systems). The MEMS may be, for example, one or more of a pressure sensor, an acceleration sensor, a gyro sensor, a tilt sensor, a microphone, and an acoustic sensor. According to one example, the functional device is a semiconductor chip including an LSI.

[0020] According to yet another aspect of the present invention, the method includes forming two or more laminated layers, and the formation of each of the two or more layers includes forming a first inorganic insulating layer having a first through hole on an insulating layer including an insulating resin layer as an outermost layer, removing a portion of the insulating layer exposed in the first through hole to form a recess in the insulating layer, forming a dummy layer on the first inorganic insulating layer, the dummy layer having a groove and a second through hole, at least one of which is connected to the recess via the first through hole, forming a conductor layer on the dummy layer so as to fill the recess, the groove, the first through hole, and the second through hole, and forming a conductor layer on the dummy layer so as to fill the recess, the groove, the first through hole, and the second through hole. The present invention provides a method for manufacturing a multilayer wiring board, the method including: polishing the conductor layer so as to remove a through hole or a portion located outside the second through hole, thereby obtaining a portion of the conductor layer in which the recess is filled, a portion in which the first through hole and the second through hole are filled, and a portion in which the groove is filled as a via portion, a land portion, and a wiring portion, respectively; then removing the dummy layer; forming a second inorganic insulating layer so as to cover at least an upper surface of the land portion and an upper surface of the wiring portion; and forming an insulating resin layer that covers the second inorganic insulating layer and fills the gap between the land portion and the wiring portion.

[0021] According to yet another aspect of the present invention, there is provided a method for manufacturing a multilayer wiring board according to the above aspect, wherein the material of the first inorganic insulating layer and the second inorganic insulating layer contains one or more insulators selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride, silicon oxide doped with fluorine, and silicon oxide doped with carbon.

[0022] According to yet another aspect of the present invention, there is provided the method for manufacturing a multilayer wiring board according to any one of the above aspects, wherein the insulating resin layer covering the second inorganic insulating layer is made of a non-photosensitive resin.

[0023] According to yet another aspect of the present invention, there is provided a method for manufacturing a multilayer wiring board according to any of the above aspects, wherein forming each of the two or more layers further includes forming a first metal-containing layer covering upper surfaces of the dummy layer and the first inorganic insulating layer, and inner surfaces of the recess, the groove, the first through hole, and the second through hole before forming the conductor layer.

[0024] According to yet another aspect of the present invention, there is provided a method for manufacturing a multilayer wiring board according to the above aspect, wherein forming each of the two or more layers further includes forming a second metal-containing layer on the first metal-containing layer before forming the conductor layer, the second metal-containing layer being made of the same material as the conductor layer or made of a metal material having a smaller ionization tendency than the material of the conductor layer.

[0025] According to yet another aspect of the present invention, there is provided the method for producing a multilayer wiring board according to any one of the above aspects, wherein the first metal-containing layer contains titanium. [Brief description of the drawings]

[0026] [Figure 1] 1 is a schematic cross-sectional view of a packaged device according to an embodiment of the present invention; [Diagram 2] 2 is a cross-sectional view showing a schematic view of a portion of a multilayer wiring substrate used in the packaged device shown in FIG. 1. [Diagram 3] 3 is an enlarged schematic cross-sectional view of a portion of the multilayer wiring board shown in FIG. 2. [Figure 4] 1 is a cross-sectional view illustrating a process of a method for manufacturing a multilayer wiring board according to an embodiment of the present invention. [Diagram 5] 6 is a cross-sectional view illustrating another step in the method for manufacturing a multilayer wiring board according to an embodiment of the present invention. [Figure 6] 11 is a cross-sectional view illustrating a process for producing a multilayer wiring board according to an embodiment of the present invention. FIG. [Figure 7] 11 is a cross-sectional view illustrating a process for producing a multilayer wiring board according to an embodiment of the present invention. FIG. [Figure 8]11 is a cross-sectional view illustrating a process for producing a multilayer wiring board according to an embodiment of the present invention. FIG. [Figure 9] 11 is a cross-sectional view illustrating a process for producing a multilayer wiring board according to an embodiment of the present invention. FIG. [Figure 10] 11 is a cross-sectional view illustrating a process for producing a multilayer wiring board according to an embodiment of the present invention. FIG. [Figure 11] 11 is a cross-sectional view illustrating a process for producing a multilayer wiring board according to an embodiment of the present invention. FIG. [Figure 12] 11 is a cross-sectional view illustrating a process for producing a multilayer wiring board according to an embodiment of the present invention. FIG. [Figure 13] 11 is a cross-sectional view illustrating a process for producing a multilayer wiring board according to an embodiment of the present invention. FIG. [Figure 14] 11 is a cross-sectional view illustrating a process for producing a multilayer wiring board according to an embodiment of the present invention. FIG. [Figure 15] 11 is a cross-sectional view illustrating a process for producing a multilayer wiring board according to an embodiment of the present invention. FIG. [Figure 16] 11 is a cross-sectional view illustrating a process for producing a multilayer wiring board according to an embodiment of the present invention. FIG. [Figure 17] 11 is a cross-sectional view illustrating a process for producing a multilayer wiring board according to an embodiment of the present invention. FIG. [Figure 18] 11 is a cross-sectional view illustrating a process for producing a multilayer wiring board according to an embodiment of the present invention. FIG. [Figure 19] 11 is a cross-sectional view illustrating a process for producing a multilayer wiring board according to an embodiment of the present invention. FIG. [Figure 20] 11 is a cross-sectional view illustrating a process for producing a multilayer wiring board according to an embodiment of the present invention. FIG. [Figure 21] 11 is a cross-sectional view illustrating a process for producing a multilayer wiring board according to an embodiment of the present invention. FIG. [Figure 22]11 is a cross-sectional view illustrating a process for producing a multilayer wiring board according to an embodiment of the present invention. FIG. [Diagram 23] 11 is a cross-sectional view illustrating a process for producing a multilayer wiring board according to an embodiment of the present invention. FIG. [Figure 24] 11 is a cross-sectional view illustrating a process for producing a multilayer wiring board according to an embodiment of the present invention. FIG. [Diagram 25] 11 is a cross-sectional view illustrating a process for producing a multilayer wiring board according to an embodiment of the present invention. FIG. [Figure 26] 11 is a cross-sectional view illustrating a process for producing a multilayer wiring board according to an embodiment of the present invention. FIG. [Figure 27] 11 is a cross-sectional view illustrating a process for producing a multilayer wiring board according to an embodiment of the present invention. FIG. [Figure 28] 11 is a cross-sectional view illustrating a process for producing a multilayer wiring board according to an embodiment of the present invention. FIG. [Figure 29] 1A-1D are cross-sectional views illustrating schematic steps of a method for manufacturing a packaged device according to an embodiment of the present invention. [Diagram 30] 5A-5C are cross-sectional views each showing a schematic diagram of another process for manufacturing a packaged device according to an embodiment of the present invention. [Diagram 31] 5A-5C are cross-sectional views illustrating schematic steps of a method for manufacturing a packaged device in accordance with an embodiment of the present invention. [Diagram 32] 5A-5C are cross-sectional views illustrating schematic steps of a method for manufacturing a packaged device in accordance with an embodiment of the present invention. [Diagram 33] FIG. 11 is a cross-sectional view illustrating a portion of a multilayer wiring board according to a comparative example. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0027] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. The embodiment described below is a more specific embodiment of any of the above aspects. The embodiment described below shows an example of the technical idea of ​​the present invention, and does not limit the technical idea of ​​the present invention to the material, shape, structure, arrangement, etc. of the components described below. Various modifications can be made to the technical idea of ​​the present invention within the technical scope defined by the claims described in the claims.

[0028] In the drawings referred to in the following description, components having the same or similar functions are given the same reference numerals. It should be noted that the drawings are schematic, and the relationship between the dimension in the thickness direction and the dimension in the direction perpendicular to the thickness direction, i.e., the in-plane direction, and the relationship between the dimensions in the thickness direction of multiple layers, etc., may differ from the actual ones. Therefore, the specific dimensions should be determined with reference to the following description. It should also be noted that the dimensional relationship between two or more components may differ between multiple drawings. It should also be noted that the same structure is drawn upside down in some drawings compared to other drawings.

[0029] In this disclosure, the terms "upper surface" and "lower surface" refer to surfaces of a plate-like member or a layer contained therein that are perpendicular to the thickness direction, and refer to the surfaces facing upward and downward in the drawings, respectively. Also, the term "side surface" refers to a surface that is parallel to or inclined with respect to the thickness direction.

[0030] 1 is a cross-sectional view showing a schematic diagram of a packaged device 1 according to an embodiment of the present invention. As shown in FIG. 1, the packaged device 1 includes a composite wiring substrate 10, a functional device 20, a first underfill layer 30, and a first bonding electrode 40.

[0031] The functional device 20 is, for example, a semiconductor chip, or a chip in which circuits and elements are formed on a substrate made of a material other than a semiconductor, such as a glass substrate. Here, as an example, the functional device 20 is a semiconductor chip. That is, here, the packaged device 1 is a semiconductor package.

[0032] The packaged device 1 includes a plurality of functional devices 20. The packaged device 1 may include only one functional device as the functional device 20.

[0033] The functional devices 20 are bonded to the composite wiring board 10 via first bonding electrodes 40. Here, the multiple functional devices 20 are bonded to the composite wiring board 10 by flip chip bonding. One or more of the functional devices 20 may be bonded to the composite wiring board 10 by other bonding methods such as wire bonding.

[0034] The first bonding electrodes 40 bond the multiple functional devices 20 to the composite wiring board 10. A plurality of first bonding electrodes 40 are provided for each functional device 20. The multiple first bonding electrodes 40 that bond one functional device 20 to the composite wiring board 10 are arranged at a narrow pitch between the functional device 20 and the composite wiring board 10. The narrow pitch here means a pitch narrower than the pitch of multiple second bonding electrodes 14 of the composite wiring board 10, which will be described later.

[0035] The first bonding electrode 40 is made of, for example, solder. When the functional device 20 is bonded to the composite wiring board 10 by wire bonding, for example, a gold wire can be used to electrically connect the functional device 20 and the composite wiring board.

[0036] The first underfill layer 30 fixes the multiple functional devices 20 to the composite wiring board 10. When the packaged device 1 is configured to include only one functional device 20, the first underfill layer 30 fixes the single functional device 20 to the composite wiring board 10. In this embodiment, the first underfill layer 30 is provided between the functional device 20 and the composite wiring board 10. The first underfill layer 30 includes a portion interposed between the functional device 20 and the composite wiring board 10 and a portion at least partially covering the side surface of the functional device 20.

[0037] Composite wiring board 10 includes a first wiring board and a second wiring board joined thereto. Here, composite wiring board 10 includes FC-BGA substrate 11, multilayer wiring board 12, second underfill layer 13, and second bonding electrode 14.

[0038] The FC-BGA substrate 11 is an example of a first wiring substrate. The FC-BGA substrate 11 is joined to, for example, a motherboard (not shown).

[0039] The FC-BGA substrate 11 includes a core layer 111 , an insulating layer 112 , a conductor layer 113 , an insulating layer 114 , and a joining conductor 115 .

[0040] The core layer 111 is an insulating layer. The core layer 111 is, for example, a fiber-reinforced substrate in which a woven or nonwoven fabric is impregnated with a thermosetting insulating resin. For example, glass fiber, carbon fiber, or aramid fiber can be used as the woven or nonwoven fabric. For example, epoxy resin can be used as the insulating resin.

[0041] Through holes are formed in the core layer 111. Part of the conductor layer 113 covers the side walls of the through holes. Here, part of the conductor layer 113 covers the side walls of the through holes provided in the core layer 111 so as to generate through holes whose side walls are made of a conductor. These through holes whose side walls are made of a conductor may be filled with an insulator.

[0042] The remainder of the conductor layers 113 and the insulating layers 112 form multi-layer wiring structures on both major surfaces of the core layer 111. Each multi-layer wiring structure includes conductor layers 113 and insulating layers 112 stacked alternately.

[0043] The insulating layer 112 is, for example, an insulating resin layer, and has a through hole.

[0044] The conductor layer 113 is made of a metal such as copper or an alloy, and may have a single-layer structure or a multi-layer structure.

[0045] The conductor layer 113 includes a wiring portion and a land portion. The conductor layer 113 facing the core layer 111 with the insulating layer 112 sandwiched therebetween further includes a via portion covering the side wall of a through hole provided in the insulating layer 112.

[0046] An insulating layer 114 is provided on the multilayer wiring structure. The insulating layer 114 is, for example, an insulating resin layer such as a solder resist. The insulating layer 114 is provided with a through hole communicating with the conductor layer 113 located on the outermost surface of the multilayer wiring structure.

[0047] The bonding conductor 115 is formed so as to be capable of electrically bonding the packaged device 1 to another component such as a substrate. The bonding conductor 115 is, for example, a metal bump provided on a portion of the conductor layer 113 that is exposed at the position of the through hole of the insulating layer 114. The bonding conductor is also called a bonding terminal. The bonding conductor 115 is, for example, made of solder.

[0048] The multilayer wiring board 12 is an example of a second wiring board. The multilayer wiring board 12 is bonded to the functional device 20 via a first bonding electrode 40. The multilayer wiring board 12 is bonded to the FC-BGA board 11 via a second bonding electrode 14. That is, in this embodiment, the multilayer wiring board 12 is an interposer that mediates the bonding between the functional device 20 and the FC-BGA board 11. The thickness of the multilayer wiring board 12 is, for example, in the range of 10 μm to 300 μm. The multilayer wiring board 12 will be described in detail later.

[0049] The second bonding electrodes 14 are arranged between the multilayer wiring substrate 12 and the functional device 20. The pitch of the second bonding electrodes 14 is wider than the pitch of the first bonding electrodes 40 and narrower than the pitch of the bonding conductors 115 located on the lower surface of the FC-BGA substrate 11. The second bonding electrodes 14 are made of, for example, solder.

[0050] The second underfill layer 13 includes a portion interposed between the FC-BGA substrate 11 and the multilayer wiring substrate 12. The underfill layer is also called a sealing resin layer. The second underfill layer 13 fixes the multilayer wiring substrate 12 to the FC-BGA substrate 11.

[0051] The multilayer wiring board 12 will be described in more detail with reference to FIGS. Fig. 2 is a cross-sectional view that diagrammatically illustrates a portion of the multilayer wiring board 12. Fig. 3 is a cross-sectional view that diagrammatically illustrates an enlarged portion of the multilayer wiring board 12 shown in Fig. 2. Fig. 3 specifically illustrates a portion of a first layer 70, a portion of a second layer 80, and their vicinities, which will be described later.

[0052] As shown in Figures 2 and 3, the multilayer wiring board 12 includes two or more stacked layers 50, an insulating resin layer 61, a seed adhesion layer 101, a seed layer 102, a conductor layer 103, a solder resist layer 104, a surface treatment layer 105, an insulating resin layer 107, a conductor layer 108, and an inorganic insulating layer 109.

[0053] Here, two layers 50 are provided. The number of layers 50 may be three or more. Hereinafter, the two layers 50 will be referred to as a first layer 70 and a second layer 80 in the description.

[0054] The first layer 70 is provided on the insulating resin layer 61. The first layer 70 includes an insulating resin layer 71, a first inorganic insulating layer 160, a wiring layer 72, and a second inorganic insulating layer 200.

[0055] The insulating resin layer 71 has insulating properties. The insulating resin layer 71 is provided on the insulating resin layer 61 via the first inorganic insulating layer 160 and the second inorganic insulating layer 200. The insulating resin layer 71 has a first surface 71a and a second surface 71b which is the reverse surface of the first surface 71a. In this embodiment, the first surface 71a is the surface on the insulating resin layer 61 side. The second surface 71b is the surface on the second layer 80 side. In addition, the insulating resin layer 71 is formed with a groove portion 74, a land recess 75 which is a first recess, and a via recess 76 which is a second recess.

[0056] The groove portion 74 is formed on the first surface 71a of the insulating resin layer 71 and opens at the first surface 71a. The groove portion 74 is filled with a wiring portion 72b described later. A plurality of groove portions 74 are provided. The groove portion 74 has a depth that does not reach the second surface 71b of the insulating resin layer 71.

[0057] The groove 74 is formed in a shape that gradually narrows toward the first surface 71a. The groove 74 has a side surface 74a that is a side wall, a bottom surface 74b, and an opening 74c.

[0058] In this embodiment, the groove 74 is formed in a trapezoidal shape when cut along a cut surface perpendicular to the extension direction of the groove 74. That is, the cross section of the groove 74 in the cut surface is inverted tapered. The cross section of the groove 74 in the cut surface may be rectangular.

[0059] The land recess 75 is formed on the first surface 71a of the insulating resin layer 71 and opens at the first surface 71a. The land recess 75 is filled with a land portion 72a described later. A plurality of land recesses 75 are formed. Each of the plurality of land recesses 75 communicates with one of the groove portions 74. In addition, one or more of the land recesses 75 communicates with a via recess 76 included in the insulating resin layer 71 in which the land recess 75 is provided. Among the land recesses 75, the bottom surface 75b of one that communicates with the via recess 76 at the position of its bottom surface 75b is configured in an annular shape.

[0060] The land recess 75 has a side wall 75a, a bottom surface 75b, and an opening 75c. The land recess 75 is formed in a shape in which the dimension in a direction perpendicular to the thickness direction gradually decreases from the second surface 71b toward the first surface 71a. That is, the land recess 75 has a cross section perpendicular to the thickness direction that is inversely tapered. The land recess 75 is formed in, for example, a truncated cone shape. The land recess 75 may have a cross section parallel to the thickness direction that is rectangular.

[0061] In addition, one or more of the land recesses 75 communicate with a recess in the insulating resin layer adjacent to the first layer 70. The recess in the insulating resin layer adjacent to the first layer 70 is a via hole 63 (described later) in the insulating resin layer 61. The edge of the land recess 75 that communicates with the via hole 63 and opens on the first surface 71a surrounds the edge of the via hole 63.

[0062] The via recess 76 is formed on the second surface 71b of the insulating resin layer 71 and opens at the second surface 71b. The via recess 76 is a recess for forming the via portion 73. A plurality of via recesses 76 are formed. Each of the via recesses 76 communicates with one of the land recesses 75. That is, the via recess 76 communicates with one or more of the land recesses 75.

[0063] The via recess 76 has a side surface 76a which is a side wall, and an opening 76c. The via recess 76 is formed in a shape in which the dimension in a direction perpendicular to the thickness direction gradually decreases from the second surface 71b toward the first surface 71a. That is, the via recess 76 has a cross section perpendicular to the thickness direction in an inverse tapered shape. The via recess 76 is formed in, for example, a truncated cone shape. The via recess 76 may have a cross section parallel to the thickness direction in a rectangular shape.

[0064] The edge of the side surface 76a on the first surface 71a side is surrounded by the edge of the land recess 75 on the second surface 71b side. When observed in the thickness direction of the insulating resin layer 71, the position of the center of each via recess 76 approximately coincides with the position of the center of the land recess 75 connected to that via recess 76.

[0065] The insulating resin layer 71 thus configured is integrally formed in the thickness direction.

[0066] The first inorganic insulating layer 160 includes a first portion 163 covering the first surface 71a, a second portion 164 closing the opening 74c of the groove portion 74, and a third portion 165 covering a peripheral portion 72c on the first surface 71a side of a land portion 72a described later of the wiring layer 72. The first inorganic insulating layer 160 has a through hole 162 at the position of a via hole 63 provided in the insulating resin layer 61.

[0067] The wiring layer 72 fills the groove portion 74, the land recess portion 75, and the recess portion of the insulating resin layer adjacent to the first layer 70. Here, in this embodiment, the recess portion of the insulating resin layer adjacent to the first layer 70 is the via hole 63 of the insulating resin layer 61.

[0068] The wiring layer 72 includes a seed adhesion layer 78 , a seed layer 79 , and a conductor layer 77 .

[0069] The conductor layer 77 fills the grooves 74 and the land recesses 75 of the insulating resin layer 71, and the via holes 63 of the insulating resin layer 61. The portion of the conductor layer 77 into which the grooves 74 are filled constitutes the wiring portion 72b. The portion of the conductor layer 77 into which the land recesses 75 are filled constitutes the land portion 72a. The portion of the conductor layer 77 into which the via holes 63 are filled constitutes the via portion 62. The via portion 62 protrudes from the first surface 71a at the position of the land portion 72a. The conductor layer 77 is made of, for example, copper.

[0070] The seed adhesion layer 78 is a first metal-containing layer. The seed adhesion layer 78 is a layer containing titanium. The seed adhesion layer 78 covers the side and bottom surfaces of the wiring portion 72b and the via portion 62. The seed adhesion layer 78 also covers the peripheral portion of the side and bottom surface of the land portion 72a.

[0071] The seed layer 79 is a second metal-containing layer. The seed layer 79 is a metal layer interposed between the seed adhesion layer 78 and the conductor layer 77. The seed layer 79 is made of the same material as the conductor layer 77 or a metal material having a smaller ionization tendency than the material of the conductor layer 77. The seed layer 79 is made of, for example, copper.

[0072] The second inorganic insulating layer 200 includes a fourth portion 201 , a fifth portion 202 , a sixth portion 203 , a seventh portion 204 , and an eighth portion 205 .

[0073] The fourth portion 201 is a portion covering the bottom surface 74b of the groove portion 74. The fifth portion 202 is a portion covering the side surface 74a of the groove portion 74. The sixth portion 203 is a portion covering the bottom surface 75b of the land recess 75. The sixth portion 203 formed in the land recess 75 communicating with the via recess 76 has a through hole 203a formed at the position of the via recess 76.

[0074] The seventh portion 204 is a portion covering the side surface 75a of the land recess 75. The eighth portion 205 is a portion interposed between the first surface 71a and the first portion 163 covering the first surface 71a of the first inorganic insulating layer 160.

[0075] 2, the second layer 80 is provided on the first layer 70. The second layer 80 has a similar structure to the first layer 70.

[0076] Specifically, the second layer 80 includes an insulating resin layer 81, a first inorganic insulating layer 170, a wiring layer 82, and a second inorganic insulating layer 210. The insulating resin layer 81, the first inorganic insulating layer 170, the wiring layer 82, and the second inorganic insulating layer 210 correspond to the insulating resin layer 71, the first inorganic insulating layer 160, the wiring layer 72, and the second inorganic insulating layer 200, respectively.

[0077] The insulating resin layer 81 has a first surface 81a and a second surface 81b which is the reverse side of the first surface. A groove 84, a land recess 85 which is the first recess, and a via recess 86 which is the second recess are formed in the insulating resin layer 81. The first surface 81a, the second surface 81b which is the reverse side, the groove 84, the land recess 85 which is the first recess, and the via recess 86 which is the second recess of the insulating resin layer 81 correspond to the first surface 71a, the second surface 71b, the groove 74, the land recess 75, and the via recess 76 of the insulating resin layer 71, respectively.

[0078] The side surface 84a, bottom surface 84b, and opening 84c of the groove 84 respectively correspond to the side surface 74a, bottom surface 74b, and opening 74c of the groove 74. The side surface 85a, bottom surface 85b, and opening 85c of the land recess 85 respectively correspond to the side surface 75a, bottom surface 75b, and opening 75c of the land recess 75. The side surface 86a and opening 86c of the via recess 86 respectively correspond to the side surface 76a and opening 76c of the via recess 76.

[0079] The first inorganic insulating layer 170 includes a first portion 173 covering the first surface 81a, a second portion 174 closing the opening 84c of the groove portion 84, and a third portion 175 covering a peripheral portion 82c on the first surface 81a side of a land portion 82a described later of the wiring layer 82. The first inorganic insulating layer 170 has a through hole 172 at the position of the opening 85c of the land recess 85.

[0080] The wiring layer 82 includes a seed adhesion layer 88, a seed layer 89, and a conductor layer 87. The seed adhesion layer 88, the seed layer 89, and the conductor layer 87 correspond to the seed adhesion layer 78, the seed layer 79, and the conductor layer 77, respectively.

[0081] The conductor layer 87 fills the grooves 84 and the land recesses 85 of the insulating resin layer 81 and the via recesses 76 of the insulating resin layer 71. The portion of the conductor layer 87 into which the grooves 84 are filled constitutes the wiring portion 82b. The portion of the conductor layer 87 into which the land recesses 85 are filled constitutes the land portion 82a. The portion of the conductor layer 87 into which the via recesses 76 are filled constitutes the via portion 73. The wiring portion 82b, the land portion 82a, and the via portion 73 correspond to the wiring portion 72b, the land portion 72a, and the via portion 62, respectively.

[0082] The second inorganic insulating layer 210 includes a fourth portion 211, a fifth portion 212, a sixth portion 213, a seventh portion 214, and an eighth portion 215. The fourth portion 211 is a portion that covers the bottom surface 84b of the groove portion 84. The fifth portion 212 is a portion that covers the side surface 84a of the groove portion 84.

[0083] The sixth portion 213 is a portion that covers the bottom surface 85b of the land recess 85. The sixth portion 213 formed in the land recess 85 that is in communication with the via recess 86 has a through hole 213a formed at the position of the via recess 86.

[0084] The seventh portion 214 is a portion that covers the side surface 85a of the land recess 85. The eighth portion 215 is a portion that is interposed between the first surface 81a and the first portion 173 that covers the first surface 81a of the first inorganic insulating layer 170.

[0085] The insulating resin layer 61 is provided on the first surface 71a side. The insulating resin layer 61 has the first surface 61a and a second surface 61b. The first surface 61a is the surface opposite to the first layer 70. The second surface 61b is the surface on the first layer 70 side.

[0086] A via hole 63 is formed in the insulating resin layer 61. The via hole 63 is a hole penetrating the insulating resin layer 61 in the thickness direction, and opens at the first surface 61a and the second surface 61b. The via hole 63 has a side surface 64 which is a side wall. The via hole 63 is formed in a shape such that the dimension in the direction perpendicular to the thickness direction gradually decreases from the second surface 61b toward the first surface 61a. The via hole 63 is formed in, for example, a truncated cone shape. As described above, the via hole 63 is filled with a part of the wiring layer 72.

[0087] The inorganic insulating layer 109 covers the second surface 81b. The inorganic insulating layer 109 has a through hole 110 at the position of the opening 86c of the recess 86 for a via.

[0088] The seed adhesion layer 101 is, for example, a first metal-containing layer. The seed adhesion layer 101 is, for example, a layer containing titanium. The seed adhesion layer 101 includes a portion that covers a part of the inorganic insulating layer 109 and a portion that covers the inner surface of the via recess 86.

[0089] The seed layer 102 is, for example, a second metal-containing layer. The seed layer 102 is a metal layer provided on the seed adhesion layer 101. The seed layer 102 is made of the same material as the conductor layer 103 or a metal material having a smaller ionization tendency than the material of the conductor layer 103. The seed layer 102 is made of, for example, copper.

[0090] The conductor layer 103 is provided on the seed adhesion layer 101. The conductor layer 103 fills the via recess 86. The portion of the conductor layer 103 that fills the via recess 86 is the via portion 83. The conductor layer 103 is electrically connected to an interlayer connection conductor layer 90 composed of a conductor layer 77 and a conductor layer 87 through the seed adhesion layer 101 and the seed layer 102. The conductor layer 103 is made of, for example, copper.

[0091] The solder resist layer 104 is provided on the inorganic insulating layer 109 and the conductor layer 103. The solder resist layer 104 has through holes 104a that expose parts of the conductor layer 103. These through holes 104a enable electrical connection between the multilayer wiring board 12 and the FC-BGA board 11 via the second bonding electrodes 14.

[0092] The surface treatment layer 105 is provided on a portion of the conductor layer 103 that is exposed in the through-hole 104a of the solder resist layer 104. The surface treatment layer 105 prevents oxidation of the surface of the conductor layer 103 and improves wettability with solder.

[0093] The insulating resin layer 107 is provided on the first surface 61a of the insulating resin layer 61 and a part of the wiring layer 72. The insulating resin layer 107 has a through hole at the position of the via portion 62.

[0094] The conductor layer 108 is formed in the through-hole of the insulating resin layer 107. The conductor layer 108 is made of, for example, copper. The first bonding electrode 40 shown in FIG.

[0095] Next, a description will be given of an example of a method for manufacturing the multilayer wiring board 12. Figures 4 to 28 are cross-sectional views that roughly show an example of a method for manufacturing the multilayer wiring board 12.

[0096] In one example of this manufacturing method, first, a structure shown in Fig. 5 is obtained. Below, the steps for obtaining the structure in Fig. 5 will be described in order.

[0097] First, as shown in FIG. 4, a release layer 3 is provided on one surface of a support 2 . The support 2 is preferably transparent since light may be irradiated onto the peeling layer 3 through the support 2. The support 2 may be, for example, a glass plate. Since a glass plate has excellent flatness and high rigidity, it is suitable for forming a fine pattern of the multilayer wiring board 12 on the support 2. Furthermore, since a glass plate has a small CTE (Coefficient of Thermal Expansion) and is not easily distorted, it is excellent in ensuring pattern arrangement accuracy and flatness.

[0098] When a glass plate is used as the support 2, the thickness of the glass plate is preferably thicker from the viewpoint of preventing warping during the manufacturing process, and is, for example, 0.5 mm or more, preferably 1.2 mm or more. The CTE of the glass plate is preferably 3 ppm or more and 16 ppm or less, and more preferably about 10 ppm from the viewpoint of the CTE of the FC-BGA substrate 11 and the functional device 20.

[0099] Examples of glass used as a material for forming the support 2 include quartz glass, borosilicate glass, alkali-free glass, soda glass, and sapphire glass. In cases where the support 2 does not need to be transparent when peeling it off, such as when a resin that foams when heated is used for the peeling layer 3, a material with little distortion, such as metal or ceramics, can be used for the support 2. In the example of this embodiment, a glass plate is used for the support 2.

[0100] The release layer 3 may be, for example, a resin that absorbs light such as UV light, generates heat or changes in quality, and becomes peelable, or may be a resin that foams when heated and becomes peelable. When a resin that becomes peelable when exposed to light such as UV light, for example, laser light, is used, the support 2 is irradiated with light from the side opposite to the side where the release layer 3 is provided, and the support 2 is removed from the bonded body of the multilayer wiring board 12 and the FC-BGA board 11 on the support 2.

[0101] The release layer 3 can be selected from organic resins such as epoxy resin, polyimide resin, polyurethane resin, silicone resin, polyester resin, oxetane resin, maleimide resin, and acrylic resin, and inorganic layers such as amorphous silicon, gallium nitride, and metal oxide layers. The release layer 3 may further contain additives such as a photodecomposition accelerator, a light absorber, a sensitizer, and a filler.

[0102] Furthermore, the peeling layer 3 may have a single-layer structure or a multi-layer structure. For example, a protective layer may be provided on the peeling layer 3 for the purpose of protecting the multilayer wiring board 12 formed on the support 2, and a layer for improving the adhesion between the support 2 and the peeling layer 3 may be provided between the support 2 and the peeling layer 3. Furthermore, a laser light reflecting layer or a metal layer may be provided between the peeling layer 3 and the multilayer wiring board 12. The configuration of the peeling layer 3 is not limited to this embodiment. In the example of this embodiment, the peeling layer 3 is made of a resin that absorbs UV light and becomes peelable.

[0103] 5, a seed adhesion layer 5 and a seed layer 6 are provided on the release layer 3, for example, in a vacuum. The seed adhesion layer 5 is a layer that improves the adhesion of the seed layer 6 to the release layer 3 and prevents peeling of the seed layer 6. The seed layer 6 also acts as a power supply layer for electrolytic plating in forming wiring.

[0104] The seed adhesion layer 5 and the seed layer 6 can be formed by, for example, a sputtering method or a vapor deposition method. Examples of materials for the seed adhesion layer 5 and the seed layer 6 include Cu, Ni, Al, Ti, Cr, Mo, W, Ta, Au, Ir, Ru, Pd, Pt, AlSi, AlSiCu, AlCu, NiFe, ITO (Indium Tin Oxide), IZO (Indium Zinc Oxide), AZO (Aluminum-doped Zinc Oxide), ZnO, PZT (Lead Zirconate Titanate), TiN, Cu 3 N 4, a Cu alloy, or a combination of a plurality of these may be used. In the example of the present embodiment, in consideration of electrical characteristics, ease of manufacture, and cost, a titanium layer is formed as the seed adhesion layer 5 and a copper layer is formed as the seed layer 6 in this order by a sputtering method.

[0105] The total thickness of the seed adhesion layer 5 and the seed layer 6 is preferably 1 μm or less. In this example, a titanium layer having a thickness of 50 nm is formed as the seed adhesion layer 5, and a copper layer having a thickness of 300 nm is formed as the seed layer 6.

[0106] Next, as shown in FIG. 6, a resist layer 140 is provided on the seed layer 6. The resist layer 140 is made of a photosensitive resin. As the photosensitive resin, for example, a photosensitive polyimide resin, a photosensitive benzocyclobutene resin, a photosensitive epoxy resin, or a modified product thereof can be used. The photosensitive resin may be in a liquid form or a film form.

[0107] When a liquid photosensitive resin is used as the material of the resist layer 140, the resist layer 140 can be formed by any of slit coating, curtain coating, die coating, spray coating, electrostatic coating, inkjet coating, gravure coating, screen printing, gravure offset printing, spin coating, and doctor coating. When a film-like photosensitive resin is used for the resist layer 140, the resist layer 140 can be provided on the seed layer 6 by any of lamination, vacuum lamination, vacuum pressing, and the like.

[0108] Next, through holes 141 are formed in the resist layer 140 by, for example, photolithography. Plasma treatment may be performed on the through holes 141 to remove residues from development. The thickness of the resist layer 140 is set according to the thickness of the conductor layer 108 to be provided in the through holes 141. In this embodiment, the thickness of the resist layer 140 is, for example, 8 μm.

[0109] The shape of the through holes 141 in a plan view is set according to the pitch of the bonding electrodes of the functional device 20 and the shape of the bonding electrodes. In this embodiment, the through holes 141 are circular, have an opening shape of φ25 μm, and have a pitch of 55 μm. Note that the plan view here refers to the shape seen in the thickness direction of the resist layer 140.

[0110] 7, a conductor layer 108 is formed on the seed layer 6 by electrolytic plating. The conductor layer 108 constitutes an electrode for bonding with the functional device 20. Examples of electrolytic plating for forming the conductor layer 108 include electrolytic nickel plating, electrolytic copper plating, electrolytic chromium plating, electrolytic Pd plating, electrolytic gold plating, electrolytic rhodium plating, and electrolytic iridium plating, among which electrolytic copper plating is preferable because it is simple, inexpensive, and has good electrical conductivity.

[0111] Since the conductor layer 108 serves as an electrode for bonding to the functional device 20, it is desirable that the thickness of the conductor layer 108 be 1 μm or more from the viewpoint of solder bonding, and 30 μm or less from the viewpoint of productivity.

[0112] 8, the resist layer 140 is removed. The resist layer 140 can be dissolved or peeled off by dry etching or by immersion in an alkaline solution or solvent.

[0113] 9, an insulating resin layer 107 is provided so as to embed the conductor layer 108. The material forming the insulating resin layer 107 may be a photosensitive resin or a non-photosensitive resin, and further, it does not have to be the same material as the insulating resin layers 61, 71, and 81 described later.

[0114] 10, the upper surface of the conductor layer 108 is exposed by physical polishing, or by physical polishing and surface polishing such as CMP processing. The conductor layer 108 may be formed by a damascene process.

[0115] 11, an insulating resin layer 61 is provided on the conductor layer 108 and the insulating resin layer 107. The insulating resin layer 61 is an example of an insulating layer that includes an insulating resin layer as an outermost layer. The insulating resin layer 61 is made of, for example, a non-photosensitive resin.

[0116] As the non-photosensitive resin, for example, polyimide resin, benzocyclobutene resin, epoxy resin, or modified products thereof can be used. Non-photosensitive resins such as polyimide have excellent insulating properties and mechanical properties, and can achieve high heat resistance. In addition, inorganic particles such as silica, alumina, and zirconia may be added to the non-photosensitive resin as a filler. Here, as an example, a non-photosensitive polyimide resin is used as the non-photosensitive resin.

[0117] The non-photosensitive resin may be in the form of a liquid or a film.

[0118] When a liquid non-photosensitive resin is used, the insulating resin layer 61 can be formed by a method selected from, for example, slit coating, curtain coating, die coating, spray coating, electrostatic coating, inkjet coating, gravure coating, screen printing, gravure offset printing, spin coating, and doctor coating. According to one example, the insulating resin layer 61 is formed by a spin coating method using a non-photosensitive resin.

[0119] When a film-like non-photosensitive resin is provided as the insulating resin layer 61, lamination, vacuum lamination, vacuum pressing, or the like can be applied. The insulating resin layer 61 is formed so as to have a thickness of, for example, 2 μm on the conductor layer 108 . After the insulating resin layer 61 is formed, the surface of the insulating resin layer 61 may be planarized by physical polishing, or physical polishing and polishing by CMP or the like. Similarly, the surfaces of the insulating resin layer 71 and the insulating resin layer 81 may be planarized after formation.

[0120] The material used to form the insulating resin layer 61 is not limited to a non-photosensitive resin. The insulating resin layer 61 may be formed from a photosensitive resin. An insulating resin layer formed using a photosensitive resin contains elements such as phosphorus and sulfur derived from an initiator, etc. On the other hand, an insulating resin layer formed from a non-photosensitive resin generally does not contain these elements. Therefore, depending on whether the insulating resin layer contains the above elements, it can be determined whether the insulating resin layer is formed from a non-photosensitive resin or a photosensitive resin.

[0121] Next, the first inorganic insulating layer 160 is formed on the insulating resin layer 61. The first inorganic insulating layer 160 is formed, for example, by plasma CVD (Chemical Vapor Deposition). The material of the first inorganic insulating layer 160 includes, for example, one or more insulators selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride, silicon oxide with added fluorine, and silicon oxide with added carbon. The material of the first inorganic insulating layer 160 may be the same as or different from the material of the second inorganic insulating layer 200, the first inorganic insulating layer 170, the second inorganic insulating layer 210, and the inorganic insulating layer 109 described later. Even if two inorganic insulating layers in contact with each other are made of the same material, the interface between them can be confirmed by observing a cross section parallel to the thickness direction, for example, with a scanning electron microscope.

[0122] 12, a resist layer 190 having through holes 191 is provided on the first inorganic insulating layer 160. The resist layer 190 can be provided by the same method as the resist layer 140, for example.

[0123] 13, the first inorganic insulating layer 160 is etched using the resist layer 190 as a mask to form the first through hole 162 at the position of the conductor layer 108. As a method for etching the first inorganic insulating layer 160, for example, a dry etching method using a fluorocarbon gas can be applied.

[0124] Next, as shown in FIG. 14, the insulating resin layer 61 is etched using the first inorganic insulating layer 160 as a mask to form via holes 63, which are recesses, at the positions of the through holes 162.

[0125] For example, a dry etching method using oxygen gas can be applied as a method for etching the insulating resin layer 61. If the via hole 63 is formed in a forward tapered shape, it becomes easy to form the seed adhesion layer 78 and the seed layer 79 without generating discontinuous parts in the via hole 63.

[0126] As shown in FIG. 14, if the resist layer 190 remains after the via hole 63 is formed, the resist layer 190 is removed as shown in FIG.

[0127] 16, a resist layer 143 having a groove 144 and a through hole 145 which is a second through hole is formed on the first inorganic insulating layer 160. The resist layer 143 can be formed by, for example, the same method as that described above for the resist layer 140.

[0128] The groove 144 corresponds to the groove portion 74. The through hole 145 corresponds to the land recess 75. Here, as an example, the groove 144 is formed so that the cross section perpendicular to the length direction has a forward tapered shape. The through hole 145 is also formed in a forward tapered shape. The groove 144 and the through hole 145 may be formed so that the cross section has a rectangular shape, but forming them in a forward tapered shape makes it easier to form the seed adhesion layer 78 and the seed layer 79 without generating discontinuous parts in the groove 144 and the through hole 145.

[0129] Furthermore, when the groove 144 and the through hole 145 are formed to have a cross section with a forward tapered shape, the contact area between the insulating resin layer 71 and the first inorganic insulating layer 160 is increased compared to when the cross section is made rectangular without changing the cross-sectional area. This makes it possible to improve the adhesion between the insulating resin layer 71 and the first inorganic insulating layer 160. Similarly, it is possible to improve the adhesion between the seed adhesion layer 78 and the seed layer 79, and between the seed layer 79 and the conductor layer 77.

[0130] The resist layer 143 in which the grooves 144 and the through holes 145 are formed as described above is an example of a dummy layer. One or more of the through holes 145 communicate with the via holes 63. The opening of the through hole 145 on the via hole 63 side is larger than the opening of the via hole 63 on the through hole 145 side. The opening of the via hole 63 on the through hole 145 side is disposed within the opening of the through hole 145.

[0131] 17, a seed adhesion layer 78 is formed on the resist layer 143, the first inorganic insulating layer 160, the insulating resin layer 61, and the conductor layer 108, for example, in a vacuum. That is, the seed adhesion layer 78 is formed to cover the upper surface of the first inorganic insulating layer 160, the upper surface of the resist layer 143, the inner surface of the via hole 63, the inner surface of the groove 144, the inner surface of the through hole 162, and the inner surface of the through hole 145. Subsequently, a seed layer 79 is formed on the seed adhesion layer 78, for example, in a vacuum.

[0132] In this embodiment, the seed adhesion layer 78 is made of titanium from the viewpoints of electrical properties, ease of manufacture, and cost, and also to function as a copper diffusion prevention layer. The seed layer 79 is made of copper, taking into consideration the electrical properties, ease of manufacture, and cost. The seed adhesion layer 78 and the seed layer 79 are formed in sequence by a sputtering method.

[0133] When a vapor deposition method is used for forming these films, a seed adhesion layer 78 and a seed layer 79 are provided on the entire exposed surfaces of the resist layer 143, the first inorganic insulating layer 160, the insulating resin layer 61, and the conductor layer 108, as shown in FIG.

[0134] The total thickness of the seed adhesion layer 78 and the seed layer 79 is preferably 1 μm or less. Note that materials other than titanium may be used for the seed adhesion layer 78 as long as they have a copper diffusion prevention function. The material of the seed layer 79 may be the same as that of the conductor layer 77 or may be a metal material having a smaller ionization tendency than that of the conductor layer 77.

[0135] In this embodiment example, the seed adhesion layer 78 has a thickness of 50 nm, and the seed layer 79 has a thickness of 300 nm.

[0136] One or more other layers made of a metal material may be provided between the seed adhesion layer 78 and the seed layer 79. The layer provided between the seed adhesion layer 78 and the seed layer 79 is made of the same material as the conductor layer 77 or a metal material having a smaller ionization tendency than the material of the conductor layer 77.

[0137] 18, a conductor layer 77 is formed on the seed layer 79 by, for example, electrolytic plating. The electrolytic plating for forming the conductor layer 77 is, for example, electrolytic copper plating. This electrolytic plating is performed so that the via hole 63, the through hole 145, the through hole 162, and the groove 144 are completely filled with the conductor layer 77, as shown in FIG.

[0138] 19, the conductor layer 77 and the seed layer 79 are subjected to polishing such as physical polishing and CMP (chemical mechanical polishing) to remove the portions of the conductor layer 77 and the seed layer 79 that are located outside the via hole 63, the through hole 145, the through hole 162, and the groove 144. The seed adhesion layer 78 is also subjected to the same polishing to remove the portions of the seed adhesion layer 78 that are located outside the via hole 63, the through hole 145, and the groove 144. Note that with this polishing, a portion near the upper surface of the resist layer 143 may also be removed.

[0139] In this manner, the portion of the conductor layer 77 in which the via hole 63 is filled, the portion in which the through hole 145 and the through hole 162 are filled, and the portion in which the groove 144 is filled are obtained as the via portion 62, the land portion 72a, and the wiring portion 72b, respectively. In contrast to the conventional semi-additive method, this method does not require an etching process, and therefore a smooth conductor surface can be obtained.

[0140] 20, the resist layer 143 is removed. The resist layer 143 can be removed by dry etching or by immersion in an alkaline solution or solvent.

[0141] 21, a second inorganic insulating layer 200 is formed so as to cover at least the upper surfaces of the land portion 72a and the wiring portion 72b. In this embodiment, the second inorganic insulating layer 200 is formed so as to cover the upper surfaces of the land portion 72a, the wiring portion 72b, the upper surface of the seed adhesion layer 78, the upper surface of the seed layer 79, the side surfaces of the seed adhesion layer 78, and the upper surface of the insulating resin layer 61.

[0142] The second inorganic insulating layer 200 can be formed by a method similar to that described above for the first inorganic insulating layer 160. The material of the second inorganic insulating layer 200 may be the same as or different from the materials of the first inorganic insulating layer 160, the first inorganic insulating layer 170, and the second inorganic insulating layer 210.

[0143] In addition, a layer made of a silane coupling agent may be provided between the first inorganic insulating layer 160 and the seed adhesion layer 78, and between the first inorganic insulating layer 100 and the insulating resin layer 71. By providing a layer made of a silane coupling agent, it is possible to improve the adhesion between the first inorganic insulating layer 160 and the seed adhesion layer 78, and the adhesion between the first inorganic insulating layer 160 and the insulating resin layer 71. When the adhesion is improved, even if the multilayer wiring substrate 12 is warped due to, for example, heat, peeling of the first inorganic insulating layer 160 and the seed adhesion layer 78, and peeling of the first inorganic insulating layer 160 and the insulating resin layer 71 are unlikely to occur.

[0144] Moreover, the multilayer wiring board 12 of the present embodiment exhibits higher insulation reliability than a configuration in which an inorganic insulating layer is formed on a wiring portion formed by a conventional semi-additive process. When the semi-additive process is used, the wiring portion is formed by etching, so that the surface of the wiring portion is roughened.

[0145] Since the surface of the wiring is roughened, the conformability of the inorganic insulating film is reduced, which may result in the formation of pinholes in the inorganic insulating film. Copper diffuses through these pinholes, reducing the insulation reliability. Furthermore, if the inorganic insulating film is made thicker to eliminate the pinholes, the effect of the difference in linear expansion coefficient between copper and the inorganic insulating film becomes stronger, which may cause peeling at the copper / inorganic insulating film interface.

[0146] Next, as shown in FIG. 22, an insulating resin layer 71 having a via recess 76 is formed on the second inorganic insulating layer 200, for example, by the same method as that described above for the insulating resin layer 61. The insulating resin layer 71 is formed so as to cover the second inorganic insulating layer 200 and fill the gap between the land portion 72a and the wiring portion 72b. For example, the insulating resin layer 71 having the via recess 76 at one or more positions of the land portion 72a is obtained by spin-coating a non-photosensitive polyimide resin on the second inorganic insulating layer 200 and patterning by etching using a mask. The material of the insulating resin layer 71 may be the same as or different from the material of the insulating resin layer 61 and the insulating resin layer 81 described later.

[0147] In this manner, the first layer 70 including the insulating resin layer 71, the conductor layer 77, the seed adhesion layer 78, the seed layer 79, the first inorganic insulating layer 160, and the second inorganic insulating layer 200 is obtained.

[0148] 11 to 20 are sequentially performed to form a first inorganic insulating layer 170, a second inorganic insulating layer 210, a seed adhesion layer 88, a seed layer 89, a conductor layer 87 including the land portion 82a, the wiring portion 82b, and the via portion 73, and an insulating resin layer 81, as shown in Figures 22 and 23. In this manner, a second layer 80 including the insulating resin layer 81, the conductor layer 87, the seed adhesion layer 88, the seed layer 89, the first inorganic insulating layer 170, and the second inorganic insulating layer 210 is obtained.

[0149] In the step of forming the second layer 80, the insulating resin layer 71 and the sixth portion 203 covering the upper surface of the land portion 72a of the second inorganic insulating layer 200 are etched using the first inorganic insulating layer 170 as a mask to form a via recess 76, which is a recess, at the position of the through hole 172, in the same manner as described with reference to FIG. 14. The insulating resin layer 71 and the second inorganic insulating layer 200 are an example of an insulating layer including an insulating resin layer as the outermost layer. The through hole 203a of the sixth portion 203 is formed in this step.

[0150] The material of the first inorganic insulating layer 170 may be the same as or different from the materials of the first inorganic insulating layer 160, the second inorganic insulating layer 200, the second inorganic insulating layer 210, and the inorganic insulating layer 109. The material of the second inorganic insulating layer 210 may be the same as or different from the materials of the first inorganic insulating layer 160, the first inorganic insulating layer 170, the second inorganic insulating layer 200, and the inorganic insulating layer 109.

[0151] The material of the insulating resin layer 81 may be the same as the material of the insulating resin layer 61 and the insulating resin layer 71, or may be different.

[0152] 23, the inorganic insulating layer 109 is formed by a method similar to that described above for the first inorganic insulating layer 160. The material of the inorganic insulating layer 109 may be the same as or different from the material of the first inorganic insulating layer 160 and the first inorganic insulating layer 170.

[0153] 14, the insulating resin layer 81 and the sixth portion 213 covering the upper surface of the land portion 82a of the second inorganic insulating layer 210 are etched using the inorganic insulating layer 109 as a mask to form a via recess 86, which is a recess, at the position of the through hole 110. The insulating resin layer 81 and the second inorganic insulating layer 210 are an example of an insulating layer including an insulating resin layer as the outermost layer. The through hole 213a of the sixth portion 213 is formed in this process.

[0154] Next, for example, by a method similar to that described above for the seed adhesion layer 78 and the seed layer 79, the seed adhesion layer 101 and the seed layer 102 are formed sequentially on the inorganic insulating layer 109, the insulating resin layer 81 and the land portion 82a, as shown in FIG. Next, for example, by the same method as that described above for the insulating resin layer 107, a resist layer 146 having through holes 147 is formed on the seed layer 102 as shown in FIG.

[0155] 26, a conductor layer 103 is formed on the seed layer 102. The conductor layer 103 is preferably formed by electrolytic copper plating.

[0156] Next, as shown in FIG. 27, the resist layer 146 is removed.

[0157] Next, the exposed portion of the seed adhesion layer 101 is removed, and then the exposed portion of the seed layer 102 is removed. The resist layer 146 is removed, for example, by a solution or a solvent. The seed adhesion layer 101 and the seed layer 102 can be removed, for example, by immersing them in a chemical solution. The chemical solution for removing the seed adhesion layer 101 is, for example, an alkaline etching agent. The chemical solution for removing the seed layer 102 is, for example, an acidic etching agent.

[0158] 28, a solder resist layer 104 is provided on the inorganic insulating layer 109 and the conductor layer 103. Next, through holes 104a are formed in the solder resist layer 104. The material for the solder resist layer 104 may be an insulating resin such as an epoxy resin or an acrylic resin. In the embodiment of the present invention, a photosensitive epoxy resin containing a filler is used as the solder resist layer 104.

[0159] Next, as shown in FIG. 29, a surface treatment layer 105 is formed on the portion of the conductor layer 103 exposed in the through hole 104a. In this embodiment, the surface treatment layer 105 is formed by electroless Ni / Pd / Au plating. The surface treatment layer 105 may be an OSP (Organic Solderability Preservative) film, that is, a surface treatment layer made of a water-soluble preflux. Alternatively, the surface treatment layer 105 may be an electroless tin plating or an electroless Ni / Au plating layer. This completes the multilayer wiring board 12 supported on the support 2, that is, the multilayer wiring board with a support.

[0160] Next, a solder material is placed on the surface treatment layer 105, and then melted, cooled, and fixed to obtain the second bonding electrode 14.

[0161] 30, the multilayer wiring board 12 on the support 2 and the FC-BGA board 11 are joined together, and then a second underfill layer 13 is formed between them. The material of the second underfill layer 13 is, for example, a material in which one of epoxy resin, urethane resin, silicone resin, polyester resin, oxetane resin, and maleimide resin, or a mixture of two or more of these resins, to which silica, titanium oxide, aluminum oxide, magnesium oxide, zinc oxide, or the like is added as a filler, is used. The second underfill layer 13 is formed by filling with a liquid resin.

[0162] Next, the support 2 is removed as shown in Fig. 31 and Fig. 32. One example of the removal is peeling. For example, as shown in Fig. 31, a laser beam 23 is irradiated from the rear surface of the support 2, i.e., the surface of the support 2 opposite to the FC-BGA substrate 11, to the peeling layer 3 formed at the interface with the support 2. By irradiating the laser beam 23, it becomes possible to remove the support 2 from the multilayer wiring substrate 12 as shown in Fig. 32.

[0163] Next, the release layer 3, the seed adhesion layer 5 and the seed layer 6 are sequentially removed to obtain the composite wiring board 10.

[0164] 1, a functional device 20 is mounted to complete the packaged device 1. Prior to mounting the functional device 20, the conductor layer exposed on the surface may be subjected to a surface treatment such as electroless Ni / Pd / Au plating, OSP, electroless tin plating, or electroless Ni / Au plating to prevent oxidation and improve the wettability of the solder bumps.

[0165] The joints are then sealed with a first underfill layer 30 . The material of the first underfill layer 30 may be, for example, the material exemplified for the second underfill layer 13. The first underfill layer 30 may be formed, for example, by the same method as that described above for the second underfill layer 13.

[0166] In this manner, the packaged device 1 shown in FIG. 1 is completed.

[0167] In the above method, the multilayer wiring board 12 is bonded to the FC-BGA substrate 11, and then the functional device 20 is bonded to the multilayer wiring board 12. Alternatively, the functional device 20 may be bonded to the multilayer wiring board 12, and then the multilayer wiring board 12 may be bonded to the FC-BGA substrate 11.

[0168] In the packaged device 1 configured in this manner, the first layer 70 includes a first inorganic insulating layer 160 and a second inorganic insulating layer 200. The first inorganic insulating layer 160 includes a first portion 163 covering the first surface 71a, a second portion 164 closing the opening of the groove portion 74, and a third portion 165 covering the periphery of the surface of the land portion 72a on the first surface 71a side.

[0169] The second inorganic insulating layer 200 includes a fourth portion 201 covering the bottom surface 74b of the groove portion 74 and a sixth portion 203 covering the bottom surface 75b of the land recess 75. That is, the second inorganic insulating layer 200 is interposed between the upper surface of the land portion 72a and the insulating resin layer 71, and between the upper surface of the wiring portion 72b and the insulating resin layer 71. The second inorganic insulating layer 200 serves as a barrier layer that makes it difficult for metal to diffuse from the upper surfaces of the land portion 72a and the wiring portion 72b into the insulating resin layer 71.

[0170] Similarly, the second layer 80 includes a first inorganic insulating layer 170 and a second inorganic insulating layer 210. The first inorganic insulating layer 170 includes a first portion 173 that covers the first surface 81a of the second layer 80, a second portion 174 that closes the opening of the groove portion 84, and a third portion 175 that covers the periphery of the surface of the land portion 82a on the first surface 81a side.

[0171] The second inorganic insulating layer 210 includes a fourth portion 211 covering the bottom surface 84b of the groove portion 84 and a sixth portion 213 covering the bottom surface 85b of the land recess 85. That is, the second inorganic insulating layer 210 is interposed between the upper surface of the land portion 82a and the insulating resin layer 81, and between the upper surface of the wiring portion 82b and the insulating resin layer 81. The second inorganic insulating layer 210 serves as a barrier layer that makes it difficult for metal to diffuse from the upper surfaces of the land portion 82a and the wiring portion 82b into the insulating resin layer 81.

[0172] For this reason, metal is unlikely to diffuse from one of the adjacent insulating resin layers to the other. Therefore, the above-mentioned multilayer wiring board 12 achieves excellent insulation reliability. Therefore, the composite wiring board 10 and the packaged device 1 including the multilayer wiring board 12 also achieve excellent insulation reliability.

[0173] In addition, the first portion 163 covering the first surface 71a of the first inorganic insulating layer 160 and the first portion 173 covering the first surface 81a of the first inorganic insulating layer 170 improve the rigidity of the first layer 70 and the second layer 80, making it possible to reduce the likelihood of warping or bending of the multilayer wiring board 12.

[0174] Furthermore, the first inorganic insulating layer 160 functions as a protective layer for the insulating resin layer 61 when removing the resist layer 190 and the resist layer 143. Therefore, it is possible to protect the insulating resin layer 61 when removing the resist layer 190 and the resist layer 143. Similarly, it is possible to protect the insulating resin layer 71 by the first inorganic insulating layer 170 of the second layer 80.

[0175] Furthermore, the first inorganic insulating layer 160 can be used as a mask for forming the via hole 63 in the insulating resin layer 61. Similarly, the first inorganic insulating layer 170 can be used as a mask for forming the via recess 76 in the insulating resin layer 71.

[0176] In the above method, the resist layer 143 is removed after the conductor layer 77 is formed and polished, and the insulating resin layer 71 is provided instead of the resist layer 143 being a component of the multilayer wiring board 12. Similarly, the resist layer 190 is removed after the conductor layer 87 is formed and polished, and the insulating resin layer 81 is provided instead of the resist layer 190 being a component of the multilayer wiring board 12.

[0177] In the deposition and polishing processes of the conductor layers 77, 87, etc., there is a risk of metal diffusing into the resist layers 143, 180. The above-described multilayer wiring board 12 does not include the resist layers 143, 190 into which metal may be diffused as a component, and is therefore advantageous in terms of achieving high insulation reliability in this respect as well.

[0178] Furthermore, in the first layer 70, the second inorganic insulating layer 200 further includes a seventh portion 204 covering the side surface 75a which is the side wall of the land recess 75, a fifth portion 202 covering the side surface 74a which is the side wall of the groove portion 74, and an eighth portion 205 interposed between the first surface 71a and the first portion 163 of the first inorganic insulating layer 160 which covers the first surface 71a.

[0179] In the second layer 80, the second inorganic insulating layer 210 further includes a seventh portion 214 covering the side surface 85a which is the side wall of the land recess 85, a fifth portion 212 covering the side surface 84a which is the side wall of the groove portion 84, and an eighth portion 205 interposed between the first surface 81a and the first portion 173 of the first inorganic insulating layer 170 which covers the first surface 81a.

[0180] Therefore, in this structure, metal is less likely to diffuse from the side surfaces of the lands 72a, 82a and the wiring portions 72b, 82b to the insulating resin layers 71, 81 compared to a structure in which the second inorganic insulating layers 200, 210 do not include portions covering the side walls of the land recesses 75, 85 and the grooves 74, 84. Therefore, the multilayer wiring board 12 achieves excellent insulation reliability. Therefore, the composite wiring board 10 and the packaged device 1 including the multilayer wiring board 12 also achieve excellent insulation reliability.

[0181] Furthermore, the rigidity of the first layer 70 and the second layer 80 is improved by the eighth portion 205 interposed between the first surface 71a and the first portion 163 covering the first surface 71a, and the eighth portion 215 interposed between the first surface 81a and the first portion 173 covering the first surface 81a, making it possible to make the multilayer wiring board 12 less susceptible to warping or bending.

[0182] Furthermore, insulating resin layer 71 and insulating resin layer 81 are made of a non-photosensitive resin. Therefore, insulating resin layer 71 and insulating resin layer 81 can achieve excellent insulation. Therefore, the above-mentioned multilayer wiring board 12 achieves excellent insulation reliability. Therefore, composite wiring board 10 and packaged device 1 including multilayer wiring board 12 also achieve excellent insulation reliability.

[0183] Furthermore, the seed adhesion layers 78 and 88 also function as barrier layers that make it difficult for metal to diffuse from the conductor layers 77 and 87 to the insulating resin layers 71 and 81. When the seed layers 79 and 89 are made of metal materials that have a smaller ionization tendency than the materials of the conductor layers 77 and 87, respectively, they also function as barrier layers that make it difficult for metal to diffuse from the conductor layers 77 and 87 to the insulating resin layers 71 and 81.

[0184] Furthermore, the seed adhesion layers 78, 88 cover the sides and bottoms of the land portions 72a, 82a, via portions 73, 83, and groove portions 74, 84, making it even more difficult for metal to diffuse from the conductor layers 77, 87 to the insulating resin layers 71, 81.

[0185] The portions of the seed adhesion layer 78 and the seed layer 79 covering the side surfaces of the land portion 72a and the wiring portion 72b tend to become thinner as the distance from the top surface of the conductor layer 77 increases. Similarly, the portions of the seed adhesion layer 88 and the seed layer 89 covering the side surfaces of the land portion 82a and the wiring portion 82b tend to become thinner as the distance from the top surface of the conductor layer 87 increases. When the thickness of the barrier layer decreases, its ability to prevent metal diffusion decreases.

[0186] In contrast, in this embodiment, as described above, the second inorganic insulating layer 200 includes a portion covering the side surface 75a which is the side wall of the land recess 75 and a portion covering the side surface 74a which is the side wall of the groove 74. The second inorganic insulating layer 210 includes a portion covering the side surface 75a which is the side wall of the land recess 85 and a portion covering the side surface 84a which is the side wall of the groove 84.

[0187] For this reason, even if the film thickness of the portions of the seed adhesion layer 78 and the seed layer 79 covering the side surfaces of the land portion 72a and the wiring portion 72b, and the portions of the seed adhesion layer 88 and the seed layer 89 covering the side surfaces of the land portion 82a and the wiring portion 72b, becomes thinner, the second inorganic insulating layers 200, 210 make it difficult for metal to diffuse from the side surfaces of the land portion 72a and the wiring portion 72b into the insulating resin layer 71.

[0188] Next, the operation and effect of the configuration of multilayer wiring board 12 of the present embodiment and the manufacturing method thereof will be described with reference to a multilayer wiring board 150 shown in FIG. 33 as a comparative example.

[0189] 2 and 3, in this embodiment, the gap between the land portion 72a and the wiring portion 72b is filled with the insulating resin layer 71. The first inorganic insulating layer 160 includes a first portion 163 that covers the first surface 71a of the insulating resin layer 71. The gap between the land portion 82a and the wiring portion 82b is filled with the insulating resin layer 81. The first inorganic insulating layer 170 includes a first portion 173 that covers the first surface 81a of the insulating resin layer 81.

[0190] For this reason, metal is unlikely to diffuse from one of the adjacent insulating resin layers to the other. Therefore, the above-mentioned multilayer wiring board 12 achieves excellent insulation reliability. Therefore, the composite wiring board 10 and the packaged device 1 including the multilayer wiring board 12 also achieve excellent insulation reliability.

[0191] Furthermore, the side surfaces of the land portions 72a, 82a of the interlayer connection conductor layer 90 contact the insulating resin layers 71, 81 via the seed adhesion layers 78, 88. By using titanium, which has good adhesion to the insulating resin layers 71, 81, for the seed adhesion layers 78, 88, it is possible to suppress peeling of the interlayer connection conductor layer 90 from the insulating resin layers 71, 81 due to the difference in linear expansion coefficient between copper and resin during a temperature cycle test.

[0192] The multilayer wiring board of the comparative example is a multilayer wiring board 150 in which conductor layers and interlayer connection conductor layers are fabricated by a semi-additive method, which is a known technique, as shown in Fig. 33. The multilayer wiring board 150 has a similar configuration to the multilayer wiring board 12 of the present embodiment, but differs in the following points. In addition, components in the multilayer wiring board 150 that have the same functions as the multilayer wiring board 12 of the present embodiment will be described with the same reference numerals as those in the multilayer wiring board 12. In addition, the cross-sectional view of Fig. 33 depicts only the wiring portion 72b and land portion 72a of the first layer 70 and their vicinity in the multilayer wiring board 150.

[0193] 33, the multilayer wiring board 150 of the comparative example differs from the multilayer wiring board 12 of the present embodiment in that it does not have a first inorganic insulating layer 160 and a first inorganic insulating layer 170. Furthermore, the multilayer wiring board 150 of the comparative example differs from the multilayer wiring board 12 of the present embodiment in that the seed adhesion layer 78 and the seed layer 79 of the wiring layer 72 do not cover the side surfaces of the conductor layer 77. Furthermore, the multilayer wiring board 150 of the comparative example differs from the multilayer wiring board 12 of the present embodiment in that the seed adhesion layer 88 and the seed layer 89 of the wiring layer 82 do not cover the side surfaces of the conductor layer 87.

[0194] The structure of the multilayer wiring board 150 of the comparative example will be described with reference to the first layer 70. As shown in FIG. 33, in the multilayer wiring board 150 of the comparative example, the side surface of the conductor layer 77 of the wiring layer 72 contacts the insulating resin layer 71. That is, the contact area of ​​the conductor layer 77 with the insulating resin layer 71 is larger than that of the multilayer wiring board 12 of the present embodiment. Therefore, the copper of the conductor layer 77 is likely to diffuse into the insulating resin layer 71. As a result, the insulating reliability of the insulating resin layer 71 is likely to decrease. In the multilayer wiring board 150 of the comparative example, the second layer 80 is similar to the first layer 70, that is, the insulating reliability of the insulating resin layer 81 is likely to decrease.

[0195] Furthermore, since the multilayer wiring board 150 of the comparative example does not include the first inorganic insulating layer 160 and the first inorganic insulating layer 170, the insulation reliability between the insulating resin layer 71 and the insulating resin layer 81 is also likely to decrease.

[0196] Furthermore, the side surface of the land portion 72a contacts the insulating resin layer 71. Therefore, due to the difference in the linear expansion coefficient between copper and resin during a temperature cycle test, peeling is likely to occur at the interface between the land portion 72a and the insulating resin layer 71. The same is true for the second layer 80, that is, peeling is likely to occur at the interface between the land portion 82a and the insulating resin layer 81. <Confirmation of action and effect> To confirm the effects of this embodiment, the following evaluations were carried out on the multilayer wiring board 12 of this embodiment and the multilayer wiring board 150 of the comparative example. <Evaluation method> Insulation reliability evaluation The evaluation was performed under a bias of 3.3 V and an environment of 130°C / 85% RH. The wiring rule was L / S=2 / 2 μm. In both the multilayer wiring board 12 and the multilayer wiring board 150, the thicknesses of the insulating resin layers were set to 1 μm, 1.5 μm, 2 μm, and 2.5 μm.

[0197] In the multilayer wiring board 12, the thickness of the first inorganic insulating layer 160 and the first inorganic insulating layer 170 was set to 50 nm. After 192 hours had elapsed under the above bias and environment, the resistance value was 10 6 The pass condition was a resistance of Ω or more. The number of evaluations for each resin thickness was N=10. <Evaluation results> Insulation reliability evaluation In the multilayer wiring board 150 of the comparative example, insulation failure was confirmed in all the boards at the time of 96 hours regardless of the thickness of the insulating resin layer. On the other hand, in the multilayer wiring board 12 of the present embodiment, the resistance value after 192 hours was 10 6 Ω or more, indicating good insulation reliability.

[0198] The above-described embodiment is merely an example, and it goes without saying that other specific details such as structure can be modified as appropriate.

[0199] Furthermore, in the above example, the first layer 70 has been described as having a configuration including a seed adhesion layer 78 made of titanium that covers the side surface of the conductor layer 77. The seed adhesion layer 78 made of titanium constitutes an inorganic insulating layer. In the case of the configuration including the seed adhesion layer 78 as in the present embodiment, the second inorganic insulating layer 200 may be configured not to include the fifth portion 202 that covers the side wall of the groove portion 74 and the seventh portion 204 that covers the side wall of the land recess 75. Even in this configuration, the seed adhesion layer 78 can prevent diffusion of metal from the conductor layer 77 to the insulating resin layer 71.

[0200] Similarly, in the second layer 80, the second inorganic insulating layer 210 may be configured not to include the fifth portion 212 covering the side wall of the groove portion 84 and the seventh portion 214 covering the side wall of the land recess 75. Even in this configuration, the seed adhesion layer 88 can prevent diffusion of metal from the conductor layer 87 to the insulating resin layer 81.

[0201] In the above example, the second inorganic insulating layer 200 is described as including the eighth portion 205 interposed between the first surface 71a and the first portion 163 covering the first surface 71a, but is not limited thereto. In another example, the second inorganic insulating layer 200 may be configured not to include the eighth portion 205. Similarly, the second inorganic insulating layer 210 is described as including the eighth portion 205 interposed between the first surface 81a and the first portion 173 covering the first surface 71a, but is not limited thereto. In another example, the second inorganic insulating layer 200 may be configured not to include the eighth portion 205.

[0202] In addition, in the above example, the multilayer wiring board 12 includes the first layer 70 and the second layer 80, but the multilayer wiring board 12 may further include one or more layers similar to the first layer 70 and the second layer 80.

[0203] The present invention can be used in a semiconductor device having a wiring board equipped with an interposer or the like interposed between a main board and an IC chip. The invention as originally claimed is set forth below. [1] The laminated structure includes two or more layers, each of which comprises: an insulating resin layer having a first surface and a second surface which is the reverse surface of the first surface, the insulating resin layer being integrally formed in a thickness direction with a first recess opening on the first surface, a groove opening on the first surface, and a second recess opening on the second surface and communicating with at least one of the first recesses; a land portion and a wiring portion in which the first recess and the groove of the insulating resin layer are filled, respectively, and a via portion protruding from the first surface at the position of the land portion, the via portion being a conductor layer in which a recess of another insulating resin layer adjacent to the first surface side is filled; a first inorganic insulating layer including a first portion covering the first surface, a second portion closing an opening of the groove portion, and a third portion covering a peripheral portion of a surface of the land portion on the first surface side; a second inorganic insulating layer including a portion covering the bottom surface of the groove and a portion covering the bottom surface of the first recess; A multilayer wiring board including: [2] 2. The multilayer wiring board according to item 1, wherein the second inorganic insulating layer further includes a portion covering the side wall of the first recess, a portion covering the side wall of the groove, and a portion interposed between the first surface and the first portion covering the first surface. [3] 3. The multilayer wiring board according to item 1 or 2, wherein the material of each of the first inorganic insulating layer and the second inorganic insulating layer contains one or more insulators selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride, silicon oxide doped with fluorine, and silicon oxide doped with carbon. [4] 4. The multilayer wiring board according to any one of items 1 to 3, wherein the insulating resin layer is made of a non-photosensitive resin. [5] 5. The multilayer wiring board according to any one of claims 1 to 4, wherein each of the two or more layers further includes a first metal-containing layer that covers the peripheral edges of the land portion, the side surfaces of the via portion and the wiring portion, the surface of the wiring portion facing the opening of the groove portion, and the surface of the land portion facing the first surface. [6] 6. The multilayer wiring board according to item 5, wherein each of the two or more layers further includes a second metal-containing layer interposed between the first metal-containing layer and the conductor layer and made of the same material as the conductor layer or made of a metal material having a smaller ionization tendency than the material of the conductor layer. [7] 7. The multilayer wiring board according to item 5 or 6, wherein the first metal-containing layer contains titanium. [8] A composite wiring board comprising a first wiring board and a second wiring board bonded to the first wiring board, the first and second wiring boards being electrically connected to each other via a bonding electrode interposed therebetween, and the second wiring board being a multilayer wiring board as described in any one of items 1 to 7. [9] 9. The composite wiring board according to item 8, wherein the first wiring board is a wiring board for a flip chip ball grid array, and the second wiring board is an interposer.

[10] Item 8 or 9, and the composite wiring board according to item 8 or 9; a functional device mounted on a surface of the second wiring substrate opposite to the surface of the first wiring substrate; A packaged device comprising:

[11] forming two or more layers in a laminate, each of the two or more layers comprising: forming a first inorganic insulating layer having a first through hole on an insulating layer including an insulating resin layer as an outermost layer; removing a portion of the insulating layer exposed in the first through hole to form a recess in the insulating layer; forming a dummy layer on the first inorganic insulating layer, the dummy layer having a groove and at least one second through hole communicating with the recess via the first through hole; forming a conductor layer on the dummy layer so as to fill the recess, the groove, the first through hole, and the second through hole; polishing the conductor layer so as to remove a portion located outside the recess, the groove, the first through hole, or the second through hole, thereby obtaining, of the conductor layer, a portion in which the recess is filled, a portion in which the first through hole and the second through hole are filled, and a portion in which the groove is filled as a via portion, a land portion, and a wiring portion, respectively; Thereafter, removing the dummy layer; forming a second inorganic insulating layer so as to cover at least an upper surface of the land portion and an upper surface of the wiring portion; forming an insulating resin layer that covers the second inorganic insulating layer and fills the gap between the land portion and the wiring portion; A method for manufacturing a multilayer wiring board comprising the steps of:

[12] Item 12. The method for manufacturing a multilayer wiring board according to item 11, wherein the material of the first inorganic insulating layer and the second inorganic insulating layer contains one or more insulators selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride, silicon oxide doped with fluorine, and silicon oxide doped with carbon.

[13] Item 13. The method for manufacturing a multilayer wiring board according to item 11 or 12, wherein the insulating resin layer covering the second inorganic insulating layer is made of a non-photosensitive resin.

[14] 14. The method for manufacturing a multilayer wiring board according to any one of claims 11 to 13, wherein the formation of each of the two or more layers further includes forming a first metal-containing layer that covers the upper surfaces of the dummy layer and the first inorganic insulating layer, and the inner surfaces of the recess, the groove, the first through hole, and the second through hole before forming the conductor layer.

[15] Item 15. The method for manufacturing a multilayer wiring board according to item 14, wherein the formation of each of the two or more layers further comprises forming a second metal-containing layer on the first metal-containing layer before forming the conductor layer, the second metal-containing layer being made of the same material as the conductor layer or made of a metal material having a smaller ionization tendency than the material of the conductor layer.

[16] Item 16. The method for manufacturing a multilayer wiring board according to item 14 or 15, wherein the first metal-containing layer contains titanium. [Explanation of symbols]

[0204] 1...packaged device, 2...support, 3...peeling layer, 5...seed adhesion layer, 6...seed layer, 10...composite wiring board, 11...FC-BGA board, 12...multilayer wiring board, 13...second underfill layer, 14...second bonding electrode, 20...functional device, 23...laser light, 30...first underfill layer, 40...first bonding electrode, 50...layer, 61...insulating resin layer, 62...via portion, 63...via hole, 64...side, 70...first layer, 71... Insulating resin layer, 72...wiring layer, 72a...land portion, 72b...wiring portion, 73...via portion, 74...groove portion, 74a...side surface, 74b...bottom surface, 74c...opening, 75...land recess, 75a...side surface, 75c...opening, 77...conductor layer, 78...seed adhesion layer, 79...seed layer, 80...second layer, 81...insulating resin layer, 82...wiring layer, 82a...land portion, 82b...wiring portion, 83...via portion, 84...groove portion, 84a...side surface, 84b...bottom surface, 84c...opening , 85a...side surface, 87...conductor layer, 88...seed adhesion layer, 89...seed layer, 90...interlayer connection conductor layer, 101...seed adhesion layer, 102...seed layer, 103...conductor layer, 104...solder resist layer, 104a...through hole, 105...surface treatment layer, 107...insulating resin layer, 108...conductor layer, 111...core layer, 112...insulating layer, 113...conductor layer, 114...insulating layer, 115...joint conductor, 134...solder resist layer, 140...resist layer, 141...through hole, 143...resist layer, 144...groove, 145...through hole, 146...resist layer, 147...through hole, 150...multilayer wiring board of comparative example, 160...first inorganic insulating layer, 162...through hole, 163...first portion, 164...second portion, 165...third portion, 170...first inorganic insulating layer, 172...through hole, 173...first portion, 174...second portion, 175...third portion, 200...second inorganic insulating layer, 210...second inorganic insulating layer.

Claims

1. The laminated structure includes two or more layers, each of which comprises: an insulating resin layer having a first surface and a second surface which is the reverse side of the first surface, the insulating resin layer being integrally formed in a thickness direction, the insulating resin layer being provided with a first recess opening on the first surface, a groove opening on the first surface, and a second recess opening on the second surface and communicating with one or more of the first recesses; a land portion and a wiring portion in which the first recess and the groove of the insulating resin layer are filled, respectively, and a via portion protruding from the first surface at the position of the land portion, the via portion being a conductor layer in which a recess of another insulating resin layer adjacent to the first surface side is filled; a first inorganic insulating layer including a first portion covering the first surface, a second portion closing an opening of the groove portion, and a third portion covering a peripheral portion of a surface of the land portion on the first surface side; a second inorganic insulating layer including a portion covering the bottom surface of the groove and a portion covering the bottom surface of the first recess; Including, A multilayer wiring board, wherein each of the two or more layers further includes a first metal-containing layer that covers the side surfaces of the land portion, the via portion, and the wiring portion, the surface of the wiring portion facing the opening of the groove portion, and the peripheral portion of the surface of the land portion facing the first surface.

2. 2. The multilayer wiring board according to claim 1, wherein the second inorganic insulating layer further includes a portion covering a side wall of the first recess, a portion covering a side wall of the groove, and a portion interposed between the first surface and the first portion covering it.

3. 3. The multilayer wiring board according to claim 1, wherein the material of each of the first inorganic insulating layer and the second inorganic insulating layer contains one or more insulators selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride, silicon oxide doped with fluorine, and silicon oxide doped with carbon.

4. 4. The multilayer wiring board according to claim 1, wherein the insulating resin layer is made of a non-photosensitive resin.

5. 5. The multilayer wiring board according to claim 1, wherein each of the two or more layers further includes a second metal-containing layer interposed between the first metal-containing layer and the conductor layer and made of the same material as the conductor layer or made of a metal material having a smaller ionization tendency than the material of the conductor layer.

6. 6. The multilayer wiring board according to claim 1, wherein the first metal-containing layer contains titanium.

7. A composite wiring board comprising a first wiring board and a second wiring board joined to the first wiring board, the first and second wiring boards being electrically connected to each other via a joining electrode interposed between them, and the second wiring board being a multilayer wiring board as defined in any one of claims 1 to 6.

8. 8. The composite wiring board according to claim 7, wherein the first wiring board is a wiring board for a flip chip ball grid array, and the second wiring board is an interposer.

9. The composite wiring board according to claim 7 or 8, a functional device mounted on a surface of the second wiring substrate opposite to the surface of the first wiring substrate; A packaged device comprising:

10. forming two or more layers in a laminate, the forming of each of the two or more layers comprising: forming a first inorganic insulating layer having a first through hole on an insulating layer including an insulating resin layer as an outermost layer; removing a portion of the insulating layer exposed in the first through hole to form a recess in the insulating layer; forming a dummy layer on the first inorganic insulating layer, the dummy layer having a groove and at least one second through hole communicating with the recess via the first through hole; forming a conductor layer on the dummy layer so as to fill the recess, the groove, the first through hole, and the second through hole; polishing the conductor layer so as to remove a portion located outside the recess, the groove, the first through hole, or the second through hole, thereby obtaining, of the conductor layer, a portion in which the recess is filled, a portion in which the first through hole and the second through hole are filled, and a portion in which the groove is filled as a via portion, a land portion, and a wiring portion, respectively; Thereafter, removing the dummy layer; forming a second inorganic insulating layer so as to cover at least an upper surface of the land portion and an upper surface of the wiring portion; forming an insulating resin layer that covers the second inorganic insulating layer and fills the gap between the land portion and the wiring portion; A method for manufacturing a multilayer wiring board comprising the steps of:

11. 11. The method for manufacturing a multilayer wiring board according to claim 10, wherein the material of the first inorganic insulating layer and the second inorganic insulating layer contains one or more insulators selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride, silicon oxide doped with fluorine, and silicon oxide doped with carbon.

12. The method for manufacturing a multilayer wiring board according to claim 10 or 11, wherein the insulating resin layer covering the second inorganic insulating layer is made of a non-photosensitive resin.

13. 13. The method for manufacturing a multilayer wiring board according to claim 10, wherein the formation of each of the two or more layers further includes forming a first metal-containing layer that covers the upper surfaces of the dummy layer and the first inorganic insulating layer, and the inner surfaces of the recess, the groove, the first through hole, and the second through hole before forming the conductor layer.

14. The method for manufacturing a multilayer wiring board according to claim 13, wherein the formation of each of the two or more layers further includes forming a second metal-containing layer on the first metal-containing layer before forming the conductor layer, the second metal-containing layer being made of the same material as the conductor layer or made of a metal material having a smaller ionization tendency than the material of the conductor layer.

15. 15. The method for manufacturing a multilayer wiring board according to claim 13, wherein the first metal-containing layer contains titanium.

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