Multi-layer wiring board

Abstract

To provide a multilayer wiring board having high insulation reliability.SOLUTION: A multilayer wiring board 12 includes two or more layers 120 laminated with each other, wherein each of the two or more layers is an insulating resin layer having a first surface S1 and a second surface S2 that is its back face, includes an insulating resin layer 1201 which is provided with a first recess R1 opened in the first surface, a groove part G opened in the first surface, and a second recess R2 which is opened in the second surface and communicates with the one or more first recesses, and which is integrally formed in a thickness direction, an inorganic insulating layer 1202 covering the first surface, and a conductor layer 1203 including a land part 1203L and a wiring part 1203W in which the first recess and the groove part of the insulating resin layer are embedded, and a via part 1203V projecting from the first surface at a position of the land position, in which the via part is embedded with the recess of the other adjacent insulating resin layer on the first surface side.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present invention relates to a multilayer wiring board. [Background technology]

[0002] In recent years, as semiconductor devices become faster and more highly integrated, there is a demand for narrower pitches of bonding terminals used for bonding to semiconductor chips and finer wiring within the substrate for wiring substrates for flip chip ball grid arrays (FC-BGA substrates) on which semiconductor chips are mounted. On the other hand, bonding between FC-BGA substrates and motherboards is required to be performed using bonding terminals arranged at almost the same pitch as before. In response to these demands, a technology has been adopted in which a multilayer wiring substrate including fine wiring, also called an interposer, is provided between the FC-BGA substrate and the semiconductor chip.

[0003] One of these is silicon interposer technology, which manufactures interposers by forming a multilayer wiring structure, each layer of which contains fine wiring, on a silicon wafer using semiconductor circuit manufacturing technology.

[0004] Also, a method has been developed in which the above multi-layer wiring structure is directly fabricated on an FC-BGA substrate, rather than being formed on a silicon wafer. This method involves forming the above multi-layer wiring structure by using chemical mechanical polishing (CMP) or the like in the manufacture of an FC-BGA substrate, the core layer of which is made of, for example, a glass epoxy substrate. This method is disclosed in Patent Document 1.

[0005] Furthermore, there is also a method (hereinafter referred to as a transfer method) in which an interposer is formed on a support such as a glass substrate, the interposer is bonded to an FC-BGA substrate, and then the support is peeled off from the interposer to provide the above-mentioned multilayer wiring structure on the FC-BGA substrate. This method is disclosed in Patent Document 2. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] JP 2014-225671 A [Patent Document 2] International Publication No. 2018 / 047861 Summary of the Invention [Problem to be solved by the invention]

[0007] An object of the present invention is to provide a multilayer wiring board having excellent insulation reliability. [Means for solving the problem]

[0008] According to one aspect of the present invention, there is provided a multilayer wiring board comprising an insulating resin layer having two or more layers stacked on top of each other, each of the two or more layers having a first surface and a second surface which is the back surface of the first surface, the insulating resin layer being formed integrally in the thickness direction with a first recess opening on the first surface, a groove opening on the first surface, and a second recess opening on the second surface and communicating with one or more of the first recesses, the insulating resin layer including an inorganic insulating layer covering the first surface, a land portion and a wiring portion respectively filled with the first recess and the groove portion of the insulating resin layer, and a via portion protruding from the first surface at the position of the land portion, the via portion including a conductor layer having a recess of another insulating resin layer adjacent on the first surface side filled with the recess.

[0009] Here, the insulating resin layer being "integrally formed in the thickness direction" means that there is no interface intersecting the thickness direction inside the insulating resin layer, that is, the insulating resin layer has a single-layer structure. Even if multiple insulating layers stacked on top of each other are made of the same material, their interfaces can be confirmed by observing the cross section with an electron microscope such as a scanning electron microscope.

[0010] According to another aspect of the present invention, there is provided a multilayer wiring board according to the above aspect, wherein the inorganic insulating layer contains one or more insulators selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride, silicon oxide doped with fluorine, and silicon oxide doped with carbon.

[0011] According to yet another aspect of the present invention, there is provided a multilayer wiring board according to any of the above aspects, wherein each of the two or more layers further includes a first metal-containing layer covering the peripheral edges of the land portion, the side surfaces of the wiring portion and the via portion, the surface of the wiring portion facing the opening of the groove portion, and the surface of the land portion facing the first surface. Alternatively, according to yet another aspect of the present invention, there is provided a multilayer wiring board according to any of the above aspects, wherein each of the two or more layers further includes a first metal-containing layer covering the side surfaces of the land portion, the wiring portion, and the via portion and the surface facing the first surface.

[0012] According to yet another aspect of the present invention, there is provided a multilayer wiring board according to any one of the above aspects, wherein the first metal-containing layer contains titanium.

[0013] According to yet another aspect of the present invention, there is provided a multilayer wiring board according to any of the above aspects, wherein each of the two or more layers further includes a second metal-containing layer interposed between the first metal-containing layer and the conductor layer and made of the same material as the conductor layer or made of a metal material having a smaller ionization tendency than the material of the conductor layer.

[0014] According to yet another aspect of the present invention, there is provided a multilayer wiring board of any of the above aspects, wherein cross sections of the first recess and the groove have an inverse tapered shape, and a cross section of the second recess has a forward tapered shape.

[0015] According to yet another aspect of the present invention, there is provided a composite wiring board comprising a first wiring board and a second wiring board joined to the first wiring board, the first and second wiring boards being electrically connected to each other via a joining electrode interposed therebetween, and the second wiring board being a multilayer wiring board according to any of the aspects described above.

[0016] According to yet another aspect of the present invention, there is provided a composite wiring board according to the above aspect, wherein the first wiring board is a wiring board for a flip chip ball grid array, and the second wiring board is an interposer.

[0017] According to yet another aspect of the present invention, there is provided a packaged device comprising a composite wiring board according to any of the above aspects and a functional device mounted on a surface of the second wiring board opposite the first wiring board.

[0018] Here, the term "functional device" refers to a device that operates when at least one of power and an electric signal is supplied, a device that outputs at least one of power and an electric signal when stimulated from the outside, or a device that operates when at least one of power and an electric signal is supplied and outputs at least one of power and an electric signal when stimulated from the outside. The functional device is in the form of a chip, such as a semiconductor chip or a chip in which circuits and elements are formed on a substrate made of a material other than a semiconductor, such as a glass substrate. The functional device may include, for example, one or more of a large scale integrated circuit (LSI), a memory, an imaging element, a light-emitting element, and a MEMS (Micro Electro Mechanical Systems). The MEMS may be, for example, one or more of a pressure sensor, an acceleration sensor, a gyro sensor, a tilt sensor, a microphone, and an acoustic sensor. According to one example, the functional device is a semiconductor chip including an LSI.

[0019] According to yet another aspect of the present invention, there is provided a method for manufacturing a multilayer wiring board, comprising forming two or more stacked layers, the formation of each of the two or more layers including forming a recess in an insulating resin layer, forming an inorganic insulating layer covering an upper surface of the insulating resin layer and an inner surface of the recess, forming a dummy layer on the inorganic insulating layer, the dummy layer having a groove and at least one through hole communicating with the recess, removing portions of the inorganic insulating layer exposed in the recess, the groove, and the through hole, forming a conductor layer on the dummy layer so as to fill the recess, the groove, and the through hole, polishing the conductor layer so as to remove portions outside the recess, the groove, or the through hole, thereby obtaining portions of the conductor layer in which the recess is filled, the portion in which the through hole is filled, and the portion in which the groove is filled as a via portion, a land portion, and a wiring portion, respectively, and then removing the dummy layer.

[0020] According to yet another aspect of the present invention, there is provided a method for manufacturing a multilayer wiring board according to the above aspect, wherein the inorganic insulating layer contains one or more insulators selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride, silicon oxide doped with fluorine, and silicon oxide doped with carbon.

[0021] According to still another aspect of the present invention, there is provided a method for manufacturing a multilayer wiring board according to any one of the above aspects, wherein the recess, the groove and the through hole are formed to have a forward tapered cross section.

[0022] According to yet another aspect of the present invention, there is provided a method for manufacturing a multilayer wiring board according to any of the above aspects, wherein forming each of the two or more layers further includes forming a first metal-containing layer covering an upper surface of the dummy layer and the inner surfaces of the recess, the groove, and the through hole before forming the conductor layer.

[0023] According to yet another aspect of the present invention, there is provided the method for producing a multilayer wiring board according to the above aspect, wherein the first metal-containing layer contains titanium.

[0024] According to yet another aspect of the present invention, there is provided a method for manufacturing a multilayer wiring board according to any of the above aspects, wherein forming each of the two or more layers further includes forming a second metal-containing layer on the first metal-containing layer before forming the conductor layer, the second metal-containing layer being made of the same material as the conductor layer or made of a metal material having a smaller ionization tendency than the material of the conductor layer. [Brief description of the drawings]

[0025] [Figure 1] 1 is a schematic cross-sectional view of a packaged device according to an embodiment of the present invention; [Diagram 2] 2 is a cross-sectional view showing a schematic diagram of a multilayer wiring substrate included in the packaged device shown in FIG. 1; [Diagram 3] 3 is an enlarged cross-sectional view showing a portion of the multilayer wiring board shown in FIG. 2. [Figure 4] 3 is an enlarged cross-sectional view showing another part of the multilayer wiring board shown in FIG. 2. [Diagram 5] 1 is a cross-sectional view illustrating a process of a method for manufacturing a multilayer wiring board according to an embodiment of the present invention. [Figure 6] 6 is a cross-sectional view illustrating another step in the method for manufacturing a multilayer wiring board according to an embodiment of the present invention. [Figure 7] 11 is a cross-sectional view illustrating a process for producing a multilayer wiring board according to an embodiment of the present invention. FIG. [Figure 8] 11 is a cross-sectional view illustrating a process for producing a multilayer wiring board according to an embodiment of the present invention. FIG. [Figure 9] 11 is a cross-sectional view illustrating a process for producing a multilayer wiring board according to an embodiment of the present invention. FIG. [Figure 10] 11 is a cross-sectional view illustrating a process for producing a multilayer wiring board according to an embodiment of the present invention. FIG. [Figure 11] 11 is a cross-sectional view illustrating a process for producing a multilayer wiring board according to an embodiment of the present invention. FIG. [Figure 12]11 is a cross-sectional view illustrating a process for producing a multilayer wiring board according to an embodiment of the present invention. FIG. [Figure 13] 11 is a cross-sectional view illustrating a process for producing a multilayer wiring board according to an embodiment of the present invention. FIG. [Figure 14] 11 is a cross-sectional view illustrating a process for producing a multilayer wiring board according to an embodiment of the present invention. FIG. [Figure 15] 11 is a cross-sectional view illustrating a process for producing a multilayer wiring board according to an embodiment of the present invention. FIG. [Figure 16] 6 is a cross-sectional view illustrating another step in the method for manufacturing a multilayer wiring board according to an embodiment of the present invention. [Figure 17] 11 is a cross-sectional view illustrating a process for producing a multilayer wiring board according to an embodiment of the present invention. FIG. [Figure 18] 11 is a cross-sectional view illustrating a process for producing a multilayer wiring board according to an embodiment of the present invention. FIG. [Figure 19] 11 is a cross-sectional view illustrating a process for producing a multilayer wiring board according to an embodiment of the present invention. FIG. [Figure 20] 11 is a cross-sectional view illustrating a process for producing a multilayer wiring board according to an embodiment of the present invention. FIG. [Figure 21] 11 is a cross-sectional view illustrating a process for producing a multilayer wiring board according to an embodiment of the present invention. FIG. [Figure 22] 11 is a cross-sectional view illustrating a process for producing a multilayer wiring board according to an embodiment of the present invention. FIG. [Diagram 23] 11 is a cross-sectional view illustrating a process for producing a multilayer wiring board according to an embodiment of the present invention. FIG. [Figure 24] 11 is a cross-sectional view illustrating a process for producing a multilayer wiring board according to an embodiment of the present invention. FIG. [Diagram 25] 11 is a cross-sectional view illustrating a process for producing a multilayer wiring board according to an embodiment of the present invention. FIG. [Figure 26]6 is a cross-sectional view illustrating another step in the method for manufacturing a multilayer wiring board according to an embodiment of the present invention. [Figure 27] 11 is a cross-sectional view illustrating a process for producing a multilayer wiring board according to an embodiment of the present invention. FIG. [Figure 28] 11 is a cross-sectional view illustrating a process for producing a multilayer wiring board according to an embodiment of the present invention. FIG. [Figure 29] 11 is a cross-sectional view illustrating a process for producing a multilayer wiring board according to an embodiment of the present invention. FIG. [Diagram 30] 11 is a cross-sectional view illustrating a process for producing a multilayer wiring board according to an embodiment of the present invention. FIG. [Diagram 31] 11 is a cross-sectional view illustrating a process for producing a multilayer wiring board according to an embodiment of the present invention. FIG. [Diagram 32] 11 is a cross-sectional view illustrating a process for producing a multilayer wiring board according to an embodiment of the present invention. FIG. [Diagram 33] 11 is a cross-sectional view illustrating a process for producing a multilayer wiring board according to an embodiment of the present invention. FIG. [Diagram 34] 11 is a cross-sectional view illustrating a process for producing a multilayer wiring board according to an embodiment of the present invention. FIG. [Diagram 35] 11 is a cross-sectional view illustrating a process for producing a multilayer wiring board according to an embodiment of the present invention. FIG. [Diagram 36] 1A-1D are cross-sectional views illustrating schematic steps in a method for manufacturing a packaged device in accordance with an embodiment of the present invention. [Figure 37] 5A-5C are cross-sectional views illustrating schematic steps in a method for manufacturing a packaged device in accordance with an embodiment of the present invention. [Figure 38] 5A-5C are cross-sectional views illustrating schematic diagrams of yet other steps in a method for manufacturing a packaged device in accordance with an embodiment of the present invention. [Figure 39] FIG. 11 is a cross-sectional view illustrating a multilayer wiring board according to a comparative example. [Diagram 40] 40 is an enlarged cross-sectional view showing a portion of the multilayer wiring board shown in FIG. 39. [Diagram 41] 40 is an enlarged cross-sectional view showing another part of the multilayer wiring board shown in FIG. 39. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0026] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. The embodiment described below is a more specific embodiment of any of the above aspects. The embodiment described below shows an example of the technical idea of ​​the present invention, and does not limit the technical idea of ​​the present invention to the material, shape, structure, arrangement, etc. of the components described below. Various modifications can be made to the technical idea of ​​the present invention within the technical scope defined by the claims described in the claims.

[0027] In the drawings referred to in the following description, components having the same or similar functions are given the same reference numerals. It should be noted that the drawings are schematic, and the relationship between the dimension in the thickness direction and the dimension in the direction perpendicular to the thickness direction, i.e., the in-plane direction, and the relationship between the dimensions in the thickness direction of multiple layers, etc., may differ from the actual ones. Therefore, the specific dimensions should be determined with reference to the following description. It should also be noted that the dimensional relationship between two or more components may differ between multiple drawings. It should also be noted that the same structure is drawn upside down in some drawings compared to other drawings.

[0028] In this disclosure, the terms "upper surface" and "lower surface" refer to the two main surfaces of a plate-like member or a layer contained therein, i.e., the surface perpendicular to the thickness direction and having the widest area, and the back surface thereof, which are the surface shown at the top and the surface shown at the bottom in the drawings, respectively. Also, the term "side surface" refers to a surface perpendicular or inclined to the main surface.

[0029] In addition, in this disclosure, the phrase "AA on BB" is used regardless of the direction of gravity. The state specified by the phrase "AA on BB" includes a state in which AA is in contact with BB. The phrase "AA on BB" does not exclude the presence of one or more other components between AA and BB.

[0030] <Structure> FIG. 1 is a schematic cross-sectional view of a packaged device according to one embodiment of the present invention.

[0031] The packaged device 1 shown in FIG. 1 includes a composite wiring board 10, a functional device 20, a sealing resin layer 30, and a bonding electrode 40.

[0032] The functional device 20 is, for example, a semiconductor chip, or a chip in which circuits and elements are formed on a substrate made of a material other than a semiconductor, such as a glass substrate. Here, as an example, the functional device 20 is a semiconductor chip. That is, here, the packaged device 1 is a semiconductor package.

[0033] The packaged device 1 includes a plurality of functional devices 20. The packaged device 1 may include only one functional device 20.

[0034] The functional device 20 is bonded to the composite wiring board 10 via bonding electrodes 40. Here, the functional device 20 is bonded to the composite wiring board 10 by flip-chip bonding. One or more of the functional devices 20 may be bonded to the composite wiring board 10 by other bonding methods such as wire bonding.

[0035] The bonding electrodes 40 are arranged at a narrow pitch between the functional device 20 and the composite wiring board 10. The bonding electrodes 40 are made of, for example, solder. When the functional device 20 is bonded to the composite wiring board 10 by wire bonding, for example, a gold wire can be used to electrically connect the functional device 20 and the composite wiring board.

[0036] The sealing resin layer 30 includes a portion interposed between the functional device 20 and the composite wiring board 10 and a portion at least partially covering the side surface of the functional device 20. The sealing resin layer 30 fixes the functional device 20 to the composite wiring board 10.

[0037] The composite wiring board 10 includes an FC-BGA substrate 11, a multilayer wiring substrate 12, a sealing resin layer 13, and a bonding electrode 14.

[0038] The FC-BGA substrate 11 is an example of a first wiring substrate. The FC-BGA substrate 11 is joined to, for example, a motherboard (not shown).

[0039] The FC-BGA substrate 11 includes a core layer 111 , an insulating layer 112 , a conductor layer 113 , an insulating layer 114 , and a joining conductor 115 .

[0040] The core layer 111 is an insulating layer. The core layer 111 is, for example, a fiber-reinforced substrate in which a woven or nonwoven fabric is impregnated with a thermosetting insulating resin. For example, glass fiber, carbon fiber, or aramid fiber can be used as the woven or nonwoven fabric. For example, epoxy resin can be used as the insulating resin.

[0041] Through holes are provided in the core layer 111. Part of the conductor layer 113 covers the side walls of the through holes. Here, part of the conductor layer 113 covers the side walls of the through holes provided in the core layer 111 so as to generate through holes whose side walls are made of a conductor. These through holes whose side walls are made of a conductor may be filled with an insulator.

[0042] The remainder of the conductor layers 113 and the insulating layers 112 form multi-layer wiring structures on both major surfaces of the core layer 111. Each multi-layer wiring structure includes conductor layers 113 and insulating layers 112 stacked alternately.

[0043] Each of the insulating layers 112 included in the multilayer wiring structure is, for example, an insulating resin layer. The insulating layers 112 are provided with through holes.

[0044] The conductor layer 113 is made of a metal such as copper or an alloy, and may have a single-layer structure or a multi-layer structure.

[0045] Each conductor layer 113 included in the multilayer wiring structure includes a wiring portion and a land portion. The conductor layer 113 facing the core layer 111 with the insulating layer 112 sandwiched therebetween further includes a via portion covering the side wall of a through hole provided in the insulating layer 112.

[0046] An insulating layer 114 is provided on the multilayer wiring structure. The insulating layer 114 is, for example, an insulating resin layer such as a solder resist. The insulating layer 114 is provided with a through hole communicating with the conductor layer 113 located on the outermost surface of the multilayer wiring structure.

[0047] The joining conductor 115 is a metal bump provided on a portion of the conductor layer 113 that is exposed at the position of the through hole of the insulating layer 114. The joining conductor is also called a joining terminal. The joining conductor 115 is made of, for example, solder.

[0048] The multilayer wiring board 12 is a second wiring board. The multilayer wiring board 12 is bonded to the functional device 20 via a bonding electrode 40, and is bonded to the FC-BGA substrate 11 via a bonding electrode 14. That is, the multilayer wiring board 12 is an interposer that mediates the bonding between the functional device 20 and the FC-BGA substrate 11. The thickness of the multilayer wiring board 12 is, for example, in the range of 10 μm to 300 μm. The multilayer wiring board 12 will be described in detail later.

[0049] The bonding electrodes 14 are arranged between the multilayer wiring substrate 12 and the functional device 20. The pitch of the bonding electrodes 14 is wider than the pitch of the bonding electrodes 40 and narrower than the pitch of the bonding conductors 115 located on the lower surface of the FC-BGA substrate 11. The bonding electrodes 14 are made of, for example, solder.

[0050] The sealing resin layer 13 includes a portion interposed between the FC-BGA substrate 11 and the multilayer wiring substrate 12. The sealing resin layer 13 is also called an underfill layer. The sealing resin layer 13 fixes the multilayer wiring substrate 12 to the FC-BGA substrate 11.

[0051] The multilayer wiring board 12 will be described in more detail with reference to FIGS. Fig. 2 is a cross-sectional view showing a schematic diagram of a multilayer wiring board included in the packaged device shown in Fig. 1. Fig. 3 is a cross-sectional view showing an enlarged view of a part of the multilayer wiring board shown in Fig. 2. Fig. 4 is a cross-sectional view showing an enlarged view of another part of the multilayer wiring board shown in Fig. 2.

[0052] The multilayer wiring board 12 shown in Figures 2 to 4 includes two or more layers 120, an insulating resin layer 124, an insulating resin layer 121, a conductor layer 123, a conductor layer 126, an adhesion layer 125a, a seed layer 125b, a surface treatment layer 127, and an insulating resin layer 128, as shown in Figure 2.

[0053] Two or more layers 120 are stacked on top of each other. Here, two layers 120 are stacked. The number of layers 120 may be three or more.

[0054] Each of these layers 120 includes an insulating resin layer 1201, an inorganic insulating layer 1202, a conductor layer 1203, a first metal-containing layer 1204a, and a second metal-containing layer 1204b.

[0055] The insulating resin layer 1201 is formed integrally in the thickness direction. The insulating resin layer 1201 is preferably made of an insulating resin that does not contain a filler.

[0056] 2 to 4, the insulating resin layer 1201 has a first surface S1 and a second surface S2 which is the reverse surface of the first surface S1. The insulating resin layer 1201 is provided with a plurality of first recesses R1, a plurality of grooves G, and a plurality of second recesses R2.

[0057] The first recess R1 is open on the first surface S1. The first recess R1 is a land recess filled with a land portion 1203L, which will be described later.

[0058] The first recesses R1 have the same depth as each other. The depth of the first recesses R1 is smaller than the thickness of the insulating resin layer 1201.

[0059] One or more of the first recesses R1 communicate with one of the grooves G. In addition, one or more of the first recesses R1 communicate with a second recess R2 included in the insulating resin layer 1201 in which the first recesses R1 are provided.

[0060] The first recess R1 has an opening, a sidewall, and a bottom surface. The bottom surface of the first recess R1 is a plane perpendicular to the thickness direction. According to one example, the first recess R1 has a circular bottom surface, and the bottom surface of the first recess R1 that communicates with the second recess R2 opens in a circular shape.

[0061] Here, the first recess R1 has a shape in which the dimension in a direction perpendicular to the thickness direction gradually increases from the opening toward the bottom surface. That is, the first recess R1 has an inverse tapered cross section perpendicular to the thickness direction. According to one example, the first recess R1 has a truncated cone shape. The first recess R1 may have a rectangular cross section parallel to the thickness direction. That is, the first recess R1 may have a prismatic or cylindrical shape with the height direction parallel to the thickness direction.

[0062] The groove G is open to the first surface S1. The groove is filled with a wiring portion 1203W, which will be described later. The depth of the groove G is equal to the depth of the first recess R1.

[0063] The groove G has an opening, a sidewall, and a bottom surface. The bottom surface of the groove G is a flat surface perpendicular to the thickness direction.

[0064] The groove G has a shape in which the width gradually increases from the opening toward the bottom surface. That is, the groove G has an inverse tapered cross section perpendicular to the length direction. The groove G may have a rectangular cross section perpendicular to the length direction.

[0065] The second recess R2 is open to the second surface S2. The second recess R2 is a via recess filled with a via portion 1203V to be described later.

[0066] The second recesses R2 communicate with one or more of the first recesses R1. Specifically, each of the second recesses R2 communicates with one of the first recesses R1.

[0067] The second recess R2 has an opening and a side wall. The second recess R2 communicates with the first recess R1 at the bottom. The orthogonal projection of the second recess R2 onto a plane perpendicular to the thickness direction is surrounded by the contour of the orthogonal projection of the bottom surface of the first recess R1, which communicates with the second recess R2, onto the preceding plane.

[0068] The second recess R2 has a shape in which the dimension in a direction perpendicular to the thickness direction gradually increases from the opening to the bottom. That is, the second recess R2 has a cross section perpendicular to the thickness direction that is inversely tapered. According to one example, the second recess R2 has a truncated cone shape. The second recess R2 may have a cross section parallel to the thickness direction that is rectangular. That is, the second recess R2 may have a prismatic or cylindrical shape with the height direction parallel to the thickness direction. The first recess R1, the groove G, and the second recess R2 will be described in more detail later.

[0069] The inorganic insulating layer 1202 covers the first surface S1 of the insulating resin layer 1201. The inorganic insulating layer 1202 covering the first surface S1 of each insulating resin layer 1201 has a through hole at the position of the second recess R2 provided in the insulating resin layer adjacent to the previous insulating resin layer 1201 with the inorganic insulating layer 1202 sandwiched therebetween. Also, the inorganic insulating layer 1202 has a slit at the position of the groove portion G provided in the insulating resin layer 1201 whose first surface S1 it covers.

[0070] The conductor layer 1203 includes a land portion 1203L and a wiring portion 1203W in which the first recessed portion R1 and the groove portion G of the insulating resin layer 1201 are respectively filled, and a via portion 1203V protruding from the first surface S1 at the position of the land portion 1203L. In each conductor layer 1203, each of the via portions 1203V is formed integrally with one of the land portions 1203L included in the conductor layer 1203. The via portion 1203V of each conductor layer 1203 fills the second recessed portion R2 of the insulating resin layer 1201 in which the first recessed portion R1 and the groove portion G are respectively filled by the land portion 1203L and the wiring portion 1203W of the conductor layer 1203, and of another insulating resin layer adjacent to the insulating resin layer 1201 on the first surface S1 side.

[0071] The conductor layer 1203 is made of a metal such as copper or an alloy. The conductor layer 1203 may have a single-layer structure or a multi-layer structure. According to one example, the conductor layer 1203 is made of copper.

[0072] 2 to 4, the first metal-containing layer 1204a includes a portion covering the peripheral portion of the side and upper surface of the land portion 1203L, a portion covering the side and upper surface of the wiring portion 1203W, and a portion covering the side and upper surface of the via portion 1203V. That is, the first metal-containing layer 1204a is provided on the bottom surfaces and side walls of the first recess R1, the second recess R2, and the groove portion G.

[0073] First metal-containing layer 1204a is an adhesion layer or seed adhesion layer that improves adhesion of second metal-containing layer 1204b to dummy layer 2201 described below, thereby making peeling of second metal-containing layer 1204b unlikely to occur. According to one example, first metal-containing layer 1204a is a layer containing titanium, such as a titanium layer.

[0074] The second metal-containing layer 1204b is interposed between the first metal-containing layer 1204a and the conductor layer 1203. The second metal-containing layer 1204b is a seed layer that serves as a power supply layer in the formation of the conductor layer 1203 by electrolytic plating. The second metal-containing layer 1204b is made of, for example, the same material as the conductor layer 1203 or a metal material having a smaller ionization tendency than the material of the conductor layer 1203. In one example, the second metal-containing layer 1204b is made of copper. Even if the two layers stacked on top of each other are made of the same material, the interface between the layers can be confirmed by observing a cross section parallel to the stacking direction with, for example, a scanning electron microscope.

[0075] 2, the insulating resin layer 124 is provided on one main surface of the multilayer wiring structure made up of the layer 120. The material of the insulating resin layer 124 may be the same as or different from the material of the insulating resin layer 1201.

[0076] The insulating resin layer 124 has a through hole at the position of the via portion 1203V of the insulating resin layer 1201 included in the adjacent layer 120. The through hole of the insulating resin layer 124 is filled with the via portion 1203V of the insulating resin layer 1201 included in the adjacent layer 120.

[0077] The through holes of the insulating resin layer 124 are recesses that open on the layer 120 side. These recesses here have a shape in which the dimension in a direction perpendicular to the thickness direction gradually decreases from the bottom to the top. That is, the recesses of the insulating resin layer 124 here have a forward tapered cross section perpendicular to the thickness direction. According to one example, these through holes have a truncated cone shape. These through holes (or recesses) may have a rectangular cross section parallel to the thickness direction. That is, these through holes may have a prismatic or cylindrical shape with the height direction parallel to the thickness direction.

[0078] The insulating resin layer 121 is provided on the insulating resin layer 124. The material of the insulating resin layer 121 may be the same as or different from the materials of the insulating resin layers 124 and 1201. The insulating resin layer 121 has a through hole at the position of the through hole of the insulating resin layer 124.

[0079] The conductor layer 123 fills the through holes of the insulating resin layer 121. The conductor layer 123 is an electrode for bonding the multilayer wiring board 12 and the functional device 20. The conductor layer 123 is made of, for example, copper.

[0080] The conductor layer 126 fills the second recess R2 of the insulating resin layer 1201 contained in the underlying layer 120, and covers the opening of the second recess R2 and its surrounding area on the second surface S2 of the insulating resin layer 1201. The conductor layer 126 is made of a metal such as copper or an alloy.

[0081] The adhesion layer 125a includes a portion covering the inner surface of the second recess R2 of the insulating resin layer 1201 included in the underlying layer 120, and a portion covering the area around the opening of the second recess R2 on the second surface S2 of the insulating resin layer 1201. The adhesion layer 125a is a layer that improves adhesion of the seed layer 125b to the insulating resin layer 1201 and makes the seed layer 125b less likely to peel off.

[0082] The seed layer 125b is provided on the adhesion layer 125a and serves as a power supply layer when the conductor layer 126 is formed by electrolytic plating.

[0083] The insulating resin layer 128 is provided on the insulating resin layer 1201 and the conductor layer 126 included in the layer 120 located below. The insulating resin layer 128 has a through hole at the position of the conductor layer 126.

[0084] The surface treatment layer 127 is provided on the portion of the conductor layer 126 that is exposed in the through hole of the insulating resin layer 128. The surface treatment layer 127 is provided to prevent oxidation of the surface of the conductor layer 126 and to improve wettability with solder.

[0085] <Manufacturing method> The multilayer wiring board 12 included in this packaged device 1 can be manufactured, for example, by the following method.

[0086] 5 to 35 are cross-sectional views that roughly show a method for manufacturing a multilayer wiring board according to one embodiment of the present invention.

[0087] In this method, first, a release layer 3 is formed on one surface of a support 2 as shown in FIG.

[0088] Since light may be irradiated to the peeling layer 3 through the support 2, it is advantageous for the support 2 to have light transmissivity. For example, a glass plate can be used as the support 2. A rectangular glass plate is suitable for large size. In addition, the glass plate can achieve excellent flatness and high rigidity. Therefore, the glass plate as the support 2 is suitable for forming a fine pattern thereon.

[0089] In addition, since a glass plate has a small coefficient of thermal expansion (CTE) and is not easily distorted, it is excellent in ensuring pattern arrangement accuracy and flatness. When a glass plate is used as the support 2, the thickness of the glass plate is preferably thicker in order to suppress the occurrence of warping in the manufacturing process, and is, for example, 0.5 mm or more, preferably 1.2 mm or more.

[0090] The CTE of the glass plate is preferably 3 ppm or more and 15 ppm or less, and from the viewpoint of compatibility with the CTE of the FC-BGA substrate 11 and the functional device 20, it is more preferably about 10 ppm.

[0091] The glass plate may be made of, for example, quartz glass, borosilicate glass, alkali-free glass, soda glass, or sapphire glass.

[0092] On the other hand, in cases where light transmittance is not required for the support 2 when peeling off the support 2, for example, when a resin that foams when heated is used for the peel-off layer 3, a material with less distortion, such as metal or ceramics, can be used for the support 2.

[0093] In the following, as an example, it is assumed that the material of the peelable layer 3 is a resin that absorbs ultraviolet light (UV light) and becomes peelable, and the support 2 is a glass plate.

[0094] The release layer 3 may be, for example, a resin that becomes peelable by absorbing light such as UV light and generating heat or changing its properties, or a resin that becomes peelable by foaming due to heat. The material of the release layer 3 may be selected from organic resins such as epoxy resin, polyimide resin, polyurethane resin, silicone resin, polyester resin, oxetane resin, maleimide resin, and acrylic resin, and inorganic materials such as amorphous silicon, gallium nitride, and metal oxide. The release layer 3 may further contain additives such as a photodecomposition promoter, a light absorber, a sensitizer, and a filler.

[0095] The release layer 3 may have a single-layer structure or a multilayer structure. For example, a protective layer may be provided on the release layer 3 for the purpose of protecting the multilayer wiring structure formed on the support 2, and a layer for improving the adhesion between the support 2 and the release layer 3 may be further provided. A laser light reflecting layer or a metal layer may be further provided between the release layer 3 and the multilayer wiring structure.

[0096] In addition, when the material of the peeling layer 3 is a resin that can be peeled off by light such as UV light, for example laser light, if the support 2 is translucent, the peeling layer 3 may be irradiated with light through the support 2.

[0097] 6 are formed in a vacuum. The adhesion layer 122a is a layer that improves the adhesion of the seed layer 122b to the peeling layer 3 and prevents peeling of the seed layer 122b in the subsequent steps. The seed layer 122b also serves as a power supply layer in electrolytic plating for forming the conductor layer 123.

[0098] The adhesion layer 122a and the seed layer 122b can be formed by, for example, a sputtering method or a vapor deposition method. Examples of materials for the adhesion layer 122a and the seed layer 122b include Cu, Ni, Al, Ti, Cr, Mo, W, Ta, Au, Ir, Ru, Pd, Pt, AlSi, AlSiCu, AlCu, NiFe, ITO (Indium Tin Oxide), IZO (Indium Zinc Oxide), AZO (Aluminum-doped Zinc Oxide), ZnO, PZT (Lead Zirconate Titanate), TiN, Cu 3 N 4 , Cu alloy, or a combination of two or more of these can be used. In this example, taking into consideration the electrical characteristics, ease of manufacture, and cost, a titanium layer and a copper layer are adopted for the adhesion layer 122a and the seed layer 122b, respectively, and they are formed by a sputtering method.

[0099] The total thickness of the adhesion layer 122a and the seed layer 122b is preferably 1 μm or less. In this example, a titanium layer having a thickness of 50 nm is formed as the adhesion layer 122a, and a copper layer having a thickness of 300 nm is formed as the seed layer 122b.

[0100] Next, as shown in FIG. 7, a resist layer 221 is provided on the seed layer 122b. The resist layer 221 is made of a photosensitive resin. As the photosensitive resin, for example, a photosensitive polyimide resin, a photosensitive benzocyclobutene resin, a photosensitive epoxy resin, or a modified product thereof can be used. The photosensitive resin may be in a liquid form or a film form.

[0101] When a liquid photosensitive resin is used as the material of the resist layer 221, the resist layer 221 can be formed on the seed layer 122b by, for example, any of slit coating, curtain coating, die coating, spray coating, electrostatic coating, inkjet coating, gravure coating, screen printing, gravure offset printing, spin coating, and doctor coating. When a film-like photosensitive resin is used for the resist layer 221, the resist layer 221 can be provided on the seed layer 122b by, for example, any of lamination, vacuum lamination, and vacuum pressing.

[0102] Next, through holes are formed in the resist layer 221 by photolithography. The shape of the through holes in a plan view is set according to the pitch and shape of the bonding electrodes of the functional device 20. Here, as an example, the through holes have a circular opening with a diameter of 25 μm and a pitch of 55 μm. Here, plan view refers to observing the object in the thickness direction, that is, observing the orthogonal projection of the object onto a plane perpendicular to the thickness direction.

[0103] The thickness of the resist layer 221 is set according to the thickness of the conductor layer 123 to be formed next. Here, as an example, the thickness of the resist layer 221 is set to 8 μm.

[0104] After these through holes are formed, a plasma treatment may be carried out in order to remove residues remaining after development.

[0105] 8, a conductor layer 123 is formed on the seed layer 122b by electrolytic plating. The conductor layer 123 constitutes an electrode for bonding to the functional device 20. Examples of electrolytic plating for forming the conductor layer 123 include electrolytic nickel plating, electrolytic copper plating, electrolytic chromium plating, electrolytic Pd plating, electrolytic gold plating, electrolytic rhodium plating, and electrolytic iridium plating. Among these, electrolytic copper plating is preferable because it is simple, inexpensive, and can achieve good electrical conductivity.

[0106] As described above, the conductor layer 123 serves as an electrode for bonding to the functional device 20. Therefore, the thickness of the conductor layer 123 is desirably 1 μm or more from the viewpoint of solder bonding, and desirably 30 μm or less from the viewpoint of productivity.

[0107] 9, the resist layer 221 is removed. The resist layer 221 is removed by, for example, a dry etching method, or is dissolved or peeled off by immersing in an alkaline solution or solvent.

[0108] 10, an insulating resin layer 121 is formed so as to embed the conductor layer 123. The material of the insulating resin layer 121 may be a photosensitive resin or a non-photosensitive resin. The material of the insulating resin layer 121 may be the same as or different from the material of the insulating resin layers 124, 128, and 1201 described below.

[0109] 11, the upper surface of the conductor layer 123 is exposed by physical polishing, or by physical polishing and surface polishing such as CMP processing. The structure obtained in this manner can also be obtained by a damascene process.

[0110] 12, an insulating resin layer 124 having a through hole at the position of the conductor layer 123 is provided on the conductor layer 123 and the insulating resin layer 121. The through hole of the insulating resin layer 124 is a second recess R2 that opens on the second surface of the insulating resin layer 124, here, the upper surface of the insulating resin layer 124. The second recess R2 may be formed so that its cross section has a rectangular shape, but is preferably formed in a forward tapered shape. Forming the second recess R2 in a forward tapered shape makes it easier to form the first metal-containing layer 1204a and the second metal-containing layer 1204b without generating discontinuous portions in the second recess R2.

[0111] The insulating resin layer 124 is made of, for example, a photosensitive resin. As the photosensitive resin, for example, the same material as described above for the resist layer 221 can be used. In addition, the insulating resin layer 124 having the through holes can be formed by, for example, the same method as described above for the resist layer 221.

[0112] Alternatively, the insulating resin layer 124 is made of a non-photosensitive resin. For example, polyimide resin, benzocyclobutene resin, epoxy resin, or modified products thereof can be used as the non-photosensitive resin. Non-photosensitive resins such as polyimide have excellent insulating properties and mechanical properties, and can also achieve high heat resistance. In addition, inorganic particles such as silica, alumina, and zirconia may be added to the non-photosensitive resin as a filler. Here, as an example, a non-photosensitive polyimide resin is used as the non-photosensitive resin.

[0113] The non-photosensitive resin may be in the form of a liquid or a film.

[0114] When a liquid non-photosensitive resin is used, the insulating resin layer 124 can be formed by a method selected from, for example, slit coating, curtain coating, die coating, spray coating, electrostatic coating, inkjet coating, gravure coating, screen printing, gravure offset printing, spin coating, and doctor coating.

[0115] When a film-like non-photosensitive resin is provided as the insulating resin layer 124, lamination, vacuum lamination, vacuum pressing, or the like can be applied.

[0116] Here, as an example, a photosensitive epoxy resin is applied onto the conductor layer 123 and the insulating resin layer 121 by a spin coating method. The photosensitive epoxy resin can be cured at a relatively low temperature and shrinks little when cured, which is advantageous for the subsequent formation of a fine pattern. Here, as an example, the insulating resin layer 124 is formed to a thickness of 2 μm.

[0117] After the insulating resin layer 124 is formed, the surface may be subjected to physical polishing or may be subjected to both physical polishing and polishing such as CMP in order to flatten the surface.

[0118] 13, the inorganic insulating layer 1202 is formed on the insulating resin layer 124 and the conductor layer 123. The inorganic insulating layer 1202 is formed so as to cover the upper surface of the insulating resin layer 124 and the inner surface of the second recess R2.

[0119] The inorganic insulating layer 1202 is formed by, for example, plasma CVD (Chemical Vapor Deposition) and is made of, for example, one or more insulators selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride, silicon oxide doped with fluorine, and silicon oxide doped with carbon.

[0120] The thickness of the inorganic insulating layer 1202 is preferably 50 nm or more, and more preferably 100 nm or more. If the inorganic insulating layer 1202 is made thin, it is more likely to produce discontinuities such as pinholes. The thickness of the inorganic insulating layer 1202 is preferably 1000 nm or less, and more preferably 500 nm or less. If the inorganic insulating layer 1202 is made thicker, it will take longer to form the layer or to partially remove it by etching, for example.

[0121] 14, a dummy layer 2201 having a groove G' and through holes R1', one or more of which communicate with the second recesses R2, is formed on the inorganic insulating layer 1202. The groove G' and through holes R1' of the dummy layer 2201 correspond to the groove portion G and the first recesses R1 of the insulating resin layer 1201, respectively.

[0122] The dummy layer 2201 is made of a photosensitive resin. For example, the same material as that described above for the resist layer 221 can be used as the photosensitive resin. The dummy layer 2201 having the groove G' and the through hole R1' can be formed by the same method as that described above for the resist layer 221.

[0123] The through hole R1' in the dummy layer 2201 is formed so that the opening diameter at the top surface thereof is larger than the opening diameter at the top surface of the through hole in the insulating resin layer 124. The through hole R1' is formed in a forward tapered shape. The groove G' is also formed so that the cross section perpendicular to the length direction has a forward tapered shape.

[0124] Groove G' and through hole R1' may be formed to have a rectangular cross section, but forming them in a forward tapered shape makes it easier to form first metal-containing layer 1204a and second metal-containing layer 1204b without creating discontinuities within groove G' and through hole R1'.

[0125] Furthermore, when the groove G' and the through hole R1' are formed to have a cross section with a forward tapered shape, the contact area between the insulating resin layer 1201 and the inorganic insulating layer 1202 is larger than when the cross section is rectangular without changing the cross-sectional area. Therefore, the adhesion between the insulating resin layer 1201 and the inorganic insulating layer 1202 can be improved. Similarly, the adhesion between the insulating resin layer 1201 and the conductor layer 1203 can also be improved. Therefore, delamination can be made less likely to occur.

[0126] 15, the portions of the inorganic insulating layer 1202 exposed in the second recess R2, the portions exposed in the groove G', and the portions exposed in the through hole R1' are removed. This removal is performed by, for example, dry etching using the dummy layer 2201 as a mask.

[0127] 16, a first metal-containing layer 1204a is formed to cover the upper surface of the dummy layer 2201, the inner surface of the second recess R2, the inner surface of the groove G', and the inner surface of the through hole R1'. Subsequently, a second metal-containing layer 1204b made of the same material as the conductor layer 1203 or made of a metal material having a smaller ionization tendency than the material of the conductor layer 1203 is formed on the first metal-containing layer 1204a.

[0128] The first metal-containing layer 1204a and the second metal-containing layer 1204b are a seed adhesion layer (or adhesion layer) and a seed layer, respectively. The first metal-containing layer 1204a and the second metal-containing layer 1204b can be made of the same materials as those described above for the adhesion layer 122a and the seed layer 122b, respectively. The first metal-containing layer 1204a and the second metal-containing layer 1204b can be formed by the same methods as those described above for the adhesion layer 122a and the seed layer 122b, respectively.

[0129] As an example, a titanium layer having a thickness of 50 nm is formed as the first metal-containing layer 1204a, and a copper layer having a thickness of 300 nm is formed as the second metal-containing layer 1204b. A layer containing another metal may be interposed between the titanium layer and the copper layer. The titanium layer may be oxidized. That is, the first metal-containing layer 1204a may be a titanium oxide layer.

[0130] Next, as shown in Fig. 17, a conductor layer 1203 is formed on the second metal-containing layer 1204b. The conductor layer 1203 is formed so as to fill the second recess R2, the groove G', and the through hole R1'. The conductor layer 1203 can be formed by the same method as described above for the conductor layer 123. Here, as an example, the conductor layer 1203 is a copper layer formed by electrolytic plating.

[0131] 18, the conductor layer 1203, the second metal-containing layer 1204b, and the first metal-containing layer 1204a are subjected to physical polishing, CMP, or other polishing to remove the portions of the conductor layer 1203, the second metal-containing layer 1204b, and the first metal-containing layer 1204a that are located outside the second recess R2, the groove G', or the through hole R1'. Note that this polishing may also remove a portion near the top surface of the dummy layer 2201.

[0132] In this manner, the portion of the conductor layer 1203 in which the second recess R2 is filled, the portion in which the through hole R1' is filled, and the portion in which the groove G' is filled are obtained as the via portion 1203V, the land portion 1203L, and the wiring portion 1203W, respectively.

[0133] 19, the dummy layer 2201 is removed. The dummy layer 2201 can be removed by dry etching or by immersion in an alkaline solution or solvent.

[0134] Next, as shown in FIG. 20, an insulating resin layer 1201 is provided to cover the conductor layer 1203 and fill the gap between the land portion 1203L and the wiring portion 1203W. A through hole is formed in the insulating resin layer 1201 as the second recess R2. The lower and upper surfaces of the insulating resin layer 1201 are the first surface S1 and the second surface S2, respectively. The recess of the insulating resin layer 1201 filled with the land portion 1203L is the first recess R1 described above. The recess of the insulating resin layer 1201 filled with the wiring portion 1203W is the groove portion G described above.

[0135] The insulating resin layer 1201 is made of a photosensitive resin or a non-photosensitive resin. For example, the same materials as those described above for the resist layer 221 and the insulating resin layer 124 can be used as the photosensitive resin or the non-photosensitive resin. The insulating resin layer 1201 having the first recess R1, the second recess R2, and the groove G can be formed by the same method as those described above for the resist layer 221 and the insulating resin layer 124.

[0136] Prior to forming the insulating resin layer 1201, a layer made of a silane coupling agent may be formed on the inorganic insulating layer 1202 and the first metal-containing layer 1204a. By providing a layer made of a silane coupling agent, the adhesion between the insulating resin layer 1201 and the inorganic insulating layer 1202 and the first metal-containing layer 1204a is improved. When the adhesion is improved, even if the multilayer wiring board 12 is warped due to, for example, heat, delamination between the conductor layer 1203 and the insulating resin layer 1201 and delamination between the inorganic insulating layer 1202 and the insulating resin layer 1201 are unlikely to occur.

[0137] In this manner, layer 120 is obtained, which includes insulating resin layer 1201, inorganic insulating layer 1202, conductor layer 1203, first metal-containing layer 1204a, and second metal-containing layer 1204b.

[0138] Thereafter, the sequence consisting of the steps described with reference to Figures 13 to 20 is repeated. As a result, the structures shown in Figures 21 to 28 are obtained in sequence. That is, a multilayer wiring structure including two layers 120 is obtained. Note that by repeating the above sequence one or more times, the number of layers 120 included in the multilayer wiring structure can be increased to three or more.

[0139] 29, an adhesive layer 125a is formed to cover the upper surface of the insulating resin layer 1201 included in the upper layer 120 and the inner surface of the first recess R1. Then, a seed layer 125b made of the same material as the conductor layer 126 or made of a metal material having a smaller ionization tendency than the material of the conductor layer 126 is formed on the adhesive layer 125a.

[0140] The adhesion layer 125a and the seed layer 125b can be formed using the same materials as those described above for the adhesion layer 122a and the seed layer 122b, respectively. Also, the adhesion layer 125a and the seed layer 125b can be formed by the same methods as those described above for the adhesion layer 122a and the seed layer 122b, respectively.

[0141] 30, a resist layer 228 having through holes is formed on the seed layer 125b. Each of the through holes of the resist layer 228 communicates with a first recess R1 provided in the insulating resin layer 1201 included in the upper layer 120.

[0142] The resist layer 228 is made of a photosensitive resin. For example, the same material as described above for the resist layer 221 can be used as the photosensitive resin. The resist layer 228 having the through holes can be formed by the same method as described above for the resist layer 221.

[0143] 31, the conductor layer 126 is formed on the seed layer 125b. The conductor layer 126 can be formed, for example, by the same method as that described above for the conductor layer 123.

[0144] 32, the resist layer 228 is removed. The resist layer 228 can be removed, for example, by a method similar to that described above for the resist layer 221.

[0145] 33, the exposed portions of the adhesion layer 125a and the seed layer 125b are removed. The exposed portions of the adhesion layer 125a and the seed layer 125b are removed by, for example, etching using the conductor layer 126 as an etching mask.

[0146] 34, an insulating resin layer 128 is formed on the insulating resin layer 1201 and the conductor layer 126. The insulating resin layer 128 has a through hole at the position of the conductor layer 126. The insulating resin layer can be formed, for example, by providing a solder resist on the insulating resin layer 1201 and the conductor layer 126, and subjecting it to exposure and development. Note that an insulating layer obtained from a solder resist is also called a solder resist layer.

[0147] The material of the solder resist may be, for example, an insulating resin such as an epoxy resin or an acrylic resin. In this example, a photosensitive epoxy resin containing a filler is used as the solder resist.

[0148] 35, a surface treatment layer 127 is provided on the conductor layer 126. The surface treatment layer 127 is provided for the purpose of preventing oxidation of the surface of the conductor layer 126 and improving wettability to solder. Here, as an example, an electroless Ni / Pd / Au plating layer is formed as the surface treatment layer 127.

[0149] An OSP (Organic Solderability Preservative) film, that is, a surface treatment layer made of a water-soluble preflux, may be formed as the surface treatment layer 127. Alternatively, an electroless tin plating layer or an electroless Ni / Au plating layer may be formed as the surface treatment layer 127.

[0150] Next, a bonding conductor 129 is formed on the surface treatment layer 127. The bonding conductor 129 is, for example, a metal bump such as a solder bump. The bonding conductor 129 can be formed, for example, by placing a solder material such as a solder ball on the surface treatment layer 127, melting it, and then cooling it to adhere to the surface treatment layer 127.

[0151] In this manner, a multilayer wiring board 12 supported by the support 2, that is, a multilayer wiring board with a support, is obtained.

[0152] By using the thus obtained multilayer wiring board with a support, the packaged device 1 shown in FIG. 1 can be manufactured, for example, by the following method.

[0153] Figure 36 is a cross-sectional view showing a schematic step in a method for manufacturing a packaged device according to an embodiment of the present invention, Figure 37 is a cross-sectional view showing another step in a method for manufacturing a packaged device according to an embodiment of the present invention, and Figure 38 is a cross-sectional view showing a schematic step in a method for manufacturing a packaged device according to an embodiment of the present invention.

[0154] 36, the multilayer wiring board 12 and the FC-BGA board 11 supported by the support body 2 are bonded together. Then, the bonded portion is sealed with the sealing resin layer 13 shown in FIG.

[0155] The material of the sealing resin layer 13 may be, for example, a mixture of a resin and a filler. The resin may be, for example, one of epoxy resin, urethane resin, silicone resin, polyester resin, oxetane resin, and maleimide resin, or a mixture of two or more of these resins. The filler may be, for example, one of silica, titanium oxide, aluminum oxide, magnesium oxide, and zinc oxide, or two or more of these. The sealing resin layer 13 may be formed, for example, by filling a liquid material between the FC-BGA substrate 11 and the multilayer wiring substrate 12.

[0156] In this manner, a composite wiring board 10 is obtained that includes the FC-BGA substrate 11 and the multilayer wiring board 12. At this point, the support body 2 remains provided on the multilayer wiring board 12.

[0157] Next, as shown in Fig. 37, the release layer 3 is irradiated with laser light LB from the support 2 side, and the support 2 and the composite wiring board 10 are peeled off from each other as shown in Fig. 38. If the release layer 3 remains on the composite wiring board 10, it is removed by, for example, etching. In addition, the adhesion layer 122a and the seed layer 122b are also removed by, for example, etching.

[0158] Thereafter, the functional device 20 shown in FIG. Prior to bonding of the functional device 20, a surface treatment layer such as an electroless Ni / Pd / Au plating layer, an OSP film, an electroless tin plating layer, or an electroless Ni / Au plating layer may be provided on the conductor layer 123 exposed on the surface for the purpose of preventing oxidation and improving wettability to solder.

[0159] Next, the joints are sealed with a sealing resin layer 30 . As the material of the sealing resin layer 30, for example, the materials exemplified as the materials of the sealing resin layer 13 can be used. The sealing resin layer 30 can be formed, for example, by the same method as that described above for the sealing resin layer 13. In this manner, the packaged device 1 shown in FIG. 1 is completed.

[0160] In the above method, the multilayer wiring board 12 is bonded to the FC-BGA substrate 11, and then the functional device 20 is bonded to the multilayer wiring board 12. Alternatively, the functional device 20 may be bonded to the multilayer wiring board 12, and then the multilayer wiring board 12 may be bonded to the FC-BGA substrate 11.

[0161] <Effects> Interposers obtained by silicon interposer technology, so-called silicon interposers, are manufactured using silicon wafers and equipment for semiconductor front-end processing. Silicon wafers are limited in shape and size, and the number of interposers that can be manufactured from one wafer is not necessarily large. In addition, the manufacturing equipment is expensive. Therefore, silicon interposers are expensive. In addition, because silicon wafers are semiconductors, there is also the problem that the transmission characteristics deteriorate when silicon interposers are used.

[0162] No silicon wafer is required to manufacture the multilayer wiring board 12. Furthermore, in the multilayer wiring board 12, many of the insulating layers can be insulating resin layers. Therefore, the multilayer wiring board 12 can be manufactured using inexpensive materials and equipment, making it possible to reduce costs and also achieving excellent transmission characteristics.

[0163] The method of directly fabricating a multi-layer wiring structure including a conductor layer with a fine wiring pattern on an FC-BGA substrate has little degradation of the transmission characteristics seen in silicon interposers. However, this method has issues with the manufacturing yield of the FC-BGA substrate itself and the difficulty of forming a multi-layer wiring structure including a conductor layer with a fine wiring pattern on a core layer such as a glass epoxy substrate, resulting in a low manufacturing yield overall. Furthermore, it is difficult to achieve high symmetry with this FC-BGA substrate with respect to the plane that bisects its thickness. Therefore, such FC-BGA substrates are prone to warping and distortion when heated.

[0164] In manufacturing the above-mentioned composite wiring board 10 and packaged device 1, multilayer wiring board 12 is manufactured separately from FC-BGA substrate 11, and they are bonded to each other. A multilayer wiring structure including conductor layer 1203 having a fine wiring pattern is not formed in FC-BGA substrate 11, but is formed in multilayer wiring board 12. Therefore, the above-mentioned composite wiring board 10 and packaged device 1 can be manufactured with a high yield.

[0165] Furthermore, in the manufacture of composite wiring board 10, the multilayer wiring structure including conductor layer 1203 having a fine wiring pattern is formed on support 2, rather than on a core layer such as a glass epoxy board. Since a support having excellent smoothness can be used as support 2, fine patterns and the like formed thereon can be formed with high shape accuracy. For these reasons as well, the above-mentioned composite wiring board 10 and packaged device 1 can be manufactured with a high yield.

[0166] In addition, in the above-described composite wiring board 10 and packaged device 1, it is easy to achieve a high degree of symmetry with respect to a plane that bisects the thickness of FC-BGA substrate 11, and it is also easy to achieve a high degree of symmetry with respect to a plane that bisects the thickness of multilayer wiring substrate 12. Therefore, the above-described composite wiring board 10 and packaged device 1 are less likely to warp or distort when heated.

[0167] In the semi-additive method, the first metal-containing layer 1204a and the second metal-containing layer 1204b are patterned by etching using the land portion 1203L and the wiring portion 1203W as a mask. Therefore, in the semi-additive method, the surfaces of the land portion 1203L and the wiring portion 1203W are damaged by this etching. That is, the surface roughness increases. When the surfaces of the land portion 1203L and the wiring portion 1203W, especially the surface roughness of the wiring portion 1203W, become large, the transmission characteristics decrease.

[0168] In contrast, in the manufacture of the multilayer wiring board 12 described above, recesses and grooves are provided in the base layer composed of a dummy layer and an insulating resin layer, and the first metal-containing layer 1204a, the second metal-containing layer 1204b, and the conductor layer 1203 are sequentially formed on the upper surface of the base layer and the inner surfaces of the recesses and grooves. Then, by removing the portions located outside the recesses and grooves among these layers by polishing, the via portion 1203V, the land portion 1203L, and the wiring portion 1203W are formed. That is, in the manufacture of the multilayer wiring board 12 described above, etching for patterning the first metal-containing layer 1204a and the second metal-containing layer 1204b is not performed. Therefore, the surfaces of the via portion 1203V, the land portion 1203L, and the wiring portion 1203W are not damaged by this etching, and they have smooth surfaces. Therefore, the multilayer wiring board 12 described above can achieve excellent transmission characteristics.

[0169] Also, in the multilayer wiring board 12 described above, each of the layers 120 includes an inorganic insulating layer 1202. When the inorganic insulating layer 1202 is provided, damage to the insulating resin layer 124 due to etching for removing the dummy layer 2201 can be reduced. Also, when the inorganic insulating layer 1202 is provided, the rigidity of the multilayer wiring board 12 is increased, and warping and bending are less likely to occur.

[0170] And the inorganic insulating layer 1202 makes it difficult for metal diffusion to occur between the insulating resin layers. Therefore, the multilayer wiring board 12 described above can achieve excellent insulation reliability.

[0171] Furthermore, in the multilayer wiring board 12 described above, the side surfaces and the lower surfaces of the via portion 1203V, the land portion 1203L, and the wiring portion 1203W are covered with the first metal-containing layer 1204a and the second metal-containing layer 1204b. The first metal-containing layer 1204a and the second metal-containing layer 1204b suppress the diffusion of metal from the conductor layer 1203 to the insulating resin layer 1201 and the like. Therefore, for such reasons as well, the multilayer wiring board 12 described above can achieve excellent insulation reliability.

[0172] <Verification of Effects> The effects exhibited by the multilayer wiring board 12 described above were verified by the method described below.

[0173] (Example) The multilayer wiring board 12 described with reference to Figures 2 to 4 was manufactured by the method described with reference to Figures 5 to 35. Here, the wiring rule was L / S=2 μm / 2 μm.

[0174] (Comparative Example) Fig. 39 is a cross-sectional view showing a schematic configuration of a multilayer wiring board according to a comparative example, Fig. 40 is a cross-sectional view showing an enlarged view of a portion of the multilayer wiring board shown in Fig. 39, and Fig. 41 is a cross-sectional view showing an enlarged view of another portion of the multilayer wiring board shown in Fig. 39.

[0175] The multilayer wiring board 12' shown in FIGS. 39 to 41 is similar to the multilayer wiring board 12 according to the embodiment, except for the following points.

[0176] That is, the multilayer wiring board 12' includes a layer 120' instead of the layer 120. Each layer 120' includes an insulating resin layer 1201, a first metal-containing layer 1204a, and a second metal-containing layer 1204b, but does not include an inorganic insulating layer 1202. Since the conventional semi-additive method was used to form the first metal-containing layer 1204a, the second metal-containing layer 1204b, and the conductor layer 1203, the side surfaces of the land portion 1203L and the wiring portion 1203W are not covered by the first metal-containing layer 1204a and the second metal-containing layer 1204b. Furthermore, the cross sections of the land portion 1203L and the wiring portion 1203W have a substantially rectangular shape. Except for these points, the multilayer wiring board 12' according to the comparative example is similar to the multilayer wiring board 12 according to the embodiment.

[0177] (test) The evaluation was performed under a bias of 3.3 V and an environment of 130°C / 85% RH. After 192 hours under this bias and environment, the resistance value was 10 6 The pass condition was a resistance of Ω or more. For each of the examples and comparative examples, the number of evaluations was N=10.

[0178] As a result, insulation failure was confirmed in all of the multilayer wiring boards 12' according to the comparative example at the time point of 96 hours. On the other hand, the resistance value after 192 hours for all of the multilayer wiring boards 12 according to the example was 10 6 Ω or more, indicating good insulation reliability. The invention as originally claimed is set forth below. [1] The laminated ... an insulating resin layer having a first surface and a second surface which is the reverse surface of the first surface, the insulating resin layer being integrally formed in a thickness direction with a first recess opening on the first surface, a groove opening on the first surface, and a second recess opening on the second surface and communicating with at least one of the first recesses; an inorganic insulating layer covering the first surface; The insulating resin layer includes a land portion and a wiring portion, which are formed by respectively filling the first recess and the groove portion, and a via portion protruding from the first surface at the position of the land portion, and the via portion is a conductor layer that fills a recess of another insulating resin layer adjacent to the first surface side. A multilayer wiring board including: [2] Item 2. The multilayer wiring board according to item 1, wherein the inorganic insulating layer contains one or more insulators selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride, silicon oxide doped with fluorine, and silicon oxide doped with carbon. [3] 3. The multilayer wiring board according to item 1 or 2, wherein each of the two or more layers further includes a first metal-containing layer that covers the peripheral edge of the land portion, the side surfaces of the wiring portion and the via portion, the surface of the wiring portion facing the opening of the groove portion, and the surface of the land portion facing the first surface. [4] 4. The multilayer wiring board according to item 3, wherein the first metal-containing layer contains titanium. [5] 5. The multilayer wiring board according to item 3 or 4, wherein each of the two or more layers further includes a second metal-containing layer interposed between the first metal-containing layer and the conductor layer and made of the same material as the conductor layer or made of a metal material having a smaller ionization tendency than the material of the conductor layer. [6] 6. The multilayer wiring board according to any one of items 1 to 5, wherein the first recess and the groove have a reverse tapered cross section, and the second recess has a forward tapered cross section. [7] A composite wiring board comprising a first wiring board and a second wiring board bonded to the first wiring board, the first and second wiring boards being electrically connected to each other via a bonding electrode interposed between them, and the second wiring board being a multilayer wiring board as described in any one of items 1 to 6. [8] 8. The composite wiring board according to item 7, wherein the first wiring board is a wiring board for a flip chip ball grid array, and the second wiring board is an interposer. [9] Item 7 or 8, and the composite wiring board according to item 7 or 8; a functional device mounted on a surface of the second wiring substrate opposite to the surface of the first wiring substrate; A packaged device comprising:

[10] forming two or more layers in a laminate, each of the two or more layers comprising: forming a recess in an insulating resin layer; forming an inorganic insulating layer covering an upper surface of the insulating resin layer and an inner surface of the recess; forming a dummy layer on the inorganic insulating layer, the dummy layer having a groove and at least one through hole communicating with the recess; removing portions of the inorganic insulating layer exposed within the recess, the groove, and the through hole; forming a conductor layer on the dummy layer so as to fill the recess, the groove, and the through hole; polishing the conductor layer so as to remove a portion located outside the recess, the groove, or the through hole, thereby obtaining a portion of the conductor layer in which the recess is filled, a portion in which the through hole is filled, and a portion in which the groove is filled as a via portion, a land portion, and a wiring portion, respectively; Thereafter, removing the dummy layer; providing an insulating resin layer that covers the conductor layer and fills the gap between the land portion and the wiring portion; A method for manufacturing a multilayer wiring board comprising the steps of:

[11] Item 11. The method for producing a multilayer wiring board according to item 10, wherein the inorganic insulating layer contains one or more insulators selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride, silicon oxide doped with fluorine, and silicon oxide doped with carbon.

[12] 12. The method for manufacturing a multilayer wiring board according to item 10 or 11, wherein the recess, the groove and the through hole are formed to have a cross section of a forward tapered shape.

[13] 13. The method for manufacturing a multilayer wiring board according to any one of claims 10 to 12, wherein the formation of each of the two or more layers further includes forming a first metal-containing layer that covers an upper surface of the dummy layer and the inner surfaces of the recess, the groove, and the through hole before forming the conductor layer.

[14] Item 14. The method for manufacturing a multilayer wiring board according to item 13, wherein the first metal-containing layer contains titanium.

[15] Item 15. The method for manufacturing a multilayer wiring board according to item 13 or 14, wherein the formation of each of the two or more layers further comprises forming a second metal-containing layer on the first metal-containing layer before forming the conductor layer, the second metal-containing layer being made of the same material as the conductor layer or made of a metal material having a smaller ionization tendency than the material of the conductor layer. [Explanation of symbols]

[0179] 1...packaged device, 2...support, 3...peeling layer, 10...composite wiring board, 11...FC-BGA board, 12...multilayer wiring board, 12'...multilayer wiring board, 13...encapsulating resin layer, 14...bonding electrode, 20...functional device, 30...encapsulating resin layer, 40...bonding electrode, 111...core layer, 112...insulating layer, 113...conductor layer, 114...insulating layer, 115...bonding conductor, 120...layer, 120'...layer, 121...insulating resin layer, 122a...adhesion layer, 122b...seed layer, 123...conductor layer, 124...insulating resin layer, 125a... Adhesion layer, 125b...seed layer, 126...conductor layer, 127...surface treatment layer, 128...insulating resin layer, 221...resist layer, 228...resist layer, 1201...insulating resin layer, 1202...inorganic insulating layer, 1203...conductor layer, 1203L...land portion, 1203V...via portion, 1203W...wiring portion, 1204a...first metal-containing layer, 1204b...second metal-containing layer, 2201...dummy layer, G...groove portion, G'...groove, LB...laser light, R1...first recess, R1'...through hole, R2...second recess, S1...first surface, S2...second surface.

Claims

1. The laminated laminate includes two or more layers laminated together, each of the two or more layers comprising: an insulating resin layer having a first surface and a second surface which is the reverse side of the first surface, the insulating resin layer being integrally formed in a thickness direction, the insulating resin layer being provided with a first recess opening on the first surface, a groove opening on the first surface, and a second recess opening on the second surface and communicating with one or more of the first recesses; an inorganic insulating layer covering the first surface; The insulating resin layer includes a land portion and a wiring portion, which are formed by respectively filling the first recess and the groove portion, and a via portion protruding from the first surface at the position of the land portion, and the via portion is a conductor layer that fills a recess of another insulating resin layer adjacent to the first surface side. Including, A multilayer wiring board, wherein each of the two or more layers further includes a first metal-containing layer that covers the side surfaces of the land portion, the wiring portion and the via portion, the surface of the wiring portion facing the opening of the groove portion, and the peripheral portion of the surface of the land portion facing the first surface.

2. 2. The multilayer wiring board according to claim 1, wherein the inorganic insulating layer contains one or more insulators selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride, silicon oxide doped with fluorine, and silicon oxide doped with carbon.

3. 3. The multilayer wiring board according to claim 1, wherein the first metal-containing layer contains titanium.

4. 4. The multilayer wiring board according to claim 1, wherein each of the two or more layers further includes a second metal-containing layer interposed between the first metal-containing layer and the conductor layer and made of the same material as the conductor layer or made of a metal material having a smaller ionization tendency than the material of the conductor layer.

5. 5. The multilayer wiring board according to claim 1, wherein the first recess and the groove have a reverse tapered cross section, and the second recess has a forward tapered cross section.

6. A composite wiring board comprising a first wiring board and a second wiring board joined to the first wiring board, the first and second wiring boards being electrically connected to each other via a joining electrode interposed between them, and the second wiring board being a multilayer wiring board as defined in any one of claims 1 to 5.

7. 7. The composite wiring board according to claim 6, wherein the first wiring board is a wiring board for a flip chip ball grid array, and the second wiring board is an interposer.

8. The composite wiring board according to claim 6 or 7, a functional device mounted on a surface of the second wiring substrate opposite to the surface of the first wiring substrate; A packaged device comprising:

9. forming two or more layers in a laminate, the forming of each of the two or more layers comprising: forming a recess in an insulating resin layer; forming an inorganic insulating layer covering an upper surface of the insulating resin layer and an inner surface of the recess; forming a dummy layer on the inorganic insulating layer, the dummy layer having a groove and at least one through hole communicating with the recess; removing portions of the inorganic insulating layer exposed within the recess, the groove, and the through hole; forming a conductor layer on the dummy layer so as to fill the recess, the groove, and the through hole; polishing the conductor layer so as to remove a portion located outside the recess, the groove, or the through hole, thereby obtaining a portion of the conductor layer in which the recess is filled, a portion in which the through hole is filled, and a portion in which the groove is filled as a via portion, a land portion, and a wiring portion, respectively; Thereafter, removing the dummy layer; providing an insulating resin layer that covers the conductor layer and fills the gap between the land portion and the wiring portion; Including, The method for manufacturing a multilayer wiring board, wherein forming each of the two or more layers further includes forming a first metal-containing layer covering an upper surface of the dummy layer and the inner surfaces of the recess, the groove, and the through hole before forming the conductor layer.

10. 10. The method for manufacturing a multilayer wiring board according to claim 9, wherein the inorganic insulating layer contains one or more insulators selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride, silicon oxide doped with fluorine, and silicon oxide doped with carbon.

11. The method for manufacturing a multilayer wiring board according to claim 9 or 10, wherein the recess, the groove and the through hole are formed to have a forward tapered cross section.

12. 12. The method for manufacturing a multilayer wiring board according to claim 9, wherein the first metal-containing layer contains titanium.

13. 13. The method for manufacturing a multilayer wiring board according to claim 9, wherein the formation of each of the two or more layers further includes forming a second metal-containing layer on the first metal-containing layer before forming the conductor layer, the second metal-containing layer being made of the same material as the conductor layer or made of a metal material having a smaller ionization tendency than the material of the conductor layer.

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