Semiconductor device and method for manufacturing the same

Abstract

To provide a semiconductor device and a manufacturing method for a semiconductor device, in which the change in characteristic of a gate electrode can be suppressed.SOLUTION: A semiconductor device includes a semiconductor layer, an insulating film provided on the semiconductor layer and including an opening, a gate electrode connected to the semiconductor layer through the opening, and a protection film covering the gate electrode. The insulating film includes a first surface on the semiconductor layer side, and a second surface on the opposite side of the first surface. The gate electrode includes a third surface facing the second surface apart from the second surface, and a fourth surface connecting the second surface and the third surface. The gate electrode includes a Ni film forming the third surface and the fourth surface and includes a Ni oxide film covering the Ni film on the third surface and the fourth surface. The protection film covers the third surface and the fourth surface from above the Ni oxide film.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present disclosure relates to a semiconductor device and a method for manufacturing a semiconductor device. [Background technology]

[0002] 2. Description of the Related Art As a semiconductor device equipped with a high electron mobility transistor (HEMT), a semiconductor device having a gate electrode equipped with a base and an overhang portion extending laterally from the base has been proposed (Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] U.S. Patent No. 8,741,715 [Patent Document 2] JP 2013-207086 A [Patent Document 3] JP 2019-216188 A Summary of the Invention [Problem to be solved by the invention]

[0004] In conventional semiconductor devices, the characteristics of the gate electrode may change.

[0005] An object of the present disclosure is to provide a semiconductor device capable of suppressing changes in the characteristics of a gate electrode and a method for manufacturing the semiconductor device. [Means for solving the problem]

[0006] A semiconductor device according to the present disclosure includes a semiconductor layer, an insulating film provided on the semiconductor layer and having an opening formed therein, a gate electrode connected to the semiconductor layer through the opening, and a protective film covering the gate electrode, the insulating film having a first surface on the semiconductor layer side and a second surface opposite to the first surface, the gate electrode having a third surface away from the second surface and facing the second surface, and a fourth surface connecting the second surface and the third surface, the gate electrode including a Ni film constituting the third surface and the fourth surface, and having a Ni oxide film covering the Ni film on the third surface and the fourth surface, a portion of the gate electrode having a surface made of Au; The protective film covers the third surface and the fourth surface from above the Ni oxide film. At the same time, the surface made of Au is directly covered. . Effect of the Invention

[0007] According to the present disclosure, changes in the characteristics of the gate electrode can be suppressed. [Brief description of the drawings]

[0008] [Figure 1] FIG. 1 is a cross-sectional view showing an overview of a semiconductor device according to an embodiment. [Diagram 2] FIG. 2 is a cross-sectional view showing details of a gate electrode and its periphery in the semiconductor device according to the embodiment. [Diagram 3] FIG. 3 is a cross-sectional view (part 1) showing the method for manufacturing the semiconductor device according to the embodiment. [Figure 4] FIG. 4 is a cross-sectional view (part 2) showing the method for manufacturing the semiconductor device according to the embodiment. [Diagram 5] FIG. 5 is a cross-sectional view (part 3) showing the method for manufacturing the semiconductor device according to the embodiment. [Figure 6] FIG. 6 is a cross-sectional view (part 4) showing the method for manufacturing the semiconductor device according to the embodiment. [Figure 7] 7A to 7C are cross-sectional views (part 5) illustrating the method for manufacturing a semiconductor device according to the embodiment. [Figure 8] FIG. 8 is a cross-sectional view (part 6) showing the method for manufacturing the semiconductor device according to the embodiment. [Figure 9] FIG. 9 is a cross-sectional view (part 7) showing the method for manufacturing a semiconductor device according to the embodiment. [Figure 10] FIG. 10 is a cross-sectional view (part 8) showing the method for manufacturing a semiconductor device according to the embodiment. [Figure 11] FIG. 11 is a ninth cross-sectional view showing the method for manufacturing a semiconductor device according to an embodiment. [Figure 12] FIG. 12 is a cross-sectional view (part 10) showing the method for manufacturing the semiconductor device according to the embodiment. [Figure 13] FIG. 13 is a cross-sectional view (part 11) showing the method for manufacturing a semiconductor device according to the embodiment. [Figure 14] FIG. 14 is a twelfth cross-sectional view showing the method for manufacturing a semiconductor device according to the embodiment. [Figure 15] FIG. 15 is a thirteenth cross-sectional view showing the method for manufacturing a semiconductor device according to an embodiment. [Figure 16] FIG. 16 is a cross-sectional view (part 14) showing the method for manufacturing a semiconductor device according to the embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] The embodiments for carrying out the invention are described below.

[0010] [Description of the embodiments of the present disclosure] First, the embodiments of the present disclosure will be described. In the following description, the same or corresponding elements are denoted by the same reference numerals, and the same description thereof will not be repeated.

[0011] [1] A semiconductor device according to one embodiment of the present disclosure includes a semiconductor layer, an insulating film provided on the semiconductor layer and having an opening formed therein, a gate electrode connected to the semiconductor layer through the opening, and a protective film covering the gate electrode, wherein the insulating film has a first surface on the semiconductor layer side and a second surface opposite to the first surface, the gate electrode has a third surface away from the second surface and facing the second surface, and a fourth surface connecting the second surface and the third surface, the gate electrode includes a Ni film constituting the third surface and the fourth surface, and has a Ni oxide film covering the Ni film on the third surface and the fourth surface, and the protective film covers the third surface and the fourth surface from above the Ni oxide film.

[0012] When a Ni film is exposed on the surface of the gate electrode and is covered with a Si nitride film formed as a protective film by a chemical vapor deposition (CVD) method, Ni may diffuse into the protective film, causing a change in the characteristics of the gate electrode. When a Ni film is covered with an Al oxide film formed as a protective film by an atomic layer deposition (ALD) method, Ni may diffuse at the interface between the protective film and the Ni film, causing a change in the characteristics of the gate electrode. In contrast, in a semiconductor device according to one embodiment of the present disclosure, the Ni film is covered with a Ni oxide film on the third and fourth surfaces, and the protective film covers the third and fourth surfaces from above the Ni oxide film. This makes it possible to suppress the diffusion of Ni in the Ni film and suppress changes in the characteristics of the gate electrode.

[0013] [2] In the structure of [1], a gap may exist between the second surface and a portion of the protective film covering the third surface, which makes it easier to reduce parasitic capacitance between the gate electrode and the stacked structure.

[0014] [3] In the structure of [1] or [2], the protective film may include an Al oxide film or a Si nitride film, which makes it easier to protect the gate electrode from the intrusion of moisture from the outside.

[0015] [4] In any of [1] to [3], the Ni oxide film may have a thickness of 3 nm or more, which makes it easier to suppress the diffusion of Ni in the Ni film.

[0016] [5] In any of [1] to [4], the protective film may further cover the insulating film, whereby the laminated structure can be more securely protected.

[0017] [6] In any of [1] to [5], the area of ​​the portion of the Ni film in contact with the insulating film may be 0.10 times or less than the area of ​​the portion of the Ni film in contact with the Ni oxide film, which makes it easier to suppress diffusion of Ni in the portion of the Ni film in contact with the insulating film.

[0018] [7] A semiconductor device according to another aspect of the present disclosure includes a semiconductor layer, an insulating film provided on the semiconductor layer and having an opening formed therein, a gate electrode connected to the semiconductor layer through the opening, and a protective film including an Al oxide film or a Si nitride film covering the gate electrode and the insulating film, the insulating film having a first surface on the semiconductor layer side and a second surface opposite to the first surface, the gate electrode having a third surface away from the second surface and facing the second surface, and a fourth surface connecting the second surface and the third surface, the gate electrode including a Ni film constituting the third surface and the fourth surface and an Au film formed on the Ni film, and having a Ni oxide film covering the Ni film on the third surface and the fourth surface, the protective film covering the third surface and the fourth surface from above the Ni oxide film, and a gap exists between a portion of the protective film covering the third surface and the second surface.

[0019] [8] A method for manufacturing a semiconductor device according to another embodiment of the present disclosure includes the steps of: forming an insulating film on a semiconductor layer, the insulating film having a first surface on the semiconductor layer side and a second surface opposite to the first surface; forming an opening in the insulating film; forming a metal layer including a Ni film that is connected to the semiconductor layer through the opening, has a third surface facing the second surface and spaced away from the second surface, and a fourth surface connecting the second surface and the third surface, the metal layer including a Ni film that constitutes the third surface and the fourth surface; oxidizing the Ni film to form a Ni oxide film that covers the Ni film on the third surface and the fourth surface, and forming a gate electrode from a remainder of the metal layer; and forming a protective film that covers the gate electrode while covering the third surface and the fourth surface from above the Ni oxide film.

[0020] [Details of the embodiment of the present disclosure] Hereinafter, the embodiments of the present disclosure will be described in detail, but the present embodiments are not limited thereto. In addition, in this specification and drawings, components having substantially the same functional configurations may be denoted by the same reference numerals to avoid redundant description.

[0021] This embodiment relates to a semiconductor device including a GaN-HEMT having a nitride semiconductor as a main constituent material. Fig. 1 is a cross-sectional view showing an overview of the semiconductor device according to the embodiment. Fig. 2 is a cross-sectional view showing details of a gate electrode and its periphery in the semiconductor device according to the embodiment. Figs. 1 and 2 show cross sections perpendicular to the gate width direction.

[0022] As shown in FIG. 1, the semiconductor device 100 according to this embodiment has a substrate 10 and a stacked structure 20 of a plurality of semiconductor layers formed on the substrate 10. The substrate 10 is, for example, a SiC substrate having a (0001) main surface, and the stacking direction of the stacked structure 20 is, for example, the

[0001] direction. The stacked structure 20 includes an electron transit layer 12, an electron supply layer 14, and a cap layer 16, which are formed in this order from the substrate 10 side. The electron transit layer 12 is, for example, an undoped GaN layer having a thickness of about 1000 nm. The electron supply layer 14 is, for example, an n-type AlGaN layer having a thickness of about 20 nm. The cap layer 16 is, for example, an n-type GaN layer having a thickness of about 5 nm. The stacked structure 20 is an example of a semiconductor layer.

[0023] A first insulating film 22 is formed on the stacked structure 20. The first insulating film 22 is, for example, a Si nitride film. An opening 31 for a source and an opening 32 for a drain are formed in the first insulating film 22 and the stacked structure 20. A source electrode 41 that makes ohmic contact with the stacked structure 20 is formed in the opening 31, and a drain electrode 42 that makes ohmic contact with the stacked structure 20 is formed in the opening 32. A second insulating film 24 is formed on the first insulating film 22, the source electrode 41, and the drain electrode 42. The second insulating film 24 is, for example, a Si nitride film. The first insulating film 22 and the second insulating film 24 are included in the insulating film 26. The insulating film 26 has a first surface 26A on the stacked structure 20 side and a second surface 26B opposite to the first surface 26A. The first surface 26A is also the lower surface of the insulating film 26, and the second surface 26B is also the upper surface of the insulating film 26. The first surface 26A may be in contact with the stacked structure 20.

[0024] 2, between the source electrode 41 and the drain electrode 42, an opening 22X is formed in the first insulating film 22, and an opening 24X is formed in the second insulating film 24. The opening width of the opening 24X, i.e., the dimension in the gate length direction, is larger than the opening width of the opening 22X. For example, the opening width of the opening 24X is about 140 nm, and the opening width of the opening 22X is about 90 nm. The opening 24X penetrates the second insulating film 24, and the opening 22X penetrates the first insulating film 22. The opening 22X is exposed through the opening 24X, and the stacked structure 20 is exposed through the openings 24X and 22X.

[0025] The semiconductor device 100 has a gate electrode 43 that contacts the stacked structure 20 through the openings 22X and 24X. The gate electrode 43 has a Ni film 64 and an Au film 66 formed on the Ni film 64. For example, the Ni film 64 has a thickness of about 50 nm to 100 nm, and the Au film 66 has a thickness of about 300 nm to 600 nm. The gate electrode 43 has, for example, a T-shaped shape in cross section. That is, the gate electrode 43 has a base 43S and an overhanging portion 43T that overhangs both sides from the base 43S. The gate electrode 43 has a third surface 43A that is separated from the second surface 26B of the insulating film 26 and faces the second surface 26B. The third surface 43A is also the lower surface of the overhanging portion 43T. The gate electrode 43 further has a fourth surface 43B that connects the second surface 26B and the third surface 43A. The fourth surface 43B is also a side surface of a portion of the base 43S that is above the second surface 26B and below the third surface 43A. The Ni film 64 forms the third surface 43A and the fourth surface 43B. The gate electrode 43 may have a Pd film between the Ni film 64 and the Au film 66, or may have a Ta film on the Au film 66.

[0026] The semiconductor device 100 has a Ni oxide film 68 that covers the Ni film 64 on the third surface 43A and the fourth surface 43B. The semiconductor device 100 further has a protective film 70 that covers the gate electrode 43. The protective film 70 covers the third surface 43A and the fourth surface 43B from above the Ni oxide film 68. The protective film 70 may cover not only the gate electrode 43 but also the insulating film 26. The protective film 70 is, for example, an Al oxide film or a Si nitride film. The thickness of the protective film 70 is not particularly limited, but the thickness of the portion covering the third surface 43A is preferably 20 nm or more, and more preferably 25 nm or more.

[0027] In this embodiment, the Ni film 64 on the third surface 43A and the fourth surface 43B is covered with the Ni oxide film 68. Therefore, diffusion of Ni in the Ni film 64 can be suppressed, and changes in the characteristics of the gate electrode 43 can be suppressed.

[0028] A gap 46 may be present between the portion of the protective film 70 covering the third surface 43A and the second surface 26B. The presence of the gap 46 makes it easier to reduce the parasitic capacitance between the overhanging portion 43T of the gate electrode 43 and the stacked structure 20. Note that a so-called low dielectric constant (low-k) material may be disposed instead of the gap 46. This can improve the mechanical strength more than when the gap 46 is present. The relative dielectric constant of the low dielectric constant material is preferably 7.0 or less, and more preferably 4.0 or less.

[0029] When the protective film 70 contains an Al oxide film or a Si nitride film, it is easy to protect the gate electrode 43 from the intrusion of moisture from the outside, etc. When the protective film 70 covers the insulating film 26, the stacked structure 20 can be protected more firmly.

[0030] The Ni oxide film 68 is thicker than a natural oxide film of Ni, and the thickness of the Ni oxide film 68 is, for example, preferably 3 nm or more, and more preferably 5 nm or more. This is to make it easier to suppress the diffusion of Ni in the Ni film 64.

[0031] The area of ​​the portion of the Ni film 64 in contact with the insulating film 26 is preferably 0.10 times or less, more preferably 0.07 times or less, and still more preferably 0.05 times or less, the area of ​​the portion of the Ni film 64 in contact with the Ni oxide film 68. This is because diffusion of Ni in the portion of the Ni film 64 in contact with the insulating film 26 can be more easily suppressed.

[0032] The insulating film 26 may include a Si oxynitride film in contact with the Ni film 64. For example, the first insulating film 22 and the second insulating film 24 may include a Si nitride film as a main component and a Si oxynitride film covering the surface of the Si nitride film. When the insulating film 26 includes a Si oxynitride film in contact with the Ni film 64, diffusion of Ni at the interface between the Ni film 64 and the insulating film 26 is easily suppressed.

[0033] Next, a method for manufacturing the semiconductor device 100 according to the embodiment will be described. Figures 3 to 16 are cross-sectional views showing the method for manufacturing the semiconductor device according to the embodiment. Figures 3 to 8 show variations of the cross section shown in Figure 1, and Figures 9 to 16 show variations of the cross section shown in Figure 2.

[0034] First, as shown in FIG. 3, a stacked structure 20 including a plurality of nitride semiconductor layers is grown on a substrate 10 by metal organic chemical vapor deposition (MOCVD). Next, a first insulating film 22 in contact with an upper surface of the stacked structure 20 is formed by low pressure (LP) CVD. The first insulating film 22 is, for example, a Si nitride film having a thickness of 40 nm. Before forming the electron transit layer 12, a nucleation layer may be formed on the substrate 10, and the electron transit layer 12 may be formed on the nucleation layer. The nucleation layer is, for example, an AlN layer having a thickness of several tens of nm.

[0035] 4, an electron beam resist 51 is applied onto the first insulating film 22, and an opening 51X is formed by electron beam lithography in the electron beam resist 51. The first insulating film 22 is exposed through the opening 51X.

[0036] 5, an opening 31 for a source and an opening 32 for a drain are formed in the first insulating film 22 and the laminated structure 20 by reactive ion etching (RIE) using an electron beam resist 51 as a mask. For example, a reactive gas containing fluorine (F) is used to etch the first insulating film 22, and a reactive gas containing chlorine (Cl) is used to etch the laminated structure 20.

[0037] 6, a metal layer 61 is formed by vapor deposition on the inside of the opening 31 and the inside of the opening 32. The metal layer 61 also adheres to the upper surface of the electron beam resist 51 and the sidewall surface of the opening 51X. The metal layer 61 includes, for example, a Ta film, an Al film, and a Mo film which are formed in this order from the substrate 10 side.

[0038] Next, as shown in FIG. 7, the electron beam resist 51 is removed. With the removal of the electron beam resist 51, the portion of the metal layer 61 adhering to the electron beam resist 51 is also removed. Meanwhile, the metal layer 61 remains inside the openings 31 and 32. That is, lift-off is performed. Next, the metal layer 61 is alloyed by heat treatment. As a result, the source electrode 41 that makes ohmic contact with the stacked structure 20 is formed in the opening 31, and the drain electrode 42 that makes ohmic contact with the stacked structure 20 is formed in the opening 32.

[0039] 8, the second insulating film 24 is formed on the first insulating film 22, the source electrode 41, and the drain electrode 42 by using a plasma enhanced (PE) CVD method. The second insulating film 24 is, for example, a Si nitride film having a thickness of 20 nm. The first insulating film 22 and the second insulating film 24 are included in the insulating film 26.

[0040] 9, an electron beam resist 52 is applied onto the second insulating film 24, the source electrode 41, and the drain electrode 42. For example, polymethyl methacrylate (PMMA) is used as the electron beam resist 52. ZEP520A-7 manufactured by Zeon Corporation may be used as the electron beam resist 52. Next, an opening 52X is formed in the electron beam resist 52 by electron beam lithography. The opening width of the opening 52X, i.e., the dimension in the gate length direction, is, for example, about 70 nm. The second insulating film 24 is exposed through the opening 52X.

[0041] Next, as shown in FIG. 10, an opening 24X for a gate is formed in the second insulating film 24 by RIE using a reactive gas containing fluorine, and an opening 22X for a gate is formed in the first insulating film 22, using the electron beam resist 52 as a mask. In forming the openings 24X and 22X, the second insulating film 24 and the first insulating film 22 are etched under certain conditions. A significant side etch occurs in the second insulating film 24, and the opening width of the opening 24X is larger than the opening width of the opening 22X. For example, the opening width of the opening 24X is about 140 nm, and the opening width of the opening 22X is about 90 nm. The stacked structure 20 is exposed through the openings 24X and 22X.

[0042] Next, as shown in FIG. 11, the electron beam resist 52 is removed. Next, the electron beam resist 53, the electron beam resist 54, and the electron beam resist 55 are applied in this order on the cap layer 16, the first insulating film 22, the second insulating film 24, the source electrode 41, and the drain electrode 42. PMMA is used as the electron beam resists 53 and 55, and polymethyl glutarimide (PMGI) is used as the electron beam resist 54. The electron beam resists 53 and 55 can be processed finer than the electron beam resist 54. Next, an opening 55X is formed in the electron beam resist 55, an opening 54X is formed in the electron beam resist 54, and an opening 53X is formed in the electron beam resist 53 by electron beam lithography. For example, the opening width of the opening 55X is about 500 nm, the opening width of the opening 54X is about 580 nm, and the opening width of the opening 53X is about 290 nm. The second insulating film 24, the first insulating film 22, and the cap layer 16 are exposed through the openings 55X, 54X, and 53X.

[0043] 12, baking is performed to deform electron beam resist 53 so that the opening width at the lower end of opening 53X becomes smaller than the opening width at the upper end. That is, the sidewall surface of opening 53X is deformed into a tapered shape. Electron beam resist 53 may also be deformed so that the lower end of opening 53X coincides with the upper end of opening 24X in a self-aligned manner.

[0044] 13, a metal layer 62 is formed on the inside of the openings 55X, 54X, 53X, 24X, and 22X by a vapor deposition method. In forming the metal layer 62, a Ni film 64 is formed, and an Au film 66 is formed on the Ni film 64. For example, the Ni film 64 has a thickness of about 50 nm to 100 nm, and the Au film 66 has a thickness of about 300 nm to 600 nm. A Pd film may be formed between the Ni film 64 and the Au film 66, or a Ta film may be formed on the Au film 66. The metal layer 62 also adheres to the upper surface of the electron beam resist 55 and the sidewall surface of the opening 55X.

[0045] 14, the electron beam resists 55, 54, and 53 are removed. With the removal of the electron beam resists 55, 54, and 53, the portion of the metal layer 62 adhering to the electron beam resist 55 is also removed. Meanwhile, the metal layer 62 remains inside the openings 24X and 22X and on the first insulating film 22 and the second insulating film 24. That is, lift-off is performed. The remaining metal layer 62 has, for example, a T-shaped shape in cross section.

[0046] 15, the surface of the Ni film 64 included in the metal layer 62 is oxidized to form a Ni oxide film 68. As a result, a gate electrode 43 is formed, which has the Ni film 64 and the Au film 66 and makes a Schottky contact with the stacked structure 20 through the opening 22X. That is, the gate electrode 43 is formed from the remaining part of the metal layer 62 that has become the Ni oxide film 68. The gate electrode 43 has, for example, a T-shaped shape in cross section. The Ni film 64 can be oxidized using, for example, ozone.

[0047] Next, as shown in FIG. 16, a protective film 70 is formed to cover the gate electrode 43. The protective film 70 is in contact with the Ni oxide film 68 and the Au film 66, but is not in contact with the Ni film 64. The protective film 70 covers the Ni film 64 from above the Ni oxide film 68. The protective film 70 is, for example, an Al oxide film or a Si nitride film. The Al oxide film can be formed by, for example, the ALD method. The Si nitride film can be formed by, for example, the plasma CVD method. When the Si nitride film is formed by the plasma CVD method, the Si nitride film may contain fluorine (F) due to the characteristics of the apparatus.

[0048] Thereafter, wiring and the like are formed as necessary. In this manner, the semiconductor device 100 including the GaN-HEMT can be manufactured.

[0049] According to such a manufacturing method, the Ni oxide film 68 that suppresses the diffusion of Ni in the Ni film 64 can be easily formed.

[0050] Furthermore, when an Al oxide film is formed as the protective film 70 by the ALD method, the film can be formed using the same equipment as that used for oxidizing the surface of the Ni film 64. On the other hand, when a Si nitride film is formed as the protective film 70 by the CVD method, the protective film 70 can be formed at a high film formation rate.

[0051] When the insulating film 26 includes a Si nitride film, the surface of the Si nitride film may be oxidized. In other words, the surface of the insulating film 26 may be a Si oxynitride film. For example, the surface of the Si nitride film may be oxidized during various heat treatments performed after the second insulating film 24 is formed and before the Ni film 64 is formed.

[0052] Furthermore, as long as the Ni film 64 can make Schottky contact with the stacked structure 20, it does not need to be continuous from the portion in contact with the stacked structure 20 to the third surface 43A, and may be partially interrupted. For example, due to the influence of coverage during deposition, etc., the Ni film 64 may be discontinuous at corners of the first insulating film 22, corners of the second insulating film 24, etc.

[0053] Although the embodiments have been described in detail above, the present invention is not limited to the specific embodiments, and various modifications and changes are possible within the scope of the claims. [Explanation of symbols]

[0054] 10: Substrate 12: Electron transport layer 14:Electron supply layer 16: Cap layer 20: Laminated structure 22: First insulating film 22X:Aperture 24: Second insulating film 24X:Aperture 26: Insulating film 26A: 1st page 26B: 2nd side 31, 32: Opening 41: Source electrode 42: Drain electrode 43: Gate electrode 43A:Side 3 43B:Side 4 43S: Base 43T: Eaves 46:Void 51, 52, 53, 54, 55: Electron beam resist 51X, 52X, 53X, 54X, 55X: Aperture 61, 62: Metal layer 64:Ni film 66:Au film 68: Ni oxide film 70:Protective film 100: Semiconductor device

Claims

1. A semiconductor layer; an insulating film provided on the semiconductor layer and having an opening; a gate electrode connected to the semiconductor layer through the opening; a protective film covering the gate electrode; having The insulating film is A first surface on the semiconductor layer side; a second surface opposite the first surface; having The gate electrode is a third surface spaced apart from the second surface and facing the second surface; a fourth surface connecting the second surface and the third surface; having the gate electrode includes a Ni film constituting the third surface and the fourth surface, a Ni oxide film covering the Ni film on the third surface and the fourth surface; a portion of the gate electrode having a surface made of Au; The protective film covers the third surface and the fourth surface from above the Ni oxide film, and also directly covers the surface made of Au.

2. The semiconductor device according to claim 1 , wherein a gap exists between the second surface and a portion of the protective film covering the third surface.

3. 3. The semiconductor device according to claim 1, wherein the protective film includes an Al oxide film or a Si nitride film.

4. 4. The semiconductor device according to claim 1, wherein the Ni oxide film has a thickness of 3 nm or more.

5. The semiconductor device according to claim 1 , wherein the protective film further covers the insulating film.

6. 6. The semiconductor device according to claim 1, wherein an area of ​​the portion of the Ni film in contact with the insulating film is 0.10 times or less an area of ​​the portion of the Ni film in contact with the Ni oxide film.

7. A semiconductor layer; an insulating film provided on the semiconductor layer and having an opening; a gate electrode connected to the semiconductor layer through the opening; a protective film including an Al oxide film or a Si nitride film covering the gate electrode and the insulating film; having The insulating film is A first surface on the semiconductor layer side; a second surface opposite the first surface; having The gate electrode is a third surface spaced apart from the second surface and facing the second surface; a fourth surface connecting the second surface and the third surface; and a Ni film constituting the third surface and the fourth surface; Au formed on the Ni film; a Ni oxide film covering the Ni film on the third surface and the fourth surface; having a part of the gate electrode has a surface made of the Au; the protective film covers the third surface and the fourth surface from above the Ni oxide film, and also directly covers the surface made of Au; A semiconductor device in which a gap exists between the second surface and a portion of the protective film covering the third surface.

8. forming an insulating film on a semiconductor layer, the insulating film having a first surface on the semiconductor layer side and a second surface opposite to the first surface; forming an opening in the insulating film; forming a metal layer including a Ni film that is connected to the semiconductor layer through the opening, has a third surface that is spaced apart from the second surface and faces the second surface, and a fourth surface that connects the second surface and the third surface; and forming a gate electrode including a surface made of Au by oxidizing the Ni film to form a Ni oxide film covering the Ni film on the third surface and the fourth surface and being formed on a remainder of the metal layer; forming a protective film covering the third and fourth surfaces from above the Ni oxide film of the gate electrode and directly covering the surface made of Au; A method for manufacturing a semiconductor device having the above structure.

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