Semiconductor device and method for manufacturing the same

Abstract

To provide a semiconductor device in which the insulation breakdown of a protection film between a source field plate and a drain electrode can be suppressed, and a manufacturing method for a semiconductor device.SOLUTION: A semiconductor device includes a source electrode and a drain electrode arranged in a first direction parallel to a first main surface of a substrate, a gate electrode existing between the source electrode and the drain electrode, a first protection film covering the source electrode, the drain electrode, and the gate electrode, a source field plate formed on the first protection film, electrically connected to the source electrode, and existing between the gate electrode and the drain electrode in a plan view from a direction perpendicular to the first main surface, and an insulation breakdown suppression part including, in a cross-sectional view from a second direction parallel to the first main surface and perpendicular to the first direction, a part existing between an end of the source field plate on the drain electrode side and an end of the drain electrode on the source field plate side, and suppressing the insulation breakdown of the first protection film.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present disclosure relates to a semiconductor device and a method for manufacturing a semiconductor device. [Background technology]

[0002] Conventionally, a semiconductor device including a source field plate connected to a source electrode has been proposed (Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Special Publication No. 2019-516244 [Patent Document 2] JP 2019-169552 A [Patent Document 3] Special Publication No. 2019-537284 Summary of the Invention [Problem to be solved by the invention]

[0004] In a semiconductor device having a conventional source field plate, if the distance between the gate electrode and the drain electrode is reduced, there is a risk of dielectric breakdown occurring in the protective film between the source field plate and the drain electrode.

[0005] An object of the present disclosure is to provide a semiconductor device and a method for manufacturing the semiconductor device that can suppress dielectric breakdown of a protective film between a source field plate and a drain electrode. [Means for solving the problem]

[0006] a gate electrode formed on the nitride semiconductor layer and positioned between the source electrode and the drain electrode; a first protective film formed on the nitride semiconductor layer and covering the source electrode, the drain electrode, and the gate electrode; a source field plate formed on the first protective film, electrically connected to the source electrode, and positioned between the gate electrode and the drain electrode in a plan view from a direction perpendicular to the first main surface; and a dielectric breakdown suppression unit comprising a portion positioned between an end of the source field plate on the drain electrode side and an end of the drain electrode on the source field plate side in a cross-sectional view from a second direction parallel to the first main surface and perpendicular to the first direction, the dielectric breakdown suppression unit suppressing dielectric breakdown of the first protective film. The dielectric breakdown suppression portion includes a gap formed in the first protective film. . Effect of the Invention

[0007] According to the present disclosure, it is possible to suppress dielectric breakdown of the protective film between the source field plate and the drain electrode. [Brief description of the drawings]

[0008] [Figure 1] FIG. 1 is a cross-sectional view showing a semiconductor device according to a first embodiment. [Diagram 2] FIG. 2 is a cross-sectional view (part 1) showing the effect of the semiconductor device according to the first embodiment. [Diagram 3] FIG. 3 is a second cross-sectional view showing the effect of the semiconductor device according to the first embodiment. [Figure 4] FIG. 4 is a cross-sectional view (part 1) illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Diagram 5] FIG. 5 is a cross-sectional view (part 2) illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Figure 6] FIG. 6 is a cross-sectional view (part 3) illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Figure 7] FIG. 7 is a cross-sectional view (part 4) illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Figure 8] FIG. 8 is a cross-sectional view (part 5) illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Figure 9] FIG. 9 is a cross-sectional view (part 6) illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Figure 10] FIG. 10 is a cross-sectional view (part 7) illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Figure 11] FIG. 11 is a cross-sectional view (part 1) showing a method for forming an insulating film and a gap. [Figure 12] FIG. 12 is a cross-sectional view (part 2) showing a method for forming an insulating film and a gap. [Figure 13] FIG. 13 is a cross-sectional view (part 3) showing a method for forming an insulating film and a gap. [Figure 14] FIG. 14 is a cross-sectional view (part 4) showing a method for forming an insulating film and a gap. [Figure 15] FIG. 15 is a cross-sectional view showing the semiconductor device according to the second embodiment. [Figure 16] FIG. 16 is a cross-sectional view (part 1) showing a method for forming an insulating film and a second protective film. [Figure 17] FIG. 17 is a cross-sectional view (part 2) showing a method for forming an insulating film and a second protective film. [Figure 18] FIG. 18 is a cross-sectional view showing a semiconductor device according to the third embodiment. [Figure 19] FIG. 19 is a diagram showing IV characteristics. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] The embodiments for carrying out the invention are described below.

[0010] [Description of the embodiments of the present disclosure] First, the embodiments of the present disclosure will be listed and described.

[0011] [1] A semiconductor device according to one aspect of the present disclosure includes a substrate, a nitride semiconductor layer formed on the substrate, a source electrode and a drain electrode formed in the nitride semiconductor layer and aligned in a first direction parallel to a first main surface of the substrate, a gate electrode formed on the nitride semiconductor layer and positioned between the source electrode and the drain electrode, a first protective film formed on the nitride semiconductor layer and covering the source electrode, the drain electrode, and the gate electrode, a source field plate formed on the first protective film and electrically connected to the source electrode and positioned between the gate electrode and the drain electrode in a plan view from a direction perpendicular to the first main surface, and a dielectric breakdown suppression portion including a portion positioned between an end of the source field plate on the drain electrode side and an end of the drain electrode on the source field plate side in a cross-sectional view from a second direction parallel to the first main surface and perpendicular to the first direction, the dielectric breakdown suppression portion suppressing dielectric breakdown of the first protective film.

[0012] When the semiconductor device operates, an electric field is generated between the source field plate and the drain electrode, and as time passes, multiple defects occur in the first protective film. As the operating time increases, the defects become connected to each other. However, since the dielectric breakdown suppression portion is provided, the defects are prevented from continuing to form between the source field plate and the drain electrode. This suppresses the generation of a leak path connecting the source field plate and the drain electrode, and suppresses dielectric breakdown of the first protective film.

[0013] [2] In [1], the dielectric breakdown suppression portion may include a void formed in the first protective film. In this case, since no defects that could become leak paths are generated in the void, dielectric breakdown is more easily suppressed.

[0014] [3] In [1], the dielectric breakdown suppression portion may include a second protective film having a film density higher than that of the first protective film. In this case, the second protective film is less likely to have defects than the first protective film, so that dielectric breakdown can be suppressed.

[0015] [4] In [3], the first protective film may be a Si nitride film, and the second protective film may be an Al oxide film. In this case, the Si nitride film and the Al oxide film can be easily formed using existing equipment.

[0016] [5] In the structure of [3] or [4], the second protective film may be embedded in the first protective film. In this case, the second protective film can be easily disposed between the source field plate and the drain electrode.

[0017] [6] In any of [1] to [5], the dielectric breakdown suppression portion may include a portion located on the shortest line segment among line segments connecting a point in the source field plate and a point in the drain electrode in the cross-sectional view. In this case, since the dielectric breakdown suppression portion is located on a line segment where a leak path is likely to occur, dielectric breakdown is easily suppressed.

[0018] [7] In any one of [1] to [6], in the cross-sectional view, the drain electrode may be located on the source field plate side, in contact with the first protective film, and have a first side perpendicular to the first direction, and the dielectric breakdown suppression part may be disposed so as to cross a region between a point in the source field plate that is closest to the drain electrode and the first side. In this case, dielectric breakdown can be easily suppressed over a wide range.

[0019] [8] In any of [1] to [7], the dimension of the dielectric breakdown suppression portion in the first direction and the dimension in the direction perpendicular to the first main surface may be 10 nm or more. In this case, the size of the defect is generally less than 10 nm, so that dielectric breakdown can be effectively suppressed.

[0020] [9] A semiconductor device according to another aspect of the present disclosure includes a substrate, a nitride semiconductor layer formed on the substrate, a source electrode and a drain electrode formed in the nitride semiconductor layer and aligned in a first direction parallel to a first main surface of the substrate, a gate electrode formed on the nitride semiconductor layer and positioned between the source electrode and the drain electrode, a Si nitride film formed on the nitride semiconductor layer and covering the source electrode, the drain electrode, and the gate electrode, a source field plate formed on the Si nitride film, electrically connected to the source electrode, and positioned between the gate electrode and the drain electrode in a plan view from a direction perpendicular to the first main surface, and a gap formed in the first protective film, the gap having a portion positioned between an end of the source field plate on the drain electrode side and an end of the drain electrode on the source field plate side in a cross-sectional view from a second direction parallel to the first main surface and perpendicular to the first direction, wherein a dimension of the gap in the first direction is equal to or greater than 50 nm and a dimension of the gap in the direction perpendicular to the first main surface is equal to or greater than 100 nm.

[0021]

[10] A method for manufacturing a semiconductor device according to another aspect of the present disclosure includes the steps of: forming a nitride semiconductor layer on a substrate; forming, in the nitride semiconductor layer, a source electrode and a drain electrode aligned in a first direction parallel to a first main surface of the substrate; forming, on the nitride semiconductor layer, a gate electrode located between the source electrode and the drain electrode; forming a first protective film on the nitride semiconductor layer to cover the source electrode, the drain electrode, and the gate electrode; forming, on the first protective film, a source field plate electrically connected to the source electrode and located between the gate electrode and the drain electrode in a plan view from a direction perpendicular to the first main surface; and forming a dielectric breakdown suppression portion that suppresses dielectric breakdown of the first protective film, the dielectric breakdown suppression portion having a portion located between an end of the source field plate on the drain electrode side and an end of the drain electrode on the source field plate side in a cross-sectional view from a second direction parallel to the first main surface and perpendicular to the first direction.

[0022]

[11] In the method of

[10] , the step of forming the dielectric breakdown suppression portion may include the steps of forming a first insulating film covering the source electrode, the drain electrode, and the gate electrode in the step of forming the first protective film, forming a recess in the first insulating film having a portion located between an end of the source field plate on the drain electrode side and an end of the drain electrode on the source field plate side in the cross-sectional view, and forming a second insulating film on the first insulating film such that at least a portion of the recess remains as a void. In this case, it is easy to form a void as the dielectric breakdown suppression portion.

[0023] [Details of the embodiment of the present disclosure] Hereinafter, the embodiments of the present disclosure will be described in detail, but the present disclosure is not limited thereto. In this specification and drawings, components having substantially the same functional configurations may be denoted by the same reference numerals to avoid redundant description.

[0024] (First embodiment) First, a first embodiment will be described. The first embodiment relates to a semiconductor device including a GaN-HEMT having a nitride semiconductor as a main constituent material. Fig. 1 is a cross-sectional view showing a semiconductor device according to the first embodiment. Fig. 1 shows a cross section perpendicular to the gate width direction.

[0025] As shown in FIG. 1, the semiconductor device 100 according to the first embodiment has a substrate 10 having a first main surface 11 and a stacked structure 20 of a plurality of nitride semiconductor layers formed on the first main surface 11 of the substrate 10. The substrate 10 is, for example, a SiC substrate having a (0001) main surface, and the stacking direction of the stacked structure 20 is, for example, the

[0001] direction. The stacked structure 20 includes an electron transit layer 12, an electron supply layer 14, and a cap layer 16, which are formed in this order from the substrate 10 side. The electron transit layer 12 is, for example, an undoped GaN layer having a thickness of about 1000 nm. The electron supply layer 14 is, for example, an n-type AlGaN layer having a thickness of about 20 nm. The cap layer 16 is, for example, an n-type GaN layer having a thickness of about 5 nm. The stacked structure 20 is an example of a nitride semiconductor layer.

[0026] An insulating film 22 is formed on the stacked structure 20. The insulating film 22 is, for example, a Si nitride film. An opening 31 for a source electrode and an opening 32 for a drain electrode are formed in the insulating film 22 and the stacked structure 20. A source electrode 41 that makes ohmic contact with the stacked structure 20 is formed in the opening 31, and a drain electrode 42 that makes ohmic contact with the stacked structure 20 is formed in the opening 32. The source electrode 41 and the drain electrode 42 are arranged in a direction parallel to the first main surface 11 of the substrate 10. In the present disclosure, the direction in which the source electrode 41 and the drain electrode 42 are arranged is referred to as the first direction, the direction parallel to the first main surface 11 and perpendicular to the first direction is referred to as the second direction, and the direction perpendicular to the first main surface 11 is referred to as the third direction. In addition, the plan view refers to a plan view from the third direction, and the cross-sectional view refers to a cross-sectional view from the second direction. The source electrode 41 and the drain electrode 42 have, for example, a Ti film and an Al film formed on the Ti film. An insulating film 24 is formed on the insulating film 22, the source electrode 41, and the drain electrode 42. The insulating film 24 is, for example, a Si nitride film.

[0027] An opening 35 for a gate electrode is formed in the insulating films 22 and 24 between the source electrode 41 and the drain electrode 42. A gate electrode 43 that makes Schottky contact with the stacked structure 20 is formed in the opening 35. A part of the gate electrode 43 may be located on the insulating film 24. The gate electrode 43 has, for example, a Ni film and an Au film formed on the Ni film.

[0028] An opening 33 for a source wiring and an opening 34 for a drain wiring are formed in the insulating film 24. A source wiring 45 connected to the source electrode 41 is formed in the opening 33, and a drain wiring 46 connected to the drain electrode 42 is formed in the opening 34. The source wiring 45 and the drain wiring 46 have, for example, an Au film. An insulating film 26 is formed on the insulating film 24, the source wiring 45, the gate electrode 43, and the drain wiring 46. The insulating film 26 is, for example, a Si nitride film. The insulating films 22, 24, and 26 are included in a first protective film 28.

[0029] A source field plate 44 is formed on the insulating film 26. The source field plate 44 is electrically connected to the source electrode 41 through a path that does not appear in the cross-sectional view of FIG. 1. The source field plate 44 is located between the gate electrode 43 and the drain electrode 42 in a plan view. The source field plate 44 has, for example, a Ti film and a Ni film formed on the Ti film. The source field plate 44 may be connected to the source electrode 41 through the path that appears in the cross-sectional view of FIG. 1, that is, so as to cover the gate electrode 43 from above the insulating film 26.

[0030] A gap 51 is formed in the insulating film 26. In a cross-sectional view, the gap 51 is located between an end of the source field plate 44 on the drain electrode 42 side and an end of the drain electrode 42 on the source field plate 44 side. In a cross-sectional view, the gap 51 preferably has a portion located on the shortest line segment 59 among line segments connecting a point in the source field plate 44 and a point in the drain electrode 42. For example, the dimension of the gap 51 in the first direction is about 50 nm, and the dimension in the third direction is about 100 nm. The gap 51 is an example of a dielectric breakdown suppressing portion.

[0031] Here, a description will be given of the effects of the semiconductor device 100 according to the first embodiment. Figures 2 and 3 are cross-sectional views showing the effects of the semiconductor device 100 according to the first embodiment.

[0032] When the semiconductor device 100 is operated, an electric field is generated between the source field plate 44 and the drain electrode 42, and over time, a number of defects 71 are generated in the first protective film 28, as shown in Fig. 2. The size of each defect 71 is generally less than 10 nm.

[0033] 3, when the operation time increases, the defects 71 become connected to each other. When multiple defects 71 become connected between the source field plate 44 and the drain electrode 42, the connected defects 71 can become a leak path. In contrast, in the first embodiment, the voids 51 are formed in the first protective film 28. Even if multiple defects 71 become connected on the source field plate 44 side of the voids 51 and multiple defects 71 become connected on the drain electrode 42 side of the voids 51, no defects that can become a leak path are generated in the voids 51, and therefore the generation of a leak path connecting the source field plate 44 and the drain electrode 42 is suppressed.

[0034] Therefore, even if the distance between the gate electrode 43 and the drain electrode 42 and the distance between the source field plate 44 and the drain electrode 42 are reduced, it is possible to suppress dielectric breakdown of the first protective film 28. By reducing the distance between the gate electrode 43 and the drain electrode 42, it is possible to reduce the resistance of the channel between the gate electrode 43 and the drain electrode 42. Furthermore, by reducing the distance between the gate electrode 43 and the drain electrode 42, it is possible to reduce the size of the semiconductor device 100, increase the number of semiconductor devices 100 that can be manufactured from one semiconductor wafer, and reduce the material cost of the semiconductor device 100.

[0035] The distance between the gate electrode 43 and the drain electrode 42 in a plan view is preferably 2.0 μm or less, more preferably 1.5 μm or less, and even more preferably 1.0 μm or less. As described above, even if the distance between the gate electrode 43 and the drain electrode 42 is small, the first protective film 28 is unlikely to break down, and the smaller this distance is, the more the channel resistance can be reduced and the material costs can be reduced.

[0036] Furthermore, the distance between the source field plate 44 and the drain electrode 42 in plan view is preferably 1.0 μm or less, more preferably 0.7 μm or less, and even more preferably 0.5 μm or less. As described above, even if the distance between the source field plate 44 and the drain electrode 42 is small, dielectric breakdown of the first protective film 28 is unlikely to occur, and the smaller this distance is, the easier it is to reduce the distance between the gate electrode 43 and the drain electrode 42.

[0037] Furthermore, if no void 51 is formed, defects 71 are likely to be connected at the shortest line segment 59 and its vicinity. However, in the first embodiment, since void 51 includes a portion on line segment 59, it is easy to suppress the connection of defects 71 between the source field plate 44 and the drain electrode 42.

[0038] In a cross-sectional view, the gap 51 is preferably disposed so as to cross a region between the first side 42A of the drain electrode 42 and a point in the source field plate 44 that is closest to the drain electrode 42. Here, the first side 42A is located on the source field plate 44 side, contacts the first protective film 28, and is perpendicular to the first direction. By disposing the gap 51 in this manner, it is possible to suppress the connection of defects 71 between the source field plate 44 and the drain electrode 42 over a wide range. Note that the first side 42A does not have to be completely perpendicular to the first direction, and may be, for example, a side that is unavoidably inclined during etching.

[0039] The first and third direction dimensions of the voids 51 are preferably 10 nm or more. As described above, the size of each defect 71 that occurs over time is generally less than 10 nm. Therefore, if the first and third direction dimensions are 10 nm or more, it is easy to suppress the connection of defects 71. The first direction dimension is preferably 30 nm or more, and more preferably 50 nm or more. Moreover, the third direction dimension is preferably 50 nm or more, and more preferably 100 nm or more.

[0040] Next, a method for manufacturing the semiconductor device 100 according to the first embodiment will be described. Figures 4 to 10 are cross-sectional views showing the method for manufacturing the semiconductor device 100 according to the first embodiment.

[0041] First, as shown in FIG. 4, a stacked structure 20 including a plurality of nitride semiconductor layers is grown on a substrate 10 by metal organic chemical vapor deposition (MOCVD). Next, an insulating film 22 in contact with the upper surface of the stacked structure 20 is formed by low pressure (LP) CVD. The insulating film 22 is, for example, a Si nitride film having a thickness of 40 nm. Before forming the electron transit layer 12, a nucleation layer may be formed on the substrate 10, and the electron transit layer 12 may be formed on the nucleation layer. The nucleation layer is, for example, an AlN layer having a thickness of several tens of nm.

[0042] Next, as shown in FIG. 5, an opening 31 for a source electrode and an opening 32 for a drain electrode are formed in the insulating film 22 and the laminated structure 20, a source electrode 41 is formed in the opening 31, and a drain electrode 42 is formed in the opening 32.

[0043] The openings 31 and 32 are formed, for example, by reactive ion etching (RIE) of the insulating film 22 and the laminated structure 20 using a mask with openings. The source electrode 41 and the drain electrode 42 are formed, for example, by forming a metal layer by a deposition method using the mask used for forming the openings 31 and 32 as a growth mask, removing the mask (lift-off), and alloying the metal layer by heat treatment.

[0044] 6, the insulating film 24 is formed by using a plasma enhanced (PE) CVD method on the insulating film 22, the source electrode 41, and the drain electrode 42. The insulating film 24 is, for example, a Si nitride film having a thickness of 20 nm.

[0045] 7, an opening 35 for a gate electrode is formed in the insulating films 24 and 22 between the source electrode 41 and the drain electrode 42, and a gate electrode 43 is formed in the opening 35. A part of the gate electrode 43 may be formed on the insulating film 24.

[0046] In forming the opening 35, for example, RIE of the insulating film 24 and the insulating film 22 is performed using a mask having an opening. In forming the gate electrode 43, for example, a metal layer is formed by a deposition method using another mask having an opening as a growth mask, and the mask is then removed (lift-off).

[0047] Next, as shown in FIG. 8, an opening 33 for a source wiring and an opening 34 for a drain wiring are formed in the insulating film 24, a source wiring 45 is formed in the opening 33, and a drain wiring 46 is formed in the opening 34.

[0048] In forming the openings 33 and 34, for example, a mask having openings is used to perform RIE of the insulating film 24. Also, the source wiring 45 and the drain wiring 46 can be formed by, for example, a plating method.

[0049] 9, an insulating film 26 and a gap 51 are formed on the insulating film 24, the source wiring 45, the gate electrode 43, and the drain wiring 46. The insulating film 26 is, for example, a Si nitride film having a thickness of 400 nm. The insulating films 22, 24, and 26 are included in a first protective film 28. A method for forming the insulating film 26 and the gap 51 will be described later.

[0050] 10, source field plate 44 is formed on insulating film 26. Source field plate 44 is electrically connected to source electrode 41 through a path that does not appear in the cross-sectional view of FIG. 1. Source field plate 44 is located between gate electrode 43 and drain electrode 42 in a plan view. In forming source field plate 44, for example, a metal layer is formed by a vapor deposition method using a mask with an opening as a growth mask, and the mask is then removed (lift-off).

[0051] Thereafter, wiring and the like are formed as necessary. In this manner, the semiconductor device 100 including the GaN-HEMT can be manufactured.

[0052] Here, a method for forming the insulating film 26 and the gap 51 will be described. Figures 11 to 14 are cross-sectional views showing a method for forming the insulating film 26 and the gap 51. Figures 11 to 14 show the region between the source field plate 44 and the drain electrode 42 in a plan view.

[0053] 11, a first insulating film 26A is formed on the insulating film 24, the source wiring 45, the gate electrode 43, and the drain wiring 46. The first insulating film 26A is a Si nitride film. The thickness of the first insulating film 26A is smaller than the thickness of the insulating film 26, and is, for example, 300 nm. The first insulating film 26A can be formed by, for example, a plasma CVD method.

[0054] 12, an i-line resist 61 is applied onto the first insulating film 26A, and an opening 61X is formed in the i-line resist 61 by photolithography. The first insulating film 26A is exposed through the opening 61X. For example, the thickness of the i-line resist 61 is 650 nm, and the dimension (opening width) of the opening 61X is 300 nm.

[0055] Next, as shown in FIG. 13, i-line resist 61 is used as a mask, and CHF is used as an etching gas. 3 and O 2 The RIE of the first insulating film 26A is performed using a mixed gas of CHF 3 and O 2 When this mixed gas is used, reaction products 62 generated by etching the first insulating film 26A tend to adhere to the sidewall surface of the opening 61X. As a result, a recess 26X that is narrower the deeper it is formed in the first insulating film 26A. For example, in a cross-sectional view of the recess 26X, the ratio of the depth D of the recess 26X to the shortest distance W between the opposing reaction products 62 is set to 2.0 or more.

[0056] Next, as shown in FIG. 14, the i-line resist 61 is removed. Next, the second insulating film 26B is formed on the first insulating film 26A. The second insulating film 26B is a Si nitride film. The thickness of the second insulating film 26B is smaller than the thickness of the insulating film 26, and is, for example, 100 nm. The second insulating film 26B can be formed by, for example, a low-pressure CVD method. At this time, the second insulating film 26B cannot fill the recessed portion 26X, and a void 51 is formed.

[0057] In this manner, the insulating film 26 made of the first insulating film 26A and the second insulating film 26B, and the gap 51 can be formed.

[0058] According to this method, it is possible to stably manufacture semiconductor device 100 having gap 51 that acts as a dielectric breakdown suppression portion.

[0059] Second embodiment Next, a second embodiment will be described. The second embodiment differs from the first embodiment in the configuration of the dielectric breakdown suppression portion. Fig. 15 is a cross-sectional view showing a semiconductor device according to the second embodiment.

[0060] 15, in the semiconductor device 200 according to the second embodiment, a second protective film 52 is formed in the insulating film 26 instead of the voids 51. That is, the second protective film 52 is embedded in the first protective film 28. The second protective film 52 is made of a material having a higher film density than the first protective film 28. For example, the first protective film 28 is a Si nitride film, and the film density of the first protective film 28 is 3.2 g / cm. 3 The second protective film 52 is an Al oxide film and has a film density of 3.9 g / cm 3 The second protective film 52 is an example of a dielectric breakdown suppressing portion. The film density is the mass per unit volume of the film, and can be measured by, for example, X-ray reflectivity.

[0061] The other configuration is similar to that of the first embodiment.

[0062] Although omitted in Figure 15, as will be understood from the explanation of the method of forming the insulating film 26 described below, the second protective film 52 may be formed so as to extend over the entire surface, rather than just at the position of the void 51 in the first embodiment.

[0063] In the semiconductor device 200 according to the second embodiment, as the operating time increases, multiple defects 71 occur in the first protective film 28 between the source field plate 44 and the drain electrode 42. However, because the film density of the second protective film 52 is higher than the film density of the first protective film 28, defects are unlikely to occur in the second protective film 52. Therefore, even if multiple defects 71 are connected on the source field plate 44 side of the second protective film 52 and multiple defects 71 are connected on the drain electrode 42 side of the second protective film 52, defects that can become leak paths are unlikely to occur in the second protective film 52, and the generation of a leak path connecting the source field plate 44 and the drain electrode 42 is suppressed.

[0064] Therefore, similarly to the first embodiment, by reducing the distance between the gate electrode 43 and the drain electrode 42, it is possible to reduce the resistance of the channel between the gate electrode 43 and the drain electrode 42 and to reduce the material costs of the semiconductor device 100.

[0065] The film density of the second protective film 52 may be higher than that of the first protective film 28, and is preferably 3.4 g / cm 3 More preferably, it is 3.6 g / cm 3 More preferably, it is 3.8 g / cm 3 When the first protective film 28 is a Si nitride film and the second protective film 52 is an Al oxide film, the films can be easily formed using existing equipment.

[0066] Next, a method for forming the insulating film 26 and the second protective film 52 will be described. Figures 16 to 17 are cross-sectional views showing the method for forming the insulating film 26 and the second protective film 52. Figures 16 to 17 show the region between the source field plate 44 and the drain electrode 42 in a plan view.

[0067] First, as shown in FIG. 16, similarly to the first embodiment, the process up to the formation of the recess 26X is performed. Next, a second protective film 52 is formed on the first insulating film 26A. The second protective film 52 is an Al oxide film. The thickness of the second protective film 52 is, for example, 35 nm on the flat portion. The thickness of the second protective film 52 here is the thickness of the portion on the first insulating film 26A outside the recess 26X. The second protective film 52 can be formed by atomic layer deposition (ALD). The Al oxide film formed by the ALD method has good coverage, and the recess 26X is filled with the second protective film 52.

[0068] Next, the second insulating film 26B is formed on the second protective film 52. The second insulating film 26B is a Si nitride film. The thickness of the second insulating film 26B is smaller than the thickness of the insulating film 26, and is, for example, 100 nm. The second insulating film 26B can be formed by, for example, a low-pressure CVD method.

[0069] In this manner, it is possible to form the insulating film 26 consisting of the first insulating film 26A and the second insulating film 26B, and the second protective film 52. Note that, before the formation of the second insulating film 26B, the second protective film 52 may be removed except for the portion inside the recess 26X.

[0070] Third embodiment Next, a third embodiment will be described. The third embodiment differs from the first and second embodiments in the configuration of the dielectric breakdown suppression portion. Fig. 18 is a cross-sectional view showing the semiconductor device according to the third embodiment.

[0071] 18, in the semiconductor device 300 according to the third embodiment, neither voids 51 nor second protective film 52 are formed in the insulating film 26, and a third protective film 53 is formed on the insulating film 26. The third protective film 53 is made of a material having a higher film density than the first protective film 28. For example, the first protective film 28 is a Si nitride film, and the film density of the first protective film 28 is 3.2 g / cm. 3 whereas the third protective film 53 is an Al oxide film and has a film density of 3.9 g / cm 3The source field plate 44 is formed on the third protective film 53. The third protective film 53 is an example of a dielectric breakdown suppressing portion.

[0072] The other configuration is similar to that of the first embodiment.

[0073] In the semiconductor device 300 according to the third embodiment, as the operating time increases, multiple defects 71 occur in the first protective film 28 between the source field plate 44 and the drain electrode 42. However, because the film density of the third protective film 53 is higher than the film density of the first protective film 28, defects are unlikely to occur in the third protective film 53. Therefore, even if multiple defects 71 are connected on the drain electrode 42 side of the third protective film 53, defects that could become a leak path are unlikely to occur in the third protective film 53, and the generation of a leak path connecting the source field plate 44 and the drain electrode 42 is suppressed.

[0074] Therefore, similarly to the first embodiment, by reducing the distance between the gate electrode 43 and the drain electrode 42, it is possible to reduce the resistance of the channel between the gate electrode 43 and the drain electrode 42 and to reduce the material costs of the semiconductor device 100.

[0075] The film density of the third protective film 53 should be higher than that of the first protective film 28, and is preferably 3.4 g / cm 3 More preferably, it is 3.6 g / cm 3 More preferably, it is 3.8 g / cm 3 It is more than that.

[0076] Next, an experiment conducted by the present inventors will be described. In this experiment, a sample (sample No. 1) was prepared according to the first embodiment. A sample (sample No. 2) in which no voids were formed in the first protective film was also prepared. Samples No. 1 and No. 2 were identical in structure except for the presence or absence of voids. The distance between the source field plate and the drain electrode in plan view was set to 1 μm. In conventional semiconductor devices, the distance between the source field plate and the drain electrode in plan view is at most about 3 μm, so this distance of 1 μm is extremely short.

[0077] Then, for samples No. 1 and No. 2, the relationship (IV characteristics) between the voltage applied between the source field plate and the drain electrode and the current flowing between the source field plate and the drain electrode was examined. The results are shown in Fig. 19. Fig. 19 is a diagram showing IV characteristics. The horizontal axis in Fig. 19 represents the voltage between the source field plate and the drain electrode, and the vertical axis represents the current flowing between the source field plate and the drain electrode.

[0078] As shown in Figure 19, in sample No. 2, where no voids are formed, the current increased rapidly when a voltage of 80 V was applied. On the other hand, in sample No. 1, where voids are formed, the current only increased slightly even when a voltage of 100 V was applied. From this result, it can be seen that the dielectric strength voltage of sample No. 2 is 80 V or less, whereas the dielectric strength voltage of sample No. 1 is 100 V or more. In other words, it can be seen that sample No. 1 has a dielectric strength voltage that is 25% or more higher than sample No. 2.

[0079] Although the embodiments have been described in detail above, the present invention is not limited to the specific embodiments, and various modifications and changes are possible within the scope of the claims. [Explanation of symbols]

[0080] 10: Substrate 11: First main surface 12: Electron transport layer 14:Electron supply layer 16: Cap layer 20: Laminated structure 22, 24, 26: insulating film 26A: First insulating film 26B: Second insulating film 26X: Recess 28: 1st protective film 31, 32, 33, 34, 35: Opening 41: Source electrode 42: Drain electrode 42A: First side 43: Gate electrode 44: Source Field Plate 45: Source wiring 46: Drain wiring 51:Void 52:Second protective film 53:Third protective film 59: Line segment 61: i-line resist 61X:Aperture 62: Reaction products 71: Defect 100, 200, 300: Semiconductor device

Claims

1. A substrate; a nitride semiconductor layer formed on the substrate; a source electrode and a drain electrode formed in the nitride semiconductor layer and aligned in a first direction parallel to a first main surface of the substrate; a gate electrode formed on the nitride semiconductor layer and located between the source electrode and the drain electrode; a first protective film formed on the nitride semiconductor layer and covering the source electrode, the drain electrode, and the gate electrode; a source field plate formed on the first protective film, electrically connected to the source electrode, and located between the gate electrode and the drain electrode in a plan view from a direction perpendicular to the first main surface; a dielectric breakdown suppression portion that suppresses dielectric breakdown of the first protective film, the dielectric breakdown suppression portion including a portion located between an end of the source field plate on the drain electrode side and an end of the drain electrode on the source field plate side in a cross-sectional view from a second direction that is parallel to the first main surface and perpendicular to the first direction; having The semiconductor device, wherein the dielectric breakdown suppression portion includes a gap formed in the first protective film.

2. The semiconductor device according to claim 1 , wherein the dielectric breakdown suppressing portion includes a second protective film having a film density higher than a film density of the first protective film.

3. 3. The semiconductor device according to claim 2, wherein the first protective film is a silicon nitride film, and the second protective film is an aluminum oxide film.

4. 4. The semiconductor device according to claim 2, wherein the second protective film is embedded in the first protective film.

5. 5. The semiconductor device according to claim 1, wherein the dielectric breakdown suppression portion includes a portion that is located on a shortest line segment among line segments connecting a point in the source field plate and a point in the drain electrode in the cross-sectional view.

6. In the cross-sectional view, the drain electrode is located on the source field plate side, is in contact with the first protection film, and has a first side perpendicular to the first direction; 6. The semiconductor device according to claim 1, wherein the dielectric breakdown suppression portion is disposed so as to cross a region between a point in the source field plate that is closest to the drain electrode and the first side.

7. A semiconductor device described in any one of claims 1 to 6, wherein the dimension of the insulation breakdown suppression portion in the first direction and the dimension in the direction perpendicular to the first main surface are 10 nm or more.

8. A substrate, a nitride semiconductor layer formed on the substrate; a source electrode and a drain electrode formed in the nitride semiconductor layer and aligned in a first direction parallel to a first main surface of the substrate; a gate electrode formed on the nitride semiconductor layer and located between the source electrode and the drain electrode; a first protective film formed on the nitride semiconductor layer and covering the source electrode, the drain electrode, and the gate electrode; a source field plate formed on the first protective film, electrically connected to the source electrode, and located between the gate electrode and the drain electrode in a plan view from a direction perpendicular to the first main surface; a dielectric breakdown suppression portion that suppresses dielectric breakdown of the first protective film, the dielectric breakdown suppression portion including a portion located between an end of the source field plate on the drain electrode side and an end of the drain electrode on the source field plate side in a cross-sectional view from a second direction that is parallel to the first main surface and perpendicular to the first direction; having a dimension of the dielectric breakdown suppression portion in the first direction and a dimension in a direction perpendicular to the first principal surface are 10 nm or more.

9. A substrate; a nitride semiconductor layer formed on the substrate; a source electrode and a drain electrode formed in the nitride semiconductor layer and aligned in a first direction parallel to a first main surface of the substrate; a gate electrode formed on the nitride semiconductor layer and located between the source electrode and the drain electrode; a silicon nitride film formed on the nitride semiconductor layer and covering the source electrode, the drain electrode, and the gate electrode; a source field plate formed on the Si nitride film, electrically connected to the source electrode, and located between the gate electrode and the drain electrode in a plan view from a direction perpendicular to the first main surface; a gap formed in the Si nitride film and having a portion located between an end of the source field plate on the drain electrode side and an end of the drain electrode on the source field plate side in a cross-sectional view from a second direction parallel to the first main surface and perpendicular to the first direction; having The dimension of the gap in the first direction is 50 nm or more, and the dimension in the direction perpendicular to the first main surface is 100 nm or more.

10. forming a nitride semiconductor layer on a substrate; forming a source electrode and a drain electrode aligned in a first direction parallel to a first main surface of the substrate in the nitride semiconductor layer; forming a gate electrode on the nitride semiconductor layer and positioned between the source electrode and the drain electrode; forming a first protective film on the nitride semiconductor layer to cover the source electrode, the drain electrode, and the gate electrode; forming a source field plate on the first protective film, the source field plate being electrically connected to the source electrode and positioned between the gate electrode and the drain electrode in a plan view from a direction perpendicular to the first main surface; forming a dielectric breakdown suppression portion that suppresses dielectric breakdown of the first protective film, the dielectric breakdown suppression portion having a portion located between an end of the source field plate on the drain electrode side and an end of the drain electrode on the source field plate side in a cross-sectional view from a second direction that is parallel to the first main surface and perpendicular to the first direction; having The step of forming the dielectric breakdown suppression portion includes: In the step of forming the first protective film, forming a first insulating film covering the source electrode, the drain electrode, and the gate electrode; forming a recess in the first insulating film, the recess having a portion located between an end of the source field plate on the drain electrode side and an end of the drain electrode on the source field plate side in the cross-sectional view; forming a second insulating film on the first insulating film so that at least a portion of the recess remains as a void; A method for manufacturing a semiconductor device having the above structure.

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