Information processing device and storage control method

Abstract

To increase processor performance by reducing the amount of data exchanged between a memory and an integrated circuit that has the processor and a cache memory.SOLUTION: An information processing device includes an integrated circuit and a memory. The integrated circuit includes: a processor; a cache memory that stores data used by the processor; a compressor and a decompressor; and a storage control device. The memory is connected to the integrated circuit. The storage control device compresses target data using the compressor when storing the target data in the memory; transmits the compressed target data to the memory; decompresses the compressed target data using the decompressor when receiving the compressed target data from the memory; and writes the decompressed target data in the cache memory.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to an information processing device and a storage control method. [Background technology]

[0002] A method has been proposed to compress cache data blocks to virtually increase the capacity of the cache itself. In this method, a data compressor / decompressor is inserted between the processor and the cache data blocks read and written by the processor, virtually increasing the size of the cache that can be stored (for example, see Non-Patent Document 1).

[0003] There are also methods that add a compression mechanism to file systems such as ZFS, BTFS, and NFS. In this method, data in storage blocks is compressed, and data indicating whether compression has been performed is stored in a "block table" in the file system separately from the data itself (for example, see Non-Patent Document 4). [Prior art documents] [Non-patent literature]

[0004] [Non-Patent Document 1] Shingo Otani, Airi Ogawa, Kenji Yoshise, Skewed DRAM Cache Using Data Compression in FPGA Systems, Proceedings of the 78th Annual Conference of the Information Processing Society of Japan, pp.1.147-1.148, March 10, 2016, https: / / www.arch.cs.titech.ac.jp / a / thesis / Bthesis-2016-02-ohya.pdf [Non-Patent Document 2] V. Young, P. J. Nair and M. K. Qureshi, "DICE: Compressing DRAM caches for bandwidth and capacity," 2017 ACM / IEEE 44th Annual International Symposium on Computer Architecture (ISCA), Toronto, ON, Canada, 2017, pp. 627-638, doi: 10.1145 / 3079856.3080243. [Non-Patent Document 3] S. Sardashti, A. Seznec and D. A. Wood, "Skewed Compressed Caches," 2014 47th Annual IEEE / ACM International Symposium on Microarchitecture, Cambridge, UK, 2014, pp. 331-342, doi: 10.1109 / MICRO.2014.41. [Non-Patent Document 4] Hyun S., Ahn S., Lee S., Bahn H., Koh K. (2007) Memory-Efficient Compressed Filesystem Architecture for NAND Flash-Based Embedded Systems. In: Gervasi O., Gavrilova M.L. (eds) Computational Science and Its Applications - ICCSA 2007. ICCSA 2007. Lecture Notes in Computer Science, vol 4705. Springer, Berlin, Heidelberg. https: / / doi.org / 10.1007 / 978-3-540-74472-6_20 [Non-Patent Document 5] Xiang Gao, Mingkai Dong, Xie Miao, Wei Du, Chao Yu, Haibo Chen, EROFS: A Compression-friendly Readonly File System for Resource-scarce Devices, 2019 {USENIX} Annual Technical Conference, https: / / www.usenix.org / conference / atc19 / presentation / gao Summary of the Invention [Problem to be solved by the invention]

[0005] In a system including an integrated circuit (LSI) having a processor and a cache memory, and a memory connected to the integrated circuit, it is desired to reduce the time required to write data to the memory and the time required to write data stored in the memory to the cache memory in order to improve the performance of the processor. For this reason, it is conceivable to compress the data to be written to the memory, write the compressed data to the memory, and decompress the data read from the memory and write it to the cache memory.

[0006] However, in the conventional technology, data to be written to memory is compressed and data to be read from memory is compressed. There is no disclosure or suggestion of the viewpoint of decompressing the compressed data and storing it in a cache memory. In addition, the size of the compressed data does not necessarily become smaller by the compression process, and conversely, the size may become larger. There is no disclosure or suggestion of the problems that occur when the size of the compressed data becomes larger than the size of the original data.

[0007] An object of the present invention is to provide an information processing device capable of improving the performance of a processor by reducing the amount of data exchanged between an integrated circuit having a processor and a cache memory and a memory. [Means for solving the problem]

[0008] One aspect of the present invention is an information processing device. The information processing device includes a processor, an integrated circuit including a cache memory that stores data used by the processor, a compressor, a decompressor, and a storage control device, and a memory connected to the integrated circuit. When storing target data in the memory, the storage control device compresses the target data using the compressor, transmits the compressed target data to the memory, and when the compressed target data is received from the memory, decompresses the compressed target data using the decompressor, and writes the decompressed target data to the cache memory.

[0009] One aspect of the present invention is a storage control method, which includes a storage control device included in an integrated circuit together with a processor, a cache memory for storing data used by the processor, and a compressor and a decompressor, compressing the target data using the compressor when storing target data in a memory connected to the integrated circuit, transmitting the compressed target data to the memory, and decompressing the compressed target data using the decompressor when the compressed target data is received from the memory, and writing the decompressed target data to the cache memory.

[0010] The storage control method may employ the following configuration: A storage area of ​​a memory is partitioned into blocks of a predetermined size, and a storage control device transfers the target data in an uncompressed state to the memory when the size of the target data in an uncompressed state does not exceed the block size, but the size of the target data in a compressed state exceeds the block size.

[0011] The storage control method may also employ the following configuration: the storage control device transmits compressed or uncompressed target data to a memory together with information indicating whether the target data is compressed or uncompressed, and when the target data and information are received from the memory and the information indicates the compressed state of the target data, decompresses the target data using a decompressor. Effect of the Invention

[0012] According to the present invention, the performance of the processor can be improved by reducing the amount of data exchanged between the memory and an integrated circuit having the processor and cache memory. [Brief description of the drawings]

[0013] [Figure 1] FIG. 1 is a diagram illustrating an example of a configuration of an information processing device according to an embodiment. [Diagram 2] FIG. 2A is an explanatory diagram for a case where target data is stored in memory, and FIG. 2B shows an example of the data structure of a management table managed by the storage control device. [Diagram 3] 3A and 3B are diagrams for explaining the problem in the reference example. [Figure 4] 4A and 4B are diagrams illustrating a storage control method according to an embodiment. [Diagram 5] FIG. 5 is a diagram illustrating a first configuration example of a memory according to the embodiment. [Figure 6] FIG. 6 is a flowchart showing an example of the operation of the storage control device when writing to memory. [Figure 7] FIG. 7 is a flowchart showing an example of the operation of the storage control device when writing to the cache memory. [Figure 8] FIG. 8 is a diagram illustrating a second configuration example of the memory. [Figure 9] FIG. 9 is a flowchart showing an example of the operation of the storage control device when the second configuration example is applied. [Figure 10] FIG. 10 is a flowchart showing an example of the operation of the storage control device when the second configuration example is applied. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0014] An information processing device according to an embodiment includes a processor, an integrated circuit including a cache memory that stores data used by the processor, a compressor, a decompressor, and a storage control device, and a memory connected to the integrated circuit. When storing target data in the memory, the storage control device compresses the target data using the compressor, transmits the compressed target data to the memory, and when the compressed target data is received from the memory, decompresses the compressed target data using the decompressor, and writes the decompressed target data to the cache memory.

[0015] According to the information processing device, when storing target data in a memory, the target data in a compressed state is transmitted from the integrated circuit to the memory. Also, when storing data in a cache memory, the target data in a compressed state is received. When the communication speed between the integrated circuit and the memory is constant, the size of the target data is reduced by compressing the target data, thereby reducing the time required for data transmission between the two. Therefore, the time required for writing data to the memory as viewed from the processor can be reduced. Also, the target data in a compressed state, which is smaller in size than the uncompressed state, is received by the integrated circuit, decompressed, and stored in the cache memory, thereby reducing the time required for reading data from the memory as viewed from the processor. In this way, the performance of the processor can be improved by reducing the write time and read time to the memory.

[0016] The information processing device may employ the following configuration. That is, when the storage area of ​​the memory is partitioned into blocks of a predetermined size capable of storing the target data, the storage control device transmits the target data in an uncompressed state to the memory when the size of the target data in an uncompressed state does not exceed the size of the block, but the size of the target data in a compressed state exceeds the size of the block. The size of the target data is not necessarily reduced by compression, and the size after compression may be larger than the original size. In such a case, the amount of data transmitted to the memory is reduced by transmitting the original target data, that is, the uncompressed target data, instead of the compressed target data, that is, the target data after compression.

[0017] The information processing device may also adopt the following configuration. That is, the storage control device transmits the compressed or uncompressed target data to the memory together with information indicating whether the target data is compressed or uncompressed. The memory stores the information and the target data in one of the blocks. When the target data and the information are received from the memory and the information indicates the compressed state of the target data, the storage control device decompresses the target data using a decompressor. In this way, information indicating whether the target data transmitted to the memory is compressed or uncompressed is stored in the memory together with the target data, and the target data and information are passed to the storage control device when reading from the memory, so that the storage control device can determine whether decompression is required. If decompression is not required, writing to the cache memory is performed without decompression, thereby shortening the time required until writing to the cache memory is completed.

[0018] When the information indicating whether the target data is compressed or uncompressed is stored in the memory, it is preferable to use an error correction code memory (ECC memory) as the memory, and to adopt a configuration in which the information is stored in the memory area of ​​the error correction code that the error correction code memory has. and the information can be stored in memory in an associated state.

[0019] The information processing device may also employ the following configuration. That is, data is specified to be stored in a storage area of ​​the memory in compressed block units having a size larger than the size of the block. The compressed target data transmitted to the memory is stored in each compressed block. By employing such a configuration, even if the size of the compressed target data becomes larger than the size of the target data before compression and the size exceeds the size of the block, the compressed target data can be suitably stored.

[0020] Hereinafter, an embodiment of an information processing device and a storage control method will be described with reference to the drawings. The configurations of the embodiments are merely examples, and the present invention is not limited to the configurations of the embodiments.

[0021] Fig. 1 shows an example of the configuration of an information processing device 1 according to an embodiment. In Fig. 1, the information processing device 1 includes a microprocessor LSI 10 (hereinafter, integrated circuit 10) which is an example of an integrated circuit, a memory (main storage device) 15 connected to the integrated circuit 10 via a bus 2, and a storage (auxiliary storage device) 21 connected to the integrated circuit 10 via the bus 2.

[0022] The integrated circuit 10 includes a processor 11, a cache memory 12, and a storage control device (Memory The MMU 13 includes a compressor 14A and a decompressor 14B used by the MMU 13.

[0023] The processor 11 is a microprocessor (MPU), a CPU (Central Processing Unit), etc. The cache memory 12 is implemented in the integrated circuit 10. The memory 15 and the storage 21 are connected to the integrated circuit 10 via the bus 2. That is, the memory 15 and the storage 21 are disposed outside the integrated circuit 10.

[0024] The cache memory 12, memory 15, and storage 21 store data used by the processor 11. The cache memory 12 is a high-speed, small-capacity (clock frequency on the order of GHz, capacity of several MB) storage medium arranged closer to the processor than the memory 15 and storage 21, and is composed of an SRAM or the like. The memory 15 is a recording medium that is slower than the cache memory 12 but has a large capacity (clock frequency of about 100 MHz, capacity of several GB), and is composed of a DRAM or the like. The storage 21 is a low-speed, large-capacity storage medium (clock frequency of several tens of MHz, capacity of several TB) than the memory 15, and is, for example, a hard disk or SSD (Solid State Drive).

[0025] Normally, when the processor 11 performs processing, data to be processed is read from the storage 11 and stored in the memory 15. In the process of passing data stored in the memory 15 to the processor 11, if the data is not stored in the cache memory 12, the data is stored in the cache memory 12. When the processor 11 requests reading of data stored in the memory 15, it is determined whether the requested data is stored in the cache memory 12, and if the data is stored, reading from the memory 15 is not performed, and the data stored in the cache memory 12 is passed to the processor 11.

[0026] Since the SRAM used in the cache memory 12 is expensive, currently, there are CPUs having first to fourth caches, but it is difficult to increase the capacity of the cache memory. For this reason, shortening the time required for writing to the memory 15 and reading from the memory 15 is an important factor for improving the performance of the processor 11.

[0027] In order to increase the input / output speed between the processor 11 and the memory 15, the following can be considered. (1) Improved memory 15 interface speed (2) Increasing the number of bits in the memory 15 interface

[0028] However, in the method (1) for increasing the speed of the interface of the memory 15, there are problems that the mounting on the printed circuit board is difficult or that the switching of the transistors is increased, which increases the power consumption and generates heat. On the other hand, in the method (2) for increasing the number of bits of the interface of the memory 15, the number of pins of the integrated circuit 10 is increased, which increases the cost. Also, as in the method (1), there are problems that the mounting on the printed circuit board is difficult or that the heat generation is caused by the increased switching of the transistors. For this reason, in this embodiment, the data to be written to the memory 15 (target data) is compressed, thereby reducing the amount of data transmitted to the memory 15 for writing and the amount of data transmitted from the memory 15 to the integrated circuit 10 for reading, thereby shortening the time required for writing and reading and improving the performance of the processor 11.

[0029] Cache control such as management of data stored in the cache memory 12 is performed by, for example, the MMU 13. However, a cache control entity (cache controller) other than the MMU may be provided, and the cache control may be performed by the cache controller. That is, the "storage control device" according to the present invention may be configured such that the MMU controls the cache, or may include the MMU and the cache controller. In this embodiment, a configuration is adopted in which the MMU 13 has the functions of the compressor 14A and the decompressor 14B, or controls the operation of the compressor 14A and the decompressor 14B, making it possible to compress and decompress the target data. There are no limitations on the compression and decompression methods applied to the compressor 14A and the decompressor 14B as long as they allow reversible compression and decompression of data.

[0030] In this embodiment, data management in the memory 15 is performed in units of physical blocks (referred to as block 15a) each of which is a collection of storage areas of a number of consecutive addresses starting from an address called a base address. The storage area of ​​the memory 15 is partitioned into blocks 15a each having a predetermined size. Reading and writing data from and to the memory 15 is performed by sequentially accessing and reading from a predetermined number of consecutive addresses constituting one block 15a starting from the base address (called burst mode). Writing data to the cache memory 12 is performed in units of blocks 15a. The size of the blocks 15a can be determined as appropriate.

[0031] In order to obtain the benefit of access in burst mode to the memory 15, the cache memory 12 has a configuration in which cache data is managed in units of blocks (storage areas) of several tens to several kilobytes, which matches the size of the block 15a, and data is exchanged with the memory 15 in units of these blocks.

[0032] 2A, the MMU 13 has a management table 16 that manages the association between the storage area of ​​the cache memory 12 and the storage area of ​​the memory 15. As shown in FIG 2B, the management table 16 stores the correspondence between a cache tag (an identifier of a block in the cache memory 12) that indicates the position (address) of the block 12a in the cache memory 12 that stores the data stored in the block 15a in the memory 15, and a base address that is the starting address of the block 15a in the memory 15 that stores the data stored in the block 12a.

[0033] The processor 11 can access all addresses in the memory 15, and data write and read commands are issued by specifying a base address of the memory 15. When data stored in a block 15a of the memory 15 is stored in a block 12a of the cache memory 12, a cache tag that identifies the block 12a of the cache memory 12 in association with the base address of the memory 15 is stored in the management table 16.

[0034] When the MMU 13 receives a command from the processor 11 to read data specifying a certain base address in the memory 15, the MMU 13 refers to the management table 16. At this time, if a cache tag related to the specified base address is stored in the management table 16, the MMU 13 reads the data from the block 12a of the cache memory 12 specified by the cache tag and supplies the data to the processor 11 (cache hit).

[0035] When the MMU 13 refers to the management table 16 and finds that the cache tag associated with the specified base address is not stored in the management table 16, the MMU 13 determines that the data to be read is not stored in the cache memory 12 (cache miss). At this time, the MMU 13 accesses (reads data from) one block of consecutive addresses starting from the base address of the memory 15 specified by the read command, and reads data from the block 15a of the memory 15 specified by the base address. The MMU 13 stores the data read from the memory 15 in a free block 12a of the cache memory 12 (including an overwritable state), and stores the cache tag of this block 12a in the management table 16 in association with the base address.

[0036] When the processor 11 updates data stored in the cache memory 12 and issues a write command to the memory 15, the MMU 13 refers to the management table 16, identifies a cache tag associated with the base address specified in the write command, and writes the updated data to the block 12a of the cache memory 12 identified by this cache tag.

[0037] For example, the MMU 13 monitors access to each block 12a of the cache memory 12 that stores data, and when a block 12a occurs that has not been accessed continuously for a predetermined time, the MMU 13 reads the data stored in the corresponding block 12a. Alternatively, when there is no block 12a in the cache memory 12 that can store data read from the memory 15 in accordance with a data read command from the processor 11, the MMU 13 selects one of the blocks 12a in accordance with a predetermined rule and reads the data stored in the selected block 12a.

[0038] As a predetermined rule for selecting a block 12a, for example, the block 12a corresponding to the current position of a pointer that cyclically (round robin) points to any of the blocks 12a is selected as the read target. There are various ways to advance the pointer, for example, the pointer is advanced by one each time any of the blocks 12a is read. Alternatively, a timestamp that records the last time of reading may be set in each block 12a, and the block 12a with the oldest timestamp may be selected as the read target. The predetermined rule is not limited to these examples.

[0039] The MMU 13 refers to the management table 16, identifies a block 15a in the memory 15 starting from the base address associated with the cache tag of the corresponding block 12a, and stores the data read from the block 12a using the burst mode in the identified block 15a. At this time, the MMU 13 deletes the pair of the corresponding cache tag and base address from the management table 16, thereby setting the block 12a of the cache memory 12 identified by the cache tag to an empty state.

[0040] Furthermore, when the processor 11 generates data that is not stored in the cache memory 13 or the memory 15 by processing or calculation according to the program, the processor 11 issues a write command for the data, specifying a base address of the write destination in the memory 15 according to the program. The base address of block 15a on memory 15 is specified in the write command. Since such a base address cannot be found in management table 16, MMU 13 writes the data to be written to block 15a identified by the base address specified in the write command.

[0041] As described above, the information processing device 1 of the present embodiment is configured such that it is not possible to access the memory 15 at a granularity finer than the base address. That is, the memory 15 is divided into sections based on base addresses.

[0042] In the information processing device 1 of this embodiment, when data is written (stored) in the memory 15, the MMU 13 compresses the data to be written using the compressor 14A. However, the size of the data to be written is not necessarily reduced by compression, and may be increased instead. Such an increase in size occurs when the data is highly random.

[0043] 3A shows a case where the size of data to be written is reduced by compression by compressor 14A. When the size of data is reduced by compression, the data (shown in shaded areas) fits within block 15a to which it is written. At this time, the amount of data to be transferred to memory 15 is reduced.

[0044] 3B shows a case where the size of data to be written increases due to compression by the compressor 14A. When the size of data increases due to compression, the data (shown in shaded areas) may not fit within the block 15a to which the data is to be written, and may end up being written to a block 15a (adjacent block) adjacent to the block 15a to which the data is to be written. In this case, overwriting the data in the adjacent block may damage the data in the adjacent block. In addition, the increase in the amount of data due to compression may increase the overhead time for writing, which may cause a decrease in the performance of the processor 11.

[0045] 4, in this embodiment, when the MMU 13 detects that the size of the compressed data to be written by the compressor 14A is equal to or larger than the size of the block 15a, the operation of the compressor 14A is stopped, and the original (uncompressed) data is transmitted to and written in the memory 15. Since the size of the original data fits in the block 15a, the amount of data transmitted to the memory 15 does not decrease, but the problem of overwriting adjacent blocks can be avoided.

[0046] Fig. 5 shows a configuration example (first configuration example) of the memory 15 according to the embodiment. As shown in Fig. 5, in the memory 15, storage areas corresponding to four addresses are collected together to form one block 15a, and an area (field) 15b is provided for each address in which information is set indicating whether the data to be written is in a compressed state or a non-compressed state (original state).

[0047] In this embodiment, when data is compressed, a bit (compression bit) indicating the compressed state of the data is set. However, a bit (uncompressed bit) indicating the uncompressed state of the data may also be set. When an address is set in units of access to the memory 15 (for example, in units of words), a compression bit is added to each word, and indicates whether the data is compressed or uncompressed in units of words. When reading data from the block 15a of the memory 15, the MMU 13 refers to the compression bit in units of words to identify whether the data is compressed or uncompressed, and to what extent the data is compressed.

[0048] The compressed bit can be implemented by adding a pin for transmitting the compressed bit to the integrated circuit 10. Also, an area 15b for storing the compressed bit is added to the memory 15. For example, when one address has a word length of 32 bits and the compressed bit is 1 bit, a 33-bit data is stored. The data width of the memory 15 is increased so that the data width can be stored. An ECC memory is applied as the memory 15, and a field for storing an error correction code is used as the area 15b, whereby the compressed bits can be stored.

[0049] 6 is a flowchart showing an example of the operation of the MMU 13 when writing data to the memory 15. In step S11, the MMU 13 acquires (receives) a command (write request) issued by the processor 11 to write data to the memory 15.

[0050] In step S12, the MMU 13 acquires data (target data) to be written to the memory 15. The target data is update data stored in the block 12a of the cache memory 12, or new data received from the processor 11 (data not stored in the cache memory 12 or the memory 15).

[0051] In step S13, the MMU 13 turns on the operation of the compressor 14A and compresses the target data. Compression is performed in units of words. In step S14, the MMU 14 determines whether the size of the compressed data exceeds the size of the block 15a of the memory 15. If it is determined that the size of the compressed data is smaller than the size of the block 15a (NO in S14), the process proceeds to step S15, and if not (if the size of the compressed data exceeds the size of the block 15a: YES in S14), the process proceeds to step S17.

[0052] In step S15, the MMU 13 judges whether compression of all the target data is completed or not. If it is judged that compression is completed, the process proceeds to step S16, and if it is judged that compression is not completed, the process returns to step S13 and compression is performed on the next word of data.

[0053] In step S16, the MMU 13 writes the compressed target data to the block 15a, starting from the base address of the destination block 15a. At this time, the MMU 13 transfers the compressed data and compressed bits to the memory 15 in word units (address units) that make up the block 15a in burst mode. The compressed data and compressed bits are written to the corresponding storage area in the block 15a.

[0054] In step S17, the MMU 13 stops the operation of the compressor 14A. In step S18, the MMU 13 writes the target data in uncompressed state to the block 15a, starting from the base address of the block 15a to which the data is to be written. At this time, the MMU 13 transfers the data in uncompressed state (uncompressed data) in word units (address units) constituting the block 15a in burst mode to the memory 15. The uncompressed data is written to the corresponding storage area in the block 15a.

[0055] The transfer of the compressed data and compressed bits in units of words may be performed in real time or in batches. In the case of real time transfer, when a YES determination is made in step S14, the transfer of the compressed data and compressed bits is stopped by stopping the data compression, and the transfer of the target data in an uncompressed state is started.

[0056] 7 is a flowchart showing an example of the operation of the MMU 13 when reading data from the memory 15. In step S21, the MMU 13 acquires (receives) a read command (read request) for reading data from the memory 15 issued by the processor 11.

[0057] In step S22, the MMU 13 refers to the management table 16 and searches the management table 16 for a record at the base address specified by the read command. If a cache tag associated with the specified base address is found in the management table 16, the MMU 13 determines that there is a cache hit, and the process proceeds to step S27. On the other hand, if a record for the specified base address is not found in the management table 16, the MMU 13 determines that there is a cache miss, and the process proceeds to step S23.

[0058] In step S23, the MMU 13 acquires data stored in block 15a of memory 15 starting from the specified base address. In step S24, the MMU 13 determines whether the data is compressed data (whether the data is compressed or uncompressed) by determining whether a compression bit has been read from block 15a. If the data is determined to be compressed data, the process proceeds to step S25, and if not, the process proceeds to step S26.

[0059] In step S25, the MMU 13 uses the decompressor 14B (by controlling the operation of the decompressor 14B) to decompress the data read from the memory 15. In step S26, the MMU 13 writes the data to an empty block 12a of the cache memory 12. At this time, the MMU 13 registers in the management table 16 a pair of the base address and the cache tag of the block 12a into which the data has been written.

[0060] In step S26, the MMU 13 supplies the data stored in the block 12a of the cache memory 12 to the processor 11. As a result, data corresponding to the read command is supplied to the processor 11.

[0061] Fig. 8 shows another example (second example) of the configuration of memory 15, which is different from the configuration of memory 15 shown in Fig. 5. In Fig. 8, a block 15c (called a compressed block) having twice the size of block 15a is defined in memory 15, as an example. Data compressed by compressor 14A is stored in units of compressed block 15c, regardless of the increase or decrease in size due to compression.

[0062] Fig. 9 is a flowchart showing an example of the operation of the MMU 13 when writing data to the memory 15 according to the second configuration example. The processes of steps S11 to S13 in the flowchart shown in Fig. 9 are the same as those of steps S11 to S13 in Fig. 6. In contrast, the flowchart shown in Fig. 9 does not include the processes of steps S14 to S18 shown in Fig. 6, but instead includes step S16A. In step S16A, the MMU 13 writes the compressed data to the compressed block 15c of the memory 15, starting from the base address. In the second configuration example, the base address is an address that is the starting point of the compressed block 15c.

[0063] Fig. 10 is a flowchart showing an example of the operation of the MMU 13 when reading data from the memory 15 in the second configuration example. When the second configuration example is applied, the data read from the memory 15 is compressed data. Therefore, in the flowchart shown in Fig. 10, the process of step S24 in the flowchart of Fig. 7, i.e., the determination of whether the data is compressed or uncompressed, is not performed, and the process proceeds from step S23 to step S25, where the data is decompressed. Except for this point, the process of the flowchart of Fig. 10 is the same as the process of the flowchart of Fig. 7.

[0064] The information processing device 1 according to the embodiment includes a processor 11, a cache memory 12 that stores data used by the processor 11, an integrated circuit 10 including a compressor 14A, a decompressor 14B, and a storage control device (MMU) 13, and a memory 15 connected to the integrated circuit 10. When storing target data in the memory 15, the MMU 13 compresses the target data using the compressor 14A and transmits the compressed target data to the memory 15. When compressed target data is received from the memory 15, the MMU 13 compresses the target data using the decompressor 14B and transmits the compressed target data to the memory 15. The compressed target data is decompressed, and the decompressed target data is written to the cache memory 12.

[0065] This reduces the amount of data transmitted between the integrated circuit 10 and the memory 15, thereby increasing the transmission band (throughput) between the integrated circuit 10 and the memory 15. This increase in throughput reduces the time required to read from and write to the memory 15, thereby improving the performance of the processor 11.

[0066] In the information processing device 1, the storage area of ​​the memory 15 is partitioned into blocks for storing target data. When the size of the target data in an uncompressed state does not exceed the size of the block 15a but the size of the target data in a compressed state exceeds the size of the block 15a, the MMU 13 transmits the target data in an uncompressed state to the memory 15. This makes it possible to reduce the amount of data transmitted to the memory 15.

[0067] Furthermore, the MMU 13 transmits the compressed target data to the memory 15 together with information (compression bit) indicating the compression state of the target data. The memory 15 stores the compressed bit and the compressed target data in one of the blocks 15a. When the target data and the compressed bit are received from the memory 15, the MMU 13 decompresses the target data using a decompressor. In this manner, the compression bit can be used to determine whether or not data read from the memory 15 needs to be decompressed. As a configuration of the memory 15 suitable for this configuration, an ECC memory is applied to the memory 15, and the compressed bit is stored in a storage area (field) 15b of an error correcting code of the ECC memory.

[0068] In addition, in the embodiment, as a second configuration example of the memory 15, it can be specified that data is stored in the storage area of ​​the memory 15 in units of compressed blocks 15c having a size larger than the size of the blocks 15a. Then, the compressed target data transmitted to the memory 15 is stored in the compressed blocks 15c. By using the compressed blocks 15c in this way, even if the data size increases due to compression, the compressed data can be stored in the compressed blocks 15c, and overwriting of adjacent blocks can be avoided. The configurations of the above-described embodiment can be appropriately combined within a range that does not deviate from the purpose of the invention. [Explanation of symbols]

[0069] 1. Information processing device 2. Bus 10. Integrated circuits (microprocessor LSI) 11. Processor 12. Cache memory 13. Memory control unit (MMU) 14A···Compressor 14B...Decompressor 15. Memory 15a···Block 15b: Compression bit storage area (field) 15c···Compression block 16. Management table

Claims

1. an integrated circuit including a processor, a cache memory for storing data used by the processor, a compressor and a decompressor, and a storage controller; a memory coupled to the integrated circuit; when storing target data in the memory, the storage control device compresses the target data using the compressor, transmits the target data in a compressed state to the memory, and when the target data in a compressed state is received from the memory, decompresses the target data in a compressed state using the decompressor, and writes the target data after decompression to the cache memory; The storage control device transmits the target data in an uncompressed state to the memory when the storage area of ​​the memory is partitioned into blocks of a predetermined size capable of storing the target data, and when the size of the target data in an uncompressed state does not exceed the size of the block, but the size of the target data in a compressed state exceeds the size of the block. Information processing device.

2. the storage control device transmits the target data in a compressed or uncompressed state to the memory together with information indicating whether the target data is compressed or uncompressed; The memory stores the information and the target data in any one of the blocks; When the target data and the information are received from the memory, and the information indicates a compression state of the target data, the storage control device decompresses the target data by the decompressor. The information processing device according to claim 1 .

3. The memory is an error correcting code memory, and the information is stored in a storage area of ​​the error correcting code in the error correcting code memory. The information processing device according to claim 2 .

4. A method for storing data in a storage device, comprising: a processor; a cache memory for storing data used by said processor; and a storage control device included in an integrated circuit together with a compressor and a decompressor, compressing the target data using the compressor when the target data is stored in a memory coupled to the integrated circuit; transmitting the target data in a compressed form to the memory; decompressing the compressed target data using the decompressor when the compressed target data is received from the memory; writing the decompressed target data into the cache memory; A storage control method comprising: transmitting the target data in an uncompressed state to the memory when the storage area of ​​the memory is partitioned into block units having a predetermined size, and the size of the target data in an uncompressed state does not exceed the size of the block, but the size of the target data in a compressed state exceeds the size of the block.

5. The storage control device transmits the target data in a compressed or uncompressed state to the memory together with information indicating whether the target data is in a compressed or uncompressed state, and when the target data and the information are received from the memory and the information indicates a compressed state of the target data, decompresses the target data using the decompressor.

5. The storage control method according to claim 4.

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