Multilayer ceramic electronic components and their mounting substrates

Abstract

The present invention relates to a multilayer ceramic electronic component and a mounting substrate for the same. According to one embodiment of the present invention, a multilayer ceramic electronic component and its mounting substrate are provided that have a new structure and low ESL characteristics by merging multiple three-terminal capacitors mounted on the power terminal of an AP (Application Processor) in order to further reduce the mounting area when mounted on a printed circuit board.

Description

[Technical field]

[0001] The present invention relates to a multilayer ceramic electronic component and a mounting substrate thereof. [Background technology]

[0002] Electronic components that use ceramic materials include capacitors, inductors, piezoelectric elements, varistors, and thermistors.

[0003] Among such ceramic electronic components, multi-layer ceramic capacitors (MLCCs) have the advantages of being small, having a high capacitance, and being easy to mount, and are useful as decoupling capacitors arranged in high-frequency circuits such as the power supply circuits of LSIs.

[0004] At this time, the stability of the power supply circuit depends on the ESL of the multilayer ceramic capacitor, and the stability is particularly high with a low ESL.

[0005] Therefore, in order to stabilize the power supply circuit, the multilayer ceramic capacitor needs to have a lower ESL value, and such a requirement is further increased by the trend toward higher frequencies and higher currents in electronic devices.

[0006] Furthermore, multilayer ceramic capacitors are used as EMI filters in addition to decoupling capacitors. In this case, it is preferable for the ESL to be low in order to improve the characteristics of removing and attenuating high-frequency noise.

[0007] Recently, the current consumption of the AP (Application Processor) power supply of a smartphone is becoming higher and higher to accommodate the diversification, speed, and sophistication of its functions.

[0008] Due to this trend, the method of connecting several multilayer ceramic capacitors in parallel to reduce the overall impedance is evolving to use capacitors with low ESL characteristics, such as three-terminal capacitors or VLC (Vertical Laminate Capacitors), which are three-terminal capacitors with internal electrodes mounted vertically to the board surface.

[0009] As described above, a large number of 3-terminal low ESL capacitors are used at the power supply end of an AP (Application Processor) in order to reduce the mounting area and increase functionality. However, as more and more 3-terminal capacitors are used, there is a growing demand for a method to further reduce the mounting area.

[0010] In other words, if the mounting area can be further reduced by replacing multiple three-terminal capacitors with capacitors having even lower ESL, it will be useful to designers as it will provide greater flexibility when designing the power supply terminal of smartphones.

[0011] FIG. 1 is a perspective view showing a multilayer ceramic capacitor in which two conventional three-terminal multilayer ceramic capacitors are simply combined.

[0012] Referring to FIG. 1, there is shown a multilayer ceramic capacitor 10' obtained by simply combining two conventional three-terminal multilayer ceramic capacitors 10 while maintaining the same internal and external electrode structures of the conventional three-terminal multilayer ceramic capacitor 10.

[0013] That is, the multilayer ceramic capacitor 10' obtained by simply combining two conventional three-terminal multilayer ceramic capacitors 10 has the same structure as the conventional three-terminal multilayer ceramic capacitor 10, but is larger in size.

[0014] In other words, if the size of a conventional three-terminal multilayer ceramic capacitor 10 is 1209 (length 1.2 mm, width 0.9 mm), a multilayer ceramic capacitor 10' that is simply combined to a size sufficient to achieve the capacitance of two capacitors has a size of approximately 1910 (length 1.9 mm, width 1.0 mm).

[0015] Although the above-mentioned simple merged structure has the effect of reducing the board mounting area, it has a problem that it cannot meet the recent trend of smartphones in which realizing low ESL is important because it increases ESL.

[0016] FIG. 2 is a graph showing the change in ESL component with frequency for two conventional three-terminal multilayer ceramic capacitors of FIG. 1 and a multilayer ceramic capacitor obtained by simply combining them.

[0017] Referring to FIG. 2, it can be seen that the ESL of the multilayer ceramic capacitor obtained by simply merging two conventional three-terminal multilayer ceramic capacitors connected in parallel is higher than that of the two conventional three-terminal multilayer ceramic capacitors connected in parallel.

[0018] Specifically, the ESL value of a conventional three-terminal multilayer ceramic capacitor is about 32 pH, whereas the ESL value of a multilayer ceramic capacitor that is a simple combination of these is about 56 pH. This is a very high ESL value, which poses a problem when applied to the power supply terminal of an AP (Application Processor). [Prior art documents] [Patent documents]

[0019] [Patent Document 1] JP 2015-026843 A Summary of the Invention [Problem to be solved by the invention]

[0020] In order to further reduce the mounting area when mounted on a printed circuit board, multiple three-terminal capacitors mounted on the AP (Application Processor) power supply end are combined to provide a capacitor with a new structure that has low ESL characteristics. [Means for solving the problem]

[0021] According to one embodiment of the present invention, a novel capacitor structure is provided that combines multiple three-terminal capacitors and has low ESL characteristics.

[0022] According to one embodiment of the present invention, there is provided a multilayer ceramic electronic component comprising: a body including a plurality of dielectric layers, the body including a plurality of first and second internal electrodes of different polarities arranged alternately with the dielectric layers in between, and having at least one lead portion extending to a side of the dielectric layers; and a plurality of external electrodes arranged outside the body and connected to the first and second internal electrodes, the external electrodes including first and second external electrodes arranged on a first surface and a second surface of an outer surface of the body, and m (m≧3) third and fourth external electrodes arranged in equal numbers on third and fourth surfaces adjacent to the first and second surfaces and facing each other, respectively, wherein the polarities between adjacent electrodes of the external electrodes are all different.

[0023] According to another embodiment of the present invention, there is provided a multilayer ceramic electronic component comprising: a body including a plurality of dielectric layers, the body including a plurality of first internal electrodes and second internal electrodes having different polarities and arranged alternately with the dielectric layers in between; and a plurality of external electrodes arranged on the outside of the body and connected to the first and second internal electrodes, the external electrodes including first and second external electrodes arranged on first and second surfaces of an outer surface of the body, third and fourth external electrodes arranged on third and fourth surfaces adjacent to the first and second surfaces and facing each other, and n (n≧3) via electrodes penetrating the body and the plurality of first and second internal electrodes and arranged to be exposed to fifth and sixth surfaces of the body, the via electrodes being connected to any one of the first and second internal electrodes.

[0024] According to another embodiment of the present invention, there is provided a mounting substrate in which the multilayer ceramic electronic component is mounted on a printed circuit board. Effect of the Invention

[0025] According to one embodiment of the present invention, while satisfying the low ESL characteristics of conventional three-terminal multilayer ceramic capacitors, multiple capacitors can be combined into one capacitor, which is advantageous in reducing the mounting area when mounting on a board.

[0026] In addition, the difficulty of wiring during substrate mounting can be reduced compared to existing multi-terminal array type capacitor products, and the present invention can replace multi-terminal array type capacitors that have been difficult to apply in the past.

[0027] Furthermore, since the capacitor according to an embodiment of the present invention has internal electrodes arranged horizontally relative to the substrate mounting surface, it can be more advantageously applied to low profile products compared to a three-terminal capacitor in which the internal electrodes are stacked vertically. [Brief description of the drawings]

[0028] [Figure 1] FIG. 1 is a perspective view illustrating a multilayer ceramic capacitor in which two conventional three-terminal multilayer ceramic capacitors are simply combined. [Diagram 2] 2 is a graph showing changes in ESL components according to frequency for two conventional three-terminal multilayer ceramic capacitors of FIG. 1 and a multilayer ceramic capacitor obtained by simply combining them. [Diagram 3] 1 is a perspective view illustrating a multilayer ceramic capacitor according to a first embodiment of the present invention; [Figure 4] 1 is a top plan view of a multilayer ceramic capacitor according to a first embodiment of the present invention; [Diagram 5] 1 is a schematic view showing first and second internal electrodes of a multilayer ceramic capacitor according to a first embodiment of the present invention. [Figure 6]FIG. 4 is a perspective view illustrating a multilayer ceramic capacitor according to a second embodiment of the present invention. [Figure 7] FIG. 5 is a top plan view of a multilayer ceramic capacitor according to a second embodiment of the present invention. [Figure 8] 5 is a schematic diagram showing first and second internal electrodes and via electrodes of a multilayer ceramic capacitor according to a second embodiment of the present invention. FIG. [Figure 9] 4 is a graph showing changes in ESL components according to frequency of the multilayer ceramic capacitor according to the comparative example and the first embodiment of the present invention. [Figure 10] 11 is a graph showing changes in ESL components according to frequency of a comparative example and a multilayer ceramic capacitor according to a second embodiment of the present invention. [Figure 11] 1 is a perspective view illustrating a multilayer ceramic capacitor according to a first embodiment of the present invention mounted on a printed circuit board; DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0029] Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings. However, the embodiments of the present invention can be modified into various other forms, and the scope of the present invention is not limited to the embodiments described below. Furthermore, the embodiments of the present invention are provided to more completely explain the present invention to those having average knowledge in the art. Therefore, the shapes and sizes of elements in the drawings may be enlarged or reduced (or highlighted or simplified) for a clearer description.

[0030] In addition, components having the same function within the same concept shown in the drawings of each embodiment will be described using the same reference numerals.

[0031] Hereinafter, a multilayer ceramic electronic component according to an embodiment of the present invention will be described, and in particular, a multilayer ceramic capacitor will be described, but the present invention is not limited thereto.

[0032] <Multilayer ceramic capacitor> In order to clearly explain the embodiments of the present invention, the directions of the capacitor body are defined as X, Y and Z shown in the drawings, which respectively indicate the length direction, width direction and thickness direction, where the thickness direction may be used in the same concept as the lamination direction of the dielectric layers and the internal electrodes.

[0033] In this embodiment, for ease of explanation, both sides of the capacitor body 110 facing in the X direction are set as the first and second sides 1, 2, both sides facing in the Y direction and connecting the ends of the first and second sides 1, 2 are set as the third and fourth sides 3, 4, and both sides facing in the Z direction and connecting the ends of the first and second sides 1, 2 and the third and fourth sides 3, 4 are set as the fifth and sixth sides 5, 6. Here, the sixth side 6 can be used in the same concept as the mounting surface.

[0034] According to one embodiment of the present invention, a novel capacitor structure is provided that combines multiple three-terminal capacitors and has low ESL characteristics.

[0035] Recently, the current consumption of the AP (Application Processor) power supply of a smartphone is becoming higher and higher to accommodate the diversification, speed, and sophistication of its functions.

[0036] Due to this trend, a method of connecting several multilayer ceramic capacitors in parallel to reduce the overall impedance is being adopted, using capacitors with low ESL characteristics such as three-terminal capacitors or VLC (Vertical Laminate Capacitors), which are three-terminal capacitors with internal electrodes mounted vertically to the board surface.

[0037] As described above, a large number of 3-terminal low ESL capacitors are used at the power supply end of an AP (Application Processor) in order to reduce the mounting area and increase functionality. However, there is a demand for a method to further reduce the mounting area by using multiple 3-terminal capacitors.

[0038] According to an embodiment of the present invention, by replacing such a plurality of three-terminal capacitors with a capacitor having a lower ESL, the mounting area can be further reduced.

[0039] In addition, compared to existing multi-terminal array type capacitor products, the difficulty of wiring when mounting on a board can be reduced, and it can replace multi-terminal array type capacitors that have been difficult to apply in the past.

[0040] In addition, since the capacitor according to an embodiment of the present invention has internal electrodes arranged horizontally relative to the substrate mounting surface, it can be more advantageously applied to low profile products compared to a three-terminal capacitor in which the internal electrodes are stacked vertically.

[0041] In the following, an embodiment of the present invention that solves the above-mentioned conventional problems will be specifically described, but the present invention is not limited to this embodiment.

[0042] FIG. 3 is a perspective view illustrating a multilayer ceramic capacitor according to a first embodiment of the present invention.

[0043] FIG. 4 is a top plan view of the multilayer ceramic capacitor according to the first embodiment of the present invention.

[0044] FIG. 5 is a schematic diagram showing first and second internal electrodes of the multilayer ceramic capacitor according to the first embodiment of the present invention.

[0045] As shown in FIG. 3, the multilayer ceramic capacitor 100 according to the first embodiment of the present invention includes a body 110 and first to fourth external electrodes 131, 132, 133, and 134 formed on the outer surface of the body 110, respectively.

[0046] Referring to FIG. 3, the first and second external electrodes 131 and 132 may be arranged one by one, and the third and fourth external electrodes 133 and 134 may be arranged at least three by one.

[0047] Specifically, the multilayer ceramic capacitor 100 according to the first embodiment of the present invention includes a body 110 including a plurality of first internal electrodes 121 and second internal electrodes 122 of different polarities, which are alternately arranged with a plurality of dielectric layers 111 sandwiched therebetween and have at least one lead portion 121a, 121b, 122a, 122b, 122c, 122d extending to a side surface of the dielectric layer 111, and a plurality of external electrodes 131, 132, 133, 134 arranged on the outside of the body 110 and connected to the first and second internal electrodes 121 and 122, where the external electrodes include first and second external electrodes 131 and 132 arranged on a first surface and a second surface of the outer surface of the body 110, and m (m≧3) third and fourth external electrodes 133 and 134 arranged in equal numbers on third and fourth surfaces adjacent to the first and second surfaces and facing each other.

[0048] FIG. 3 shows an example of an eight-terminal multilayer ceramic capacitor structure in which the above m is 3, but the present invention is not limited to this.

[0049] The body 110 is formed by laminating a plurality of dielectric layers 111. A plurality of first and second internal electrodes 121 and 122 are arranged in the body 110 and separated from each other by the dielectric layers 111. The first and second internal electrodes are arranged alternately such that the internal electrodes of different polarities face each other with one dielectric layer 111 in between, thereby forming a capacitance.

[0050] In the first embodiment, the first external electrode 131 and the second external electrode 132 are disposed on a first surface and a second surface, which are both side surfaces of the outer surface of the body 110 in the length direction of the body 110.

[0051] Three third external electrodes 133 and three fourth external electrodes 134 are provided. External electrodes having different polarities may be alternately arranged on one side of the body 110 and the opposite side thereof.

[0052] The one side surface and the other side surface opposite thereto of the body 110 may be a third surface and a fourth surface in the width direction of the body 110.

[0053] That is, as shown in FIG. 3, the third and fourth external electrodes 133 and 134 may be arranged such that the external electrodes of different polarities are located in corresponding regions of the third and fourth surfaces of the body 110 and the external electrodes of different polarities are adjacent to each other on the same side.

[0054] According to the first embodiment of the present invention, the third and fourth external electrodes 133 and 134 are arranged in threes each in corresponding regions of the third and fourth surfaces of the body 110, so that the multilayer ceramic capacitor 100 according to the first embodiment has an eight-terminal structure including the first and second external electrodes 131 and 132.

[0055] According to the first embodiment of the present invention, the m may be an odd number.

[0056] When m is an odd number of 3 or more, multiple capacitors can be combined into one capacitor while maintaining the low ESL characteristics of a conventional three-terminal multilayer ceramic capacitor, which is more effective in reducing the mounting area when mounting on a board.

[0057] Furthermore, when the above m is an odd number of 3 or more, a lower ESL value can be achieved.

[0058] Referring to FIG. 4, in the multilayer ceramic capacitor 100 according to the first embodiment of the present invention, the external electrodes 131, 132, 133, and 134 are characterized in that adjacent electrodes have opposite polarities.

[0059] As shown in FIG. 4, when the first and second external electrodes 131, 132 have a (+) polarity, the external electrodes adjacent to the first and second external electrodes 131, 132 among the third and fourth external electrodes 133, 134 have a (-) polarity, and the third and fourth external electrodes 133, 134 are arranged such that the polarities of the adjacent external electrodes are different from each other.

[0060] As described above, according to the first embodiment of the present invention, the external electrodes 131, 132, 133, and 134 are characterized in that the polarities between adjacent electrodes are all opposite to each other. This allows multiple capacitors to be combined into one capacitor while still maintaining the low ESL characteristics of a conventional three-terminal multilayer ceramic capacitor, thereby providing an excellent effect of reducing the mounting area when mounting on a board.

[0061] In the case of simply combining a plurality of conventional three-terminal multilayer ceramic capacitors or in the case of a general multilayer ceramic capacitor having a multi-terminal array configuration, it is difficult to obtain low ESL characteristics as in the first embodiment of the present invention, since all of the adjacent external electrodes are not arranged with different polarities as described above.

[0062] According to the first embodiment of the present invention, the total number of the external electrodes 131, 132, 133, and 134 and the number of the current paths may be the same.

[0063] That is, in the multilayer ceramic capacitor according to the first embodiment of the present invention, the total number of the external electrodes 131, 132, 133, and 134 is the same as the number of electrode paths (current paths), so that the number of electrode paths is greater than that of a general multilayer ceramic capacitor having a multi-terminal array type, and low ESL characteristics can be obtained.

[0064] Specifically, the ESL characteristics of the multilayer ceramic capacitor depend on the length and number of electrode paths (current paths). When the length of the electrode paths (current paths) is short and when the number of electrode paths (current paths) is large, the multilayer ceramic capacitor can have a low ESL value.

[0065] According to the first embodiment of the present invention, since the polarities of adjacent external electrodes are all arranged differently, current paths are generated in the total number of external electrodes 131, 132, 133, and 134, and the number of current paths can be maximized, resulting in a low ESL value.

[0066] According to the first embodiment of the present invention, the first and second external electrodes 131 and 132 may have the same polarity.

[0067] Referring to FIG. 4, the first and second external electrodes 131 and 132 are shown to have a (+) polarity, but are not limited thereto and may have a (-) polarity by being connected to other internal electrodes.

[0068] Also, according to the first embodiment of the present invention, the third and fourth external electrodes 133 and 134 may be arranged such that the external electrodes having the same polarity are located in areas facing each other on the third and fourth surfaces.

[0069] The third and fourth external electrodes 133 and 134 may be disposed with the same polarity in the regions facing each other of the third and fourth surfaces, so that the polarities of adjacent external electrodes may be arranged differently as in the first embodiment of the present invention. As a result, the number of electrode paths may be maximized, and a multilayer ceramic capacitor having a low ESL value may be realized.

[0070] The polarity of the external electrodes in this embodiment can be understood more specifically based on the arrangement of the internal electrodes and the connection relationship with the external electrodes, which will be described later.

[0071] Referring to FIG. 5, the multilayer ceramic capacitor 100 according to the first embodiment of the present invention includes a plurality of first and second internal electrodes 121, 122 arranged alternately in the body 110 such that the internal electrodes 121, 122 of different polarities face each other across the dielectric layer 111.

[0072] The shapes of the first and second internal electrodes 121, 122 are not particularly limited, and the connection relationship between the first and second internal electrodes 121, 122 and the first to fourth external electrodes 131, 132, 133, 134 will be mainly described in detail below.

[0073] In the first embodiment of the present invention, the first internal electrode 121 may include leads 121a and 121b exposed to first and second surfaces, which are both end surfaces in the length direction of the body 110, and exposed to third and fourth surfaces, which are both side surfaces in the width direction of the body 110, respectively.

[0074] The leads 121a and 121b including the first internal electrode 121 are exposed to the third and fourth surfaces, which are both side surfaces in the width direction of the body, and may be one each, but are not necessarily limited thereto.

[0075] Meanwhile, the second internal electrode 122 includes leads 122a, 122b, 122c, and 122d that are exposed to the third and fourth surfaces, which are both widthwise sides of the body 110, and are spaced apart at a certain distance so as to be electrically insulated from the leads 121a and 121b of the first internal electrode 121.

[0076] The leads 122a, 122b, 122c, and 122d including the second internal electrode 122 are exposed to the third and fourth surfaces, which are both side surfaces in the width direction of the main body, and may be two each, but are not necessarily limited thereto.

[0077] That is, like the first embodiment of the present invention, the second internal electrode 122 may include two leads 122a, 122b, 122c, and 122d exposed on one side and the other side, respectively, to be connected to the external electrodes 131, 132, 133, and 134 of the eight-terminal multilayer ceramic capacitor.

[0078] The first internal electrode 121 is exposed to a first surface and a second surface, which are both side surfaces in the length direction of the body 110, and is electrically connected to the first and second external electrodes 131 and 132.

[0079] In addition, the first internal electrode 121 includes leads 121a and 121b exposed to third and fourth surfaces, which are both widthwise sides of the body 110, respectively, and is electrically connected to the third and fourth external electrodes 133 and 134 through the leads.

[0080] In addition, the second internal electrode 122 includes leads 122a, 122b, 122c, and 122d that are exposed to third and fourth surfaces, which are both widthwise side surfaces of the body 110, and are formed at a certain distance apart so as to be electrically insulated from the leads 121a and 121b of the first internal electrode 121, and the second internal electrode 122 is electrically connected to the third and fourth external electrodes 133 and 134 through the leads 122a, 122b, 122c, and 122d.

[0081] Due to this connection structure, the multilayer ceramic capacitor according to the first embodiment of the present invention can realize an 8-terminal capacitor structure, and can obtain the same effect as when two conventional 3-terminal capacitors are combined.

[0082] That is, according to the first embodiment of the present invention, while satisfying the low ESL characteristics of the conventional three-terminal multilayer ceramic capacitor, multiple capacitors can be merged into one capacitor, which is excellent in reducing the mounting area when mounting on a board.

[0083] Whereas the size of a conventional three-terminal multilayer ceramic capacitor is 1209 (length 1.2 mm, width 0.9 mm), the multilayer ceramic capacitor according to the first embodiment of the present invention has a size of about 1910 (length 1.9 mm, width 1.0 mm) and has an 8-terminal capacitor structure.

[0084] In addition, compared to existing multi-terminal array type capacitor products, the difficulty of wiring when mounting on a board can be reduced, and it can replace multi-terminal array type capacitors that have been difficult to apply in the past.

[0085] According to the first embodiment of the present invention, the thickness of the body 110 is smaller than its width.

[0086] Since the thickness of the body 110 is smaller than its width, it can be advantageously applied to low profile products, unlike a three-terminal capacitor in which internal electrodes are vertically stacked.

[0087] In addition, since the capacitor according to the first embodiment of the present invention has internal electrodes arranged horizontally relative to the board mounting surface, it can be more advantageously applied to low profile type products than a three-terminal capacitor in which the internal electrodes are stacked vertically.

[0088] According to the first embodiment of the present invention, the body 110 includes an active part including a plurality of first and second internal electrodes 121, 122 as a part that contributes to forming a capacitance, and a cover part that does not contribute to forming a capacitance and is disposed on the upper and lower parts of the active part, and the cover part may have a smaller thickness in the area disposed on the lower part than in the area disposed on the upper part.

[0089] By arranging the lower cover part so that its thickness is smaller than that of the upper cover part, the length of the electrode path (current path) can be shortened, thereby realizing a multilayer ceramic capacitor having a lower ESL value.

[0090] FIG. 6 is a perspective view illustrating a multilayer ceramic capacitor according to a second embodiment of the present invention.

[0091] FIG. 7 is a top plan view of the multilayer ceramic capacitor according to the second embodiment of the present invention.

[0092] FIG. 8 is a schematic diagram showing first and second internal electrodes and via electrodes of a multilayer ceramic capacitor according to a second embodiment of the present invention.

[0093] As shown in FIG. 6, the multilayer ceramic capacitor 200 according to the second embodiment of the present invention includes a body 210, first to fourth external electrodes 231, 232, 233, 234, and a via electrode 235 formed on an outer surface of the body 210.

[0094] Referring to FIG. 6, the first to fourth external electrodes 231, 232, 233, and 234 may be arranged one by one, and at least three via electrodes 235 may be arranged.

[0095] Specifically, the multilayer ceramic capacitor 200 according to the second embodiment of the present invention includes a body 210 including a plurality of dielectric layers 211, a plurality of first internal electrodes 221 and second internal electrodes 222 having different polarities and alternately arranged with the dielectric layers 211 in between, and a plurality of external electrodes 231, 232, 233, 234, and 235 arranged on the outside of the body 210 and connected to the first and second internal electrodes 221 and 222. The external electrodes are disposed on an outer surface of the body 210. The semiconductor device includes first and second external electrodes 231, 232 arranged on the first and second surfaces, third and fourth external electrodes 233, 234 arranged on third and fourth surfaces adjacent to the first and second surfaces and facing each other, and n (n≧3) via electrodes 235 penetrating the body 210 and a plurality of first and second internal electrodes 221, 222 and arranged to be exposed on fifth and sixth surfaces of the body, and the via electrode 235 is connected to one of the first and second internal electrodes 221, 222.

[0096] FIG. 6 shows an example of a multilayer ceramic capacitor structure in which n is 3 and three via electrodes 235 are exposed and arranged on each of the fifth and sixth surfaces of the body 210, but is not limited thereto.

[0097] In the second embodiment, the first and second external electrodes 231 and 232 are disposed on a first surface and a second surface, which are both side surfaces of the outer surface of the body 210 in the length direction of the body.

[0098] Also, the third external electrode 233 and the fourth external electrode 234 are disposed on third and fourth surfaces adjacent to the first and second surfaces of the body 210, extending to the first and second surfaces, respectively.

[0099] In the second embodiment, a structure in which one each of the first to fourth external electrodes 231, 232, 233, and 234 is disposed is disclosed, but the present invention is not necessarily limited to this.

[0100] The via electrodes 235 penetrate the body 210 and the first and second internal electrodes 221 and 222, and are disposed so that three or more via electrodes 235 are exposed on each of a fifth surface and a sixth surface of the body 210. The fifth and sixth surfaces of the body 210 may be upper and lower surfaces of the body 210, and in particular, the sixth surface 6 may be a mounting surface when the multilayer ceramic capacitor 200 is mounted on a printed circuit board.

[0101] According to the second embodiment of the present invention, the first to fourth external electrodes 231, 232, 233, 234 are arranged in corresponding regions of the first to fourth surfaces of the main body 210, respectively, and a via electrode 235 is arranged and exposed on the fifth and sixth surfaces of the main body, thereby forming a three-terminal multilayer ceramic capacitor structure having the via electrode 235.

[0102] 7, in the multilayer ceramic capacitor 200 according to the second embodiment of the present invention, the n via electrodes 235 have the same polarity. The via electrode 235 is connected to one of the first and second internal electrodes 221 and 222, and thus the n via electrodes 235 have the same polarity.

[0103] 7, the via electrode 235 penetrates through both the first and second internal electrodes 221 and 222 and is electrically connected to the first internal electrode 221 but is electrically insulated from the second internal electrode 222. Thus, the via electrode 235 may have a (+) polarity.

[0104] Alternatively, when the via electrode 235 is electrically insulated from the first internal electrode 221 and electrically connected to the second internal electrode 222, it may have a negative polarity.

[0105] The via electrode 235 and the first and second external electrodes 231 and 232 may have the same polarity. In addition, the polarity of the via electrode 235 and the first and second external electrodes 231 and 232 having the same polarity may be different from the polarity of the third and fourth external electrodes 233 and 234.

[0106] As shown in FIG. 7, when the via electrode 235 has a (+) polarity, the first and second external electrodes 231 and 232 may also have a (+) polarity, and the third and fourth external electrodes 233 and 234 may have a (-) polarity.

[0107] As described above, according to the second embodiment of the present invention, the via electrode 235 and the first and second external electrodes 231, 232 have the same polarity, and the polarities of the via electrode 235 and the first and second external electrodes 231, 232 are different from the polarities of the third and fourth external electrodes 233, 234. Therefore, a plurality of three-terminal multilayer ceramic capacitors can be merged into one capacitor, and an effect of reducing the mounting area when mounting a substrate is excellent.

[0108] According to the second embodiment of the present invention, when the total number of the external electrodes is n+4 (n≧3), the number of the electrode paths (current paths) may be 2n+4 (n≧3).

[0109] That is, in the multilayer ceramic capacitor according to the second embodiment of the present invention, the via electrode 235 and the first and second external electrodes 231, 232 have the same polarity, and the polarities of the via electrode 235 and the first and second external electrodes 231, 232 are different from the polarities of the third and fourth external electrodes 233, 234. Therefore, the number of electrode paths can be 2n+4 (n≧3), which is greater than the number of electrode paths in a general multilayer ceramic capacitor having a multi-terminal array, and low ESL characteristics can be obtained.

[0110] Referring to FIG. 8, the multilayer ceramic capacitor 200 according to the second embodiment of the present invention includes a plurality of first and second internal electrodes 221, 222 alternately arranged in the body 210 such that the internal electrodes 221, 222 of different polarities face each other across the dielectric layer 211.

[0111] The shapes of the plurality of first and second internal electrodes 221, 222 are not particularly limited.

[0112] In the second embodiment of the present invention, the first internal electrode 221 may include leads 221a and 221b exposed to first and second surfaces, which are both side surfaces in the length direction of the body 210, respectively.

[0113] Meanwhile, the second internal electrode 222 is exposed to third and fourth surfaces, which are both side surfaces in the width direction of the body 210 .

[0114] The first internal electrode 221 includes leads 221a and 221b exposed to first and second surfaces of both longitudinal sides of the body 210, respectively, and is electrically connected to the first and second external electrodes 231 and 232 through the leads 221a and 221b.

[0115] The second internal electrode 222 is exposed to third and fourth surfaces, which are both widthwise sides of the body 210 , and is electrically connected to the third and fourth external electrodes 233 and 234 .

[0116] Meanwhile, the via electrodes 235 penetrate the body 210 and the first and second internal electrodes 221 and 222 and are exposed to the fifth and sixth surfaces of the body 210, respectively.

[0117] According to the second embodiment of the present invention, the via electrode 235 may be electrically connected to the first internal electrode 221 or the second internal electrode 222 of the plurality of first and second internal electrodes 221 and 222 .

[0118] The number of via electrodes 235 connected to the first internal electrode 221 or the second internal electrode 222 may be three or more. In the present embodiment, the number of via electrodes 235 is three, and one multilayer ceramic capacitor according to the second embodiment can provide the same effect as that obtained by combining two conventional three-terminal capacitors.

[0119] According to the second embodiment of the present invention, at least one of the first internal electrode 221 and the second internal electrode 222 has one or more through holes formed therein, and the via electrode 235 passes through the through holes.

[0120] When the via electrode 235 is electrically connected to the first internal electrode 221, the via electrode 235 passing through a through hole does not contact an inner peripheral surface of the through hole in the second internal electrode 222. That is, the via electrode 235 in the second internal electrode 222 is spaced a certain distance from the inner peripheral surface of the through hole, and is thus electrically insulated from the second internal electrode 222.

[0121] Similarly, when the via electrode 235 is electrically connected to the second internal electrode 222, the via electrode 235 passing through a through hole does not contact the inner peripheral surface of the through hole in the first internal electrode 221. That is, the via electrode 235 in the first internal electrode 221 is spaced a certain distance from the inner peripheral surface of the through hole, and is thus electrically insulated from the first internal electrode 221.

[0122] According to the second embodiment of the present invention, the lead-out portion of the via electrode 235 formed on the fifth and sixth surfaces, which are the upper and lower surfaces, of the body 210 may be formed in a bump shape. Alternatively, the lead-out portion of the via electrode 235 may be formed in a pad shape.

[0123] According to the embodiment of the present invention, the lead-out portion of the via electrode 235 and the first to fourth external electrodes 231, 232, 233, and 234 serve as external terminals of the multilayer ceramic capacitor 200. Therefore, current flows not only from the lower portion of the external electrodes but also from the via electrodes. As a result, the external electrodes and the via electrodes form inductances connected in parallel with each other. Therefore, the overall ESL value is further reduced compared to the conventional art.

[0124] Due to this connection structure, the multilayer ceramic capacitor 200 according to the second embodiment of the present invention can realize a three-terminal capacitor structure including via electrodes, and can obtain the same effect as when two conventional three-terminal capacitors are combined.

[0125] That is, according to one embodiment of the present invention, while satisfying the low ESL characteristics of the conventional three-terminal multilayer ceramic capacitor, multiple capacitors can be merged into one capacitor, which is excellent in reducing the mounting area when mounting on a board.

[0126] While the size of a conventional three-terminal multilayer ceramic capacitor is 1209 (length 1.2 mm, width 0.9 mm), the multilayer ceramic capacitor according to the second embodiment of the present invention has a size of about 1910 (length 1.9 mm, width 1.0 mm) and has a three-terminal capacitor structure including via electrodes.

[0127] In addition, compared to existing multi-terminal array type capacitor products, the difficulty of wiring when mounting on a board can be reduced, and it can replace multi-terminal array type capacitors that have been difficult to apply in the past.

[0128] According to the second embodiment of the present invention, the thickness of the body 210 is smaller than the width. Since the thickness of the body 210 is smaller than the width, it can be advantageously applied to low profile products, unlike a three-terminal capacitor in which internal electrodes are vertically stacked.

[0129] In addition, since the capacitor 200 according to the second embodiment of the present invention has internal electrodes arranged horizontally relative to the substrate mounting surface, it can be more advantageously applied to low profile products than a three-terminal capacitor in which the internal electrodes are stacked vertically.

[0130] According to the second embodiment of the present invention, the body 210 includes an active part including a plurality of first and second internal electrodes 221, 222 as a part that contributes to forming a capacitance, and a cover part that does not contribute to forming a capacitance and is disposed on the upper and lower parts of the active part, and the cover part may have a smaller thickness in the area disposed on the lower part than in the area disposed on the upper part.

[0131] By arranging the lower cover part so that its thickness is smaller than that of the upper cover part, the length of the electrode path (current path) can be shortened, thereby realizing a multilayer ceramic capacitor having a lower ESL value.

[0132] FIG. 9 is a graph showing changes in ESL components according to frequency of the multilayer ceramic capacitor according to the comparative example and the first embodiment of the present invention.

[0133] Referring to FIG. 9, it can be seen that the ESL value of the conventional three-terminal multilayer ceramic capacitor as a comparative example is almost similar to the ESL value of the multilayer ceramic capacitor according to the first embodiment of the present invention.

[0134] Specifically, the ESL value of a conventional 3-terminal multilayer ceramic capacitor is about 32 pH, while the ESL value of the 8-terminal multilayer ceramic capacitor according to the first embodiment of the present invention is also about 32 pH.

[0135] That is, according to the first embodiment of the present invention, while satisfying the low ESL characteristics of the conventional three-terminal multilayer ceramic capacitor, multiple capacitors can be merged into one capacitor, which is excellent in reducing the mounting area when mounting on a board.

[0136] FIG. 10 is a graph showing changes in ESL components according to frequency of the multilayer ceramic capacitor according to the comparative example and the second embodiment of the present invention.

[0137] Referring to FIG. 10, when comparing the ESL value of the conventional three-terminal multilayer ceramic capacitor as a comparative example with the ESL value of the multilayer ceramic capacitor according to the second embodiment of the present invention, it can be seen that the ESL value of the multilayer ceramic capacitor according to the second embodiment of the present invention is somewhat increased.

[0138] Specifically, the ESL value of a conventional 3-terminal multilayer ceramic capacitor is about 32 pH, while the ESL value of the 8-terminal multilayer ceramic capacitor according to the first embodiment of the present invention is also about 44 pH.

[0139] That is, according to the second embodiment of the present invention, although the ESL value is higher than that of a conventional three-terminal multilayer ceramic capacitor, since multiple capacitors can be combined into one capacitor, it has an excellent effect of reducing the mounting area when mounting on a board.

[0140] Multilayer ceramic capacitor mounting board FIG. 11 is a perspective view illustrating a state in which the multilayer ceramic capacitor according to the first embodiment of the present invention is mounted on a printed circuit board.

[0141] Referring to FIG. 11, a multilayer ceramic electronic component mounting substrate 300 according to the present embodiment includes a printed circuit board 310 on which a multilayer ceramic electronic component is mounted, and a plurality of electrode pads 311, 312, 313, 314, and 315 formed spaced apart on an upper surface of the printed circuit board 310.

[0142] In this case, the multilayer ceramic capacitor, which is a multilayer ceramic electronic component, is disposed on the lower side with the sixth surface in the thickness direction of the body 110 as a mounting surface, and may be electrically connected to the printed circuit board 310 by solder (not shown) in a state in which the first to fourth external electrodes 131, 132, 133, 134 or the first to fourth external electrodes and via electrodes are respectively in contact with and positioned on the plurality of electrode pads 311, 312, 313, 314, 315.

[0143] When the multilayer ceramic capacitor according to an embodiment of the present invention is used as an EMI filter, some of the first to fourth external electrodes 131, 132, 133, and 134 can be connected to an input terminal and an output terminal of a signal line, respectively, and the remaining terminals can be connected to a ground terminal to remove high frequency noise from the signal line.

[0144] Specifically, the external electrodes indicated as (+) poles are connected to electrode pads and correspond to input / output terminals, respectively, and the external electrodes indicated as (-) poles are connected to electrode pads and correspond to ground terminals.

[0145] As another application example, when the multilayer ceramic capacitor according to an embodiment of the present invention is used as a decoupling capacitor, some of the first to fourth external electrodes 131, 132, 133, and 134 can be connected to a power supply line and the remaining ones can be connected to a ground line to stabilize the power supply circuit.

[0146] Although the embodiments of the present invention have been described in detail above, it will be apparent to those skilled in the art that the scope of the present invention is not limited thereto, and that various modifications and variations are possible within the scope of the technical idea of ​​the present invention described in the claims. [Explanation of symbols]

[0147] 100, 200 Multilayer ceramic capacitor 110, 210 Main unit 111, 211 Dielectric layer 121, 122, 221, 222 First and second internal electrodes 121a, 121b, 122a, 122b, 122c, 122d, 221a, 221b lead part 131, 132, 133, 134, 231, 232, 233, 234 1st to 4th external electrodes 235 Via Electrode 300 Mounting board for multilayer ceramic electronic components 310 Printed Circuit Board 311, 312, 313, 314, 315 Electrode pads

Claims

1. a body including a plurality of dielectric layers, the plurality of dielectric layers being alternately disposed between first and second internal electrodes of different polarities, the plurality of dielectric layers being sandwiched between first and second internal electrodes, the plurality of dielectric layers having at least one lead portion extending to a side surface of the plurality of dielectric layers; a plurality of external electrodes disposed outside the body and connected to the first and second internal electrodes; the plurality of external electrodes include first and second external electrodes disposed on the entire first and second surfaces of the outer surface of the body, and an equal number of m (m≧3) third and fourth external electrodes disposed on third and fourth surfaces adjacent to the first and second surfaces and facing each other, The plurality of external electrodes have polarities different between adjacent electrodes, The first internal electrodes are exposed to first and second surfaces of the outer surface of the body, and lead portions of the first internal electrodes are exposed to third and fourth surfaces of the outer surface of the body. Multilayer ceramic electronic components.

2. 2. The multilayer ceramic electronic component according to claim 1, wherein said m is an odd number.

3. 3. The multilayer ceramic electronic component according to claim 1, wherein the total number of the external electrodes is equal to the number of the current paths.

4. 4. The multilayer ceramic electronic component according to claim 1, wherein the lead portions of the second internal electrodes are arranged adjacent to and alternately with the lead portions of the first internal electrodes and exposed to third and fourth surfaces of the outer surface of the body.

5. The multilayer ceramic electronic component according to claim 1 , wherein the first and second external electrodes have the same polarity.

6. 6. The multilayer ceramic electronic component according to claim 1, wherein the third and fourth external electrodes are arranged such that external electrodes of the same polarity are located in regions of the third surface and the fourth surface facing each other.

7. 7. The multilayer ceramic electronic component according to claim 1, wherein the thickness of the body is smaller than its width.

8. the body includes an active portion including a plurality of first and second internal electrodes as a portion contributing to the formation of a capacitance, and a cover portion not contributing to the formation of a capacitance and disposed on an upper portion and a lower portion of the active portion, The multilayer ceramic electronic component according to claim 1 , wherein the cover portion has a thickness smaller in a region disposed at a lower part than in a region disposed at an upper part.

9. a printed circuit board having a plurality of electrode pads thereon; 9. A mounting substrate for a multilayer ceramic electronic component comprising the multilayer ceramic electronic component according to claim 1, wherein a plurality of external electrodes are provided on the plurality of electrode pads, respectively.

10. a main body having a first surface and a second surface opposed to each other in a first direction, a third surface and a fourth surface opposed to each other in a second direction perpendicular to the first direction, and a fifth surface and a sixth surface opposed to each other in a third direction perpendicular to the first and second directions; a plurality of first and second internal electrodes arranged alternately with a dielectric layer interposed therebetween within the body; first and second external electrodes disposed on the entire surface of the first surface and the entire surface of the second surface of the body and connected to the first internal electrode; at least three third external electrodes disposed on a third surface of the body and connected to the first lead portion of the first internal electrode, the first lead portion of the second internal electrode, and the second lead portion of the second internal electrode, respectively; at least three or more fourth external electrodes are disposed on a fourth surface of the body and connected to the second lead portion of the first internal electrode, the third lead portion of the second internal electrode, and the fourth lead portion of the second internal electrode, respectively; the first internal electrode includes lead portions exposed to first and second surfaces of the body and exposed to third and fourth surfaces of the body, the second internal electrode includes first and second lead portions spaced apart from the first lead portion of the first internal electrode from a first direction of the body and exposed to a third surface, and third and fourth lead portions spaced apart from the second lead portion of the first internal electrode from the first direction of the body and exposed to a fourth surface, A multilayer ceramic electronic component, in which the first and third lead portions of the second internal electrode are arranged between the first external electrode and the first lead portion of the first internal electrode from the first direction of the main body, and the second and fourth lead portions of the second internal electrode are arranged between the second external electrode and the first lead portion of the first internal electrode from the first direction of the main body.

11. 11. The multilayer ceramic electronic component according to claim 10, wherein N third external electrodes are arranged on the third surface of the body, and N fourth external electrodes are arranged on the fourth surface of the body, where N is an odd number.

12. 12. The multilayer ceramic electronic component according to claim 10, wherein the thickness of the body is smaller than its width.

13. a printed circuit board having a plurality of electrode pads thereon; and the multilayer ceramic electronic component according to claim 10 , which is mounted on the printed circuit board and electrically connected to the plurality of electrode pads. the body of the multilayer ceramic electronic component further includes an upper cover and a lower cover disposed on an upper portion and a lower portion of the first and second internal electrodes, respectively; The lower cover adjacent to the printed circuit board is thinner than the upper cover spaced apart from the printed circuit board, and is a mounting substrate for multilayer ceramic electronic components.

Images