Three-dimensional packaging structure and method for bonded wall fan-out devices - Patents.com

Abstract

The three-dimensional packaging structure and method for a bonded-wall fan-out device (10) includes a first surface of the device (10) having a functional area (12) and several pads (11), and an encapsulation material (20) covering the entire surface of the device (10) other than the first surface. A wall structure (30) is formed on the first surface of the device (10) and extends to the first surface of the encapsulation material (20). The wall structure (30) partially covers at least one pad (11) and has a first opening (31) in the pad (11) portion. A cover plate (40) is also provided, bonded to the wall structure (30) to form a cavity (13) structure in the functional area (12) of the device (10). The cover plate (40) has at least one second opening (41) communicating with the first opening (31). A metal connection structure is provided on the surface of the cover plate 40, which is electrically connected to the pad 11 through the first opening 31 and the second opening 41. This improves the reliability of the entire structure, reduces risks, and reduces costs.

Description

[Technical field]

[0001] The present invention relates to the field of semiconductor packaging, and in particular to a three-dimensional packaging structure and method for a joint wall fan-out device. [Background technology]

[0002] Many MEMS (e.g., accelerometers, RF switches, gyroscopes) and various sensors (e.g., filters, CMOS image sensors) require the formation of a protective cavity to protect the device and provide a vacuum or airtight operating environment for the device. Although chip sizes are becoming smaller with technological advances, many devices, such as SAW filters and CMOS image sensors, have no choice but to place the sealing wall at a position other than the device area. However, to reduce costs, the area used for wall formation tends to shrink, and the width of the wall is becoming narrower and narrower. The reduction in the bonding area between the wall and the cover plate leads to a decrease in the bonding force at the bonding interface, which has a significant impact on the reliability of the device. Therefore, it is necessary to seek a new solution that is low cost and reliable.

[0003] Fan-out packaging technology is currently the mainstream advanced packaging technology. With the further improvement of chip integration and the further increase of I / O number, it is becoming difficult for the conventional wafer level chip scale package (WLCSP) to meet product requirements, and it is necessary to solve the contradiction between the excessive number of I / O and the insufficient chip area in WLCSP. Infineon proposed the wafer level fan-out eWLB (Embedded Wafer Level BGA) technology (Patent Document 1) in 2004. The main feature of this technology is that a new fan-out plane is formed around the chip using molding compound and the chip surface, and metal wiring is drawn from the chip to the fan-out surface. In principle, the fan-out packaging technology is not limited by the chip size, and the number of I / O and the solder ball pitch are also not limited by the chip size. In addition, since no substrate is used, the package thickness is reduced, and it has excellent cost and electrical advantages. However, in the conventional fan-out packaging technology, the fan-out part has a planar structure, and is often used for the layout of electric circuits. In addition, the technology is complicated.

[0004] As process technology gradually matures, the cost of FOWLP continues to fall. Coupled with the continuous improvement of chip technology, FOWLP is expected to grow explosively. In addition, in order to reduce the thickness of the PoP package in conventional AP processors and improve electrical performance, 3D FOWLP stacking technology, which creates through-holes on the molding compound and connects them, is being further developed based on FOWLP technology. A representative example is the InFO technology developed by TSMC, which provides packaging services for Apple A10, A11, and A12 processors. This has led to a research and development fever for 3D FOWLP stacking technology in the industry. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] U.S. Patent No. 6,727,576 Summary of the Invention [Problem to be solved by the invention]

[0006] The main objective of the present invention is to provide a three-dimensional packaging structure and method for a joint-wall fan-out device with improved reliability, reduced risk and cost, in order to overcome the above-mentioned shortcomings in the prior art. [Means for solving the problem]

[0007] The present invention adopts the following technical solutions:

[0008] The three-dimensional packaging structure of the joint-wall fan-out device includes a first surface of the device having a functional area and some pads, and a molded encapsulant covering the entire surface of the device except the first surface, and a fan-out surface is formed on the first surface of the encapsulant that is horizontally connected to the first surface of the device.

[0009] A wall structure is fabricated on a first surface of the device and extends to the fan-out surface, the wall structure partially covering at least one pad and having a first opening in the pad.

[0010] A cover plate is provided that is adhered to the wall structure to form a cavity structure in the functional area of ​​the device, The cover plate has at least one second opening in communication with the first opening.

[0011] A metal connection structure is provided on the surface of the cover plate, the metal connection structure being electrically connected to the pad through the first opening and the second opening.

[0012] Preferably, the cover plate is a polymer film, glass, silicon or ceramic.

[0013] Preferably, the material of the wall structure is a polymer, glass, ceramic or an insulator.

[0014] Preferably, the material of the wall structure is a photoresist or a dry film, and the material is disposed on the first surface and the fan-out surface of the device by resist coating or film compression, and then exposed and developed by photolithography to form the walls.

[0015] Preferably, the material of the device is lithium niobate, lithium tantalate, glass or silicon.

[0016] Preferably, the encapsulant is a polymer, a plastic encapsulant, an epoxy resin or a glass paste.

[0017] Preferably, the metal connection structure includes a conductive circuit, a passivation layer, and a signal port. The conductive circuit and the cover plate are insulated. The conductive circuit is disposed on the surface of the cover plate, and extends to the second opening and the first opening to be electrically connected to the pad. The passivation layer covers the conductive circuit and the exposed surface of the cover plate, and is provided with a third opening. The signal port is located in the third opening and is electrically connected to the conductive circuit.

[0018] Preferably, the signal ports are BGA solder balls, nickel-palladium-gold, nickel-gold, or titanium-copper pads.

[0019] Preferably, the device is a filter chip having several pads on a first surface, the wall structure being a frame structure with an internal extension to cover each pad and with a first opening at each pad.

[0020] The present invention provides a three-dimensional packaging method for a joint-wall fan-out device, the method including: 1) Dice the device wafer. 2) Place the device on the temporary substrate by pick and place. 3) Encapsulating the device to form a fan-out surface on a first surface of the encapsulant that is horizontally connected to the first surface of the device. 4) Separate the encapsulated devices from the substrate to obtain a reconstituted wafer or a square wafer with the encapsulation material. 5) Creating a wall structure on the edge and fan-out surface of the first side of the device, extending partially over at least one pad and leaving an opening for that pad. 6) A cover plate is added to the surface of the wall structure to form a cavity in the functional area and to open up the pad area. 7) Fabricate metal interconnects to electrically connect to the pads.

[0021] Preferably, in step 3) the sealing is performed by plastic sealing, film crimping or adhesive application.

[0022] Preferably, in step 5), a photoresist or a dry film is selected as the material for the wall structure, the material is disposed on the first surface and the fan-out surface of the device by resist coating or film compression, and the walls are formed by exposing and developing the material by photolithography.

[0023] Preferably, the wall covers a part of the pad area of ​​the chip during photolithography to hold an opening. Then, after bonding the cover plate, the cover plate is opened by photolithography or laser light to open holes corresponding to the pad positions. Then, bumps or leads are made by PVD or electroplating, and the pads are drawn to the surface of the cover plate by conductor wires. Effect of the Invention

[0024] As is apparent from the above description of the present invention, compared with the prior art, the present invention has the following beneficial effects:

[0025] 1. In the present invention, a fan-out surface is formed by encapsulating the device on all but the first surface with an encapsulant. A wall structure is then placed on the fan-out surface of the device and encapsulant to support the cover plate and form a large cavity. The wall structure is created using the fan-out area, providing ample locations for spreading the wall structure. This increases the reliability of the entire structure, reduces risk, and reduces costs.

[0026] 2. The structure and method of the present invention eliminates the fragility of attributes through the reconstructed wafer, which is advantageous for improving the yield in the product manufacturing process, is easy to process, and reduces the risk of breakage.

[0027] 3. The structure and method of the present invention increases the area of ​​devices and decreases the area of ​​non-device regions, resulting in more devices and lower costs for similar raw materials.

[0028] 4. The structure and method of the present invention can adopt wafer-level chip-scale packaging, which is suitable for large-scale and mass production, reduces production costs, and ensures uniformity of device performance. [Brief description of the drawings]

[0029] [Figure 1] FIG. 1 is a structural diagram of the present invention. [Diagram 2] FIG. 2 is a structural diagram of the device wafer. [Diagram 3] FIG. 3 is a schematic diagram of dicing. [Figure 4] FIG. 4 is a plan view of FIG. [Diagram 5] FIG. 5 is a schematic diagram showing a case where the chip is mounted on the temporary substrate. [Figure 6] FIG. 6 is a schematic diagram of the seal. [Figure 7] FIG. 7 is a plan view of FIG. [Figure 8] FIG. 8 is a schematic diagram of the case where the joint is removed. [Figure 9]FIG. 9 is a schematic showing the fabrication of the wall structure. [Figure 10] FIG. 10 is a plan view of FIG. [Figure 11] FIG. 11 is a schematic diagram showing the fabrication of a cover plate. [Figure 12] FIG. 12 is a schematic diagram of the conductive circuit of the device. [Figure 13] FIG. 13 is a plan view of FIG. [Figure 14] FIG. 14 is a structural diagram of the present invention (before dicing). DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0030] The present invention will be further described below with reference to specific embodiments.

[0031] In the embodiment, the three-dimensional packaging structure of the junction wall fan-out device includes a device 10, an encapsulation material 20, a wall structure 30, a cover plate 40, and a metal connection structure, etc., with reference to Figs. 1 to 14. The first surface of the device 10 is provided with a pad 11 and a functional area 12. The functional area 12 is provided with an IDT. The pad 11 can be an aluminum pad, an aluminum-nickel-gold pad, an aluminum-nickel-palladium-gold pad, etc. The chip type of the device in this embodiment is a SAW filter, a BAW filter, or a filter device with other similar functions. The device 10 is a device 10 obtained by dicing a wafer material such as lithium niobate, lithium tantalate, glass, silicon, etc.

[0032] The encapsulation material 20 encapsulates the device 10 except for the first surface. Referring to FIG. 1, the encapsulation material 20 encapsulates the four sides and one bottom surface of the device 10. The top side of the device becomes the first surface and is not encapsulated. This forms a fan-out surface 21 on the first surface of the encapsulation material 20 that is horizontally connected to the first surface of the device 10. The encapsulation material 20 can be realized by plastic encapsulation, film compression, or adhesive application, and the thickness of the encapsulation can be set as needed. The encapsulation material 20 can be a polymer, a plastic encapsulation material, an epoxy resin, a glass paste, or the like.

[0033] The wall structure 30 is disposed on the edge of the first side of the device 10 and on the fan-out surface 21 of the encapsulation material 20. The fan-out surface 21 of the encapsulation material 20 and the first side of the device 10 are located on the same plane. That is, the wall structure 30 covers the interface between the device 10 and the fan-out surface 21 of the encapsulation material 20. The wall structure 30 may completely or partially cover the fan-out surface 21 of the encapsulation material 20.

[0034] The wall structure 30 further extends partially to at least cover the pad 11, and a first opening 31 is provided in the pad 11. The first opening 31 is located on the upper surface of the pad 11. The area of ​​the first opening 31 is slightly smaller than the area of ​​the pad 11. The number of pads covered by the wall structure 30 may be one, two, three, or even all of the pads, and is not limited here. The wall structure 30 may be a polymer, a glass, a ceramic, an insulator, etc.

[0035] The cover plate 40 covers the surface of the wall structure 30 to form a cavity 13 in the functional area 12, and a second opening 41 is provided in the pad 11. The height of the cavity 13 is determined by the thickness of the wall structure 30. The second opening 41 and the first opening 31 communicate with each other. The area of ​​the second opening 41 may be slightly larger or equal to the area of ​​the first opening 31, and is preferably larger. The cover plate 40 can be made of a material such as a polymer film, glass, silicon, or ceramics.

[0036] In the embodiment, the metal connection structure includes a conductive circuit 50, a passivation layer 60, a signal port 70, etc., which is disposed on the surface of the cover plate 40, extends to the second opening 41 and the first opening 31, and is electrically connected to the pad 11. The conductive circuit 50 and the cover plate 40 are insulated. The conductive circuit 50 is disposed on the surface of the cover plate 40, extends to the second opening 41 and the first opening 31, and is electrically connected to the pad 11. The conductive circuit 50 is made of a metal material. The passivation layer 60 covers the conductive circuit 50 and the exposed surface of the cover plate 40, and has a third opening 61 in the external connection area. The signal port 70 is located in the third opening 61 and is electrically connected to the conductive circuit 50.

[0037] The passivation layer 60 is used to protect the conductive circuit 50 and can be made of a polymer material, which can improve the insulation performance of the product and provide oxidation protection to the conductive circuit 50. The signal port 70 is a BGA solder ball, nickel-palladium-gold, nickel-gold, or titanium-copper pad. The metal connection +- structure of the present invention can be realized by any other common metal external connection structure.

[0038] The device 10 can be a filter chip having on a first surface several pads 11. The wall structure 30 is a frame structure, the inner part of which extends accordingly to cover each pad, and each pad is provided with a first opening 31.

[0039] A three-dimensional packaging method for a joint-wall fan-out device is used to manufacture the above three-dimensional packaging structure of the joint-wall fan-out device, with reference to Figures 2 to 14. The method includes the following steps:

[0040] 1) Referring to Figure 2, select a wafer of filter devices and dice the device wafer to obtain single devices 10. The device wafer is a wafer of lithium niobate or lithium carbonate, etc. See Figures 3 and 4 for structural diagrams after dicing.

[0041] 2) Referring to FIG. 5, the device 10 is placed on a temporary substrate 80 by pick and place using the alignment marks.

[0042] 6, the device 10 is sealed except for the first surface by plastic sealing, film compression or adhesive application to form a fan-out surface 21 on the first surface of the sealing material 20 that is connected horizontally to the first surface of the device 10. The sealing material may be a polymer, a plastic sealing material, an epoxy resin, a glass paste, or the like.

[0043] 7 and 8, the encapsulated device is separated from the temporary substrate 80, i.e., the temporary substrate 80 is removed to obtain a reconstructed wafer or a square wafer having the encapsulation material 20.

[0044] 9 and 10, a wall structure 30 is fabricated on the edge of the first face of the device 10 and on the fan-out face 21 of the encapsulation material 20, extending partially to cover at least one pad 11 and opening a first opening 31 at said pad 11. The wall structure 30 can be a polymer, glass, ceramic or insulator.

[0045] 6) The surface of the wall structure 30 is covered with a cover plate 40 to form a cavity 13 in the functional region 12 of the device 10 and to open a second opening 41 in the pad 11. Referring to Fig. 11 and Fig. 13, the cover plate 40 can be made of a material such as a dry film, glass, silicon, or ceramics, and can be opened by photolithography or laser light.

[0046] 7) A metal connection structure is fabricated and electrically connected to the pad 11. Specifically, referring to FIG. 12, a conductive circuit 50 is first fabricated on the surface of the cover plate 40, and is extended to the second opening 41 and the first opening 31 to be electrically connected to the pad 11. Next, a passivation layer 60 is fabricated to cover the conductive circuit 50 and the exposed surface of the cover plate 40, and a third opening 61 is opened in the external connection region by photolithography. A signal port 70 is also fabricated in the third opening 61 portion of the external connection region to be electrically connected to the conductive circuit 50. The signal port 70 can be a common signal port such as a BGA solder ball, nickel-palladium-gold, nickel-gold, or titanium-copper pad.

[0047] 8) Referring to FIG. 14, the reconstituted wafer or the square wafer is diced to obtain the final package.

[0048] In the embodiment of the present invention, photoresist or dry film can be selected as the material for the wall structure. The material is placed on the first surface and the fan-out surface of the device by resist coating or film compression, and then exposed and developed by photolithography to form the walls. Then, the material itself (if it has adhesive function) or an adhesive is applied to the surface to bond materials such as glass, silicon, dry film, etc.

[0049] The trend of chip area reduction is that the surface area of ​​the chip other than the device is compressed to a very small size in order to reduce the manufacturing cost of the chip. Accordingly, the bonding walls that create the cavity structure are thinned, and the bonding surface with the cover plate is reduced, which reduces the bonding force and affects the reliability of the device. In order to meet the standard outer dimensions of the packaging, the present invention proposes to solve the reliability challenge associated with the miniaturization of the chip in the wafer level chip scale package with a sealed cavity by fanning out the bonding walls. Unlike the standard fan-out packaging that fans out the electric signal of the metal wiring, the present invention dices the device before embedding it in other materials, and uses the fan-out area to create the wall structure. This provides ample space for the wall structure to be expanded, which allows for a large cavity, high reliability, and reduced cost.

[0050] The above is merely a specific embodiment of the present invention, and the design concept of the present invention is not limited thereto. Any insubstantial changes made to the present invention using the concept will be considered as an infringement of the scope of protection of the present invention. [Industrial Applicability]

[0051] In the present invention, a fan-out surface is formed by encapsulating the device except for the first surface with an encapsulant. A wall structure is then provided on the fan-out surface of the device and the encapsulant to support the cover plate and form a large cavity. The wall structure is created using the fan-out area, providing ample locations for spreading the wall structure. This improves the reliability of the entire structure, reduces risk, and reduces costs, and has good industrial applicability. [Explanation of symbols]

[0052] 10 Devices 11 Pad 12 functional areas 13 Cavity 20 Sealing material 30 Wall structure 31 First Opening 40 Cover Plate 41 Second Opening 50 Conductive Circuit 60 Passivation Layer 61 3rd Opening 70 Signal Port 80 Temporary board

Claims

1. A method for three-dimensional packaging of a joint wall fan-out device, comprising: 1) dicing the device wafer; 2) placing the device on a temporary substrate by pick-up and placing; 3) encapsulating the device to form a fan-out surface on a first surface of the encapsulant that is horizontally connected to a first surface of the device; 4) Separating the encapsulated device from the substrate to obtain a reconstituted wafer or a square wafer with the encapsulation material; 5) creating a wall structure on the edge and fan-out surface of the first side of the device, extending partially over at least one pad and leaving an opening in said pad; 6) Adding a cover plate to the surface of the wall structure to form a cavity in the functional area and open the pad area; 7) preparing and electrically connecting metal interconnect structures to the pads.

2. A three-dimensional packaging method for a joint wall fan-out device as described in claim 1, characterized in that in step 3), sealing is performed by plastic sealing, film crimping or adhesive application.

3. A three-dimensional packaging method for a joint wall fan-out device as described in claim 1, characterized in that in step 5), photoresist or dry film is selected as the material for the walls, the material is placed on the first surface and the fan-out surface of the device by resist coating or film pressing, and the walls are formed by exposing and developing by photolithography.

4. A three-dimensional packaging method for a joint wall fan-out device as described in Claim 3, characterized in that during photolithography, the wall covers a portion of the pad area of ​​the chip to maintain an opening, and after bonding of the cover plate, the wall is opened using photolithography or laser light to open holes in the cover plate corresponding to the pad positions, and then bumps or lead wires are created by PVD or electroplating, and the pads are brought out to the surface of the cover plate by conductor wires.

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