Photoelectric conversion device and imaging system

Abstract

To provide a photoelectric conversion device capable of effectively suppressing the influence of noise caused by simultaneous inversion of the output level of a comparator.SOLUTION: A photoelectric conversion device includes a plurality of pixels arranged in a plurality of columns, a plurality of AD conversion circuits provided corresponding to the plurality of columns, and a control circuit that controls the AD conversion circuit. The plurality of pixels includes OB pixels arranged in the first column and effective pixels arranged in the second column. The plurality of AD conversion circuits includes a first AD conversion circuit having a first comparator for receiving OB pixel signals and a second AD conversion circuit having a second comparator for receiving valid pixel signals. The control circuit controls the first and second comparators such that the result of AD conversion in the first AD conversion circuit is determined earlier than the result of AD conversion in the second AD conversion circuit for signals of the same level.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] The present invention relates to a photoelectric conversion device and an imaging system. [Background technology]

[0002] Among photoelectric conversion devices such as CMOS image sensors, there are those that perform analog-to-digital (AD) conversion of pixel signals and output them. In these photoelectric conversion devices, each of a plurality of comparators provided corresponding to a pixel column compares a pixel signal output from the pixel in the corresponding column with a reference signal and outputs a comparison signal according to the comparison result. The pixel signal can be AD converted by capturing the digital value of the counter in memory at the timing when the comparison signal is output. Patent Document 1 describes a technology for suppressing noise caused by the simultaneous inversion of the output levels of the comparators provided in each column. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2014-096670 A Summary of the Invention [Problem to be solved by the invention]

[0004] The effect of noise caused by the simultaneous inversion of the output levels of the comparators is particularly noticeable in horizontal OB pixels, and has a large impact on image quality. However, in Patent Document 1, no distinction is made between horizontal OB pixels and effective pixels. Therefore, the technology in Patent Document 1 cannot be said to have sufficiently improved image quality.

[0005] An object of the present invention is to provide a photoelectric conversion device capable of effectively suppressing the influence of noise caused by simultaneous inversion of the output levels of comparators. [Means for solving the problem]

[0006] According to one disclosure of the present specification, a pixel array unit is provided in which a plurality of pixels, each having a photoelectric conversion element, are arranged in a plurality of columns, a plurality of AD conversion circuits are provided corresponding to the plurality of columns, and a control circuit is provided for controlling the plurality of AD conversion circuits, the plurality of pixels include a first pixel arranged in a first column of the plurality of columns and having a light-shielded photoelectric conversion element, and a second pixel arranged in a second column of the plurality of columns different from the first column, and having light incident on the photoelectric conversion element, the plurality of AD conversion circuits include a first AD conversion circuit having a first comparator that receives a signal from the first pixel, and a second AD conversion circuit having a second comparator that receives a signal from the second pixel, a timing at which the signal of the first pixel is input to the first comparator and a timing at which the signal of the second pixel is input to the second comparator are the same; The control circuit is at the same level The signal of the first pixel and the signal of the second pixel are Whereas, The signal value output from the first comparator changes before the signal value output from the second comparator changes. There is provided a photoelectric conversion device configured to control the first comparator and the second comparator so as to obtain a first comparator and a second comparator.

[0007] According to another disclosure of the present specification, there is provided a photoelectric conversion device comprising: a pixel array section in which a plurality of pixels, each having a photoelectric conversion element, are arranged in a plurality of columns; and a plurality of AD conversion circuits provided corresponding to the plurality of columns, wherein the plurality of pixels include a first pixel arranged in a first column of the plurality of columns and having a light-shielded photoelectric conversion element, and a second pixel arranged in a second column of the plurality of columns different from the first column, and having light incident on the photoelectric conversion element, wherein the plurality of AD conversion circuits include a first AD conversion circuit having a first comparator that receives a signal from the first pixel, and a second AD conversion circuit having a second comparator that receives a signal from the second pixel, and wherein a slew rate in the first comparator is higher than a slew rate in the second comparator. Effect of the Invention

[0008] According to the present invention, it is possible to effectively suppress noise caused by simultaneous inversion of the output levels of the comparators. [Brief description of the drawings]

[0009] [Figure 1] 1 is a block diagram showing a schematic configuration of a photoelectric conversion device according to a first embodiment of the present invention. [Diagram 2] 1 is a circuit diagram showing an example of the configuration of pixels and column circuits in a photoelectric conversion device according to a first embodiment of the present invention. [Diagram 3] 2 is a circuit diagram showing an example of the configuration of a comparator in the photoelectric conversion device according to the first embodiment of the present invention. FIG. [Figure 4] FIG. 2 is a timing chart showing the operation of the photoelectric conversion device according to the first embodiment of the present invention. [Diagram 5] FIG. 11 is a circuit diagram showing an example of the configuration of a comparator in a photoelectric conversion device according to a second embodiment of the present invention. [Figure 6] FIG. 11 is a timing chart showing the operation of the photoelectric conversion device according to the third embodiment of the present invention. [Figure 7] FIG. 11 is a circuit diagram showing an example of the configuration of pixels and column circuits in a photoelectric conversion device according to a fourth embodiment of the present invention. [Figure 8] FIG. 11 is a timing chart showing the operation of the photoelectric conversion device according to the fourth embodiment of the present invention. [Figure 9] FIG. 13 is a block diagram showing a schematic configuration of an imaging system according to a fifth embodiment of the present invention. [Figure 10] FIG. 13 is a diagram showing an example of the configuration of an imaging system and a moving object according to a sixth embodiment of the present invention. [Figure 11] FIG. 13 is a block diagram showing a schematic configuration of an apparatus according to a seventh embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] [First embodiment] A photoelectric conversion device and a driving method thereof according to a first embodiment of the present invention will be described with reference to Figs. 1 to 4. Fig. 1 is a block diagram showing a schematic configuration of a photoelectric conversion device according to this embodiment. Fig. 2 is a circuit diagram showing an example of the configuration of pixels and column circuits in a photoelectric conversion device according to this embodiment. Fig. 3 is a circuit diagram showing an example of the configuration of a comparator in a photoelectric conversion device according to this embodiment. Fig. 4 is a timing chart showing the operation of a photoelectric conversion device according to this embodiment.

[0011] First, a schematic configuration of a photoelectric conversion device according to a first embodiment of the present invention will be described with reference to FIG.

[0012] As shown in FIG. 1, the photoelectric conversion device 100 according to this embodiment can be composed of a pixel array section 10, a vertical scanning circuit 20, a readout circuit 30, a reference signal generating circuit 36, a horizontal scanning circuit 50, a digital signal processing circuit 60, and a timing generator 70.

[0013] The pixel array section 10 includes a plurality of pixels 12, 14 arranged in a matrix across a plurality of rows and a plurality of columns. Each of the pixels 12, 14 includes a photoelectric conversion section made up of a photoelectric conversion element such as a photodiode. The pixel 14 is an effective pixel that receives light on its photoelectric conversion element and outputs a pixel signal according to the amount of light incident on the photoelectric conversion element. The pixel 12 is an optical black pixel (OB pixel) in which the photoelectric conversion element is shielded from light, and its output signal is used as a reference for the black level.

[0014] The pixels 12 are arranged in some rows and / or some columns of the multiple rows and columns constituting the pixel array section 10, generally in rows and columns adjacent to two sides of the periphery of the pixel array section 10. A column in which only the pixels 12 are arranged may be called a horizontal OB pixel region, and pixels arranged in the horizontal OB pixel region may be called horizontal OB pixels. A row in which only the pixels 12 are arranged may be called a vertical OB pixel region, and pixels arranged in the vertical OB pixel region may be called vertical OB pixels. For the sake of simplicity of the drawing, FIG. 1 shows an example in which the pixels 12 are arranged in the leftmost column (first column) of the multiple columns of the pixel array section 10, and the pixels 14 are arranged in the other columns (second to Nth columns), but typically the horizontal OB pixel region is composed of multiple columns.

[0015] At least one pixel 12 and a plurality of pixels 14 are arranged in each of a plurality of rows of the pixel array unit 10. A reference signal output from a pixel 12 is used in correction processing of a pixel signal output from a pixel 14 in the same row.

[0016] In each row of the pixel array section 10, a control line 16 is arranged so as to extend in a first direction (the horizontal direction in FIG. 1). Each of the control lines 16 is connected to the pixels 12, 14 aligned in the first direction, respectively, and serves as a common signal line for these pixels 12, 14. The first direction in which the control lines 16 extend may be called the row direction or horizontal direction. The control lines 16 are connected to a vertical scanning circuit 20.

[0017] In each column of the pixel array section 10, an output line 18 is arranged to extend in a second direction (vertical direction in FIG. 1) intersecting the first direction. Each of the output lines 18 is connected to the pixels 12 or 14 aligned in the second direction, and serves as a common signal line for these pixels 12 or 14. The second direction in which the output lines 18 extend may be called the column direction or vertical direction. Each of the output lines 18 is connected to a current source 22 and a readout circuit 30.

[0018] The vertical scanning circuit 20 is a control circuit having a function of receiving a control signal output from the timing generator 70, generating a control signal for driving the pixels 12, 14, and supplying the control signal to the pixels 12, 14 via a control line 16. The vertical scanning circuit 20 may include logic circuits such as a shift register and an address decoder. The vertical scanning circuit 20 drives the pixels 12, 14 of the pixel array section 10 on a row-by-row basis. The signals read out from the pixels 12, 14 on a row-by-row basis are input to a readout circuit 30 via an output line 18 provided for each column of the pixel array section 10.

[0019] The readout circuit 30 has a plurality of column circuits 32, 34 provided corresponding to each column of the pixel array section 10. The column circuit 32 is connected to the output line 18 of the column (first column) in which the pixels 12 are arranged. The column circuit 34 is connected to the output line 18 of the column (second column to Nth column) in which the pixels 14 are arranged. Each of the column circuits 32, 34 functions as an AD conversion circuit that performs AD conversion on an analog pixel signal output from the output line 18 of the corresponding column, and functions as a digital signal holding section that holds a digital pixel signal after AD conversion.

[0020] The reference signal generating circuit 36 ​​is a circuit that receives a control signal output from the timing generator 70 and generates a reference signal to be supplied to the column circuits 32 and 34. The reference signal is a signal having a predetermined amplitude, and may be, for example, a signal whose signal level (signal magnitude) changes over time. The reference signal is typically a ramp signal. A ramp signal is a signal whose signal level changes monotonically over time, for example, a signal whose output voltage monotonically decreases or increases over time. Note that the reference signal is not particularly limited as long as it has an amplitude applicable to AD conversion.

[0021] The horizontal scanning circuit 50 is a control circuit that supplies the readout circuit 30 with a control signal for sequentially transferring the pixel signals processed by the readout circuit 30 to the digital signal processing circuit 60 for each column. The horizontal scanning circuit 50 can be configured using a shift register and an address decoder.

[0022] The digital signal processing circuit 60 is a processing circuit that performs predetermined processing on the digital pixel signals transferred from the readout circuit 30. Examples of the signal processing performed by the digital signal processing circuit 60 include correction processing and amplification processing using digital correlated double sampling.

[0023] The timing generator 70 is a control circuit for supplying control signals for controlling the operations and timings of the vertical scanning circuit 20, the readout circuit 30, the reference signal generating circuit 36, and the horizontal scanning circuit 50. At least some of the control signals supplied to the vertical scanning circuit 20, the readout circuit 30, the reference signal generating circuit 36, and the horizontal scanning circuit 50 may be supplied from outside the photoelectric conversion device 100.

[0024] Next, a configuration example of the pixels 12, 14 and the column circuits 32, 34 in the photoelectric conversion device according to the present embodiment will be described with reference to FIG.

[0025] 2 shows each of the pixels 12, 14 arranged in the same row among the multiple pixels 12, 14 that make up the pixel array unit 10. Also shown in Fig. 2 is a column circuit 32 connected to the pixel 12 and a column circuit 34 connected to the pixel 14.

[0026] Each of the pixels 12 and 14 may be configured, for example, as shown in FIG. 2, with a photoelectric conversion element PD, a transfer transistor M1, a reset transistor M2, an amplification transistor M3, and a selection transistor M4.

[0027] The photoelectric conversion element PD is, for example, a photodiode, with an anode connected to a ground node and a cathode connected to a source of a transfer transistor M1. The drain of the transfer transistor M1 is connected to a source of a reset transistor M2 and a gate of an amplification transistor M3. A node FD to which the drain of the transfer transistor M1, the source of the reset transistor M2, and the gate of the amplification transistor M3 are connected is a so-called floating diffusion portion. The floating diffusion portion includes a capacitance component (floating diffusion capacitance) and functions as a charge storage portion. The floating diffusion capacitance includes a PN junction capacitance and a wiring capacitance.

[0028] The drain of the reset transistor M2 and the drain of the amplifying transistor M3 are connected to a power supply voltage node to which a voltage Vdd is supplied. The source of the amplifying transistor M3 is connected to the drain of the selection transistor M4. The source of the selection transistor M4 is connected to the output line 18.

[0029] The pixel 12 and the pixel 14 have the same circuit configuration as shown in Fig. 2. The pixel 12 differs from the pixel 14 in that the photoelectric conversion element PD is shielded from light by a light shielding film (not shown).

[0030] A current source 22 and a column circuit 32 are connected to the output line 18 connected to the pixel 12. A current source 22 and a column circuit 34 are connected to the output line 18 connected to the pixel 14. The current source 22 may be a current source whose current value is switchable, or may be a constant current source whose current value is constant.

[0031] 2, the control lines 16 of each row include a signal line connected to the gate of the transfer transistor M1, a signal line connected to the gate of the reset transistor M2, and a signal line connected to the gate of the selection transistor M4. A control signal PTX is supplied to the gate of the transfer transistor M1 from the vertical scanning circuit 20. A control signal PRES is supplied to the gate of the reset transistor M2 from the vertical scanning circuit 20. A control signal PSEL is supplied to the gate of the selection transistor M4 from the vertical scanning circuit 20. The pixels 12 and 14 in the same row are connected to a common signal line and are simultaneously controlled by a common control signal.

[0032] In this embodiment, the description will be made on the assumption that, of the electron-hole pairs generated in the photoelectric conversion element PD by the incidence of light, the electrons are used as signal charges. When electrons are used as signal charges, each transistor constituting the pixels 12 and 14 may be composed of an N-type MOS transistor. When each transistor is composed of an N-type MOS transistor, when a high-level control signal is supplied from the vertical scanning circuit 20, the corresponding transistor is turned on. Also, when a low-level control signal is supplied from the vertical scanning circuit 20, the corresponding transistor is turned off. However, the signal charge is not limited to electrons, and holes may be used as signal charges. When holes are used as signal charges, the conductivity type of each transistor is the opposite conductivity type to that described in this embodiment. Also, the names of the source and drain of a MOS transistor may differ depending on the conductivity type of the transistor and the function of interest. Some or all of the names of the source and drain used in this embodiment may be called by the opposite names.

[0033] The column circuit 32 includes capacitance elements C1 and C2, a comparator 42, a counter circuit 46, and a memory unit 48. One electrode of the capacitance element C1 is connected to the output line 18. The other electrode of the capacitance element C1 is connected to the inverting input terminal of the comparator 42. One electrode of the capacitance element C2 is connected to a signal line 54. The other electrode of the capacitance element C2 is connected to the non-inverting input terminal of the comparator 42. The counter circuit 46 has two input terminals and one output terminal. The output terminal of the comparator 42 is connected to a first input terminal of the counter circuit 46. The second input terminal of the counter circuit 46 is connected to a signal line 56. The memory unit 48 has two input terminals and one output terminal. The output terminal of the counter circuit 46 is connected to a first input terminal of the memory unit 48. The second input terminal of the memory unit 48 is connected to the horizontal scanning circuit 50. The output terminal of the memory unit 48 is connected to an output line 52.

[0034] The signal line 54 is connected to the reference signal generating circuit 36. The reference signal Vramp is supplied to the signal line 54 from the reference signal generating circuit 36. The signal line 56 is connected to the timing generator 70. The clock signal CLK is supplied to the signal line 56 from the timing generator 70.

[0035] 2, the column circuit 34 has the same circuit configuration as the column circuit 32. For convenience of the following explanation, the comparator of the column circuit 32 will be represented by reference numeral 42, and the comparator of the column circuit 34 will be represented by reference numeral 44.

[0036] Next, an overview of the operations of the pixels 12, 14 and the column circuits 32, 34 will be described with reference to Fig. 2. Note that although the operations of the pixel 14 and the column circuit 34 will be described here, the operations of the pixel 12 and the column circuit 32 are also similar.

[0037] The photoelectric conversion element PD converts incident light into an amount of charge corresponding to the amount of light (photoelectric conversion). When the transfer transistor M1 is turned on, it transfers the charge held by the photoelectric conversion element PD to the node FD. The charge transferred from the photoelectric conversion element PD is held in the capacitance (floating diffusion capacitance) of the node FD. As a result, the node FD has a potential corresponding to the amount of charge transferred from the photoelectric conversion element PD through charge-voltage conversion by the floating diffusion capacitance.

[0038] When the selection transistor M4 is turned on, it connects the amplification transistor M3 to the output line 18. The amplification transistor M3 has a configuration in which a voltage Vdd is supplied to its drain and a bias current is supplied to its source from a current source 22 via the selection transistor M4, forming an amplification section (source follower circuit) with its gate as an input node. As a result, the amplification transistor M3 outputs a signal based on the voltage of the node FD to the output line 18 via the selection transistor M4. In this sense, the amplification transistor M3 and the selection transistor M4 are an output section that outputs a pixel signal according to the amount of charge held in the node FD.

[0039] The reset transistor M2 has a function of controlling the supply of a voltage (voltage Vdd) to the FD node for resetting the node FD as a charge storage unit. The reset transistor M2 resets the node FD to a voltage according to the voltage Vdd by being turned on.

[0040] A pixel signal input from the pixel 14 to the column circuit 34 via the output line 18 is input to an inverting input terminal of the comparator 44 via a capacitive element C1. In addition, a reference signal Vramp output from the reference signal generation circuit 36 ​​is input to a non-inverting input terminal of the comparator 44 via a signal line 54 and a capacitive element C2. The comparator 44 performs a comparison operation to compare the signal level of the pixel signal with the signal level of the reference signal Vramp supplied from the reference signal generation circuit 36, and outputs a latch signal at the timing when the signal level of the pixel signal and the signal level of the reference signal Vramp satisfy a predetermined relationship. The output signal of the comparator 44 is input to a counter circuit 46.

[0041] The counter circuit 46 starts counting pulses superimposed on the clock signal CLK supplied from the timing generator 70 via the signal line 56, in synchronization with the start of the comparison operation between the signal level of the pixel signal and the signal level of the reference signal Vramp in the comparator 44. When the counter circuit 46 receives the latch signal from the comparator 44, it outputs the count value held at the timing of receiving the latch signal to the memory unit 48. The memory unit 48 holds the count value received from the counter circuit 46 as digital data of the pixel signal.

[0042] The horizontal scanning circuit 50 outputs control signals sequentially to the memory units 48 of the column circuits of each column under the control of the timing generator 70. The memory units 48 that receive the control signals from the horizontal scanning circuit 50 output digital data of the pixel signals to the output lines 52.

[0043] Next, a configuration example of the comparators 42 and 44 in the photoelectric conversion device according to the present embodiment will be described with reference to FIG.

[0044] The comparator 42 may be composed of P-type transistors MP1, MP2, and MP3, and N-type transistors MN1, MN2, MN3, and MN4.

[0045] The sources of P-type transistors MP1, MP2, and MP3 are connected to a power supply voltage node (voltage Vdd). The gates of P-type transistors MP1 and MP2 and the drain of P-type transistor MP1 are connected to the drain of N-type transistor MN1. The drain of P-type transistor MP2 is connected to the gate of P-type transistor MP3 and the drain of N-type transistor MN2. The sources of N-type transistors MN1 and MN2 are connected to the drain of N-type transistor MN3. The source of N-type transistor MN3 is connected to a reference voltage node. The drain of P-type transistor MP3 is connected to the drain of N-type transistor MN4. The source of N-type transistor MN4 is connected to the reference voltage node.

[0046] The gate of the N-type transistor MN1 is the non-inverting input terminal (INP) of the comparator 42. The gate of the N-type transistor MN2 is the inverting input terminal (INM) of the comparator 42. In addition, the connection node between the drain of the P-type transistor MP3 and the drain of the N-type transistor MN4 is the output terminal (OUT1) of the comparator 42.

[0047] A switch SW1 is connected between the inverting input terminal (INM) of the comparator 42 and a connection node of the drain of the P-type transistor MP2, the gate of the P-type transistor MP3, and the drain of the N-type transistor MN2. A switch SW2 is connected between the non-inverting input terminal (INP) of the comparator 42 and a connection node of the gates of the P-type transistors MP1 and MP2, the drain of the P-type transistor MP1, and the drain of the N-type transistor MN1. The switches SW1 and SW2 are controlled by a control signal supplied from the timing generator 70, and may be composed of, for example, N-type transistors.

[0048] 3, the comparator 44 has the same circuit configuration as the comparator 42. For convenience in the following explanation, the output terminal of the comparator 42 is represented by the symbol OUT1, and the output terminal of the comparator 44 is represented by the symbol OUT2.

[0049] The gates of the N-type transistors MN3 and MN4 of the comparator 42 are connected to a current source circuit 40a. The current source circuit 40a has a current source 58a and an N-type transistor MN5. One terminal of the current source 58a is connected to a power supply voltage node. The other terminal of the current source 58a is connected to the drain and gate of the N-type transistor MN5. The source of the N-type transistor MN5 is connected to a reference voltage node. A connection node between the current source 58a and the drain and gate of the N-type transistor MN5 is an output terminal of the current source circuit 40a, which is connected to the gates of the N-type transistors MN3 and MN4 of the comparator 42.

[0050] The gates of the N-type transistors MN3 and MN4 of the comparator 44 are connected to a current source circuit 40b. The current source circuit 40b has a current source 58b and an N-type transistor MN6. One terminal of the current source 58b is connected to a power supply voltage node. The other terminal of the current source 58b is connected to the drain and gate of the N-type transistor MN6. The source of the N-type transistor MN6 is connected to a reference voltage node. A connection node between the current source 58b and the drain and gate of the N-type transistor MN6 is an output terminal of the current source circuit 40b, which is connected to the gates of the N-type transistors MN3 and MN4 of the comparator 44.

[0051] In each of the comparators 42 and 44, the N-type transistors MN1, MN2, and MN3 and the P-type transistors MP1, MP2, and MP3 form a differential amplifier circuit. The gate of the N-type transistor MN1 is the positive input terminal of the differential amplifier circuit, and the gate of the N-type transistor MN2 is the negative input terminal of the differential amplifier circuit. The connection node between the gate of the P-type transistor MP1, the gate of the P-type transistor MP2, the drain of the P-type transistor MP1, and the drain of the N-type transistor MN1 is the negative output terminal of the differential amplifier circuit. In addition, the connection node between the drain of the P-type transistor MP2 and the drain of the N-type transistor MN2 is the positive output terminal of the differential amplifier circuit. The N-type transistor MN3 forms a tail current source for the differential amplifier circuit.

[0052] In each of the comparators 42, 44, the P-type transistor MP3 and the N-type transistor MN4 form a grounded-source amplifier circuit. The gate of the P-type transistor MP3 is the input terminal of the grounded-source amplifier circuit, and the connection node between the drain of the P-type transistor MP3 and the drain of the N-type transistor MN4 is the output terminal of the grounded-source amplifier circuit. The N-type transistor MN4 forms a tail current source of the grounded-source amplifier circuit. The input terminal of the grounded-source amplifier circuit is connected to the positive output terminal of the differential amplifier circuit. The output terminal of the grounded-source amplifier circuit is the output terminal of the comparators 42, 44.

[0053] In this manner, the comparators 42 and 44 are each configured with a two-stage amplifier circuit including a differential amplifier circuit and a common-source amplifier circuit connected in the subsequent stage of the differential amplifier circuit.

[0054] Each of the N-type transistors MN3 and MN4 of the comparator 42 forms a current mirror circuit together with the N-type transistor MN5 of the current source circuit 40a, and operates as a constant current source (tail current source). Similarly, each of the N-type transistors MN3 and MN4 of the comparator 44 forms a current mirror circuit together with the N-type transistor MN6 of the current source circuit 40b, and operates as a constant current source (tail current source).

[0055] Here, current source circuits 40a and 40b are driven so that current I1 is larger than current I2, where I1 is the current flowing through N-type transistor MN5 and I2 is the current flowing through N-type transistor MN6. As a result, the current flowing through N-type transistor MN3 of comparator 42 becomes larger than the current flowing through N-type transistor MN3 of comparator 44, and the slew rate of comparator 42 becomes higher than the slew rate of comparator 44. As a result, the inversion delay time of comparator 42 becomes shorter than the inversion delay time of comparator 44.

[0056] The current I1 flowing through the N-type transistor MN5 of the current source circuit 40a and the current I2 flowing through the N-type transistor MN6 of the current source circuit 40b may be configured to be controllable by the timing generator 70, or may be a fixed value.

[0057] The switches SW1 and SW2 connected between the input node and the output node of the differential amplifier circuit of the comparators 42 and 44 are switches (reset switches) for determining the auto-zero of the comparators 42 and 44. The switches SW1 and SW2 are controlled by a common control signal PSW.

[0058] Next, the operation of the photoelectric conversion device according to this embodiment will be described with reference to Fig. 4. Fig. 4 shows the levels of the control signals PSEL, PRES, PTX of the pixels 12, 14, the control signal PSW of the switches SW1, SW2, the signal VOUT of the output line 18, the reference signal Vramp, and the output signals (signals LAT) of the comparators 42, 44. Note that the transfer transistor M1, the reset transistor M2, the selection transistor M4, and the switches SW1, SW2 are turned on (conductive state) when receiving a High level control signal, and are turned off (non-conductive state) when receiving a Low level control signal.

[0059] Just before time t1, the control signals PSEL, PTX, and PSW are at a low level, and the control signal PRES is at a high level. The reset transistors M2 of the pixels 12 and 14 are turned on, and the nodes FD of the pixels 12 and 14 are reset to a voltage (reset voltage) of a reset level corresponding to the voltage Vdd.

[0060] At time t1, the vertical scanning circuit 20 controls the control signal PSEL to change from a low level to a high level. This turns on the selection transistor M4 of the pixels 12 and 14, and the amplification transistor M3 of the pixels 12 and 14 is connected to the output line 18 via the selection transistor M4. As a result, a bias current is supplied from the current source 22 to the amplification transistor M3 via the output line 18 and the selection transistor M4, and a signal corresponding to the reset voltage of the node FD is output to the output line 18 via the selection transistor M4.

[0061] Also at time t1, the timing generator 70 controls the control signal PSW from a low level to a high level. This turns on the switches SW1 and SW2 of the column circuits 32 and 34, and resets the comparators 42 and 44. More specifically, the offset voltages (threshold voltages) of the comparators 42 and 44 are reset to a voltage equivalent to the potential difference between the signal VOUT and the reference signal Vramp when the switches SW1 and SW2 are switched from on to off. In addition, the reference signal Vramp changes from the reset voltage to the offset voltage.

[0062] At the next time t2, the vertical scanning circuit 20 controls the control signal PRES from a high level to a low level. This turns off the reset transistor M2 of the pixels 12 and 14, and the reset state of the node FD of the pixels 12 and 14 is released. When the control signal PRES transitions from a high level to a low level, the potential of the node FD changes due to charge injection occurring in the reset transistor M2, and the signal level of the output line 18 also changes accordingly. The signal output to the output line 18 after the reset transistor M2 turns off is the pixel signal (noise signal) when the pixels 12 and 14 are in the reset state. This pixel signal is denoted as an N signal.

[0063] At the next time t3, the timing generator 70 controls the control signal PSW from a high level to a low level. This turns off the switches SW1 and SW2, and the reset state of the comparators 42 and 44 is released. In addition, the N signal is clamped to the capacitance element C1 of the column circuits 32 and 34, and the offset voltage of the comparators 42 and 44 is clamped to the capacitance element C2 of the column circuits 32 and 34. The difference between the level of the signal VOUT and the level of the reference signal Vramp at this time is represented as a voltage VCL.

[0064] At the next time t4, the reference signal generating circuit 36 ​​returns the level of the reference signal Vramp from the offset voltage level to the reset voltage level, so that the difference between the level of the signal VOUT on the output line and the level of the reference signal Vramp becomes smaller than the voltage VCL, and the outputs of the comparators 42 and 44 transition from the low level to the high level.

[0065] From the next time t5, the reference signal generating circuit 36 ​​monotonically decreases the level of the reference signal Vramp with time. Also from time t5, the counter circuits 46 of the column circuits 32, 34 start counting the pulses superimposed on the clock signal CLK. The comparators 42, 44 compare the level of the signal input to the inverting input terminal from the output line 18 via the capacitance element C1 with the level of the signal input to the non-inverting input terminal from the signal line 54 via the capacitance element C2.

[0066] At the next time t6, it is assumed that the difference between the level of the output line signal VOUT and the level of the reference signal Vramp becomes larger than the voltage VCL. Then, the magnitude relationship between the level of the signal input to the inverting input terminal of the comparator 42, 44 via the capacitance element C1 and the level of the signal input to the non-inverting input terminal of the comparator 42, 44 via the capacitance element C2 is reversed. As a result, the signal LAT output from the comparator 42, 44 starts to change from a high level to a low level.

[0067] The comparator 42 has a certain delay time with respect to time t6. As a result, the signal LAT output from the comparator 42 becomes low level at the timing of time t7 when the signal LAT reaches the inversion threshold, and the counting operation of the counter circuit 46 stops (shown by a solid line in FIG. 4). The count value (n1) during the period from time t5 to time t7 is a digital signal (digital N signal) obtained by AD converting (N converting) the analog signal (N signal) output from the pixel 12. The digital N signal generated in this manner is held in the memory unit 48 of the column circuit 32.

[0068] Like the comparator 42, the comparator 44 also has a certain delay time with respect to time t6. However, as described with reference to FIG. 3, the current value of the tail current source of the comparator 44 is smaller than the current value of the tail current source of the comparator 42, so the delay time of the comparator 44 is larger than the delay time of the comparator 42. As a result, the signal LAT output from the comparator 44 reaches the inversion threshold value at the timing of time t8, which is later than time t7, and becomes low level, and the counting operation of the counter circuit 46 stops (indicated by a broken line in FIG. 4). The count value (n2) during the period from time t5 to time t8 is a digital signal (digital N signal) obtained by AD conversion (N conversion) of the analog signal (N signal) output from the pixel 14. The digital N signal generated in this manner is held in the memory unit 48 of the column circuit 34.

[0069] In this manner, by using two comparators 42, 44 having different current values ​​for the tail current sources, it is possible to shift the timing at which the digital N signal converted from the signal of pixel 12 is output from the timing at which the digital N signal converted from the signal of pixel 14 is output.

[0070] At the following time t9, the reference signal generating circuit 36 ​​stops decreasing the level of the reference signal Vramp and returns it to the level of the reset voltage.

[0071] In this manner, the analog signals (N signals) output from the pixels 12, 14 to the output line 18 are converted (AD converted) into digital signals (digital N signals) by the operations during the period from time t4 to time t9. The digital N signals thus obtained are signals mainly composed of components of characteristic variations between columns of the comparators 42, 44. The digital N signals may include noise generated when the node FD is reset by the reset transistor M2, offset signals of the comparators 42, 44, and the like.

[0072] In this embodiment, the count value n1 is the value of a digital signal obtained by AD converting (N conversion) an N signal output from an OB pixel (pixel 12), and the count value n2 is the value of a digital signal obtained by AD converting (N conversion) an N signal output from an effective pixel (pixel 14). The time (time t7) at which the count value n1 is determined is earlier than the time (time t8) at which the count value n2 is determined.

[0073] Let us assume that this order is reversed, and the count value n2 is determined first, followed by the count value n1. In this case, noise caused by the comparators 44 inverting all at once in the AD conversion of the pixel signals of the pixels 14 may affect the AD conversion of the pixel signals of the pixels 12 that is performed thereafter, possibly causing an error in the count value n1.

[0074] In this regard, in this embodiment, the count value n1 is determined first, and then the count value n2 is determined, so that an error in the count value n1 caused by noise generated when the comparators 44 all invert at once can be reduced.

[0075] On the other hand, in this embodiment, there is a possibility that an error may occur in the count value n2 due to noise caused by the simultaneous inversion of the comparators 42. However, an error occurring in the count value n2 is less likely to cause deterioration in image quality than an error occurring in the count value n1. This is because the count value n1 is the reference for the black level, and therefore if there is an effect of noise, it is erroneously determined that the reference level is shifted, whereas the count value n2 does not affect the reference level. In addition, since the noise is a phenomenon that occurs when light is irradiated onto the effective pixels, the noise becoming less noticeable due to the effect of the photoelectric conversion signal (optical shot noise and sensitivity variation) is also considered to be a factor that is less likely to cause deterioration in image quality.

[0076] In this manner, in this embodiment, the value of the digital signal converted by comparator 42 and the value of the digital signal converted by comparator 44 are dispersed, and the digital signal converted by comparator 42 is output prior to the digital signal converted by comparator 44. Therefore, it is possible to obtain a good image with little influence of noise.

[0077] In the subsequent period from time t10 to time t11, the vertical scanning circuit 20 controls the control signal PTX from a low level to a high level. This turns on the transfer transistor M1 of the pixels 12 and 14, and the charge held by the photoelectric conversion element PD of the pixels 12 and 14 is transferred to the node FD. The node FD has a potential corresponding to the amount of charge transferred from the photoelectric conversion element PD by charge-voltage conversion by the floating diffusion capacitance. The amplification transistor M3 outputs a pixel signal corresponding to the potential of the node FD to the output line 18 via the selection transistor M4. The signal output to the output line 18 after the transfer transistor M1 is turned off is a pixel signal (photoelectric conversion signal) corresponding to the amount of charge generated by the photoelectric conversion element PD. This pixel signal contains a component corresponding to the amount of charge generated by the photoelectric conversion element PD as well as an N signal component, so it is expressed as an S+N signal.

[0078] As a result, the level of the signal VOUT on the output line 18 connected to the pixel 14 drops to a predetermined level according to the amount of charge transferred from the photoelectric conversion element PD. On the other hand, since the photoelectric conversion element PD of the pixel 12 is shielded from light, the level of the signal VOUT on the output line 18 connected to the pixel 12 does not change. The pixel signal output to the output line 18 is input to the inverting input terminals of the comparators 42 and 44 via the capacitive element C1 that clamps the N signal.

[0079] From the next time t12, the reference signal generating circuit 36 ​​monotonically decreases the level of the reference signal Vramp with time. Also from time t12, the counter circuits 46 of the column circuits 32, 34 start counting the pulses superimposed on the clock signal CLK. The comparators 42, 44 compare the level of the signal input to the inverting input terminal from the output line 18 via the capacitance element C1 with the level of the signal input to the non-inverting input terminal from the signal line 54 via the capacitance element C2.

[0080] At the next time t13, it is assumed that the difference between the level of the signal VOUT of the output line 18 connected to the pixel 12 and the level of the reference signal Vramp becomes larger than the voltage VCL. Then, the magnitude relationship between the level of the signal input to the inverting input terminal of the comparator 42 via the capacitance element C1 and the level of the signal input to the non-inverting input terminal of the comparator 42 via the capacitance element C2 is reversed. As a result, the signal LAT output from the comparator 42 starts to change from a high level to a low level.

[0081] The comparator 42 has a certain delay time with respect to time t13. As a result, the signal LAT output from the comparator 42 becomes low level at the timing of time t14 when the inversion threshold is reached, and the counting operation of the counter circuit 46 stops (shown by a solid line in FIG. 4). The count value S1 (=n1+A1) during the period from time t12 to time t14 is a digital signal (digital S signal) obtained by AD converting (S converting) the analog signal (S+N signal) output from the pixel 12. The count value S1 is typically the same as the count value n1. The digital S signal generated in this manner is held in the memory unit 48 of the column circuit 34.

[0082] At the next time t15, it is assumed that the difference between the level of the signal VOUT of the output line 18 connected to the pixel 14 and the level of the reference signal Vramp becomes larger than the voltage VCL. Then, the magnitude relationship between the level of the signal input to the inverting input terminal of the comparator 44 via the capacitance element C1 and the level of the signal input to the non-inverting input terminal of the comparator 44 via the capacitance element C2 is reversed. As a result, the signal LAT output from the comparator 44 starts to change from a high level to a low level.

[0083] The comparator 44 has a certain delay time with respect to time t15. As a result, the signal LAT output from the comparator 44 goes to a low level at the timing of time t16 when the inversion threshold is reached, and the counting operation of the counter circuit 46 stops (indicated by a dotted line in FIG. 4). The count value S2 (=n2+A2) during the period from time t12 to time t16 is a digital signal (digital S signal) obtained by AD converting (S converting) the analog signal (S+N signal) output from the pixel 14. The digital S signal generated in this manner is held in the memory unit 48 of the column circuit 34.

[0084] At the next time t17, the reference signal generating circuit 36 ​​stops decreasing the level of the reference signal Vramp and again increases the level of the reference signal Vramp to the level of the reset voltage.

[0085] In this manner, the analog signals (S+N signals) output from the pixels 12 and 14 on each column are converted (AD converted) into digital signals (digital S signals) by the operation in the period from time t10 to time t17.

[0086] Thereafter, the horizontal scanning circuit 50 sequentially selects the memory units 48 of the column circuits 32 and 34 of each column, and transfers the digital N signal and the digital S signal held in the memory units 48 to the digital signal processing circuit 60 via the output line 52.

[0087] The digital signal processing circuit 60 performs differential processing between the digital S signal and the digital N signal, thereby removing noise components superimposed on the digital S signal and obtaining a signal corresponding to the change in the signal VOUT.

[0088] In addition, since the delay times of the comparators 42, 44 are values ​​determined by the circuit constants, current values, etc., the delay time during N conversion is equal to the delay time during S conversion. Therefore, by performing differential processing between the digital S signal and the digital N signal, the influence of the delay time of the comparators 42, 44 is canceled, and the values ​​of the count values ​​A1, A2 after differential processing become values ​​corresponding to the change in the signal VOUT that are unrelated to the delay time of the comparators 42, 44.

[0089] Therefore, the operation of dispersing the value of the digital signal converted to N by comparator 44 and the value of the digital signal converted to N by comparator 42 and outputting the digital signal converted to N by comparator 42 before the digital signal converted to N by comparator 44 does not affect image quality.

[0090] Furthermore, by outputting the AD conversion result of pixel 14 (OB pixel) before the AD conversion result of pixel 14 (effective pixel), even if a step occurs between the level of the output signal of pixel 12 and the level of the output signal of pixel 14, this phenomenon can be corrected.

[0091] For example, the pixel array unit 10 is provided with a pixel row in which the pixel 14 is arranged in every column, and a pixel row including the pixel 12 and the pixel 14. In this way, if a step occurs between the level of the output signal of the pixel 12 in the row in which the pixels 12 and 14 are arranged and the level of the output signal of the pixel 14, a similar step also occurs in the level of the output signal of the pixel 14 in the row in which only the pixel 14 is arranged. Therefore, by using the pixel signal in the row in which only the pixel 14 is arranged, the step between the level of the output signal of the pixel 12 and the level of the output signal of the pixel 14 that occurs between the columns can be corrected.

[0092] As described above, according to the present embodiment, it is possible to effectively suppress noise caused by simultaneous inversion of the output levels of the comparators 42 and 44. This makes it possible to reduce noise superimposed on the reference signal obtained from the pixel 12 and obtain an image with good image quality.

[0093] In this embodiment, two types of comparators 42 and 44 with different delay times are used, but the number of comparators with different delay times is not limited to two, and may be three or more. In this case, too, the same effect as in this embodiment can be obtained by configuring so that the AD conversion result of the OB pixel (pixel 14) is output before the AD conversion result of the other pixels (pixel 14).

[0094] Also, the current amount of the tail current source of the comparators 42, 44 of each column may be changed in an analog manner, so that the delay time of the comparators 42, 44 differs slightly for each column. Even with such a configuration, the same effect as that of this embodiment can be obtained.

[0095] [Second embodiment] A photoelectric conversion device and a driving method thereof according to a second embodiment of the present invention will be described with reference to Fig. 5. The same components as those in the first embodiment are given the same reference numerals, and descriptions thereof will be omitted or simplified. Fig. 5 is a circuit diagram showing an example of the configuration of a comparator in the photoelectric conversion device according to this embodiment.

[0096] The photoelectric conversion device according to the present embodiment differs from the photoelectric conversion device according to the first embodiment in the configuration of the comparators 42 and 44.

[0097] That is, in the comparators 42 and 44 of the photoelectric conversion device according to this embodiment, a switch SW3 and a capacitance element C4 are connected in series between the positive output terminal of the differential amplifier circuit and the output terminal of the common-source amplifier circuit, as shown in Fig. 5. The switch SW3 of the comparator 42 is a switch controlled by a control signal Control1 supplied from the timing generator 70. The switch SW3 of the comparator 44 is a switch controlled by a control signal Control2 supplied from the timing generator 70.

[0098] Furthermore, each of the N-type transistors MN3, MN4 of the comparators 42, 44 of the photoelectric conversion device according to this embodiment forms a current mirror circuit with the N-type transistor MN5 of the current source circuit 40, and operates as a constant current source. The current flowing through the N-type transistor MN3 of the comparator 42 is the same as the current flowing through the N-type transistor MN3 of the comparator 44. Furthermore, the current flowing through the N-type transistor MN4 of the comparator 42 is the same as the current flowing through the N-type transistor MN4 of the comparator 44.

[0099] The other configuration of the photoelectric conversion device according to this embodiment is similar to that of the photoelectric conversion device according to the first embodiment.

[0100] The switch SW3 and the capacitance element C4 connected in series between the positive output terminal of the differential amplifier circuit of the comparators 42, 44 and the output terminal of the common-source amplifier circuit configure a delay circuit capable of switching the delay time of the comparators 42, 44. That is, the delay time of the comparators 42, 44 can be changed by selecting whether or not the capacitance element C4 is connected using the switch SW3. Note that instead of providing the comparators 42, 44 with a delay circuit capable of switching the delay time, a delay circuit may be selectively provided in the comparator 44.

[0101] In this embodiment, when the control signals Control1 and Control2 are at a high level, the switch SW3 is turned on (conductive state), and the capacitive element C4 is connected (large delay time). When the control signals Control1 and Control2 are at a low level, the switch SW3 is turned off (non-conductive state), and the capacitive element C4 is disconnected (small delay time). In this case, by controlling the control signal Control1 to a low level and the control signal Control2 to a high level, the slew rate of the comparator 42 becomes higher than the slew rate of the comparator 44. In other words, the delay time of the comparator 44 becomes longer than the delay time of the comparator 42.

[0102] This allows the AD conversion of pixel signals of OB pixels to be completed before the AD conversion of pixel signals of effective pixels, similar to the first embodiment when the current value of the tail current source of comparator 42 is made larger than the current value of the tail current source of comparator 44. Therefore, good image quality with less noise can be obtained.

[0103] As described above, according to the present embodiment, it is possible to effectively suppress noise caused by simultaneous inversion of the output levels of the comparators 42 and 44. This makes it possible to reduce noise superimposed on the reference signal obtained from the pixel 12 and obtain an image with good image quality.

[0104] In this embodiment, the delay time of the comparators 42, 44 is controlled using the capacitive element C4, but the method of controlling the delay time of the comparators 42, 44 is not limited to this. For example, the delay time may be controlled by changing the wiring resistance or the threshold voltage of the transistor between the comparators 42, 44. The arrangement of the capacitive elements is also not limited to this embodiment, and the delay circuit may be configured using capacitive elements for GND, power supply, etc.

[0105] In addition, in this embodiment, two types of comparators 42 and 44 with different delay times are used, but the number of types of comparators with different delay times is not limited to two, and three or more types may be used. In this case, too, by configuring so that the AD conversion result of the OB pixel (pixel 14) is output before the AD conversion results of other pixels, it is possible to obtain the same effect as in this embodiment.

[0106] [Third embodiment] A method for driving a photoelectric conversion device according to a third embodiment of the present invention will be described with reference to Fig. 6. The same components as those in the first embodiment are given the same reference numerals, and descriptions thereof will be omitted or simplified. Fig. 6 is a timing chart showing the operation of the photoelectric conversion device according to this embodiment.

[0107] In this embodiment, another method of driving the photoelectric conversion device according to the first embodiment will be described. In the first embodiment, the switches SW1, SW2 connected to the comparator 44 and the switches SW1, SW2 connected to the comparator 42 are driven at the same timing. In the present embodiment, the switches SW1, SW2 connected to the comparator 44 and the switches SW1, SW2 connected to the comparator 42 are driven at different timings.

[0108] FIG. 6 shows the levels of the control signals PSEL, PRES, and PTX of the pixels 12 and 14, the control signal PSW1 of the switch of the comparator 42, the control signal PSW2 of the switch of the comparator 44, the signal VOUT of the output line 18, and the reference signal Vramp.

[0109] Just before time t1, the control signals PSEL, PTX, PSW1, and PSW2 are at a low level, and the control signal PRES is at a high level. The reset transistors M2 of the pixels 12 and 14 are on, and the nodes FD of the pixels 12 and 14 are reset to a voltage (reset voltage) of a reset level corresponding to the voltage Vdd.

[0110] At time t1, the vertical scanning circuit 20 controls the control signal PSEL to change from a low level to a high level. This turns on the selection transistor M4 of the pixels 12 and 14, and the amplification transistor M3 of the pixels 12 and 14 is connected to the output line 18 via the selection transistor M4. As a result, a bias current is supplied from the current source 22 to the amplification transistor M3 via the output line 18 and the selection transistor M4, and a signal corresponding to the reset voltage of the node FD is output to the output line 18 via the selection transistor M4.

[0111] Also at time t1, the timing generator 70 controls the control signals PSW1 and PSW2 to change from a low level to a high level, which turns on the switches SW1 and SW2 of the column circuits 32 and 34 and resets the comparators 42 and 44. In addition, the reference signal Vramp changes from the reset voltage to the offset voltage.

[0112] At the next time t2, the vertical scanning circuit 20 changes the control signal PRES from a high level to a low level, which turns off the reset transistors M2 of the pixels 12 and 14 and releases the reset state of the nodes FD of the pixels 12 and 14. A pixel signal (N signal) when the pixels 12 and 14 are in the reset state is output to the output line 18.

[0113] At the next time t3, the timing generator 70 controls the control signal PSW1 to change from a high level to a low level. This turns off the switches SW1 and SW2 of the comparator 42, and releases the reset state of the comparator 42. In addition, the N signal of the pixel 14 is clamped to the capacitive element C1 of the column circuit 32, and the voltage VCL1 is clamped to the capacitive element C2 of the column circuit 32.

[0114] At the following time t3a, the reference signal generating circuit 36 ​​controls the level of the reference signal Vramp so that the difference in level of the reference signal Vramp with respect to the signal VOUT becomes a voltage VCL2 that is greater than the voltage VCL1.

[0115] At the next time t3b, the timing generator 70 controls the control signal PSW2 to change from High to Low. This turns off the switches SW1 and SW2 of the comparator 44, and the reset state of the comparator 44 is released. In addition, the N signal of the pixel 14 is clamped to the capacitive element C1 of the column circuit 34, and the voltage VCL2 is clamped to the capacitive element C2 of the column circuit 34.

[0116] At the next time t4, the reference signal generating circuit 36 ​​returns the level of the reference signal Vramp to the reset voltage level, which causes the voltages of the non-inverting input terminals of the comparators 42 and 44 to become higher than the voltages of the inverting input terminals, causing the outputs of the comparators 42 and 44 to transition from a low level to a high level.

[0117] Thereafter, in the period from time t5 to time t9, AD conversion of the N signals is performed in the same manner as in the first embodiment.

[0118] At time t6, the difference between the level of the signal VOUT of the output line and the level of the reference signal Vramp becomes larger than the voltage VCL1. Then, the magnitude relationship between the level of the signal input to the inverting input terminal of the comparator 42 via the capacitance element C1 and the level of the signal input to the non-inverting input terminal of the comparator 42 via the capacitance element C2 is reversed. As a result, at time t7, which is a predetermined delay time after time t6, the signal LAT output from the comparator 42 transitions from a high level to a low level, and the count value (n1) during the period from time t5 to time t7 is held in the memory unit 48 of the column circuit 32.

[0119] Also, assume that the difference between the level of the output line signal VOUT and the level of the reference signal Vramp becomes greater than the voltage VCL2 at a timing after time 6. Then, the magnitude relationship between the level of the signal input to the inverting input terminal of the comparator 44 via the capacitive element C1 and the level of the signal input to the non-inverting input terminal of the comparator 44 via the capacitive element C2 is reversed. As a result, at time t8 after a predetermined delay time, the signal LAT output from the comparator 44 transitions from a high level to a low level, and the count value (n2) during the period from time t5 to time t8 is held in the memory unit 48 of the column circuit 34.

[0120] In this manner, in this embodiment, the voltage VCL2 clamped to the capacitive element C2 of the column circuit 34 is made larger than the voltage VCL1 clamped to the capacitive element C2 of the column circuit 32, so that the timing at which the comparator 44 inverts is made slower than the timing at which the comparator 42 inverts.

[0121] This allows the AD conversion of pixel signals of OB pixels to be completed before the AD conversion of pixel signals of effective pixels, similar to the first embodiment when the current value of the tail current source of comparator 42 is made larger than the current value of the tail current source of comparator 44. Therefore, good image quality with less noise can be obtained.

[0122] As described above, according to the present embodiment, it is possible to effectively suppress noise caused by simultaneous inversion of the output levels of the comparators 42 and 44. This makes it possible to reduce noise superimposed on the reference signal obtained from the pixel 12 and obtain an image with good image quality.

[0123] [Fourth embodiment] A photoelectric conversion device and a driving method thereof according to a fourth embodiment of the present invention will be described with reference to Figs. 7 and 8. The same components as those in the first embodiment are given the same reference numerals, and descriptions thereof will be omitted or simplified. Fig. 7 is a circuit diagram showing an example of the configuration of pixels and column circuits in the photoelectric conversion device according to this embodiment. Fig. 8 is a timing chart showing the operation of the photoelectric conversion device according to this embodiment.

[0124] The photoelectric conversion device according to the present embodiment differs from the photoelectric conversion device according to the first embodiment in the configuration of the column circuits 32, 34. That is, the column circuits 32, 34 of the photoelectric conversion device according to the present embodiment further include a capacitive element C3, as shown in FIG.

[0125] One electrode of the capacitive element C3 of the column circuit 32 is connected to the inverting input terminal of the comparator 42. The other electrode of the capacitive element C3 of the column circuit 32 is connected to the timing generator 70 via a signal line 62a. A signal Vl1 is supplied from the timing generator 70 to the signal line 62a.

[0126] One electrode of the capacitive element C3 of the column circuit 34 is connected to the inverting input terminal of the comparator 44. The other electrode of the capacitive element C3 of the column circuit 34 is connected to the timing generator 70 via a signal line 62b. A signal Vl2 is supplied from the timing generator 70 to the signal line 62b.

[0127] The other configuration of the photoelectric conversion device according to this embodiment is similar to that of the photoelectric conversion device according to the first embodiment.

[0128] Next, the operation of the photoelectric conversion device according to this embodiment will be described with reference to Fig. 8. Fig. 8 shows the levels of the control signals PSEL, PRES, and PTX of the pixels 12 and 14, the control signal PSW of the switches SW1 and SW2, and the signals Vl1 and Vl2. Fig. 8 also shows the levels of the signal VOUT of the output line 18, the voltage Vc1 at the inverting input terminal of the comparator 42, the voltage Vc2 at the inverting input terminal of the comparator 44, and the reference signal Vramp.

[0129] Just before time t1, the control signals PSEL, PTX, and PSW are at low level, and the control signal PRES is at high level. The reset transistors M2 of the pixels 12 and 14 are on, and the nodes FD of the pixels 12 and 14 are reset to a voltage (reset voltage) of a reset level corresponding to the voltage Vdd. In addition, the signal Vl1 of the signal line 62a and the signal Vl2 of the signal line 62b are both at voltage Va.

[0130] At time t1, the vertical scanning circuit 20 controls the control signal PSEL to change from a low level to a high level. This turns on the selection transistor M4 of the pixels 12 and 14, and the amplification transistor M3 of the pixels 12 and 14 is connected to the output line 18 via the selection transistor M4. As a result, a bias current is supplied from the current source 22 to the amplification transistor M3 via the output line 18 and the selection transistor M4, and a signal corresponding to the reset voltage of the node FD is output to the output line 18 via the selection transistor M4.

[0131] Also at time t1, the timing generator 70 controls the control signal PSW to change from a low level to a high level, which turns on the switches SW1 and SW2 of the column circuits 32 and 34 and resets the comparators 42 and 44. In addition, the reference signal Vramp changes from the reset voltage to the offset voltage.

[0132] At the next time t2, the vertical scanning circuit 20 changes the control signal PRES from a high level to a low level, which turns off the reset transistors M2 of the pixels 12 and 14 and releases the reset state of the nodes FD of the pixels 12 and 14. A pixel signal (N signal) when the pixels 12 and 14 are in the reset state is output to the output line 18.

[0133] At the next time t3, the timing generator 70 controls the control signal PSW to change from a high level to a low level. This turns off the switches SW1 and SW2 of the comparators 42 and 44, and releases the reset state of the comparators 42 and 44. In addition, the N signal of the pixel 14 is clamped to the capacitive element C1 of the column circuits 32 and 34, and the voltage VCL is clamped to the capacitive element C2 of the column circuits 32 and 34.

[0134] At the next time t3a, the timing generator 70 controls the level of the signal Vl2 on the signal line 62b from voltage Va to voltage Vb, which is lower than voltage Va. In response to this voltage change of the signal Vl2, the voltage Vc2 of the inverting input terminal of the comparator 44 also decreases. Note that, since the signal Vl1 remains at voltage Va, the voltage Vc1 of the inverting input terminal of the comparator 42 does not change.

[0135] At the next time t4, the reference signal generating circuit 36 ​​returns the level of the reference signal Vramp to the reset voltage level, which causes the voltages of the non-inverting input terminals of the comparators 42 and 44 to become higher than the voltages of the inverting input terminals, causing the outputs of the comparators 42 and 44 to transition from a low level to a high level.

[0136] Thereafter, in the period from time t5 to time t9, AD conversion of the N signals is performed in the same manner as in the first embodiment.

[0137] At time t6, the difference between the level of the voltage Vc1 and the level of the reference signal Vramp becomes larger than the voltage VCL, and the difference in the levels of the signals input to the inverting input terminal and the non-inverting input terminal of the comparator 42 exceeds the inversion threshold of the comparator 42. As a result, at time t7, which is a predetermined delay time after time t6, the signal LAT output from the comparator 42 transitions from a high level to a low level, and the count value (n1) for the period from time t5 to time t7 is held in the memory unit 48 of the column circuit 32.

[0138] Also, at a timing after time t6, the difference between the level of the voltage Vc2 and the level of the reference signal Vramp becomes larger than the voltage VCL, and the difference in the levels of the signals input to the inverting input terminal and the non-inverting input terminal of the comparator 44 exceeds the inversion threshold of the comparator 44. As a result, at time t8 after a predetermined delay time, the signal LAT output from the comparator 44 transitions from a high level to a low level, and the count value (n2) for the period from time t5 to time t8 is held in the memory unit 48 of the column circuit 34.

[0139] In this manner, in this embodiment, by making the voltage at the inverting input terminal of comparator 44 lower than the voltage at the inverting input terminal of comparator 42, the timing at which comparator 44 inverts is made slower than the timing at which comparator 42 inverts.

[0140] This allows the AD conversion of pixel signals of OB pixels to be completed before the AD conversion of pixel signals of effective pixels, similar to the first embodiment when the current value of the tail current source of comparator 42 is made larger than the current value of the tail current source of comparator 44. Therefore, good image quality with less noise can be obtained.

[0141] As described above, according to the present embodiment, it is possible to effectively suppress noise caused by simultaneous inversion of the output levels of the comparators 42 and 44. This makes it possible to reduce noise superimposed on the reference signal obtained from the pixel 12 and obtain an image with good image quality.

[0142] In this embodiment, the voltage of the inverting input terminal of the comparator 44 is controlled to be lower than the voltage of the inverting input terminal of the comparator 42, but the voltage of the inverting input terminal of the comparator 42 may be controlled to be higher than the voltage of the inverting input terminal of the comparator 44. Alternatively, the voltages of the inverting input terminal of the comparator 42 and the voltages of the inverting input terminal of the comparator 44 may be controlled so that the voltage of the inverting input terminal of the comparator 42 is lower than the voltage of the inverting input terminal of the comparator 44.

[0143] [Fifth embodiment] An imaging system according to a fifth embodiment of the present invention will be described with reference to Fig. 9. Fig. 9 is a block diagram showing a schematic configuration of the imaging system according to this embodiment.

[0144] The photoelectric conversion device 100 described in the first to fourth embodiments is applicable to various imaging systems. Examples of applicable imaging systems include digital still cameras, digital camcorders, security cameras, copiers, fax machines, mobile phones, vehicle-mounted cameras, and observation satellites. Camera modules equipped with an optical system such as a lens and an imaging device are also included in the imaging system. FIG. 9 illustrates a block diagram of a digital still camera as an example of these.

[0145] 9 includes an imaging device 201, a lens 202 that forms an optical image of a subject on the imaging device 201, an aperture 204 that varies the amount of light passing through the lens 202, and a barrier 206 that protects the lens 202. The lens 202 and the aperture 204 form an optical system that focuses light on the imaging device 201. The imaging device 201 is the photoelectric conversion device 100 described in any one of the first to fourth embodiments, and converts the optical image formed by the lens 202 into image data.

[0146] The imaging system 200 also includes a signal processing unit 208 that processes an output signal output from the imaging device 201. The signal processing unit 208 generates image data from a digital signal output from the imaging device 201. The signal processing unit 208 also performs various corrections and compression as necessary to output image data. The imaging device 201 may include an AD conversion unit that generates a digital signal to be processed by the signal processing unit 208. The AD conversion unit may be formed in a semiconductor layer (semiconductor substrate) in which a photoelectric conversion unit of the imaging device 201 is formed, or may be formed in a semiconductor substrate different from the semiconductor layer in which the photoelectric conversion unit of the imaging device 201 is formed. The signal processing unit 208 may also be formed in the same semiconductor substrate as the imaging device 201.

[0147] The imaging system 200 further includes a memory unit 210 for temporarily storing image data, and an external interface unit (external I / F unit) 212 for communicating with an external computer or the like. The imaging system 200 further includes a recording medium 214 such as a semiconductor memory for recording or reading out imaging data, and a recording medium control interface unit (recording medium control I / F unit) 216 for recording or reading out on the recording medium 214. The recording medium 214 may be built into the imaging system 200, or may be removable.

[0148] Furthermore, the imaging system 200 has an overall control / calculation unit 218 that performs various calculations and controls the entire digital still camera, and a timing generation unit 220 that outputs various timing signals to the imaging device 201 and the signal processing unit 208. Here, the timing signals and the like may be input from outside, and the imaging system 200 only needs to have at least the imaging device 201 and the signal processing unit 208 that processes the output signal output from the imaging device 201.

[0149] The imaging device 201 outputs an imaging signal to the signal processing unit 208. The signal processing unit 208 performs predetermined signal processing on the imaging signal output from the imaging device 201, and outputs image data. The signal processing unit 208 generates an image using the imaging signal.

[0150] In this way, according to this embodiment, it is possible to realize an imaging system to which the photoelectric conversion device 100 according to the first to fourth embodiments is applied.

[0151] [Sixth embodiment] An imaging system and a moving object according to a sixth embodiment of the present invention will be described with reference to Fig. 10. Fig. 10 is a diagram showing the configuration of an imaging system and a moving object according to this embodiment.

[0152] FIG. 10(a) shows an example of an imaging system related to an in-vehicle camera. The imaging system 300 has an imaging device 310. The imaging device 310 is the photoelectric conversion device 100 described in any one of the first to fourth embodiments. The imaging system 300 has an image processing unit 312 that performs image processing on a plurality of image data acquired by the imaging device 310, and a parallax acquisition unit 314 that calculates parallax (phase difference of parallax images) from the plurality of image data acquired by the imaging system 300. The imaging system 300 also has a distance acquisition unit 316 that calculates a distance to an object based on the calculated parallax, and a collision determination unit 318 that determines whether or not there is a possibility of a collision based on the calculated distance. Here, the parallax acquisition unit 314 and the distance acquisition unit 316 are examples of distance information acquisition means that acquire distance information to the object. That is, the distance information is information related to the parallax, the defocus amount, the distance to the object, and the like. The collision determination unit 318 may determine the possibility of a collision using any of these distance information. The distance information acquisition means may be realized by dedicated hardware, a software module, a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), or a combination of these.

[0153] The imaging system 300 is connected to a vehicle information acquisition device 320, and can acquire vehicle information such as vehicle speed, yaw rate, and steering angle. The imaging system 300 is also connected to a control ECU 330, which is a control device that outputs a control signal to generate a braking force for the vehicle based on the judgment result of the collision judgment unit 318. The imaging system 300 is also connected to an alarm device 340 that issues an alarm to the driver based on the judgment result of the collision judgment unit 318. For example, when the judgment result of the collision judgment unit 318 indicates that there is a high possibility of a collision, the control ECU 330 performs vehicle control to avoid a collision and reduce damage by applying the brakes, releasing the accelerator, suppressing engine output, etc. The alarm device 340 warns the user by sounding an alarm, displaying alarm information on the screen of a car navigation system, etc., and vibrating the seat belt or steering wheel.

[0154] In this embodiment, the surroundings of the vehicle, for example, the front or rear, are imaged by the imaging system 300. Fig. 10(b) shows an imaging system for imaging the area in front of the vehicle (imaging range 350). A vehicle information acquisition device 320 sends instructions to the imaging system 300 or the imaging device 310. This configuration can further improve the accuracy of distance measurement.

[0155] Although the above describes an example of control to prevent collision with other vehicles, the present invention can also be applied to control of automatic driving by following other vehicles, control of automatic driving to prevent deviation from lanes, etc. Furthermore, the imaging system is not limited to vehicles such as the vehicle itself, but can be applied to moving bodies (moving devices) such as ships, aircraft, and industrial robots. In addition, the present invention can be applied not only to moving bodies, but also to devices that use object recognition widely, such as intelligent transport systems (ITS).

[0156] [Seventh embodiment] A device according to a seventh embodiment of the present invention will be described with reference to Fig. 11. Fig. 11 is a block diagram showing a schematic configuration of the device according to this embodiment.

[0157] FIG. 11 is a schematic diagram showing an apparatus EQP including a photoelectric conversion device APR. The photoelectric conversion device APR has the functions of the photoelectric conversion device 100 according to any one of the first to fourth embodiments. All or a part of the photoelectric conversion device APR is a semiconductor device IC. The photoelectric conversion device APR of this example can be used as, for example, an image sensor, an AF (Auto Focus) sensor, a photometry sensor, or a distance measurement sensor. The semiconductor device IC has a pixel area PX in which pixel circuits PXC including photoelectric conversion units are arranged in a matrix. The semiconductor device IC can have a peripheral area PR around the pixel area PX. Circuits other than pixel circuits can be arranged in the peripheral area PR.

[0158] The photoelectric conversion device APR may have a structure (a chip stacking structure) in which a first semiconductor chip provided with a plurality of photoelectric conversion units and a second semiconductor chip provided with peripheral circuits are stacked. The peripheral circuits in the second semiconductor chip may be column circuits corresponding to the pixel columns of the first semiconductor chip. The peripheral circuits in the second semiconductor chip may be matrix circuits corresponding to the pixels or pixel blocks of the first semiconductor chip. The first and second semiconductor chips may be connected to each other by through-hole vias (TSVs), inter-chip wiring by direct bonding of a conductor such as copper, connection by microbumps between chips, connection by wire bonding, or the like.

[0159] The photoelectric conversion device APR may include a package PKG that houses the semiconductor device IC in addition to the semiconductor device IC. The package PKG may include a base to which the semiconductor device IC is fixed, a cover such as glass that faces the semiconductor device IC, and connection members such as bonding wires and bumps that connect terminals provided on the base and terminals provided on the semiconductor device IC.

[0160] The equipment EQP may further include at least one of an optical device OPT, a control device CTRL, a processing device PRCS, a display device DSPL, a memory device MMRY, and a mechanical device MCHN. The optical device OPT corresponds to the photoelectric conversion device APR as a photoelectric conversion device, and is, for example, a lens, a shutter, or a mirror. The control device CTRL controls the photoelectric conversion device APR, and is, for example, a semiconductor device such as an ASIC. The processing device PRCS processes a signal output from the photoelectric conversion device APR, and constitutes an AFE (analog front end) or a DFE (digital front end). The processing device PRCS is a semiconductor device such as a CPU (central processing unit) or an ASIC (application specific integrated circuit). The display device DSPL is an EL display device or a liquid crystal display device that displays information (images) obtained by the photoelectric conversion device APR. The memory device MMRY is a magnetic device or a semiconductor device that stores information (images) obtained by the photoelectric conversion device APR. The memory device MMRY is a volatile memory such as an SRAM or a DRAM, or a non-volatile memory such as a flash memory or a hard disk drive. The mechanical device MCHN has a moving part or a propulsion part such as a motor or an engine. In the device EQP, the signal output from the photoelectric conversion device APR is displayed on the display device DSPL, and is transmitted to the outside by a communication device (not shown) provided in the device EQP. For this purpose, the device EQP preferably further includes a memory device MMRY and a processing device PRCS in addition to the memory circuit unit and the arithmetic circuit unit provided in the photoelectric conversion device APR.

[0161] The device EQP shown in FIG. 11 may be an electronic device such as an information terminal having a photographing function (e.g., a smartphone or a wearable device) or a camera (e.g., an interchangeable lens camera, a compact camera, a video camera, or a surveillance camera). The mechanical device MCHN in the camera can drive components of the optical device OPT for zooming, focusing, and shutter operation. The device EQP may also be a transportation device (moving object) such as a vehicle, a ship, or an aircraft. The device EQP may also be a medical device such as an endoscope or a CT scanner. The device EQP may also be a medical device such as an endoscope or a CT scanner.

[0162] The mechanical device MCHN in the transportation equipment can be used as a moving device. The device EQP as a transportation equipment is suitable for transporting the photoelectric conversion device APR and for assisting and / or automating driving (operation) by using a photographing function. The processing device PRCS for assisting and / or automating driving (operation) can perform processing for operating the mechanical device MCHN as a moving device based on information obtained by the photoelectric conversion device APR.

[0163] The photoelectric conversion device APR according to this embodiment can provide high value to its designer, manufacturer, seller, purchaser and / or user. Therefore, if the photoelectric conversion device APR is installed in equipment EQP, the value of the equipment EQP can also be increased. Therefore, when manufacturing and selling equipment EQP, deciding to install the photoelectric conversion device APR of this embodiment in the equipment EQP is advantageous in increasing the value of the equipment EQP.

[0164] [Modified embodiment] The present invention is not limited to the above-described embodiment, and various modifications are possible. For example, an example in which part of the configuration of any one of the embodiments is added to another embodiment, or an example in which part of the configuration of another embodiment is substituted therefor, is also an embodiment of the present invention.

[0165] 2 is an example and can be modified as appropriate. For example, each of the pixels 12 and 14 may have two or more photoelectric conversion elements. Also, the pixels 12 and 14 do not necessarily have to have the selection transistor M4.

[0166] Furthermore, in the above first to fourth embodiments, the AD conversion result of pixel 14 (OB pixel) is determined before the AD conversion result of pixel 12 (effective pixel), but when there are multiple pixels 14 in one row, it is not necessarily necessary to determine the AD conversion results of all pixels 14 first.

[0167] For example, AD conversion of the pixels 14 may be performed in the column circuit 32, AD conversion of some of the pixels 12 may be performed in the column circuit 32, and AD conversion of the other part of the pixels 12 may be performed in the column circuit 34. Even in such a case, the effects described in the above embodiment can be obtained as long as the number of pixels 12 that undergo AD conversion in the column circuit 34 is sufficiently greater than the number of pixels 12 that undergo AD conversion in the column circuit 32.

[0168] Moreover, the noise caused by the simultaneous inversion of the comparators 42 and 44 has a particularly large effect on adjacent columns. Therefore, if the AD conversion result of the pixel 14 is determined at least before the AD conversion result of the pixel 12 located near the pixel 14, the effects described in the above embodiment can be obtained.

[0169] In addition, in the first to fourth embodiments, the comparators 42, 44 are configured with a differential amplifier circuit and a common-source amplifier circuit, but the circuit configuration of the comparators 42, 44 is not limited to this. For example, the comparators 42, 44 do not necessarily have to include a common-source amplifier circuit, and may be configured with a single stage of a differential amplifier circuit.

[0170] Furthermore, the imaging systems shown in the fifth and sixth embodiments are examples of imaging systems to which the photoelectric conversion device of the present invention can be applied, and imaging systems to which the photoelectric conversion device of the present invention can be applied are not limited to the configurations shown in Figures 9 and 10.

[0171] It should be noted that the above-mentioned embodiments are merely examples of the implementation of the present invention, and the technical scope of the present invention should not be interpreted as being limited by these embodiments. In other words, the present invention can be implemented in various forms without departing from its technical concept or main features. [Explanation of symbols]

[0172] 10...Pixel array section 12,14…pixels 16…Control line 18…Output line 20...Vertical scanning circuit 22,58,58a,58b…Current source 30...Readout circuit 32,34…column circuit 36...Reference signal generation circuit 40a,40b…Current source circuit 42,44...Comparator 46…Counter circuit 48…Memory section 50...Horizontal scanning circuit 52…Output line 54,54,62a,62b…Signal line 60...Digital signal processing circuit 70...Timing generator 100...Photoelectric conversion device

Claims

1. a pixel array section in which a plurality of pixels, each having a photoelectric conversion element, are arranged in a plurality of columns; A plurality of AD conversion circuits provided corresponding to the plurality of columns; A control circuit for controlling the plurality of AD conversion circuits, the plurality of pixels include a first pixel arranged in a first column among the plurality of columns, the first pixel having a light-shielded photoelectric conversion element, and a second pixel arranged in a second column among the plurality of columns different from the first column, the second pixel having light incident on the photoelectric conversion element, the plurality of AD conversion circuits include a first AD conversion circuit having a first comparator that receives a signal from the first pixel, and a second AD conversion circuit having a second comparator that receives a signal from the second pixel; a timing at which the signal of the first pixel is input to the first comparator and a timing at which the signal of the second pixel is input to the second comparator are the same; The control circuit is configured to control the first comparator and the second comparator such that, for a signal of the first pixel and a signal of the second pixel having the same level, a signal value output from the first comparator changes before a signal value output from the second comparator changes. A photoelectric conversion device comprising:

2. The control circuit controls the first comparator and the second comparator so that a slew rate in the first comparator is higher than a slew rate in the second comparator when AD converting the signal of the first pixel and the signal of the second pixel.

2. The photoelectric conversion device according to claim 1.

3. the first comparator and the second comparator each have a differential amplifier circuit; The control circuit controls the first comparator and the second comparator so that a current value of a tail current source of the differential amplifier circuit of the first comparator is larger than a current value of a tail current source of the differential amplifier circuit of the second comparator.

3. The photoelectric conversion device according to claim 2.

4. the first comparator and the second comparator each have a delay circuit configured to be able to switch a slew rate; The control circuit controls the delay circuit so that a slew rate in the first comparator is higher than a slew rate in the second comparator.

3. The photoelectric conversion device according to claim 2.

5. the first comparator and the second comparator are configured to compare pixel signals output from pixels in corresponding columns with a reference signal whose level changes over time, and to output comparison signals indicating different levels depending on whether a difference between the pixel signal and the reference signal is smaller than a threshold voltage or larger than a threshold voltage; The control circuit resets the first comparator and the second comparator so that a threshold voltage of the second comparator is greater than a threshold voltage of the first comparator when AD converting the signal of the first pixel and the signal of the second pixel.

2. The photoelectric conversion device according to claim 1.

6. The level of the reference signal when the first comparator is reset is different from the level of the reference signal when the second comparator is reset.

6. The photoelectric conversion device according to claim 5.

7. the first comparator and the second comparator are configured to compare pixel signals output from pixels in corresponding columns with a reference signal whose level changes over time, and to output comparison signals indicating different levels depending on whether a difference between the pixel signal and the reference signal is smaller than a threshold voltage or larger than a threshold voltage; The control circuit controls a level of the first input terminal of the first comparator and a level of the first input terminal of the second comparator so that a potential difference between a first input terminal receiving the pixel signal and a second input terminal receiving the reference signal is smaller in the second comparator than in the first comparator when AD converting a signal of the first pixel and a signal of the second pixel.

2. The photoelectric conversion device according to claim 1.

8. The control circuit controls the first comparator and the second comparator so that, for the signal of the first pixel and the signal of the second pixel having the same level, a time from the start of AD conversion until a signal value output from the first comparator changes is shorter than a time from the start of AD conversion until a signal value output from the second comparator changes.

8. The photoelectric conversion device according to claim 1, wherein the first and second electrodes are arranged in a first direction.

9. the first AD conversion circuit has a first memory that stores a result of the AD conversion, and the second AD conversion circuit has a second memory that stores a result of the AD conversion, The control circuit controls the first memory and the second memory so that the first memory holds a result of the AD conversion before the second memory holds a result of the AD conversion.

9. The photoelectric conversion device according to claim 1,

10. The control circuit controls the first memory and the second memory so that the result of the AD conversion held in the first memory and the result of the AD conversion held in the second memory are output in sequence.

10. The photoelectric conversion device according to claim 9.

11. the first pixel and the second pixel output a noise signal and a photoelectric conversion signal, respectively; The control circuit controls the first comparator and the second comparator so that the signal values ​​change in the following order: a signal output from the first comparator in response to the noise signal output from the first pixel, a signal output from the second comparator in response to the noise signal output from the second pixel, a signal output from the first comparator in response to the photoelectric conversion signal output from the first pixel, and a signal output from the second comparator in response to the photoelectric conversion signal output from the second pixel.

11. The photoelectric conversion device according to claim 1,

12. the first comparator and the second comparator are configured to compare pixel signals output from pixels in corresponding columns with a reference signal whose level changes over time, and to output comparison signals indicating different levels depending on whether a difference between the pixel signal and the reference signal is smaller than a threshold voltage or larger than a threshold voltage; The control circuit controls the first comparator and the second comparator so that the first comparator completes the comparison before the second comparator completes the comparison.

2. The photoelectric conversion device according to claim 1.

13. a pixel array section in which a plurality of pixels, each having a photoelectric conversion element, are arranged in a plurality of columns; A plurality of AD conversion circuits provided corresponding to the plurality of columns; the plurality of pixels include a first pixel arranged in a first column among the plurality of columns, the first pixel having a light-shielded photoelectric conversion element, and a second pixel arranged in a second column among the plurality of columns different from the first column, the second pixel having light incident on the photoelectric conversion element, the plurality of AD conversion circuits include a first AD conversion circuit having a first comparator that receives a signal from the first pixel, and a second AD conversion circuit having a second comparator that receives a signal from the second pixel; The slew rate of the first comparator is higher than the slew rate of the second comparator. A photoelectric conversion device comprising:

14. the first comparator and the second comparator each have a differential amplifier circuit; The current value of the tail current source of the differential amplifier circuit of the first comparator is greater than the current value of the tail current source of the differential amplifier circuit of the second comparator.

14. The photoelectric conversion device according to claim 13.

15. The first comparator and the second comparator each have a delay circuit configured to be able to switch a slew rate.

14. The photoelectric conversion device according to claim 13.

16. The second comparator has a delay circuit for making the slew rate lower than that of the first comparator.

14. The photoelectric conversion device according to claim 13.

17. The first comparator and the second comparator each have a differential amplifier circuit and a source-grounded amplifier circuit provided in a subsequent stage of the differential amplifier circuit, and the delay circuit is provided between an output terminal of the differential amplifier circuit and an input terminal of the source-grounded amplifier circuit.

17. The photoelectric conversion device according to claim 15 or 16.

18. The first pixel and the second pixel are simultaneously controlled by a common control signal.

18. The photoelectric conversion device according to claim 1,

19. The first row and the second row are adjacent to each other.

19. The photoelectric conversion device according to claim 1,

20. The photoelectric conversion device according to any one of claims 1 to 19, a signal processing unit that processes a signal output from the photoelectric conversion device; An imaging system comprising:

21. A mobile object, The photoelectric conversion device according to any one of claims 1 to 19, a distance information acquiring means for acquiring distance information to an object from a parallax image based on a signal from the photoelectric conversion device; a control means for controlling the moving object based on the distance information; A moving object comprising:

22. The photoelectric conversion device according to any one of claims 1 to 19, an optical device corresponding to the photoelectric conversion device; A control device for controlling the photoelectric conversion device; a processing device that processes a signal output from the photoelectric conversion device; a mechanical device controlled based on information obtained by the photoelectric conversion device; A display device that displays information obtained by the photoelectric conversion device; and a storage device for storing information obtained by the photoelectric conversion device; An apparatus comprising:

Images