Semiconductor device and its manufacturing method

Abstract

To improve reliability of a semiconductor device and to suppress a decrease in a yield of the semiconductor device.SOLUTION: A method for manufacturing a semiconductor device comprises the steps of: forming a conductor pattern CP1 on a semiconductor substrate SUB of a scribe region SR via an insulation film GF; forming a plurality of conductor patterns CP2 connected to the conductor pattern CP1 on the conductor pattern CP1; forming a conductor pattern CP3 connected to the plurality of conductor patterns CP2 on the plurality of conductor patterns CP2; and cutting the scribe region SR along a Y direction using a dicing blade so as to leave a part of the scribe region SR in a chip region CR. In a X direction, a width of the dicing blade is narrower than widths of the conductor patterns CP1 and CP3. After the scribe region SR is cut, a part of the conductor pattern CP1, the whole or a part of one conductor pattern CP2 among the plurality of conductor patterns CP2, and a part of the conductor pattern CP3 are left in the scribe region SR.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device having a conductor pattern in a scribe region and a manufacturing method thereof. [Background technology]

[0002] Conventionally, a method has been used in which a semiconductor wafer is cut along a scribe area of ​​the semiconductor wafer with a dicing blade or the like to separate the semiconductor wafer and obtain a plurality of semiconductor chips. In addition, in order to effectively utilize the scribe area, a test pattern is provided in the scribe area.

[0003] For example, Patent Document 1 discloses a technique in which a conductor pattern for testing is formed in a scribe region, and the entire conductor pattern is cut with a dicing blade having a width greater than that of the conductor pattern.

[0004] Patent Document 2 discloses a technique in which a plurality of rows of metal patterns are formed in a scribe region, and the entire metal pattern in the central row is cut off by a dicing blade having a width greater than that of the metal patterns. The metal pattern is made of a multi-layer wiring layer in which wiring and plugs are stacked. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] JP 2011-124487 A [Patent Document 2] JP 2015-056605 A Summary of the Invention [Problem to be solved by the invention]

[0006] 1 shows a scribe region of a semiconductor device in an example studied by the inventors of the present application. In the scribe region, an insulating film IL is formed on a semiconductor substrate SUB, and a conductor pattern CP0 is formed on the insulating film IL. Although not shown in detail, a plurality of test elements are formed on the semiconductor substrate SUB, and the conductor pattern CP0 is provided as a measurement pad for contacting a test terminal, for example, in a WAT ​​(Wafer Acceptance Test) or the like. Note that the chip region in which transistors and the like are formed is covered with a protective film PIQ such as a polyimide film, but the presence of the protective film PIQ in the scribe region makes it difficult to perform a dicing process, so the scribe region is exposed from the protective film PIQ.

[0007] Generally, as shown in Fig. 1, a dicing process is performed in which a dicing blade DC cuts a scribe area to obtain a plurality of semiconductor devices by dividing a semiconductor substrate SUB. At this time, a part of the cut conductor pattern CP0 is left as a conductor pattern piece CP0a in the scribe area. Here, since the conductor pattern CP0 is not covered by a protective film PIQ or the like, there is a risk that the remaining conductor pattern piece CP0a will peel off from the insulating film IL and scatter into the chip area as a foreign object.

[0008] In particular, discrete devices often have only one wiring layer. In such cases, there is no wiring pattern other than the conductor pattern CP0 in the scribe area. Therefore, it can be said that the remaining conductor pattern piece CP0a is in a state where it is easily peeled off from the insulating film IL.

[0009] The above-mentioned foreign matter is detected by a subsequent visual inspection, and the semiconductor device is determined to be a defective product. In other words, the yield of the semiconductor device is reduced. In addition, depending on the state of adhesion of the foreign matter, it may be difficult to detect the foreign matter. In such a case, the foreign matter may act as a leak path, etc., resulting in the manufacture of a semiconductor device with low reliability.

[0010] In order to prevent such a possibility, it is conceivable to reduce the width of the conductor pattern CP0 so that the width of the conductor pattern CP0 is narrower than the width of the dicing blade DC. This allows the entire conductor pattern CP0 to be removed during the dicing process. However, narrowing the width of the conductor pattern CP0 reduces the contact area between the inspection terminal and the conductor pattern CP0, which is problematic in that it reduces the accuracy of the measurement results. In addition, it also becomes difficult to align the inspection terminal, which is problematic in that it reduces the stability of the measurement.

[0011] On the other hand, it is possible to remove the entire conductor pattern CP0 without reducing the accuracy of the measurement results and the stability of the measurement by widening the width of the scribe area and applying a wide dicing blade DC. However, widening the width of the scribe area causes problems such as an increase in chip size or a decrease in the number of chips that can be obtained.

[0012] The main object of the present application is to provide a technology capable of preventing scattering of conductor pattern pieces CP0a without applying methods such as reducing the size of the conductor pattern CP0 or widening the width of the scribe region, etc. In other words, the main object of the present application is to improve the reliability of semiconductor devices and suppress a decrease in the yield of semiconductor devices.

[0013] Other objects and novel features will become apparent from the description of this specification and the accompanying drawings. [Means for solving the problem]

[0014] In one embodiment, a method for manufacturing a semiconductor device includes the steps of: (a) preparing a semiconductor substrate having a first chip region, a second chip region, and a scribe region disposed between the first chip region and the second chip region and extending in a first direction in a plan view; (b) forming a first conductor pattern on the semiconductor substrate in the scribe region via a first insulating film; (c) forming a second insulating film covering the first conductor pattern; (d) forming a plurality of holes in the second insulating film so as to be positioned on the first conductor pattern; (e) forming a plurality of second conductor patterns in the plurality of holes, the second conductor patterns connected to the first conductor pattern; (f) forming a third conductor pattern on the second insulating film and on the plurality of second conductor patterns, the third conductor pattern connected to the plurality of second conductor patterns; and (g) cutting the scribe region along the first direction using a dicing blade so that a portion of the scribe region remains on the outer periphery of each of the first chip region and the second chip region. In a second direction intersecting the first direction in a plan view, the width of the dicing blade is narrower than the width of the first conductor pattern and the width of the third conductor pattern before the step (g). After the step (g), a part of the first conductor pattern, all or a part of at least one of the second conductor patterns, and a part of the third conductor pattern remain in the scribe region on the first chip region side and the scribe region on the second chip region side.

[0015] In one embodiment, a semiconductor device includes a semiconductor substrate having a first chip region for forming transistors and a scribe region surrounding the periphery of the first chip region, a gate insulating film formed on the semiconductor substrate in the first chip region, a first insulating film formed on the semiconductor substrate in the scribe region, a gate electrode formed on the gate insulating film, a first conductor pattern piece formed on the first insulating film, a second insulating film covering the gate electrode and the first conductor pattern, a via hole formed in the second insulating film so as to be located on the gate electrode, a hole formed in the second insulating film so as to be located on the first conductor pattern piece, a via formed in the via hole and connected to the gate electrode, a second conductor pattern piece formed in the hole and connected to the first conductor pattern, a gate wiring formed on the second insulating film and on the via and connected to the via, and a third conductor pattern piece formed on the second insulating film and on the second conductor pattern piece and connected to the second conductor pattern piece.

[0016] In one embodiment, a method for manufacturing a semiconductor device includes the steps of: (a) preparing a semiconductor substrate having a first conductivity type, a first chip region, a second chip region, and a scribe region provided between the first chip region and the second chip region and extending in a first direction in a plan view; (b) forming a seventh conductor pattern having a second conductivity type opposite to the first conductivity type within the semiconductor substrate in the scribe region; (c) forming a second insulating film covering the seventh conductor pattern; (d) forming a plurality of holes in the second insulating film so as to be located on the seventh conductor pattern; (e) forming a plurality of second conductor patterns connected to the seventh conductor pattern within the plurality of holes; (f) forming a third conductor pattern connected to the plurality of second conductor patterns on the second insulating film and on the plurality of second conductor patterns; and (g) cutting the scribe region along the first direction using a dicing blade so that a portion of the scribe region remains on the outer periphery of each of the first chip region and the second chip region. In a second direction intersecting the first direction in a plan view, the width of the dicing blade is narrower than the width of the seventh conductor pattern and the width of the third conductor pattern before the step (g). Furthermore, after the step (g), a part of the seventh conductor pattern, at least one of the second conductor patterns, and a part of the third conductor pattern remain in the scribe region on the first chip region side and the scribe region on the second chip region side. Effect of the Invention

[0017] According to one embodiment, the reliability of the semiconductor device can be improved, and a decrease in the yield of the semiconductor device can be suppressed. [Brief description of the drawings]

[0018] [Figure 1] FIG. 11 is a cross-sectional view showing a scribe region of a semiconductor device in a study example. [Diagram 2] 1 is a plan view showing a semiconductor substrate in a first embodiment. [Diagram 3]2 is a cross-sectional view showing a scribe region of the semiconductor device in the first embodiment. [Figure 4] 2 is a cross-sectional view showing a scribe region of the semiconductor device in the first embodiment. [Diagram 5] 2 is a plan view showing a scribe region of the semiconductor device in the first embodiment. FIG. [Figure 6] 1 is a plan view showing a conductor pattern in accordance with the first embodiment. [Figure 7] 1 is a plan view showing a conductor pattern in accordance with the first embodiment. [Figure 8] 1 is a plan view showing a semiconductor device in a first embodiment. [Figure 9] 2 is a cross-sectional view showing a chip region of the semiconductor device in the first embodiment. [Figure 10] 3A to 3C are cross-sectional views showing a manufacturing process of the chip region of the semiconductor device in the first embodiment. [Figure 11] 11 is a cross-sectional view showing a manufacturing process following FIG. 10. [Figure 12] 12 is a cross-sectional view showing a manufacturing process following FIG. 11. [Figure 13] 13 is a cross-sectional view showing a manufacturing process following FIG. 12. [Figure 14] 14 is a cross-sectional view showing a manufacturing process following FIG. 13. [Figure 15] 15 is a cross-sectional view showing a manufacturing process following FIG. 14. [Figure 16] 16 is a cross-sectional view showing a manufacturing process following FIG. 15. [Figure 17] 5A to 5C are cross-sectional views showing a manufacturing process of a scribe region of the semiconductor device in the first embodiment. [Figure 18] 18 is a cross-sectional view showing a manufacturing process following FIG. 17. [Figure 19] 19 is a cross-sectional view showing a manufacturing process following FIG. 18. [Figure 20] 19A to 19C are cross-sectional views showing the manufacturing process following FIG. [Figure 21] 21 is a cross-sectional view showing a manufacturing process following FIG. 20. [Figure 22] 22 is a cross-sectional view showing a manufacturing process following FIG. 21. [Diagram 23] 23 is a cross-sectional view showing a manufacturing process following FIG. 22. [Figure 24] 11 is a plan view showing an example in which the conductor pattern in the first embodiment is used as a measurement pattern. FIG. [Diagram 25] 11 is a plan view showing an example in which the conductor pattern in the first embodiment is used as a measurement pattern. FIG. [Figure 26] 11 is a plan view showing an example in which the conductor pattern in the first embodiment is used as a measurement pattern. FIG. [Figure 27] 11 is a plan view showing an example in which the conductor pattern in the first embodiment is used as a measurement pattern. FIG. [Figure 28] 1 is a plan view showing an example in which the conductor pattern in the first embodiment is used as an alignment mark. [Figure 29] FIG. 11 is a cross-sectional view showing a scribe region of a semiconductor device in a second embodiment. [Diagram 30] FIG. 11 is a cross-sectional view showing a scribe region of a semiconductor device in a second embodiment. [Diagram 31] FIG. 11 is a cross-sectional view showing a chip region of a semiconductor device in a second embodiment. [Diagram 32] FIG. 11 is a cross-sectional view showing a chip region of a semiconductor device in a third embodiment. [Diagram 33] FIG. 13 is a cross-sectional view showing a scribe region of a semiconductor device in a fourth embodiment. [Diagram 34] FIG. 11 is a cross-sectional view showing a scribe region of a semiconductor device in a fourth embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0019] Hereinafter, the embodiments will be described in detail with reference to the drawings. In all the drawings for explaining the embodiments, the same reference numerals are used for the members having the same functions, and the repeated explanations are omitted. In the following embodiments, the explanations of the same or similar parts will not be repeated as a rule unless it is particularly necessary.

[0020] In addition, the X-direction, Y-direction, and Z-direction described in this application intersect with each other and are perpendicular to each other. In this application, the Z-direction is described as the up-down direction, height direction, or thickness direction of a structure. In addition, expressions such as "plan view" or "planar view" used in this application mean that a surface formed by the X-direction and the Y-direction is a "plane" and this "plane" is viewed from the Z-direction.

[0021] (Embodiment 1) <Configuration of Semiconductor Device> The semiconductor device 100 according to the first embodiment will be described below with reference to Figures 2 to 9. Figure 2 shows the semiconductor substrate SUB used in the first embodiment, and Figures 3 to 7 show the conductor patterns CP1 to CP3 formed in the scribe region SR. Figures 8 and 9 show the transistors formed in the chip region CR.

[0022] 2, the semiconductor substrate SUB is made of, for example, silicon, and has a plurality of chip regions CR and scribe regions SR provided between each chip region CR. The chip regions CR are regions where semiconductor elements such as transistors are mainly formed. The scribe regions SR extend in the X and Y directions in a plan view. A dicing blade DC is used to cut the scribe regions SR along the X and Y directions to obtain a plurality of semiconductor devices 100 each including a chip region CR and a part of the scribe region SR.

[0023] FIG. 3 shows the state of the scribe region SR before the dicing step performed using a dicing blade DC, and FIG. 4 shows the state of the scribe region SR after the dicing step.

[0024] As shown in FIG. 3, a drift region ND, which is a low-concentration n-type impurity region, is formed in the semiconductor substrate SUB in the scribe region SR. An insulating film GF made of, for example, a silicon oxide film is formed on the semiconductor substrate SUB in the scribe region SR. The insulating film GF has a thickness of, for example, 50 to 100 nm. A conductor pattern CP1 made of, for example, an n-type polycrystalline silicon film is formed on the insulating film GF. The conductor pattern CP1 has a thickness of, for example, 400 to 800 nm. The conductor pattern CP1 is covered with an insulating film IL made of, for example, a silicon oxide film. The insulating film IL has a thickness of, for example, 400 to 1000 nm.

[0025] A plurality of holes TH are formed in the insulating film IL so as to be located above the conductive pattern CP1. A plurality of conductive patterns CP2 connected to the conductive pattern CP1 are formed in the plurality of holes TH. The conductive pattern CP2 includes a tungsten film as a main conductive film. Specifically, the conductive pattern CP2 is made of a laminated film of a barrier metal film such as a titanium film and a titanium nitride film, and a conductive film such as a tungsten film formed on the barrier metal film.

[0026] Conductive patterns CP3 are formed on the conductive patterns CP2 and connected to the conductive patterns CP2, respectively. The conductive pattern CP3 includes an aluminum film as a main conductive film. Specifically, the conductive pattern CP3 is made of a laminated film of a barrier metal film such as a tungsten titanium film, a titanium nitride film, or a titanium tungsten film, and a conductive film such as an aluminum film or an aluminum alloy film formed on the barrier metal film. The thickness of the conductive pattern CP3 is, for example, 0.5 to 6 μm.

[0027] Further, a protective film PIQ made of, for example, a polyimide film is formed on the insulating film IL. The protective film PIQ has an opening for opening the scribe region SR, and the scribe region SR is exposed from the protective film PIQ.

[0028] 4, after the dicing process, a part of the scribe region SR remains on the outer periphery of each chip region CR. In these scribe regions SR, a part of the conductor pattern CP1, all or a part of at least one of the multiple conductor patterns CP2, and a part of the conductor pattern CP3 remain as conductor pattern pieces CP1a, CP2a, and CP3a.

[0029] FIG. 5 shows a case where a dicing process is performed on a scribe region SR extending in the Y direction using a dicing blade DC along the Y direction, and shows the relationship between the width of each conductor pattern and the width of the dicing blade DC.

[0030] 5, in the X direction, the width W2 of the dicing blade DC is narrower than the width W1 of the conductor pattern CP1 and the width W1 of the conductor pattern CP3 before the dicing process. In the X direction, the width W1 of the conductor pattern CP1 and the width W1 of the conductor pattern CP3 before the dicing process are each at least twice the width W2 of the dicing blade DC. In addition, in the X direction, the width W3 of the conductor pattern piece CP1a and the width W3 of the conductor pattern piece CP3a after the dicing process are each at least 1 / 2 the width W2 of the dicing blade DC.

[0031] Furthermore, after the dicing process, the width W4 of the conductor pattern piece CP1a and the width W4 of the conductor pattern piece CP3a in the Y direction are wider than the width W3 of the conductor pattern piece CP1a and the width W3 of the conductor pattern piece CP3a in the X direction, respectively. By making the width W4 wider than the width W3, the conductor pattern piece CP2a can be left in more locations after the dicing process, thereby further increasing the bonding strength of the conductor pattern pieces CP1a to CP3a.

[0032] The width W1 is, for example, 60 μm or more, the width W2 is, for example, 30 μm, the width W3 is, for example, 15 μm or more, and the width W4 is, for example, 60 μm or more.

[0033] In this manner, in the first embodiment, the width W1 of the conductor pattern CP1 and the width W1 of the conductor pattern CP3 are set wide. Therefore, for example, when the conductor patterns CP1 to CP3 are used as measurement pads, the contact area between the inspection terminal and the conductor pattern CP3 can be increased, thereby improving the accuracy of the measurement results. In addition, the alignment of the inspection terminal is also facilitated, improving the stability of the measurement.

[0034] Moreover, in the first embodiment, the technique of widening the width W2 of the dicing blade DC and the width of the scribe region SR in order to remove all of the conductor patterns CP1 to CP3 is not used, which solves the problem of the increased chip size or the reduced number of obtainable chips.

[0035] On the other hand, in the first embodiment, parts of the conductor patterns CP1 to CP3 are left in the scribe region SR. In that case, in the example of FIG. 1, there is a risk that the remaining conductor pattern pieces CP0a will peel off from the insulating film IL and scatter as foreign matter into the chip region CR.

[0036] In contrast, in the first embodiment, after the dicing step, a part of the conductor pattern CP1, all or a part of at least one of the conductor patterns CP2, and a part of the conductor pattern CP3 are left as conductor pattern pieces CP1a, CP2a, and CP3a. That is, the conductor pattern pieces CP1a to CP3a are left in the scribe region SR with the conductor pattern piece CP3a connected to the conductor pattern piece CP2a and conductor pattern piece CP1a.

[0037] Therefore, the first embodiment has an effect (anchor effect) that the conductor pattern pieces CP3a are unlikely to peel off from the insulating film IL. That is, according to the first embodiment, scattering of the conductor pattern pieces CP3a can be prevented, so that the reliability of the semiconductor device 100 can be improved and a decrease in the yield of the semiconductor device 100 can be suppressed.

[0038] 4 illustrates an example in which two conductor pattern pieces CP2a and one conductor pattern piece CP2a from which a part has been removed remain in the scribe region SR, but the number of conductor pattern pieces CP2a to be left is not limited to this. What is important is that a conductor that connects the conductor pattern piece CP3a and the conductor pattern piece CP1a remains in the scribe region SR.

[0039] 3 and 4, the holes TH are formed from the top surface of the conductor pattern CP1 (conductor pattern piece CP1a) to a position that reaches the inside. That is, the conductor patterns CP2 (conductor pattern pieces CP2a) are formed from the top surface of the conductor pattern CP1 (conductor pattern piece CP1a) to a position that reaches the inside. This can further increase the bonding strength between the conductor patterns CP2 and the conductor pattern CP1.

[0040] Incidentally, the extending direction of each of the holes TH and the conductor patterns CP2 can be designed to be any direction. For example, as shown in FIG. 6, the holes TH and the conductor patterns CP2 may extend in the Y direction so that their width in the Y direction is wider than their width in the X direction. Also, as shown in FIG. 7, they may extend in the X direction so that their width in the X direction is wider than their width in the Y direction. When the structure of FIG. 7 is applied, after the dicing process, a part of each of the conductor patterns CP2 remains as a plurality of conductor pattern pieces CP2a in the scribe region SR. Therefore, like the structure of FIG. 6, scattering of the conductor pattern pieces CP3a can be prevented.

[0041] Fig. 8 shows a semiconductor device (semiconductor chip) 100 obtained after the dicing process. The semiconductor substrate SUB of the semiconductor device 100 has a chip region CR for forming transistors, and a scribe region SR surrounding the outer periphery of the chip region CR. Fig. 9 shows a region (cell region) 2A in which main transistors are formed, and a region (gate lead-out region) 1A for leading out gate electrodes GE of the transistors, in the chip region CR. In the first embodiment, a GG-type IGBT (Insulated Gate Bipolar Transistor) is exemplified as such a transistor.

[0042] As shown in Fig. 8, most of the semiconductor device 100 is covered with an emitter wiring EW, and a gate wiring GW is formed around the emitter wiring EW. Although not shown here, the emitter wiring EW and the gate wiring GW are covered with a protective film PIQ. An opening is provided in a part of the protective film PIQ, and the emitter wiring EW and the gate wiring GW exposed in the opening become an emitter pad and a gate pad. External connection terminals such as wire bonding or clips (copper plates) are connected to the emitter pad and the gate pad, so that the semiconductor device 100 is electrically connected to another chip or a wiring board.

[0043] 9, a drift region ND, which is a low-concentration n-type impurity region, is formed in the semiconductor substrate SUB. An n-type field stop region NS having a higher impurity concentration than the drift region ND, a p-type collector region PC, and a collector electrode CE made of a metal film are formed on the back surface side of the semiconductor substrate SUB. That is, when the IGBT is in operation, a collector potential is applied to the collector region PC via the collector electrode CE.

[0044] A trench TR is formed on the front surface side of the semiconductor substrate SUB. A gate insulating film GF is formed on the semiconductor substrate SUB. The gate insulating film GF is a film in the same layer as the insulating film GF in the scribe region SR, and is made of the same material and has the same thickness as the insulating film GF.

[0045] A gate electrode GE is formed on the gate insulating film GF. The gate electrode GE is a film in the same layer as the conductor pattern CP1 in the scribe region SR, and is made of the same material and thickness as the conductor pattern CP1. The gate electrode GE has a buried electrode portion GEa buried in the trench TR via the gate insulating film GF, and an extension portion GEb located on the semiconductor substrate SUB via the gate insulating film GF.

[0046] A p-type floating region PF is formed in the semiconductor substrate SUB, and a p-type base region PB having a higher impurity concentration than the floating region PF is formed on the surface of the floating region PF. The floating region PF is formed to a position deeper than the bottom of the trench TR.

[0047] A hole barrier region NHB having a higher impurity concentration than the drift region ND is formed in the semiconductor substrate SUB between the two trenches TR, and a p-type base region PB is formed on the surface of the hole barrier region NHB. An n-type emitter region NE having a higher impurity concentration than the hole barrier region NHB is formed in the base region PB between the two trenches TR.

[0048] An insulating film IL is formed on the emitter region NE and the base region PB. The insulating film IL covers the conductor pattern CP1 in the scribe region SR and covers the gate electrode GE in the chip region CR. The insulating film IL is formed with a via hole VH1 located on the gate electrode GE and a via hole VH2 penetrating the emitter region NE and reaching the base region PB. In the first embodiment, the via hole VH1 is located on the drawn-out portion GEb.

[0049] A p-type body region PR having a higher impurity concentration than the base region PB is formed around the bottom of the via hole VH2. The body region PR is provided to reduce the contact resistance with the emitter wiring EW embedded in the via hole VH2 and to prevent latch-up.

[0050] In the via hole VH1, a via VIA1 connected to the gate electrode GE (drawing portion GEb) is formed. In the via hole VH2, a via VIA2 connected to the emitter region NE, the base region PB, and the body region PR is formed. The via VIA1 and the via VIA2 are films in the same layer as the conductor pattern CP2 in the scribe region SR, and are made of the same material and have the same thickness as the conductor pattern CP2.

[0051] A gate wiring GW connected to the via VIA1 is formed on the insulating film IL and the via VIA1. An emitter wiring EW connected to the via VIA2 is formed on the insulating film IL and the via VIA2. The gate wiring GW and the emitter wiring EW are films in the same layer as the conductor pattern CP3, and are made of the same material and have the same thickness as the conductor pattern CP3. When the IGBT is in operation, a gate potential is applied to the gate electrode GE via the gate wiring GW, and an emitter potential is applied to the emitter region NE, the base region PB, and the body region PR via the emitter wiring EW.

[0052] A protective film PIQ is formed on the gate wiring GW and the emitter wiring EW. The protective film PIQ is formed in the chip region CR and is not formed in the scribe region SR.

[0053] In this manner, the semiconductor device 100 includes the IGBT formed in the chip region CR, and the conductor patterns CP1-CP3 (conductor pattern pieces CP1a-CP3a) formed in the scribe region SR. Furthermore, the conductor pattern pieces CP1a-CP3a can be formed in the same process as the process for forming the gate electrode GE, vias VIA1, VIA2, gate wiring GW, and emitter wiring EW that constitute the IGBT, so that the conductor pattern pieces CP1a-CP3 do not increase the number of manufacturing steps.

[0054] <Method of Manufacturing Semiconductor Device> The method for manufacturing the semiconductor device in the first embodiment will be described below with reference to Figures 10 to 23. Figures 10 to 16 show the portions corresponding to Figure 9, and Figures 17 to 23 show the portions corresponding to Figures 3 and 4.

[0055] First, a semiconductor substrate SUB is prepared, which has a plurality of chip regions CR and scribe regions SR provided between each of the chip regions CR.

[0056] Next, as shown in Figures 10 and 17, a drift region ND is formed in the semiconductor substrate SUB. The drift region ND can be formed by preparing a semiconductor substrate SUB in which an n-type impurity has been introduced in advance, and using the n-type semiconductor substrate SUB as the drift region ND. Alternatively, a p-type semiconductor substrate SUB can be prepared, and the drift region ND can be formed on the p-type semiconductor substrate SUB by an epitaxial method.

[0057] Next, using photolithography and ion implantation, a hole barrier region NHB is formed in the semiconductor substrate SUB in the region 2A, and a floating region PF is formed in the semiconductor substrate SUB in the regions 1A and 2A.

[0058] Next, an insulating film made of, for example, a silicon oxide film is formed on the semiconductor substrate SUB in the regions 1A and 2A, and the insulating film is patterned using photolithography and dry etching to form a hard mask. Next, the semiconductor substrate SUB is etched using the hard mask as a mask to form a plurality of trenches TR in the semiconductor substrate SUB. Thereafter, the hard mask is removed.

[0059] Next, the semiconductor substrate SUB is subjected to a heat treatment to diffuse the impurities contained in the hole barrier region NHB and the floating region PF. This heat treatment causes the hole barrier region NHB to diffuse to the vicinity of the bottom of each of the trenches TR, and causes the floating region PF to diffuse to a position deeper than the bottom of each of the trenches TR so as to cover the bottom of each of the trenches TR.

[0060] 11 and 18, a thermal oxidation process is performed on the semiconductor substrate SUB to form an insulating film GF in the trenches TR and on the semiconductor substrate SUB in the regions 1A and 2A, and on the semiconductor substrate SUB in the scribe region SR. The insulating film GF in the regions 1A and 2A functions as a gate insulating film GF.

[0061] Next, a polycrystalline silicon film SI is formed as a conductor film on the insulating film GF by, for example, a CVD (Chemical Vapor Deposition) method so as to fill the inside of the trench TR. Next, a resist pattern RP1 is formed on the polycrystalline silicon film SI. The resist pattern RP1 has a pattern that covers a part of the polycrystalline silicon film SI in the region 1A and the scribe region SR and opens the polycrystalline silicon film SI in the region 2A.

[0062] 12 and 19, the polycrystalline silicon film SI is dry-etched using the resist pattern RP1 as a mask to selectively pattern the polycrystalline silicon film SI. This forms a gate electrode GE in the chip region CR, the gate electrode GE having a buried electrode portion GEa buried in the trench TR and a lead-out portion GEb located on the semiconductor substrate SUB and connected to the buried electrode portion GEa. Also, a conductor pattern CP1 is formed on the semiconductor substrate SUB in the scribe region.

[0063] Next, by using photolithography and ion implantation, a base region PB is formed on the surface of each of the floating region PF and the hole barrier region NHB, and an n-type emitter region NE is formed on the surface of the base region PB.

[0064] Next, as shown in FIGS. 13 and 20, an insulating film IL is formed on the semiconductor substrate SUB by, for example, a CVD method so as to cover the gate electrode GE in the regions 1A and 2A and to cover the conductor pattern CP1 in the scribe region SR.

[0065] 14 and 21, a via hole VH1 is formed in the insulating film IL so as to be located on the lead-out portion GEb in region 1A, a via hole VH2 is formed in the insulating film IL so as to reach the emitter region NE and the base region PB in region 2A, and a plurality of holes TH are formed in the insulating film IL so as to be located on the conductor pattern CP1 in the scribe region SR, by using a photolithography method and a dry etching process. Here, the via hole VH1, the via hole VH2, and the plurality of holes TH can be formed by the same process, but may be formed by different processes.

[0066] Next, a body region PR is formed at the bottom of the via hole VH2 by using an ion implantation method, followed by a heat treatment for activating each impurity region.

[0067] 15 and 22, a barrier metal film such as a titanium film and a titanium nitride film, and a conductor film such as a tungsten film are formed in the via holes VH1 and VH2, in the holes TH, and on the insulating film IL by, for example, a sputtering method or a CVD method. Next, the barrier metal film and the conductor film outside the via holes VH1 and VH2 and the holes TH are removed by a dry etching process or a CMP (Chemical Mechanical Polishing) method. As a result, vias VIA1 and VIA2 and a plurality of conductive patterns CP2 are formed in the via holes VH1 and VH2 and the holes TH.

[0068] 16 and 23, a barrier metal film such as a tungsten titanium film, a titanium nitride film, or a titanium tungsten film, and a conductor film such as an aluminum film or an aluminum alloy film are formed on the vias VIA1 and VIA2, the conductive patterns CP2, and the insulating film IL by, for example, a sputtering method. Next, the conductive film and the barrier metal film on the insulating film IL are patterned by using a photolithography method and a dry etching process. As a result, a gate wiring GW is formed on the via VIA1 and the insulating film IL in the region 1A, an emitter wiring EW is formed on the via VIA2 and the insulating film IL in the region 2A, and a conductor pattern CP3 is formed on the conductive patterns CP2 and the insulating film IL in the scribe region SR.

[0069] 9 and 3, a protective film PIQ is formed by, for example, a coating method so as to cover the gate wiring GW, the emitter wiring EW, and the conductor pattern CP3. After that, the protective film PIQ is selectively patterned by using a photolithography method and a dry etching process, thereby exposing a part of the gate wiring GW, a part of the emitter wiring EW, and the conductor pattern CP3.

[0070] Next, a polishing process is performed on the rear surface of the semiconductor substrate SUB to reduce the thickness of the semiconductor substrate SUB. Next, a field stop region NS and a p-type collector region PC are formed on the rear surface of the semiconductor substrate SUB by photolithography and ion implantation. Next, a collector electrode CE is formed on the surface of the collector region PC exposed on the rear surface side of the semiconductor substrate SUB by, for example, sputtering, in which a multilayer metal film such as an aluminum film, a titanium film, a nickel film, a gold film, or a silver film is formed.

[0071] Thereafter, as shown in FIG. 4, the semiconductor substrate SUB is cut along the scribe regions SR with a dicing blade DC to obtain a plurality of semiconductor devices 100.

[0072] <Application example 1 of conductor patterns CP1 to CP3> 24 to 27, a case where the conductor pattern CP1, the multiple conductor patterns CP2 and the conductor pattern CP3 are used as the measurement pattern MP will be described below. An inspection terminal such as a probe terminal comes into contact with the conductor pattern CP3 of the measurement pad MP.

[0073] Two or more sets of measurement pads MP are provided in the scribe region SR. Here, two sets of measurement pads MP are shown as an example of two or more sets of measurement pads MP. Between the two sets of measurement pads MP, a conductor pattern CP4, a plurality of conductor patterns CP5 connected to the conductor pattern CP4, and a conductor pattern CP6 connected to the plurality of conductor patterns CP5 are provided.

[0074] The conductor pattern CP4 is formed on the same layer as the conductor pattern CP1 and is made of the same material and thickness as the conductor pattern CP1. The multiple conductor patterns CP5 are formed on the same layer as the multiple conductor patterns CP2 and are made of the same material and thickness as the multiple conductor patterns CP2. The conductor pattern CP6 is formed on the same layer as the conductor pattern CP3 and is made of the same material and thickness as the conductor pattern CP3.

[0075] The conductor pattern CP6 is provided as a test element and is electrically connected to at least one of the two sets of measurement pads MP.

[0076] 24 shows an inspection element for short circuit defects between wirings. The conductor pattern CP6 connected to one measurement pad MP and the conductor pattern CP6 connected to the other measurement pad MP are each arranged in a comb shape with the teeth of the comb alternately arranged. By applying different voltages to the one measurement pad MP and the other measurement pad MP, the dielectric strength voltage between the one conductor pattern CP6 and the other conductor pattern CP6 can be measured.

[0077] 25 shows a test element for wiring resistance. A conductor pattern MP6 that is folded back multiple times is connected to two pairs of measurement pads MP. This makes it possible to measure the resistance between the two pairs of measurement pads MP.

[0078] 26 and 27 show a test element known as a chain resistor. By preparing a plurality of conductor patterns MP6 and appropriately combining and connecting these with a plurality of conductor patterns CP5, it is possible to form various wiring resistor patterns.

[0079] In each of the test elements, a part of the conductor pattern CP4, all or a part of at least one of the plurality of conductor patterns CP5, and a part of the conductor pattern CP6 remain in the scribe region SR after the dicing process.

[0080] After the dicing process, the conductor patterns CP4 to CP6 are removed by the dicing blade DC. However, a part of the conductor pattern CP6 is left in the scribe region SR. By making sure that the remaining conductor pattern CP6 is connected to the conductor patterns CP4 and CP5, it is possible to prevent a part of the remaining testing element from peeling off.

[0081] <Application example 2 of conductor patterns CP1 to CP3> A case where a conductor pattern CP1, a plurality of conductor patterns CP2, and a conductor pattern CP3 are used as alignment patterns will be described below with reference to Fig. 28. As shown in Fig. 28, an alignment mark AM is provided on the conductor pattern CP3. The alignment mark AM is formed as an opening in which a part of the conductor pattern CP3 is opened.

[0082] In order to facilitate detection of such alignment marks AM, it is preferable that no other conductors are formed below the alignment marks AM. Therefore, the conductor pattern CP1, the multiple holes TH, and the multiple conductor patterns CP2 are provided at positions that do not overlap the alignment marks AM in a plan view. These are also provided at positions that are connected to the conductor pattern CP3 that is left in the scribe region SR after the dicing process. Therefore, even if the alignment marks AM are removed after the dicing process, the conductor pattern CP3 can be prevented from peeling off.

[0083] (Embodiment 2) 29 to 31, a semiconductor device 100 according to the second embodiment will be described below. In the following description, differences from the first embodiment will be mainly described, and descriptions of points that overlap with the first embodiment will be omitted.

[0084] In the first embodiment, the step of forming the conductor pattern CP2 and the step of forming the conductor pattern CP3 are performed as separate steps, whereas in the second embodiment, these steps are performed as the same step.

[0085] The manufacturing process of the second embodiment is the same as that of the first embodiment up to the steps shown in FIG. 14 and FIG. 21. Next, the barrier metal film and the conductor film described in FIG. 16 and FIG. 23 are formed. That is, for example, by a sputtering method, a barrier metal film such as a tungsten titanium film, a titanium nitride film, or a titanium tungsten film, and a conductor film such as an aluminum film or an aluminum alloy film are formed in the via holes VH1 and VH2, in the holes TH, and on the insulating film IL. Next, the conductor film and the barrier metal film on the insulating film IL are patterned by using a photolithography method and a dry etching process.

[0086] As a result, in the region 1A, the via VI1 in the via hole VH1 and the gate wiring GW on the insulating film IL are integrally formed, as shown in Fig. 31. Also, in the region 2A, the via VIA2 in the via hole VH12 and the emitter wiring EW on the insulating film IL are integrally formed. Also, in the scribe region SR, the multiple conductor patterns CP2 in the multiple holes TH and the conductor pattern CP3 on the insulating film IL are integrally formed, as shown in Fig. 29.

[0087] After the dicing process, a plurality of integrated conductor pattern pieces CP2a and conductor pattern pieces CP3a are left in the scribe region SR, as shown in Fig. 30. Also in the second embodiment, scattering of the conductor pattern pieces CP3a can be prevented, so that the reliability of the semiconductor device 100 can be improved and a decrease in the yield of the semiconductor device 100 can be suppressed.

[0088] Furthermore, in the second embodiment, compared to the first embodiment, the process of forming the plurality of conductor patterns CP2 can be omitted, so that the manufacturing process can be simplified and the manufacturing costs can be reduced.

[0089] (Embodiment 3) The semiconductor device 100 according to the third embodiment will be described below with reference to Fig. 32. In the following description, differences from the first embodiment will be mainly described, and descriptions of points that overlap with the first embodiment will be omitted.

[0090] In the first embodiment, the gate electrode GE is composed of a buried electrode portion GEa buried in the trench TR and an extension portion GEb formed on the semiconductor substrate SUB. In the third embodiment, as shown in region 1A of FIG. 32, the entire gate electrode GE is buried in the trench TR via the gate insulating film GF. In other words, the entire gate electrode GE is formed as a buried electrode portion GEa. Then, in the insulating film IL, a via hole VH1 is formed so as to be located above the gate electrode GE, and a via VIA1 is directly connected to the buried gate electrode GE.

[0091] Moreover, the semiconductor substrate SUB of the third embodiment has a region (resistance element forming region) 3A for forming a resistance element RE in a position different from the regions 1A and 2A. The resistance element RE is formed on the semiconductor substrate SUB in the region 3A and is separated from the gate electrode GE via a gate insulating film GF.

[0092] The resistor element RE is covered with an insulating film IL. A via hole VH3 is formed in the insulating film IL so as to be located above the resistor element RE. A via VIA3 is formed in the via hole VH3 and is connected to the resistor element RE. A resistor wiring RW connected to the via VIA3 is formed on the via VIA3 and the insulating film IL.

[0093] To form such a resistor element RE, the resist pattern RP1 described in Fig. 11 is formed so as to selectively cover the polycrystalline silicon film SI in the region 3A without being formed in the region 1A. In this state, the dry etching process described in Fig. 12 is performed to selectively pattern the polycrystalline silicon film SI. As a result, the gate electrode GE embedded in the trench TR can be formed in the region 1A and the region 2A, and the resistor element RE separated from the gate electrode GE can be formed in the region 3A.

[0094] The via hole VH3, the via VIA3, and the resistor wiring RW can be formed in the same process as the process for forming the via hole VH1, the via VIA1, and the gate wiring GW. That is, the via VIA3 and the resistor wiring RW are films in the same layer as the via VIA1 and the gate wiring GW, and are made of the same material and have the same thickness as the via VIA1 and the gate wiring GW.

[0095] In this way, even in a configuration in which the entire gate wiring GW is embedded in the trench TR, the resistive element RE and the conductor pattern CP1 can be simultaneously formed by using the resist pattern RP1.

[0096] The technique disclosed in the second embodiment can also be applied to the technique disclosed in the third embodiment.

[0097] (Embodiment 4) A semiconductor device 100 according to the fourth embodiment will be described below with reference to Figures 33 and 34. In the following description, differences from the first embodiment will be mainly described, and descriptions of points that overlap with the first embodiment will be omitted.

[0098] In the first embodiment, the conductor pattern CP1 is formed by utilizing a polycrystalline silicon film SI. In the fourth embodiment, as shown in Fig. 33, a conductor pattern CP7 which is a p-type impurity region formed in a semiconductor substrate SUB is used instead of the conductor pattern CP1.

[0099] In the first embodiment, the conductor pattern CP1 is electrically insulated from the semiconductor substrate SUB by the insulating film GF. In the third embodiment, the conductivity type of the conductor pattern CP7 is made opposite to that of the semiconductor substrate SUB (drift region ND), so that the conductor pattern CP7 can be electrically isolated from the semiconductor substrate SUB.

[0100] Such a conductor pattern CP7 can be formed by the same process as the process for forming the floating region PF or the base region PB. Moreover, the processes after the formation of the conductor pattern CP7 are the same as those in the embodiment 1. Note that, as shown in Fig. 34, after the dicing process, a part of the conductor pattern CP7 remains in the scribe region SR as a conductor pattern piece CP7a.

[0101] Also in the fourth embodiment, scattering of the conductor pattern pieces CP3a can be prevented, so that the reliability of the semiconductor device 100 can be improved and a decrease in the yield of the semiconductor device 100 can be suppressed.

[0102] The techniques disclosed in the second and third embodiments can also be applied to the technique disclosed in the fourth embodiment.

[0103] Although the present invention has been specifically described above based on the above embodiment, the present invention is not limited to the above embodiment and can be modified in various ways without departing from the spirit of the present invention.

[0104] For example, in the above embodiment, an IGBT with a GG structure is exemplified as a transistor, but the IGBT may have a GGEE structure or an EGE structure. The transistor is not limited to an IGBT, but may be a power MOSFET. The transistor is not limited to a trench gate type in which a gate electrode GE is embedded in a trench TR, but may be a planar type in which a gate electrode GE is formed on a semiconductor substrate SUB.

[0105] In the above embodiment, a transistor is exemplified as a semiconductor element formed in the chip region CR, but the semiconductor element may be a diode or a bipolar transistor formed in the semiconductor substrate SUB. Depending on the structure of the diode or bipolar transistor, the polycrystalline silicon film SI may not be used. For example, the technique of the fourth embodiment can be suitably used in the semiconductor device 100 in which the polycrystalline silicon film SI is not used. [Explanation of symbols]

[0106] 100 Semiconductor devices (semiconductor chips) 1A area (gate pull-out area) 2A area (cell area) 3A area (resistance element formation area) AM alignment mark CE collector electrode CP1~CP7 Conductor pattern CP1a~CP7a Conductor pattern pieces CR Chip Area DC Dicing Blade EW Emitter wiring (emitter electrode) GE gate electrode GEa embedded electrode part GEb Drawer GF Gate insulating film GW Gate wiring IE Inspection Elements IL insulating film MP measurement pattern ND Drift Region NE emitter region NS field stop region NHB Hole Barrier Region PB Base Area PC Collector Area PF floating area PR body region PIQ protective film RP1 Resist pattern RE Resistance element RW resistance wiring SI Polycrystalline silicon film (conductor film) SR Scribe Area SUB Semiconductor Substrate TH hole TR groove VH1~VH3 via holes VIA1~VIA3 vias

Claims

1. (a) preparing a semiconductor substrate of a first conductivity type having a first chip region, a second chip region, and a scribe region provided between the first chip region and the second chip region and extending in a first direction in a plan view; (b) forming a seventh conductor pattern in the semiconductor substrate in the scribe area, the seventh conductor pattern being of a second conductivity type opposite to the first conductivity type; (c) forming a second insulating film covering the seventh conductor pattern; (d) forming a plurality of holes in the second insulating film so as to be located above the seventh conductor pattern; (e) forming a plurality of second conductor patterns in the plurality of holes, the second conductor patterns being connected to the seventh conductor pattern; (f) forming a third conductor pattern on the second insulating film and on the second conductor patterns, the third conductor pattern being connected to the second conductor patterns; (g) cutting the scribe region along the first direction using a dicing blade so that a portion of the scribe region remains on an outer periphery of each of the first chip region and the second chip region; Equipped with In a second direction intersecting the first direction in a plan view, a width of the dicing blade is narrower than a width of the seventh conductor pattern and a width of the third conductor pattern before the (g) step; a portion of the seventh conductor pattern, at least one of the second conductor patterns, and a portion of the third conductor pattern remain in each of the scribe region on the first chip region side and the scribe region on the second chip region side after the step (g).

2. 2. The method of manufacturing a semiconductor device according to claim 1, The steps (e) and (f) are carried out as separate steps; The step (e) comprises: (e1) forming a first conductor film in the holes and on the second insulating film; (e2) forming the second conductor patterns within the holes by removing the first conductor film outside the holes; having The step (f) comprises: (f1) forming a second conductor film on the second insulating film and on the plurality of second conductor patterns; (f2) forming the second conductor pattern on the second insulating film and on the plurality of second conductor patterns by patterning the second conductor film on the second insulating film; having the first conductor film includes a tungsten film; The method for manufacturing a semiconductor device, wherein the second conductor film includes an aluminum film or an aluminum alloy film.

3. 2. The method of manufacturing a semiconductor device according to claim 1, The step (e) and the step (f) are carried out as the same step; forming a second conductor film in the holes and on the second insulating film, and patterning the second conductor film on the second insulating film, so that the second conductor patterns in the holes and the third conductor pattern on the second insulating film are integrally formed; The method for manufacturing a semiconductor device, wherein the second conductor film includes an aluminum film or an aluminum alloy film.

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